1fe0fe473SAlistair Francis /* 2fe0fe473SAlistair Francis * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3fe0fe473SAlistair Francis * 4fe0fe473SAlistair Francis * Copyright (c) 2020 Western Digital 5fe0fe473SAlistair Francis * 6fe0fe473SAlistair Francis * Provides a board compatible with the OpenTitan FPGA platform: 7fe0fe473SAlistair Francis * 8fe0fe473SAlistair Francis * This program is free software; you can redistribute it and/or modify it 9fe0fe473SAlistair Francis * under the terms and conditions of the GNU General Public License, 10fe0fe473SAlistair Francis * version 2 or later, as published by the Free Software Foundation. 11fe0fe473SAlistair Francis * 12fe0fe473SAlistair Francis * This program is distributed in the hope it will be useful, but WITHOUT 13fe0fe473SAlistair Francis * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14fe0fe473SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15fe0fe473SAlistair Francis * more details. 16fe0fe473SAlistair Francis * 17fe0fe473SAlistair Francis * You should have received a copy of the GNU General Public License along with 18fe0fe473SAlistair Francis * this program. If not, see <http://www.gnu.org/licenses/>. 19fe0fe473SAlistair Francis */ 20fe0fe473SAlistair Francis 21fe0fe473SAlistair Francis #include "qemu/osdep.h" 22fe0fe473SAlistair Francis #include "hw/riscv/opentitan.h" 23fe0fe473SAlistair Francis #include "qapi/error.h" 24fe0fe473SAlistair Francis #include "hw/boards.h" 25fe0fe473SAlistair Francis #include "hw/misc/unimp.h" 26fe0fe473SAlistair Francis #include "hw/riscv/boot.h" 27fe0fe473SAlistair Francis #include "exec/address-spaces.h" 28888c9af2SAlistair Francis #include "qemu/units.h" 29*b9fc5135SAlistair Francis #include "sysemu/sysemu.h" 30fe0fe473SAlistair Francis 31fe0fe473SAlistair Francis static const struct MemmapEntry { 32fe0fe473SAlistair Francis hwaddr base; 33fe0fe473SAlistair Francis hwaddr size; 34fe0fe473SAlistair Francis } ibex_memmap[] = { 35888c9af2SAlistair Francis [IBEX_ROM] = { 0x00008000, 16 * KiB }, 36fe0fe473SAlistair Francis [IBEX_RAM] = { 0x10000000, 0x10000 }, 37fe0fe473SAlistair Francis [IBEX_FLASH] = { 0x20000000, 0x80000 }, 38fe0fe473SAlistair Francis [IBEX_UART] = { 0x40000000, 0x10000 }, 39fe0fe473SAlistair Francis [IBEX_GPIO] = { 0x40010000, 0x10000 }, 40fe0fe473SAlistair Francis [IBEX_SPI] = { 0x40020000, 0x10000 }, 41fe0fe473SAlistair Francis [IBEX_FLASH_CTRL] = { 0x40030000, 0x10000 }, 42fe0fe473SAlistair Francis [IBEX_PINMUX] = { 0x40070000, 0x10000 }, 43fe0fe473SAlistair Francis [IBEX_RV_TIMER] = { 0x40080000, 0x10000 }, 44fe0fe473SAlistair Francis [IBEX_PLIC] = { 0x40090000, 0x10000 }, 45fe0fe473SAlistair Francis [IBEX_PWRMGR] = { 0x400A0000, 0x10000 }, 46fe0fe473SAlistair Francis [IBEX_RSTMGR] = { 0x400B0000, 0x10000 }, 47fe0fe473SAlistair Francis [IBEX_CLKMGR] = { 0x400C0000, 0x10000 }, 48fe0fe473SAlistair Francis [IBEX_AES] = { 0x40110000, 0x10000 }, 49fe0fe473SAlistair Francis [IBEX_HMAC] = { 0x40120000, 0x10000 }, 50fe0fe473SAlistair Francis [IBEX_ALERT_HANDLER] = { 0x40130000, 0x10000 }, 51fe0fe473SAlistair Francis [IBEX_NMI_GEN] = { 0x40140000, 0x10000 }, 52fe0fe473SAlistair Francis [IBEX_USBDEV] = { 0x40150000, 0x10000 }, 53fe0fe473SAlistair Francis [IBEX_PADCTRL] = { 0x40160000, 0x10000 } 54fe0fe473SAlistair Francis }; 55fe0fe473SAlistair Francis 56fe0fe473SAlistair Francis static void riscv_opentitan_init(MachineState *machine) 57fe0fe473SAlistair Francis { 58fe0fe473SAlistair Francis const struct MemmapEntry *memmap = ibex_memmap; 59fe0fe473SAlistair Francis OpenTitanState *s = g_new0(OpenTitanState, 1); 60fe0fe473SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 61fe0fe473SAlistair Francis MemoryRegion *main_mem = g_new(MemoryRegion, 1); 62fe0fe473SAlistair Francis 63fe0fe473SAlistair Francis /* Initialize SoC */ 64fe0fe473SAlistair Francis object_initialize_child(OBJECT(machine), "soc", &s->soc, 659fc7fc4dSMarkus Armbruster TYPE_RISCV_IBEX_SOC); 66ce189ab2SMarkus Armbruster qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 67fe0fe473SAlistair Francis 68fe0fe473SAlistair Francis memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", 69fe0fe473SAlistair Francis memmap[IBEX_RAM].size, &error_fatal); 70fe0fe473SAlistair Francis memory_region_add_subregion(sys_mem, 71fe0fe473SAlistair Francis memmap[IBEX_RAM].base, main_mem); 72fe0fe473SAlistair Francis 73fe0fe473SAlistair Francis 74fe0fe473SAlistair Francis if (machine->firmware) { 75fe0fe473SAlistair Francis riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL); 76fe0fe473SAlistair Francis } 77fe0fe473SAlistair Francis 78fe0fe473SAlistair Francis if (machine->kernel_filename) { 79fe0fe473SAlistair Francis riscv_load_kernel(machine->kernel_filename, NULL); 80fe0fe473SAlistair Francis } 81fe0fe473SAlistair Francis } 82fe0fe473SAlistair Francis 83fe0fe473SAlistair Francis static void riscv_opentitan_machine_init(MachineClass *mc) 84fe0fe473SAlistair Francis { 85fe0fe473SAlistair Francis mc->desc = "RISC-V Board compatible with OpenTitan"; 86fe0fe473SAlistair Francis mc->init = riscv_opentitan_init; 87fe0fe473SAlistair Francis mc->max_cpus = 1; 88fe0fe473SAlistair Francis mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 89fe0fe473SAlistair Francis } 90fe0fe473SAlistair Francis 91fe0fe473SAlistair Francis DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init) 92fe0fe473SAlistair Francis 93fe0fe473SAlistair Francis static void riscv_lowrisc_ibex_soc_init(Object *obj) 94fe0fe473SAlistair Francis { 95fe0fe473SAlistair Francis LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 96fe0fe473SAlistair Francis 97db873cc5SMarkus Armbruster object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 98*b9fc5135SAlistair Francis 99*b9fc5135SAlistair Francis object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); 100fe0fe473SAlistair Francis } 101fe0fe473SAlistair Francis 102fe0fe473SAlistair Francis static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 103fe0fe473SAlistair Francis { 104fe0fe473SAlistair Francis const struct MemmapEntry *memmap = ibex_memmap; 105fe0fe473SAlistair Francis MachineState *ms = MACHINE(qdev_get_machine()); 106fe0fe473SAlistair Francis LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 107fe0fe473SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 108*b9fc5135SAlistair Francis Error *err = NULL; 109fe0fe473SAlistair Francis 110fe0fe473SAlistair Francis object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", 111fe0fe473SAlistair Francis &error_abort); 112fe0fe473SAlistair Francis object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 113fe0fe473SAlistair Francis &error_abort); 114db873cc5SMarkus Armbruster sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 115fe0fe473SAlistair Francis 116fe0fe473SAlistair Francis /* Boot ROM */ 117fe0fe473SAlistair Francis memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 118fe0fe473SAlistair Francis memmap[IBEX_ROM].size, &error_fatal); 119fe0fe473SAlistair Francis memory_region_add_subregion(sys_mem, 120fe0fe473SAlistair Francis memmap[IBEX_ROM].base, &s->rom); 121fe0fe473SAlistair Francis 122fe0fe473SAlistair Francis /* Flash memory */ 123fe0fe473SAlistair Francis memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 124fe0fe473SAlistair Francis memmap[IBEX_FLASH].size, &error_fatal); 125fe0fe473SAlistair Francis memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base, 126fe0fe473SAlistair Francis &s->flash_mem); 127fe0fe473SAlistair Francis 128*b9fc5135SAlistair Francis /* PLIC */ 129*b9fc5135SAlistair Francis sysbus_realize(SYS_BUS_DEVICE(&s->plic), &err); 130*b9fc5135SAlistair Francis if (err != NULL) { 131*b9fc5135SAlistair Francis error_propagate(errp, err); 132*b9fc5135SAlistair Francis return; 133*b9fc5135SAlistair Francis } 134*b9fc5135SAlistair Francis sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base); 135*b9fc5135SAlistair Francis 136fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.uart", 137fe0fe473SAlistair Francis memmap[IBEX_UART].base, memmap[IBEX_UART].size); 138fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.gpio", 139fe0fe473SAlistair Francis memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size); 140fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.spi", 141fe0fe473SAlistair Francis memmap[IBEX_SPI].base, memmap[IBEX_SPI].size); 142fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 143fe0fe473SAlistair Francis memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size); 144fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", 145fe0fe473SAlistair Francis memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size); 146fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 147fe0fe473SAlistair Francis memmap[IBEX_PWRMGR].base, memmap[IBEX_PWRMGR].size); 148fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 149fe0fe473SAlistair Francis memmap[IBEX_RSTMGR].base, memmap[IBEX_RSTMGR].size); 150fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 151fe0fe473SAlistair Francis memmap[IBEX_CLKMGR].base, memmap[IBEX_CLKMGR].size); 152fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.aes", 153fe0fe473SAlistair Francis memmap[IBEX_AES].base, memmap[IBEX_AES].size); 154fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.hmac", 155fe0fe473SAlistair Francis memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size); 156fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 157fe0fe473SAlistair Francis memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size); 158fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 159fe0fe473SAlistair Francis memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size); 160fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", 161fe0fe473SAlistair Francis memmap[IBEX_NMI_GEN].base, memmap[IBEX_NMI_GEN].size); 162fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 163fe0fe473SAlistair Francis memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size); 164fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.padctrl", 165fe0fe473SAlistair Francis memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size); 166fe0fe473SAlistair Francis } 167fe0fe473SAlistair Francis 168fe0fe473SAlistair Francis static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 169fe0fe473SAlistair Francis { 170fe0fe473SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc); 171fe0fe473SAlistair Francis 172fe0fe473SAlistair Francis dc->realize = riscv_lowrisc_ibex_soc_realize; 173fe0fe473SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 174fe0fe473SAlistair Francis dc->user_creatable = false; 175fe0fe473SAlistair Francis } 176fe0fe473SAlistair Francis 177fe0fe473SAlistair Francis static const TypeInfo riscv_lowrisc_ibex_soc_type_info = { 178fe0fe473SAlistair Francis .name = TYPE_RISCV_IBEX_SOC, 179fe0fe473SAlistair Francis .parent = TYPE_DEVICE, 180fe0fe473SAlistair Francis .instance_size = sizeof(LowRISCIbexSoCState), 181fe0fe473SAlistair Francis .instance_init = riscv_lowrisc_ibex_soc_init, 182fe0fe473SAlistair Francis .class_init = riscv_lowrisc_ibex_soc_class_init, 183fe0fe473SAlistair Francis }; 184fe0fe473SAlistair Francis 185fe0fe473SAlistair Francis static void riscv_lowrisc_ibex_soc_register_types(void) 186fe0fe473SAlistair Francis { 187fe0fe473SAlistair Francis type_register_static(&riscv_lowrisc_ibex_soc_type_info); 188fe0fe473SAlistair Francis } 189fe0fe473SAlistair Francis 190fe0fe473SAlistair Francis type_init(riscv_lowrisc_ibex_soc_register_types) 191