1 /* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 10 * 11 * 0) CLINT (Core Level Interruptor) 12 * 1) PLIC (Platform Level Interrupt Controller) 13 * 2) eNVM (Embedded Non-Volatile Memory) 14 * 3) MMUARTs (Multi-Mode UART) 15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it 16 * 5) SiFive Platform DMA (Direct Memory Access Controller) 17 * 6) GEM (Gigabit Ethernet MAC Controller) 18 * 7) DMC (DDR Memory Controller) 19 * 8) IOSCB modules 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qemu/units.h" 40 #include "qemu/cutils.h" 41 #include "qapi/error.h" 42 #include "qapi/visitor.h" 43 #include "hw/boards.h" 44 #include "hw/loader.h" 45 #include "hw/sysbus.h" 46 #include "chardev/char.h" 47 #include "hw/cpu/cluster.h" 48 #include "target/riscv/cpu.h" 49 #include "hw/misc/unimp.h" 50 #include "hw/riscv/boot.h" 51 #include "hw/riscv/riscv_hart.h" 52 #include "hw/riscv/microchip_pfsoc.h" 53 #include "hw/intc/riscv_aclint.h" 54 #include "hw/intc/sifive_plic.h" 55 #include "system/device_tree.h" 56 #include "system/system.h" 57 58 /* 59 * The BIOS image used by this machine is called Hart Software Services (HSS). 60 * See https://github.com/polarfire-soc/hart-software-services 61 */ 62 #define BIOS_FILENAME "hss.bin" 63 #define RESET_VECTOR 0x20220000 64 65 /* GEM version */ 66 #define GEM_REVISION 0x0107010c 67 68 /* 69 * The complete description of the whole PolarFire SoC memory map is scattered 70 * in different documents. There are several places to look at for memory maps: 71 * 72 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 73 * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 74 * https://www.microsemi.com/document-portal/doc_download/ 75 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 76 * describes the whole picture of the PolarFire SoC memory map. 77 * 78 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 79 * https://www.microsemi.com/document-portal/doc_download/ 80 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 81 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 82 * describes the complete integrated peripherals memory map 83 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 84 * describes the complete IOSCB modules memory maps 85 */ 86 static const MemMapEntry microchip_pfsoc_memmap[] = { 87 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 88 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 89 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 90 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 91 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 92 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 93 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 94 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 95 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 96 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 97 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 98 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 99 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 100 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 101 [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, 102 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 103 [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, 104 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 105 [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, 106 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 107 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 108 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 109 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 110 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 111 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 112 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 113 [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, 114 [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, 115 [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, 116 [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, 117 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, 118 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, 119 [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, 120 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, 121 [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, 122 [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, 123 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 124 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 125 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 126 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 127 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 128 [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, 129 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 130 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 131 [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, 132 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, 133 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 134 [MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 }, 135 [MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 }, 136 [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, 137 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, 138 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, 139 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, 140 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, 141 142 }; 143 144 static void microchip_pfsoc_soc_instance_init(Object *obj) 145 { 146 MachineState *ms = MACHINE(qdev_get_machine()); 147 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 148 149 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 150 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 151 152 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 153 TYPE_RISCV_HART_ARRAY); 154 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 155 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 156 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 157 TYPE_RISCV_CPU_SIFIVE_E51); 158 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 159 160 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 161 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 162 163 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 164 TYPE_RISCV_HART_ARRAY); 165 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 166 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 167 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 168 TYPE_RISCV_CPU_SIFIVE_U54); 169 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 170 171 object_initialize_child(obj, "dma-controller", &s->dma, 172 TYPE_SIFIVE_PDMA); 173 174 object_initialize_child(obj, "sysreg", &s->sysreg, 175 TYPE_MCHP_PFSOC_SYSREG); 176 177 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 178 TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 179 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 180 TYPE_MCHP_PFSOC_DDR_CFG); 181 182 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 183 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 184 185 object_initialize_child(obj, "sd-controller", &s->sdhci, 186 TYPE_CADENCE_SDHCI); 187 188 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 189 } 190 191 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 192 { 193 MachineState *ms = MACHINE(qdev_get_machine()); 194 MicrochipIcicleKitState *iks = MICROCHIP_ICICLE_KIT_MACHINE(ms); 195 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 196 const MemMapEntry *memmap = microchip_pfsoc_memmap; 197 MemoryRegion *system_memory = get_system_memory(); 198 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 199 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 200 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 201 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 202 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 203 char *plic_hart_config; 204 int i; 205 206 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 207 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 208 /* 209 * The cluster must be realized after the RISC-V hart array container, 210 * as the container's CPU object is only created on realize, and the 211 * CPU must exist and have been parented into the cluster before the 212 * cluster is realized. 213 */ 214 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 215 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 216 217 /* Reserved Memory at address 0 */ 218 memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 219 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 220 memory_region_add_subregion(system_memory, 221 memmap[MICROCHIP_PFSOC_RSVD0].base, 222 rsvd0_mem); 223 224 /* E51 DTIM */ 225 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 226 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 227 memory_region_add_subregion(system_memory, 228 memmap[MICROCHIP_PFSOC_E51_DTIM].base, 229 e51_dtim_mem); 230 231 /* Bus Error Units */ 232 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 233 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 234 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 235 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 236 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 237 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 238 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 239 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 240 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 241 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 242 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 243 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 244 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 245 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 246 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 247 248 /* CLINT */ 249 riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base, 250 0, ms->smp.cpus, false); 251 riscv_aclint_mtimer_create( 252 memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, 253 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 254 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 255 iks->clint_timebase_freq, false); 256 257 /* L2 cache controller */ 258 create_unimplemented_device("microchip.pfsoc.l2cc", 259 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 260 261 /* 262 * Add L2-LIM at reset size. 263 * This should be reduced in size as the L2 Cache Controller WayEnable 264 * register is incremented. Unfortunately I don't see a nice (or any) way 265 * to handle reducing or blocking out the L2 LIM while still allowing it 266 * be re returned to all enabled after a reset. For the time being, just 267 * leave it enabled all the time. This won't break anything, but will be 268 * too generous to misbehaving guests. 269 */ 270 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 271 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 272 memory_region_add_subregion(system_memory, 273 memmap[MICROCHIP_PFSOC_L2LIM].base, 274 l2lim_mem); 275 276 /* create PLIC hart topology configuration string */ 277 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); 278 279 /* PLIC */ 280 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 281 plic_hart_config, ms->smp.cpus, 0, 282 MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 283 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 284 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 285 MICROCHIP_PFSOC_PLIC_PENDING_BASE, 286 MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 287 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 288 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 289 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 290 memmap[MICROCHIP_PFSOC_PLIC].size); 291 g_free(plic_hart_config); 292 293 /* DMA */ 294 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 296 memmap[MICROCHIP_PFSOC_DMA].base); 297 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 299 qdev_get_gpio_in(DEVICE(s->plic), 300 MICROCHIP_PFSOC_DMA_IRQ0 + i)); 301 } 302 303 /* SYSREG */ 304 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 305 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 306 memmap[MICROCHIP_PFSOC_SYSREG].base); 307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, 308 qdev_get_gpio_in(DEVICE(s->plic), 309 MICROCHIP_PFSOC_MAILBOX_IRQ)); 310 311 /* AXISW */ 312 create_unimplemented_device("microchip.pfsoc.axisw", 313 memmap[MICROCHIP_PFSOC_AXISW].base, 314 memmap[MICROCHIP_PFSOC_AXISW].size); 315 316 /* MPUCFG */ 317 create_unimplemented_device("microchip.pfsoc.mpucfg", 318 memmap[MICROCHIP_PFSOC_MPUCFG].base, 319 memmap[MICROCHIP_PFSOC_MPUCFG].size); 320 321 /* FMETER */ 322 create_unimplemented_device("microchip.pfsoc.fmeter", 323 memmap[MICROCHIP_PFSOC_FMETER].base, 324 memmap[MICROCHIP_PFSOC_FMETER].size); 325 326 /* DDR SGMII PHY */ 327 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 328 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 329 memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 330 331 /* DDR CFG */ 332 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 334 memmap[MICROCHIP_PFSOC_DDR_CFG].base); 335 336 /* SDHCI */ 337 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 338 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 339 memmap[MICROCHIP_PFSOC_EMMC_SD].base); 340 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 341 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 342 343 /* MMUARTs */ 344 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 345 memmap[MICROCHIP_PFSOC_MMUART0].base, 346 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 347 serial_hd(0)); 348 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 349 memmap[MICROCHIP_PFSOC_MMUART1].base, 350 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 351 serial_hd(1)); 352 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 353 memmap[MICROCHIP_PFSOC_MMUART2].base, 354 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 355 serial_hd(2)); 356 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 357 memmap[MICROCHIP_PFSOC_MMUART3].base, 358 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 359 serial_hd(3)); 360 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 361 memmap[MICROCHIP_PFSOC_MMUART4].base, 362 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 363 serial_hd(4)); 364 365 /* Watchdogs */ 366 create_unimplemented_device("microchip.pfsoc.watchdog0", 367 memmap[MICROCHIP_PFSOC_WDOG0].base, 368 memmap[MICROCHIP_PFSOC_WDOG0].size); 369 create_unimplemented_device("microchip.pfsoc.watchdog1", 370 memmap[MICROCHIP_PFSOC_WDOG1].base, 371 memmap[MICROCHIP_PFSOC_WDOG1].size); 372 create_unimplemented_device("microchip.pfsoc.watchdog2", 373 memmap[MICROCHIP_PFSOC_WDOG2].base, 374 memmap[MICROCHIP_PFSOC_WDOG2].size); 375 create_unimplemented_device("microchip.pfsoc.watchdog3", 376 memmap[MICROCHIP_PFSOC_WDOG3].base, 377 memmap[MICROCHIP_PFSOC_WDOG3].size); 378 create_unimplemented_device("microchip.pfsoc.watchdog4", 379 memmap[MICROCHIP_PFSOC_WDOG4].base, 380 memmap[MICROCHIP_PFSOC_WDOG4].size); 381 382 /* SPI */ 383 create_unimplemented_device("microchip.pfsoc.spi0", 384 memmap[MICROCHIP_PFSOC_SPI0].base, 385 memmap[MICROCHIP_PFSOC_SPI0].size); 386 create_unimplemented_device("microchip.pfsoc.spi1", 387 memmap[MICROCHIP_PFSOC_SPI1].base, 388 memmap[MICROCHIP_PFSOC_SPI1].size); 389 390 /* I2C */ 391 create_unimplemented_device("microchip.pfsoc.i2c0", 392 memmap[MICROCHIP_PFSOC_I2C0].base, 393 memmap[MICROCHIP_PFSOC_I2C0].size); 394 create_unimplemented_device("microchip.pfsoc.i2c1", 395 memmap[MICROCHIP_PFSOC_I2C1].base, 396 memmap[MICROCHIP_PFSOC_I2C1].size); 397 398 /* CAN */ 399 create_unimplemented_device("microchip.pfsoc.can0", 400 memmap[MICROCHIP_PFSOC_CAN0].base, 401 memmap[MICROCHIP_PFSOC_CAN0].size); 402 create_unimplemented_device("microchip.pfsoc.can1", 403 memmap[MICROCHIP_PFSOC_CAN1].base, 404 memmap[MICROCHIP_PFSOC_CAN1].size); 405 406 /* USB */ 407 create_unimplemented_device("microchip.pfsoc.usb", 408 memmap[MICROCHIP_PFSOC_USB].base, 409 memmap[MICROCHIP_PFSOC_USB].size); 410 411 /* GEMs */ 412 qemu_configure_nic_device(DEVICE(&s->gem0), true, NULL); 413 qemu_configure_nic_device(DEVICE(&s->gem1), true, NULL); 414 415 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 416 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 417 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 419 memmap[MICROCHIP_PFSOC_GEM0].base); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 421 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 422 423 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 424 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 425 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 427 memmap[MICROCHIP_PFSOC_GEM1].base); 428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 429 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 430 431 /* GPIOs */ 432 create_unimplemented_device("microchip.pfsoc.gpio0", 433 memmap[MICROCHIP_PFSOC_GPIO0].base, 434 memmap[MICROCHIP_PFSOC_GPIO0].size); 435 create_unimplemented_device("microchip.pfsoc.gpio1", 436 memmap[MICROCHIP_PFSOC_GPIO1].base, 437 memmap[MICROCHIP_PFSOC_GPIO1].size); 438 create_unimplemented_device("microchip.pfsoc.gpio2", 439 memmap[MICROCHIP_PFSOC_GPIO2].base, 440 memmap[MICROCHIP_PFSOC_GPIO2].size); 441 442 /* eNVM */ 443 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 444 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 445 &error_fatal); 446 memory_region_add_subregion(system_memory, 447 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 448 envm_data); 449 450 /* IOSCB */ 451 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 453 memmap[MICROCHIP_PFSOC_IOSCB].base); 454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0, 455 qdev_get_gpio_in(DEVICE(s->plic), 456 MICROCHIP_PFSOC_MAILBOX_IRQ)); 457 458 /* FPGA Fabric */ 459 create_unimplemented_device("microchip.pfsoc.fabricfic3", 460 memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base, 461 memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size); 462 /* FPGA Fabric */ 463 create_unimplemented_device("microchip.pfsoc.fabricfic0", 464 memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base, 465 memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size); 466 /* FPGA Fabric */ 467 create_unimplemented_device("microchip.pfsoc.fabricfic1", 468 memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base, 469 memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size); 470 471 /* QSPI Flash */ 472 memory_region_init_rom(qspi_xip_mem, OBJECT(dev), 473 "microchip.pfsoc.qspi_xip", 474 memmap[MICROCHIP_PFSOC_QSPI_XIP].size, 475 &error_fatal); 476 memory_region_add_subregion(system_memory, 477 memmap[MICROCHIP_PFSOC_QSPI_XIP].base, 478 qspi_xip_mem); 479 } 480 481 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, const void *data) 482 { 483 DeviceClass *dc = DEVICE_CLASS(oc); 484 485 dc->realize = microchip_pfsoc_soc_realize; 486 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 487 dc->user_creatable = false; 488 } 489 490 static const TypeInfo microchip_pfsoc_soc_type_info = { 491 .name = TYPE_MICROCHIP_PFSOC, 492 .parent = TYPE_DEVICE, 493 .instance_size = sizeof(MicrochipPFSoCState), 494 .instance_init = microchip_pfsoc_soc_instance_init, 495 .class_init = microchip_pfsoc_soc_class_init, 496 }; 497 498 static void microchip_pfsoc_soc_register_types(void) 499 { 500 type_register_static(µchip_pfsoc_soc_type_info); 501 } 502 503 type_init(microchip_pfsoc_soc_register_types) 504 505 static void microchip_icicle_kit_machine_init(MachineState *machine) 506 { 507 MachineClass *mc = MACHINE_GET_CLASS(machine); 508 const MemMapEntry *memmap = microchip_pfsoc_memmap; 509 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 510 MemoryRegion *system_memory = get_system_memory(); 511 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 512 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 513 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 514 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 515 uint64_t mem_low_size, mem_high_size; 516 hwaddr firmware_load_addr; 517 const char *firmware_name; 518 target_ulong firmware_end_addr, kernel_start_addr; 519 uint64_t kernel_entry; 520 uint64_t fdt_load_addr; 521 DriveInfo *dinfo = drive_get(IF_SD, 0, 0); 522 RISCVBootInfo boot_info; 523 524 /* Sanity check on RAM size */ 525 if (machine->ram_size < mc->default_ram_size) { 526 char *sz = size_to_str(mc->default_ram_size); 527 error_report("Invalid RAM size, should be bigger than %s", sz); 528 g_free(sz); 529 exit(EXIT_FAILURE); 530 } 531 532 /* Initialize SoC */ 533 object_initialize_child(OBJECT(machine), "soc", &s->soc, 534 TYPE_MICROCHIP_PFSOC); 535 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 536 537 /* Split RAM into low and high regions using aliases to machine->ram */ 538 mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; 539 mem_high_size = machine->ram_size - mem_low_size; 540 memory_region_init_alias(mem_low, NULL, 541 "microchip.icicle.kit.ram_low", machine->ram, 542 0, mem_low_size); 543 memory_region_init_alias(mem_high, NULL, 544 "microchip.icicle.kit.ram_high", machine->ram, 545 mem_low_size, mem_high_size); 546 547 /* Register RAM */ 548 memory_region_add_subregion(system_memory, 549 memmap[MICROCHIP_PFSOC_DRAM_LO].base, 550 mem_low); 551 memory_region_add_subregion(system_memory, 552 memmap[MICROCHIP_PFSOC_DRAM_HI].base, 553 mem_high); 554 555 /* Create aliases for the low and high RAM regions */ 556 memory_region_init_alias(mem_low_alias, NULL, 557 "microchip.icicle.kit.ram_low.alias", 558 mem_low, 0, mem_low_size); 559 memory_region_add_subregion(system_memory, 560 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, 561 mem_low_alias); 562 memory_region_init_alias(mem_high_alias, NULL, 563 "microchip.icicle.kit.ram_high.alias", 564 mem_high, 0, mem_high_size); 565 memory_region_add_subregion(system_memory, 566 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, 567 mem_high_alias); 568 569 /* Attach an SD card */ 570 if (dinfo) { 571 CadenceSDHCIState *sdhci = &(s->soc.sdhci); 572 DeviceState *card = qdev_new(TYPE_SD_CARD); 573 574 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 575 &error_fatal); 576 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 577 } 578 579 /* 580 * We follow the following table to select which firmware we use. 581 * 582 * -bios | -kernel | firmware 583 * --------------+------------+-------- 584 * none | N | error 585 * none | Y | kernel 586 * NULL, default | N | BIOS_FILENAME 587 * NULL, default | Y | RISCV64_BIOS_BIN 588 * other | don't care | other 589 */ 590 if (machine->firmware && !strcmp(machine->firmware, "none")) { 591 if (!machine->kernel_filename) { 592 error_report("for -bios none, a kernel is required"); 593 exit(1); 594 } 595 596 firmware_name = NULL; 597 firmware_load_addr = RESET_VECTOR; 598 } else if (!machine->firmware || !strcmp(machine->firmware, "default")) { 599 if (machine->kernel_filename) { 600 firmware_name = RISCV64_BIOS_BIN; 601 firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base; 602 } else { 603 firmware_name = BIOS_FILENAME; 604 firmware_load_addr = RESET_VECTOR; 605 } 606 } else { 607 firmware_name = machine->firmware; 608 firmware_load_addr = RESET_VECTOR; 609 } 610 611 /* Load the firmware if necessary */ 612 firmware_end_addr = firmware_load_addr; 613 if (firmware_name) { 614 char *filename = riscv_find_firmware(firmware_name, NULL); 615 if (filename) { 616 firmware_end_addr = riscv_load_firmware(filename, 617 &firmware_load_addr, NULL); 618 g_free(filename); 619 } 620 } 621 622 riscv_boot_info_init(&boot_info, &s->soc.u_cpus); 623 if (machine->kernel_filename) { 624 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, 625 firmware_end_addr); 626 627 riscv_load_kernel(machine, &boot_info, kernel_start_addr, 628 true, NULL); 629 kernel_entry = boot_info.image_low_addr; 630 631 if (machine->dtb) { 632 int fdt_size; 633 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 634 if (!machine->fdt) { 635 error_report("load_device_tree() failed"); 636 exit(1); 637 } 638 639 /* Compute the FDT load address in DRAM */ 640 hwaddr kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_LO].base; 641 hwaddr kernel_ram_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; 642 643 if (kernel_entry - kernel_ram_base >= kernel_ram_size) { 644 kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base; 645 kernel_ram_size = mem_high_size; 646 } 647 648 fdt_load_addr = riscv_compute_fdt_addr(kernel_ram_base, kernel_ram_size, 649 machine, &boot_info); 650 riscv_load_fdt(fdt_load_addr, machine->fdt); 651 } else { 652 warn_report_once("The QEMU microchip-icicle-kit machine does not " 653 "generate a device tree, so no device tree is " 654 "being provided to the guest."); 655 fdt_load_addr = 0; 656 } 657 658 hwaddr start_addr; 659 if (firmware_name) { 660 start_addr = firmware_load_addr; 661 } else { 662 start_addr = kernel_entry; 663 } 664 665 /* Load the reset vector */ 666 riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, start_addr, 667 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 668 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 669 kernel_entry, fdt_load_addr); 670 } 671 } 672 673 static void microchip_icicle_kit_set_clint_timebase_freq(Object *obj, 674 Visitor *v, 675 const char *name, 676 void *opaque, 677 Error **errp) 678 { 679 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(obj); 680 uint32_t value; 681 682 if (!visit_type_uint32(v, name, &value, errp)) { 683 return; 684 } 685 686 s->clint_timebase_freq = value; 687 } 688 689 static void microchip_icicle_kit_get_clint_timebase_freq(Object *obj, 690 Visitor *v, 691 const char *name, 692 void *opaque, 693 Error **errp) 694 { 695 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(obj); 696 uint32_t value = s->clint_timebase_freq; 697 698 visit_type_uint32(v, name, &value, errp); 699 } 700 701 static void microchip_icicle_kit_machine_instance_init(Object *obj) 702 { 703 MicrochipIcicleKitState *m = MICROCHIP_ICICLE_KIT_MACHINE(obj); 704 m->clint_timebase_freq = 1000000; 705 } 706 707 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, 708 const void *data) 709 { 710 MachineClass *mc = MACHINE_CLASS(oc); 711 712 mc->desc = "Microchip PolarFire SoC Icicle Kit"; 713 mc->init = microchip_icicle_kit_machine_init; 714 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 715 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 716 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 717 mc->default_cpus = mc->min_cpus; 718 mc->default_ram_id = "microchip.icicle.kit.ram"; 719 mc->auto_create_sdcard = true; 720 721 /* 722 * Map 513 MiB high memory, the minimum required high memory size, because 723 * HSS will do memory test against the high memory address range regardless 724 * of physical memory installed. 725 * 726 * See memory_tests() in mss_ddr.c in the HSS source code. 727 */ 728 mc->default_ram_size = 1537 * MiB; 729 730 object_class_property_add(oc, "clint-timebase-frequency", "uint32_t", 731 microchip_icicle_kit_get_clint_timebase_freq, 732 microchip_icicle_kit_set_clint_timebase_freq, 733 NULL, NULL); 734 object_class_property_set_description(oc, "clint-timebase-frequency", 735 "Set CLINT timebase frequency in Hz."); 736 } 737 738 static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 739 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 740 .parent = TYPE_MACHINE, 741 .class_init = microchip_icicle_kit_machine_class_init, 742 .instance_init = microchip_icicle_kit_machine_instance_init, 743 .instance_size = sizeof(MicrochipIcicleKitState), 744 }; 745 746 static void microchip_icicle_kit_machine_init_register_types(void) 747 { 748 type_register_static(µchip_icicle_kit_machine_typeinfo); 749 } 750 751 type_init(microchip_icicle_kit_machine_init_register_types) 752