1 /* 2 * QEMU model of Microblaze V generic board. 3 * 4 * based on hw/microblaze/petalogix_ml605_mmu.c 5 * 6 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> 7 * Copyright (c) 2011 PetaLogix 8 * Copyright (c) 2009 Edgar E. Iglesias. 9 * Copyright (C) 2024, Advanced Micro Devices, Inc. 10 * SPDX-License-Identifier: GPL-2.0-or-later 11 * 12 * Written by Sai Pavan Boddu <sai.pavan.boddu@amd.com 13 * and by Michal Simek <michal.simek@amd.com>. 14 */ 15 16 #include "qemu/osdep.h" 17 #include "qemu/units.h" 18 #include "qapi/error.h" 19 #include "cpu.h" 20 #include "hw/sysbus.h" 21 #include "system/system.h" 22 #include "net/net.h" 23 #include "hw/boards.h" 24 #include "hw/char/serial-mm.h" 25 #include "exec/address-spaces.h" 26 #include "hw/char/xilinx_uartlite.h" 27 #include "hw/misc/unimp.h" 28 29 #define LMB_BRAM_SIZE (128 * KiB) 30 #define MEMORY_BASEADDR 0x80000000 31 #define INTC_BASEADDR 0x41200000 32 #define TIMER_BASEADDR 0x41c00000 33 #define TIMER_BASEADDR2 0x41c10000 34 #define UARTLITE_BASEADDR 0x40600000 35 #define ETHLITE_BASEADDR 0x40e00000 36 #define UART16550_BASEADDR 0x44a10000 37 #define AXIENET_BASEADDR 0x40c00000 38 #define AXIDMA_BASEADDR 0x41e00000 39 #define GPIO_BASEADDR 0x40000000 40 #define GPIO_BASEADDR2 0x40010000 41 #define GPIO_BASEADDR3 0x40020000 42 #define I2C_BASEADDR 0x40800000 43 #define QSPI_BASEADDR 0x44a00000 44 45 #define TIMER_IRQ 0 46 #define UARTLITE_IRQ 1 47 #define UART16550_IRQ 4 48 #define ETHLITE_IRQ 5 49 #define TIMER_IRQ2 6 50 #define AXIENET_IRQ 7 51 #define AXIDMA_IRQ1 8 52 #define AXIDMA_IRQ0 9 53 54 static void mb_v_generic_init(MachineState *machine) 55 { 56 ram_addr_t ram_size = machine->ram_size; 57 DeviceState *dev, *dma, *eth0; 58 Object *ds, *cs; 59 int i; 60 RISCVCPU *cpu; 61 hwaddr ddr_base = MEMORY_BASEADDR; 62 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); 63 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 64 qemu_irq irq[32]; 65 MemoryRegion *sysmem = get_system_memory(); 66 67 cpu = RISCV_CPU(object_new(machine->cpu_type)); 68 object_property_set_bool(OBJECT(cpu), "h", false, NULL); 69 object_property_set_bool(OBJECT(cpu), "d", false, NULL); 70 qdev_realize(DEVICE(cpu), NULL, &error_abort); 71 /* Attach emulated BRAM through the LMB. */ 72 memory_region_init_ram(phys_lmb_bram, NULL, 73 "mb_v.lmb_bram", LMB_BRAM_SIZE, 74 &error_fatal); 75 memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram); 76 77 memory_region_init_ram(phys_ram, NULL, "mb_v.ram", 78 ram_size, &error_fatal); 79 memory_region_add_subregion(sysmem, ddr_base, phys_ram); 80 81 dev = qdev_new("xlnx.xps-intc"); 82 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE); 83 qdev_prop_set_uint32(dev, "kind-of-intr", 84 1 << UARTLITE_IRQ); 85 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 86 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 87 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 88 qdev_get_gpio_in(DEVICE(cpu), 11)); 89 for (i = 0; i < 32; i++) { 90 irq[i] = qdev_get_gpio_in(dev, i); 91 } 92 93 /* Uartlite */ 94 dev = qdev_new(TYPE_XILINX_UARTLITE); 95 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE); 96 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 97 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 98 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); 99 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]); 100 101 /* Full uart */ 102 serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2, 103 irq[UART16550_IRQ], 115200, serial_hd(1), 104 DEVICE_LITTLE_ENDIAN); 105 106 /* 2 timers at irq 0 @ 100 Mhz. */ 107 dev = qdev_new("xlnx.xps-timer"); 108 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE); 109 qdev_prop_set_uint32(dev, "one-timer-only", 0); 110 qdev_prop_set_uint32(dev, "clock-frequency", 100000000); 111 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 112 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 113 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 114 115 /* 2 timers at irq 3 @ 100 Mhz. */ 116 dev = qdev_new("xlnx.xps-timer"); 117 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE); 118 qdev_prop_set_uint32(dev, "one-timer-only", 0); 119 qdev_prop_set_uint32(dev, "clock-frequency", 100000000); 120 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 121 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2); 122 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]); 123 124 /* Emaclite */ 125 dev = qdev_new("xlnx.xps-ethernetlite"); 126 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE); 127 qemu_configure_nic_device(dev, true, NULL); 128 qdev_prop_set_uint32(dev, "tx-ping-pong", 0); 129 qdev_prop_set_uint32(dev, "rx-ping-pong", 0); 130 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 131 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); 132 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); 133 134 /* axi ethernet and dma initialization. */ 135 eth0 = qdev_new("xlnx.axi-ethernet"); 136 dma = qdev_new("xlnx.axi-dma"); 137 138 /* FIXME: attach to the sysbus instead */ 139 object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0)); 140 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma)); 141 142 ds = object_property_get_link(OBJECT(dma), 143 "axistream-connected-target", NULL); 144 cs = object_property_get_link(OBJECT(dma), 145 "axistream-control-connected-target", NULL); 146 qemu_configure_nic_device(eth0, true, NULL); 147 qdev_prop_set_uint32(eth0, "rxmem", 0x1000); 148 qdev_prop_set_uint32(eth0, "txmem", 0x1000); 149 object_property_set_link(OBJECT(eth0), "axistream-connected", ds, 150 &error_abort); 151 object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs, 152 &error_abort); 153 sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal); 154 sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR); 155 sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]); 156 157 ds = object_property_get_link(OBJECT(eth0), 158 "axistream-connected-target", NULL); 159 cs = object_property_get_link(OBJECT(eth0), 160 "axistream-control-connected-target", NULL); 161 qdev_prop_set_uint32(dma, "freqhz", 100000000); 162 object_property_set_link(OBJECT(dma), "axistream-connected", ds, 163 &error_abort); 164 object_property_set_link(OBJECT(dma), "axistream-control-connected", cs, 165 &error_abort); 166 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 167 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); 168 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]); 169 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]); 170 171 /* unimplemented devices */ 172 create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000); 173 create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000); 174 create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000); 175 create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000); 176 create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000); 177 } 178 179 static void mb_v_generic_machine_init(MachineClass *mc) 180 { 181 mc->desc = "AMD Microblaze-V generic platform"; 182 mc->init = mb_v_generic_init; 183 mc->min_cpus = 1; 184 mc->max_cpus = 1; 185 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 186 mc->default_cpus = 1; 187 } 188 189 DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init) 190