xref: /qemu/hw/riscv/meson.build (revision 56f6e31e7b7e06a66a0efd5464fa4257de7ec242)
12c44220dSMarc-André Lureauriscv_ss = ss.source_set()
2feabc71dSPaolo Bonziniriscv_ss.add(files('boot.c'), fdt)
383fcaefdSAnup Patelriscv_ss.add(files('numa.c'))
42c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
52c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
62c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
72c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
82c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
92c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
102c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
112c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
122c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
132c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
142c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
152c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
162c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
172c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
182c44220dSMarc-André Lureauriscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
19*56f6e31eSBin Mengriscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
202c44220dSMarc-André Lureau
212c44220dSMarc-André Lureauhw_arch += {'riscv': riscv_ss}
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