1 /* 2 * Copyright © 2018, 2021 Oracle and/or its affiliates. 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 * 7 */ 8 9 #include "qemu/osdep.h" 10 11 #include "hw/remote/proxy.h" 12 #include "hw/pci/pci.h" 13 #include "qapi/error.h" 14 #include "io/channel-util.h" 15 #include "hw/qdev-properties.h" 16 #include "monitor/monitor.h" 17 #include "migration/blocker.h" 18 #include "qemu/sockets.h" 19 #include "hw/remote/mpqemu-link.h" 20 #include "qemu/error-report.h" 21 #include "hw/remote/proxy-memory-listener.h" 22 #include "qom/object.h" 23 #include "qemu/event_notifier.h" 24 #include "system/kvm.h" 25 26 static void probe_pci_info(PCIDevice *dev, Error **errp); 27 static void proxy_device_reset(DeviceState *dev); 28 29 static void proxy_intx_update(PCIDevice *pci_dev) 30 { 31 PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev); 32 PCIINTxRoute route; 33 int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 34 35 if (dev->virq != -1) { 36 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq); 37 dev->virq = -1; 38 } 39 40 route = pci_device_route_intx_to_irq(pci_dev, pin); 41 42 dev->virq = route.irq; 43 44 if (dev->virq != -1) { 45 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr, 46 &dev->resample, dev->virq); 47 } 48 } 49 50 static void setup_irqfd(PCIProxyDev *dev) 51 { 52 PCIDevice *pci_dev = PCI_DEVICE(dev); 53 MPQemuMsg msg; 54 Error *local_err = NULL; 55 56 event_notifier_init(&dev->intr, 0); 57 event_notifier_init(&dev->resample, 0); 58 59 memset(&msg, 0, sizeof(MPQemuMsg)); 60 msg.cmd = MPQEMU_CMD_SET_IRQFD; 61 msg.num_fds = 2; 62 msg.fds[0] = event_notifier_get_fd(&dev->intr); 63 msg.fds[1] = event_notifier_get_fd(&dev->resample); 64 msg.size = 0; 65 66 if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) { 67 error_report_err(local_err); 68 } 69 70 dev->virq = -1; 71 72 proxy_intx_update(pci_dev); 73 74 pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update); 75 } 76 77 static void pci_proxy_dev_realize(PCIDevice *device, Error **errp) 78 { 79 ERRP_GUARD(); 80 PCIProxyDev *dev = PCI_PROXY_DEV(device); 81 uint8_t *pci_conf = device->config; 82 int fd; 83 84 if (!dev->fd) { 85 error_setg(errp, "fd parameter not specified for %s", 86 DEVICE(device)->id); 87 return; 88 } 89 90 fd = monitor_fd_param(monitor_cur(), dev->fd, errp); 91 if (fd == -1) { 92 error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd); 93 return; 94 } 95 96 if (!fd_is_socket(fd)) { 97 error_setg(errp, "proxy: fd %d is not a socket", fd); 98 close(fd); 99 return; 100 } 101 102 dev->ioc = qio_channel_new_fd(fd, errp); 103 if (!dev->ioc) { 104 close(fd); 105 return; 106 } 107 108 error_setg(&dev->migration_blocker, "%s does not support migration", 109 TYPE_PCI_PROXY_DEV); 110 if (migrate_add_blocker(&dev->migration_blocker, errp) < 0) { 111 object_unref(dev->ioc); 112 return; 113 } 114 115 qemu_mutex_init(&dev->io_mutex); 116 qio_channel_set_blocking(dev->ioc, true, NULL); 117 118 pci_conf[PCI_LATENCY_TIMER] = 0xff; 119 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 120 121 proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc); 122 123 setup_irqfd(dev); 124 125 probe_pci_info(PCI_DEVICE(dev), errp); 126 } 127 128 static void pci_proxy_dev_exit(PCIDevice *pdev) 129 { 130 PCIProxyDev *dev = PCI_PROXY_DEV(pdev); 131 132 if (dev->ioc) { 133 qio_channel_close(dev->ioc, NULL); 134 } 135 136 migrate_del_blocker(&dev->migration_blocker); 137 138 proxy_memory_listener_deconfigure(&dev->proxy_listener); 139 140 event_notifier_cleanup(&dev->intr); 141 event_notifier_cleanup(&dev->resample); 142 } 143 144 static void config_op_send(PCIProxyDev *pdev, uint32_t addr, uint32_t *val, 145 int len, unsigned int op) 146 { 147 MPQemuMsg msg = { 0 }; 148 uint64_t ret = -EINVAL; 149 Error *local_err = NULL; 150 151 msg.cmd = op; 152 msg.data.pci_conf_data.addr = addr; 153 msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0; 154 msg.data.pci_conf_data.len = len; 155 msg.size = sizeof(PciConfDataMsg); 156 157 ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 158 if (local_err) { 159 error_report_err(local_err); 160 } 161 162 if (ret == UINT64_MAX) { 163 error_report("Failed to perform PCI config %s operation", 164 (op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE"); 165 } 166 167 if (op == MPQEMU_CMD_PCI_CFGREAD) { 168 *val = (uint32_t)ret; 169 } 170 } 171 172 static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len) 173 { 174 uint32_t val; 175 176 config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD); 177 178 return val; 179 } 180 181 static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val, 182 int len) 183 { 184 /* 185 * Some of the functions access the copy of remote device's PCI config 186 * space which is cached in the proxy device. Therefore, maintain 187 * it updated. 188 */ 189 pci_default_write_config(d, addr, val, len); 190 191 config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE); 192 } 193 194 static const Property proxy_properties[] = { 195 DEFINE_PROP_STRING("fd", PCIProxyDev, fd), 196 }; 197 198 static void pci_proxy_dev_class_init(ObjectClass *klass, void *data) 199 { 200 DeviceClass *dc = DEVICE_CLASS(klass); 201 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 202 203 k->realize = pci_proxy_dev_realize; 204 k->exit = pci_proxy_dev_exit; 205 k->config_read = pci_proxy_read_config; 206 k->config_write = pci_proxy_write_config; 207 208 device_class_set_legacy_reset(dc, proxy_device_reset); 209 210 device_class_set_props(dc, proxy_properties); 211 } 212 213 static const TypeInfo pci_proxy_dev_type_info = { 214 .name = TYPE_PCI_PROXY_DEV, 215 .parent = TYPE_PCI_DEVICE, 216 .instance_size = sizeof(PCIProxyDev), 217 .class_init = pci_proxy_dev_class_init, 218 .interfaces = (InterfaceInfo[]) { 219 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 220 { }, 221 }, 222 }; 223 224 static void pci_proxy_dev_register_types(void) 225 { 226 type_register_static(&pci_proxy_dev_type_info); 227 } 228 229 type_init(pci_proxy_dev_register_types) 230 231 static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr, 232 bool write, hwaddr addr, uint64_t *val, 233 unsigned size, bool memory) 234 { 235 MPQemuMsg msg = { 0 }; 236 long ret = -EINVAL; 237 Error *local_err = NULL; 238 239 msg.size = sizeof(BarAccessMsg); 240 msg.data.bar_access.addr = mr->addr + addr; 241 msg.data.bar_access.size = size; 242 msg.data.bar_access.memory = memory; 243 244 if (write) { 245 msg.cmd = MPQEMU_CMD_BAR_WRITE; 246 msg.data.bar_access.val = *val; 247 } else { 248 msg.cmd = MPQEMU_CMD_BAR_READ; 249 } 250 251 ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 252 if (local_err) { 253 error_report_err(local_err); 254 } 255 256 if (!write) { 257 *val = ret; 258 } 259 } 260 261 static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val, 262 unsigned size) 263 { 264 ProxyMemoryRegion *pmr = opaque; 265 266 send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size, 267 pmr->memory); 268 } 269 270 static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size) 271 { 272 ProxyMemoryRegion *pmr = opaque; 273 uint64_t val; 274 275 send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size, 276 pmr->memory); 277 278 return val; 279 } 280 281 const MemoryRegionOps proxy_mr_ops = { 282 .read = proxy_bar_read, 283 .write = proxy_bar_write, 284 .endianness = DEVICE_NATIVE_ENDIAN, 285 .impl = { 286 .min_access_size = 1, 287 .max_access_size = 8, 288 }, 289 }; 290 291 static void probe_pci_info(PCIDevice *dev, Error **errp) 292 { 293 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 294 uint32_t orig_val, new_val, base_class, val; 295 PCIProxyDev *pdev = PCI_PROXY_DEV(dev); 296 DeviceClass *dc = DEVICE_CLASS(pc); 297 uint8_t type; 298 int i, size; 299 300 config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 301 pc->vendor_id = (uint16_t)val; 302 303 config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 304 pc->device_id = (uint16_t)val; 305 306 config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 307 pc->class_id = (uint16_t)val; 308 309 config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 310 pc->subsystem_id = (uint16_t)val; 311 312 base_class = pc->class_id >> 4; 313 switch (base_class) { 314 case PCI_BASE_CLASS_BRIDGE: 315 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 316 break; 317 case PCI_BASE_CLASS_STORAGE: 318 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 319 break; 320 case PCI_BASE_CLASS_NETWORK: 321 case PCI_BASE_CLASS_WIRELESS: 322 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 323 break; 324 case PCI_BASE_CLASS_INPUT: 325 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 326 break; 327 case PCI_BASE_CLASS_DISPLAY: 328 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 329 break; 330 case PCI_BASE_CLASS_PROCESSOR: 331 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 332 break; 333 default: 334 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 335 break; 336 } 337 338 for (i = 0; i < PCI_NUM_REGIONS; i++) { 339 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, 340 MPQEMU_CMD_PCI_CFGREAD); 341 new_val = 0xffffffff; 342 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, 343 MPQEMU_CMD_PCI_CFGWRITE); 344 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, 345 MPQEMU_CMD_PCI_CFGREAD); 346 size = (~(new_val & 0xFFFFFFF0)) + 1; 347 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, 348 MPQEMU_CMD_PCI_CFGWRITE); 349 type = (new_val & 0x1) ? 350 PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY; 351 352 if (size) { 353 g_autofree char *name = g_strdup_printf("bar-region-%d", i); 354 pdev->region[i].dev = pdev; 355 pdev->region[i].present = true; 356 if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) { 357 pdev->region[i].memory = true; 358 } 359 memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev), 360 &proxy_mr_ops, &pdev->region[i], 361 name, size); 362 pci_register_bar(dev, i, type, &pdev->region[i].mr); 363 } 364 } 365 } 366 367 static void proxy_device_reset(DeviceState *dev) 368 { 369 PCIProxyDev *pdev = PCI_PROXY_DEV(dev); 370 MPQemuMsg msg = { 0 }; 371 Error *local_err = NULL; 372 373 msg.cmd = MPQEMU_CMD_DEVICE_RESET; 374 msg.size = 0; 375 376 mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 377 if (local_err) { 378 error_report_err(local_err); 379 } 380 381 } 382