1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "hw/hw.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/msi.h" 29 #include "hw/pci/msix.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/ppc/spapr.h" 32 #include "hw/pci-host/spapr.h" 33 #include "exec/address-spaces.h" 34 #include <libfdt.h> 35 #include "trace.h" 36 #include "qemu/error-report.h" 37 #include "qapi/qmp/qerror.h" 38 39 #include "hw/pci/pci_bridge.h" 40 #include "hw/pci/pci_bus.h" 41 #include "hw/ppc/spapr_drc.h" 42 #include "sysemu/device_tree.h" 43 44 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 45 #define RTAS_QUERY_FN 0 46 #define RTAS_CHANGE_FN 1 47 #define RTAS_RESET_FN 2 48 #define RTAS_CHANGE_MSI_FN 3 49 #define RTAS_CHANGE_MSIX_FN 4 50 51 /* Interrupt types to return on RTAS_CHANGE_* */ 52 #define RTAS_TYPE_MSI 1 53 #define RTAS_TYPE_MSIX 2 54 55 #define FDT_NAME_MAX 128 56 57 #define _FDT(exp) \ 58 do { \ 59 int ret = (exp); \ 60 if (ret < 0) { \ 61 return ret; \ 62 } \ 63 } while (0) 64 65 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) 66 { 67 sPAPRPHBState *sphb; 68 69 QLIST_FOREACH(sphb, &spapr->phbs, list) { 70 if (sphb->buid != buid) { 71 continue; 72 } 73 return sphb; 74 } 75 76 return NULL; 77 } 78 79 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 80 uint32_t config_addr) 81 { 82 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); 83 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 84 int bus_num = (config_addr >> 16) & 0xFF; 85 int devfn = (config_addr >> 8) & 0xFF; 86 87 if (!phb) { 88 return NULL; 89 } 90 91 return pci_find_device(phb->bus, bus_num, devfn); 92 } 93 94 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 95 { 96 /* This handles the encoding of extended config space addresses */ 97 return ((arg >> 20) & 0xf00) | (arg & 0xff); 98 } 99 100 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, 101 uint32_t addr, uint32_t size, 102 target_ulong rets) 103 { 104 PCIDevice *pci_dev; 105 uint32_t val; 106 107 if ((size != 1) && (size != 2) && (size != 4)) { 108 /* access must be 1, 2 or 4 bytes */ 109 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 110 return; 111 } 112 113 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 114 addr = rtas_pci_cfgaddr(addr); 115 116 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 117 /* Access must be to a valid device, within bounds and 118 * naturally aligned */ 119 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 120 return; 121 } 122 123 val = pci_host_config_read_common(pci_dev, addr, 124 pci_config_size(pci_dev), size); 125 126 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 127 rtas_st(rets, 1, val); 128 } 129 130 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 131 uint32_t token, uint32_t nargs, 132 target_ulong args, 133 uint32_t nret, target_ulong rets) 134 { 135 uint64_t buid; 136 uint32_t size, addr; 137 138 if ((nargs != 4) || (nret != 2)) { 139 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 140 return; 141 } 142 143 buid = rtas_ldq(args, 1); 144 size = rtas_ld(args, 3); 145 addr = rtas_ld(args, 0); 146 147 finish_read_pci_config(spapr, buid, addr, size, rets); 148 } 149 150 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 151 uint32_t token, uint32_t nargs, 152 target_ulong args, 153 uint32_t nret, target_ulong rets) 154 { 155 uint32_t size, addr; 156 157 if ((nargs != 2) || (nret != 2)) { 158 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 159 return; 160 } 161 162 size = rtas_ld(args, 1); 163 addr = rtas_ld(args, 0); 164 165 finish_read_pci_config(spapr, 0, addr, size, rets); 166 } 167 168 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, 169 uint32_t addr, uint32_t size, 170 uint32_t val, target_ulong rets) 171 { 172 PCIDevice *pci_dev; 173 174 if ((size != 1) && (size != 2) && (size != 4)) { 175 /* access must be 1, 2 or 4 bytes */ 176 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 177 return; 178 } 179 180 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 181 addr = rtas_pci_cfgaddr(addr); 182 183 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 184 /* Access must be to a valid device, within bounds and 185 * naturally aligned */ 186 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 187 return; 188 } 189 190 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 191 val, size); 192 193 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 194 } 195 196 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 197 uint32_t token, uint32_t nargs, 198 target_ulong args, 199 uint32_t nret, target_ulong rets) 200 { 201 uint64_t buid; 202 uint32_t val, size, addr; 203 204 if ((nargs != 5) || (nret != 1)) { 205 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 206 return; 207 } 208 209 buid = rtas_ldq(args, 1); 210 val = rtas_ld(args, 4); 211 size = rtas_ld(args, 3); 212 addr = rtas_ld(args, 0); 213 214 finish_write_pci_config(spapr, buid, addr, size, val, rets); 215 } 216 217 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 218 uint32_t token, uint32_t nargs, 219 target_ulong args, 220 uint32_t nret, target_ulong rets) 221 { 222 uint32_t val, size, addr; 223 224 if ((nargs != 3) || (nret != 1)) { 225 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 226 return; 227 } 228 229 230 val = rtas_ld(args, 2); 231 size = rtas_ld(args, 1); 232 addr = rtas_ld(args, 0); 233 234 finish_write_pci_config(spapr, 0, addr, size, val, rets); 235 } 236 237 /* 238 * Set MSI/MSIX message data. 239 * This is required for msi_notify()/msix_notify() which 240 * will write at the addresses via spapr_msi_write(). 241 * 242 * If hwaddr == 0, all entries will have .data == first_irq i.e. 243 * table will be reset. 244 */ 245 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 246 unsigned first_irq, unsigned req_num) 247 { 248 unsigned i; 249 MSIMessage msg = { .address = addr, .data = first_irq }; 250 251 if (!msix) { 252 msi_set_message(pdev, msg); 253 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 254 return; 255 } 256 257 for (i = 0; i < req_num; ++i) { 258 msix_set_message(pdev, i, msg); 259 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 260 if (addr) { 261 ++msg.data; 262 } 263 } 264 } 265 266 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 267 uint32_t token, uint32_t nargs, 268 target_ulong args, uint32_t nret, 269 target_ulong rets) 270 { 271 uint32_t config_addr = rtas_ld(args, 0); 272 uint64_t buid = rtas_ldq(args, 1); 273 unsigned int func = rtas_ld(args, 3); 274 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 275 unsigned int seq_num = rtas_ld(args, 5); 276 unsigned int ret_intr_type; 277 unsigned int irq, max_irqs = 0, num = 0; 278 sPAPRPHBState *phb = NULL; 279 PCIDevice *pdev = NULL; 280 spapr_pci_msi *msi; 281 int *config_addr_key; 282 283 switch (func) { 284 case RTAS_CHANGE_MSI_FN: 285 case RTAS_CHANGE_FN: 286 ret_intr_type = RTAS_TYPE_MSI; 287 break; 288 case RTAS_CHANGE_MSIX_FN: 289 ret_intr_type = RTAS_TYPE_MSIX; 290 break; 291 default: 292 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 293 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 294 return; 295 } 296 297 /* Fins sPAPRPHBState */ 298 phb = spapr_pci_find_phb(spapr, buid); 299 if (phb) { 300 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 301 } 302 if (!phb || !pdev) { 303 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 304 return; 305 } 306 307 /* Releasing MSIs */ 308 if (!req_num) { 309 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 310 if (!msi) { 311 trace_spapr_pci_msi("Releasing wrong config", config_addr); 312 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 313 return; 314 } 315 316 xics_free(spapr->icp, msi->first_irq, msi->num); 317 if (msi_present(pdev)) { 318 spapr_msi_setmsg(pdev, 0, false, 0, num); 319 } 320 if (msix_present(pdev)) { 321 spapr_msi_setmsg(pdev, 0, true, 0, num); 322 } 323 g_hash_table_remove(phb->msi, &config_addr); 324 325 trace_spapr_pci_msi("Released MSIs", config_addr); 326 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 327 rtas_st(rets, 1, 0); 328 return; 329 } 330 331 /* Enabling MSI */ 332 333 /* Check if the device supports as many IRQs as requested */ 334 if (ret_intr_type == RTAS_TYPE_MSI) { 335 max_irqs = msi_nr_vectors_allocated(pdev); 336 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 337 max_irqs = pdev->msix_entries_nr; 338 } 339 if (!max_irqs) { 340 error_report("Requested interrupt type %d is not enabled for device %x", 341 ret_intr_type, config_addr); 342 rtas_st(rets, 0, -1); /* Hardware error */ 343 return; 344 } 345 /* Correct the number if the guest asked for too many */ 346 if (req_num > max_irqs) { 347 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 348 req_num = max_irqs; 349 irq = 0; /* to avoid misleading trace */ 350 goto out; 351 } 352 353 /* Allocate MSIs */ 354 irq = xics_alloc_block(spapr->icp, 0, req_num, false, 355 ret_intr_type == RTAS_TYPE_MSI); 356 if (!irq) { 357 error_report("Cannot allocate MSIs for device %x", config_addr); 358 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 359 return; 360 } 361 362 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 363 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 364 irq, req_num); 365 366 /* Add MSI device to cache */ 367 msi = g_new(spapr_pci_msi, 1); 368 msi->first_irq = irq; 369 msi->num = req_num; 370 config_addr_key = g_new(int, 1); 371 *config_addr_key = config_addr; 372 g_hash_table_insert(phb->msi, config_addr_key, msi); 373 374 out: 375 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 376 rtas_st(rets, 1, req_num); 377 rtas_st(rets, 2, ++seq_num); 378 if (nret > 3) { 379 rtas_st(rets, 3, ret_intr_type); 380 } 381 382 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 383 } 384 385 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 386 sPAPRMachineState *spapr, 387 uint32_t token, 388 uint32_t nargs, 389 target_ulong args, 390 uint32_t nret, 391 target_ulong rets) 392 { 393 uint32_t config_addr = rtas_ld(args, 0); 394 uint64_t buid = rtas_ldq(args, 1); 395 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 396 sPAPRPHBState *phb = NULL; 397 PCIDevice *pdev = NULL; 398 spapr_pci_msi *msi; 399 400 /* Find sPAPRPHBState */ 401 phb = spapr_pci_find_phb(spapr, buid); 402 if (phb) { 403 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 404 } 405 if (!phb || !pdev) { 406 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 407 return; 408 } 409 410 /* Find device descriptor and start IRQ */ 411 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 412 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 413 trace_spapr_pci_msi("Failed to return vector", config_addr); 414 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 415 return; 416 } 417 intr_src_num = msi->first_irq + ioa_intr_num; 418 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 419 intr_src_num); 420 421 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 422 rtas_st(rets, 1, intr_src_num); 423 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 424 } 425 426 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 427 sPAPRMachineState *spapr, 428 uint32_t token, uint32_t nargs, 429 target_ulong args, uint32_t nret, 430 target_ulong rets) 431 { 432 sPAPRPHBState *sphb; 433 sPAPRPHBClass *spc; 434 PCIDevice *pdev; 435 uint32_t addr, option; 436 uint64_t buid; 437 int ret; 438 439 if ((nargs != 4) || (nret != 1)) { 440 goto param_error_exit; 441 } 442 443 buid = rtas_ldq(args, 1); 444 addr = rtas_ld(args, 0); 445 option = rtas_ld(args, 3); 446 447 sphb = spapr_pci_find_phb(spapr, buid); 448 if (!sphb) { 449 goto param_error_exit; 450 } 451 452 pdev = pci_find_device(PCI_HOST_BRIDGE(sphb)->bus, 453 (addr >> 16) & 0xFF, (addr >> 8) & 0xFF); 454 if (!pdev || !object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 455 goto param_error_exit; 456 } 457 458 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 459 if (!spc->eeh_set_option) { 460 goto param_error_exit; 461 } 462 463 ret = spc->eeh_set_option(sphb, addr, option); 464 rtas_st(rets, 0, ret); 465 return; 466 467 param_error_exit: 468 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 469 } 470 471 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 472 sPAPRMachineState *spapr, 473 uint32_t token, uint32_t nargs, 474 target_ulong args, uint32_t nret, 475 target_ulong rets) 476 { 477 sPAPRPHBState *sphb; 478 sPAPRPHBClass *spc; 479 PCIDevice *pdev; 480 uint32_t addr, option; 481 uint64_t buid; 482 483 if ((nargs != 4) || (nret != 2)) { 484 goto param_error_exit; 485 } 486 487 buid = rtas_ldq(args, 1); 488 sphb = spapr_pci_find_phb(spapr, buid); 489 if (!sphb) { 490 goto param_error_exit; 491 } 492 493 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 494 if (!spc->eeh_set_option) { 495 goto param_error_exit; 496 } 497 498 /* 499 * We always have PE address of form "00BB0001". "BB" 500 * represents the bus number of PE's primary bus. 501 */ 502 option = rtas_ld(args, 3); 503 switch (option) { 504 case RTAS_GET_PE_ADDR: 505 addr = rtas_ld(args, 0); 506 pdev = spapr_pci_find_dev(spapr, buid, addr); 507 if (!pdev) { 508 goto param_error_exit; 509 } 510 511 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); 512 break; 513 case RTAS_GET_PE_MODE: 514 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 515 break; 516 default: 517 goto param_error_exit; 518 } 519 520 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 521 return; 522 523 param_error_exit: 524 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 525 } 526 527 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 528 sPAPRMachineState *spapr, 529 uint32_t token, uint32_t nargs, 530 target_ulong args, uint32_t nret, 531 target_ulong rets) 532 { 533 sPAPRPHBState *sphb; 534 sPAPRPHBClass *spc; 535 uint64_t buid; 536 int state, ret; 537 538 if ((nargs != 3) || (nret != 4 && nret != 5)) { 539 goto param_error_exit; 540 } 541 542 buid = rtas_ldq(args, 1); 543 sphb = spapr_pci_find_phb(spapr, buid); 544 if (!sphb) { 545 goto param_error_exit; 546 } 547 548 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 549 if (!spc->eeh_get_state) { 550 goto param_error_exit; 551 } 552 553 ret = spc->eeh_get_state(sphb, &state); 554 rtas_st(rets, 0, ret); 555 if (ret != RTAS_OUT_SUCCESS) { 556 return; 557 } 558 559 rtas_st(rets, 1, state); 560 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 561 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 562 if (nret >= 5) { 563 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 564 } 565 return; 566 567 param_error_exit: 568 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 569 } 570 571 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 572 sPAPRMachineState *spapr, 573 uint32_t token, uint32_t nargs, 574 target_ulong args, uint32_t nret, 575 target_ulong rets) 576 { 577 sPAPRPHBState *sphb; 578 sPAPRPHBClass *spc; 579 uint32_t option; 580 uint64_t buid; 581 int ret; 582 583 if ((nargs != 4) || (nret != 1)) { 584 goto param_error_exit; 585 } 586 587 buid = rtas_ldq(args, 1); 588 option = rtas_ld(args, 3); 589 sphb = spapr_pci_find_phb(spapr, buid); 590 if (!sphb) { 591 goto param_error_exit; 592 } 593 594 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 595 if (!spc->eeh_reset) { 596 goto param_error_exit; 597 } 598 599 ret = spc->eeh_reset(sphb, option); 600 rtas_st(rets, 0, ret); 601 return; 602 603 param_error_exit: 604 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 605 } 606 607 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 608 sPAPRMachineState *spapr, 609 uint32_t token, uint32_t nargs, 610 target_ulong args, uint32_t nret, 611 target_ulong rets) 612 { 613 sPAPRPHBState *sphb; 614 sPAPRPHBClass *spc; 615 uint64_t buid; 616 int ret; 617 618 if ((nargs != 3) || (nret != 1)) { 619 goto param_error_exit; 620 } 621 622 buid = rtas_ldq(args, 1); 623 sphb = spapr_pci_find_phb(spapr, buid); 624 if (!sphb) { 625 goto param_error_exit; 626 } 627 628 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 629 if (!spc->eeh_configure) { 630 goto param_error_exit; 631 } 632 633 ret = spc->eeh_configure(sphb); 634 rtas_st(rets, 0, ret); 635 return; 636 637 param_error_exit: 638 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 639 } 640 641 /* To support it later */ 642 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 643 sPAPRMachineState *spapr, 644 uint32_t token, uint32_t nargs, 645 target_ulong args, uint32_t nret, 646 target_ulong rets) 647 { 648 sPAPRPHBState *sphb; 649 sPAPRPHBClass *spc; 650 int option; 651 uint64_t buid; 652 653 if ((nargs != 8) || (nret != 1)) { 654 goto param_error_exit; 655 } 656 657 buid = rtas_ldq(args, 1); 658 sphb = spapr_pci_find_phb(spapr, buid); 659 if (!sphb) { 660 goto param_error_exit; 661 } 662 663 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 664 if (!spc->eeh_set_option) { 665 goto param_error_exit; 666 } 667 668 option = rtas_ld(args, 7); 669 switch (option) { 670 case RTAS_SLOT_TEMP_ERR_LOG: 671 case RTAS_SLOT_PERM_ERR_LOG: 672 break; 673 default: 674 goto param_error_exit; 675 } 676 677 /* We don't have error log yet */ 678 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 679 return; 680 681 param_error_exit: 682 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 683 } 684 685 static int pci_spapr_swizzle(int slot, int pin) 686 { 687 return (slot + pin) % PCI_NUM_PINS; 688 } 689 690 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) 691 { 692 /* 693 * Here we need to convert pci_dev + irq_num to some unique value 694 * which is less than number of IRQs on the specific bus (4). We 695 * use standard PCI swizzling, that is (slot number + pin number) 696 * % 4. 697 */ 698 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); 699 } 700 701 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 702 { 703 /* 704 * Here we use the number returned by pci_spapr_map_irq to find a 705 * corresponding qemu_irq. 706 */ 707 sPAPRPHBState *phb = opaque; 708 709 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 710 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 711 } 712 713 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 714 { 715 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 716 PCIINTxRoute route; 717 718 route.mode = PCI_INTX_ENABLED; 719 route.irq = sphb->lsi_table[pin].irq; 720 721 return route; 722 } 723 724 /* 725 * MSI/MSIX memory region implementation. 726 * The handler handles both MSI and MSIX. 727 * For MSI-X, the vector number is encoded as a part of the address, 728 * data is set to 0. 729 * For MSI, the vector number is encoded in least bits in data. 730 */ 731 static void spapr_msi_write(void *opaque, hwaddr addr, 732 uint64_t data, unsigned size) 733 { 734 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 735 uint32_t irq = data; 736 737 trace_spapr_pci_msi_write(addr, data, irq); 738 739 qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); 740 } 741 742 static const MemoryRegionOps spapr_msi_ops = { 743 /* There is no .read as the read result is undefined by PCI spec */ 744 .read = NULL, 745 .write = spapr_msi_write, 746 .endianness = DEVICE_LITTLE_ENDIAN 747 }; 748 749 /* 750 * PHB PCI device 751 */ 752 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 753 { 754 sPAPRPHBState *phb = opaque; 755 756 return &phb->iommu_as; 757 } 758 759 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 760 { 761 char *path = NULL, *buf = NULL, *host = NULL; 762 763 /* Get the PCI VFIO host id */ 764 host = object_property_get_str(OBJECT(pdev), "host", NULL); 765 if (!host) { 766 goto err_out; 767 } 768 769 /* Construct the path of the file that will give us the DT location */ 770 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 771 g_free(host); 772 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 773 goto err_out; 774 } 775 g_free(path); 776 777 /* Construct and read from host device tree the loc-code */ 778 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 779 g_free(buf); 780 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 781 goto err_out; 782 } 783 return buf; 784 785 err_out: 786 g_free(path); 787 return NULL; 788 } 789 790 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 791 { 792 char *buf; 793 const char *devtype = "qemu"; 794 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 795 796 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 797 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 798 if (buf) { 799 return buf; 800 } 801 devtype = "vfio"; 802 } 803 /* 804 * For emulated devices and VFIO-failure case, make up 805 * the loc-code. 806 */ 807 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 808 devtype, pdev->name, sphb->index, busnr, 809 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 810 return buf; 811 } 812 813 /* Macros to operate with address in OF binding to PCI */ 814 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 815 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 816 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 817 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 818 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 819 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 820 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 821 #define b_fff(x) b_x((x), 8, 3) /* function number */ 822 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 823 824 /* for 'reg'/'assigned-addresses' OF properties */ 825 #define RESOURCE_CELLS_SIZE 2 826 #define RESOURCE_CELLS_ADDRESS 3 827 828 typedef struct ResourceFields { 829 uint32_t phys_hi; 830 uint32_t phys_mid; 831 uint32_t phys_lo; 832 uint32_t size_hi; 833 uint32_t size_lo; 834 } QEMU_PACKED ResourceFields; 835 836 typedef struct ResourceProps { 837 ResourceFields reg[8]; 838 ResourceFields assigned[7]; 839 uint32_t reg_len; 840 uint32_t assigned_len; 841 } ResourceProps; 842 843 /* fill in the 'reg'/'assigned-resources' OF properties for 844 * a PCI device. 'reg' describes resource requirements for a 845 * device's IO/MEM regions, 'assigned-addresses' describes the 846 * actual resource assignments. 847 * 848 * the properties are arrays of ('phys-addr', 'size') pairs describing 849 * the addressable regions of the PCI device, where 'phys-addr' is a 850 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 851 * (phys.hi, phys.mid, phys.lo), and 'size' is a 852 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 853 * 854 * phys.hi = 0xYYXXXXZZ, where: 855 * 0xYY = npt000ss 856 * ||| | 857 * ||| +-- space code 858 * ||| | 859 * ||| + 00 if configuration space 860 * ||| + 01 if IO region, 861 * ||| + 10 if 32-bit MEM region 862 * ||| + 11 if 64-bit MEM region 863 * ||| 864 * ||+------ for non-relocatable IO: 1 if aliased 865 * || for relocatable IO: 1 if below 64KB 866 * || for MEM: 1 if below 1MB 867 * |+------- 1 if region is prefetchable 868 * +-------- 1 if region is non-relocatable 869 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 870 * bits respectively 871 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 872 * to the region 873 * 874 * phys.mid and phys.lo correspond respectively to the hi/lo portions 875 * of the actual address of the region. 876 * 877 * how the phys-addr/size values are used differ slightly between 878 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 879 * an additional description for the config space region of the 880 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 881 * to describe the region as relocatable, with an address-mapping 882 * that corresponds directly to the PHB's address space for the 883 * resource. 'assigned-addresses' always has n=1 set with an absolute 884 * address assigned for the resource. in general, 'assigned-addresses' 885 * won't be populated, since addresses for PCI devices are generally 886 * unmapped initially and left to the guest to assign. 887 * 888 * note also that addresses defined in these properties are, at least 889 * for PAPR guests, relative to the PHBs IO/MEM windows, and 890 * correspond directly to the addresses in the BARs. 891 * 892 * in accordance with PCI Bus Binding to Open Firmware, 893 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 894 * Appendix C. 895 */ 896 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 897 { 898 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 899 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 900 b_ddddd(PCI_SLOT(d->devfn)) | 901 b_fff(PCI_FUNC(d->devfn))); 902 ResourceFields *reg, *assigned; 903 int i, reg_idx = 0, assigned_idx = 0; 904 905 /* config space region */ 906 reg = &rp->reg[reg_idx++]; 907 reg->phys_hi = cpu_to_be32(dev_id); 908 reg->phys_mid = 0; 909 reg->phys_lo = 0; 910 reg->size_hi = 0; 911 reg->size_lo = 0; 912 913 for (i = 0; i < PCI_NUM_REGIONS; i++) { 914 if (!d->io_regions[i].size) { 915 continue; 916 } 917 918 reg = &rp->reg[reg_idx++]; 919 920 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 921 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 922 reg->phys_hi |= cpu_to_be32(b_ss(1)); 923 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 924 reg->phys_hi |= cpu_to_be32(b_ss(3)); 925 } else { 926 reg->phys_hi |= cpu_to_be32(b_ss(2)); 927 } 928 reg->phys_mid = 0; 929 reg->phys_lo = 0; 930 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 931 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 932 933 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 934 continue; 935 } 936 937 assigned = &rp->assigned[assigned_idx++]; 938 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); 939 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 940 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 941 assigned->size_hi = reg->size_hi; 942 assigned->size_lo = reg->size_lo; 943 } 944 945 rp->reg_len = reg_idx * sizeof(ResourceFields); 946 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 947 } 948 949 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 950 PCIDevice *pdev); 951 952 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, 953 sPAPRPHBState *sphb) 954 { 955 ResourceProps rp; 956 bool is_bridge = false; 957 int pci_status, err; 958 char *buf = NULL; 959 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); 960 uint32_t max_msi, max_msix; 961 962 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == 963 PCI_HEADER_TYPE_BRIDGE) { 964 is_bridge = true; 965 } 966 967 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 968 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", 969 pci_default_read_config(dev, PCI_VENDOR_ID, 2))); 970 _FDT(fdt_setprop_cell(fdt, offset, "device-id", 971 pci_default_read_config(dev, PCI_DEVICE_ID, 2))); 972 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", 973 pci_default_read_config(dev, PCI_REVISION_ID, 1))); 974 _FDT(fdt_setprop_cell(fdt, offset, "class-code", 975 pci_default_read_config(dev, PCI_CLASS_PROG, 3))); 976 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { 977 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", 978 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); 979 } 980 981 if (!is_bridge) { 982 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", 983 pci_default_read_config(dev, PCI_MIN_GNT, 1))); 984 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", 985 pci_default_read_config(dev, PCI_MAX_LAT, 1))); 986 } 987 988 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { 989 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", 990 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); 991 } 992 993 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { 994 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 995 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); 996 } 997 998 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", 999 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); 1000 1001 /* the following fdt cells are masked off the pci status register */ 1002 pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1003 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1004 PCI_STATUS_DEVSEL_MASK & pci_status)); 1005 1006 if (pci_status & PCI_STATUS_FAST_BACK) { 1007 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1008 } 1009 if (pci_status & PCI_STATUS_66MHZ) { 1010 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1011 } 1012 if (pci_status & PCI_STATUS_UDF) { 1013 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1014 } 1015 1016 /* NOTE: this is normally generated by firmware via path/unit name, 1017 * but in our case we must set it manually since it does not get 1018 * processed by OF beforehand 1019 */ 1020 _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); 1021 buf = spapr_phb_get_loc_code(sphb, dev); 1022 if (!buf) { 1023 error_report("Failed setting the ibm,loc-code"); 1024 return -1; 1025 } 1026 1027 err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); 1028 g_free(buf); 1029 if (err < 0) { 1030 return err; 1031 } 1032 1033 if (drc_index) { 1034 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); 1035 } 1036 1037 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1038 RESOURCE_CELLS_ADDRESS)); 1039 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1040 RESOURCE_CELLS_SIZE)); 1041 1042 max_msi = msi_nr_vectors_allocated(dev); 1043 if (max_msi) { 1044 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1045 } 1046 max_msix = dev->msix_entries_nr; 1047 if (max_msix) { 1048 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1049 } 1050 1051 populate_resource_props(dev, &rp); 1052 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1053 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1054 (uint8_t *)rp.assigned, rp.assigned_len)); 1055 1056 return 0; 1057 } 1058 1059 /* create OF node for pci device and required OF DT properties */ 1060 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, 1061 void *fdt, int node_offset) 1062 { 1063 int offset, ret; 1064 int slot = PCI_SLOT(dev->devfn); 1065 int func = PCI_FUNC(dev->devfn); 1066 char nodename[FDT_NAME_MAX]; 1067 1068 if (func != 0) { 1069 snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); 1070 } else { 1071 snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); 1072 } 1073 offset = fdt_add_subnode(fdt, node_offset, nodename); 1074 ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); 1075 1076 g_assert(!ret); 1077 if (ret) { 1078 return 0; 1079 } 1080 return offset; 1081 } 1082 1083 static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, 1084 sPAPRPHBState *phb, 1085 PCIDevice *pdev, 1086 Error **errp) 1087 { 1088 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1089 DeviceState *dev = DEVICE(pdev); 1090 void *fdt = NULL; 1091 int fdt_start_offset = 0, fdt_size; 1092 1093 if (dev->hotplugged) { 1094 fdt = create_device_tree(&fdt_size); 1095 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); 1096 if (!fdt_start_offset) { 1097 error_setg(errp, "Failed to create pci child device tree node"); 1098 goto out; 1099 } 1100 } 1101 1102 drck->attach(drc, DEVICE(pdev), 1103 fdt, fdt_start_offset, !dev->hotplugged, errp); 1104 out: 1105 if (*errp) { 1106 g_free(fdt); 1107 } 1108 } 1109 1110 static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) 1111 { 1112 /* some version guests do not wait for completion of a device 1113 * cleanup (generally done asynchronously by the kernel) before 1114 * signaling to QEMU that the device is safe, but instead sleep 1115 * for some 'safe' period of time. unfortunately on a busy host 1116 * this sleep isn't guaranteed to be long enough, resulting in 1117 * bad things like IRQ lines being left asserted during final 1118 * device removal. to deal with this we call reset just prior 1119 * to finalizing the device, which will put the device back into 1120 * an 'idle' state, as the device cleanup code expects. 1121 */ 1122 pci_device_reset(PCI_DEVICE(dev)); 1123 object_unparent(OBJECT(dev)); 1124 } 1125 1126 static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, 1127 sPAPRPHBState *phb, 1128 PCIDevice *pdev, 1129 Error **errp) 1130 { 1131 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1132 1133 drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); 1134 } 1135 1136 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, 1137 PCIDevice *pdev) 1138 { 1139 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 1140 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, 1141 (phb->index << 16) | 1142 (busnr << 8) | 1143 pdev->devfn); 1144 } 1145 1146 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1147 PCIDevice *pdev) 1148 { 1149 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1150 sPAPRDRConnectorClass *drck; 1151 1152 if (!drc) { 1153 return 0; 1154 } 1155 1156 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1157 return drck->get_index(drc); 1158 } 1159 1160 static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, 1161 DeviceState *plugged_dev, Error **errp) 1162 { 1163 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1164 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1165 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1166 Error *local_err = NULL; 1167 1168 /* if DR is disabled we don't need to do anything in the case of 1169 * hotplug or coldplug callbacks 1170 */ 1171 if (!phb->dr_enabled) { 1172 /* if this is a hotplug operation initiated by the user 1173 * we need to let them know it's not enabled 1174 */ 1175 if (plugged_dev->hotplugged) { 1176 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1177 object_get_typename(OBJECT(phb))); 1178 } 1179 return; 1180 } 1181 1182 g_assert(drc); 1183 1184 spapr_phb_add_pci_device(drc, phb, pdev, &local_err); 1185 if (local_err) { 1186 error_propagate(errp, local_err); 1187 return; 1188 } 1189 if (plugged_dev->hotplugged) { 1190 spapr_hotplug_req_add_by_index(drc); 1191 } 1192 } 1193 1194 static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, 1195 DeviceState *plugged_dev, Error **errp) 1196 { 1197 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1198 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1199 sPAPRDRConnectorClass *drck; 1200 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1201 Error *local_err = NULL; 1202 1203 if (!phb->dr_enabled) { 1204 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1205 object_get_typename(OBJECT(phb))); 1206 return; 1207 } 1208 1209 g_assert(drc); 1210 1211 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1212 if (!drck->release_pending(drc)) { 1213 spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); 1214 if (local_err) { 1215 error_propagate(errp, local_err); 1216 return; 1217 } 1218 spapr_hotplug_req_remove_by_index(drc); 1219 } 1220 } 1221 1222 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1223 { 1224 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1225 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1226 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1227 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1228 sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); 1229 char *namebuf; 1230 int i; 1231 PCIBus *bus; 1232 uint64_t msi_window_size = 4096; 1233 1234 if (sphb->index != (uint32_t)-1) { 1235 hwaddr windows_base; 1236 1237 if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) 1238 || (sphb->mem_win_addr != (hwaddr)-1) 1239 || (sphb->io_win_addr != (hwaddr)-1)) { 1240 error_setg(errp, "Either \"index\" or other parameters must" 1241 " be specified for PAPR PHB, not both"); 1242 return; 1243 } 1244 1245 if (sphb->index > SPAPR_PCI_MAX_INDEX) { 1246 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 1247 SPAPR_PCI_MAX_INDEX); 1248 return; 1249 } 1250 1251 sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; 1252 sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); 1253 1254 windows_base = SPAPR_PCI_WINDOW_BASE 1255 + sphb->index * SPAPR_PCI_WINDOW_SPACING; 1256 sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; 1257 sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; 1258 } 1259 1260 if (sphb->buid == (uint64_t)-1) { 1261 error_setg(errp, "BUID not specified for PHB"); 1262 return; 1263 } 1264 1265 if (sphb->dma_liobn == (uint32_t)-1) { 1266 error_setg(errp, "LIOBN not specified for PHB"); 1267 return; 1268 } 1269 1270 if (sphb->mem_win_addr == (hwaddr)-1) { 1271 error_setg(errp, "Memory window address not specified for PHB"); 1272 return; 1273 } 1274 1275 if (sphb->io_win_addr == (hwaddr)-1) { 1276 error_setg(errp, "IO window address not specified for PHB"); 1277 return; 1278 } 1279 1280 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1281 error_setg(errp, "PCI host bridges must have unique BUIDs"); 1282 return; 1283 } 1284 1285 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1286 1287 namebuf = alloca(strlen(sphb->dtbusname) + 32); 1288 1289 /* Initialize memory regions */ 1290 sprintf(namebuf, "%s.mmio", sphb->dtbusname); 1291 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1292 1293 sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); 1294 memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), 1295 namebuf, &sphb->memspace, 1296 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1297 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1298 &sphb->memwindow); 1299 1300 /* Initialize IO regions */ 1301 sprintf(namebuf, "%s.io", sphb->dtbusname); 1302 memory_region_init(&sphb->iospace, OBJECT(sphb), 1303 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1304 1305 sprintf(namebuf, "%s.io-alias", sphb->dtbusname); 1306 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1307 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1308 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1309 &sphb->iowindow); 1310 1311 bus = pci_register_bus(dev, NULL, 1312 pci_spapr_set_irq, pci_spapr_map_irq, sphb, 1313 &sphb->memspace, &sphb->iospace, 1314 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); 1315 phb->bus = bus; 1316 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); 1317 1318 /* 1319 * Initialize PHB address space. 1320 * By default there will be at least one subregion for default 1321 * 32bit DMA window. 1322 * Later the guest might want to create another DMA window 1323 * which will become another memory subregion. 1324 */ 1325 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); 1326 1327 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1328 namebuf, UINT64_MAX); 1329 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1330 sphb->dtbusname); 1331 1332 /* 1333 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1334 * we need to allocate some memory to catch those writes coming 1335 * from msi_notify()/msix_notify(). 1336 * As MSIMessage:addr is going to be the same and MSIMessage:data 1337 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1338 * be used. 1339 * 1340 * For KVM we want to ensure that this memory is a full page so that 1341 * our memory slot is of page size granularity. 1342 */ 1343 #ifdef CONFIG_KVM 1344 if (kvm_enabled()) { 1345 msi_window_size = getpagesize(); 1346 } 1347 #endif 1348 1349 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, 1350 "msi", msi_window_size); 1351 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1352 &sphb->msiwindow); 1353 1354 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1355 1356 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1357 1358 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1359 1360 /* Initialize the LSI table */ 1361 for (i = 0; i < PCI_NUM_PINS; i++) { 1362 uint32_t irq; 1363 1364 irq = xics_alloc_block(spapr->icp, 0, 1, true, false); 1365 if (!irq) { 1366 error_setg(errp, "spapr_allocate_lsi failed"); 1367 return; 1368 } 1369 1370 sphb->lsi_table[i].irq = irq; 1371 } 1372 1373 /* allocate connectors for child PCI devices */ 1374 if (sphb->dr_enabled) { 1375 for (i = 0; i < PCI_SLOT_MAX * 8; i++) { 1376 spapr_dr_connector_new(OBJECT(phb), 1377 SPAPR_DR_CONNECTOR_TYPE_PCI, 1378 (sphb->index << 16) | i); 1379 } 1380 } 1381 1382 if (!info->finish_realize) { 1383 error_setg(errp, "finish_realize not defined"); 1384 return; 1385 } 1386 1387 info->finish_realize(sphb, errp); 1388 1389 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 1390 } 1391 1392 static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) 1393 { 1394 sPAPRTCETable *tcet; 1395 uint32_t nb_table; 1396 1397 nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; 1398 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, 1399 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); 1400 if (!tcet) { 1401 error_setg(errp, "Unable to create TCE table for %s", 1402 sphb->dtbusname); 1403 return ; 1404 } 1405 1406 /* Register default 32bit DMA window */ 1407 memory_region_add_subregion(&sphb->iommu_root, 0, 1408 spapr_tce_get_iommu(tcet)); 1409 } 1410 1411 static int spapr_phb_children_reset(Object *child, void *opaque) 1412 { 1413 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 1414 1415 if (dev) { 1416 device_reset(dev); 1417 } 1418 1419 return 0; 1420 } 1421 1422 static void spapr_phb_reset(DeviceState *qdev) 1423 { 1424 /* Reset the IOMMU state */ 1425 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 1426 } 1427 1428 static Property spapr_phb_properties[] = { 1429 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), 1430 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), 1431 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), 1432 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), 1433 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, 1434 SPAPR_PCI_MMIO_WIN_SIZE), 1435 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), 1436 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, 1437 SPAPR_PCI_IO_WIN_SIZE), 1438 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, 1439 true), 1440 DEFINE_PROP_END_OF_LIST(), 1441 }; 1442 1443 static const VMStateDescription vmstate_spapr_pci_lsi = { 1444 .name = "spapr_pci/lsi", 1445 .version_id = 1, 1446 .minimum_version_id = 1, 1447 .fields = (VMStateField[]) { 1448 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), 1449 1450 VMSTATE_END_OF_LIST() 1451 }, 1452 }; 1453 1454 static const VMStateDescription vmstate_spapr_pci_msi = { 1455 .name = "spapr_pci/msi", 1456 .version_id = 1, 1457 .minimum_version_id = 1, 1458 .fields = (VMStateField []) { 1459 VMSTATE_UINT32(key, spapr_pci_msi_mig), 1460 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 1461 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 1462 VMSTATE_END_OF_LIST() 1463 }, 1464 }; 1465 1466 static void spapr_pci_pre_save(void *opaque) 1467 { 1468 sPAPRPHBState *sphb = opaque; 1469 GHashTableIter iter; 1470 gpointer key, value; 1471 int i; 1472 1473 g_free(sphb->msi_devs); 1474 sphb->msi_devs = NULL; 1475 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 1476 if (!sphb->msi_devs_num) { 1477 return; 1478 } 1479 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); 1480 1481 g_hash_table_iter_init(&iter, sphb->msi); 1482 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 1483 sphb->msi_devs[i].key = *(uint32_t *) key; 1484 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 1485 } 1486 } 1487 1488 static int spapr_pci_post_load(void *opaque, int version_id) 1489 { 1490 sPAPRPHBState *sphb = opaque; 1491 gpointer key, value; 1492 int i; 1493 1494 for (i = 0; i < sphb->msi_devs_num; ++i) { 1495 key = g_memdup(&sphb->msi_devs[i].key, 1496 sizeof(sphb->msi_devs[i].key)); 1497 value = g_memdup(&sphb->msi_devs[i].value, 1498 sizeof(sphb->msi_devs[i].value)); 1499 g_hash_table_insert(sphb->msi, key, value); 1500 } 1501 g_free(sphb->msi_devs); 1502 sphb->msi_devs = NULL; 1503 sphb->msi_devs_num = 0; 1504 1505 return 0; 1506 } 1507 1508 static const VMStateDescription vmstate_spapr_pci = { 1509 .name = "spapr_pci", 1510 .version_id = 2, 1511 .minimum_version_id = 2, 1512 .pre_save = spapr_pci_pre_save, 1513 .post_load = spapr_pci_post_load, 1514 .fields = (VMStateField[]) { 1515 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), 1516 VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), 1517 VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), 1518 VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), 1519 VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), 1520 VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), 1521 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, 1522 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 1523 VMSTATE_INT32(msi_devs_num, sPAPRPHBState), 1524 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, 1525 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 1526 VMSTATE_END_OF_LIST() 1527 }, 1528 }; 1529 1530 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 1531 PCIBus *rootbus) 1532 { 1533 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 1534 1535 return sphb->dtbusname; 1536 } 1537 1538 static void spapr_phb_class_init(ObjectClass *klass, void *data) 1539 { 1540 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 1541 DeviceClass *dc = DEVICE_CLASS(klass); 1542 sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); 1543 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 1544 1545 hc->root_bus_path = spapr_phb_root_bus_path; 1546 dc->realize = spapr_phb_realize; 1547 dc->props = spapr_phb_properties; 1548 dc->reset = spapr_phb_reset; 1549 dc->vmsd = &vmstate_spapr_pci; 1550 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1551 dc->cannot_instantiate_with_device_add_yet = false; 1552 spc->finish_realize = spapr_phb_finish_realize; 1553 hp->plug = spapr_phb_hot_plug_child; 1554 hp->unplug = spapr_phb_hot_unplug_child; 1555 } 1556 1557 static const TypeInfo spapr_phb_info = { 1558 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 1559 .parent = TYPE_PCI_HOST_BRIDGE, 1560 .instance_size = sizeof(sPAPRPHBState), 1561 .class_init = spapr_phb_class_init, 1562 .class_size = sizeof(sPAPRPHBClass), 1563 .interfaces = (InterfaceInfo[]) { 1564 { TYPE_HOTPLUG_HANDLER }, 1565 { } 1566 } 1567 }; 1568 1569 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) 1570 { 1571 DeviceState *dev; 1572 1573 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 1574 qdev_prop_set_uint32(dev, "index", index); 1575 qdev_init_nofail(dev); 1576 1577 return PCI_HOST_BRIDGE(dev); 1578 } 1579 1580 typedef struct sPAPRFDT { 1581 void *fdt; 1582 int node_off; 1583 sPAPRPHBState *sphb; 1584 } sPAPRFDT; 1585 1586 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, 1587 void *opaque) 1588 { 1589 PCIBus *sec_bus; 1590 sPAPRFDT *p = opaque; 1591 int offset; 1592 sPAPRFDT s_fdt; 1593 1594 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); 1595 if (!offset) { 1596 error_report("Failed to create pci child device tree node"); 1597 return; 1598 } 1599 1600 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1601 PCI_HEADER_TYPE_BRIDGE)) { 1602 return; 1603 } 1604 1605 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1606 if (!sec_bus) { 1607 return; 1608 } 1609 1610 s_fdt.fdt = p->fdt; 1611 s_fdt.node_off = offset; 1612 s_fdt.sphb = p->sphb; 1613 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1614 spapr_populate_pci_devices_dt, 1615 &s_fdt); 1616 } 1617 1618 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 1619 void *opaque) 1620 { 1621 unsigned int *bus_no = opaque; 1622 unsigned int primary = *bus_no; 1623 unsigned int subordinate = 0xff; 1624 PCIBus *sec_bus = NULL; 1625 1626 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1627 PCI_HEADER_TYPE_BRIDGE)) { 1628 return; 1629 } 1630 1631 (*bus_no)++; 1632 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 1633 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 1634 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1635 1636 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1637 if (!sec_bus) { 1638 return; 1639 } 1640 1641 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 1642 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1643 spapr_phb_pci_enumerate_bridge, bus_no); 1644 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1645 } 1646 1647 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) 1648 { 1649 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1650 unsigned int bus_no = 0; 1651 1652 pci_for_each_device(bus, pci_bus_num(bus), 1653 spapr_phb_pci_enumerate_bridge, 1654 &bus_no); 1655 1656 } 1657 1658 int spapr_populate_pci_dt(sPAPRPHBState *phb, 1659 uint32_t xics_phandle, 1660 void *fdt) 1661 { 1662 int bus_off, i, j, ret; 1663 char nodename[FDT_NAME_MAX]; 1664 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 1665 const uint64_t mmiosize = memory_region_size(&phb->memwindow); 1666 const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; 1667 const uint64_t w32size = MIN(w32max, mmiosize); 1668 const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; 1669 struct { 1670 uint32_t hi; 1671 uint64_t child; 1672 uint64_t parent; 1673 uint64_t size; 1674 } QEMU_PACKED ranges[] = { 1675 { 1676 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 1677 cpu_to_be64(phb->io_win_addr), 1678 cpu_to_be64(memory_region_size(&phb->iospace)), 1679 }, 1680 { 1681 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 1682 cpu_to_be64(phb->mem_win_addr), 1683 cpu_to_be64(w32size), 1684 }, 1685 { 1686 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), 1687 cpu_to_be64(phb->mem_win_addr + w32size), 1688 cpu_to_be64(w64size) 1689 }, 1690 }; 1691 const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); 1692 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 1693 uint32_t interrupt_map_mask[] = { 1694 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 1695 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 1696 sPAPRTCETable *tcet; 1697 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1698 sPAPRFDT s_fdt; 1699 1700 /* Start populating the FDT */ 1701 snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); 1702 bus_off = fdt_add_subnode(fdt, 0, nodename); 1703 if (bus_off < 0) { 1704 return bus_off; 1705 } 1706 1707 /* Write PHB properties */ 1708 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 1709 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 1710 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); 1711 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); 1712 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 1713 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 1714 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 1715 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 1716 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 1717 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 1718 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); 1719 1720 /* Build the interrupt-map, this must matches what is done 1721 * in pci_spapr_map_irq 1722 */ 1723 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 1724 &interrupt_map_mask, sizeof(interrupt_map_mask))); 1725 for (i = 0; i < PCI_SLOT_MAX; i++) { 1726 for (j = 0; j < PCI_NUM_PINS; j++) { 1727 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 1728 int lsi_num = pci_spapr_swizzle(i, j); 1729 1730 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 1731 irqmap[1] = 0; 1732 irqmap[2] = 0; 1733 irqmap[3] = cpu_to_be32(j+1); 1734 irqmap[4] = cpu_to_be32(xics_phandle); 1735 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); 1736 irqmap[6] = cpu_to_be32(0x8); 1737 } 1738 } 1739 /* Write interrupt map */ 1740 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 1741 sizeof(interrupt_map))); 1742 1743 tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); 1744 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 1745 tcet->liobn, tcet->bus_offset, 1746 tcet->nb_table << tcet->page_shift); 1747 1748 /* Walk the bridges and program the bus numbers*/ 1749 spapr_phb_pci_enumerate(phb); 1750 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 1751 1752 /* Populate tree nodes with PCI devices attached */ 1753 s_fdt.fdt = fdt; 1754 s_fdt.node_off = bus_off; 1755 s_fdt.sphb = phb; 1756 pci_for_each_device(bus, pci_bus_num(bus), 1757 spapr_populate_pci_devices_dt, 1758 &s_fdt); 1759 1760 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), 1761 SPAPR_DR_CONNECTOR_TYPE_PCI); 1762 if (ret) { 1763 return ret; 1764 } 1765 1766 return 0; 1767 } 1768 1769 void spapr_pci_rtas_init(void) 1770 { 1771 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 1772 rtas_read_pci_config); 1773 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 1774 rtas_write_pci_config); 1775 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 1776 rtas_ibm_read_pci_config); 1777 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 1778 rtas_ibm_write_pci_config); 1779 if (msi_supported) { 1780 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 1781 "ibm,query-interrupt-source-number", 1782 rtas_ibm_query_interrupt_source_number); 1783 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 1784 rtas_ibm_change_msi); 1785 } 1786 1787 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 1788 "ibm,set-eeh-option", 1789 rtas_ibm_set_eeh_option); 1790 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 1791 "ibm,get-config-addr-info2", 1792 rtas_ibm_get_config_addr_info2); 1793 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 1794 "ibm,read-slot-reset-state2", 1795 rtas_ibm_read_slot_reset_state2); 1796 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 1797 "ibm,set-slot-reset", 1798 rtas_ibm_set_slot_reset); 1799 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 1800 "ibm,configure-pe", 1801 rtas_ibm_configure_pe); 1802 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 1803 "ibm,slot-error-detail", 1804 rtas_ibm_slot_error_detail); 1805 } 1806 1807 static void spapr_pci_register_types(void) 1808 { 1809 type_register_static(&spapr_phb_info); 1810 } 1811 1812 type_init(spapr_pci_register_types) 1813 1814 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 1815 { 1816 bool be = *(bool *)opaque; 1817 1818 if (object_dynamic_cast(OBJECT(dev), "VGA") 1819 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 1820 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 1821 &error_abort); 1822 } 1823 return 0; 1824 } 1825 1826 void spapr_pci_switch_vga(bool big_endian) 1827 { 1828 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1829 sPAPRPHBState *sphb; 1830 1831 /* 1832 * For backward compatibility with existing guests, we switch 1833 * the endianness of the VGA controller when changing the guest 1834 * interrupt mode 1835 */ 1836 QLIST_FOREACH(sphb, &spapr->phbs, list) { 1837 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 1838 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 1839 &big_endian); 1840 } 1841 } 1842