1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "hw/hw.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci/msi.h" 28 #include "hw/pci/msix.h" 29 #include "hw/pci/pci_host.h" 30 #include "hw/ppc/spapr.h" 31 #include "hw/pci-host/spapr.h" 32 #include "exec/address-spaces.h" 33 #include <libfdt.h> 34 #include "trace.h" 35 36 #include "hw/pci/pci_bus.h" 37 38 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 39 #define RTAS_QUERY_FN 0 40 #define RTAS_CHANGE_FN 1 41 #define RTAS_RESET_FN 2 42 #define RTAS_CHANGE_MSI_FN 3 43 #define RTAS_CHANGE_MSIX_FN 4 44 45 /* Interrupt types to return on RTAS_CHANGE_* */ 46 #define RTAS_TYPE_MSI 1 47 #define RTAS_TYPE_MSIX 2 48 49 static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid) 50 { 51 sPAPRPHBState *sphb; 52 53 QLIST_FOREACH(sphb, &spapr->phbs, list) { 54 if (sphb->buid != buid) { 55 continue; 56 } 57 return sphb; 58 } 59 60 return NULL; 61 } 62 63 static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid, 64 uint32_t config_addr) 65 { 66 sPAPRPHBState *sphb = find_phb(spapr, buid); 67 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 68 int bus_num = (config_addr >> 16) & 0xFF; 69 int devfn = (config_addr >> 8) & 0xFF; 70 71 if (!phb) { 72 return NULL; 73 } 74 75 return pci_find_device(phb->bus, bus_num, devfn); 76 } 77 78 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 79 { 80 /* This handles the encoding of extended config space addresses */ 81 return ((arg >> 20) & 0xf00) | (arg & 0xff); 82 } 83 84 static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, 85 uint32_t addr, uint32_t size, 86 target_ulong rets) 87 { 88 PCIDevice *pci_dev; 89 uint32_t val; 90 91 if ((size != 1) && (size != 2) && (size != 4)) { 92 /* access must be 1, 2 or 4 bytes */ 93 rtas_st(rets, 0, -1); 94 return; 95 } 96 97 pci_dev = find_dev(spapr, buid, addr); 98 addr = rtas_pci_cfgaddr(addr); 99 100 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 101 /* Access must be to a valid device, within bounds and 102 * naturally aligned */ 103 rtas_st(rets, 0, -1); 104 return; 105 } 106 107 val = pci_host_config_read_common(pci_dev, addr, 108 pci_config_size(pci_dev), size); 109 110 rtas_st(rets, 0, 0); 111 rtas_st(rets, 1, val); 112 } 113 114 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, 115 uint32_t token, uint32_t nargs, 116 target_ulong args, 117 uint32_t nret, target_ulong rets) 118 { 119 uint64_t buid; 120 uint32_t size, addr; 121 122 if ((nargs != 4) || (nret != 2)) { 123 rtas_st(rets, 0, -1); 124 return; 125 } 126 127 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 128 size = rtas_ld(args, 3); 129 addr = rtas_ld(args, 0); 130 131 finish_read_pci_config(spapr, buid, addr, size, rets); 132 } 133 134 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, 135 uint32_t token, uint32_t nargs, 136 target_ulong args, 137 uint32_t nret, target_ulong rets) 138 { 139 uint32_t size, addr; 140 141 if ((nargs != 2) || (nret != 2)) { 142 rtas_st(rets, 0, -1); 143 return; 144 } 145 146 size = rtas_ld(args, 1); 147 addr = rtas_ld(args, 0); 148 149 finish_read_pci_config(spapr, 0, addr, size, rets); 150 } 151 152 static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, 153 uint32_t addr, uint32_t size, 154 uint32_t val, target_ulong rets) 155 { 156 PCIDevice *pci_dev; 157 158 if ((size != 1) && (size != 2) && (size != 4)) { 159 /* access must be 1, 2 or 4 bytes */ 160 rtas_st(rets, 0, -1); 161 return; 162 } 163 164 pci_dev = find_dev(spapr, buid, addr); 165 addr = rtas_pci_cfgaddr(addr); 166 167 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 168 /* Access must be to a valid device, within bounds and 169 * naturally aligned */ 170 rtas_st(rets, 0, -1); 171 return; 172 } 173 174 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 175 val, size); 176 177 rtas_st(rets, 0, 0); 178 } 179 180 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, 181 uint32_t token, uint32_t nargs, 182 target_ulong args, 183 uint32_t nret, target_ulong rets) 184 { 185 uint64_t buid; 186 uint32_t val, size, addr; 187 188 if ((nargs != 5) || (nret != 1)) { 189 rtas_st(rets, 0, -1); 190 return; 191 } 192 193 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 194 val = rtas_ld(args, 4); 195 size = rtas_ld(args, 3); 196 addr = rtas_ld(args, 0); 197 198 finish_write_pci_config(spapr, buid, addr, size, val, rets); 199 } 200 201 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, 202 uint32_t token, uint32_t nargs, 203 target_ulong args, 204 uint32_t nret, target_ulong rets) 205 { 206 uint32_t val, size, addr; 207 208 if ((nargs != 3) || (nret != 1)) { 209 rtas_st(rets, 0, -1); 210 return; 211 } 212 213 214 val = rtas_ld(args, 2); 215 size = rtas_ld(args, 1); 216 addr = rtas_ld(args, 0); 217 218 finish_write_pci_config(spapr, 0, addr, size, val, rets); 219 } 220 221 /* 222 * Find an entry with config_addr or returns the empty one if not found AND 223 * alloc_new is set. 224 * At the moment the msi_table entries are never released so there is 225 * no point to look till the end of the list if we need to find the free entry. 226 */ 227 static int spapr_msicfg_find(sPAPRPHBState *phb, uint32_t config_addr, 228 bool alloc_new) 229 { 230 int i; 231 232 for (i = 0; i < SPAPR_MSIX_MAX_DEVS; ++i) { 233 if (!phb->msi_table[i].nvec) { 234 break; 235 } 236 if (phb->msi_table[i].config_addr == config_addr) { 237 return i; 238 } 239 } 240 if ((i < SPAPR_MSIX_MAX_DEVS) && alloc_new) { 241 trace_spapr_pci_msi("Allocating new MSI config", i, config_addr); 242 return i; 243 } 244 245 return -1; 246 } 247 248 /* 249 * Set MSI/MSIX message data. 250 * This is required for msi_notify()/msix_notify() which 251 * will write at the addresses via spapr_msi_write(). 252 */ 253 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, 254 bool msix, unsigned req_num) 255 { 256 unsigned i; 257 MSIMessage msg = { .address = addr, .data = 0 }; 258 259 if (!msix) { 260 msi_set_message(pdev, msg); 261 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 262 return; 263 } 264 265 for (i = 0; i < req_num; ++i) { 266 msg.address = addr | (i << 2); 267 msix_set_message(pdev, i, msg); 268 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 269 } 270 } 271 272 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, 273 uint32_t token, uint32_t nargs, 274 target_ulong args, uint32_t nret, 275 target_ulong rets) 276 { 277 uint32_t config_addr = rtas_ld(args, 0); 278 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 279 unsigned int func = rtas_ld(args, 3); 280 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 281 unsigned int seq_num = rtas_ld(args, 5); 282 unsigned int ret_intr_type; 283 int ndev, irq; 284 sPAPRPHBState *phb = NULL; 285 PCIDevice *pdev = NULL; 286 287 switch (func) { 288 case RTAS_CHANGE_MSI_FN: 289 case RTAS_CHANGE_FN: 290 ret_intr_type = RTAS_TYPE_MSI; 291 break; 292 case RTAS_CHANGE_MSIX_FN: 293 ret_intr_type = RTAS_TYPE_MSIX; 294 break; 295 default: 296 fprintf(stderr, "rtas_ibm_change_msi(%u) is not implemented\n", func); 297 rtas_st(rets, 0, -3); /* Parameter error */ 298 return; 299 } 300 301 /* Fins sPAPRPHBState */ 302 phb = find_phb(spapr, buid); 303 if (phb) { 304 pdev = find_dev(spapr, buid, config_addr); 305 } 306 if (!phb || !pdev) { 307 rtas_st(rets, 0, -3); /* Parameter error */ 308 return; 309 } 310 311 /* Releasing MSIs */ 312 if (!req_num) { 313 ndev = spapr_msicfg_find(phb, config_addr, false); 314 if (ndev < 0) { 315 trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr); 316 rtas_st(rets, 0, -1); /* Hardware error */ 317 return; 318 } 319 trace_spapr_pci_msi("Released MSIs", ndev, config_addr); 320 rtas_st(rets, 0, 0); 321 rtas_st(rets, 1, 0); 322 return; 323 } 324 325 /* Enabling MSI */ 326 327 /* Find a device number in the map to add or reuse the existing one */ 328 ndev = spapr_msicfg_find(phb, config_addr, true); 329 if (ndev >= SPAPR_MSIX_MAX_DEVS || ndev < 0) { 330 fprintf(stderr, "No free entry for a new MSI device\n"); 331 rtas_st(rets, 0, -1); /* Hardware error */ 332 return; 333 } 334 trace_spapr_pci_msi("Configuring MSI", ndev, config_addr); 335 336 /* Check if there is an old config and MSI number has not changed */ 337 if (phb->msi_table[ndev].nvec && (req_num != phb->msi_table[ndev].nvec)) { 338 /* Unexpected behaviour */ 339 fprintf(stderr, "Cannot reuse MSI config for device#%d", ndev); 340 rtas_st(rets, 0, -1); /* Hardware error */ 341 return; 342 } 343 344 /* There is no cached config, allocate MSIs */ 345 if (!phb->msi_table[ndev].nvec) { 346 irq = spapr_allocate_irq_block(req_num, false); 347 if (irq < 0) { 348 fprintf(stderr, "Cannot allocate MSIs for device#%d", ndev); 349 rtas_st(rets, 0, -1); /* Hardware error */ 350 return; 351 } 352 phb->msi_table[ndev].irq = irq; 353 phb->msi_table[ndev].nvec = req_num; 354 phb->msi_table[ndev].config_addr = config_addr; 355 } 356 357 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 358 spapr_msi_setmsg(pdev, phb->msi_win_addr | (ndev << 16), 359 ret_intr_type == RTAS_TYPE_MSIX, req_num); 360 361 rtas_st(rets, 0, 0); 362 rtas_st(rets, 1, req_num); 363 rtas_st(rets, 2, ++seq_num); 364 rtas_st(rets, 3, ret_intr_type); 365 366 trace_spapr_pci_rtas_ibm_change_msi(func, req_num); 367 } 368 369 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 370 sPAPREnvironment *spapr, 371 uint32_t token, 372 uint32_t nargs, 373 target_ulong args, 374 uint32_t nret, 375 target_ulong rets) 376 { 377 uint32_t config_addr = rtas_ld(args, 0); 378 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 379 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 380 int ndev; 381 sPAPRPHBState *phb = NULL; 382 383 /* Fins sPAPRPHBState */ 384 phb = find_phb(spapr, buid); 385 if (!phb) { 386 rtas_st(rets, 0, -3); /* Parameter error */ 387 return; 388 } 389 390 /* Find device descriptor and start IRQ */ 391 ndev = spapr_msicfg_find(phb, config_addr, false); 392 if (ndev < 0) { 393 trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr); 394 rtas_st(rets, 0, -1); /* Hardware error */ 395 return; 396 } 397 398 intr_src_num = phb->msi_table[ndev].irq + ioa_intr_num; 399 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 400 intr_src_num); 401 402 rtas_st(rets, 0, 0); 403 rtas_st(rets, 1, intr_src_num); 404 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 405 } 406 407 static int pci_spapr_swizzle(int slot, int pin) 408 { 409 return (slot + pin) % PCI_NUM_PINS; 410 } 411 412 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) 413 { 414 /* 415 * Here we need to convert pci_dev + irq_num to some unique value 416 * which is less than number of IRQs on the specific bus (4). We 417 * use standard PCI swizzling, that is (slot number + pin number) 418 * % 4. 419 */ 420 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); 421 } 422 423 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 424 { 425 /* 426 * Here we use the number returned by pci_spapr_map_irq to find a 427 * corresponding qemu_irq. 428 */ 429 sPAPRPHBState *phb = opaque; 430 431 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 432 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 433 } 434 435 /* 436 * MSI/MSIX memory region implementation. 437 * The handler handles both MSI and MSIX. 438 * For MSI-X, the vector number is encoded as a part of the address, 439 * data is set to 0. 440 * For MSI, the vector number is encoded in least bits in data. 441 */ 442 static void spapr_msi_write(void *opaque, hwaddr addr, 443 uint64_t data, unsigned size) 444 { 445 sPAPRPHBState *phb = opaque; 446 int ndev = addr >> 16; 447 int vec = ((addr & 0xFFFF) >> 2) | data; 448 uint32_t irq = phb->msi_table[ndev].irq + vec; 449 450 trace_spapr_pci_msi_write(addr, data, irq); 451 452 qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); 453 } 454 455 static const MemoryRegionOps spapr_msi_ops = { 456 /* There is no .read as the read result is undefined by PCI spec */ 457 .read = NULL, 458 .write = spapr_msi_write, 459 .endianness = DEVICE_LITTLE_ENDIAN 460 }; 461 462 /* 463 * PHB PCI device 464 */ 465 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 466 { 467 sPAPRPHBState *phb = opaque; 468 469 return &phb->iommu_as; 470 } 471 472 static int spapr_phb_init(SysBusDevice *s) 473 { 474 DeviceState *dev = DEVICE(s); 475 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 476 PCIHostState *phb = PCI_HOST_BRIDGE(s); 477 const char *busname; 478 char *namebuf; 479 int i; 480 PCIBus *bus; 481 482 if (sphb->index != -1) { 483 hwaddr windows_base; 484 485 if ((sphb->buid != -1) || (sphb->dma_liobn != -1) 486 || (sphb->mem_win_addr != -1) 487 || (sphb->io_win_addr != -1) 488 || (sphb->msi_win_addr != -1)) { 489 fprintf(stderr, "Either \"index\" or other parameters must" 490 " be specified for PAPR PHB, not both\n"); 491 return -1; 492 } 493 494 sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; 495 sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN + sphb->index; 496 497 windows_base = SPAPR_PCI_WINDOW_BASE 498 + sphb->index * SPAPR_PCI_WINDOW_SPACING; 499 sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; 500 sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; 501 sphb->msi_win_addr = windows_base + SPAPR_PCI_MSI_WIN_OFF; 502 } 503 504 if (sphb->buid == -1) { 505 fprintf(stderr, "BUID not specified for PHB\n"); 506 return -1; 507 } 508 509 if (sphb->dma_liobn == -1) { 510 fprintf(stderr, "LIOBN not specified for PHB\n"); 511 return -1; 512 } 513 514 if (sphb->mem_win_addr == -1) { 515 fprintf(stderr, "Memory window address not specified for PHB\n"); 516 return -1; 517 } 518 519 if (sphb->io_win_addr == -1) { 520 fprintf(stderr, "IO window address not specified for PHB\n"); 521 return -1; 522 } 523 524 if (sphb->msi_win_addr == -1) { 525 fprintf(stderr, "MSI window address not specified for PHB\n"); 526 return -1; 527 } 528 529 if (find_phb(spapr, sphb->buid)) { 530 fprintf(stderr, "PCI host bridges must have unique BUIDs\n"); 531 return -1; 532 } 533 534 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 535 536 namebuf = alloca(strlen(sphb->dtbusname) + 32); 537 538 /* Initialize memory regions */ 539 sprintf(namebuf, "%s.mmio", sphb->dtbusname); 540 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, INT64_MAX); 541 542 sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); 543 memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), 544 namebuf, &sphb->memspace, 545 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 546 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 547 &sphb->memwindow); 548 549 /* On ppc, we only have MMIO no specific IO space from the CPU 550 * perspective. In theory we ought to be able to embed the PCI IO 551 * memory region direction in the system memory space. However, 552 * if any of the IO BAR subregions use the old_portio mechanism, 553 * that won't be processed properly unless accessed from the 554 * system io address space. This hack to bounce things via 555 * system_io works around the problem until all the users of 556 * old_portion are updated */ 557 sprintf(namebuf, "%s.io", sphb->dtbusname); 558 memory_region_init(&sphb->iospace, OBJECT(sphb), 559 namebuf, SPAPR_PCI_IO_WIN_SIZE); 560 /* FIXME: fix to support multiple PHBs */ 561 memory_region_add_subregion(get_system_io(), 0, &sphb->iospace); 562 563 sprintf(namebuf, "%s.io-alias", sphb->dtbusname); 564 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 565 get_system_io(), 0, SPAPR_PCI_IO_WIN_SIZE); 566 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 567 &sphb->iowindow); 568 569 /* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 570 * we need to allocate some memory to catch those writes coming 571 * from msi_notify()/msix_notify() */ 572 if (msi_supported) { 573 sprintf(namebuf, "%s.msi", sphb->dtbusname); 574 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, sphb, 575 namebuf, SPAPR_MSIX_MAX_DEVS * 0x10000); 576 memory_region_add_subregion(get_system_memory(), sphb->msi_win_addr, 577 &sphb->msiwindow); 578 } 579 580 /* 581 * Selecting a busname is more complex than you'd think, due to 582 * interacting constraints. If the user has specified an id 583 * explicitly for the phb , then we want to use the qdev default 584 * of naming the bus based on the bridge device (so the user can 585 * then assign devices to it in the way they expect). For the 586 * first / default PCI bus (index=0) we want to use just "pci" 587 * because libvirt expects there to be a bus called, simply, 588 * "pci". Otherwise, we use the same name as in the device tree, 589 * since it's unique by construction, and makes the guest visible 590 * BUID clear. 591 */ 592 if (dev->id) { 593 busname = NULL; 594 } else if (sphb->index == 0) { 595 busname = "pci"; 596 } else { 597 busname = sphb->dtbusname; 598 } 599 bus = pci_register_bus(dev, busname, 600 pci_spapr_set_irq, pci_spapr_map_irq, sphb, 601 &sphb->memspace, &sphb->iospace, 602 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); 603 phb->bus = bus; 604 605 sphb->dma_window_start = 0; 606 sphb->dma_window_size = 0x40000000; 607 sphb->tcet = spapr_tce_new_table(dev, sphb->dma_liobn, 608 sphb->dma_window_size); 609 if (!sphb->tcet) { 610 fprintf(stderr, "Unable to create TCE table for %s\n", sphb->dtbusname); 611 return -1; 612 } 613 address_space_init(&sphb->iommu_as, spapr_tce_get_iommu(sphb->tcet), 614 sphb->dtbusname); 615 616 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 617 618 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 619 620 /* Initialize the LSI table */ 621 for (i = 0; i < PCI_NUM_PINS; i++) { 622 uint32_t irq; 623 624 irq = spapr_allocate_lsi(0); 625 if (!irq) { 626 return -1; 627 } 628 629 sphb->lsi_table[i].irq = irq; 630 } 631 632 return 0; 633 } 634 635 static void spapr_phb_reset(DeviceState *qdev) 636 { 637 SysBusDevice *s = SYS_BUS_DEVICE(qdev); 638 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 639 640 /* Reset the IOMMU state */ 641 device_reset(DEVICE(sphb->tcet)); 642 } 643 644 static Property spapr_phb_properties[] = { 645 DEFINE_PROP_INT32("index", sPAPRPHBState, index, -1), 646 DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, -1), 647 DEFINE_PROP_HEX32("liobn", sPAPRPHBState, dma_liobn, -1), 648 DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), 649 DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 650 SPAPR_PCI_MMIO_WIN_SIZE), 651 DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, -1), 652 DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 653 SPAPR_PCI_IO_WIN_SIZE), 654 DEFINE_PROP_HEX64("msi_win_addr", sPAPRPHBState, msi_win_addr, -1), 655 DEFINE_PROP_END_OF_LIST(), 656 }; 657 658 static const VMStateDescription vmstate_spapr_pci_lsi = { 659 .name = "spapr_pci/lsi", 660 .version_id = 1, 661 .minimum_version_id = 1, 662 .minimum_version_id_old = 1, 663 .fields = (VMStateField []) { 664 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), 665 666 VMSTATE_END_OF_LIST() 667 }, 668 }; 669 670 static const VMStateDescription vmstate_spapr_pci_msi = { 671 .name = "spapr_pci/lsi", 672 .version_id = 1, 673 .minimum_version_id = 1, 674 .minimum_version_id_old = 1, 675 .fields = (VMStateField []) { 676 VMSTATE_UINT32(config_addr, struct spapr_pci_msi), 677 VMSTATE_UINT32(irq, struct spapr_pci_msi), 678 VMSTATE_UINT32(nvec, struct spapr_pci_msi), 679 680 VMSTATE_END_OF_LIST() 681 }, 682 }; 683 684 static const VMStateDescription vmstate_spapr_pci = { 685 .name = "spapr_pci", 686 .version_id = 1, 687 .minimum_version_id = 1, 688 .minimum_version_id_old = 1, 689 .fields = (VMStateField []) { 690 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), 691 VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), 692 VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), 693 VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), 694 VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), 695 VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), 696 VMSTATE_UINT64_EQUAL(msi_win_addr, sPAPRPHBState), 697 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, 698 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 699 VMSTATE_STRUCT_ARRAY(msi_table, sPAPRPHBState, SPAPR_MSIX_MAX_DEVS, 0, 700 vmstate_spapr_pci_msi, struct spapr_pci_msi), 701 702 VMSTATE_END_OF_LIST() 703 }, 704 }; 705 706 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 707 PCIBus *rootbus) 708 { 709 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 710 711 return sphb->dtbusname; 712 } 713 714 static void spapr_phb_class_init(ObjectClass *klass, void *data) 715 { 716 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 717 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 718 DeviceClass *dc = DEVICE_CLASS(klass); 719 720 hc->root_bus_path = spapr_phb_root_bus_path; 721 sdc->init = spapr_phb_init; 722 dc->props = spapr_phb_properties; 723 dc->reset = spapr_phb_reset; 724 dc->vmsd = &vmstate_spapr_pci; 725 } 726 727 static const TypeInfo spapr_phb_info = { 728 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 729 .parent = TYPE_PCI_HOST_BRIDGE, 730 .instance_size = sizeof(sPAPRPHBState), 731 .class_init = spapr_phb_class_init, 732 }; 733 734 PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index) 735 { 736 DeviceState *dev; 737 738 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 739 qdev_prop_set_uint32(dev, "index", index); 740 qdev_init_nofail(dev); 741 742 return PCI_HOST_BRIDGE(dev); 743 } 744 745 /* Macros to operate with address in OF binding to PCI */ 746 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 747 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 748 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 749 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 750 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 751 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 752 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 753 #define b_fff(x) b_x((x), 8, 3) /* function number */ 754 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 755 756 int spapr_populate_pci_dt(sPAPRPHBState *phb, 757 uint32_t xics_phandle, 758 void *fdt) 759 { 760 int bus_off, i, j; 761 char nodename[256]; 762 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 763 struct { 764 uint32_t hi; 765 uint64_t child; 766 uint64_t parent; 767 uint64_t size; 768 } QEMU_PACKED ranges[] = { 769 { 770 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 771 cpu_to_be64(phb->io_win_addr), 772 cpu_to_be64(memory_region_size(&phb->iospace)), 773 }, 774 { 775 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 776 cpu_to_be64(phb->mem_win_addr), 777 cpu_to_be64(memory_region_size(&phb->memwindow)), 778 }, 779 }; 780 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 781 uint32_t interrupt_map_mask[] = { 782 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 783 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 784 785 /* Start populating the FDT */ 786 sprintf(nodename, "pci@%" PRIx64, phb->buid); 787 bus_off = fdt_add_subnode(fdt, 0, nodename); 788 if (bus_off < 0) { 789 return bus_off; 790 } 791 792 #define _FDT(exp) \ 793 do { \ 794 int ret = (exp); \ 795 if (ret < 0) { \ 796 return ret; \ 797 } \ 798 } while (0) 799 800 /* Write PHB properties */ 801 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 802 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 803 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); 804 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); 805 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 806 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 807 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 808 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges))); 809 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 810 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 811 812 /* Build the interrupt-map, this must matches what is done 813 * in pci_spapr_map_irq 814 */ 815 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 816 &interrupt_map_mask, sizeof(interrupt_map_mask))); 817 for (i = 0; i < PCI_SLOT_MAX; i++) { 818 for (j = 0; j < PCI_NUM_PINS; j++) { 819 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 820 int lsi_num = pci_spapr_swizzle(i, j); 821 822 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 823 irqmap[1] = 0; 824 irqmap[2] = 0; 825 irqmap[3] = cpu_to_be32(j+1); 826 irqmap[4] = cpu_to_be32(xics_phandle); 827 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); 828 irqmap[6] = cpu_to_be32(0x8); 829 } 830 } 831 /* Write interrupt map */ 832 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 833 sizeof(interrupt_map))); 834 835 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 836 phb->dma_liobn, phb->dma_window_start, 837 phb->dma_window_size); 838 839 return 0; 840 } 841 842 void spapr_pci_rtas_init(void) 843 { 844 spapr_rtas_register("read-pci-config", rtas_read_pci_config); 845 spapr_rtas_register("write-pci-config", rtas_write_pci_config); 846 spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config); 847 spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config); 848 if (msi_supported) { 849 spapr_rtas_register("ibm,query-interrupt-source-number", 850 rtas_ibm_query_interrupt_source_number); 851 spapr_rtas_register("ibm,change-msi", rtas_ibm_change_msi); 852 } 853 } 854 855 static void spapr_pci_register_types(void) 856 { 857 type_register_static(&spapr_phb_info); 858 } 859 860 type_init(spapr_pci_register_types) 861