1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "hw/hw.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/msi.h" 29 #include "hw/pci/msix.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/ppc/spapr.h" 32 #include "hw/pci-host/spapr.h" 33 #include "exec/address-spaces.h" 34 #include <libfdt.h> 35 #include "trace.h" 36 #include "qemu/error-report.h" 37 #include "qapi/qmp/qerror.h" 38 39 #include "hw/pci/pci_bridge.h" 40 #include "hw/pci/pci_bus.h" 41 #include "hw/ppc/spapr_drc.h" 42 #include "sysemu/device_tree.h" 43 44 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 45 #define RTAS_QUERY_FN 0 46 #define RTAS_CHANGE_FN 1 47 #define RTAS_RESET_FN 2 48 #define RTAS_CHANGE_MSI_FN 3 49 #define RTAS_CHANGE_MSIX_FN 4 50 51 /* Interrupt types to return on RTAS_CHANGE_* */ 52 #define RTAS_TYPE_MSI 1 53 #define RTAS_TYPE_MSIX 2 54 55 #define FDT_NAME_MAX 128 56 57 #define _FDT(exp) \ 58 do { \ 59 int ret = (exp); \ 60 if (ret < 0) { \ 61 return ret; \ 62 } \ 63 } while (0) 64 65 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) 66 { 67 sPAPRPHBState *sphb; 68 69 QLIST_FOREACH(sphb, &spapr->phbs, list) { 70 if (sphb->buid != buid) { 71 continue; 72 } 73 return sphb; 74 } 75 76 return NULL; 77 } 78 79 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 80 uint32_t config_addr) 81 { 82 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); 83 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 84 int bus_num = (config_addr >> 16) & 0xFF; 85 int devfn = (config_addr >> 8) & 0xFF; 86 87 if (!phb) { 88 return NULL; 89 } 90 91 return pci_find_device(phb->bus, bus_num, devfn); 92 } 93 94 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 95 { 96 /* This handles the encoding of extended config space addresses */ 97 return ((arg >> 20) & 0xf00) | (arg & 0xff); 98 } 99 100 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, 101 uint32_t addr, uint32_t size, 102 target_ulong rets) 103 { 104 PCIDevice *pci_dev; 105 uint32_t val; 106 107 if ((size != 1) && (size != 2) && (size != 4)) { 108 /* access must be 1, 2 or 4 bytes */ 109 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 110 return; 111 } 112 113 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 114 addr = rtas_pci_cfgaddr(addr); 115 116 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 117 /* Access must be to a valid device, within bounds and 118 * naturally aligned */ 119 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 120 return; 121 } 122 123 val = pci_host_config_read_common(pci_dev, addr, 124 pci_config_size(pci_dev), size); 125 126 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 127 rtas_st(rets, 1, val); 128 } 129 130 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 131 uint32_t token, uint32_t nargs, 132 target_ulong args, 133 uint32_t nret, target_ulong rets) 134 { 135 uint64_t buid; 136 uint32_t size, addr; 137 138 if ((nargs != 4) || (nret != 2)) { 139 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 140 return; 141 } 142 143 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 144 size = rtas_ld(args, 3); 145 addr = rtas_ld(args, 0); 146 147 finish_read_pci_config(spapr, buid, addr, size, rets); 148 } 149 150 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 151 uint32_t token, uint32_t nargs, 152 target_ulong args, 153 uint32_t nret, target_ulong rets) 154 { 155 uint32_t size, addr; 156 157 if ((nargs != 2) || (nret != 2)) { 158 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 159 return; 160 } 161 162 size = rtas_ld(args, 1); 163 addr = rtas_ld(args, 0); 164 165 finish_read_pci_config(spapr, 0, addr, size, rets); 166 } 167 168 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, 169 uint32_t addr, uint32_t size, 170 uint32_t val, target_ulong rets) 171 { 172 PCIDevice *pci_dev; 173 174 if ((size != 1) && (size != 2) && (size != 4)) { 175 /* access must be 1, 2 or 4 bytes */ 176 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 177 return; 178 } 179 180 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 181 addr = rtas_pci_cfgaddr(addr); 182 183 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 184 /* Access must be to a valid device, within bounds and 185 * naturally aligned */ 186 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 187 return; 188 } 189 190 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 191 val, size); 192 193 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 194 } 195 196 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 197 uint32_t token, uint32_t nargs, 198 target_ulong args, 199 uint32_t nret, target_ulong rets) 200 { 201 uint64_t buid; 202 uint32_t val, size, addr; 203 204 if ((nargs != 5) || (nret != 1)) { 205 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 206 return; 207 } 208 209 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 210 val = rtas_ld(args, 4); 211 size = rtas_ld(args, 3); 212 addr = rtas_ld(args, 0); 213 214 finish_write_pci_config(spapr, buid, addr, size, val, rets); 215 } 216 217 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 218 uint32_t token, uint32_t nargs, 219 target_ulong args, 220 uint32_t nret, target_ulong rets) 221 { 222 uint32_t val, size, addr; 223 224 if ((nargs != 3) || (nret != 1)) { 225 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 226 return; 227 } 228 229 230 val = rtas_ld(args, 2); 231 size = rtas_ld(args, 1); 232 addr = rtas_ld(args, 0); 233 234 finish_write_pci_config(spapr, 0, addr, size, val, rets); 235 } 236 237 /* 238 * Set MSI/MSIX message data. 239 * This is required for msi_notify()/msix_notify() which 240 * will write at the addresses via spapr_msi_write(). 241 * 242 * If hwaddr == 0, all entries will have .data == first_irq i.e. 243 * table will be reset. 244 */ 245 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 246 unsigned first_irq, unsigned req_num) 247 { 248 unsigned i; 249 MSIMessage msg = { .address = addr, .data = first_irq }; 250 251 if (!msix) { 252 msi_set_message(pdev, msg); 253 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 254 return; 255 } 256 257 for (i = 0; i < req_num; ++i) { 258 msix_set_message(pdev, i, msg); 259 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 260 if (addr) { 261 ++msg.data; 262 } 263 } 264 } 265 266 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 267 uint32_t token, uint32_t nargs, 268 target_ulong args, uint32_t nret, 269 target_ulong rets) 270 { 271 uint32_t config_addr = rtas_ld(args, 0); 272 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 273 unsigned int func = rtas_ld(args, 3); 274 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 275 unsigned int seq_num = rtas_ld(args, 5); 276 unsigned int ret_intr_type; 277 unsigned int irq, max_irqs = 0, num = 0; 278 sPAPRPHBState *phb = NULL; 279 PCIDevice *pdev = NULL; 280 spapr_pci_msi *msi; 281 int *config_addr_key; 282 283 switch (func) { 284 case RTAS_CHANGE_MSI_FN: 285 case RTAS_CHANGE_FN: 286 ret_intr_type = RTAS_TYPE_MSI; 287 break; 288 case RTAS_CHANGE_MSIX_FN: 289 ret_intr_type = RTAS_TYPE_MSIX; 290 break; 291 default: 292 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 293 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 294 return; 295 } 296 297 /* Fins sPAPRPHBState */ 298 phb = spapr_pci_find_phb(spapr, buid); 299 if (phb) { 300 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 301 } 302 if (!phb || !pdev) { 303 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 304 return; 305 } 306 307 /* Releasing MSIs */ 308 if (!req_num) { 309 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 310 if (!msi) { 311 trace_spapr_pci_msi("Releasing wrong config", config_addr); 312 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 313 return; 314 } 315 316 xics_free(spapr->icp, msi->first_irq, msi->num); 317 if (msi_present(pdev)) { 318 spapr_msi_setmsg(pdev, 0, false, 0, num); 319 } 320 if (msix_present(pdev)) { 321 spapr_msi_setmsg(pdev, 0, true, 0, num); 322 } 323 g_hash_table_remove(phb->msi, &config_addr); 324 325 trace_spapr_pci_msi("Released MSIs", config_addr); 326 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 327 rtas_st(rets, 1, 0); 328 return; 329 } 330 331 /* Enabling MSI */ 332 333 /* Check if the device supports as many IRQs as requested */ 334 if (ret_intr_type == RTAS_TYPE_MSI) { 335 max_irqs = msi_nr_vectors_allocated(pdev); 336 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 337 max_irqs = pdev->msix_entries_nr; 338 } 339 if (!max_irqs) { 340 error_report("Requested interrupt type %d is not enabled for device %x", 341 ret_intr_type, config_addr); 342 rtas_st(rets, 0, -1); /* Hardware error */ 343 return; 344 } 345 /* Correct the number if the guest asked for too many */ 346 if (req_num > max_irqs) { 347 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 348 req_num = max_irqs; 349 irq = 0; /* to avoid misleading trace */ 350 goto out; 351 } 352 353 /* Allocate MSIs */ 354 irq = xics_alloc_block(spapr->icp, 0, req_num, false, 355 ret_intr_type == RTAS_TYPE_MSI); 356 if (!irq) { 357 error_report("Cannot allocate MSIs for device %x", config_addr); 358 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 359 return; 360 } 361 362 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 363 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 364 irq, req_num); 365 366 /* Add MSI device to cache */ 367 msi = g_new(spapr_pci_msi, 1); 368 msi->first_irq = irq; 369 msi->num = req_num; 370 config_addr_key = g_new(int, 1); 371 *config_addr_key = config_addr; 372 g_hash_table_insert(phb->msi, config_addr_key, msi); 373 374 out: 375 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 376 rtas_st(rets, 1, req_num); 377 rtas_st(rets, 2, ++seq_num); 378 rtas_st(rets, 3, ret_intr_type); 379 380 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 381 } 382 383 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 384 sPAPRMachineState *spapr, 385 uint32_t token, 386 uint32_t nargs, 387 target_ulong args, 388 uint32_t nret, 389 target_ulong rets) 390 { 391 uint32_t config_addr = rtas_ld(args, 0); 392 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 393 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 394 sPAPRPHBState *phb = NULL; 395 PCIDevice *pdev = NULL; 396 spapr_pci_msi *msi; 397 398 /* Find sPAPRPHBState */ 399 phb = spapr_pci_find_phb(spapr, buid); 400 if (phb) { 401 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 402 } 403 if (!phb || !pdev) { 404 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 405 return; 406 } 407 408 /* Find device descriptor and start IRQ */ 409 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 410 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 411 trace_spapr_pci_msi("Failed to return vector", config_addr); 412 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 413 return; 414 } 415 intr_src_num = msi->first_irq + ioa_intr_num; 416 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 417 intr_src_num); 418 419 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 420 rtas_st(rets, 1, intr_src_num); 421 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 422 } 423 424 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 425 sPAPRMachineState *spapr, 426 uint32_t token, uint32_t nargs, 427 target_ulong args, uint32_t nret, 428 target_ulong rets) 429 { 430 sPAPRPHBState *sphb; 431 sPAPRPHBClass *spc; 432 uint32_t addr, option; 433 uint64_t buid; 434 int ret; 435 436 if ((nargs != 4) || (nret != 1)) { 437 goto param_error_exit; 438 } 439 440 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 441 addr = rtas_ld(args, 0); 442 option = rtas_ld(args, 3); 443 444 sphb = spapr_pci_find_phb(spapr, buid); 445 if (!sphb) { 446 goto param_error_exit; 447 } 448 449 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 450 if (!spc->eeh_set_option) { 451 goto param_error_exit; 452 } 453 454 ret = spc->eeh_set_option(sphb, addr, option); 455 rtas_st(rets, 0, ret); 456 return; 457 458 param_error_exit: 459 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 460 } 461 462 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 463 sPAPRMachineState *spapr, 464 uint32_t token, uint32_t nargs, 465 target_ulong args, uint32_t nret, 466 target_ulong rets) 467 { 468 sPAPRPHBState *sphb; 469 sPAPRPHBClass *spc; 470 PCIDevice *pdev; 471 uint32_t addr, option; 472 uint64_t buid; 473 474 if ((nargs != 4) || (nret != 2)) { 475 goto param_error_exit; 476 } 477 478 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 479 sphb = spapr_pci_find_phb(spapr, buid); 480 if (!sphb) { 481 goto param_error_exit; 482 } 483 484 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 485 if (!spc->eeh_set_option) { 486 goto param_error_exit; 487 } 488 489 /* 490 * We always have PE address of form "00BB0001". "BB" 491 * represents the bus number of PE's primary bus. 492 */ 493 option = rtas_ld(args, 3); 494 switch (option) { 495 case RTAS_GET_PE_ADDR: 496 addr = rtas_ld(args, 0); 497 pdev = spapr_pci_find_dev(spapr, buid, addr); 498 if (!pdev) { 499 goto param_error_exit; 500 } 501 502 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); 503 break; 504 case RTAS_GET_PE_MODE: 505 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 506 break; 507 default: 508 goto param_error_exit; 509 } 510 511 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 512 return; 513 514 param_error_exit: 515 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 516 } 517 518 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 519 sPAPRMachineState *spapr, 520 uint32_t token, uint32_t nargs, 521 target_ulong args, uint32_t nret, 522 target_ulong rets) 523 { 524 sPAPRPHBState *sphb; 525 sPAPRPHBClass *spc; 526 uint64_t buid; 527 int state, ret; 528 529 if ((nargs != 3) || (nret != 4 && nret != 5)) { 530 goto param_error_exit; 531 } 532 533 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 534 sphb = spapr_pci_find_phb(spapr, buid); 535 if (!sphb) { 536 goto param_error_exit; 537 } 538 539 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 540 if (!spc->eeh_get_state) { 541 goto param_error_exit; 542 } 543 544 ret = spc->eeh_get_state(sphb, &state); 545 rtas_st(rets, 0, ret); 546 if (ret != RTAS_OUT_SUCCESS) { 547 return; 548 } 549 550 rtas_st(rets, 1, state); 551 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 552 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 553 if (nret >= 5) { 554 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 555 } 556 return; 557 558 param_error_exit: 559 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 560 } 561 562 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 563 sPAPRMachineState *spapr, 564 uint32_t token, uint32_t nargs, 565 target_ulong args, uint32_t nret, 566 target_ulong rets) 567 { 568 sPAPRPHBState *sphb; 569 sPAPRPHBClass *spc; 570 uint32_t option; 571 uint64_t buid; 572 int ret; 573 574 if ((nargs != 4) || (nret != 1)) { 575 goto param_error_exit; 576 } 577 578 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 579 option = rtas_ld(args, 3); 580 sphb = spapr_pci_find_phb(spapr, buid); 581 if (!sphb) { 582 goto param_error_exit; 583 } 584 585 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 586 if (!spc->eeh_reset) { 587 goto param_error_exit; 588 } 589 590 ret = spc->eeh_reset(sphb, option); 591 rtas_st(rets, 0, ret); 592 return; 593 594 param_error_exit: 595 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 596 } 597 598 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 599 sPAPRMachineState *spapr, 600 uint32_t token, uint32_t nargs, 601 target_ulong args, uint32_t nret, 602 target_ulong rets) 603 { 604 sPAPRPHBState *sphb; 605 sPAPRPHBClass *spc; 606 uint64_t buid; 607 int ret; 608 609 if ((nargs != 3) || (nret != 1)) { 610 goto param_error_exit; 611 } 612 613 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 614 sphb = spapr_pci_find_phb(spapr, buid); 615 if (!sphb) { 616 goto param_error_exit; 617 } 618 619 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 620 if (!spc->eeh_configure) { 621 goto param_error_exit; 622 } 623 624 ret = spc->eeh_configure(sphb); 625 rtas_st(rets, 0, ret); 626 return; 627 628 param_error_exit: 629 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 630 } 631 632 /* To support it later */ 633 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 634 sPAPRMachineState *spapr, 635 uint32_t token, uint32_t nargs, 636 target_ulong args, uint32_t nret, 637 target_ulong rets) 638 { 639 sPAPRPHBState *sphb; 640 sPAPRPHBClass *spc; 641 int option; 642 uint64_t buid; 643 644 if ((nargs != 8) || (nret != 1)) { 645 goto param_error_exit; 646 } 647 648 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 649 sphb = spapr_pci_find_phb(spapr, buid); 650 if (!sphb) { 651 goto param_error_exit; 652 } 653 654 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 655 if (!spc->eeh_set_option) { 656 goto param_error_exit; 657 } 658 659 option = rtas_ld(args, 7); 660 switch (option) { 661 case RTAS_SLOT_TEMP_ERR_LOG: 662 case RTAS_SLOT_PERM_ERR_LOG: 663 break; 664 default: 665 goto param_error_exit; 666 } 667 668 /* We don't have error log yet */ 669 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 670 return; 671 672 param_error_exit: 673 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 674 } 675 676 static int pci_spapr_swizzle(int slot, int pin) 677 { 678 return (slot + pin) % PCI_NUM_PINS; 679 } 680 681 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) 682 { 683 /* 684 * Here we need to convert pci_dev + irq_num to some unique value 685 * which is less than number of IRQs on the specific bus (4). We 686 * use standard PCI swizzling, that is (slot number + pin number) 687 * % 4. 688 */ 689 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); 690 } 691 692 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 693 { 694 /* 695 * Here we use the number returned by pci_spapr_map_irq to find a 696 * corresponding qemu_irq. 697 */ 698 sPAPRPHBState *phb = opaque; 699 700 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 701 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 702 } 703 704 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 705 { 706 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 707 PCIINTxRoute route; 708 709 route.mode = PCI_INTX_ENABLED; 710 route.irq = sphb->lsi_table[pin].irq; 711 712 return route; 713 } 714 715 /* 716 * MSI/MSIX memory region implementation. 717 * The handler handles both MSI and MSIX. 718 * For MSI-X, the vector number is encoded as a part of the address, 719 * data is set to 0. 720 * For MSI, the vector number is encoded in least bits in data. 721 */ 722 static void spapr_msi_write(void *opaque, hwaddr addr, 723 uint64_t data, unsigned size) 724 { 725 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 726 uint32_t irq = data; 727 728 trace_spapr_pci_msi_write(addr, data, irq); 729 730 qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); 731 } 732 733 static const MemoryRegionOps spapr_msi_ops = { 734 /* There is no .read as the read result is undefined by PCI spec */ 735 .read = NULL, 736 .write = spapr_msi_write, 737 .endianness = DEVICE_LITTLE_ENDIAN 738 }; 739 740 /* 741 * PHB PCI device 742 */ 743 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 744 { 745 sPAPRPHBState *phb = opaque; 746 747 return &phb->iommu_as; 748 } 749 750 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 751 { 752 char *path = NULL, *buf = NULL, *host = NULL; 753 754 /* Get the PCI VFIO host id */ 755 host = object_property_get_str(OBJECT(pdev), "host", NULL); 756 if (!host) { 757 goto err_out; 758 } 759 760 /* Construct the path of the file that will give us the DT location */ 761 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 762 g_free(host); 763 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 764 goto err_out; 765 } 766 g_free(path); 767 768 /* Construct and read from host device tree the loc-code */ 769 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 770 g_free(buf); 771 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 772 goto err_out; 773 } 774 return buf; 775 776 err_out: 777 g_free(path); 778 return NULL; 779 } 780 781 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 782 { 783 char *buf; 784 const char *devtype = "qemu"; 785 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 786 787 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 788 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 789 if (buf) { 790 return buf; 791 } 792 devtype = "vfio"; 793 } 794 /* 795 * For emulated devices and VFIO-failure case, make up 796 * the loc-code. 797 */ 798 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 799 devtype, pdev->name, sphb->index, busnr, 800 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 801 return buf; 802 } 803 804 /* Macros to operate with address in OF binding to PCI */ 805 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 806 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 807 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 808 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 809 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 810 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 811 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 812 #define b_fff(x) b_x((x), 8, 3) /* function number */ 813 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 814 815 /* for 'reg'/'assigned-addresses' OF properties */ 816 #define RESOURCE_CELLS_SIZE 2 817 #define RESOURCE_CELLS_ADDRESS 3 818 819 typedef struct ResourceFields { 820 uint32_t phys_hi; 821 uint32_t phys_mid; 822 uint32_t phys_lo; 823 uint32_t size_hi; 824 uint32_t size_lo; 825 } QEMU_PACKED ResourceFields; 826 827 typedef struct ResourceProps { 828 ResourceFields reg[8]; 829 ResourceFields assigned[7]; 830 uint32_t reg_len; 831 uint32_t assigned_len; 832 } ResourceProps; 833 834 /* fill in the 'reg'/'assigned-resources' OF properties for 835 * a PCI device. 'reg' describes resource requirements for a 836 * device's IO/MEM regions, 'assigned-addresses' describes the 837 * actual resource assignments. 838 * 839 * the properties are arrays of ('phys-addr', 'size') pairs describing 840 * the addressable regions of the PCI device, where 'phys-addr' is a 841 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 842 * (phys.hi, phys.mid, phys.lo), and 'size' is a 843 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 844 * 845 * phys.hi = 0xYYXXXXZZ, where: 846 * 0xYY = npt000ss 847 * ||| | 848 * ||| +-- space code 849 * ||| | 850 * ||| + 00 if configuration space 851 * ||| + 01 if IO region, 852 * ||| + 10 if 32-bit MEM region 853 * ||| + 11 if 64-bit MEM region 854 * ||| 855 * ||+------ for non-relocatable IO: 1 if aliased 856 * || for relocatable IO: 1 if below 64KB 857 * || for MEM: 1 if below 1MB 858 * |+------- 1 if region is prefetchable 859 * +-------- 1 if region is non-relocatable 860 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 861 * bits respectively 862 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 863 * to the region 864 * 865 * phys.mid and phys.lo correspond respectively to the hi/lo portions 866 * of the actual address of the region. 867 * 868 * how the phys-addr/size values are used differ slightly between 869 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 870 * an additional description for the config space region of the 871 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 872 * to describe the region as relocatable, with an address-mapping 873 * that corresponds directly to the PHB's address space for the 874 * resource. 'assigned-addresses' always has n=1 set with an absolute 875 * address assigned for the resource. in general, 'assigned-addresses' 876 * won't be populated, since addresses for PCI devices are generally 877 * unmapped initially and left to the guest to assign. 878 * 879 * note also that addresses defined in these properties are, at least 880 * for PAPR guests, relative to the PHBs IO/MEM windows, and 881 * correspond directly to the addresses in the BARs. 882 * 883 * in accordance with PCI Bus Binding to Open Firmware, 884 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 885 * Appendix C. 886 */ 887 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 888 { 889 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 890 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 891 b_ddddd(PCI_SLOT(d->devfn)) | 892 b_fff(PCI_FUNC(d->devfn))); 893 ResourceFields *reg, *assigned; 894 int i, reg_idx = 0, assigned_idx = 0; 895 896 /* config space region */ 897 reg = &rp->reg[reg_idx++]; 898 reg->phys_hi = cpu_to_be32(dev_id); 899 reg->phys_mid = 0; 900 reg->phys_lo = 0; 901 reg->size_hi = 0; 902 reg->size_lo = 0; 903 904 for (i = 0; i < PCI_NUM_REGIONS; i++) { 905 if (!d->io_regions[i].size) { 906 continue; 907 } 908 909 reg = &rp->reg[reg_idx++]; 910 911 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 912 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 913 reg->phys_hi |= cpu_to_be32(b_ss(1)); 914 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 915 reg->phys_hi |= cpu_to_be32(b_ss(3)); 916 } else { 917 reg->phys_hi |= cpu_to_be32(b_ss(2)); 918 } 919 reg->phys_mid = 0; 920 reg->phys_lo = 0; 921 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 922 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 923 924 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 925 continue; 926 } 927 928 assigned = &rp->assigned[assigned_idx++]; 929 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); 930 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 931 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 932 assigned->size_hi = reg->size_hi; 933 assigned->size_lo = reg->size_lo; 934 } 935 936 rp->reg_len = reg_idx * sizeof(ResourceFields); 937 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 938 } 939 940 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, 941 int phb_index, int drc_index, 942 sPAPRPHBState *sphb) 943 { 944 ResourceProps rp; 945 bool is_bridge = false; 946 int pci_status, err; 947 char *buf = NULL; 948 949 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == 950 PCI_HEADER_TYPE_BRIDGE) { 951 is_bridge = true; 952 } 953 954 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 955 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", 956 pci_default_read_config(dev, PCI_VENDOR_ID, 2))); 957 _FDT(fdt_setprop_cell(fdt, offset, "device-id", 958 pci_default_read_config(dev, PCI_DEVICE_ID, 2))); 959 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", 960 pci_default_read_config(dev, PCI_REVISION_ID, 1))); 961 _FDT(fdt_setprop_cell(fdt, offset, "class-code", 962 pci_default_read_config(dev, PCI_CLASS_PROG, 3))); 963 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { 964 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", 965 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); 966 } 967 968 if (!is_bridge) { 969 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", 970 pci_default_read_config(dev, PCI_MIN_GNT, 1))); 971 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", 972 pci_default_read_config(dev, PCI_MAX_LAT, 1))); 973 } 974 975 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { 976 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", 977 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); 978 } 979 980 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { 981 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 982 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); 983 } 984 985 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", 986 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); 987 988 /* the following fdt cells are masked off the pci status register */ 989 pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 990 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 991 PCI_STATUS_DEVSEL_MASK & pci_status)); 992 993 if (pci_status & PCI_STATUS_FAST_BACK) { 994 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 995 } 996 if (pci_status & PCI_STATUS_66MHZ) { 997 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 998 } 999 if (pci_status & PCI_STATUS_UDF) { 1000 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1001 } 1002 1003 /* NOTE: this is normally generated by firmware via path/unit name, 1004 * but in our case we must set it manually since it does not get 1005 * processed by OF beforehand 1006 */ 1007 _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); 1008 buf = spapr_phb_get_loc_code(sphb, dev); 1009 if (!buf) { 1010 error_report("Failed setting the ibm,loc-code"); 1011 return -1; 1012 } 1013 1014 err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); 1015 g_free(buf); 1016 if (err < 0) { 1017 return err; 1018 } 1019 1020 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); 1021 1022 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1023 RESOURCE_CELLS_ADDRESS)); 1024 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1025 RESOURCE_CELLS_SIZE)); 1026 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", 1027 RESOURCE_CELLS_SIZE)); 1028 1029 populate_resource_props(dev, &rp); 1030 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1031 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1032 (uint8_t *)rp.assigned, rp.assigned_len)); 1033 1034 return 0; 1035 } 1036 1037 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1038 PCIDevice *pdev); 1039 1040 /* create OF node for pci device and required OF DT properties */ 1041 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, 1042 int drc_index, const char *drc_name, 1043 void *fdt, int node_offset) 1044 { 1045 int offset, ret; 1046 int slot = PCI_SLOT(dev->devfn); 1047 int func = PCI_FUNC(dev->devfn); 1048 char nodename[FDT_NAME_MAX]; 1049 1050 if (func != 0) { 1051 snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); 1052 } else { 1053 snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); 1054 } 1055 offset = fdt_add_subnode(fdt, node_offset, nodename); 1056 ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb->index, drc_index, 1057 phb); 1058 g_assert(!ret); 1059 if (ret) { 1060 return 0; 1061 } 1062 return offset; 1063 } 1064 1065 static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, 1066 sPAPRPHBState *phb, 1067 PCIDevice *pdev, 1068 Error **errp) 1069 { 1070 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1071 DeviceState *dev = DEVICE(pdev); 1072 int drc_index = drck->get_index(drc); 1073 void *fdt = NULL; 1074 int fdt_start_offset = 0, fdt_size; 1075 1076 if (dev->hotplugged) { 1077 fdt = create_device_tree(&fdt_size); 1078 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, 1079 drc_index, NULL, 1080 fdt, 0); 1081 if (!fdt_start_offset) { 1082 error_setg(errp, "Failed to create pci child device tree node"); 1083 goto out; 1084 } 1085 } 1086 1087 drck->attach(drc, DEVICE(pdev), 1088 fdt, fdt_start_offset, !dev->hotplugged, errp); 1089 out: 1090 if (*errp) { 1091 g_free(fdt); 1092 } 1093 } 1094 1095 static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) 1096 { 1097 /* some version guests do not wait for completion of a device 1098 * cleanup (generally done asynchronously by the kernel) before 1099 * signaling to QEMU that the device is safe, but instead sleep 1100 * for some 'safe' period of time. unfortunately on a busy host 1101 * this sleep isn't guaranteed to be long enough, resulting in 1102 * bad things like IRQ lines being left asserted during final 1103 * device removal. to deal with this we call reset just prior 1104 * to finalizing the device, which will put the device back into 1105 * an 'idle' state, as the device cleanup code expects. 1106 */ 1107 pci_device_reset(PCI_DEVICE(dev)); 1108 object_unparent(OBJECT(dev)); 1109 } 1110 1111 static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, 1112 sPAPRPHBState *phb, 1113 PCIDevice *pdev, 1114 Error **errp) 1115 { 1116 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1117 1118 drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); 1119 } 1120 1121 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, 1122 PCIDevice *pdev) 1123 { 1124 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 1125 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, 1126 (phb->index << 16) | 1127 (busnr << 8) | 1128 pdev->devfn); 1129 } 1130 1131 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1132 PCIDevice *pdev) 1133 { 1134 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1135 sPAPRDRConnectorClass *drck; 1136 1137 if (!drc) { 1138 return 0; 1139 } 1140 1141 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1142 return drck->get_index(drc); 1143 } 1144 1145 static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, 1146 DeviceState *plugged_dev, Error **errp) 1147 { 1148 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1149 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1150 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1151 Error *local_err = NULL; 1152 1153 /* if DR is disabled we don't need to do anything in the case of 1154 * hotplug or coldplug callbacks 1155 */ 1156 if (!phb->dr_enabled) { 1157 /* if this is a hotplug operation initiated by the user 1158 * we need to let them know it's not enabled 1159 */ 1160 if (plugged_dev->hotplugged) { 1161 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1162 object_get_typename(OBJECT(phb))); 1163 } 1164 return; 1165 } 1166 1167 g_assert(drc); 1168 1169 spapr_phb_add_pci_device(drc, phb, pdev, &local_err); 1170 if (local_err) { 1171 error_propagate(errp, local_err); 1172 return; 1173 } 1174 if (plugged_dev->hotplugged) { 1175 spapr_hotplug_req_add_event(drc); 1176 } 1177 } 1178 1179 static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, 1180 DeviceState *plugged_dev, Error **errp) 1181 { 1182 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1183 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1184 sPAPRDRConnectorClass *drck; 1185 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1186 Error *local_err = NULL; 1187 1188 if (!phb->dr_enabled) { 1189 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1190 object_get_typename(OBJECT(phb))); 1191 return; 1192 } 1193 1194 g_assert(drc); 1195 1196 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1197 if (!drck->release_pending(drc)) { 1198 spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); 1199 if (local_err) { 1200 error_propagate(errp, local_err); 1201 return; 1202 } 1203 spapr_hotplug_req_remove_event(drc); 1204 } 1205 } 1206 1207 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1208 { 1209 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1210 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1211 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1212 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1213 sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); 1214 char *namebuf; 1215 int i; 1216 PCIBus *bus; 1217 uint64_t msi_window_size = 4096; 1218 1219 if (sphb->index != (uint32_t)-1) { 1220 hwaddr windows_base; 1221 1222 if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) 1223 || (sphb->mem_win_addr != (hwaddr)-1) 1224 || (sphb->io_win_addr != (hwaddr)-1)) { 1225 error_setg(errp, "Either \"index\" or other parameters must" 1226 " be specified for PAPR PHB, not both"); 1227 return; 1228 } 1229 1230 if (sphb->index > SPAPR_PCI_MAX_INDEX) { 1231 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 1232 SPAPR_PCI_MAX_INDEX); 1233 return; 1234 } 1235 1236 sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; 1237 sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); 1238 1239 windows_base = SPAPR_PCI_WINDOW_BASE 1240 + sphb->index * SPAPR_PCI_WINDOW_SPACING; 1241 sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; 1242 sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; 1243 } 1244 1245 if (sphb->buid == (uint64_t)-1) { 1246 error_setg(errp, "BUID not specified for PHB"); 1247 return; 1248 } 1249 1250 if (sphb->dma_liobn == (uint32_t)-1) { 1251 error_setg(errp, "LIOBN not specified for PHB"); 1252 return; 1253 } 1254 1255 if (sphb->mem_win_addr == (hwaddr)-1) { 1256 error_setg(errp, "Memory window address not specified for PHB"); 1257 return; 1258 } 1259 1260 if (sphb->io_win_addr == (hwaddr)-1) { 1261 error_setg(errp, "IO window address not specified for PHB"); 1262 return; 1263 } 1264 1265 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1266 error_setg(errp, "PCI host bridges must have unique BUIDs"); 1267 return; 1268 } 1269 1270 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1271 1272 namebuf = alloca(strlen(sphb->dtbusname) + 32); 1273 1274 /* Initialize memory regions */ 1275 sprintf(namebuf, "%s.mmio", sphb->dtbusname); 1276 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1277 1278 sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); 1279 memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), 1280 namebuf, &sphb->memspace, 1281 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1282 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1283 &sphb->memwindow); 1284 1285 /* Initialize IO regions */ 1286 sprintf(namebuf, "%s.io", sphb->dtbusname); 1287 memory_region_init(&sphb->iospace, OBJECT(sphb), 1288 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1289 1290 sprintf(namebuf, "%s.io-alias", sphb->dtbusname); 1291 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1292 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1293 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1294 &sphb->iowindow); 1295 1296 bus = pci_register_bus(dev, NULL, 1297 pci_spapr_set_irq, pci_spapr_map_irq, sphb, 1298 &sphb->memspace, &sphb->iospace, 1299 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); 1300 phb->bus = bus; 1301 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); 1302 1303 /* 1304 * Initialize PHB address space. 1305 * By default there will be at least one subregion for default 1306 * 32bit DMA window. 1307 * Later the guest might want to create another DMA window 1308 * which will become another memory subregion. 1309 */ 1310 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); 1311 1312 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1313 namebuf, UINT64_MAX); 1314 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1315 sphb->dtbusname); 1316 1317 /* 1318 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1319 * we need to allocate some memory to catch those writes coming 1320 * from msi_notify()/msix_notify(). 1321 * As MSIMessage:addr is going to be the same and MSIMessage:data 1322 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1323 * be used. 1324 * 1325 * For KVM we want to ensure that this memory is a full page so that 1326 * our memory slot is of page size granularity. 1327 */ 1328 #ifdef CONFIG_KVM 1329 if (kvm_enabled()) { 1330 msi_window_size = getpagesize(); 1331 } 1332 #endif 1333 1334 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, 1335 "msi", msi_window_size); 1336 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1337 &sphb->msiwindow); 1338 1339 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1340 1341 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1342 1343 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1344 1345 /* Initialize the LSI table */ 1346 for (i = 0; i < PCI_NUM_PINS; i++) { 1347 uint32_t irq; 1348 1349 irq = xics_alloc_block(spapr->icp, 0, 1, true, false); 1350 if (!irq) { 1351 error_setg(errp, "spapr_allocate_lsi failed"); 1352 return; 1353 } 1354 1355 sphb->lsi_table[i].irq = irq; 1356 } 1357 1358 /* allocate connectors for child PCI devices */ 1359 if (sphb->dr_enabled) { 1360 for (i = 0; i < PCI_SLOT_MAX * 8; i++) { 1361 spapr_dr_connector_new(OBJECT(phb), 1362 SPAPR_DR_CONNECTOR_TYPE_PCI, 1363 (sphb->index << 16) | i); 1364 } 1365 } 1366 1367 if (!info->finish_realize) { 1368 error_setg(errp, "finish_realize not defined"); 1369 return; 1370 } 1371 1372 info->finish_realize(sphb, errp); 1373 1374 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 1375 } 1376 1377 static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) 1378 { 1379 sPAPRTCETable *tcet; 1380 uint32_t nb_table; 1381 1382 nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; 1383 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, 1384 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); 1385 if (!tcet) { 1386 error_setg(errp, "Unable to create TCE table for %s", 1387 sphb->dtbusname); 1388 return ; 1389 } 1390 1391 /* Register default 32bit DMA window */ 1392 memory_region_add_subregion(&sphb->iommu_root, 0, 1393 spapr_tce_get_iommu(tcet)); 1394 } 1395 1396 static int spapr_phb_children_reset(Object *child, void *opaque) 1397 { 1398 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 1399 1400 if (dev) { 1401 device_reset(dev); 1402 } 1403 1404 return 0; 1405 } 1406 1407 static void spapr_phb_reset(DeviceState *qdev) 1408 { 1409 /* Reset the IOMMU state */ 1410 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 1411 } 1412 1413 static Property spapr_phb_properties[] = { 1414 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), 1415 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), 1416 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), 1417 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), 1418 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, 1419 SPAPR_PCI_MMIO_WIN_SIZE), 1420 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), 1421 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, 1422 SPAPR_PCI_IO_WIN_SIZE), 1423 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, 1424 true), 1425 DEFINE_PROP_END_OF_LIST(), 1426 }; 1427 1428 static const VMStateDescription vmstate_spapr_pci_lsi = { 1429 .name = "spapr_pci/lsi", 1430 .version_id = 1, 1431 .minimum_version_id = 1, 1432 .fields = (VMStateField[]) { 1433 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), 1434 1435 VMSTATE_END_OF_LIST() 1436 }, 1437 }; 1438 1439 static const VMStateDescription vmstate_spapr_pci_msi = { 1440 .name = "spapr_pci/msi", 1441 .version_id = 1, 1442 .minimum_version_id = 1, 1443 .fields = (VMStateField []) { 1444 VMSTATE_UINT32(key, spapr_pci_msi_mig), 1445 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 1446 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 1447 VMSTATE_END_OF_LIST() 1448 }, 1449 }; 1450 1451 static void spapr_pci_pre_save(void *opaque) 1452 { 1453 sPAPRPHBState *sphb = opaque; 1454 GHashTableIter iter; 1455 gpointer key, value; 1456 int i; 1457 1458 if (sphb->msi_devs) { 1459 g_free(sphb->msi_devs); 1460 sphb->msi_devs = NULL; 1461 } 1462 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 1463 if (!sphb->msi_devs_num) { 1464 return; 1465 } 1466 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); 1467 1468 g_hash_table_iter_init(&iter, sphb->msi); 1469 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 1470 sphb->msi_devs[i].key = *(uint32_t *) key; 1471 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 1472 } 1473 } 1474 1475 static int spapr_pci_post_load(void *opaque, int version_id) 1476 { 1477 sPAPRPHBState *sphb = opaque; 1478 gpointer key, value; 1479 int i; 1480 1481 for (i = 0; i < sphb->msi_devs_num; ++i) { 1482 key = g_memdup(&sphb->msi_devs[i].key, 1483 sizeof(sphb->msi_devs[i].key)); 1484 value = g_memdup(&sphb->msi_devs[i].value, 1485 sizeof(sphb->msi_devs[i].value)); 1486 g_hash_table_insert(sphb->msi, key, value); 1487 } 1488 if (sphb->msi_devs) { 1489 g_free(sphb->msi_devs); 1490 sphb->msi_devs = NULL; 1491 } 1492 sphb->msi_devs_num = 0; 1493 1494 return 0; 1495 } 1496 1497 static const VMStateDescription vmstate_spapr_pci = { 1498 .name = "spapr_pci", 1499 .version_id = 2, 1500 .minimum_version_id = 2, 1501 .pre_save = spapr_pci_pre_save, 1502 .post_load = spapr_pci_post_load, 1503 .fields = (VMStateField[]) { 1504 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), 1505 VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), 1506 VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), 1507 VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), 1508 VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), 1509 VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), 1510 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, 1511 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 1512 VMSTATE_INT32(msi_devs_num, sPAPRPHBState), 1513 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, 1514 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 1515 VMSTATE_END_OF_LIST() 1516 }, 1517 }; 1518 1519 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 1520 PCIBus *rootbus) 1521 { 1522 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 1523 1524 return sphb->dtbusname; 1525 } 1526 1527 static void spapr_phb_class_init(ObjectClass *klass, void *data) 1528 { 1529 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 1530 DeviceClass *dc = DEVICE_CLASS(klass); 1531 sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); 1532 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 1533 1534 hc->root_bus_path = spapr_phb_root_bus_path; 1535 dc->realize = spapr_phb_realize; 1536 dc->props = spapr_phb_properties; 1537 dc->reset = spapr_phb_reset; 1538 dc->vmsd = &vmstate_spapr_pci; 1539 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1540 dc->cannot_instantiate_with_device_add_yet = false; 1541 spc->finish_realize = spapr_phb_finish_realize; 1542 hp->plug = spapr_phb_hot_plug_child; 1543 hp->unplug = spapr_phb_hot_unplug_child; 1544 } 1545 1546 static const TypeInfo spapr_phb_info = { 1547 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 1548 .parent = TYPE_PCI_HOST_BRIDGE, 1549 .instance_size = sizeof(sPAPRPHBState), 1550 .class_init = spapr_phb_class_init, 1551 .class_size = sizeof(sPAPRPHBClass), 1552 .interfaces = (InterfaceInfo[]) { 1553 { TYPE_HOTPLUG_HANDLER }, 1554 { } 1555 } 1556 }; 1557 1558 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) 1559 { 1560 DeviceState *dev; 1561 1562 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 1563 qdev_prop_set_uint32(dev, "index", index); 1564 qdev_init_nofail(dev); 1565 1566 return PCI_HOST_BRIDGE(dev); 1567 } 1568 1569 typedef struct sPAPRFDT { 1570 void *fdt; 1571 int node_off; 1572 sPAPRPHBState *sphb; 1573 } sPAPRFDT; 1574 1575 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, 1576 void *opaque) 1577 { 1578 PCIBus *sec_bus; 1579 sPAPRFDT *p = opaque; 1580 int offset; 1581 sPAPRFDT s_fdt; 1582 uint32_t drc_index = spapr_phb_get_pci_drc_index(p->sphb, pdev); 1583 1584 offset = spapr_create_pci_child_dt(p->sphb, pdev, 1585 drc_index, NULL, 1586 p->fdt, p->node_off); 1587 if (!offset) { 1588 error_report("Failed to create pci child device tree node"); 1589 return; 1590 } 1591 1592 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1593 PCI_HEADER_TYPE_BRIDGE)) { 1594 return; 1595 } 1596 1597 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1598 if (!sec_bus) { 1599 return; 1600 } 1601 1602 s_fdt.fdt = p->fdt; 1603 s_fdt.node_off = offset; 1604 s_fdt.sphb = p->sphb; 1605 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1606 spapr_populate_pci_devices_dt, 1607 &s_fdt); 1608 } 1609 1610 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 1611 void *opaque) 1612 { 1613 unsigned int *bus_no = opaque; 1614 unsigned int primary = *bus_no; 1615 unsigned int subordinate = 0xff; 1616 PCIBus *sec_bus = NULL; 1617 1618 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1619 PCI_HEADER_TYPE_BRIDGE)) { 1620 return; 1621 } 1622 1623 (*bus_no)++; 1624 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 1625 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 1626 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1627 1628 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1629 if (!sec_bus) { 1630 return; 1631 } 1632 1633 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 1634 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1635 spapr_phb_pci_enumerate_bridge, bus_no); 1636 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1637 } 1638 1639 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) 1640 { 1641 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1642 unsigned int bus_no = 0; 1643 1644 pci_for_each_device(bus, pci_bus_num(bus), 1645 spapr_phb_pci_enumerate_bridge, 1646 &bus_no); 1647 1648 } 1649 1650 int spapr_populate_pci_dt(sPAPRPHBState *phb, 1651 uint32_t xics_phandle, 1652 void *fdt) 1653 { 1654 int bus_off, i, j, ret; 1655 char nodename[FDT_NAME_MAX]; 1656 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 1657 const uint64_t mmiosize = memory_region_size(&phb->memwindow); 1658 const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; 1659 const uint64_t w32size = MIN(w32max, mmiosize); 1660 const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; 1661 struct { 1662 uint32_t hi; 1663 uint64_t child; 1664 uint64_t parent; 1665 uint64_t size; 1666 } QEMU_PACKED ranges[] = { 1667 { 1668 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 1669 cpu_to_be64(phb->io_win_addr), 1670 cpu_to_be64(memory_region_size(&phb->iospace)), 1671 }, 1672 { 1673 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 1674 cpu_to_be64(phb->mem_win_addr), 1675 cpu_to_be64(w32size), 1676 }, 1677 { 1678 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), 1679 cpu_to_be64(phb->mem_win_addr + w32size), 1680 cpu_to_be64(w64size) 1681 }, 1682 }; 1683 const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); 1684 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 1685 uint32_t interrupt_map_mask[] = { 1686 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 1687 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 1688 sPAPRTCETable *tcet; 1689 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1690 sPAPRFDT s_fdt; 1691 1692 /* Start populating the FDT */ 1693 snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); 1694 bus_off = fdt_add_subnode(fdt, 0, nodename); 1695 if (bus_off < 0) { 1696 return bus_off; 1697 } 1698 1699 /* Write PHB properties */ 1700 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 1701 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 1702 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); 1703 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); 1704 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 1705 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 1706 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 1707 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 1708 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 1709 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 1710 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); 1711 1712 /* Build the interrupt-map, this must matches what is done 1713 * in pci_spapr_map_irq 1714 */ 1715 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 1716 &interrupt_map_mask, sizeof(interrupt_map_mask))); 1717 for (i = 0; i < PCI_SLOT_MAX; i++) { 1718 for (j = 0; j < PCI_NUM_PINS; j++) { 1719 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 1720 int lsi_num = pci_spapr_swizzle(i, j); 1721 1722 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 1723 irqmap[1] = 0; 1724 irqmap[2] = 0; 1725 irqmap[3] = cpu_to_be32(j+1); 1726 irqmap[4] = cpu_to_be32(xics_phandle); 1727 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); 1728 irqmap[6] = cpu_to_be32(0x8); 1729 } 1730 } 1731 /* Write interrupt map */ 1732 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 1733 sizeof(interrupt_map))); 1734 1735 tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); 1736 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 1737 tcet->liobn, tcet->bus_offset, 1738 tcet->nb_table << tcet->page_shift); 1739 1740 /* Walk the bridges and program the bus numbers*/ 1741 spapr_phb_pci_enumerate(phb); 1742 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 1743 1744 /* Populate tree nodes with PCI devices attached */ 1745 s_fdt.fdt = fdt; 1746 s_fdt.node_off = bus_off; 1747 s_fdt.sphb = phb; 1748 pci_for_each_device(bus, pci_bus_num(bus), 1749 spapr_populate_pci_devices_dt, 1750 &s_fdt); 1751 1752 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), 1753 SPAPR_DR_CONNECTOR_TYPE_PCI); 1754 if (ret) { 1755 return ret; 1756 } 1757 1758 return 0; 1759 } 1760 1761 void spapr_pci_rtas_init(void) 1762 { 1763 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 1764 rtas_read_pci_config); 1765 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 1766 rtas_write_pci_config); 1767 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 1768 rtas_ibm_read_pci_config); 1769 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 1770 rtas_ibm_write_pci_config); 1771 if (msi_supported) { 1772 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 1773 "ibm,query-interrupt-source-number", 1774 rtas_ibm_query_interrupt_source_number); 1775 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 1776 rtas_ibm_change_msi); 1777 } 1778 1779 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 1780 "ibm,set-eeh-option", 1781 rtas_ibm_set_eeh_option); 1782 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 1783 "ibm,get-config-addr-info2", 1784 rtas_ibm_get_config_addr_info2); 1785 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 1786 "ibm,read-slot-reset-state2", 1787 rtas_ibm_read_slot_reset_state2); 1788 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 1789 "ibm,set-slot-reset", 1790 rtas_ibm_set_slot_reset); 1791 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 1792 "ibm,configure-pe", 1793 rtas_ibm_configure_pe); 1794 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 1795 "ibm,slot-error-detail", 1796 rtas_ibm_slot_error_detail); 1797 } 1798 1799 static void spapr_pci_register_types(void) 1800 { 1801 type_register_static(&spapr_phb_info); 1802 } 1803 1804 type_init(spapr_pci_register_types) 1805 1806 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 1807 { 1808 bool be = *(bool *)opaque; 1809 1810 if (object_dynamic_cast(OBJECT(dev), "VGA") 1811 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 1812 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 1813 &error_abort); 1814 } 1815 return 0; 1816 } 1817 1818 void spapr_pci_switch_vga(bool big_endian) 1819 { 1820 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1821 sPAPRPHBState *sphb; 1822 1823 /* 1824 * For backward compatibility with existing guests, we switch 1825 * the endianness of the VGA controller when changing the guest 1826 * interrupt mode 1827 */ 1828 QLIST_FOREACH(sphb, &spapr->phbs, list) { 1829 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 1830 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 1831 &big_endian); 1832 } 1833 } 1834