1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "cpu.h" 29 #include "hw/hw.h" 30 #include "hw/sysbus.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/msi.h" 33 #include "hw/pci/msix.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/ppc/spapr.h" 36 #include "hw/pci-host/spapr.h" 37 #include "exec/address-spaces.h" 38 #include "exec/ram_addr.h" 39 #include <libfdt.h> 40 #include "trace.h" 41 #include "qemu/error-report.h" 42 #include "qapi/qmp/qerror.h" 43 44 #include "hw/pci/pci_bridge.h" 45 #include "hw/pci/pci_bus.h" 46 #include "hw/pci/pci_ids.h" 47 #include "hw/ppc/spapr_drc.h" 48 #include "sysemu/device_tree.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/hostmem.h" 51 #include "sysemu/numa.h" 52 53 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 54 #define RTAS_QUERY_FN 0 55 #define RTAS_CHANGE_FN 1 56 #define RTAS_RESET_FN 2 57 #define RTAS_CHANGE_MSI_FN 3 58 #define RTAS_CHANGE_MSIX_FN 4 59 60 /* Interrupt types to return on RTAS_CHANGE_* */ 61 #define RTAS_TYPE_MSI 1 62 #define RTAS_TYPE_MSIX 2 63 64 #define FDT_NAME_MAX 128 65 66 #define _FDT(exp) \ 67 do { \ 68 int ret = (exp); \ 69 if (ret < 0) { \ 70 return ret; \ 71 } \ 72 } while (0) 73 74 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) 75 { 76 sPAPRPHBState *sphb; 77 78 QLIST_FOREACH(sphb, &spapr->phbs, list) { 79 if (sphb->buid != buid) { 80 continue; 81 } 82 return sphb; 83 } 84 85 return NULL; 86 } 87 88 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 89 uint32_t config_addr) 90 { 91 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); 92 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 93 int bus_num = (config_addr >> 16) & 0xFF; 94 int devfn = (config_addr >> 8) & 0xFF; 95 96 if (!phb) { 97 return NULL; 98 } 99 100 return pci_find_device(phb->bus, bus_num, devfn); 101 } 102 103 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 104 { 105 /* This handles the encoding of extended config space addresses */ 106 return ((arg >> 20) & 0xf00) | (arg & 0xff); 107 } 108 109 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, 110 uint32_t addr, uint32_t size, 111 target_ulong rets) 112 { 113 PCIDevice *pci_dev; 114 uint32_t val; 115 116 if ((size != 1) && (size != 2) && (size != 4)) { 117 /* access must be 1, 2 or 4 bytes */ 118 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 119 return; 120 } 121 122 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 123 addr = rtas_pci_cfgaddr(addr); 124 125 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 126 /* Access must be to a valid device, within bounds and 127 * naturally aligned */ 128 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 129 return; 130 } 131 132 val = pci_host_config_read_common(pci_dev, addr, 133 pci_config_size(pci_dev), size); 134 135 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 136 rtas_st(rets, 1, val); 137 } 138 139 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 140 uint32_t token, uint32_t nargs, 141 target_ulong args, 142 uint32_t nret, target_ulong rets) 143 { 144 uint64_t buid; 145 uint32_t size, addr; 146 147 if ((nargs != 4) || (nret != 2)) { 148 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 149 return; 150 } 151 152 buid = rtas_ldq(args, 1); 153 size = rtas_ld(args, 3); 154 addr = rtas_ld(args, 0); 155 156 finish_read_pci_config(spapr, buid, addr, size, rets); 157 } 158 159 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 160 uint32_t token, uint32_t nargs, 161 target_ulong args, 162 uint32_t nret, target_ulong rets) 163 { 164 uint32_t size, addr; 165 166 if ((nargs != 2) || (nret != 2)) { 167 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 168 return; 169 } 170 171 size = rtas_ld(args, 1); 172 addr = rtas_ld(args, 0); 173 174 finish_read_pci_config(spapr, 0, addr, size, rets); 175 } 176 177 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, 178 uint32_t addr, uint32_t size, 179 uint32_t val, target_ulong rets) 180 { 181 PCIDevice *pci_dev; 182 183 if ((size != 1) && (size != 2) && (size != 4)) { 184 /* access must be 1, 2 or 4 bytes */ 185 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 186 return; 187 } 188 189 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 190 addr = rtas_pci_cfgaddr(addr); 191 192 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 193 /* Access must be to a valid device, within bounds and 194 * naturally aligned */ 195 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 196 return; 197 } 198 199 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 200 val, size); 201 202 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 203 } 204 205 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 206 uint32_t token, uint32_t nargs, 207 target_ulong args, 208 uint32_t nret, target_ulong rets) 209 { 210 uint64_t buid; 211 uint32_t val, size, addr; 212 213 if ((nargs != 5) || (nret != 1)) { 214 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 215 return; 216 } 217 218 buid = rtas_ldq(args, 1); 219 val = rtas_ld(args, 4); 220 size = rtas_ld(args, 3); 221 addr = rtas_ld(args, 0); 222 223 finish_write_pci_config(spapr, buid, addr, size, val, rets); 224 } 225 226 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 227 uint32_t token, uint32_t nargs, 228 target_ulong args, 229 uint32_t nret, target_ulong rets) 230 { 231 uint32_t val, size, addr; 232 233 if ((nargs != 3) || (nret != 1)) { 234 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 235 return; 236 } 237 238 239 val = rtas_ld(args, 2); 240 size = rtas_ld(args, 1); 241 addr = rtas_ld(args, 0); 242 243 finish_write_pci_config(spapr, 0, addr, size, val, rets); 244 } 245 246 /* 247 * Set MSI/MSIX message data. 248 * This is required for msi_notify()/msix_notify() which 249 * will write at the addresses via spapr_msi_write(). 250 * 251 * If hwaddr == 0, all entries will have .data == first_irq i.e. 252 * table will be reset. 253 */ 254 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 255 unsigned first_irq, unsigned req_num) 256 { 257 unsigned i; 258 MSIMessage msg = { .address = addr, .data = first_irq }; 259 260 if (!msix) { 261 msi_set_message(pdev, msg); 262 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 263 return; 264 } 265 266 for (i = 0; i < req_num; ++i) { 267 msix_set_message(pdev, i, msg); 268 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 269 if (addr) { 270 ++msg.data; 271 } 272 } 273 } 274 275 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 276 uint32_t token, uint32_t nargs, 277 target_ulong args, uint32_t nret, 278 target_ulong rets) 279 { 280 uint32_t config_addr = rtas_ld(args, 0); 281 uint64_t buid = rtas_ldq(args, 1); 282 unsigned int func = rtas_ld(args, 3); 283 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 284 unsigned int seq_num = rtas_ld(args, 5); 285 unsigned int ret_intr_type; 286 unsigned int irq, max_irqs = 0; 287 sPAPRPHBState *phb = NULL; 288 PCIDevice *pdev = NULL; 289 spapr_pci_msi *msi; 290 int *config_addr_key; 291 Error *err = NULL; 292 293 switch (func) { 294 case RTAS_CHANGE_MSI_FN: 295 case RTAS_CHANGE_FN: 296 ret_intr_type = RTAS_TYPE_MSI; 297 break; 298 case RTAS_CHANGE_MSIX_FN: 299 ret_intr_type = RTAS_TYPE_MSIX; 300 break; 301 default: 302 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 303 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 304 return; 305 } 306 307 /* Fins sPAPRPHBState */ 308 phb = spapr_pci_find_phb(spapr, buid); 309 if (phb) { 310 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 311 } 312 if (!phb || !pdev) { 313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 314 return; 315 } 316 317 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 318 319 /* Releasing MSIs */ 320 if (!req_num) { 321 if (!msi) { 322 trace_spapr_pci_msi("Releasing wrong config", config_addr); 323 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 324 return; 325 } 326 327 spapr_ics_free(spapr->ics, msi->first_irq, msi->num); 328 if (msi_present(pdev)) { 329 spapr_msi_setmsg(pdev, 0, false, 0, 0); 330 } 331 if (msix_present(pdev)) { 332 spapr_msi_setmsg(pdev, 0, true, 0, 0); 333 } 334 g_hash_table_remove(phb->msi, &config_addr); 335 336 trace_spapr_pci_msi("Released MSIs", config_addr); 337 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 338 rtas_st(rets, 1, 0); 339 return; 340 } 341 342 /* Enabling MSI */ 343 344 /* Check if the device supports as many IRQs as requested */ 345 if (ret_intr_type == RTAS_TYPE_MSI) { 346 max_irqs = msi_nr_vectors_allocated(pdev); 347 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 348 max_irqs = pdev->msix_entries_nr; 349 } 350 if (!max_irqs) { 351 error_report("Requested interrupt type %d is not enabled for device %x", 352 ret_intr_type, config_addr); 353 rtas_st(rets, 0, -1); /* Hardware error */ 354 return; 355 } 356 /* Correct the number if the guest asked for too many */ 357 if (req_num > max_irqs) { 358 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 359 req_num = max_irqs; 360 irq = 0; /* to avoid misleading trace */ 361 goto out; 362 } 363 364 /* Allocate MSIs */ 365 irq = spapr_ics_alloc_block(spapr->ics, req_num, false, 366 ret_intr_type == RTAS_TYPE_MSI, &err); 367 if (err) { 368 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 369 config_addr); 370 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 371 return; 372 } 373 374 /* Release previous MSIs */ 375 if (msi) { 376 spapr_ics_free(spapr->ics, msi->first_irq, msi->num); 377 g_hash_table_remove(phb->msi, &config_addr); 378 } 379 380 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 381 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 382 irq, req_num); 383 384 /* Add MSI device to cache */ 385 msi = g_new(spapr_pci_msi, 1); 386 msi->first_irq = irq; 387 msi->num = req_num; 388 config_addr_key = g_new(int, 1); 389 *config_addr_key = config_addr; 390 g_hash_table_insert(phb->msi, config_addr_key, msi); 391 392 out: 393 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 394 rtas_st(rets, 1, req_num); 395 rtas_st(rets, 2, ++seq_num); 396 if (nret > 3) { 397 rtas_st(rets, 3, ret_intr_type); 398 } 399 400 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 401 } 402 403 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 404 sPAPRMachineState *spapr, 405 uint32_t token, 406 uint32_t nargs, 407 target_ulong args, 408 uint32_t nret, 409 target_ulong rets) 410 { 411 uint32_t config_addr = rtas_ld(args, 0); 412 uint64_t buid = rtas_ldq(args, 1); 413 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 414 sPAPRPHBState *phb = NULL; 415 PCIDevice *pdev = NULL; 416 spapr_pci_msi *msi; 417 418 /* Find sPAPRPHBState */ 419 phb = spapr_pci_find_phb(spapr, buid); 420 if (phb) { 421 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 422 } 423 if (!phb || !pdev) { 424 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 425 return; 426 } 427 428 /* Find device descriptor and start IRQ */ 429 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 430 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 431 trace_spapr_pci_msi("Failed to return vector", config_addr); 432 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 433 return; 434 } 435 intr_src_num = msi->first_irq + ioa_intr_num; 436 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 437 intr_src_num); 438 439 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 440 rtas_st(rets, 1, intr_src_num); 441 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 442 } 443 444 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 445 sPAPRMachineState *spapr, 446 uint32_t token, uint32_t nargs, 447 target_ulong args, uint32_t nret, 448 target_ulong rets) 449 { 450 sPAPRPHBState *sphb; 451 uint32_t addr, option; 452 uint64_t buid; 453 int ret; 454 455 if ((nargs != 4) || (nret != 1)) { 456 goto param_error_exit; 457 } 458 459 buid = rtas_ldq(args, 1); 460 addr = rtas_ld(args, 0); 461 option = rtas_ld(args, 3); 462 463 sphb = spapr_pci_find_phb(spapr, buid); 464 if (!sphb) { 465 goto param_error_exit; 466 } 467 468 if (!spapr_phb_eeh_available(sphb)) { 469 goto param_error_exit; 470 } 471 472 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 473 rtas_st(rets, 0, ret); 474 return; 475 476 param_error_exit: 477 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 478 } 479 480 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 481 sPAPRMachineState *spapr, 482 uint32_t token, uint32_t nargs, 483 target_ulong args, uint32_t nret, 484 target_ulong rets) 485 { 486 sPAPRPHBState *sphb; 487 PCIDevice *pdev; 488 uint32_t addr, option; 489 uint64_t buid; 490 491 if ((nargs != 4) || (nret != 2)) { 492 goto param_error_exit; 493 } 494 495 buid = rtas_ldq(args, 1); 496 sphb = spapr_pci_find_phb(spapr, buid); 497 if (!sphb) { 498 goto param_error_exit; 499 } 500 501 if (!spapr_phb_eeh_available(sphb)) { 502 goto param_error_exit; 503 } 504 505 /* 506 * We always have PE address of form "00BB0001". "BB" 507 * represents the bus number of PE's primary bus. 508 */ 509 option = rtas_ld(args, 3); 510 switch (option) { 511 case RTAS_GET_PE_ADDR: 512 addr = rtas_ld(args, 0); 513 pdev = spapr_pci_find_dev(spapr, buid, addr); 514 if (!pdev) { 515 goto param_error_exit; 516 } 517 518 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); 519 break; 520 case RTAS_GET_PE_MODE: 521 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 522 break; 523 default: 524 goto param_error_exit; 525 } 526 527 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 528 return; 529 530 param_error_exit: 531 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 532 } 533 534 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 535 sPAPRMachineState *spapr, 536 uint32_t token, uint32_t nargs, 537 target_ulong args, uint32_t nret, 538 target_ulong rets) 539 { 540 sPAPRPHBState *sphb; 541 uint64_t buid; 542 int state, ret; 543 544 if ((nargs != 3) || (nret != 4 && nret != 5)) { 545 goto param_error_exit; 546 } 547 548 buid = rtas_ldq(args, 1); 549 sphb = spapr_pci_find_phb(spapr, buid); 550 if (!sphb) { 551 goto param_error_exit; 552 } 553 554 if (!spapr_phb_eeh_available(sphb)) { 555 goto param_error_exit; 556 } 557 558 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 559 rtas_st(rets, 0, ret); 560 if (ret != RTAS_OUT_SUCCESS) { 561 return; 562 } 563 564 rtas_st(rets, 1, state); 565 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 566 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 567 if (nret >= 5) { 568 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 569 } 570 return; 571 572 param_error_exit: 573 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 574 } 575 576 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 577 sPAPRMachineState *spapr, 578 uint32_t token, uint32_t nargs, 579 target_ulong args, uint32_t nret, 580 target_ulong rets) 581 { 582 sPAPRPHBState *sphb; 583 uint32_t option; 584 uint64_t buid; 585 int ret; 586 587 if ((nargs != 4) || (nret != 1)) { 588 goto param_error_exit; 589 } 590 591 buid = rtas_ldq(args, 1); 592 option = rtas_ld(args, 3); 593 sphb = spapr_pci_find_phb(spapr, buid); 594 if (!sphb) { 595 goto param_error_exit; 596 } 597 598 if (!spapr_phb_eeh_available(sphb)) { 599 goto param_error_exit; 600 } 601 602 ret = spapr_phb_vfio_eeh_reset(sphb, option); 603 rtas_st(rets, 0, ret); 604 return; 605 606 param_error_exit: 607 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 608 } 609 610 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 611 sPAPRMachineState *spapr, 612 uint32_t token, uint32_t nargs, 613 target_ulong args, uint32_t nret, 614 target_ulong rets) 615 { 616 sPAPRPHBState *sphb; 617 uint64_t buid; 618 int ret; 619 620 if ((nargs != 3) || (nret != 1)) { 621 goto param_error_exit; 622 } 623 624 buid = rtas_ldq(args, 1); 625 sphb = spapr_pci_find_phb(spapr, buid); 626 if (!sphb) { 627 goto param_error_exit; 628 } 629 630 if (!spapr_phb_eeh_available(sphb)) { 631 goto param_error_exit; 632 } 633 634 ret = spapr_phb_vfio_eeh_configure(sphb); 635 rtas_st(rets, 0, ret); 636 return; 637 638 param_error_exit: 639 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 640 } 641 642 /* To support it later */ 643 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 644 sPAPRMachineState *spapr, 645 uint32_t token, uint32_t nargs, 646 target_ulong args, uint32_t nret, 647 target_ulong rets) 648 { 649 sPAPRPHBState *sphb; 650 int option; 651 uint64_t buid; 652 653 if ((nargs != 8) || (nret != 1)) { 654 goto param_error_exit; 655 } 656 657 buid = rtas_ldq(args, 1); 658 sphb = spapr_pci_find_phb(spapr, buid); 659 if (!sphb) { 660 goto param_error_exit; 661 } 662 663 if (!spapr_phb_eeh_available(sphb)) { 664 goto param_error_exit; 665 } 666 667 option = rtas_ld(args, 7); 668 switch (option) { 669 case RTAS_SLOT_TEMP_ERR_LOG: 670 case RTAS_SLOT_PERM_ERR_LOG: 671 break; 672 default: 673 goto param_error_exit; 674 } 675 676 /* We don't have error log yet */ 677 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 678 return; 679 680 param_error_exit: 681 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 682 } 683 684 static int pci_spapr_swizzle(int slot, int pin) 685 { 686 return (slot + pin) % PCI_NUM_PINS; 687 } 688 689 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) 690 { 691 /* 692 * Here we need to convert pci_dev + irq_num to some unique value 693 * which is less than number of IRQs on the specific bus (4). We 694 * use standard PCI swizzling, that is (slot number + pin number) 695 * % 4. 696 */ 697 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); 698 } 699 700 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 701 { 702 /* 703 * Here we use the number returned by pci_spapr_map_irq to find a 704 * corresponding qemu_irq. 705 */ 706 sPAPRPHBState *phb = opaque; 707 708 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 709 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 710 } 711 712 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 713 { 714 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 715 PCIINTxRoute route; 716 717 route.mode = PCI_INTX_ENABLED; 718 route.irq = sphb->lsi_table[pin].irq; 719 720 return route; 721 } 722 723 /* 724 * MSI/MSIX memory region implementation. 725 * The handler handles both MSI and MSIX. 726 * For MSI-X, the vector number is encoded as a part of the address, 727 * data is set to 0. 728 * For MSI, the vector number is encoded in least bits in data. 729 */ 730 static void spapr_msi_write(void *opaque, hwaddr addr, 731 uint64_t data, unsigned size) 732 { 733 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 734 uint32_t irq = data; 735 736 trace_spapr_pci_msi_write(addr, data, irq); 737 738 qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), irq)); 739 } 740 741 static const MemoryRegionOps spapr_msi_ops = { 742 /* There is no .read as the read result is undefined by PCI spec */ 743 .read = NULL, 744 .write = spapr_msi_write, 745 .endianness = DEVICE_LITTLE_ENDIAN 746 }; 747 748 /* 749 * PHB PCI device 750 */ 751 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 752 { 753 sPAPRPHBState *phb = opaque; 754 755 return &phb->iommu_as; 756 } 757 758 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 759 { 760 char *path = NULL, *buf = NULL, *host = NULL; 761 762 /* Get the PCI VFIO host id */ 763 host = object_property_get_str(OBJECT(pdev), "host", NULL); 764 if (!host) { 765 goto err_out; 766 } 767 768 /* Construct the path of the file that will give us the DT location */ 769 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 770 g_free(host); 771 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 772 goto err_out; 773 } 774 g_free(path); 775 776 /* Construct and read from host device tree the loc-code */ 777 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 778 g_free(buf); 779 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 780 goto err_out; 781 } 782 return buf; 783 784 err_out: 785 g_free(path); 786 return NULL; 787 } 788 789 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 790 { 791 char *buf; 792 const char *devtype = "qemu"; 793 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 794 795 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 796 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 797 if (buf) { 798 return buf; 799 } 800 devtype = "vfio"; 801 } 802 /* 803 * For emulated devices and VFIO-failure case, make up 804 * the loc-code. 805 */ 806 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 807 devtype, pdev->name, sphb->index, busnr, 808 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 809 return buf; 810 } 811 812 /* Macros to operate with address in OF binding to PCI */ 813 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 814 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 815 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 816 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 817 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 818 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 819 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 820 #define b_fff(x) b_x((x), 8, 3) /* function number */ 821 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 822 823 /* for 'reg'/'assigned-addresses' OF properties */ 824 #define RESOURCE_CELLS_SIZE 2 825 #define RESOURCE_CELLS_ADDRESS 3 826 827 typedef struct ResourceFields { 828 uint32_t phys_hi; 829 uint32_t phys_mid; 830 uint32_t phys_lo; 831 uint32_t size_hi; 832 uint32_t size_lo; 833 } QEMU_PACKED ResourceFields; 834 835 typedef struct ResourceProps { 836 ResourceFields reg[8]; 837 ResourceFields assigned[7]; 838 uint32_t reg_len; 839 uint32_t assigned_len; 840 } ResourceProps; 841 842 /* fill in the 'reg'/'assigned-resources' OF properties for 843 * a PCI device. 'reg' describes resource requirements for a 844 * device's IO/MEM regions, 'assigned-addresses' describes the 845 * actual resource assignments. 846 * 847 * the properties are arrays of ('phys-addr', 'size') pairs describing 848 * the addressable regions of the PCI device, where 'phys-addr' is a 849 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 850 * (phys.hi, phys.mid, phys.lo), and 'size' is a 851 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 852 * 853 * phys.hi = 0xYYXXXXZZ, where: 854 * 0xYY = npt000ss 855 * ||| | 856 * ||| +-- space code 857 * ||| | 858 * ||| + 00 if configuration space 859 * ||| + 01 if IO region, 860 * ||| + 10 if 32-bit MEM region 861 * ||| + 11 if 64-bit MEM region 862 * ||| 863 * ||+------ for non-relocatable IO: 1 if aliased 864 * || for relocatable IO: 1 if below 64KB 865 * || for MEM: 1 if below 1MB 866 * |+------- 1 if region is prefetchable 867 * +-------- 1 if region is non-relocatable 868 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 869 * bits respectively 870 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 871 * to the region 872 * 873 * phys.mid and phys.lo correspond respectively to the hi/lo portions 874 * of the actual address of the region. 875 * 876 * how the phys-addr/size values are used differ slightly between 877 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 878 * an additional description for the config space region of the 879 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 880 * to describe the region as relocatable, with an address-mapping 881 * that corresponds directly to the PHB's address space for the 882 * resource. 'assigned-addresses' always has n=1 set with an absolute 883 * address assigned for the resource. in general, 'assigned-addresses' 884 * won't be populated, since addresses for PCI devices are generally 885 * unmapped initially and left to the guest to assign. 886 * 887 * note also that addresses defined in these properties are, at least 888 * for PAPR guests, relative to the PHBs IO/MEM windows, and 889 * correspond directly to the addresses in the BARs. 890 * 891 * in accordance with PCI Bus Binding to Open Firmware, 892 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 893 * Appendix C. 894 */ 895 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 896 { 897 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 898 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 899 b_ddddd(PCI_SLOT(d->devfn)) | 900 b_fff(PCI_FUNC(d->devfn))); 901 ResourceFields *reg, *assigned; 902 int i, reg_idx = 0, assigned_idx = 0; 903 904 /* config space region */ 905 reg = &rp->reg[reg_idx++]; 906 reg->phys_hi = cpu_to_be32(dev_id); 907 reg->phys_mid = 0; 908 reg->phys_lo = 0; 909 reg->size_hi = 0; 910 reg->size_lo = 0; 911 912 for (i = 0; i < PCI_NUM_REGIONS; i++) { 913 if (!d->io_regions[i].size) { 914 continue; 915 } 916 917 reg = &rp->reg[reg_idx++]; 918 919 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 920 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 921 reg->phys_hi |= cpu_to_be32(b_ss(1)); 922 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 923 reg->phys_hi |= cpu_to_be32(b_ss(3)); 924 } else { 925 reg->phys_hi |= cpu_to_be32(b_ss(2)); 926 } 927 reg->phys_mid = 0; 928 reg->phys_lo = 0; 929 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 930 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 931 932 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 933 continue; 934 } 935 936 assigned = &rp->assigned[assigned_idx++]; 937 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); 938 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 939 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 940 assigned->size_hi = reg->size_hi; 941 assigned->size_lo = reg->size_lo; 942 } 943 944 rp->reg_len = reg_idx * sizeof(ResourceFields); 945 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 946 } 947 948 typedef struct PCIClass PCIClass; 949 typedef struct PCISubClass PCISubClass; 950 typedef struct PCIIFace PCIIFace; 951 952 struct PCIIFace { 953 int iface; 954 const char *name; 955 }; 956 957 struct PCISubClass { 958 int subclass; 959 const char *name; 960 const PCIIFace *iface; 961 }; 962 963 struct PCIClass { 964 const char *name; 965 const PCISubClass *subc; 966 }; 967 968 static const PCISubClass undef_subclass[] = { 969 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 970 { 0xFF, NULL, NULL }, 971 }; 972 973 static const PCISubClass mass_subclass[] = { 974 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 975 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 976 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 977 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 978 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 979 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 980 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 981 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 982 { 0xFF, NULL, NULL }, 983 }; 984 985 static const PCISubClass net_subclass[] = { 986 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 987 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 988 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 989 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 990 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 991 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 992 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 993 { 0xFF, NULL, NULL }, 994 }; 995 996 static const PCISubClass displ_subclass[] = { 997 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 998 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 999 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 1000 { 0xFF, NULL, NULL }, 1001 }; 1002 1003 static const PCISubClass media_subclass[] = { 1004 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 1005 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 1006 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 1007 { 0xFF, NULL, NULL }, 1008 }; 1009 1010 static const PCISubClass mem_subclass[] = { 1011 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1012 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1013 { 0xFF, NULL, NULL }, 1014 }; 1015 1016 static const PCISubClass bridg_subclass[] = { 1017 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1018 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1019 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1020 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1021 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1022 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1023 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1024 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1025 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1026 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1027 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1028 { 0xFF, NULL, NULL }, 1029 }; 1030 1031 static const PCISubClass comm_subclass[] = { 1032 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1033 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1034 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1035 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1036 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1037 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1038 { 0xFF, NULL, NULL, }, 1039 }; 1040 1041 static const PCIIFace pic_iface[] = { 1042 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1043 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1044 { 0xFF, NULL }, 1045 }; 1046 1047 static const PCISubClass sys_subclass[] = { 1048 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1049 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1050 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1051 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1052 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1053 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1054 { 0xFF, NULL, NULL }, 1055 }; 1056 1057 static const PCISubClass inp_subclass[] = { 1058 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1059 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1060 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1061 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1062 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1063 { 0xFF, NULL, NULL }, 1064 }; 1065 1066 static const PCISubClass dock_subclass[] = { 1067 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1068 { 0xFF, NULL, NULL }, 1069 }; 1070 1071 static const PCISubClass cpu_subclass[] = { 1072 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1073 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1074 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1075 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1076 { 0xFF, NULL, NULL }, 1077 }; 1078 1079 static const PCIIFace usb_iface[] = { 1080 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1081 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1082 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1083 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1084 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1085 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1086 { 0xFF, NULL }, 1087 }; 1088 1089 static const PCISubClass ser_subclass[] = { 1090 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1091 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1092 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1093 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1094 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1095 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1096 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1097 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1098 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1099 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1100 { 0xFF, NULL, NULL }, 1101 }; 1102 1103 static const PCISubClass wrl_subclass[] = { 1104 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1105 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1106 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1107 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1108 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1109 { 0xFF, NULL, NULL }, 1110 }; 1111 1112 static const PCISubClass sat_subclass[] = { 1113 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1114 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1115 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1116 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1117 { 0xFF, NULL, NULL }, 1118 }; 1119 1120 static const PCISubClass crypt_subclass[] = { 1121 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1122 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1123 "entertainment-encryption", NULL }, 1124 { 0xFF, NULL, NULL }, 1125 }; 1126 1127 static const PCISubClass spc_subclass[] = { 1128 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1129 { PCI_CLASS_SP_PERF, "counter", NULL }, 1130 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1131 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1132 { 0xFF, NULL, NULL }, 1133 }; 1134 1135 static const PCIClass pci_classes[] = { 1136 { "legacy-device", undef_subclass }, 1137 { "mass-storage", mass_subclass }, 1138 { "network", net_subclass }, 1139 { "display", displ_subclass, }, 1140 { "multimedia-device", media_subclass }, 1141 { "memory-controller", mem_subclass }, 1142 { "unknown-bridge", bridg_subclass }, 1143 { "communication-controller", comm_subclass}, 1144 { "system-peripheral", sys_subclass }, 1145 { "input-controller", inp_subclass }, 1146 { "docking-station", dock_subclass }, 1147 { "cpu", cpu_subclass }, 1148 { "serial-bus", ser_subclass }, 1149 { "wireless-controller", wrl_subclass }, 1150 { "intelligent-io", NULL }, 1151 { "satellite-device", sat_subclass }, 1152 { "encryption", crypt_subclass }, 1153 { "data-processing-controller", spc_subclass }, 1154 }; 1155 1156 static const char *pci_find_device_name(uint8_t class, uint8_t subclass, 1157 uint8_t iface) 1158 { 1159 const PCIClass *pclass; 1160 const PCISubClass *psubclass; 1161 const PCIIFace *piface; 1162 const char *name; 1163 1164 if (class >= ARRAY_SIZE(pci_classes)) { 1165 return "pci"; 1166 } 1167 1168 pclass = pci_classes + class; 1169 name = pclass->name; 1170 1171 if (pclass->subc == NULL) { 1172 return name; 1173 } 1174 1175 psubclass = pclass->subc; 1176 while ((psubclass->subclass & 0xff) != 0xff) { 1177 if ((psubclass->subclass & 0xff) == subclass) { 1178 name = psubclass->name; 1179 break; 1180 } 1181 psubclass++; 1182 } 1183 1184 piface = psubclass->iface; 1185 if (piface == NULL) { 1186 return name; 1187 } 1188 while ((piface->iface & 0xff) != 0xff) { 1189 if ((piface->iface & 0xff) == iface) { 1190 name = piface->name; 1191 break; 1192 } 1193 piface++; 1194 } 1195 1196 return name; 1197 } 1198 1199 static void pci_get_node_name(char *nodename, int len, PCIDevice *dev) 1200 { 1201 int slot = PCI_SLOT(dev->devfn); 1202 int func = PCI_FUNC(dev->devfn); 1203 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1204 const char *name; 1205 1206 name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1207 ccode & 0xff); 1208 1209 if (func != 0) { 1210 snprintf(nodename, len, "%s@%x,%x", name, slot, func); 1211 } else { 1212 snprintf(nodename, len, "%s@%x", name, slot); 1213 } 1214 } 1215 1216 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1217 PCIDevice *pdev); 1218 1219 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, 1220 sPAPRPHBState *sphb) 1221 { 1222 ResourceProps rp; 1223 bool is_bridge = false; 1224 int pci_status, err; 1225 char *buf = NULL; 1226 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); 1227 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1228 uint32_t max_msi, max_msix; 1229 1230 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == 1231 PCI_HEADER_TYPE_BRIDGE) { 1232 is_bridge = true; 1233 } 1234 1235 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1236 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", 1237 pci_default_read_config(dev, PCI_VENDOR_ID, 2))); 1238 _FDT(fdt_setprop_cell(fdt, offset, "device-id", 1239 pci_default_read_config(dev, PCI_DEVICE_ID, 2))); 1240 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", 1241 pci_default_read_config(dev, PCI_REVISION_ID, 1))); 1242 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1243 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { 1244 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", 1245 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); 1246 } 1247 1248 if (!is_bridge) { 1249 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", 1250 pci_default_read_config(dev, PCI_MIN_GNT, 1))); 1251 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", 1252 pci_default_read_config(dev, PCI_MAX_LAT, 1))); 1253 } 1254 1255 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { 1256 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", 1257 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); 1258 } 1259 1260 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { 1261 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1262 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); 1263 } 1264 1265 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", 1266 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); 1267 1268 /* the following fdt cells are masked off the pci status register */ 1269 pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1270 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1271 PCI_STATUS_DEVSEL_MASK & pci_status)); 1272 1273 if (pci_status & PCI_STATUS_FAST_BACK) { 1274 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1275 } 1276 if (pci_status & PCI_STATUS_66MHZ) { 1277 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1278 } 1279 if (pci_status & PCI_STATUS_UDF) { 1280 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1281 } 1282 1283 _FDT(fdt_setprop_string(fdt, offset, "name", 1284 pci_find_device_name((ccode >> 16) & 0xff, 1285 (ccode >> 8) & 0xff, 1286 ccode & 0xff))); 1287 buf = spapr_phb_get_loc_code(sphb, dev); 1288 if (!buf) { 1289 error_report("Failed setting the ibm,loc-code"); 1290 return -1; 1291 } 1292 1293 err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); 1294 g_free(buf); 1295 if (err < 0) { 1296 return err; 1297 } 1298 1299 if (drc_index) { 1300 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); 1301 } 1302 1303 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1304 RESOURCE_CELLS_ADDRESS)); 1305 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1306 RESOURCE_CELLS_SIZE)); 1307 1308 max_msi = msi_nr_vectors_allocated(dev); 1309 if (max_msi) { 1310 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1311 } 1312 max_msix = dev->msix_entries_nr; 1313 if (max_msix) { 1314 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1315 } 1316 1317 populate_resource_props(dev, &rp); 1318 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1319 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1320 (uint8_t *)rp.assigned, rp.assigned_len)); 1321 1322 if (sphb->pcie_ecs && pci_is_express(dev)) { 1323 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1324 } 1325 1326 return 0; 1327 } 1328 1329 /* create OF node for pci device and required OF DT properties */ 1330 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, 1331 void *fdt, int node_offset) 1332 { 1333 int offset, ret; 1334 char nodename[FDT_NAME_MAX]; 1335 1336 pci_get_node_name(nodename, FDT_NAME_MAX, dev); 1337 offset = fdt_add_subnode(fdt, node_offset, nodename); 1338 ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); 1339 1340 g_assert(!ret); 1341 if (ret) { 1342 return 0; 1343 } 1344 return offset; 1345 } 1346 1347 static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, 1348 sPAPRPHBState *phb, 1349 PCIDevice *pdev, 1350 Error **errp) 1351 { 1352 DeviceState *dev = DEVICE(pdev); 1353 void *fdt = NULL; 1354 int fdt_start_offset = 0, fdt_size; 1355 1356 fdt = create_device_tree(&fdt_size); 1357 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); 1358 if (!fdt_start_offset) { 1359 error_setg(errp, "Failed to create pci child device tree node"); 1360 goto out; 1361 } 1362 1363 spapr_drc_attach(drc, DEVICE(pdev), 1364 fdt, fdt_start_offset, !dev->hotplugged, errp); 1365 out: 1366 if (*errp) { 1367 g_free(fdt); 1368 } 1369 } 1370 1371 /* Callback to be called during DRC release. */ 1372 void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1373 { 1374 /* some version guests do not wait for completion of a device 1375 * cleanup (generally done asynchronously by the kernel) before 1376 * signaling to QEMU that the device is safe, but instead sleep 1377 * for some 'safe' period of time. unfortunately on a busy host 1378 * this sleep isn't guaranteed to be long enough, resulting in 1379 * bad things like IRQ lines being left asserted during final 1380 * device removal. to deal with this we call reset just prior 1381 * to finalizing the device, which will put the device back into 1382 * an 'idle' state, as the device cleanup code expects. 1383 */ 1384 pci_device_reset(PCI_DEVICE(dev)); 1385 object_unparent(OBJECT(dev)); 1386 } 1387 1388 static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, 1389 sPAPRPHBState *phb, 1390 PCIDevice *pdev, 1391 Error **errp) 1392 { 1393 spapr_drc_detach(drc, DEVICE(pdev), errp); 1394 } 1395 1396 static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb, 1397 uint32_t busnr, 1398 int32_t devfn) 1399 { 1400 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1401 (phb->index << 16) | (busnr << 8) | devfn); 1402 } 1403 1404 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, 1405 PCIDevice *pdev) 1406 { 1407 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 1408 return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn); 1409 } 1410 1411 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1412 PCIDevice *pdev) 1413 { 1414 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1415 1416 if (!drc) { 1417 return 0; 1418 } 1419 1420 return spapr_drc_index(drc); 1421 } 1422 1423 static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, 1424 DeviceState *plugged_dev, Error **errp) 1425 { 1426 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1427 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1428 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1429 Error *local_err = NULL; 1430 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1431 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1432 1433 /* if DR is disabled we don't need to do anything in the case of 1434 * hotplug or coldplug callbacks 1435 */ 1436 if (!phb->dr_enabled) { 1437 /* if this is a hotplug operation initiated by the user 1438 * we need to let them know it's not enabled 1439 */ 1440 if (plugged_dev->hotplugged) { 1441 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1442 object_get_typename(OBJECT(phb))); 1443 } 1444 return; 1445 } 1446 1447 g_assert(drc); 1448 1449 /* Following the QEMU convention used for PCIe multifunction 1450 * hotplug, we do not allow functions to be hotplugged to a 1451 * slot that already has function 0 present 1452 */ 1453 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1454 PCI_FUNC(pdev->devfn) != 0) { 1455 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 1456 " additional functions can no longer be exposed to guest.", 1457 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1458 return; 1459 } 1460 1461 spapr_phb_add_pci_device(drc, phb, pdev, &local_err); 1462 if (local_err) { 1463 error_propagate(errp, local_err); 1464 return; 1465 } 1466 1467 /* If this is function 0, signal hotplug for all the device functions. 1468 * Otherwise defer sending the hotplug event. 1469 */ 1470 if (plugged_dev->hotplugged && PCI_FUNC(pdev->devfn) == 0) { 1471 int i; 1472 1473 for (i = 0; i < 8; i++) { 1474 sPAPRDRConnector *func_drc; 1475 sPAPRDRConnectorClass *func_drck; 1476 sPAPRDREntitySense state; 1477 1478 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), 1479 PCI_DEVFN(slotnr, i)); 1480 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1481 state = func_drck->dr_entity_sense(func_drc); 1482 1483 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1484 spapr_hotplug_req_add_by_index(func_drc); 1485 } 1486 } 1487 } 1488 } 1489 1490 static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, 1491 DeviceState *plugged_dev, Error **errp) 1492 { 1493 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1494 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1495 sPAPRDRConnectorClass *drck; 1496 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1497 Error *local_err = NULL; 1498 1499 if (!phb->dr_enabled) { 1500 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1501 object_get_typename(OBJECT(phb))); 1502 return; 1503 } 1504 1505 g_assert(drc); 1506 1507 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1508 if (!drck->release_pending(drc)) { 1509 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1510 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1511 sPAPRDRConnector *func_drc; 1512 sPAPRDRConnectorClass *func_drck; 1513 sPAPRDREntitySense state; 1514 int i; 1515 1516 /* ensure any other present functions are pending unplug */ 1517 if (PCI_FUNC(pdev->devfn) == 0) { 1518 for (i = 1; i < 8; i++) { 1519 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), 1520 PCI_DEVFN(slotnr, i)); 1521 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1522 state = func_drck->dr_entity_sense(func_drc); 1523 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1524 && !func_drck->release_pending(func_drc)) { 1525 error_setg(errp, 1526 "PCI: slot %d, function %d still present. " 1527 "Must unplug all non-0 functions first.", 1528 slotnr, i); 1529 return; 1530 } 1531 } 1532 } 1533 1534 spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); 1535 if (local_err) { 1536 error_propagate(errp, local_err); 1537 return; 1538 } 1539 1540 /* if this isn't func 0, defer unplug event. otherwise signal removal 1541 * for all present functions 1542 */ 1543 if (PCI_FUNC(pdev->devfn) == 0) { 1544 for (i = 7; i >= 0; i--) { 1545 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), 1546 PCI_DEVFN(slotnr, i)); 1547 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1548 state = func_drck->dr_entity_sense(func_drc); 1549 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1550 spapr_hotplug_req_remove_by_index(func_drc); 1551 } 1552 } 1553 } 1554 } 1555 } 1556 1557 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1558 { 1559 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1560 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1561 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1562 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1563 char *namebuf; 1564 int i; 1565 PCIBus *bus; 1566 uint64_t msi_window_size = 4096; 1567 sPAPRTCETable *tcet; 1568 const unsigned windows_supported = 1569 sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; 1570 1571 if (sphb->index != (uint32_t)-1) { 1572 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1573 Error *local_err = NULL; 1574 1575 if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn[0] != (uint32_t)-1) 1576 || (sphb->dma_liobn[1] != (uint32_t)-1 && windows_supported == 2) 1577 || (sphb->mem_win_addr != (hwaddr)-1) 1578 || (sphb->mem64_win_addr != (hwaddr)-1) 1579 || (sphb->io_win_addr != (hwaddr)-1)) { 1580 error_setg(errp, "Either \"index\" or other parameters must" 1581 " be specified for PAPR PHB, not both"); 1582 return; 1583 } 1584 1585 smc->phb_placement(spapr, sphb->index, 1586 &sphb->buid, &sphb->io_win_addr, 1587 &sphb->mem_win_addr, &sphb->mem64_win_addr, 1588 windows_supported, sphb->dma_liobn, &local_err); 1589 if (local_err) { 1590 error_propagate(errp, local_err); 1591 return; 1592 } 1593 } 1594 1595 if (sphb->buid == (uint64_t)-1) { 1596 error_setg(errp, "BUID not specified for PHB"); 1597 return; 1598 } 1599 1600 if ((sphb->dma_liobn[0] == (uint32_t)-1) || 1601 ((sphb->dma_liobn[1] == (uint32_t)-1) && (windows_supported > 1))) { 1602 error_setg(errp, "LIOBN(s) not specified for PHB"); 1603 return; 1604 } 1605 1606 if (sphb->mem_win_addr == (hwaddr)-1) { 1607 error_setg(errp, "Memory window address not specified for PHB"); 1608 return; 1609 } 1610 1611 if (sphb->io_win_addr == (hwaddr)-1) { 1612 error_setg(errp, "IO window address not specified for PHB"); 1613 return; 1614 } 1615 1616 if (sphb->mem64_win_size != 0) { 1617 if (sphb->mem64_win_addr == (hwaddr)-1) { 1618 error_setg(errp, 1619 "64-bit memory window address not specified for PHB"); 1620 return; 1621 } 1622 1623 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1624 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1625 " (max 2 GiB)", sphb->mem_win_size); 1626 return; 1627 } 1628 1629 if (sphb->mem64_win_pciaddr == (hwaddr)-1) { 1630 /* 64-bit window defaults to identity mapping */ 1631 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1632 } 1633 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1634 /* 1635 * For compatibility with old configuration, if no 64-bit MMIO 1636 * window is specified, but the ordinary (32-bit) memory 1637 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1638 * window, with a 64-bit MMIO window following on immediately 1639 * afterwards 1640 */ 1641 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1642 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1643 sphb->mem64_win_pciaddr = 1644 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1645 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1646 } 1647 1648 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1649 error_setg(errp, "PCI host bridges must have unique BUIDs"); 1650 return; 1651 } 1652 1653 if (sphb->numa_node != -1 && 1654 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) { 1655 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1656 return; 1657 } 1658 1659 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1660 1661 namebuf = alloca(strlen(sphb->dtbusname) + 32); 1662 1663 /* Initialize memory regions */ 1664 sprintf(namebuf, "%s.mmio", sphb->dtbusname); 1665 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1666 1667 sprintf(namebuf, "%s.mmio32-alias", sphb->dtbusname); 1668 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1669 namebuf, &sphb->memspace, 1670 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1671 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1672 &sphb->mem32window); 1673 1674 sprintf(namebuf, "%s.mmio64-alias", sphb->dtbusname); 1675 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1676 namebuf, &sphb->memspace, 1677 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1678 memory_region_add_subregion(get_system_memory(), sphb->mem64_win_addr, 1679 &sphb->mem64window); 1680 1681 /* Initialize IO regions */ 1682 sprintf(namebuf, "%s.io", sphb->dtbusname); 1683 memory_region_init(&sphb->iospace, OBJECT(sphb), 1684 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1685 1686 sprintf(namebuf, "%s.io-alias", sphb->dtbusname); 1687 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1688 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1689 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1690 &sphb->iowindow); 1691 1692 bus = pci_register_bus(dev, NULL, 1693 pci_spapr_set_irq, pci_spapr_map_irq, sphb, 1694 &sphb->memspace, &sphb->iospace, 1695 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); 1696 phb->bus = bus; 1697 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); 1698 1699 /* 1700 * Initialize PHB address space. 1701 * By default there will be at least one subregion for default 1702 * 32bit DMA window. 1703 * Later the guest might want to create another DMA window 1704 * which will become another memory subregion. 1705 */ 1706 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); 1707 1708 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1709 namebuf, UINT64_MAX); 1710 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1711 sphb->dtbusname); 1712 1713 /* 1714 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1715 * we need to allocate some memory to catch those writes coming 1716 * from msi_notify()/msix_notify(). 1717 * As MSIMessage:addr is going to be the same and MSIMessage:data 1718 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1719 * be used. 1720 * 1721 * For KVM we want to ensure that this memory is a full page so that 1722 * our memory slot is of page size granularity. 1723 */ 1724 #ifdef CONFIG_KVM 1725 if (kvm_enabled()) { 1726 msi_window_size = getpagesize(); 1727 } 1728 #endif 1729 1730 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, 1731 "msi", msi_window_size); 1732 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1733 &sphb->msiwindow); 1734 1735 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1736 1737 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1738 1739 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1740 1741 /* Initialize the LSI table */ 1742 for (i = 0; i < PCI_NUM_PINS; i++) { 1743 uint32_t irq; 1744 Error *local_err = NULL; 1745 1746 irq = spapr_ics_alloc_block(spapr->ics, 1, true, false, &local_err); 1747 if (local_err) { 1748 error_propagate(errp, local_err); 1749 error_prepend(errp, "can't allocate LSIs: "); 1750 return; 1751 } 1752 1753 sphb->lsi_table[i].irq = irq; 1754 } 1755 1756 /* allocate connectors for child PCI devices */ 1757 if (sphb->dr_enabled) { 1758 for (i = 0; i < PCI_SLOT_MAX * 8; i++) { 1759 spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI, 1760 (sphb->index << 16) | i); 1761 } 1762 } 1763 1764 /* DMA setup */ 1765 if ((sphb->page_size_mask & qemu_getrampagesize()) == 0) { 1766 error_report("System page size 0x%lx is not enabled in page_size_mask " 1767 "(0x%"PRIx64"). Performance may be slow", 1768 qemu_getrampagesize(), sphb->page_size_mask); 1769 } 1770 1771 for (i = 0; i < windows_supported; ++i) { 1772 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 1773 if (!tcet) { 1774 error_setg(errp, "Creating window#%d failed for %s", 1775 i, sphb->dtbusname); 1776 return; 1777 } 1778 memory_region_add_subregion_overlap(&sphb->iommu_root, 0, 1779 spapr_tce_get_iommu(tcet), 0); 1780 } 1781 1782 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 1783 } 1784 1785 static int spapr_phb_children_reset(Object *child, void *opaque) 1786 { 1787 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 1788 1789 if (dev) { 1790 device_reset(dev); 1791 } 1792 1793 return 0; 1794 } 1795 1796 void spapr_phb_dma_reset(sPAPRPHBState *sphb) 1797 { 1798 int i; 1799 sPAPRTCETable *tcet; 1800 1801 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 1802 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1803 1804 if (tcet && tcet->nb_table) { 1805 spapr_tce_table_disable(tcet); 1806 } 1807 } 1808 1809 /* Register default 32bit DMA window */ 1810 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 1811 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 1812 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 1813 } 1814 1815 static void spapr_phb_reset(DeviceState *qdev) 1816 { 1817 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 1818 1819 spapr_phb_dma_reset(sphb); 1820 1821 /* Reset the IOMMU state */ 1822 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 1823 1824 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 1825 spapr_phb_vfio_reset(qdev); 1826 } 1827 } 1828 1829 static Property spapr_phb_properties[] = { 1830 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), 1831 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), 1832 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn[0], -1), 1833 DEFINE_PROP_UINT32("liobn64", sPAPRPHBState, dma_liobn[1], -1), 1834 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), 1835 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, 1836 SPAPR_PCI_MEM32_WIN_SIZE), 1837 DEFINE_PROP_UINT64("mem64_win_addr", sPAPRPHBState, mem64_win_addr, -1), 1838 DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size, 1839 SPAPR_PCI_MEM64_WIN_SIZE), 1840 DEFINE_PROP_UINT64("mem64_win_pciaddr", sPAPRPHBState, mem64_win_pciaddr, 1841 -1), 1842 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), 1843 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, 1844 SPAPR_PCI_IO_WIN_SIZE), 1845 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, 1846 true), 1847 /* Default DMA window is 0..1GB */ 1848 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0), 1849 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000), 1850 DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr, 1851 0x800000000000000ULL), 1852 DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true), 1853 DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask, 1854 (1ULL << 12) | (1ULL << 16)), 1855 DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1), 1856 DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState, 1857 pre_2_8_migration, false), 1858 DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState, 1859 pcie_ecs, true), 1860 DEFINE_PROP_END_OF_LIST(), 1861 }; 1862 1863 static const VMStateDescription vmstate_spapr_pci_lsi = { 1864 .name = "spapr_pci/lsi", 1865 .version_id = 1, 1866 .minimum_version_id = 1, 1867 .fields = (VMStateField[]) { 1868 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), 1869 1870 VMSTATE_END_OF_LIST() 1871 }, 1872 }; 1873 1874 static const VMStateDescription vmstate_spapr_pci_msi = { 1875 .name = "spapr_pci/msi", 1876 .version_id = 1, 1877 .minimum_version_id = 1, 1878 .fields = (VMStateField []) { 1879 VMSTATE_UINT32(key, spapr_pci_msi_mig), 1880 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 1881 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 1882 VMSTATE_END_OF_LIST() 1883 }, 1884 }; 1885 1886 static void spapr_pci_pre_save(void *opaque) 1887 { 1888 sPAPRPHBState *sphb = opaque; 1889 GHashTableIter iter; 1890 gpointer key, value; 1891 int i; 1892 1893 g_free(sphb->msi_devs); 1894 sphb->msi_devs = NULL; 1895 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 1896 if (!sphb->msi_devs_num) { 1897 return; 1898 } 1899 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); 1900 1901 g_hash_table_iter_init(&iter, sphb->msi); 1902 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 1903 sphb->msi_devs[i].key = *(uint32_t *) key; 1904 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 1905 } 1906 1907 if (sphb->pre_2_8_migration) { 1908 sphb->mig_liobn = sphb->dma_liobn[0]; 1909 sphb->mig_mem_win_addr = sphb->mem_win_addr; 1910 sphb->mig_mem_win_size = sphb->mem_win_size; 1911 sphb->mig_io_win_addr = sphb->io_win_addr; 1912 sphb->mig_io_win_size = sphb->io_win_size; 1913 1914 if ((sphb->mem64_win_size != 0) 1915 && (sphb->mem64_win_addr 1916 == (sphb->mem_win_addr + sphb->mem_win_size))) { 1917 sphb->mig_mem_win_size += sphb->mem64_win_size; 1918 } 1919 } 1920 } 1921 1922 static int spapr_pci_post_load(void *opaque, int version_id) 1923 { 1924 sPAPRPHBState *sphb = opaque; 1925 gpointer key, value; 1926 int i; 1927 1928 for (i = 0; i < sphb->msi_devs_num; ++i) { 1929 key = g_memdup(&sphb->msi_devs[i].key, 1930 sizeof(sphb->msi_devs[i].key)); 1931 value = g_memdup(&sphb->msi_devs[i].value, 1932 sizeof(sphb->msi_devs[i].value)); 1933 g_hash_table_insert(sphb->msi, key, value); 1934 } 1935 g_free(sphb->msi_devs); 1936 sphb->msi_devs = NULL; 1937 sphb->msi_devs_num = 0; 1938 1939 return 0; 1940 } 1941 1942 static bool pre_2_8_migration(void *opaque, int version_id) 1943 { 1944 sPAPRPHBState *sphb = opaque; 1945 1946 return sphb->pre_2_8_migration; 1947 } 1948 1949 static const VMStateDescription vmstate_spapr_pci = { 1950 .name = "spapr_pci", 1951 .version_id = 2, 1952 .minimum_version_id = 2, 1953 .pre_save = spapr_pci_pre_save, 1954 .post_load = spapr_pci_post_load, 1955 .fields = (VMStateField[]) { 1956 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), 1957 VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration), 1958 VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration), 1959 VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration), 1960 VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration), 1961 VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration), 1962 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, 1963 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 1964 VMSTATE_INT32(msi_devs_num, sPAPRPHBState), 1965 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, 1966 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 1967 VMSTATE_END_OF_LIST() 1968 }, 1969 }; 1970 1971 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 1972 PCIBus *rootbus) 1973 { 1974 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 1975 1976 return sphb->dtbusname; 1977 } 1978 1979 static void spapr_phb_class_init(ObjectClass *klass, void *data) 1980 { 1981 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 1982 DeviceClass *dc = DEVICE_CLASS(klass); 1983 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 1984 1985 hc->root_bus_path = spapr_phb_root_bus_path; 1986 dc->realize = spapr_phb_realize; 1987 dc->props = spapr_phb_properties; 1988 dc->reset = spapr_phb_reset; 1989 dc->vmsd = &vmstate_spapr_pci; 1990 /* Supported by TYPE_SPAPR_MACHINE */ 1991 dc->user_creatable = true; 1992 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1993 hp->plug = spapr_phb_hot_plug_child; 1994 hp->unplug = spapr_phb_hot_unplug_child; 1995 } 1996 1997 static const TypeInfo spapr_phb_info = { 1998 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 1999 .parent = TYPE_PCI_HOST_BRIDGE, 2000 .instance_size = sizeof(sPAPRPHBState), 2001 .class_init = spapr_phb_class_init, 2002 .interfaces = (InterfaceInfo[]) { 2003 { TYPE_HOTPLUG_HANDLER }, 2004 { } 2005 } 2006 }; 2007 2008 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) 2009 { 2010 DeviceState *dev; 2011 2012 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2013 qdev_prop_set_uint32(dev, "index", index); 2014 qdev_init_nofail(dev); 2015 2016 return PCI_HOST_BRIDGE(dev); 2017 } 2018 2019 typedef struct sPAPRFDT { 2020 void *fdt; 2021 int node_off; 2022 sPAPRPHBState *sphb; 2023 } sPAPRFDT; 2024 2025 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, 2026 void *opaque) 2027 { 2028 PCIBus *sec_bus; 2029 sPAPRFDT *p = opaque; 2030 int offset; 2031 sPAPRFDT s_fdt; 2032 2033 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); 2034 if (!offset) { 2035 error_report("Failed to create pci child device tree node"); 2036 return; 2037 } 2038 2039 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2040 PCI_HEADER_TYPE_BRIDGE)) { 2041 return; 2042 } 2043 2044 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2045 if (!sec_bus) { 2046 return; 2047 } 2048 2049 s_fdt.fdt = p->fdt; 2050 s_fdt.node_off = offset; 2051 s_fdt.sphb = p->sphb; 2052 pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus), 2053 spapr_populate_pci_devices_dt, 2054 &s_fdt); 2055 } 2056 2057 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2058 void *opaque) 2059 { 2060 unsigned int *bus_no = opaque; 2061 unsigned int primary = *bus_no; 2062 unsigned int subordinate = 0xff; 2063 PCIBus *sec_bus = NULL; 2064 2065 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2066 PCI_HEADER_TYPE_BRIDGE)) { 2067 return; 2068 } 2069 2070 (*bus_no)++; 2071 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 2072 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2073 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2074 2075 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2076 if (!sec_bus) { 2077 return; 2078 } 2079 2080 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 2081 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 2082 spapr_phb_pci_enumerate_bridge, bus_no); 2083 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2084 } 2085 2086 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) 2087 { 2088 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2089 unsigned int bus_no = 0; 2090 2091 pci_for_each_device(bus, pci_bus_num(bus), 2092 spapr_phb_pci_enumerate_bridge, 2093 &bus_no); 2094 2095 } 2096 2097 int spapr_populate_pci_dt(sPAPRPHBState *phb, 2098 uint32_t xics_phandle, 2099 void *fdt) 2100 { 2101 int bus_off, i, j, ret; 2102 char nodename[FDT_NAME_MAX]; 2103 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2104 struct { 2105 uint32_t hi; 2106 uint64_t child; 2107 uint64_t parent; 2108 uint64_t size; 2109 } QEMU_PACKED ranges[] = { 2110 { 2111 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2112 cpu_to_be64(phb->io_win_addr), 2113 cpu_to_be64(memory_region_size(&phb->iospace)), 2114 }, 2115 { 2116 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2117 cpu_to_be64(phb->mem_win_addr), 2118 cpu_to_be64(phb->mem_win_size), 2119 }, 2120 { 2121 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2122 cpu_to_be64(phb->mem64_win_addr), 2123 cpu_to_be64(phb->mem64_win_size), 2124 }, 2125 }; 2126 const unsigned sizeof_ranges = 2127 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2128 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2129 uint32_t interrupt_map_mask[] = { 2130 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2131 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2132 uint32_t ddw_applicable[] = { 2133 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2134 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2135 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2136 }; 2137 uint32_t ddw_extensions[] = { 2138 cpu_to_be32(1), 2139 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) 2140 }; 2141 uint32_t associativity[] = {cpu_to_be32(0x4), 2142 cpu_to_be32(0x0), 2143 cpu_to_be32(0x0), 2144 cpu_to_be32(0x0), 2145 cpu_to_be32(phb->numa_node)}; 2146 sPAPRTCETable *tcet; 2147 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2148 sPAPRFDT s_fdt; 2149 2150 /* Start populating the FDT */ 2151 snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); 2152 bus_off = fdt_add_subnode(fdt, 0, nodename); 2153 if (bus_off < 0) { 2154 return bus_off; 2155 } 2156 2157 /* Write PHB properties */ 2158 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2159 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2160 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); 2161 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); 2162 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2163 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2164 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2165 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2166 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2167 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2168 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR)); 2169 2170 /* Dynamic DMA window */ 2171 if (phb->ddw_enabled) { 2172 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2173 sizeof(ddw_applicable))); 2174 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2175 &ddw_extensions, sizeof(ddw_extensions))); 2176 } 2177 2178 /* Advertise NUMA via ibm,associativity */ 2179 if (phb->numa_node != -1) { 2180 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, 2181 sizeof(associativity))); 2182 } 2183 2184 /* Build the interrupt-map, this must matches what is done 2185 * in pci_spapr_map_irq 2186 */ 2187 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2188 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2189 for (i = 0; i < PCI_SLOT_MAX; i++) { 2190 for (j = 0; j < PCI_NUM_PINS; j++) { 2191 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2192 int lsi_num = pci_spapr_swizzle(i, j); 2193 2194 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2195 irqmap[1] = 0; 2196 irqmap[2] = 0; 2197 irqmap[3] = cpu_to_be32(j+1); 2198 irqmap[4] = cpu_to_be32(xics_phandle); 2199 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); 2200 irqmap[6] = cpu_to_be32(0x8); 2201 } 2202 } 2203 /* Write interrupt map */ 2204 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2205 sizeof(interrupt_map))); 2206 2207 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2208 if (!tcet) { 2209 return -1; 2210 } 2211 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2212 tcet->liobn, tcet->bus_offset, 2213 tcet->nb_table << tcet->page_shift); 2214 2215 /* Walk the bridges and program the bus numbers*/ 2216 spapr_phb_pci_enumerate(phb); 2217 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2218 2219 /* Populate tree nodes with PCI devices attached */ 2220 s_fdt.fdt = fdt; 2221 s_fdt.node_off = bus_off; 2222 s_fdt.sphb = phb; 2223 pci_for_each_device_reverse(bus, pci_bus_num(bus), 2224 spapr_populate_pci_devices_dt, 2225 &s_fdt); 2226 2227 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), 2228 SPAPR_DR_CONNECTOR_TYPE_PCI); 2229 if (ret) { 2230 return ret; 2231 } 2232 2233 return 0; 2234 } 2235 2236 void spapr_pci_rtas_init(void) 2237 { 2238 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2239 rtas_read_pci_config); 2240 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2241 rtas_write_pci_config); 2242 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2243 rtas_ibm_read_pci_config); 2244 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2245 rtas_ibm_write_pci_config); 2246 if (msi_nonbroken) { 2247 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2248 "ibm,query-interrupt-source-number", 2249 rtas_ibm_query_interrupt_source_number); 2250 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2251 rtas_ibm_change_msi); 2252 } 2253 2254 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2255 "ibm,set-eeh-option", 2256 rtas_ibm_set_eeh_option); 2257 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2258 "ibm,get-config-addr-info2", 2259 rtas_ibm_get_config_addr_info2); 2260 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2261 "ibm,read-slot-reset-state2", 2262 rtas_ibm_read_slot_reset_state2); 2263 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2264 "ibm,set-slot-reset", 2265 rtas_ibm_set_slot_reset); 2266 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2267 "ibm,configure-pe", 2268 rtas_ibm_configure_pe); 2269 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2270 "ibm,slot-error-detail", 2271 rtas_ibm_slot_error_detail); 2272 } 2273 2274 static void spapr_pci_register_types(void) 2275 { 2276 type_register_static(&spapr_phb_info); 2277 } 2278 2279 type_init(spapr_pci_register_types) 2280 2281 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2282 { 2283 bool be = *(bool *)opaque; 2284 2285 if (object_dynamic_cast(OBJECT(dev), "VGA") 2286 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 2287 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 2288 &error_abort); 2289 } 2290 return 0; 2291 } 2292 2293 void spapr_pci_switch_vga(bool big_endian) 2294 { 2295 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 2296 sPAPRPHBState *sphb; 2297 2298 /* 2299 * For backward compatibility with existing guests, we switch 2300 * the endianness of the VGA controller when changing the guest 2301 * interrupt mode 2302 */ 2303 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2304 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2305 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2306 &big_endian); 2307 } 2308 } 2309