1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "exec/exec-all.h" 4 #include "exec/cputlb.h" 5 #include "helper_regs.h" 6 #include "hw/ppc/ppc.h" 7 #include "hw/ppc/spapr.h" 8 #include "hw/ppc/spapr_cpu_core.h" 9 #include "hw/ppc/spapr_nested.h" 10 #include "mmu-book3s-v3.h" 11 #include "cpu-models.h" 12 #include "qemu/log.h" 13 14 void spapr_nested_reset(SpaprMachineState *spapr) 15 { 16 if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) { 17 spapr_unregister_nested_hv(); 18 spapr_register_nested_hv(); 19 } else if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_PAPR)) { 20 spapr->nested.capabilities_set = false; 21 spapr_unregister_nested_papr(); 22 spapr_register_nested_papr(); 23 spapr_nested_gsb_init(); 24 } else { 25 spapr->nested.api = 0; 26 } 27 } 28 29 uint8_t spapr_nested_api(SpaprMachineState *spapr) 30 { 31 return spapr->nested.api; 32 } 33 34 #ifdef CONFIG_TCG 35 36 bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, 37 target_ulong lpid, ppc_v3_pate_t *entry) 38 { 39 uint64_t patb, pats; 40 41 assert(lpid != 0); 42 43 patb = spapr->nested.ptcr & PTCR_PATB; 44 pats = spapr->nested.ptcr & PTCR_PATS; 45 46 /* Check if partition table is properly aligned */ 47 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 48 return false; 49 } 50 51 /* Calculate number of entries */ 52 pats = 1ull << (pats + 12 - 4); 53 if (pats <= lpid) { 54 return false; 55 } 56 57 /* Grab entry */ 58 patb += 16 * lpid; 59 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 60 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 61 return true; 62 } 63 64 static 65 SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *spapr, 66 target_ulong guestid) 67 { 68 SpaprMachineStateNestedGuest *guest; 69 70 guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid)); 71 return guest; 72 } 73 74 bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, 75 target_ulong lpid, ppc_v3_pate_t *entry) 76 { 77 SpaprMachineStateNestedGuest *guest; 78 assert(lpid != 0); 79 guest = spapr_get_nested_guest(spapr, lpid); 80 if (!guest) { 81 return false; 82 } 83 84 entry->dw0 = guest->parttbl[0]; 85 entry->dw1 = guest->parttbl[1]; 86 return true; 87 } 88 89 #define PRTS_MASK 0x1f 90 91 static target_ulong h_set_ptbl(PowerPCCPU *cpu, 92 SpaprMachineState *spapr, 93 target_ulong opcode, 94 target_ulong *args) 95 { 96 target_ulong ptcr = args[0]; 97 98 if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) { 99 return H_FUNCTION; 100 } 101 102 if ((ptcr & PRTS_MASK) + 12 - 4 > 12) { 103 return H_PARAMETER; 104 } 105 106 spapr->nested.ptcr = ptcr; /* Save new partition table */ 107 108 return H_SUCCESS; 109 } 110 111 static target_ulong h_tlb_invalidate(PowerPCCPU *cpu, 112 SpaprMachineState *spapr, 113 target_ulong opcode, 114 target_ulong *args) 115 { 116 /* 117 * The spapr virtual hypervisor nested HV implementation retains no L2 118 * translation state except for TLB. And the TLB is always invalidated 119 * across L1<->L2 transitions, so nothing is required here. 120 */ 121 122 return H_SUCCESS; 123 } 124 125 static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu, 126 SpaprMachineState *spapr, 127 target_ulong opcode, 128 target_ulong *args) 129 { 130 /* 131 * This HCALL is not required, L1 KVM will take a slow path and walk the 132 * page tables manually to do the data copy. 133 */ 134 return H_FUNCTION; 135 } 136 137 static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu) 138 { 139 CPUPPCState *env = &cpu->env; 140 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 141 142 memcpy(save->gpr, env->gpr, sizeof(save->gpr)); 143 144 save->lr = env->lr; 145 save->ctr = env->ctr; 146 save->cfar = env->cfar; 147 save->msr = env->msr; 148 save->nip = env->nip; 149 150 save->cr = ppc_get_cr(env); 151 save->xer = cpu_read_xer(env); 152 153 save->lpcr = env->spr[SPR_LPCR]; 154 save->lpidr = env->spr[SPR_LPIDR]; 155 save->pcr = env->spr[SPR_PCR]; 156 save->dpdes = env->spr[SPR_DPDES]; 157 save->hfscr = env->spr[SPR_HFSCR]; 158 save->srr0 = env->spr[SPR_SRR0]; 159 save->srr1 = env->spr[SPR_SRR1]; 160 save->sprg0 = env->spr[SPR_SPRG0]; 161 save->sprg1 = env->spr[SPR_SPRG1]; 162 save->sprg2 = env->spr[SPR_SPRG2]; 163 save->sprg3 = env->spr[SPR_SPRG3]; 164 save->pidr = env->spr[SPR_BOOKS_PID]; 165 save->ppr = env->spr[SPR_PPR]; 166 167 if (spapr_nested_api(spapr) == NESTED_API_PAPR) { 168 save->amor = env->spr[SPR_AMOR]; 169 save->dawr0 = env->spr[SPR_DAWR0]; 170 save->dawrx0 = env->spr[SPR_DAWRX0]; 171 save->ciabr = env->spr[SPR_CIABR]; 172 save->purr = env->spr[SPR_PURR]; 173 save->spurr = env->spr[SPR_SPURR]; 174 save->ic = env->spr[SPR_IC]; 175 save->vtb = env->spr[SPR_VTB]; 176 save->hdar = env->spr[SPR_HDAR]; 177 save->hdsisr = env->spr[SPR_HDSISR]; 178 save->heir = env->spr[SPR_HEIR]; 179 save->asdr = env->spr[SPR_ASDR]; 180 save->dawr1 = env->spr[SPR_DAWR1]; 181 save->dawrx1 = env->spr[SPR_DAWRX1]; 182 save->dexcr = env->spr[SPR_DEXCR]; 183 save->hdexcr = env->spr[SPR_HDEXCR]; 184 save->hashkeyr = env->spr[SPR_HASHKEYR]; 185 save->hashpkeyr = env->spr[SPR_HASHPKEYR]; 186 memcpy(save->vsr, env->vsr, sizeof(save->vsr)); 187 save->ebbhr = env->spr[SPR_EBBHR]; 188 save->tar = env->spr[SPR_TAR]; 189 save->ebbrr = env->spr[SPR_EBBRR]; 190 save->bescr = env->spr[SPR_BESCR]; 191 save->iamr = env->spr[SPR_IAMR]; 192 save->amr = env->spr[SPR_AMR]; 193 save->uamor = env->spr[SPR_UAMOR]; 194 save->dscr = env->spr[SPR_DSCR]; 195 save->fscr = env->spr[SPR_FSCR]; 196 save->pspb = env->spr[SPR_PSPB]; 197 save->ctrl = env->spr[SPR_CTRL]; 198 save->vrsave = env->spr[SPR_VRSAVE]; 199 save->dar = env->spr[SPR_DAR]; 200 save->dsisr = env->spr[SPR_DSISR]; 201 save->pmc1 = env->spr[SPR_POWER_PMC1]; 202 save->pmc2 = env->spr[SPR_POWER_PMC2]; 203 save->pmc3 = env->spr[SPR_POWER_PMC3]; 204 save->pmc4 = env->spr[SPR_POWER_PMC4]; 205 save->pmc5 = env->spr[SPR_POWER_PMC5]; 206 save->pmc6 = env->spr[SPR_POWER_PMC6]; 207 save->mmcr0 = env->spr[SPR_POWER_MMCR0]; 208 save->mmcr1 = env->spr[SPR_POWER_MMCR1]; 209 save->mmcr2 = env->spr[SPR_POWER_MMCR2]; 210 save->mmcra = env->spr[SPR_POWER_MMCRA]; 211 save->sdar = env->spr[SPR_POWER_SDAR]; 212 save->siar = env->spr[SPR_POWER_SIAR]; 213 save->sier = env->spr[SPR_POWER_SIER]; 214 save->vscr = ppc_get_vscr(env); 215 save->fpscr = env->fpscr; 216 } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) { 217 save->tb_offset = env->tb_env->tb_offset; 218 } 219 } 220 221 static void nested_post_load_state(CPUPPCState *env, CPUState *cs) 222 { 223 /* 224 * compute hflags and possible interrupts. 225 */ 226 hreg_compute_hflags(env); 227 ppc_maybe_interrupt(env); 228 /* 229 * Nested HV does not tag TLB entries between L1 and L2, so must 230 * flush on transition. 231 */ 232 tlb_flush(cs); 233 env->reserve_addr = -1; /* Reset the reservation */ 234 } 235 236 static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load) 237 { 238 CPUPPCState *env = &cpu->env; 239 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 240 241 memcpy(env->gpr, load->gpr, sizeof(env->gpr)); 242 243 env->lr = load->lr; 244 env->ctr = load->ctr; 245 env->cfar = load->cfar; 246 env->msr = load->msr; 247 env->nip = load->nip; 248 249 ppc_set_cr(env, load->cr); 250 cpu_write_xer(env, load->xer); 251 252 env->spr[SPR_LPCR] = load->lpcr; 253 env->spr[SPR_LPIDR] = load->lpidr; 254 env->spr[SPR_PCR] = load->pcr; 255 env->spr[SPR_DPDES] = load->dpdes; 256 env->spr[SPR_HFSCR] = load->hfscr; 257 env->spr[SPR_SRR0] = load->srr0; 258 env->spr[SPR_SRR1] = load->srr1; 259 env->spr[SPR_SPRG0] = load->sprg0; 260 env->spr[SPR_SPRG1] = load->sprg1; 261 env->spr[SPR_SPRG2] = load->sprg2; 262 env->spr[SPR_SPRG3] = load->sprg3; 263 env->spr[SPR_BOOKS_PID] = load->pidr; 264 env->spr[SPR_PPR] = load->ppr; 265 266 if (spapr_nested_api(spapr) == NESTED_API_PAPR) { 267 env->spr[SPR_AMOR] = load->amor; 268 env->spr[SPR_DAWR0] = load->dawr0; 269 env->spr[SPR_DAWRX0] = load->dawrx0; 270 env->spr[SPR_CIABR] = load->ciabr; 271 env->spr[SPR_PURR] = load->purr; 272 env->spr[SPR_SPURR] = load->purr; 273 env->spr[SPR_IC] = load->ic; 274 env->spr[SPR_VTB] = load->vtb; 275 env->spr[SPR_HDAR] = load->hdar; 276 env->spr[SPR_HDSISR] = load->hdsisr; 277 env->spr[SPR_HEIR] = load->heir; 278 env->spr[SPR_ASDR] = load->asdr; 279 env->spr[SPR_DAWR1] = load->dawr1; 280 env->spr[SPR_DAWRX1] = load->dawrx1; 281 env->spr[SPR_DEXCR] = load->dexcr; 282 env->spr[SPR_HDEXCR] = load->hdexcr; 283 env->spr[SPR_HASHKEYR] = load->hashkeyr; 284 env->spr[SPR_HASHPKEYR] = load->hashpkeyr; 285 memcpy(env->vsr, load->vsr, sizeof(env->vsr)); 286 env->spr[SPR_EBBHR] = load->ebbhr; 287 env->spr[SPR_TAR] = load->tar; 288 env->spr[SPR_EBBRR] = load->ebbrr; 289 env->spr[SPR_BESCR] = load->bescr; 290 env->spr[SPR_IAMR] = load->iamr; 291 env->spr[SPR_AMR] = load->amr; 292 env->spr[SPR_UAMOR] = load->uamor; 293 env->spr[SPR_DSCR] = load->dscr; 294 env->spr[SPR_FSCR] = load->fscr; 295 env->spr[SPR_PSPB] = load->pspb; 296 env->spr[SPR_CTRL] = load->ctrl; 297 env->spr[SPR_VRSAVE] = load->vrsave; 298 env->spr[SPR_DAR] = load->dar; 299 env->spr[SPR_DSISR] = load->dsisr; 300 env->spr[SPR_POWER_PMC1] = load->pmc1; 301 env->spr[SPR_POWER_PMC2] = load->pmc2; 302 env->spr[SPR_POWER_PMC3] = load->pmc3; 303 env->spr[SPR_POWER_PMC4] = load->pmc4; 304 env->spr[SPR_POWER_PMC5] = load->pmc5; 305 env->spr[SPR_POWER_PMC6] = load->pmc6; 306 env->spr[SPR_POWER_MMCR0] = load->mmcr0; 307 env->spr[SPR_POWER_MMCR1] = load->mmcr1; 308 env->spr[SPR_POWER_MMCR2] = load->mmcr2; 309 env->spr[SPR_POWER_MMCRA] = load->mmcra; 310 env->spr[SPR_POWER_SDAR] = load->sdar; 311 env->spr[SPR_POWER_SIAR] = load->siar; 312 env->spr[SPR_POWER_SIER] = load->sier; 313 ppc_store_vscr(env, load->vscr); 314 ppc_store_fpscr(env, load->fpscr); 315 } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) { 316 env->tb_env->tb_offset = load->tb_offset; 317 } 318 } 319 320 /* 321 * When this handler returns, the environment is switched to the L2 guest 322 * and TCG begins running that. spapr_exit_nested() performs the switch from 323 * L2 back to L1 and returns from the H_ENTER_NESTED hcall. 324 */ 325 static target_ulong h_enter_nested(PowerPCCPU *cpu, 326 SpaprMachineState *spapr, 327 target_ulong opcode, 328 target_ulong *args) 329 { 330 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 331 CPUPPCState *env = &cpu->env; 332 CPUState *cs = CPU(cpu); 333 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 334 struct nested_ppc_state l2_state; 335 target_ulong hv_ptr = args[0]; 336 target_ulong regs_ptr = args[1]; 337 target_ulong hdec, now = cpu_ppc_load_tbl(env); 338 target_ulong lpcr, lpcr_mask; 339 struct kvmppc_hv_guest_state *hvstate; 340 struct kvmppc_hv_guest_state hv_state; 341 struct kvmppc_pt_regs *regs; 342 hwaddr len; 343 344 if (spapr->nested.ptcr == 0) { 345 return H_NOT_AVAILABLE; 346 } 347 348 len = sizeof(*hvstate); 349 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false, 350 MEMTXATTRS_UNSPECIFIED); 351 if (len != sizeof(*hvstate)) { 352 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false); 353 return H_PARAMETER; 354 } 355 356 memcpy(&hv_state, hvstate, len); 357 358 address_space_unmap(CPU(cpu)->as, hvstate, len, len, false); 359 360 /* 361 * We accept versions 1 and 2. Version 2 fields are unused because TCG 362 * does not implement DAWR*. 363 */ 364 if (hv_state.version > HV_GUEST_STATE_VERSION) { 365 return H_PARAMETER; 366 } 367 368 if (hv_state.lpid == 0) { 369 return H_PARAMETER; 370 } 371 372 spapr_cpu->nested_host_state = g_try_new(struct nested_ppc_state, 1); 373 if (!spapr_cpu->nested_host_state) { 374 return H_NO_MEM; 375 } 376 377 assert(env->spr[SPR_LPIDR] == 0); 378 assert(env->spr[SPR_DPDES] == 0); 379 nested_save_state(spapr_cpu->nested_host_state, cpu); 380 381 len = sizeof(*regs); 382 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false, 383 MEMTXATTRS_UNSPECIFIED); 384 if (!regs || len != sizeof(*regs)) { 385 address_space_unmap(CPU(cpu)->as, regs, len, 0, false); 386 g_free(spapr_cpu->nested_host_state); 387 return H_P2; 388 } 389 390 len = sizeof(l2_state.gpr); 391 assert(len == sizeof(regs->gpr)); 392 memcpy(l2_state.gpr, regs->gpr, len); 393 394 l2_state.lr = regs->link; 395 l2_state.ctr = regs->ctr; 396 l2_state.xer = regs->xer; 397 l2_state.cr = regs->ccr; 398 l2_state.msr = regs->msr; 399 l2_state.nip = regs->nip; 400 401 address_space_unmap(CPU(cpu)->as, regs, len, len, false); 402 403 l2_state.cfar = hv_state.cfar; 404 l2_state.lpidr = hv_state.lpid; 405 406 lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; 407 lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask); 408 lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; 409 lpcr &= ~LPCR_LPES0; 410 l2_state.lpcr = lpcr & pcc->lpcr_mask; 411 412 l2_state.pcr = hv_state.pcr; 413 /* hv_state.amor is not used */ 414 l2_state.dpdes = hv_state.dpdes; 415 l2_state.hfscr = hv_state.hfscr; 416 /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/ 417 l2_state.srr0 = hv_state.srr0; 418 l2_state.srr1 = hv_state.srr1; 419 l2_state.sprg0 = hv_state.sprg[0]; 420 l2_state.sprg1 = hv_state.sprg[1]; 421 l2_state.sprg2 = hv_state.sprg[2]; 422 l2_state.sprg3 = hv_state.sprg[3]; 423 l2_state.pidr = hv_state.pidr; 424 l2_state.ppr = hv_state.ppr; 425 l2_state.tb_offset = env->tb_env->tb_offset + hv_state.tb_offset; 426 427 /* 428 * Switch to the nested guest environment and start the "hdec" timer. 429 */ 430 nested_load_state(cpu, &l2_state); 431 nested_post_load_state(env, cs); 432 433 hdec = hv_state.hdec_expiry - now; 434 cpu_ppc_hdecr_init(env); 435 cpu_ppc_store_hdecr(env, hdec); 436 437 /* 438 * The hv_state.vcpu_token is not needed. It is used by the KVM 439 * implementation to remember which L2 vCPU last ran on which physical 440 * CPU so as to invalidate process scope translations if it is moved 441 * between physical CPUs. For now TLBs are always flushed on L1<->L2 442 * transitions so this is not a problem. 443 * 444 * Could validate that the same vcpu_token does not attempt to run on 445 * different L1 vCPUs at the same time, but that would be a L1 KVM bug 446 * and it's not obviously worth a new data structure to do it. 447 */ 448 449 spapr_cpu->in_nested = true; 450 451 /* 452 * The spapr hcall helper sets env->gpr[3] to the return value, but at 453 * this point the L1 is not returning from the hcall but rather we 454 * start running the L2, so r3 must not be clobbered, so return env->gpr[3] 455 * to leave it unchanged. 456 */ 457 return env->gpr[3]; 458 } 459 460 static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp) 461 { 462 CPUPPCState *env = &cpu->env; 463 CPUState *cs = CPU(cpu); 464 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 465 struct nested_ppc_state l2_state; 466 target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4]; 467 target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5]; 468 target_ulong hsrr0, hsrr1, hdar, asdr, hdsisr; 469 struct kvmppc_hv_guest_state *hvstate; 470 struct kvmppc_pt_regs *regs; 471 hwaddr len; 472 473 nested_save_state(&l2_state, cpu); 474 hsrr0 = env->spr[SPR_HSRR0]; 475 hsrr1 = env->spr[SPR_HSRR1]; 476 hdar = env->spr[SPR_HDAR]; 477 hdsisr = env->spr[SPR_HDSISR]; 478 asdr = env->spr[SPR_ASDR]; 479 480 /* 481 * Switch back to the host environment (including for any error). 482 */ 483 assert(env->spr[SPR_LPIDR] != 0); 484 nested_load_state(cpu, spapr_cpu->nested_host_state); 485 nested_post_load_state(env, cs); 486 env->gpr[3] = env->excp_vectors[excp]; /* hcall return value */ 487 488 cpu_ppc_hdecr_exit(env); 489 490 spapr_cpu->in_nested = false; 491 492 g_free(spapr_cpu->nested_host_state); 493 spapr_cpu->nested_host_state = NULL; 494 495 len = sizeof(*hvstate); 496 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true, 497 MEMTXATTRS_UNSPECIFIED); 498 if (len != sizeof(*hvstate)) { 499 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true); 500 env->gpr[3] = H_PARAMETER; 501 return; 502 } 503 504 hvstate->cfar = l2_state.cfar; 505 hvstate->lpcr = l2_state.lpcr; 506 hvstate->pcr = l2_state.pcr; 507 hvstate->dpdes = l2_state.dpdes; 508 hvstate->hfscr = l2_state.hfscr; 509 510 if (excp == POWERPC_EXCP_HDSI) { 511 hvstate->hdar = hdar; 512 hvstate->hdsisr = hdsisr; 513 hvstate->asdr = asdr; 514 } else if (excp == POWERPC_EXCP_HISI) { 515 hvstate->asdr = asdr; 516 } 517 518 /* HEIR should be implemented for HV mode and saved here. */ 519 hvstate->srr0 = l2_state.srr0; 520 hvstate->srr1 = l2_state.srr1; 521 hvstate->sprg[0] = l2_state.sprg0; 522 hvstate->sprg[1] = l2_state.sprg1; 523 hvstate->sprg[2] = l2_state.sprg2; 524 hvstate->sprg[3] = l2_state.sprg3; 525 hvstate->pidr = l2_state.pidr; 526 hvstate->ppr = l2_state.ppr; 527 528 /* Is it okay to specify write length larger than actual data written? */ 529 address_space_unmap(CPU(cpu)->as, hvstate, len, len, true); 530 531 len = sizeof(*regs); 532 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true, 533 MEMTXATTRS_UNSPECIFIED); 534 if (!regs || len != sizeof(*regs)) { 535 address_space_unmap(CPU(cpu)->as, regs, len, 0, true); 536 env->gpr[3] = H_P2; 537 return; 538 } 539 540 len = sizeof(env->gpr); 541 assert(len == sizeof(regs->gpr)); 542 memcpy(regs->gpr, l2_state.gpr, len); 543 544 regs->link = l2_state.lr; 545 regs->ctr = l2_state.ctr; 546 regs->xer = l2_state.xer; 547 regs->ccr = l2_state.cr; 548 549 if (excp == POWERPC_EXCP_MCHECK || 550 excp == POWERPC_EXCP_RESET || 551 excp == POWERPC_EXCP_SYSCALL) { 552 regs->nip = l2_state.srr0; 553 regs->msr = l2_state.srr1 & env->msr_mask; 554 } else { 555 regs->nip = hsrr0; 556 regs->msr = hsrr1 & env->msr_mask; 557 } 558 559 /* Is it okay to specify write length larger than actual data written? */ 560 address_space_unmap(CPU(cpu)->as, regs, len, len, true); 561 } 562 563 static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest, 564 target_ulong vcpuid, bool inoutbuf) 565 { 566 struct SpaprMachineStateNestedGuestVcpu *vcpu; 567 /* 568 * Perform sanity checks for the provided vcpuid of a guest. 569 * For now, ensure its valid, allocated and enabled for use. 570 */ 571 572 if (vcpuid >= PAPR_NESTED_GUEST_VCPU_MAX) { 573 return false; 574 } 575 576 if (!(vcpuid < guest->nr_vcpus)) { 577 return false; 578 } 579 580 vcpu = &guest->vcpus[vcpuid]; 581 if (!vcpu->enabled) { 582 return false; 583 } 584 585 if (!inoutbuf) { 586 return true; 587 } 588 589 /* Check to see if the in/out buffers are registered */ 590 if (vcpu->runbufin.addr && vcpu->runbufout.addr) { 591 return true; 592 } 593 594 return false; 595 } 596 597 static void *get_vcpu_state_ptr(SpaprMachineStateNestedGuest *guest, 598 target_ulong vcpuid) 599 { 600 assert(spapr_nested_vcpu_check(guest, vcpuid, false)); 601 return &guest->vcpus[vcpuid].state; 602 } 603 604 static void *get_vcpu_ptr(SpaprMachineStateNestedGuest *guest, 605 target_ulong vcpuid) 606 { 607 assert(spapr_nested_vcpu_check(guest, vcpuid, false)); 608 return &guest->vcpus[vcpuid]; 609 } 610 611 static void *get_guest_ptr(SpaprMachineStateNestedGuest *guest, 612 target_ulong vcpuid) 613 { 614 return guest; /* for GSBE_NESTED */ 615 } 616 617 /* 618 * set=1 means the L1 is trying to set some state 619 * set=0 means the L1 is trying to get some state 620 */ 621 static void copy_state_8to8(void *a, void *b, bool set) 622 { 623 /* set takes from the Big endian element_buf and sets internal buffer */ 624 625 if (set) { 626 *(uint64_t *)a = be64_to_cpu(*(uint64_t *)b); 627 } else { 628 *(uint64_t *)b = cpu_to_be64(*(uint64_t *)a); 629 } 630 } 631 632 static void copy_state_4to4(void *a, void *b, bool set) 633 { 634 if (set) { 635 *(uint32_t *)a = be32_to_cpu(*(uint32_t *)b); 636 } else { 637 *(uint32_t *)b = cpu_to_be32(*((uint32_t *)a)); 638 } 639 } 640 641 static void copy_state_16to16(void *a, void *b, bool set) 642 { 643 uint64_t *src, *dst; 644 645 if (set) { 646 src = b; 647 dst = a; 648 649 dst[1] = be64_to_cpu(src[0]); 650 dst[0] = be64_to_cpu(src[1]); 651 } else { 652 src = a; 653 dst = b; 654 655 dst[1] = cpu_to_be64(src[0]); 656 dst[0] = cpu_to_be64(src[1]); 657 } 658 } 659 660 static void copy_state_4to8(void *a, void *b, bool set) 661 { 662 if (set) { 663 *(uint64_t *)a = (uint64_t) be32_to_cpu(*(uint32_t *)b); 664 } else { 665 *(uint32_t *)b = cpu_to_be32((uint32_t) (*((uint64_t *)a))); 666 } 667 } 668 669 static void copy_state_pagetbl(void *a, void *b, bool set) 670 { 671 uint64_t *pagetbl; 672 uint64_t *buf; /* 3 double words */ 673 uint64_t rts; 674 675 assert(set); 676 677 pagetbl = a; 678 buf = b; 679 680 *pagetbl = be64_to_cpu(buf[0]); 681 /* as per ISA section 6.7.6.1 */ 682 *pagetbl |= PATE0_HR; /* Host Radix bit is 1 */ 683 684 /* RTS */ 685 rts = be64_to_cpu(buf[1]); 686 assert(rts == 52); 687 rts = rts - 31; /* since radix tree size = 2^(RTS+31) */ 688 *pagetbl |= ((rts & 0x7) << 5); /* RTS2 is bit 56:58 */ 689 *pagetbl |= (((rts >> 3) & 0x3) << 61); /* RTS1 is bit 1:2 */ 690 691 /* RPDS {Size = 2^(RPDS+3) , RPDS >=5} */ 692 *pagetbl |= 63 - clz64(be64_to_cpu(buf[2])) - 3; 693 } 694 695 static void copy_state_proctbl(void *a, void *b, bool set) 696 { 697 uint64_t *proctbl; 698 uint64_t *buf; /* 2 double words */ 699 700 assert(set); 701 702 proctbl = a; 703 buf = b; 704 /* PRTB: Process Table Base */ 705 *proctbl = be64_to_cpu(buf[0]); 706 /* PRTS: Process Table Size = 2^(12+PRTS) */ 707 if (be64_to_cpu(buf[1]) == (1ULL << 12)) { 708 *proctbl |= 0; 709 } else if (be64_to_cpu(buf[1]) == (1ULL << 24)) { 710 *proctbl |= 12; 711 } else { 712 g_assert_not_reached(); 713 } 714 } 715 716 static void copy_state_runbuf(void *a, void *b, bool set) 717 { 718 uint64_t *buf; /* 2 double words */ 719 struct SpaprMachineStateNestedGuestVcpuRunBuf *runbuf; 720 721 assert(set); 722 723 runbuf = a; 724 buf = b; 725 726 runbuf->addr = be64_to_cpu(buf[0]); 727 assert(runbuf->addr); 728 729 /* per spec */ 730 assert(be64_to_cpu(buf[1]) <= 16384); 731 732 /* 733 * This will also hit in the input buffer but should be fine for 734 * now. If not we can split this function. 735 */ 736 assert(be64_to_cpu(buf[1]) >= VCPU_OUT_BUF_MIN_SZ); 737 738 runbuf->size = be64_to_cpu(buf[1]); 739 } 740 741 /* tell the L1 how big we want the output vcpu run buffer */ 742 static void out_buf_min_size(void *a, void *b, bool set) 743 { 744 uint64_t *buf; /* 1 double word */ 745 746 assert(!set); 747 748 buf = b; 749 750 buf[0] = cpu_to_be64(VCPU_OUT_BUF_MIN_SZ); 751 } 752 753 static void copy_logical_pvr(void *a, void *b, bool set) 754 { 755 SpaprMachineStateNestedGuest *guest; 756 uint32_t *buf; /* 1 word */ 757 uint32_t *pvr_logical_ptr; 758 uint32_t pvr_logical; 759 target_ulong pcr = 0; 760 761 pvr_logical_ptr = a; 762 buf = b; 763 764 if (!set) { 765 buf[0] = cpu_to_be32(*pvr_logical_ptr); 766 return; 767 } 768 769 pvr_logical = be32_to_cpu(buf[0]); 770 771 *pvr_logical_ptr = pvr_logical; 772 773 if (*pvr_logical_ptr) { 774 switch (*pvr_logical_ptr) { 775 case CPU_POWERPC_LOGICAL_3_10_P11: 776 case CPU_POWERPC_LOGICAL_3_10: 777 pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00; 778 break; 779 case CPU_POWERPC_LOGICAL_3_00: 780 pcr = PCR_COMPAT_3_00; 781 break; 782 default: 783 qemu_log_mask(LOG_GUEST_ERROR, 784 "Could not set PCR for LPVR=0x%08x\n", 785 *pvr_logical_ptr); 786 return; 787 } 788 } 789 790 guest = container_of(pvr_logical_ptr, 791 struct SpaprMachineStateNestedGuest, 792 pvr_logical); 793 for (int i = 0; i < guest->nr_vcpus; i++) { 794 guest->vcpus[i].state.pcr = ~pcr | HVMASK_PCR; 795 } 796 } 797 798 static void copy_tb_offset(void *a, void *b, bool set) 799 { 800 SpaprMachineStateNestedGuest *guest; 801 uint64_t *buf; /* 1 double word */ 802 uint64_t *tb_offset_ptr; 803 uint64_t tb_offset; 804 805 tb_offset_ptr = a; 806 buf = b; 807 808 if (!set) { 809 buf[0] = cpu_to_be64(*tb_offset_ptr); 810 return; 811 } 812 813 tb_offset = be64_to_cpu(buf[0]); 814 /* need to copy this to the individual tb_offset for each vcpu */ 815 guest = container_of(tb_offset_ptr, 816 struct SpaprMachineStateNestedGuest, 817 tb_offset); 818 for (int i = 0; i < guest->nr_vcpus; i++) { 819 guest->vcpus[i].tb_offset = tb_offset; 820 } 821 } 822 823 static void copy_state_hdecr(void *a, void *b, bool set) 824 { 825 uint64_t *buf; /* 1 double word */ 826 uint64_t *hdecr_expiry_tb; 827 828 hdecr_expiry_tb = a; 829 buf = b; 830 831 if (!set) { 832 buf[0] = cpu_to_be64(*hdecr_expiry_tb); 833 return; 834 } 835 836 *hdecr_expiry_tb = be64_to_cpu(buf[0]); 837 } 838 839 struct guest_state_element_type guest_state_element_types[] = { 840 GUEST_STATE_ELEMENT_NOP(GSB_HV_VCPU_IGNORED_ID, 0), 841 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR0, gpr[0]), 842 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR1, gpr[1]), 843 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR2, gpr[2]), 844 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR3, gpr[3]), 845 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR4, gpr[4]), 846 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR5, gpr[5]), 847 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR6, gpr[6]), 848 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR7, gpr[7]), 849 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR8, gpr[8]), 850 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR9, gpr[9]), 851 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR10, gpr[10]), 852 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR11, gpr[11]), 853 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR12, gpr[12]), 854 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR13, gpr[13]), 855 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR14, gpr[14]), 856 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR15, gpr[15]), 857 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR16, gpr[16]), 858 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR17, gpr[17]), 859 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR18, gpr[18]), 860 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR19, gpr[19]), 861 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR20, gpr[20]), 862 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR21, gpr[21]), 863 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR22, gpr[22]), 864 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR23, gpr[23]), 865 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR24, gpr[24]), 866 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR25, gpr[25]), 867 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR26, gpr[26]), 868 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR27, gpr[27]), 869 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR28, gpr[28]), 870 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR29, gpr[29]), 871 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR30, gpr[30]), 872 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR31, gpr[31]), 873 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_NIA, nip), 874 GSE_ENV_DWM(GSB_VCPU_SPR_MSR, msr, HVMASK_MSR), 875 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTR, ctr), 876 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_LR, lr), 877 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_XER, xer), 878 GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_CR, cr), 879 GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_MMCR3), 880 GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER2), 881 GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER3), 882 GUEST_STATE_ELEMENT_NOP_W(GSB_VCPU_SPR_WORT), 883 GSE_ENV_DWM(GSB_VCPU_SPR_LPCR, lpcr, HVMASK_LPCR), 884 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMOR, amor), 885 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HFSCR, hfscr), 886 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR0, dawr0), 887 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX0, dawrx0), 888 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CIABR, ciabr), 889 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PURR, purr), 890 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPURR, spurr), 891 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IC, ic), 892 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_VTB, vtb), 893 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HDAR, hdar), 894 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HDSISR, hdsisr), 895 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HEIR, heir), 896 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_ASDR, asdr), 897 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR0, srr0), 898 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR1, srr1), 899 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG0, sprg0), 900 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG1, sprg1), 901 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG2, sprg2), 902 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG3, sprg3), 903 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PIDR, pidr), 904 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CFAR, cfar), 905 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PPR, ppr), 906 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR1, dawr1), 907 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX1, dawrx1), 908 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DEXCR, dexcr), 909 GSE_ENV_DWM(GSB_VCPU_SPR_HDEXCR, hdexcr, HVMASK_HDEXCR), 910 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHKEYR, hashkeyr), 911 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHPKEYR, hashpkeyr), 912 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR0, vsr[0]), 913 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR1, vsr[1]), 914 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR2, vsr[2]), 915 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR3, vsr[3]), 916 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR4, vsr[4]), 917 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR5, vsr[5]), 918 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR6, vsr[6]), 919 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR7, vsr[7]), 920 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR8, vsr[8]), 921 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR9, vsr[9]), 922 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR10, vsr[10]), 923 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR11, vsr[11]), 924 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR12, vsr[12]), 925 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR13, vsr[13]), 926 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR14, vsr[14]), 927 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR15, vsr[15]), 928 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR16, vsr[16]), 929 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR17, vsr[17]), 930 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR18, vsr[18]), 931 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR19, vsr[19]), 932 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR20, vsr[20]), 933 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR21, vsr[21]), 934 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR22, vsr[22]), 935 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR23, vsr[23]), 936 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR24, vsr[24]), 937 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR25, vsr[25]), 938 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR26, vsr[26]), 939 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR27, vsr[27]), 940 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR28, vsr[28]), 941 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR29, vsr[29]), 942 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR30, vsr[30]), 943 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR31, vsr[31]), 944 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR32, vsr[32]), 945 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR33, vsr[33]), 946 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR34, vsr[34]), 947 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR35, vsr[35]), 948 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR36, vsr[36]), 949 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR37, vsr[37]), 950 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR38, vsr[38]), 951 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR39, vsr[39]), 952 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR40, vsr[40]), 953 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR41, vsr[41]), 954 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR42, vsr[42]), 955 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR43, vsr[43]), 956 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR44, vsr[44]), 957 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR45, vsr[45]), 958 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR46, vsr[46]), 959 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR47, vsr[47]), 960 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR48, vsr[48]), 961 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR49, vsr[49]), 962 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR50, vsr[50]), 963 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR51, vsr[51]), 964 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR52, vsr[52]), 965 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR53, vsr[53]), 966 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR54, vsr[54]), 967 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR55, vsr[55]), 968 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR56, vsr[56]), 969 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR57, vsr[57]), 970 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR58, vsr[58]), 971 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR59, vsr[59]), 972 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR60, vsr[60]), 973 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR61, vsr[61]), 974 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR62, vsr[62]), 975 GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR63, vsr[63]), 976 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBHR, ebbhr), 977 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_TAR, tar), 978 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBRR, ebbrr), 979 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_BESCR, bescr), 980 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IAMR, iamr), 981 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMR, amr), 982 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_UAMOR, uamor), 983 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DSCR, dscr), 984 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FSCR, fscr), 985 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PSPB, pspb), 986 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTRL, ctrl), 987 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DPDES, dpdes), 988 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_VRSAVE, vrsave), 989 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAR, dar), 990 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DSISR, dsisr), 991 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC1, pmc1), 992 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC2, pmc2), 993 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC3, pmc3), 994 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC4, pmc4), 995 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC5, pmc5), 996 GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC6, pmc6), 997 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR0, mmcr0), 998 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR1, mmcr1), 999 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR2, mmcr2), 1000 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCRA, mmcra), 1001 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SDAR , sdar), 1002 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIAR , siar), 1003 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIER , sier), 1004 GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_VSCR, vscr), 1005 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FPSCR, fpscr), 1006 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_DEC_EXPIRE_TB, dec_expiry_tb), 1007 GSBE_NESTED(GSB_PART_SCOPED_PAGETBL, 0x18, parttbl[0], copy_state_pagetbl), 1008 GSBE_NESTED(GSB_PROCESS_TBL, 0x10, parttbl[1], copy_state_proctbl), 1009 GSBE_NESTED(GSB_VCPU_LPVR, 0x4, pvr_logical, copy_logical_pvr), 1010 GSBE_NESTED_MSK(GSB_TB_OFFSET, 0x8, tb_offset, copy_tb_offset, 1011 HVMASK_TB_OFFSET), 1012 GSBE_NESTED_VCPU(GSB_VCPU_IN_BUFFER, 0x10, runbufin, copy_state_runbuf), 1013 GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUFFER, 0x10, runbufout, copy_state_runbuf), 1014 GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUF_MIN_SZ, 0x8, runbufout, out_buf_min_size), 1015 GSBE_NESTED_VCPU(GSB_VCPU_HDEC_EXPIRY_TB, 0x8, hdecr_expiry_tb, 1016 copy_state_hdecr) 1017 }; 1018 1019 void spapr_nested_gsb_init(void) 1020 { 1021 struct guest_state_element_type *type; 1022 1023 /* Init the guest state elements lookup table, flags for now */ 1024 for (int i = 0; i < ARRAY_SIZE(guest_state_element_types); i++) { 1025 type = &guest_state_element_types[i]; 1026 1027 assert(type->id <= GSB_LAST); 1028 if (type->id >= GSB_VCPU_SPR_HDAR) 1029 /* 0xf000 - 0xf005 Thread + RO */ 1030 type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY; 1031 else if (type->id >= GSB_VCPU_IN_BUFFER) 1032 /* 0x0c00 - 0xf000 Thread + RW */ 1033 type->flags = 0; 1034 else if (type->id >= GSB_VCPU_LPVR) 1035 /* 0x0003 - 0x0bff Guest + RW */ 1036 type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE; 1037 else if (type->id >= GSB_HV_VCPU_STATE_SIZE) 1038 /* 0x0001 - 0x0002 Guest + RO */ 1039 type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY | 1040 GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE; 1041 } 1042 } 1043 1044 static struct guest_state_element *guest_state_element_next( 1045 struct guest_state_element *element, 1046 int64_t *len, 1047 int64_t *num_elements) 1048 { 1049 uint16_t size; 1050 1051 /* size is of element->value[] only. Not whole guest_state_element */ 1052 size = be16_to_cpu(element->size); 1053 1054 if (len) { 1055 *len -= size + offsetof(struct guest_state_element, value); 1056 } 1057 1058 if (num_elements) { 1059 *num_elements -= 1; 1060 } 1061 1062 return (struct guest_state_element *)(element->value + size); 1063 } 1064 1065 static 1066 struct guest_state_element_type *guest_state_element_type_find(uint16_t id) 1067 { 1068 int i; 1069 1070 for (i = 0; i < ARRAY_SIZE(guest_state_element_types); i++) 1071 if (id == guest_state_element_types[i].id) { 1072 return &guest_state_element_types[i]; 1073 } 1074 1075 return NULL; 1076 } 1077 1078 static void log_element(struct guest_state_element *element, 1079 struct guest_state_request *gsr) 1080 { 1081 qemu_log_mask(LOG_GUEST_ERROR, "h_guest_%s_state id:0x%04x size:0x%04x", 1082 gsr->flags & GUEST_STATE_REQUEST_SET ? "set" : "get", 1083 be16_to_cpu(element->id), be16_to_cpu(element->size)); 1084 qemu_log_mask(LOG_GUEST_ERROR, "buf:0x%016"PRIx64" ...\n", 1085 be64_to_cpu(*(uint64_t *)element->value)); 1086 } 1087 1088 static bool guest_state_request_check(struct guest_state_request *gsr) 1089 { 1090 int64_t num_elements, len = gsr->len; 1091 struct guest_state_buffer *gsb = gsr->gsb; 1092 struct guest_state_element *element; 1093 struct guest_state_element_type *type; 1094 uint16_t id, size; 1095 1096 /* gsb->num_elements = 0 == 32 bits long */ 1097 assert(len >= 4); 1098 1099 num_elements = be32_to_cpu(gsb->num_elements); 1100 element = gsb->elements; 1101 len -= sizeof(gsb->num_elements); 1102 1103 /* Walk the buffer to validate the length */ 1104 while (num_elements) { 1105 1106 id = be16_to_cpu(element->id); 1107 size = be16_to_cpu(element->size); 1108 1109 if (false) { 1110 log_element(element, gsr); 1111 } 1112 /* buffer size too small */ 1113 if (len < 0) { 1114 return false; 1115 } 1116 1117 type = guest_state_element_type_find(id); 1118 if (!type) { 1119 qemu_log_mask(LOG_GUEST_ERROR, "Element ID %04x unknown\n", id); 1120 log_element(element, gsr); 1121 return false; 1122 } 1123 1124 if (id == GSB_HV_VCPU_IGNORED_ID) { 1125 goto next_element; 1126 } 1127 1128 if (size != type->size) { 1129 qemu_log_mask(LOG_GUEST_ERROR, "Size mismatch. Element ID:%04x." 1130 "Size Exp:%i Got:%i\n", id, type->size, size); 1131 log_element(element, gsr); 1132 return false; 1133 } 1134 1135 if ((type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY) && 1136 (gsr->flags & GUEST_STATE_REQUEST_SET)) { 1137 qemu_log_mask(LOG_GUEST_ERROR, "Trying to set a read-only Element " 1138 "ID:%04x.\n", id); 1139 return false; 1140 } 1141 1142 if (type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE) { 1143 /* guest wide element type */ 1144 if (!(gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE)) { 1145 qemu_log_mask(LOG_GUEST_ERROR, "trying to set a guest wide " 1146 "Element ID:%04x.\n", id); 1147 return false; 1148 } 1149 } else { 1150 /* thread wide element type */ 1151 if (gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE) { 1152 qemu_log_mask(LOG_GUEST_ERROR, "trying to set a thread wide " 1153 "Element ID:%04x.\n", id); 1154 return false; 1155 } 1156 } 1157 next_element: 1158 element = guest_state_element_next(element, &len, &num_elements); 1159 1160 } 1161 return true; 1162 } 1163 1164 static bool is_gsr_invalid(struct guest_state_request *gsr, 1165 struct guest_state_element *element, 1166 struct guest_state_element_type *type) 1167 { 1168 if ((gsr->flags & GUEST_STATE_REQUEST_SET) && 1169 (*(uint64_t *)(element->value) & ~(type->mask))) { 1170 log_element(element, gsr); 1171 qemu_log_mask(LOG_GUEST_ERROR, "L1 can't set reserved bits " 1172 "(allowed mask: 0x%08"PRIx64")\n", type->mask); 1173 return true; 1174 } 1175 return false; 1176 } 1177 1178 static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu, 1179 SpaprMachineState *spapr, 1180 target_ulong opcode, 1181 target_ulong *args) 1182 { 1183 CPUPPCState *env = &cpu->env; 1184 target_ulong flags = args[0]; 1185 1186 if (flags) { /* don't handle any flags capabilities for now */ 1187 return H_PARAMETER; 1188 } 1189 1190 /* P11 capabilities */ 1191 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0, 1192 spapr->max_compat_pvr)) { 1193 env->gpr[4] |= H_GUEST_CAPABILITIES_P11_MODE; 1194 } 1195 1196 /* P10 capabilities */ 1197 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, 1198 spapr->max_compat_pvr)) { 1199 env->gpr[4] |= H_GUEST_CAPABILITIES_P10_MODE; 1200 } 1201 1202 /* P9 capabilities */ 1203 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1204 spapr->max_compat_pvr)) { 1205 env->gpr[4] |= H_GUEST_CAPABILITIES_P9_MODE; 1206 } 1207 1208 return H_SUCCESS; 1209 } 1210 1211 static target_ulong h_guest_set_capabilities(PowerPCCPU *cpu, 1212 SpaprMachineState *spapr, 1213 target_ulong opcode, 1214 target_ulong *args) 1215 { 1216 CPUPPCState *env = &cpu->env; 1217 target_ulong flags = args[0]; 1218 target_ulong capabilities = args[1]; 1219 env->gpr[4] = 0; 1220 1221 if (flags) { /* don't handle any flags capabilities for now */ 1222 return H_PARAMETER; 1223 } 1224 1225 if (capabilities & H_GUEST_CAPABILITIES_COPY_MEM) { 1226 env->gpr[4] = 1; 1227 return H_P2; /* isn't supported */ 1228 } 1229 1230 /* 1231 * If there are no capabilities configured, set the R5 to the index of 1232 * the first supported Power Processor Mode 1233 */ 1234 if (!capabilities) { 1235 env->gpr[4] = 1; 1236 1237 /* set R5 to the first supported Power Processor Mode */ 1238 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0, 1239 spapr->max_compat_pvr)) { 1240 env->gpr[5] = H_GUEST_CAP_P11_MODE_BMAP; 1241 } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, 1242 spapr->max_compat_pvr)) { 1243 env->gpr[5] = H_GUEST_CAP_P10_MODE_BMAP; 1244 } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1245 spapr->max_compat_pvr)) { 1246 env->gpr[5] = H_GUEST_CAP_P9_MODE_BMAP; 1247 } 1248 1249 return H_P2; 1250 } 1251 1252 /* 1253 * If an invalid capability is set, R5 should contain the index of the 1254 * invalid capability bit 1255 */ 1256 if (capabilities & ~H_GUEST_CAP_VALID_MASK) { 1257 env->gpr[4] = 1; 1258 1259 /* Set R5 to the index of the invalid capability */ 1260 env->gpr[5] = 63 - ctz64(capabilities); 1261 1262 return H_P2; 1263 } 1264 1265 if (!spapr->nested.capabilities_set) { 1266 spapr->nested.capabilities_set = true; 1267 spapr->nested.pvr_base = env->spr[SPR_PVR]; 1268 return H_SUCCESS; 1269 } else { 1270 return H_STATE; 1271 } 1272 } 1273 1274 static void 1275 destroy_guest_helper(gpointer value) 1276 { 1277 struct SpaprMachineStateNestedGuest *guest = value; 1278 g_free(guest->vcpus); 1279 g_free(guest); 1280 } 1281 1282 static target_ulong h_guest_create(PowerPCCPU *cpu, 1283 SpaprMachineState *spapr, 1284 target_ulong opcode, 1285 target_ulong *args) 1286 { 1287 CPUPPCState *env = &cpu->env; 1288 target_ulong flags = args[0]; 1289 target_ulong continue_token = args[1]; 1290 uint64_t guestid; 1291 int nguests = 0; 1292 struct SpaprMachineStateNestedGuest *guest; 1293 1294 if (flags) { /* don't handle any flags for now */ 1295 return H_UNSUPPORTED_FLAG; 1296 } 1297 1298 if (continue_token != -1) { 1299 return H_P2; 1300 } 1301 1302 if (!spapr->nested.capabilities_set) { 1303 return H_STATE; 1304 } 1305 1306 if (!spapr->nested.guests) { 1307 spapr->nested.guests = g_hash_table_new_full(NULL, 1308 NULL, 1309 NULL, 1310 destroy_guest_helper); 1311 } 1312 1313 nguests = g_hash_table_size(spapr->nested.guests); 1314 1315 if (nguests == PAPR_NESTED_GUEST_MAX) { 1316 return H_NO_MEM; 1317 } 1318 1319 /* Lookup for available guestid */ 1320 for (guestid = 1; guestid < PAPR_NESTED_GUEST_MAX; guestid++) { 1321 if (!(g_hash_table_lookup(spapr->nested.guests, 1322 GINT_TO_POINTER(guestid)))) { 1323 break; 1324 } 1325 } 1326 1327 if (guestid == PAPR_NESTED_GUEST_MAX) { 1328 return H_NO_MEM; 1329 } 1330 1331 guest = g_try_new0(struct SpaprMachineStateNestedGuest, 1); 1332 if (!guest) { 1333 return H_NO_MEM; 1334 } 1335 1336 guest->pvr_logical = spapr->nested.pvr_base; 1337 g_hash_table_insert(spapr->nested.guests, GINT_TO_POINTER(guestid), guest); 1338 env->gpr[4] = guestid; 1339 1340 return H_SUCCESS; 1341 } 1342 1343 static target_ulong h_guest_delete(PowerPCCPU *cpu, 1344 SpaprMachineState *spapr, 1345 target_ulong opcode, 1346 target_ulong *args) 1347 { 1348 target_ulong flags = args[0]; 1349 target_ulong guestid = args[1]; 1350 struct SpaprMachineStateNestedGuest *guest; 1351 1352 /* 1353 * handle flag deleteAllGuests, if set: 1354 * guestid is ignored and all guests are deleted 1355 * 1356 */ 1357 if (flags & ~H_GUEST_DELETE_ALL_FLAG) { 1358 return H_UNSUPPORTED_FLAG; /* other flag bits reserved */ 1359 } else if (flags & H_GUEST_DELETE_ALL_FLAG) { 1360 g_hash_table_destroy(spapr->nested.guests); 1361 return H_SUCCESS; 1362 } 1363 1364 guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid)); 1365 if (!guest) { 1366 return H_P2; 1367 } 1368 1369 g_hash_table_remove(spapr->nested.guests, GINT_TO_POINTER(guestid)); 1370 1371 return H_SUCCESS; 1372 } 1373 1374 static target_ulong h_guest_create_vcpu(PowerPCCPU *cpu, 1375 SpaprMachineState *spapr, 1376 target_ulong opcode, 1377 target_ulong *args) 1378 { 1379 target_ulong flags = args[0]; 1380 target_ulong guestid = args[1]; 1381 target_ulong vcpuid = args[2]; 1382 SpaprMachineStateNestedGuest *guest; 1383 1384 if (flags) { /* don't handle any flags for now */ 1385 return H_UNSUPPORTED_FLAG; 1386 } 1387 1388 guest = spapr_get_nested_guest(spapr, guestid); 1389 if (!guest) { 1390 return H_P2; 1391 } 1392 1393 if (vcpuid < guest->nr_vcpus) { 1394 qemu_log_mask(LOG_UNIMP, "vcpuid " TARGET_FMT_ld " already in use.", 1395 vcpuid); 1396 return H_IN_USE; 1397 } 1398 /* linear vcpuid allocation only */ 1399 assert(vcpuid == guest->nr_vcpus); 1400 1401 if (guest->nr_vcpus >= PAPR_NESTED_GUEST_VCPU_MAX) { 1402 return H_P3; 1403 } 1404 1405 SpaprMachineStateNestedGuestVcpu *vcpus, *curr_vcpu; 1406 vcpus = g_try_renew(struct SpaprMachineStateNestedGuestVcpu, 1407 guest->vcpus, 1408 guest->nr_vcpus + 1); 1409 if (!vcpus) { 1410 return H_NO_MEM; 1411 } 1412 guest->vcpus = vcpus; 1413 curr_vcpu = &vcpus[guest->nr_vcpus]; 1414 memset(curr_vcpu, 0, sizeof(SpaprMachineStateNestedGuestVcpu)); 1415 1416 curr_vcpu->enabled = true; 1417 guest->nr_vcpus++; 1418 1419 return H_SUCCESS; 1420 } 1421 1422 static target_ulong getset_state(SpaprMachineStateNestedGuest *guest, 1423 uint64_t vcpuid, 1424 struct guest_state_request *gsr) 1425 { 1426 void *ptr; 1427 uint16_t id; 1428 struct guest_state_element *element; 1429 struct guest_state_element_type *type; 1430 int64_t lenleft, num_elements; 1431 1432 lenleft = gsr->len; 1433 1434 if (!guest_state_request_check(gsr)) { 1435 return H_P3; 1436 } 1437 1438 num_elements = be32_to_cpu(gsr->gsb->num_elements); 1439 element = gsr->gsb->elements; 1440 /* Process the elements */ 1441 while (num_elements) { 1442 type = NULL; 1443 /* log_element(element, gsr); */ 1444 1445 id = be16_to_cpu(element->id); 1446 if (id == GSB_HV_VCPU_IGNORED_ID) { 1447 goto next_element; 1448 } 1449 1450 type = guest_state_element_type_find(id); 1451 assert(type); 1452 1453 /* Get pointer to guest data to get/set */ 1454 if (type->location && type->copy) { 1455 ptr = type->location(guest, vcpuid); 1456 assert(ptr); 1457 if (!~(type->mask) && is_gsr_invalid(gsr, element, type)) { 1458 return H_INVALID_ELEMENT_VALUE; 1459 } 1460 type->copy(ptr + type->offset, element->value, 1461 gsr->flags & GUEST_STATE_REQUEST_SET ? true : false); 1462 } 1463 1464 next_element: 1465 element = guest_state_element_next(element, &lenleft, &num_elements); 1466 } 1467 1468 return H_SUCCESS; 1469 } 1470 1471 static target_ulong map_and_getset_state(PowerPCCPU *cpu, 1472 SpaprMachineStateNestedGuest *guest, 1473 uint64_t vcpuid, 1474 struct guest_state_request *gsr) 1475 { 1476 target_ulong rc; 1477 int64_t len; 1478 bool is_write; 1479 1480 len = gsr->len; 1481 /* only get_state would require write access to the provided buffer */ 1482 is_write = (gsr->flags & GUEST_STATE_REQUEST_SET) ? false : true; 1483 gsr->gsb = address_space_map(CPU(cpu)->as, gsr->buf, (uint64_t *)&len, 1484 is_write, MEMTXATTRS_UNSPECIFIED); 1485 if (!gsr->gsb) { 1486 rc = H_P3; 1487 goto out1; 1488 } 1489 1490 if (len != gsr->len) { 1491 rc = H_P3; 1492 goto out1; 1493 } 1494 1495 rc = getset_state(guest, vcpuid, gsr); 1496 1497 out1: 1498 address_space_unmap(CPU(cpu)->as, gsr->gsb, len, is_write, len); 1499 return rc; 1500 } 1501 1502 static target_ulong h_guest_getset_state(PowerPCCPU *cpu, 1503 SpaprMachineState *spapr, 1504 target_ulong *args, 1505 bool set) 1506 { 1507 target_ulong flags = args[0]; 1508 target_ulong lpid = args[1]; 1509 target_ulong vcpuid = args[2]; 1510 target_ulong buf = args[3]; 1511 target_ulong buflen = args[4]; 1512 struct guest_state_request gsr; 1513 SpaprMachineStateNestedGuest *guest; 1514 1515 guest = spapr_get_nested_guest(spapr, lpid); 1516 if (!guest) { 1517 return H_P2; 1518 } 1519 gsr.buf = buf; 1520 assert(buflen <= GSB_MAX_BUF_SIZE); 1521 gsr.len = buflen; 1522 gsr.flags = 0; 1523 if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) { 1524 gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE; 1525 } 1526 if (flags & ~H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) { 1527 return H_PARAMETER; /* flag not supported yet */ 1528 } 1529 1530 if (set) { 1531 gsr.flags |= GUEST_STATE_REQUEST_SET; 1532 } 1533 return map_and_getset_state(cpu, guest, vcpuid, &gsr); 1534 } 1535 1536 static target_ulong h_guest_set_state(PowerPCCPU *cpu, 1537 SpaprMachineState *spapr, 1538 target_ulong opcode, 1539 target_ulong *args) 1540 { 1541 return h_guest_getset_state(cpu, spapr, args, true); 1542 } 1543 1544 static target_ulong h_guest_get_state(PowerPCCPU *cpu, 1545 SpaprMachineState *spapr, 1546 target_ulong opcode, 1547 target_ulong *args) 1548 { 1549 return h_guest_getset_state(cpu, spapr, args, false); 1550 } 1551 1552 static void exit_nested_store_l2(PowerPCCPU *cpu, int excp, 1553 SpaprMachineStateNestedGuestVcpu *vcpu) 1554 { 1555 CPUPPCState *env = &cpu->env; 1556 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1557 target_ulong now, hdar, hdsisr, asdr; 1558 1559 assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr)); /* sanity check */ 1560 1561 now = cpu_ppc_load_tbl(env); /* L2 timebase */ 1562 now -= vcpu->tb_offset; /* L1 timebase */ 1563 vcpu->state.dec_expiry_tb = now - cpu_ppc_load_decr(env); 1564 cpu_ppc_store_decr(env, spapr_cpu->nested_host_state->dec_expiry_tb - now); 1565 /* backup hdar, hdsisr, asdr if reqd later below */ 1566 hdar = vcpu->state.hdar; 1567 hdsisr = vcpu->state.hdsisr; 1568 asdr = vcpu->state.asdr; 1569 1570 nested_save_state(&vcpu->state, cpu); 1571 1572 if (excp == POWERPC_EXCP_MCHECK || 1573 excp == POWERPC_EXCP_RESET || 1574 excp == POWERPC_EXCP_SYSCALL) { 1575 vcpu->state.nip = env->spr[SPR_SRR0]; 1576 vcpu->state.msr = env->spr[SPR_SRR1] & env->msr_mask; 1577 } else { 1578 vcpu->state.nip = env->spr[SPR_HSRR0]; 1579 vcpu->state.msr = env->spr[SPR_HSRR1] & env->msr_mask; 1580 } 1581 1582 /* hdar, hdsisr, asdr should be retained unless certain exceptions */ 1583 if ((excp != POWERPC_EXCP_HDSI) && (excp != POWERPC_EXCP_HISI)) { 1584 vcpu->state.asdr = asdr; 1585 } else if (excp != POWERPC_EXCP_HDSI) { 1586 vcpu->state.hdar = hdar; 1587 vcpu->state.hdsisr = hdsisr; 1588 } 1589 } 1590 1591 static int get_exit_ids(uint64_t srr0, uint16_t ids[16]) 1592 { 1593 int nr; 1594 1595 switch (srr0) { 1596 case 0xc00: 1597 nr = 10; 1598 ids[0] = GSB_VCPU_GPR3; 1599 ids[1] = GSB_VCPU_GPR4; 1600 ids[2] = GSB_VCPU_GPR5; 1601 ids[3] = GSB_VCPU_GPR6; 1602 ids[4] = GSB_VCPU_GPR7; 1603 ids[5] = GSB_VCPU_GPR8; 1604 ids[6] = GSB_VCPU_GPR9; 1605 ids[7] = GSB_VCPU_GPR10; 1606 ids[8] = GSB_VCPU_GPR11; 1607 ids[9] = GSB_VCPU_GPR12; 1608 break; 1609 case 0xe00: 1610 nr = 5; 1611 ids[0] = GSB_VCPU_SPR_HDAR; 1612 ids[1] = GSB_VCPU_SPR_HDSISR; 1613 ids[2] = GSB_VCPU_SPR_ASDR; 1614 ids[3] = GSB_VCPU_SPR_NIA; 1615 ids[4] = GSB_VCPU_SPR_MSR; 1616 break; 1617 case 0xe20: 1618 nr = 4; 1619 ids[0] = GSB_VCPU_SPR_HDAR; 1620 ids[1] = GSB_VCPU_SPR_ASDR; 1621 ids[2] = GSB_VCPU_SPR_NIA; 1622 ids[3] = GSB_VCPU_SPR_MSR; 1623 break; 1624 case 0xe40: 1625 nr = 3; 1626 ids[0] = GSB_VCPU_SPR_HEIR; 1627 ids[1] = GSB_VCPU_SPR_NIA; 1628 ids[2] = GSB_VCPU_SPR_MSR; 1629 break; 1630 case 0xf80: 1631 nr = 3; 1632 ids[0] = GSB_VCPU_SPR_HFSCR; 1633 ids[1] = GSB_VCPU_SPR_NIA; 1634 ids[2] = GSB_VCPU_SPR_MSR; 1635 break; 1636 default: 1637 nr = 0; 1638 break; 1639 } 1640 1641 return nr; 1642 } 1643 1644 static void exit_process_output_buffer(PowerPCCPU *cpu, 1645 SpaprMachineStateNestedGuest *guest, 1646 target_ulong vcpuid, 1647 target_ulong *r3) 1648 { 1649 SpaprMachineStateNestedGuestVcpu *vcpu = &guest->vcpus[vcpuid]; 1650 struct guest_state_request gsr; 1651 struct guest_state_buffer *gsb; 1652 struct guest_state_element *element; 1653 struct guest_state_element_type *type; 1654 int exit_id_count = 0; 1655 uint16_t exit_cause_ids[16]; 1656 hwaddr len; 1657 1658 len = vcpu->runbufout.size; 1659 gsb = address_space_map(CPU(cpu)->as, vcpu->runbufout.addr, &len, true, 1660 MEMTXATTRS_UNSPECIFIED); 1661 if (!gsb || len != vcpu->runbufout.size) { 1662 address_space_unmap(CPU(cpu)->as, gsb, len, true, len); 1663 *r3 = H_P2; 1664 return; 1665 } 1666 1667 exit_id_count = get_exit_ids(*r3, exit_cause_ids); 1668 1669 /* Create a buffer of elements to send back */ 1670 gsb->num_elements = cpu_to_be32(exit_id_count); 1671 element = gsb->elements; 1672 for (int i = 0; i < exit_id_count; i++) { 1673 type = guest_state_element_type_find(exit_cause_ids[i]); 1674 assert(type); 1675 element->id = cpu_to_be16(exit_cause_ids[i]); 1676 element->size = cpu_to_be16(type->size); 1677 element = guest_state_element_next(element, NULL, NULL); 1678 } 1679 gsr.gsb = gsb; 1680 gsr.len = VCPU_OUT_BUF_MIN_SZ; 1681 gsr.flags = 0; /* get + never guest wide */ 1682 getset_state(guest, vcpuid, &gsr); 1683 1684 address_space_unmap(CPU(cpu)->as, gsb, len, true, len); 1685 return; 1686 } 1687 1688 static 1689 void spapr_exit_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, int excp) 1690 { 1691 CPUPPCState *env = &cpu->env; 1692 CPUState *cs = CPU(cpu); 1693 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1694 target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */ 1695 target_ulong lpid = 0, vcpuid = 0; 1696 struct SpaprMachineStateNestedGuestVcpu *vcpu = NULL; 1697 struct SpaprMachineStateNestedGuest *guest = NULL; 1698 1699 lpid = spapr_cpu->nested_host_state->gpr[5]; 1700 vcpuid = spapr_cpu->nested_host_state->gpr[6]; 1701 guest = spapr_get_nested_guest(spapr, lpid); 1702 assert(guest); 1703 spapr_nested_vcpu_check(guest, vcpuid, false); 1704 vcpu = &guest->vcpus[vcpuid]; 1705 1706 exit_nested_store_l2(cpu, excp, vcpu); 1707 /* do the output buffer for run_vcpu*/ 1708 exit_process_output_buffer(cpu, guest, vcpuid, &r3_return); 1709 1710 assert(env->spr[SPR_LPIDR] != 0); 1711 nested_load_state(cpu, spapr_cpu->nested_host_state); 1712 cpu_ppc_decrease_tb_by_offset(env, vcpu->tb_offset); 1713 env->gpr[3] = H_SUCCESS; 1714 env->gpr[4] = r3_return; 1715 nested_post_load_state(env, cs); 1716 cpu_ppc_hdecr_exit(env); 1717 1718 spapr_cpu->in_nested = false; 1719 g_free(spapr_cpu->nested_host_state); 1720 spapr_cpu->nested_host_state = NULL; 1721 } 1722 1723 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 1724 { 1725 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1726 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1727 1728 assert(spapr_cpu->in_nested); 1729 if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) { 1730 spapr_exit_nested_hv(cpu, excp); 1731 } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) { 1732 spapr_exit_nested_papr(spapr, cpu, excp); 1733 } else { 1734 g_assert_not_reached(); 1735 } 1736 } 1737 1738 static void nested_papr_load_l2(PowerPCCPU *cpu, 1739 CPUPPCState *env, 1740 SpaprMachineStateNestedGuestVcpu *vcpu, 1741 target_ulong now) 1742 { 1743 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1744 target_ulong lpcr, lpcr_mask, hdec; 1745 lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; 1746 1747 assert(vcpu); 1748 assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr)); 1749 nested_load_state(cpu, &vcpu->state); 1750 lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | 1751 (vcpu->state.lpcr & lpcr_mask); 1752 lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; 1753 lpcr &= ~LPCR_LPES0; 1754 env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask; 1755 1756 hdec = vcpu->hdecr_expiry_tb - now; 1757 cpu_ppc_store_decr(env, vcpu->state.dec_expiry_tb - now); 1758 cpu_ppc_hdecr_init(env); 1759 cpu_ppc_store_hdecr(env, hdec); 1760 1761 cpu_ppc_increase_tb_by_offset(env, vcpu->tb_offset); 1762 } 1763 1764 static void nested_papr_run_vcpu(PowerPCCPU *cpu, 1765 uint64_t lpid, 1766 SpaprMachineStateNestedGuestVcpu *vcpu) 1767 { 1768 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1769 CPUPPCState *env = &cpu->env; 1770 CPUState *cs = CPU(cpu); 1771 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1772 target_ulong now = cpu_ppc_load_tbl(env); 1773 1774 assert(env->spr[SPR_LPIDR] == 0); 1775 assert(spapr->nested.api); /* ensure API version is initialized */ 1776 spapr_cpu->nested_host_state = g_try_new(struct nested_ppc_state, 1); 1777 assert(spapr_cpu->nested_host_state); 1778 nested_save_state(spapr_cpu->nested_host_state, cpu); 1779 spapr_cpu->nested_host_state->dec_expiry_tb = now - cpu_ppc_load_decr(env); 1780 nested_papr_load_l2(cpu, env, vcpu, now); 1781 env->spr[SPR_LPIDR] = lpid; /* post load l2 */ 1782 1783 spapr_cpu->in_nested = true; 1784 nested_post_load_state(env, cs); 1785 } 1786 1787 static target_ulong h_guest_run_vcpu(PowerPCCPU *cpu, 1788 SpaprMachineState *spapr, 1789 target_ulong opcode, 1790 target_ulong *args) 1791 { 1792 CPUPPCState *env = &cpu->env; 1793 target_ulong flags = args[0]; 1794 target_ulong lpid = args[1]; 1795 target_ulong vcpuid = args[2]; 1796 struct SpaprMachineStateNestedGuestVcpu *vcpu; 1797 struct guest_state_request gsr; 1798 SpaprMachineStateNestedGuest *guest; 1799 target_ulong rc; 1800 1801 if (flags) /* don't handle any flags for now */ 1802 return H_PARAMETER; 1803 1804 guest = spapr_get_nested_guest(spapr, lpid); 1805 if (!guest) { 1806 return H_P2; 1807 } 1808 if (!spapr_nested_vcpu_check(guest, vcpuid, true)) { 1809 return H_P3; 1810 } 1811 1812 if (guest->parttbl[0] == 0) { 1813 /* At least need a partition scoped radix tree */ 1814 return H_NOT_AVAILABLE; 1815 } 1816 1817 vcpu = &guest->vcpus[vcpuid]; 1818 1819 /* Read run_vcpu input buffer to update state */ 1820 gsr.buf = vcpu->runbufin.addr; 1821 gsr.len = vcpu->runbufin.size; 1822 gsr.flags = GUEST_STATE_REQUEST_SET; /* Thread wide + writing */ 1823 rc = map_and_getset_state(cpu, guest, vcpuid, &gsr); 1824 if (rc == H_SUCCESS) { 1825 nested_papr_run_vcpu(cpu, lpid, vcpu); 1826 } else { 1827 env->gpr[3] = rc; 1828 } 1829 return env->gpr[3]; 1830 } 1831 1832 void spapr_register_nested_hv(void) 1833 { 1834 spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); 1835 spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested); 1836 spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate); 1837 spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest); 1838 } 1839 1840 void spapr_unregister_nested_hv(void) 1841 { 1842 spapr_unregister_hypercall(KVMPPC_H_SET_PARTITION_TABLE); 1843 spapr_unregister_hypercall(KVMPPC_H_ENTER_NESTED); 1844 spapr_unregister_hypercall(KVMPPC_H_TLB_INVALIDATE); 1845 spapr_unregister_hypercall(KVMPPC_H_COPY_TOFROM_GUEST); 1846 } 1847 1848 void spapr_register_nested_papr(void) 1849 { 1850 spapr_register_hypercall(H_GUEST_GET_CAPABILITIES, 1851 h_guest_get_capabilities); 1852 spapr_register_hypercall(H_GUEST_SET_CAPABILITIES, 1853 h_guest_set_capabilities); 1854 spapr_register_hypercall(H_GUEST_CREATE, h_guest_create); 1855 spapr_register_hypercall(H_GUEST_DELETE, h_guest_delete); 1856 spapr_register_hypercall(H_GUEST_CREATE_VCPU, h_guest_create_vcpu); 1857 spapr_register_hypercall(H_GUEST_SET_STATE, h_guest_set_state); 1858 spapr_register_hypercall(H_GUEST_GET_STATE, h_guest_get_state); 1859 spapr_register_hypercall(H_GUEST_RUN_VCPU, h_guest_run_vcpu); 1860 } 1861 1862 void spapr_unregister_nested_papr(void) 1863 { 1864 spapr_unregister_hypercall(H_GUEST_GET_CAPABILITIES); 1865 spapr_unregister_hypercall(H_GUEST_SET_CAPABILITIES); 1866 spapr_unregister_hypercall(H_GUEST_CREATE); 1867 spapr_unregister_hypercall(H_GUEST_DELETE); 1868 spapr_unregister_hypercall(H_GUEST_CREATE_VCPU); 1869 spapr_unregister_hypercall(H_GUEST_SET_STATE); 1870 spapr_unregister_hypercall(H_GUEST_GET_STATE); 1871 spapr_unregister_hypercall(H_GUEST_RUN_VCPU); 1872 } 1873 1874 #else 1875 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 1876 { 1877 g_assert_not_reached(); 1878 } 1879 1880 void spapr_register_nested_hv(void) 1881 { 1882 /* DO NOTHING */ 1883 } 1884 1885 void spapr_unregister_nested_hv(void) 1886 { 1887 /* DO NOTHING */ 1888 } 1889 1890 bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, 1891 target_ulong lpid, ppc_v3_pate_t *entry) 1892 { 1893 return false; 1894 } 1895 1896 bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, 1897 target_ulong lpid, ppc_v3_pate_t *entry) 1898 { 1899 return false; 1900 } 1901 1902 void spapr_register_nested_papr(void) 1903 { 1904 /* DO NOTHING */ 1905 } 1906 1907 void spapr_unregister_nested_papr(void) 1908 { 1909 /* DO NOTHING */ 1910 } 1911 1912 void spapr_nested_gsb_init(void) 1913 { 1914 /* DO NOTHING */ 1915 } 1916 1917 #endif 1918