xref: /qemu/hw/ppc/spapr_irq.c (revision db592b5b16b4f2821b8bb3f4f46825d660d2d4c2) 
1 /*
2  * QEMU PowerPC sPAPR IRQ interface
3  *
4  * Copyright (c) 2018, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include "hw/ppc/spapr.h"
15 #include "hw/ppc/spapr_xive.h"
16 #include "hw/ppc/xics.h"
17 #include "sysemu/kvm.h"
18 
19 #include "trace.h"
20 
21 void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
22 {
23     spapr->irq_map_nr = nr_msis;
24     spapr->irq_map = bitmap_new(spapr->irq_map_nr);
25 }
26 
27 int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
28                         Error **errp)
29 {
30     int irq;
31 
32     /*
33      * The 'align_mask' parameter of bitmap_find_next_zero_area()
34      * should be one less than a power of 2; 0 means no
35      * alignment. Adapt the 'align' value of the former allocator
36      * to fit the requirements of bitmap_find_next_zero_area()
37      */
38     align -= 1;
39 
40     irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
41                                      align);
42     if (irq == spapr->irq_map_nr) {
43         error_setg(errp, "can't find a free %d-IRQ block", num);
44         return -1;
45     }
46 
47     bitmap_set(spapr->irq_map, irq, num);
48 
49     return irq + SPAPR_IRQ_MSI;
50 }
51 
52 void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
53 {
54     bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
55 }
56 
57 void spapr_irq_msi_reset(sPAPRMachineState *spapr)
58 {
59     bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
60 }
61 
62 
63 /*
64  * XICS IRQ backend.
65  */
66 
67 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
68                                   const char *type_ics,
69                                   int nr_irqs, Error **errp)
70 {
71     Error *local_err = NULL;
72     Object *obj;
73 
74     obj = object_new(type_ics);
75     object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
76     object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
77                                    &error_abort);
78     object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
79     if (local_err) {
80         goto error;
81     }
82     object_property_set_bool(obj, true, "realized", &local_err);
83     if (local_err) {
84         goto error;
85     }
86 
87     return ICS_BASE(obj);
88 
89 error:
90     error_propagate(errp, local_err);
91     return NULL;
92 }
93 
94 static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
95 {
96     MachineState *machine = MACHINE(spapr);
97     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
98     int nr_irqs = smc->irq->nr_irqs;
99     Error *local_err = NULL;
100 
101     if (kvm_enabled()) {
102         if (machine_kernel_irqchip_allowed(machine) &&
103             !xics_kvm_init(spapr, &local_err)) {
104             spapr->icp_type = TYPE_KVM_ICP;
105             spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
106                                           &local_err);
107         }
108         if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
109             error_prepend(&local_err,
110                           "kernel_irqchip requested but unavailable: ");
111             goto error;
112         }
113         error_free(local_err);
114         local_err = NULL;
115     }
116 
117     if (!spapr->ics) {
118         xics_spapr_init(spapr);
119         spapr->icp_type = TYPE_ICP;
120         spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
121                                       &local_err);
122     }
123 
124 error:
125     error_propagate(errp, local_err);
126 }
127 
128 #define ICS_IRQ_FREE(ics, srcno)   \
129     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
130 
131 static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
132                                 Error **errp)
133 {
134     ICSState *ics = spapr->ics;
135 
136     assert(ics);
137 
138     if (!ics_valid_irq(ics, irq)) {
139         error_setg(errp, "IRQ %d is invalid", irq);
140         return -1;
141     }
142 
143     if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
144         error_setg(errp, "IRQ %d is not free", irq);
145         return -1;
146     }
147 
148     ics_set_irq_type(ics, irq - ics->offset, lsi);
149     return 0;
150 }
151 
152 static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
153 {
154     ICSState *ics = spapr->ics;
155     uint32_t srcno = irq - ics->offset;
156     int i;
157 
158     if (ics_valid_irq(ics, irq)) {
159         trace_spapr_irq_free(0, irq, num);
160         for (i = srcno; i < srcno + num; ++i) {
161             if (ICS_IRQ_FREE(ics, i)) {
162                 trace_spapr_irq_free_warn(0, i);
163             }
164             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
165         }
166     }
167 }
168 
169 static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
170 {
171     ICSState *ics = spapr->ics;
172     uint32_t srcno = irq - ics->offset;
173 
174     if (ics_valid_irq(ics, irq)) {
175         return ics->qirqs[srcno];
176     }
177 
178     return NULL;
179 }
180 
181 static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
182 {
183     CPUState *cs;
184 
185     CPU_FOREACH(cs) {
186         PowerPCCPU *cpu = POWERPC_CPU(cs);
187 
188         icp_pic_print_info(ICP(cpu->intc), mon);
189     }
190 
191     ics_pic_print_info(spapr->ics, mon);
192 }
193 
194 static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
195                                               Object *cpu, Error **errp)
196 {
197     return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
198 }
199 
200 static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
201 {
202     if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
203         CPUState *cs;
204         CPU_FOREACH(cs) {
205             PowerPCCPU *cpu = POWERPC_CPU(cs);
206             icp_resend(ICP(cpu->intc));
207         }
208     }
209     return 0;
210 }
211 
212 #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
213 #define SPAPR_IRQ_XICS_NR_MSIS     \
214     (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
215 
216 sPAPRIrq spapr_irq_xics = {
217     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
218     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
219     .ov5         = SPAPR_OV5_XIVE_LEGACY,
220 
221     .init        = spapr_irq_init_xics,
222     .claim       = spapr_irq_claim_xics,
223     .free        = spapr_irq_free_xics,
224     .qirq        = spapr_qirq_xics,
225     .print_info  = spapr_irq_print_info_xics,
226     .dt_populate = spapr_dt_xics,
227     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
228     .post_load   = spapr_irq_post_load_xics,
229 };
230 
231 /*
232  * XIVE IRQ backend.
233  */
234 static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
235 {
236     MachineState *machine = MACHINE(spapr);
237     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
238     uint32_t nr_servers = spapr_max_server_number(spapr);
239     DeviceState *dev;
240     int i;
241 
242     /* KVM XIVE device not yet available */
243     if (kvm_enabled()) {
244         if (machine_kernel_irqchip_required(machine)) {
245             error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
246             return;
247         }
248     }
249 
250     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
251     qdev_prop_set_uint32(dev, "nr-irqs", smc->irq->nr_irqs);
252     /*
253      * 8 XIVE END structures per CPU. One for each available priority
254      */
255     qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
256     qdev_init_nofail(dev);
257 
258     spapr->xive = SPAPR_XIVE(dev);
259 
260     /* Enable the CPU IPIs */
261     for (i = 0; i < nr_servers; ++i) {
262         spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
263     }
264 
265     spapr_xive_hcall_init(spapr);
266 }
267 
268 static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
269                                 Error **errp)
270 {
271     if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
272         error_setg(errp, "IRQ %d is invalid", irq);
273         return -1;
274     }
275     return 0;
276 }
277 
278 static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
279 {
280     int i;
281 
282     for (i = irq; i < irq + num; ++i) {
283         spapr_xive_irq_free(spapr->xive, i);
284     }
285 }
286 
287 static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
288 {
289     return spapr_xive_qirq(spapr->xive, irq);
290 }
291 
292 static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
293                                       Monitor *mon)
294 {
295     CPUState *cs;
296 
297     CPU_FOREACH(cs) {
298         PowerPCCPU *cpu = POWERPC_CPU(cs);
299 
300         xive_tctx_pic_print_info(XIVE_TCTX(cpu->intc), mon);
301     }
302 
303     spapr_xive_pic_print_info(spapr->xive, mon);
304 }
305 
306 static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
307                                               Object *cpu, Error **errp)
308 {
309     Object *obj = xive_tctx_create(cpu, XIVE_ROUTER(spapr->xive), errp);
310 
311     /*
312      * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
313      * don't benificiate from the reset of the XIVE IRQ backend
314      */
315     spapr_xive_set_tctx_os_cam(XIVE_TCTX(obj));
316     return obj;
317 }
318 
319 static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
320 {
321     return 0;
322 }
323 
324 static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
325 {
326     CPUState *cs;
327 
328     CPU_FOREACH(cs) {
329         PowerPCCPU *cpu = POWERPC_CPU(cs);
330 
331         /* (TCG) Set the OS CAM line of the thread interrupt context. */
332         spapr_xive_set_tctx_os_cam(XIVE_TCTX(cpu->intc));
333     }
334 }
335 
336 /*
337  * XIVE uses the full IRQ number space. Set it to 8K to be compatible
338  * with XICS.
339  */
340 
341 #define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
342 #define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
343 
344 sPAPRIrq spapr_irq_xive = {
345     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
346     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
347     .ov5         = SPAPR_OV5_XIVE_EXPLOIT,
348 
349     .init        = spapr_irq_init_xive,
350     .claim       = spapr_irq_claim_xive,
351     .free        = spapr_irq_free_xive,
352     .qirq        = spapr_qirq_xive,
353     .print_info  = spapr_irq_print_info_xive,
354     .dt_populate = spapr_dt_xive,
355     .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
356     .post_load   = spapr_irq_post_load_xive,
357     .reset       = spapr_irq_reset_xive,
358 };
359 
360 /*
361  * sPAPR IRQ frontend routines for devices
362  */
363 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
364 {
365     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
366 
367     /* Initialize the MSI IRQ allocator. */
368     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
369         spapr_irq_msi_init(spapr, smc->irq->nr_msis);
370     }
371 
372     smc->irq->init(spapr, errp);
373 }
374 
375 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
376 {
377     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
378 
379     return smc->irq->claim(spapr, irq, lsi, errp);
380 }
381 
382 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
383 {
384     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
385 
386     smc->irq->free(spapr, irq, num);
387 }
388 
389 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
390 {
391     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
392 
393     return smc->irq->qirq(spapr, irq);
394 }
395 
396 int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
397 {
398     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
399 
400     return smc->irq->post_load(spapr, version_id);
401 }
402 
403 void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp)
404 {
405     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
406 
407     if (smc->irq->reset) {
408         smc->irq->reset(spapr, errp);
409     }
410 }
411 
412 /*
413  * XICS legacy routines - to deprecate one day
414  */
415 
416 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
417 {
418     int first, i;
419 
420     for (first = 0; first < ics->nr_irqs; first += alignnum) {
421         if (num > (ics->nr_irqs - first)) {
422             return -1;
423         }
424         for (i = first; i < first + num; ++i) {
425             if (!ICS_IRQ_FREE(ics, i)) {
426                 break;
427             }
428         }
429         if (i == (first + num)) {
430             return first;
431         }
432     }
433 
434     return -1;
435 }
436 
437 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
438 {
439     ICSState *ics = spapr->ics;
440     int first = -1;
441 
442     assert(ics);
443 
444     /*
445      * MSIMesage::data is used for storing VIRQ so
446      * it has to be aligned to num to support multiple
447      * MSI vectors. MSI-X is not affected by this.
448      * The hint is used for the first IRQ, the rest should
449      * be allocated continuously.
450      */
451     if (align) {
452         assert((num == 1) || (num == 2) || (num == 4) ||
453                (num == 8) || (num == 16) || (num == 32));
454         first = ics_find_free_block(ics, num, num);
455     } else {
456         first = ics_find_free_block(ics, num, 1);
457     }
458 
459     if (first < 0) {
460         error_setg(errp, "can't find a free %d-IRQ block", num);
461         return -1;
462     }
463 
464     return first + ics->offset;
465 }
466 
467 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400
468 
469 sPAPRIrq spapr_irq_xics_legacy = {
470     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
471     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
472     .ov5         = SPAPR_OV5_XIVE_LEGACY,
473 
474     .init        = spapr_irq_init_xics,
475     .claim       = spapr_irq_claim_xics,
476     .free        = spapr_irq_free_xics,
477     .qirq        = spapr_qirq_xics,
478     .print_info  = spapr_irq_print_info_xics,
479     .dt_populate = spapr_dt_xics,
480     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
481     .post_load   = spapr_irq_post_load_xics,
482 };
483