xref: /qemu/hw/ppc/spapr_irq.c (revision 23bcd5eb9a472cc7bd147403d9ba18e293ee6adc) 
1 /*
2  * QEMU PowerPC sPAPR IRQ interface
3  *
4  * Copyright (c) 2018, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include "hw/ppc/spapr.h"
15 #include "hw/ppc/spapr_xive.h"
16 #include "hw/ppc/xics.h"
17 #include "sysemu/kvm.h"
18 
19 #include "trace.h"
20 
21 void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
22 {
23     spapr->irq_map_nr = nr_msis;
24     spapr->irq_map = bitmap_new(spapr->irq_map_nr);
25 }
26 
27 int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
28                         Error **errp)
29 {
30     int irq;
31 
32     /*
33      * The 'align_mask' parameter of bitmap_find_next_zero_area()
34      * should be one less than a power of 2; 0 means no
35      * alignment. Adapt the 'align' value of the former allocator
36      * to fit the requirements of bitmap_find_next_zero_area()
37      */
38     align -= 1;
39 
40     irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
41                                      align);
42     if (irq == spapr->irq_map_nr) {
43         error_setg(errp, "can't find a free %d-IRQ block", num);
44         return -1;
45     }
46 
47     bitmap_set(spapr->irq_map, irq, num);
48 
49     return irq + SPAPR_IRQ_MSI;
50 }
51 
52 void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
53 {
54     bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
55 }
56 
57 void spapr_irq_msi_reset(sPAPRMachineState *spapr)
58 {
59     bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
60 }
61 
62 
63 /*
64  * XICS IRQ backend.
65  */
66 
67 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
68                                   const char *type_ics,
69                                   int nr_irqs, Error **errp)
70 {
71     Error *local_err = NULL;
72     Object *obj;
73 
74     obj = object_new(type_ics);
75     object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
76     object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
77                                    &error_abort);
78     object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
79     if (local_err) {
80         goto error;
81     }
82     object_property_set_bool(obj, true, "realized", &local_err);
83     if (local_err) {
84         goto error;
85     }
86 
87     return ICS_BASE(obj);
88 
89 error:
90     error_propagate(errp, local_err);
91     return NULL;
92 }
93 
94 static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
95 {
96     MachineState *machine = MACHINE(spapr);
97     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
98     int nr_irqs = smc->irq->nr_irqs;
99     Error *local_err = NULL;
100 
101     if (kvm_enabled()) {
102         if (machine_kernel_irqchip_allowed(machine) &&
103             !xics_kvm_init(spapr, &local_err)) {
104             spapr->icp_type = TYPE_KVM_ICP;
105             spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
106                                           &local_err);
107         }
108         if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
109             error_prepend(&local_err,
110                           "kernel_irqchip requested but unavailable: ");
111             goto error;
112         }
113         error_free(local_err);
114         local_err = NULL;
115     }
116 
117     if (!spapr->ics) {
118         xics_spapr_init(spapr);
119         spapr->icp_type = TYPE_ICP;
120         spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
121                                       &local_err);
122     }
123 
124 error:
125     error_propagate(errp, local_err);
126 }
127 
128 #define ICS_IRQ_FREE(ics, srcno)   \
129     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
130 
131 static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
132                                 Error **errp)
133 {
134     ICSState *ics = spapr->ics;
135 
136     assert(ics);
137 
138     if (!ics_valid_irq(ics, irq)) {
139         error_setg(errp, "IRQ %d is invalid", irq);
140         return -1;
141     }
142 
143     if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
144         error_setg(errp, "IRQ %d is not free", irq);
145         return -1;
146     }
147 
148     ics_set_irq_type(ics, irq - ics->offset, lsi);
149     return 0;
150 }
151 
152 static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
153 {
154     ICSState *ics = spapr->ics;
155     uint32_t srcno = irq - ics->offset;
156     int i;
157 
158     if (ics_valid_irq(ics, irq)) {
159         trace_spapr_irq_free(0, irq, num);
160         for (i = srcno; i < srcno + num; ++i) {
161             if (ICS_IRQ_FREE(ics, i)) {
162                 trace_spapr_irq_free_warn(0, i);
163             }
164             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
165         }
166     }
167 }
168 
169 static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
170 {
171     ICSState *ics = spapr->ics;
172     uint32_t srcno = irq - ics->offset;
173 
174     if (ics_valid_irq(ics, irq)) {
175         return ics->qirqs[srcno];
176     }
177 
178     return NULL;
179 }
180 
181 static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
182 {
183     CPUState *cs;
184 
185     CPU_FOREACH(cs) {
186         PowerPCCPU *cpu = POWERPC_CPU(cs);
187 
188         icp_pic_print_info(ICP(cpu->intc), mon);
189     }
190 
191     ics_pic_print_info(spapr->ics, mon);
192 }
193 
194 #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
195 #define SPAPR_IRQ_XICS_NR_MSIS     \
196     (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
197 
198 sPAPRIrq spapr_irq_xics = {
199     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
200     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
201 
202     .init        = spapr_irq_init_xics,
203     .claim       = spapr_irq_claim_xics,
204     .free        = spapr_irq_free_xics,
205     .qirq        = spapr_qirq_xics,
206     .print_info  = spapr_irq_print_info_xics,
207 };
208 
209 /*
210  * XIVE IRQ backend.
211  */
212 static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
213 {
214     MachineState *machine = MACHINE(spapr);
215     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
216     uint32_t nr_servers = spapr_max_server_number(spapr);
217     DeviceState *dev;
218     int i;
219 
220     /* KVM XIVE device not yet available */
221     if (kvm_enabled()) {
222         if (machine_kernel_irqchip_required(machine)) {
223             error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
224             return;
225         }
226     }
227 
228     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
229     qdev_prop_set_uint32(dev, "nr-irqs", smc->irq->nr_irqs);
230     /*
231      * 8 XIVE END structures per CPU. One for each available priority
232      */
233     qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
234     qdev_init_nofail(dev);
235 
236     spapr->xive = SPAPR_XIVE(dev);
237 
238     /* Enable the CPU IPIs */
239     for (i = 0; i < nr_servers; ++i) {
240         spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
241     }
242 
243     spapr_xive_hcall_init(spapr);
244 }
245 
246 static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
247                                 Error **errp)
248 {
249     if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
250         error_setg(errp, "IRQ %d is invalid", irq);
251         return -1;
252     }
253     return 0;
254 }
255 
256 static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
257 {
258     int i;
259 
260     for (i = irq; i < irq + num; ++i) {
261         spapr_xive_irq_free(spapr->xive, i);
262     }
263 }
264 
265 static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
266 {
267     return spapr_xive_qirq(spapr->xive, irq);
268 }
269 
270 static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
271                                       Monitor *mon)
272 {
273     CPUState *cs;
274 
275     CPU_FOREACH(cs) {
276         PowerPCCPU *cpu = POWERPC_CPU(cs);
277 
278         xive_tctx_pic_print_info(XIVE_TCTX(cpu->intc), mon);
279     }
280 
281     spapr_xive_pic_print_info(spapr->xive, mon);
282 }
283 
284 /*
285  * XIVE uses the full IRQ number space. Set it to 8K to be compatible
286  * with XICS.
287  */
288 
289 #define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
290 #define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
291 
292 sPAPRIrq spapr_irq_xive = {
293     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
294     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
295 
296     .init        = spapr_irq_init_xive,
297     .claim       = spapr_irq_claim_xive,
298     .free        = spapr_irq_free_xive,
299     .qirq        = spapr_qirq_xive,
300     .print_info  = spapr_irq_print_info_xive,
301 };
302 
303 /*
304  * sPAPR IRQ frontend routines for devices
305  */
306 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
307 {
308     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
309 
310     /* Initialize the MSI IRQ allocator. */
311     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
312         spapr_irq_msi_init(spapr, smc->irq->nr_msis);
313     }
314 
315     smc->irq->init(spapr, errp);
316 }
317 
318 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
319 {
320     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
321 
322     return smc->irq->claim(spapr, irq, lsi, errp);
323 }
324 
325 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
326 {
327     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
328 
329     smc->irq->free(spapr, irq, num);
330 }
331 
332 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
333 {
334     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
335 
336     return smc->irq->qirq(spapr, irq);
337 }
338 
339 /*
340  * XICS legacy routines - to deprecate one day
341  */
342 
343 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
344 {
345     int first, i;
346 
347     for (first = 0; first < ics->nr_irqs; first += alignnum) {
348         if (num > (ics->nr_irqs - first)) {
349             return -1;
350         }
351         for (i = first; i < first + num; ++i) {
352             if (!ICS_IRQ_FREE(ics, i)) {
353                 break;
354             }
355         }
356         if (i == (first + num)) {
357             return first;
358         }
359     }
360 
361     return -1;
362 }
363 
364 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
365 {
366     ICSState *ics = spapr->ics;
367     int first = -1;
368 
369     assert(ics);
370 
371     /*
372      * MSIMesage::data is used for storing VIRQ so
373      * it has to be aligned to num to support multiple
374      * MSI vectors. MSI-X is not affected by this.
375      * The hint is used for the first IRQ, the rest should
376      * be allocated continuously.
377      */
378     if (align) {
379         assert((num == 1) || (num == 2) || (num == 4) ||
380                (num == 8) || (num == 16) || (num == 32));
381         first = ics_find_free_block(ics, num, num);
382     } else {
383         first = ics_find_free_block(ics, num, 1);
384     }
385 
386     if (first < 0) {
387         error_setg(errp, "can't find a free %d-IRQ block", num);
388         return -1;
389     }
390 
391     return first + ics->offset;
392 }
393 
394 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400
395 
396 sPAPRIrq spapr_irq_xics_legacy = {
397     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
398     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
399 
400     .init        = spapr_irq_init_xics,
401     .claim       = spapr_irq_claim_xics,
402     .free        = spapr_irq_free_xics,
403     .qirq        = spapr_qirq_xics,
404     .print_info  = spapr_irq_print_info_xics,
405 };
406