1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "qapi/error.h" 4 #include "system/hw_accel.h" 5 #include "system/runstate.h" 6 #include "system/tcg.h" 7 #include "qemu/log.h" 8 #include "qemu/main-loop.h" 9 #include "qemu/module.h" 10 #include "qemu/error-report.h" 11 #include "exec/tb-flush.h" 12 #include "exec/target_page.h" 13 #include "helper_regs.h" 14 #include "hw/ppc/ppc.h" 15 #include "hw/ppc/spapr.h" 16 #include "hw/ppc/spapr_cpu_core.h" 17 #include "hw/ppc/spapr_nested.h" 18 #include "mmu-hash64.h" 19 #include "cpu-models.h" 20 #include "trace.h" 21 #include "kvm_ppc.h" 22 #include "hw/ppc/fdt.h" 23 #include "hw/ppc/spapr_ovec.h" 24 #include "hw/ppc/spapr_numa.h" 25 #include "mmu-book3s-v3.h" 26 #include "hw/mem/memory-device.h" 27 28 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 29 { 30 MachineState *machine = MACHINE(spapr); 31 DeviceMemoryState *dms = machine->device_memory; 32 33 if (addr < machine->ram_size) { 34 return true; 35 } 36 if (dms && (addr >= dms->base) 37 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 38 return true; 39 } 40 41 return false; 42 } 43 44 /* Convert a return code from the KVM ioctl()s implementing resize HPT 45 * into a PAPR hypercall return code */ 46 static target_ulong resize_hpt_convert_rc(int ret) 47 { 48 if (ret >= 100000) { 49 return H_LONG_BUSY_ORDER_100_SEC; 50 } else if (ret >= 10000) { 51 return H_LONG_BUSY_ORDER_10_SEC; 52 } else if (ret >= 1000) { 53 return H_LONG_BUSY_ORDER_1_SEC; 54 } else if (ret >= 100) { 55 return H_LONG_BUSY_ORDER_100_MSEC; 56 } else if (ret >= 10) { 57 return H_LONG_BUSY_ORDER_10_MSEC; 58 } else if (ret > 0) { 59 return H_LONG_BUSY_ORDER_1_MSEC; 60 } 61 62 switch (ret) { 63 case 0: 64 return H_SUCCESS; 65 case -EPERM: 66 return H_AUTHORITY; 67 case -EINVAL: 68 return H_PARAMETER; 69 case -ENXIO: 70 return H_CLOSED; 71 case -ENOSPC: 72 return H_PTEG_FULL; 73 case -EBUSY: 74 return H_BUSY; 75 case -ENOMEM: 76 return H_NO_MEM; 77 default: 78 return H_HARDWARE; 79 } 80 } 81 82 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 83 SpaprMachineState *spapr, 84 target_ulong opcode, 85 target_ulong *args) 86 { 87 target_ulong flags = args[0]; 88 int shift = args[1]; 89 uint64_t current_ram_size; 90 int rc; 91 92 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 93 return H_AUTHORITY; 94 } 95 96 if (!spapr->htab_shift) { 97 /* Radix guest, no HPT */ 98 return H_NOT_AVAILABLE; 99 } 100 101 trace_spapr_h_resize_hpt_prepare(flags, shift); 102 103 if (flags != 0) { 104 return H_PARAMETER; 105 } 106 107 if (shift && ((shift < 18) || (shift > 46))) { 108 return H_PARAMETER; 109 } 110 111 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 112 113 /* We only allow the guest to allocate an HPT one order above what 114 * we'd normally give them (to stop a small guest claiming a huge 115 * chunk of resources in the HPT */ 116 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 117 return H_RESOURCE; 118 } 119 120 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 121 if (rc != -ENOSYS) { 122 return resize_hpt_convert_rc(rc); 123 } 124 125 if (kvm_enabled()) { 126 return H_HARDWARE; 127 } else if (tcg_enabled()) { 128 return vhyp_mmu_resize_hpt_prepare(cpu, spapr, shift); 129 } else { 130 g_assert_not_reached(); 131 } 132 } 133 134 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 135 { 136 int ret; 137 138 cpu_synchronize_state(cs); 139 140 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 141 if (ret < 0) { 142 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 143 exit(1); 144 } 145 } 146 147 void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 148 { 149 CPUState *cs; 150 151 /* 152 * This is a hack for the benefit of KVM PR - it abuses the SDR1 153 * slot in kvm_sregs to communicate the userspace address of the 154 * HPT 155 */ 156 if (!kvm_enabled() || !spapr->htab) { 157 return; 158 } 159 160 CPU_FOREACH(cs) { 161 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 162 } 163 } 164 165 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 166 SpaprMachineState *spapr, 167 target_ulong opcode, 168 target_ulong *args) 169 { 170 target_ulong flags = args[0]; 171 target_ulong shift = args[1]; 172 int rc; 173 174 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 175 return H_AUTHORITY; 176 } 177 178 if (!spapr->htab_shift) { 179 /* Radix guest, no HPT */ 180 return H_NOT_AVAILABLE; 181 } 182 183 trace_spapr_h_resize_hpt_commit(flags, shift); 184 185 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 186 if (rc != -ENOSYS) { 187 rc = resize_hpt_convert_rc(rc); 188 if (rc == H_SUCCESS) { 189 /* Need to set the new htab_shift in the machine state */ 190 spapr->htab_shift = shift; 191 } 192 return rc; 193 } 194 195 if (kvm_enabled()) { 196 return H_HARDWARE; 197 } else if (tcg_enabled()) { 198 return vhyp_mmu_resize_hpt_commit(cpu, spapr, flags, shift); 199 } else { 200 g_assert_not_reached(); 201 } 202 } 203 204 205 206 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 207 target_ulong opcode, target_ulong *args) 208 { 209 cpu_synchronize_state(CPU(cpu)); 210 cpu->env.spr[SPR_SPRG0] = args[0]; 211 212 return H_SUCCESS; 213 } 214 215 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 216 target_ulong opcode, target_ulong *args) 217 { 218 if (!ppc_has_spr(cpu, SPR_DABR)) { 219 return H_HARDWARE; /* DABR register not available */ 220 } 221 cpu_synchronize_state(CPU(cpu)); 222 223 if (ppc_has_spr(cpu, SPR_DABRX)) { 224 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 225 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 226 return H_RESERVED_DABR; 227 } 228 229 cpu->env.spr[SPR_DABR] = args[0]; 230 return H_SUCCESS; 231 } 232 233 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 234 target_ulong opcode, target_ulong *args) 235 { 236 target_ulong dabrx = args[1]; 237 238 if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 239 return H_HARDWARE; 240 } 241 242 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 243 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 244 return H_PARAMETER; 245 } 246 247 cpu_synchronize_state(CPU(cpu)); 248 cpu->env.spr[SPR_DABRX] = dabrx; 249 cpu->env.spr[SPR_DABR] = args[0]; 250 251 return H_SUCCESS; 252 } 253 254 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 255 target_ulong opcode, target_ulong *args) 256 { 257 target_ulong flags = args[0]; 258 hwaddr dst = args[1]; 259 hwaddr src = args[2]; 260 hwaddr len = TARGET_PAGE_SIZE; 261 uint8_t *pdst, *psrc; 262 target_long ret = H_SUCCESS; 263 264 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 265 | H_COPY_PAGE | H_ZERO_PAGE)) { 266 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 267 flags); 268 return H_PARAMETER; 269 } 270 271 /* Map-in destination */ 272 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 273 return H_PARAMETER; 274 } 275 pdst = cpu_physical_memory_map(dst, &len, true); 276 if (!pdst || len != TARGET_PAGE_SIZE) { 277 return H_PARAMETER; 278 } 279 280 if (flags & H_COPY_PAGE) { 281 /* Map-in source, copy to destination, and unmap source again */ 282 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 283 ret = H_PARAMETER; 284 goto unmap_out; 285 } 286 psrc = cpu_physical_memory_map(src, &len, false); 287 if (!psrc || len != TARGET_PAGE_SIZE) { 288 ret = H_PARAMETER; 289 goto unmap_out; 290 } 291 memcpy(pdst, psrc, len); 292 cpu_physical_memory_unmap(psrc, len, 0, len); 293 } else if (flags & H_ZERO_PAGE) { 294 memset(pdst, 0, len); /* Just clear the destination page */ 295 } 296 297 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 298 kvmppc_dcbst_range(cpu, pdst, len); 299 } 300 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 301 if (kvm_enabled()) { 302 kvmppc_icbi_range(cpu, pdst, len); 303 } else if (tcg_enabled()) { 304 tb_flush(CPU(cpu)); 305 } else { 306 g_assert_not_reached(); 307 } 308 } 309 310 unmap_out: 311 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 312 return ret; 313 } 314 315 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 316 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 317 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 318 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 319 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 320 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 321 322 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 323 { 324 CPUState *cs = CPU(cpu); 325 CPUPPCState *env = &cpu->env; 326 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 327 uint16_t size; 328 uint8_t tmp; 329 330 if (vpa == 0) { 331 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 332 return H_HARDWARE; 333 } 334 335 if (vpa % env->dcache_line_size) { 336 return H_PARAMETER; 337 } 338 /* FIXME: bounds check the address */ 339 340 size = lduw_be_phys(cs->as, vpa + 0x4); 341 342 if (size < VPA_MIN_SIZE) { 343 return H_PARAMETER; 344 } 345 346 /* VPA is not allowed to cross a page boundary */ 347 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 348 return H_PARAMETER; 349 } 350 351 spapr_cpu->vpa_addr = vpa; 352 353 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 354 tmp |= VPA_SHARED_PROC_VAL; 355 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 356 357 return H_SUCCESS; 358 } 359 360 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 361 { 362 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 363 364 if (spapr_cpu->slb_shadow_addr) { 365 return H_RESOURCE; 366 } 367 368 if (spapr_cpu->dtl_addr) { 369 return H_RESOURCE; 370 } 371 372 spapr_cpu->vpa_addr = 0; 373 return H_SUCCESS; 374 } 375 376 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 377 { 378 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 379 uint32_t size; 380 381 if (addr == 0) { 382 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 383 return H_HARDWARE; 384 } 385 386 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 387 if (size < 0x8) { 388 return H_PARAMETER; 389 } 390 391 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 392 return H_PARAMETER; 393 } 394 395 if (!spapr_cpu->vpa_addr) { 396 return H_RESOURCE; 397 } 398 399 spapr_cpu->slb_shadow_addr = addr; 400 spapr_cpu->slb_shadow_size = size; 401 402 return H_SUCCESS; 403 } 404 405 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 406 { 407 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 408 409 spapr_cpu->slb_shadow_addr = 0; 410 spapr_cpu->slb_shadow_size = 0; 411 return H_SUCCESS; 412 } 413 414 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 415 { 416 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 417 uint32_t size; 418 419 if (addr == 0) { 420 hcall_dprintf("Can't cope with DTL at logical 0\n"); 421 return H_HARDWARE; 422 } 423 424 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 425 426 if (size < 48) { 427 return H_PARAMETER; 428 } 429 430 if (!spapr_cpu->vpa_addr) { 431 return H_RESOURCE; 432 } 433 434 spapr_cpu->dtl_addr = addr; 435 spapr_cpu->dtl_size = size; 436 437 return H_SUCCESS; 438 } 439 440 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 441 { 442 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 443 444 spapr_cpu->dtl_addr = 0; 445 spapr_cpu->dtl_size = 0; 446 447 return H_SUCCESS; 448 } 449 450 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 451 target_ulong opcode, target_ulong *args) 452 { 453 target_ulong flags = args[0]; 454 target_ulong procno = args[1]; 455 target_ulong vpa = args[2]; 456 target_ulong ret = H_PARAMETER; 457 PowerPCCPU *tcpu; 458 459 tcpu = spapr_find_cpu(procno); 460 if (!tcpu) { 461 return H_PARAMETER; 462 } 463 464 switch (flags) { 465 case FLAGS_REGISTER_VPA: 466 ret = register_vpa(tcpu, vpa); 467 break; 468 469 case FLAGS_DEREGISTER_VPA: 470 ret = deregister_vpa(tcpu, vpa); 471 break; 472 473 case FLAGS_REGISTER_SLBSHADOW: 474 ret = register_slb_shadow(tcpu, vpa); 475 break; 476 477 case FLAGS_DEREGISTER_SLBSHADOW: 478 ret = deregister_slb_shadow(tcpu, vpa); 479 break; 480 481 case FLAGS_REGISTER_DTL: 482 ret = register_dtl(tcpu, vpa); 483 break; 484 485 case FLAGS_DEREGISTER_DTL: 486 ret = deregister_dtl(tcpu, vpa); 487 break; 488 } 489 490 return ret; 491 } 492 493 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 494 target_ulong opcode, target_ulong *args) 495 { 496 CPUPPCState *env = &cpu->env; 497 CPUState *cs = CPU(cpu); 498 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 499 500 env->msr |= (1ULL << MSR_EE); 501 hreg_compute_hflags(env); 502 ppc_maybe_interrupt(env); 503 504 if (spapr_cpu->prod) { 505 spapr_cpu->prod = false; 506 return H_SUCCESS; 507 } 508 509 if (!cpu_has_work(cs)) { 510 cs->halted = 1; 511 cs->exception_index = EXCP_HLT; 512 cs->exit_request = 1; 513 ppc_maybe_interrupt(env); 514 } 515 516 return H_SUCCESS; 517 } 518 519 /* 520 * Confer to self, aka join. Cede could use the same pattern as well, if 521 * EXCP_HLT can be changed to ECXP_HALTED. 522 */ 523 static target_ulong h_confer_self(PowerPCCPU *cpu) 524 { 525 CPUState *cs = CPU(cpu); 526 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 527 528 if (spapr_cpu->prod) { 529 spapr_cpu->prod = false; 530 return H_SUCCESS; 531 } 532 cs->halted = 1; 533 cs->exception_index = EXCP_HALTED; 534 cs->exit_request = 1; 535 ppc_maybe_interrupt(&cpu->env); 536 537 return H_SUCCESS; 538 } 539 540 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 541 target_ulong opcode, target_ulong *args) 542 { 543 CPUPPCState *env = &cpu->env; 544 CPUState *cs; 545 bool last_unjoined = true; 546 547 if (env->msr & (1ULL << MSR_EE)) { 548 return H_BAD_MODE; 549 } 550 551 /* 552 * Must not join the last CPU running. Interestingly, no such restriction 553 * for H_CONFER-to-self, but that is probably not intended to be used 554 * when H_JOIN is available. 555 */ 556 CPU_FOREACH(cs) { 557 PowerPCCPU *c = POWERPC_CPU(cs); 558 CPUPPCState *e = &c->env; 559 if (c == cpu) { 560 continue; 561 } 562 563 /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 564 if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 565 last_unjoined = false; 566 break; 567 } 568 } 569 if (last_unjoined) { 570 return H_CONTINUE; 571 } 572 573 return h_confer_self(cpu); 574 } 575 576 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 577 target_ulong opcode, target_ulong *args) 578 { 579 target_long target = args[0]; 580 uint32_t dispatch = args[1]; 581 CPUState *cs = CPU(cpu); 582 SpaprCpuState *spapr_cpu; 583 584 assert(tcg_enabled()); /* KVM will have handled this */ 585 586 /* 587 * -1 means confer to all other CPUs without dispatch counter check, 588 * otherwise it's a targeted confer. 589 */ 590 if (target != -1) { 591 PowerPCCPU *target_cpu = spapr_find_cpu(target); 592 uint32_t target_dispatch; 593 594 if (!target_cpu) { 595 return H_PARAMETER; 596 } 597 598 /* 599 * target == self is a special case, we wait until prodded, without 600 * dispatch counter check. 601 */ 602 if (cpu == target_cpu) { 603 return h_confer_self(cpu); 604 } 605 606 spapr_cpu = spapr_cpu_state(target_cpu); 607 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 608 return H_SUCCESS; 609 } 610 611 target_dispatch = ldl_be_phys(cs->as, 612 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 613 if (target_dispatch != dispatch) { 614 return H_SUCCESS; 615 } 616 617 /* 618 * The targeted confer does not do anything special beyond yielding 619 * the current vCPU, but even this should be better than nothing. 620 * At least for single-threaded tcg, it gives the target a chance to 621 * run before we run again. Multi-threaded tcg does not really do 622 * anything with EXCP_YIELD yet. 623 */ 624 } 625 626 cs->exception_index = EXCP_YIELD; 627 cs->exit_request = 1; 628 cpu_loop_exit(cs); 629 630 return H_SUCCESS; 631 } 632 633 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 634 target_ulong opcode, target_ulong *args) 635 { 636 target_long target = args[0]; 637 PowerPCCPU *tcpu; 638 CPUState *cs; 639 SpaprCpuState *spapr_cpu; 640 641 tcpu = spapr_find_cpu(target); 642 cs = CPU(tcpu); 643 if (!cs) { 644 return H_PARAMETER; 645 } 646 647 spapr_cpu = spapr_cpu_state(tcpu); 648 spapr_cpu->prod = true; 649 cs->halted = 0; 650 ppc_maybe_interrupt(&cpu->env); 651 qemu_cpu_kick(cs); 652 653 return H_SUCCESS; 654 } 655 656 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 657 target_ulong opcode, target_ulong *args) 658 { 659 target_ulong rtas_r3 = args[0]; 660 uint32_t token = rtas_ld(rtas_r3, 0); 661 uint32_t nargs = rtas_ld(rtas_r3, 1); 662 uint32_t nret = rtas_ld(rtas_r3, 2); 663 664 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 665 nret, rtas_r3 + 12 + 4*nargs); 666 } 667 668 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 669 target_ulong opcode, target_ulong *args) 670 { 671 CPUState *cs = CPU(cpu); 672 target_ulong size = args[0]; 673 target_ulong addr = args[1]; 674 675 switch (size) { 676 case 1: 677 args[0] = ldub_phys(cs->as, addr); 678 return H_SUCCESS; 679 case 2: 680 args[0] = lduw_phys(cs->as, addr); 681 return H_SUCCESS; 682 case 4: 683 args[0] = ldl_phys(cs->as, addr); 684 return H_SUCCESS; 685 case 8: 686 args[0] = ldq_phys(cs->as, addr); 687 return H_SUCCESS; 688 } 689 return H_PARAMETER; 690 } 691 692 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 693 target_ulong opcode, target_ulong *args) 694 { 695 CPUState *cs = CPU(cpu); 696 697 target_ulong size = args[0]; 698 target_ulong addr = args[1]; 699 target_ulong val = args[2]; 700 701 switch (size) { 702 case 1: 703 stb_phys(cs->as, addr, val); 704 return H_SUCCESS; 705 case 2: 706 stw_phys(cs->as, addr, val); 707 return H_SUCCESS; 708 case 4: 709 stl_phys(cs->as, addr, val); 710 return H_SUCCESS; 711 case 8: 712 stq_phys(cs->as, addr, val); 713 return H_SUCCESS; 714 } 715 return H_PARAMETER; 716 } 717 718 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 719 target_ulong opcode, target_ulong *args) 720 { 721 CPUState *cs = CPU(cpu); 722 723 target_ulong dst = args[0]; /* Destination address */ 724 target_ulong src = args[1]; /* Source address */ 725 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 726 target_ulong count = args[3]; /* Element count */ 727 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 728 uint64_t tmp; 729 unsigned int mask = (1 << esize) - 1; 730 int step = 1 << esize; 731 732 if (count > 0x80000000) { 733 return H_PARAMETER; 734 } 735 736 if ((dst & mask) || (src & mask) || (op > 1)) { 737 return H_PARAMETER; 738 } 739 740 if (dst >= src && dst < (src + (count << esize))) { 741 dst = dst + ((count - 1) << esize); 742 src = src + ((count - 1) << esize); 743 step = -step; 744 } 745 746 while (count--) { 747 switch (esize) { 748 case 0: 749 tmp = ldub_phys(cs->as, src); 750 break; 751 case 1: 752 tmp = lduw_phys(cs->as, src); 753 break; 754 case 2: 755 tmp = ldl_phys(cs->as, src); 756 break; 757 case 3: 758 tmp = ldq_phys(cs->as, src); 759 break; 760 default: 761 return H_PARAMETER; 762 } 763 if (op == 1) { 764 tmp = ~tmp; 765 } 766 switch (esize) { 767 case 0: 768 stb_phys(cs->as, dst, tmp); 769 break; 770 case 1: 771 stw_phys(cs->as, dst, tmp); 772 break; 773 case 2: 774 stl_phys(cs->as, dst, tmp); 775 break; 776 case 3: 777 stq_phys(cs->as, dst, tmp); 778 break; 779 } 780 dst = dst + step; 781 src = src + step; 782 } 783 784 return H_SUCCESS; 785 } 786 787 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 788 target_ulong opcode, target_ulong *args) 789 { 790 /* Nothing to do on emulation, KVM will trap this in the kernel */ 791 return H_SUCCESS; 792 } 793 794 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 795 target_ulong opcode, target_ulong *args) 796 { 797 /* Nothing to do on emulation, KVM will trap this in the kernel */ 798 return H_SUCCESS; 799 } 800 801 static target_ulong h_set_mode_resource_set_ciabr(PowerPCCPU *cpu, 802 SpaprMachineState *spapr, 803 target_ulong mflags, 804 target_ulong value1, 805 target_ulong value2) 806 { 807 CPUPPCState *env = &cpu->env; 808 809 assert(tcg_enabled()); /* KVM will have handled this */ 810 811 if (mflags) { 812 return H_UNSUPPORTED_FLAG; 813 } 814 if (value2) { 815 return H_P4; 816 } 817 if ((value1 & PPC_BITMASK(62, 63)) == 0x3) { 818 return H_P3; 819 } 820 821 ppc_store_ciabr(env, value1); 822 823 return H_SUCCESS; 824 } 825 826 static target_ulong h_set_mode_resource_set_dawr(PowerPCCPU *cpu, 827 SpaprMachineState *spapr, 828 target_ulong mflags, 829 target_ulong resource, 830 target_ulong value1, 831 target_ulong value2) 832 { 833 CPUPPCState *env = &cpu->env; 834 835 assert(tcg_enabled()); /* KVM will have handled this */ 836 837 if (mflags) { 838 return H_UNSUPPORTED_FLAG; 839 } 840 if (value2 & PPC_BIT(61)) { 841 return H_P4; 842 } 843 844 if (resource == H_SET_MODE_RESOURCE_SET_DAWR0) { 845 ppc_store_dawr0(env, value1); 846 ppc_store_dawrx0(env, value2); 847 } else if (resource == H_SET_MODE_RESOURCE_SET_DAWR1) { 848 ppc_store_dawr1(env, value1); 849 ppc_store_dawrx1(env, value2); 850 } else { 851 g_assert_not_reached(); 852 } 853 854 return H_SUCCESS; 855 } 856 857 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 858 SpaprMachineState *spapr, 859 target_ulong mflags, 860 target_ulong value1, 861 target_ulong value2) 862 { 863 if (value1) { 864 return H_P3; 865 } 866 if (value2) { 867 return H_P4; 868 } 869 870 switch (mflags) { 871 case H_SET_MODE_ENDIAN_BIG: 872 spapr_set_all_lpcrs(0, LPCR_ILE); 873 spapr_pci_switch_vga(spapr, true); 874 return H_SUCCESS; 875 876 case H_SET_MODE_ENDIAN_LITTLE: 877 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 878 spapr_pci_switch_vga(spapr, false); 879 return H_SUCCESS; 880 } 881 882 return H_UNSUPPORTED_FLAG; 883 } 884 885 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 886 SpaprMachineState *spapr, 887 target_ulong mflags, 888 target_ulong value1, 889 target_ulong value2) 890 { 891 if (value1) { 892 return H_P3; 893 } 894 895 if (value2) { 896 return H_P4; 897 } 898 899 /* 900 * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr. 901 * It is supported for faithful emulation of bare metal systems, but for 902 * compatibility concerns we leave it out of the pseries machine. 903 */ 904 if (mflags != 0 && mflags != 3) { 905 return H_UNSUPPORTED_FLAG; 906 } 907 908 if (mflags == 3) { 909 if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) { 910 return H_UNSUPPORTED_FLAG; 911 } 912 } 913 914 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 915 916 return H_SUCCESS; 917 } 918 919 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 920 target_ulong opcode, target_ulong *args) 921 { 922 target_ulong resource = args[1]; 923 target_ulong ret = H_P2; 924 925 switch (resource) { 926 case H_SET_MODE_RESOURCE_SET_CIABR: 927 ret = h_set_mode_resource_set_ciabr(cpu, spapr, args[0], args[2], 928 args[3]); 929 break; 930 case H_SET_MODE_RESOURCE_SET_DAWR0: 931 case H_SET_MODE_RESOURCE_SET_DAWR1: 932 ret = h_set_mode_resource_set_dawr(cpu, spapr, args[0], args[1], 933 args[2], args[3]); 934 break; 935 case H_SET_MODE_RESOURCE_LE: 936 ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 937 break; 938 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 939 ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0], 940 args[2], args[3]); 941 break; 942 } 943 944 return ret; 945 } 946 947 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 948 target_ulong opcode, target_ulong *args) 949 { 950 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 951 opcode, " (H_CLEAN_SLB)"); 952 return H_FUNCTION; 953 } 954 955 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 956 target_ulong opcode, target_ulong *args) 957 { 958 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 959 opcode, " (H_INVALIDATE_PID)"); 960 return H_FUNCTION; 961 } 962 963 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 964 uint64_t patbe_old, uint64_t patbe_new) 965 { 966 /* 967 * We have 4 Options: 968 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 969 * HASH->RADIX : Free HPT 970 * RADIX->HASH : Allocate HPT 971 * NOTHING->HASH : Allocate HPT 972 * Note: NOTHING implies the case where we said the guest could choose 973 * later and so assumed radix and now it's called H_REG_PROC_TBL 974 */ 975 976 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 977 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 978 } else if (!(patbe_old & PATE1_GR)) { 979 /* HASH->RADIX : Free HPT */ 980 spapr_free_hpt(spapr); 981 } else if (!(patbe_new & PATE1_GR)) { 982 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 983 spapr_setup_hpt(spapr); 984 } 985 return; 986 } 987 988 #define FLAGS_MASK 0x01FULL 989 #define FLAG_MODIFY 0x10 990 #define FLAG_REGISTER 0x08 991 #define FLAG_RADIX 0x04 992 #define FLAG_HASH_PROC_TBL 0x02 993 #define FLAG_GTSE 0x01 994 995 static target_ulong h_register_process_table(PowerPCCPU *cpu, 996 SpaprMachineState *spapr, 997 target_ulong opcode, 998 target_ulong *args) 999 { 1000 target_ulong flags = args[0]; 1001 target_ulong proc_tbl = args[1]; 1002 target_ulong page_size = args[2]; 1003 target_ulong table_size = args[3]; 1004 target_ulong update_lpcr = 0; 1005 target_ulong table_byte_size; 1006 uint64_t cproc; 1007 1008 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1009 return H_PARAMETER; 1010 } 1011 if (flags & FLAG_MODIFY) { 1012 if (flags & FLAG_REGISTER) { 1013 /* Check process table alignment */ 1014 table_byte_size = 1ULL << (table_size + 12); 1015 if (proc_tbl & (table_byte_size - 1)) { 1016 qemu_log_mask(LOG_GUEST_ERROR, 1017 "%s: process table not properly aligned: proc_tbl 0x" 1018 TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", 1019 __func__, proc_tbl, table_byte_size); 1020 } 1021 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1022 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1023 return H_P2; 1024 } else if (page_size) { 1025 return H_P3; 1026 } else if (table_size > 24) { 1027 return H_P4; 1028 } 1029 cproc = PATE1_GR | proc_tbl | table_size; 1030 } else { /* Register new HPT process table */ 1031 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1032 /* TODO - Not Supported */ 1033 /* Technically caused by flag bits => H_PARAMETER */ 1034 return H_PARAMETER; 1035 } else { /* Hash with SLB */ 1036 if (proc_tbl >> 38) { 1037 return H_P2; 1038 } else if (page_size & ~0x7) { 1039 return H_P3; 1040 } else if (table_size > 24) { 1041 return H_P4; 1042 } 1043 } 1044 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1045 } 1046 1047 } else { /* Deregister current process table */ 1048 /* 1049 * Set to benign value: (current GR) | 0. This allows 1050 * deregistration in KVM to succeed even if the radix bit 1051 * in flags doesn't match the radix bit in the old PATE. 1052 */ 1053 cproc = spapr->patb_entry & PATE1_GR; 1054 } 1055 } else { /* Maintain current registration */ 1056 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1057 /* Technically caused by flag bits => H_PARAMETER */ 1058 return H_PARAMETER; /* Existing Process Table Mismatch */ 1059 } 1060 cproc = spapr->patb_entry; 1061 } 1062 1063 /* Check if we need to setup OR free the hpt */ 1064 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1065 1066 spapr->patb_entry = cproc; /* Save new process table */ 1067 1068 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1069 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1070 update_lpcr |= (LPCR_UPRT | LPCR_HR); 1071 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1072 update_lpcr |= LPCR_UPRT; 1073 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 1074 update_lpcr |= LPCR_GTSE; 1075 1076 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1077 1078 if (kvm_enabled()) { 1079 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1080 flags & FLAG_GTSE, cproc); 1081 } 1082 return H_SUCCESS; 1083 } 1084 1085 #define H_SIGNAL_SYS_RESET_ALL -1 1086 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1087 1088 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1089 SpaprMachineState *spapr, 1090 target_ulong opcode, target_ulong *args) 1091 { 1092 target_long target = args[0]; 1093 CPUState *cs; 1094 1095 if (target < 0) { 1096 /* Broadcast */ 1097 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1098 return H_PARAMETER; 1099 } 1100 1101 CPU_FOREACH(cs) { 1102 PowerPCCPU *c = POWERPC_CPU(cs); 1103 1104 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1105 if (c == cpu) { 1106 continue; 1107 } 1108 } 1109 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1110 } 1111 return H_SUCCESS; 1112 1113 } else { 1114 /* Unicast */ 1115 cs = CPU(spapr_find_cpu(target)); 1116 if (cs) { 1117 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1118 return H_SUCCESS; 1119 } 1120 return H_PARAMETER; 1121 } 1122 } 1123 1124 /* Returns either a logical PVR or zero if none was found */ 1125 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1126 target_ulong *addr, bool *raw_mode_supported) 1127 { 1128 bool explicit_match = false; /* Matched the CPU's real PVR */ 1129 uint32_t best_compat = 0; 1130 int i; 1131 1132 /* 1133 * We scan the supplied table of PVRs looking for two things 1134 * 1. Is our real CPU PVR in the list? 1135 * 2. What's the "best" listed logical PVR 1136 */ 1137 for (i = 0; i < 512; ++i) { 1138 uint32_t pvr, pvr_mask; 1139 1140 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1141 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1142 *addr += 8; 1143 1144 if (~pvr_mask & pvr) { 1145 break; /* Terminator record */ 1146 } 1147 1148 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1149 explicit_match = true; 1150 } else { 1151 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1152 best_compat = pvr; 1153 } 1154 } 1155 } 1156 1157 *raw_mode_supported = explicit_match; 1158 1159 /* Parsing finished */ 1160 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1161 1162 return best_compat; 1163 } 1164 1165 static 1166 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1167 SpaprMachineState *spapr, 1168 target_ulong vec, 1169 target_ulong fdt_bufsize) 1170 { 1171 target_ulong ov_table; /* Working address in data buffer */ 1172 uint32_t cas_pvr; 1173 SpaprOptionVector *ov1_guest, *ov5_guest; 1174 bool guest_radix; 1175 bool raw_mode_supported = false; 1176 bool guest_xive; 1177 CPUState *cs; 1178 void *fdt; 1179 uint32_t max_compat = spapr->max_compat_pvr; 1180 1181 /* CAS is supposed to be called early when only the boot vCPU is active. */ 1182 CPU_FOREACH(cs) { 1183 if (cs == CPU(cpu)) { 1184 continue; 1185 } 1186 if (!cs->halted) { 1187 warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 1188 return H_MULTI_THREADS_ACTIVE; 1189 } 1190 } 1191 1192 cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1193 if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1194 /* 1195 * We couldn't find a suitable compatibility mode, and either 1196 * the guest doesn't support "raw" mode for this CPU, or "raw" 1197 * mode is disabled because a maximum compat mode is set. 1198 */ 1199 error_report("Couldn't negotiate a suitable PVR during CAS"); 1200 return H_HARDWARE; 1201 } 1202 1203 /* Update CPUs */ 1204 if (cpu->compat_pvr != cas_pvr) { 1205 Error *local_err = NULL; 1206 1207 if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1208 /* We fail to set compat mode (likely because running with KVM PR), 1209 * but maybe we can fallback to raw mode if the guest supports it. 1210 */ 1211 if (!raw_mode_supported) { 1212 error_report_err(local_err); 1213 return H_HARDWARE; 1214 } 1215 error_free(local_err); 1216 } 1217 } 1218 1219 /* For the future use: here @ov_table points to the first option vector */ 1220 ov_table = vec; 1221 1222 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1223 if (!ov1_guest) { 1224 warn_report("guest didn't provide option vector 1"); 1225 return H_PARAMETER; 1226 } 1227 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1228 if (!ov5_guest) { 1229 spapr_ovec_cleanup(ov1_guest); 1230 warn_report("guest didn't provide option vector 5"); 1231 return H_PARAMETER; 1232 } 1233 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1234 error_report("guest requested hash and radix MMU, which is invalid."); 1235 exit(EXIT_FAILURE); 1236 } 1237 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1238 error_report("guest requested an invalid interrupt mode"); 1239 exit(EXIT_FAILURE); 1240 } 1241 1242 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1243 1244 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1245 1246 /* 1247 * HPT resizing is a bit of a special case, because when enabled 1248 * we assume an HPT guest will support it until it says it 1249 * doesn't, instead of assuming it won't support it until it says 1250 * it does. Strictly speaking that approach could break for 1251 * guests which don't make a CAS call, but those are so old we 1252 * don't care about them. Without that assumption we'd have to 1253 * make at least a temporary allocation of an HPT sized for max 1254 * memory, which could be impossibly difficult under KVM HV if 1255 * maxram is large. 1256 */ 1257 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1258 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1259 1260 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1261 error_report( 1262 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1263 exit(1); 1264 } 1265 1266 if (spapr->htab_shift < maxshift) { 1267 /* Guest doesn't know about HPT resizing, so we 1268 * pre-emptively resize for the maximum permitted RAM. At 1269 * the point this is called, nothing should have been 1270 * entered into the existing HPT */ 1271 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1272 push_sregs_to_kvm_pr(spapr); 1273 } 1274 } 1275 1276 /* NOTE: there are actually a number of ov5 bits where input from the 1277 * guest is always zero, and the platform/QEMU enables them independently 1278 * of guest input. To model these properly we'd want some sort of mask, 1279 * but since they only currently apply to memory migration as defined 1280 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1281 * to worry about this for now. 1282 */ 1283 1284 /* full range of negotiated ov5 capabilities */ 1285 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1286 spapr_ovec_cleanup(ov5_guest); 1287 1288 spapr_check_mmu_mode(guest_radix); 1289 1290 spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 1291 spapr_ovec_cleanup(ov1_guest); 1292 1293 /* 1294 * Check for NUMA affinity conditions now that we know which NUMA 1295 * affinity the guest will use. 1296 */ 1297 spapr_numa_associativity_check(spapr); 1298 1299 /* 1300 * Ensure the guest asks for an interrupt mode we support; 1301 * otherwise terminate the boot. 1302 */ 1303 if (guest_xive) { 1304 if (!spapr->irq->xive) { 1305 error_report( 1306 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1307 exit(EXIT_FAILURE); 1308 } 1309 } else { 1310 if (!spapr->irq->xics) { 1311 error_report( 1312 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1313 exit(EXIT_FAILURE); 1314 } 1315 } 1316 1317 spapr_irq_update_active_intc(spapr); 1318 1319 /* 1320 * Process all pending hot-plug/unplug requests now. An updated full 1321 * rendered FDT will be returned to the guest. 1322 */ 1323 spapr_drc_reset_all(spapr); 1324 spapr_clear_pending_hotplug_events(spapr); 1325 1326 /* 1327 * If spapr_machine_reset() did not set up a HPT but one is necessary 1328 * (because the guest isn't going to use radix) then set it up here. 1329 */ 1330 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1331 /* legacy hash or new hash: */ 1332 spapr_setup_hpt(spapr); 1333 } 1334 1335 fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 1336 g_free(spapr->fdt_blob); 1337 spapr->fdt_size = fdt_totalsize(fdt); 1338 spapr->fdt_initial_size = spapr->fdt_size; 1339 spapr->fdt_blob = fdt; 1340 1341 /* 1342 * Set the machine->fdt pointer again since we just freed 1343 * it above (by freeing spapr->fdt_blob). We set this 1344 * pointer to enable support for the 'dumpdtb' QMP/HMP 1345 * command. 1346 */ 1347 MACHINE(spapr)->fdt = fdt; 1348 1349 return H_SUCCESS; 1350 } 1351 1352 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1353 SpaprMachineState *spapr, 1354 target_ulong opcode, 1355 target_ulong *args) 1356 { 1357 target_ulong vec = ppc64_phys_to_real(args[0]); 1358 target_ulong fdt_buf = args[1]; 1359 target_ulong fdt_bufsize = args[2]; 1360 target_ulong ret; 1361 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1362 1363 if (fdt_bufsize < sizeof(hdr)) { 1364 error_report("SLOF provided insufficient CAS buffer " 1365 TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 1366 exit(EXIT_FAILURE); 1367 } 1368 1369 fdt_bufsize -= sizeof(hdr); 1370 1371 ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 1372 if (ret == H_SUCCESS) { 1373 _FDT((fdt_pack(spapr->fdt_blob))); 1374 spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 1375 spapr->fdt_initial_size = spapr->fdt_size; 1376 1377 cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 1378 cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 1379 spapr->fdt_size); 1380 trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 1381 } 1382 1383 return ret; 1384 } 1385 1386 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1387 CPUState *cs, 1388 target_ulong ovec_addr) 1389 { 1390 SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1391 1392 target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1393 ovec_addr, FDT_MAX_SIZE); 1394 1395 /* 1396 * This adds stdout and generates phandles for boottime and CAS FDTs. 1397 * It is alright to update the FDT here as do_client_architecture_support() 1398 * does not pack it. 1399 */ 1400 spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1401 1402 return ret; 1403 } 1404 1405 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1406 SpaprMachineState *spapr, 1407 target_ulong opcode, 1408 target_ulong *args) 1409 { 1410 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1411 ~H_CPU_CHAR_THR_RECONF_TRIG; 1412 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1413 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1414 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1415 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1416 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1417 SPAPR_CAP_CCF_ASSIST); 1418 1419 switch (safe_cache) { 1420 case SPAPR_CAP_WORKAROUND: 1421 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1422 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1423 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1424 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1425 break; 1426 case SPAPR_CAP_FIXED: 1427 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 1428 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1429 break; 1430 default: /* broken */ 1431 assert(safe_cache == SPAPR_CAP_BROKEN); 1432 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1433 break; 1434 } 1435 1436 switch (safe_bounds_check) { 1437 case SPAPR_CAP_WORKAROUND: 1438 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1439 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1440 break; 1441 case SPAPR_CAP_FIXED: 1442 break; 1443 default: /* broken */ 1444 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1445 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1446 break; 1447 } 1448 1449 switch (safe_indirect_branch) { 1450 case SPAPR_CAP_FIXED_NA: 1451 break; 1452 case SPAPR_CAP_FIXED_CCD: 1453 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1454 break; 1455 case SPAPR_CAP_FIXED_IBS: 1456 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1457 break; 1458 case SPAPR_CAP_WORKAROUND: 1459 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1460 if (count_cache_flush_assist) { 1461 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1462 } 1463 break; 1464 default: /* broken */ 1465 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1466 break; 1467 } 1468 1469 args[0] = characteristics; 1470 args[1] = behaviour; 1471 return H_SUCCESS; 1472 } 1473 1474 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1475 target_ulong opcode, target_ulong *args) 1476 { 1477 target_ulong dt = ppc64_phys_to_real(args[0]); 1478 struct fdt_header hdr = { 0 }; 1479 unsigned cb; 1480 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1481 void *fdt; 1482 1483 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1484 cb = fdt32_to_cpu(hdr.totalsize); 1485 1486 if (!smc->update_dt_enabled) { 1487 return H_SUCCESS; 1488 } 1489 1490 /* Check that the fdt did not grow out of proportion */ 1491 if (cb > spapr->fdt_initial_size * 2) { 1492 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1493 fdt32_to_cpu(hdr.magic)); 1494 return H_PARAMETER; 1495 } 1496 1497 fdt = g_malloc0(cb); 1498 cpu_physical_memory_read(dt, fdt, cb); 1499 1500 /* Check the fdt consistency */ 1501 if (fdt_check_full(fdt, cb)) { 1502 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1503 fdt32_to_cpu(hdr.magic)); 1504 return H_PARAMETER; 1505 } 1506 1507 g_free(spapr->fdt_blob); 1508 spapr->fdt_size = cb; 1509 spapr->fdt_blob = fdt; 1510 trace_spapr_update_dt(cb); 1511 1512 return H_SUCCESS; 1513 } 1514 1515 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1516 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1517 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 1518 1519 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1520 { 1521 spapr_hcall_fn *slot; 1522 1523 if (opcode <= MAX_HCALL_OPCODE) { 1524 assert((opcode & 0x3) == 0); 1525 1526 slot = &papr_hypercall_table[opcode / 4]; 1527 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1528 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1529 assert((opcode & 0x3) == 0); 1530 1531 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1532 } else { 1533 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1534 1535 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1536 } 1537 1538 assert(!(*slot)); 1539 *slot = fn; 1540 } 1541 1542 void spapr_unregister_hypercall(target_ulong opcode) 1543 { 1544 spapr_hcall_fn *slot; 1545 1546 if (opcode <= MAX_HCALL_OPCODE) { 1547 assert((opcode & 0x3) == 0); 1548 1549 slot = &papr_hypercall_table[opcode / 4]; 1550 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1551 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1552 assert((opcode & 0x3) == 0); 1553 1554 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1555 } else { 1556 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1557 1558 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1559 } 1560 1561 *slot = NULL; 1562 } 1563 1564 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1565 target_ulong *args) 1566 { 1567 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1568 1569 if ((opcode <= MAX_HCALL_OPCODE) 1570 && ((opcode & 0x3) == 0)) { 1571 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1572 1573 if (fn) { 1574 return fn(cpu, spapr, opcode, args); 1575 } 1576 } else if ((opcode >= SVM_HCALL_BASE) && 1577 (opcode <= SVM_HCALL_MAX)) { 1578 spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1579 1580 if (fn) { 1581 return fn(cpu, spapr, opcode, args); 1582 } 1583 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1584 (opcode <= KVMPPC_HCALL_MAX)) { 1585 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1586 1587 if (fn) { 1588 return fn(cpu, spapr, opcode, args); 1589 } 1590 } 1591 1592 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1593 opcode); 1594 return H_FUNCTION; 1595 } 1596 1597 #ifdef CONFIG_TCG 1598 static void hypercall_register_softmmu(void) 1599 { 1600 /* DO NOTHING */ 1601 } 1602 #else 1603 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1604 target_ulong opcode, target_ulong *args) 1605 { 1606 g_assert_not_reached(); 1607 } 1608 1609 static void hypercall_register_softmmu(void) 1610 { 1611 /* hcall-pft */ 1612 spapr_register_hypercall(H_ENTER, h_softmmu); 1613 spapr_register_hypercall(H_REMOVE, h_softmmu); 1614 spapr_register_hypercall(H_PROTECT, h_softmmu); 1615 spapr_register_hypercall(H_READ, h_softmmu); 1616 1617 /* hcall-bulk */ 1618 spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1619 } 1620 #endif 1621 1622 static void hypercall_register_types(void) 1623 { 1624 hypercall_register_softmmu(); 1625 1626 /* hcall-hpt-resize */ 1627 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1628 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1629 1630 /* hcall-splpar */ 1631 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1632 spapr_register_hypercall(H_CEDE, h_cede); 1633 spapr_register_hypercall(H_CONFER, h_confer); 1634 spapr_register_hypercall(H_PROD, h_prod); 1635 1636 /* hcall-join */ 1637 spapr_register_hypercall(H_JOIN, h_join); 1638 1639 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1640 1641 /* processor register resource access h-calls */ 1642 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1643 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1644 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1645 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1646 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1647 1648 /* In Memory Table MMU h-calls */ 1649 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1650 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1651 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1652 1653 /* hcall-get-cpu-characteristics */ 1654 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1655 h_get_cpu_characteristics); 1656 1657 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differentiate 1658 * here between the "CI" and the "CACHE" variants, they will use whatever 1659 * mapping attributes qemu is using. When using KVM, the kernel will 1660 * enforce the attributes more strongly 1661 */ 1662 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1663 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1664 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1665 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1666 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1667 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1668 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1669 1670 /* qemu/KVM-PPC specific hcalls */ 1671 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1672 1673 /* ibm,client-architecture-support support */ 1674 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1675 1676 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1677 } 1678 1679 type_init(hypercall_register_types) 1680