1 #include "sysemu/sysemu.h" 2 #include "cpu.h" 3 #include "helper_regs.h" 4 #include "hw/ppc/spapr.h" 5 #include "mmu-hash64.h" 6 7 static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, 8 target_ulong pte_index) 9 { 10 target_ulong rb, va_low; 11 12 rb = (v & ~0x7fULL) << 16; /* AVA field */ 13 va_low = pte_index >> 3; 14 if (v & HPTE64_V_SECONDARY) { 15 va_low = ~va_low; 16 } 17 /* xor vsid from AVA */ 18 if (!(v & HPTE64_V_1TB_SEG)) { 19 va_low ^= v >> 12; 20 } else { 21 va_low ^= v >> 24; 22 } 23 va_low &= 0x7ff; 24 if (v & HPTE64_V_LARGE) { 25 rb |= 1; /* L field */ 26 #if 0 /* Disable that P7 specific bit for now */ 27 if (r & 0xff000) { 28 /* non-16MB large page, must be 64k */ 29 /* (masks depend on page size) */ 30 rb |= 0x1000; /* page encoding in LP field */ 31 rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */ 32 rb |= (va_low & 0xfe); /* AVAL field */ 33 } 34 #endif 35 } else { 36 /* 4kB page */ 37 rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ 38 } 39 rb |= (v >> 54) & 0x300; /* B field */ 40 return rb; 41 } 42 43 static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index) 44 { 45 /* 46 * hash value/pteg group index is normalized by htab_mask 47 */ 48 if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) { 49 return false; 50 } 51 return true; 52 } 53 54 static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr, 55 target_ulong opcode, target_ulong *args) 56 { 57 CPUPPCState *env = &cpu->env; 58 target_ulong flags = args[0]; 59 target_ulong pte_index = args[1]; 60 target_ulong pteh = args[2]; 61 target_ulong ptel = args[3]; 62 target_ulong page_shift = 12; 63 target_ulong raddr; 64 target_ulong i; 65 hwaddr hpte; 66 67 /* only handle 4k and 16M pages for now */ 68 if (pteh & HPTE64_V_LARGE) { 69 #if 0 /* We don't support 64k pages yet */ 70 if ((ptel & 0xf000) == 0x1000) { 71 /* 64k page */ 72 } else 73 #endif 74 if ((ptel & 0xff000) == 0) { 75 /* 16M page */ 76 page_shift = 24; 77 /* lowest AVA bit must be 0 for 16M pages */ 78 if (pteh & 0x80) { 79 return H_PARAMETER; 80 } 81 } else { 82 return H_PARAMETER; 83 } 84 } 85 86 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1); 87 88 if (raddr < spapr->ram_limit) { 89 /* Regular RAM - should have WIMG=0010 */ 90 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 91 return H_PARAMETER; 92 } 93 } else { 94 /* Looks like an IO address */ 95 /* FIXME: What WIMG combinations could be sensible for IO? 96 * For now we allow WIMG=010x, but are there others? */ 97 /* FIXME: Should we check against registered IO addresses? */ 98 if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) { 99 return H_PARAMETER; 100 } 101 } 102 103 pteh &= ~0x60ULL; 104 105 if (!valid_pte_index(env, pte_index)) { 106 return H_PARAMETER; 107 } 108 if (likely((flags & H_EXACT) == 0)) { 109 pte_index &= ~7ULL; 110 hpte = pte_index * HASH_PTE_SIZE_64; 111 for (i = 0; ; ++i) { 112 if (i == 8) { 113 return H_PTEG_FULL; 114 } 115 if ((ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) == 0) { 116 break; 117 } 118 hpte += HASH_PTE_SIZE_64; 119 } 120 } else { 121 i = 0; 122 hpte = pte_index * HASH_PTE_SIZE_64; 123 if (ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) { 124 return H_PTEG_FULL; 125 } 126 } 127 ppc_hash64_store_hpte1(env, hpte, ptel); 128 /* eieio(); FIXME: need some sort of barrier for smp? */ 129 ppc_hash64_store_hpte0(env, hpte, pteh | HPTE64_V_HPTE_DIRTY); 130 131 args[0] = pte_index + i; 132 return H_SUCCESS; 133 } 134 135 typedef enum { 136 REMOVE_SUCCESS = 0, 137 REMOVE_NOT_FOUND = 1, 138 REMOVE_PARM = 2, 139 REMOVE_HW = 3, 140 } RemoveResult; 141 142 static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex, 143 target_ulong avpn, 144 target_ulong flags, 145 target_ulong *vp, target_ulong *rp) 146 { 147 hwaddr hpte; 148 target_ulong v, r, rb; 149 150 if (!valid_pte_index(env, ptex)) { 151 return REMOVE_PARM; 152 } 153 154 hpte = ptex * HASH_PTE_SIZE_64; 155 156 v = ppc_hash64_load_hpte0(env, hpte); 157 r = ppc_hash64_load_hpte1(env, hpte); 158 159 if ((v & HPTE64_V_VALID) == 0 || 160 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 161 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 162 return REMOVE_NOT_FOUND; 163 } 164 *vp = v; 165 *rp = r; 166 ppc_hash64_store_hpte0(env, hpte, HPTE64_V_HPTE_DIRTY); 167 rb = compute_tlbie_rb(v, r, ptex); 168 ppc_tlb_invalidate_one(env, rb); 169 return REMOVE_SUCCESS; 170 } 171 172 static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, 173 target_ulong opcode, target_ulong *args) 174 { 175 CPUPPCState *env = &cpu->env; 176 target_ulong flags = args[0]; 177 target_ulong pte_index = args[1]; 178 target_ulong avpn = args[2]; 179 RemoveResult ret; 180 181 ret = remove_hpte(env, pte_index, avpn, flags, 182 &args[0], &args[1]); 183 184 switch (ret) { 185 case REMOVE_SUCCESS: 186 return H_SUCCESS; 187 188 case REMOVE_NOT_FOUND: 189 return H_NOT_FOUND; 190 191 case REMOVE_PARM: 192 return H_PARAMETER; 193 194 case REMOVE_HW: 195 return H_HARDWARE; 196 } 197 198 g_assert_not_reached(); 199 } 200 201 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 202 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 203 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 204 #define H_BULK_REMOVE_END 0xc000000000000000ULL 205 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 206 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 207 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 208 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 209 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 210 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 211 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 212 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 213 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 214 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 215 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 216 217 #define H_BULK_REMOVE_MAX_BATCH 4 218 219 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, 220 target_ulong opcode, target_ulong *args) 221 { 222 CPUPPCState *env = &cpu->env; 223 int i; 224 225 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 226 target_ulong *tsh = &args[i*2]; 227 target_ulong tsl = args[i*2 + 1]; 228 target_ulong v, r, ret; 229 230 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 231 break; 232 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 233 return H_PARAMETER; 234 } 235 236 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 237 *tsh |= H_BULK_REMOVE_RESPONSE; 238 239 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 240 *tsh |= H_BULK_REMOVE_PARM; 241 return H_PARAMETER; 242 } 243 244 ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl, 245 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 246 &v, &r); 247 248 *tsh |= ret << 60; 249 250 switch (ret) { 251 case REMOVE_SUCCESS: 252 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 253 break; 254 255 case REMOVE_PARM: 256 return H_PARAMETER; 257 258 case REMOVE_HW: 259 return H_HARDWARE; 260 } 261 } 262 263 return H_SUCCESS; 264 } 265 266 static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr, 267 target_ulong opcode, target_ulong *args) 268 { 269 CPUPPCState *env = &cpu->env; 270 target_ulong flags = args[0]; 271 target_ulong pte_index = args[1]; 272 target_ulong avpn = args[2]; 273 hwaddr hpte; 274 target_ulong v, r, rb; 275 276 if (!valid_pte_index(env, pte_index)) { 277 return H_PARAMETER; 278 } 279 280 hpte = pte_index * HASH_PTE_SIZE_64; 281 282 v = ppc_hash64_load_hpte0(env, hpte); 283 r = ppc_hash64_load_hpte1(env, hpte); 284 285 if ((v & HPTE64_V_VALID) == 0 || 286 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 287 return H_NOT_FOUND; 288 } 289 290 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 291 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 292 r |= (flags << 55) & HPTE64_R_PP0; 293 r |= (flags << 48) & HPTE64_R_KEY_HI; 294 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 295 rb = compute_tlbie_rb(v, r, pte_index); 296 ppc_hash64_store_hpte0(env, hpte, (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY); 297 ppc_tlb_invalidate_one(env, rb); 298 ppc_hash64_store_hpte1(env, hpte, r); 299 /* Don't need a memory barrier, due to qemu's global lock */ 300 ppc_hash64_store_hpte0(env, hpte, v | HPTE64_V_HPTE_DIRTY); 301 return H_SUCCESS; 302 } 303 304 static target_ulong h_read(PowerPCCPU *cpu, sPAPREnvironment *spapr, 305 target_ulong opcode, target_ulong *args) 306 { 307 CPUPPCState *env = &cpu->env; 308 target_ulong flags = args[0]; 309 target_ulong pte_index = args[1]; 310 uint8_t *hpte; 311 int i, ridx, n_entries = 1; 312 313 if (!valid_pte_index(env, pte_index)) { 314 return H_PARAMETER; 315 } 316 317 if (flags & H_READ_4) { 318 /* Clear the two low order bits */ 319 pte_index &= ~(3ULL); 320 n_entries = 4; 321 } 322 323 hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); 324 325 for (i = 0, ridx = 0; i < n_entries; i++) { 326 args[ridx++] = ldq_p(hpte); 327 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 328 hpte += HASH_PTE_SIZE_64; 329 } 330 331 return H_SUCCESS; 332 } 333 334 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr, 335 target_ulong opcode, target_ulong *args) 336 { 337 /* FIXME: actually implement this */ 338 return H_HARDWARE; 339 } 340 341 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 342 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 343 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 344 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 345 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 346 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 347 348 #define VPA_MIN_SIZE 640 349 #define VPA_SIZE_OFFSET 0x4 350 #define VPA_SHARED_PROC_OFFSET 0x9 351 #define VPA_SHARED_PROC_VAL 0x2 352 353 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 354 { 355 CPUState *cs = ENV_GET_CPU(env); 356 uint16_t size; 357 uint8_t tmp; 358 359 if (vpa == 0) { 360 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 361 return H_HARDWARE; 362 } 363 364 if (vpa % env->dcache_line_size) { 365 return H_PARAMETER; 366 } 367 /* FIXME: bounds check the address */ 368 369 size = lduw_be_phys(cs->as, vpa + 0x4); 370 371 if (size < VPA_MIN_SIZE) { 372 return H_PARAMETER; 373 } 374 375 /* VPA is not allowed to cross a page boundary */ 376 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 377 return H_PARAMETER; 378 } 379 380 env->vpa_addr = vpa; 381 382 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 383 tmp |= VPA_SHARED_PROC_VAL; 384 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 385 386 return H_SUCCESS; 387 } 388 389 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 390 { 391 if (env->slb_shadow_addr) { 392 return H_RESOURCE; 393 } 394 395 if (env->dtl_addr) { 396 return H_RESOURCE; 397 } 398 399 env->vpa_addr = 0; 400 return H_SUCCESS; 401 } 402 403 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 404 { 405 CPUState *cs = ENV_GET_CPU(env); 406 uint32_t size; 407 408 if (addr == 0) { 409 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 410 return H_HARDWARE; 411 } 412 413 size = ldl_be_phys(cs->as, addr + 0x4); 414 if (size < 0x8) { 415 return H_PARAMETER; 416 } 417 418 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 419 return H_PARAMETER; 420 } 421 422 if (!env->vpa_addr) { 423 return H_RESOURCE; 424 } 425 426 env->slb_shadow_addr = addr; 427 env->slb_shadow_size = size; 428 429 return H_SUCCESS; 430 } 431 432 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 433 { 434 env->slb_shadow_addr = 0; 435 env->slb_shadow_size = 0; 436 return H_SUCCESS; 437 } 438 439 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 440 { 441 CPUState *cs = ENV_GET_CPU(env); 442 uint32_t size; 443 444 if (addr == 0) { 445 hcall_dprintf("Can't cope with DTL at logical 0\n"); 446 return H_HARDWARE; 447 } 448 449 size = ldl_be_phys(cs->as, addr + 0x4); 450 451 if (size < 48) { 452 return H_PARAMETER; 453 } 454 455 if (!env->vpa_addr) { 456 return H_RESOURCE; 457 } 458 459 env->dtl_addr = addr; 460 env->dtl_size = size; 461 462 return H_SUCCESS; 463 } 464 465 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 466 { 467 env->dtl_addr = 0; 468 env->dtl_size = 0; 469 470 return H_SUCCESS; 471 } 472 473 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr, 474 target_ulong opcode, target_ulong *args) 475 { 476 target_ulong flags = args[0]; 477 target_ulong procno = args[1]; 478 target_ulong vpa = args[2]; 479 target_ulong ret = H_PARAMETER; 480 CPUPPCState *tenv; 481 CPUState *tcpu; 482 483 tcpu = qemu_get_cpu(procno); 484 if (!tcpu) { 485 return H_PARAMETER; 486 } 487 tenv = tcpu->env_ptr; 488 489 switch (flags) { 490 case FLAGS_REGISTER_VPA: 491 ret = register_vpa(tenv, vpa); 492 break; 493 494 case FLAGS_DEREGISTER_VPA: 495 ret = deregister_vpa(tenv, vpa); 496 break; 497 498 case FLAGS_REGISTER_SLBSHADOW: 499 ret = register_slb_shadow(tenv, vpa); 500 break; 501 502 case FLAGS_DEREGISTER_SLBSHADOW: 503 ret = deregister_slb_shadow(tenv, vpa); 504 break; 505 506 case FLAGS_REGISTER_DTL: 507 ret = register_dtl(tenv, vpa); 508 break; 509 510 case FLAGS_DEREGISTER_DTL: 511 ret = deregister_dtl(tenv, vpa); 512 break; 513 } 514 515 return ret; 516 } 517 518 static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, 519 target_ulong opcode, target_ulong *args) 520 { 521 CPUPPCState *env = &cpu->env; 522 CPUState *cs = CPU(cpu); 523 524 env->msr |= (1ULL << MSR_EE); 525 hreg_compute_hflags(env); 526 if (!cpu_has_work(cs)) { 527 cs->halted = 1; 528 env->exception_index = EXCP_HLT; 529 cs->exit_request = 1; 530 } 531 return H_SUCCESS; 532 } 533 534 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr, 535 target_ulong opcode, target_ulong *args) 536 { 537 target_ulong rtas_r3 = args[0]; 538 uint32_t token = rtas_ld(rtas_r3, 0); 539 uint32_t nargs = rtas_ld(rtas_r3, 1); 540 uint32_t nret = rtas_ld(rtas_r3, 2); 541 542 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 543 nret, rtas_r3 + 12 + 4*nargs); 544 } 545 546 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr, 547 target_ulong opcode, target_ulong *args) 548 { 549 CPUState *cs = CPU(cpu); 550 target_ulong size = args[0]; 551 target_ulong addr = args[1]; 552 553 switch (size) { 554 case 1: 555 args[0] = ldub_phys(cs->as, addr); 556 return H_SUCCESS; 557 case 2: 558 args[0] = lduw_phys(cs->as, addr); 559 return H_SUCCESS; 560 case 4: 561 args[0] = ldl_phys(cs->as, addr); 562 return H_SUCCESS; 563 case 8: 564 args[0] = ldq_phys(cs->as, addr); 565 return H_SUCCESS; 566 } 567 return H_PARAMETER; 568 } 569 570 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr, 571 target_ulong opcode, target_ulong *args) 572 { 573 CPUState *cs = CPU(cpu); 574 575 target_ulong size = args[0]; 576 target_ulong addr = args[1]; 577 target_ulong val = args[2]; 578 579 switch (size) { 580 case 1: 581 stb_phys(cs->as, addr, val); 582 return H_SUCCESS; 583 case 2: 584 stw_phys(cs->as, addr, val); 585 return H_SUCCESS; 586 case 4: 587 stl_phys(cs->as, addr, val); 588 return H_SUCCESS; 589 case 8: 590 stq_phys(cs->as, addr, val); 591 return H_SUCCESS; 592 } 593 return H_PARAMETER; 594 } 595 596 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr, 597 target_ulong opcode, target_ulong *args) 598 { 599 CPUState *cs = CPU(cpu); 600 601 target_ulong dst = args[0]; /* Destination address */ 602 target_ulong src = args[1]; /* Source address */ 603 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 604 target_ulong count = args[3]; /* Element count */ 605 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 606 uint64_t tmp; 607 unsigned int mask = (1 << esize) - 1; 608 int step = 1 << esize; 609 610 if (count > 0x80000000) { 611 return H_PARAMETER; 612 } 613 614 if ((dst & mask) || (src & mask) || (op > 1)) { 615 return H_PARAMETER; 616 } 617 618 if (dst >= src && dst < (src + (count << esize))) { 619 dst = dst + ((count - 1) << esize); 620 src = src + ((count - 1) << esize); 621 step = -step; 622 } 623 624 while (count--) { 625 switch (esize) { 626 case 0: 627 tmp = ldub_phys(cs->as, src); 628 break; 629 case 1: 630 tmp = lduw_phys(cs->as, src); 631 break; 632 case 2: 633 tmp = ldl_phys(cs->as, src); 634 break; 635 case 3: 636 tmp = ldq_phys(cs->as, src); 637 break; 638 default: 639 return H_PARAMETER; 640 } 641 if (op == 1) { 642 tmp = ~tmp; 643 } 644 switch (esize) { 645 case 0: 646 stb_phys(cs->as, dst, tmp); 647 break; 648 case 1: 649 stw_phys(cs->as, dst, tmp); 650 break; 651 case 2: 652 stl_phys(cs->as, dst, tmp); 653 break; 654 case 3: 655 stq_phys(cs->as, dst, tmp); 656 break; 657 } 658 dst = dst + step; 659 src = src + step; 660 } 661 662 return H_SUCCESS; 663 } 664 665 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr, 666 target_ulong opcode, target_ulong *args) 667 { 668 /* Nothing to do on emulation, KVM will trap this in the kernel */ 669 return H_SUCCESS; 670 } 671 672 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr, 673 target_ulong opcode, target_ulong *args) 674 { 675 /* Nothing to do on emulation, KVM will trap this in the kernel */ 676 return H_SUCCESS; 677 } 678 679 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, 680 target_ulong opcode, target_ulong *args) 681 { 682 CPUState *cs; 683 target_ulong mflags = args[0]; 684 target_ulong resource = args[1]; 685 target_ulong value1 = args[2]; 686 target_ulong value2 = args[3]; 687 target_ulong ret = H_P2; 688 689 if (resource == H_SET_MODE_ENDIAN) { 690 if (value1) { 691 ret = H_P3; 692 goto out; 693 } 694 if (value2) { 695 ret = H_P4; 696 goto out; 697 } 698 699 switch (mflags) { 700 case H_SET_MODE_ENDIAN_BIG: 701 CPU_FOREACH(cs) { 702 PowerPCCPU *cp = POWERPC_CPU(cs); 703 CPUPPCState *env = &cp->env; 704 env->spr[SPR_LPCR] &= ~LPCR_ILE; 705 } 706 ret = H_SUCCESS; 707 break; 708 709 case H_SET_MODE_ENDIAN_LITTLE: 710 CPU_FOREACH(cs) { 711 PowerPCCPU *cp = POWERPC_CPU(cs); 712 CPUPPCState *env = &cp->env; 713 env->spr[SPR_LPCR] |= LPCR_ILE; 714 } 715 ret = H_SUCCESS; 716 break; 717 718 default: 719 ret = H_UNSUPPORTED_FLAG; 720 } 721 } 722 723 out: 724 return ret; 725 } 726 727 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 728 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 729 730 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 731 { 732 spapr_hcall_fn *slot; 733 734 if (opcode <= MAX_HCALL_OPCODE) { 735 assert((opcode & 0x3) == 0); 736 737 slot = &papr_hypercall_table[opcode / 4]; 738 } else { 739 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 740 741 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 742 } 743 744 assert(!(*slot)); 745 *slot = fn; 746 } 747 748 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 749 target_ulong *args) 750 { 751 if ((opcode <= MAX_HCALL_OPCODE) 752 && ((opcode & 0x3) == 0)) { 753 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 754 755 if (fn) { 756 return fn(cpu, spapr, opcode, args); 757 } 758 } else if ((opcode >= KVMPPC_HCALL_BASE) && 759 (opcode <= KVMPPC_HCALL_MAX)) { 760 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 761 762 if (fn) { 763 return fn(cpu, spapr, opcode, args); 764 } 765 } 766 767 hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); 768 return H_FUNCTION; 769 } 770 771 static void hypercall_register_types(void) 772 { 773 /* hcall-pft */ 774 spapr_register_hypercall(H_ENTER, h_enter); 775 spapr_register_hypercall(H_REMOVE, h_remove); 776 spapr_register_hypercall(H_PROTECT, h_protect); 777 spapr_register_hypercall(H_READ, h_read); 778 779 /* hcall-bulk */ 780 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 781 782 /* hcall-dabr */ 783 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 784 785 /* hcall-splpar */ 786 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 787 spapr_register_hypercall(H_CEDE, h_cede); 788 789 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 790 * here between the "CI" and the "CACHE" variants, they will use whatever 791 * mapping attributes qemu is using. When using KVM, the kernel will 792 * enforce the attributes more strongly 793 */ 794 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 795 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 796 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 797 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 798 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 799 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 800 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 801 802 /* qemu/KVM-PPC specific hcalls */ 803 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 804 805 spapr_register_hypercall(H_SET_MODE, h_set_mode); 806 } 807 808 type_init(hypercall_register_types) 809