1 #include "sysemu/sysemu.h" 2 #include "cpu.h" 3 #include "helper_regs.h" 4 #include "hw/ppc/spapr.h" 5 #include "mmu-hash64.h" 6 7 static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, 8 target_ulong pte_index) 9 { 10 target_ulong rb, va_low; 11 12 rb = (v & ~0x7fULL) << 16; /* AVA field */ 13 va_low = pte_index >> 3; 14 if (v & HPTE64_V_SECONDARY) { 15 va_low = ~va_low; 16 } 17 /* xor vsid from AVA */ 18 if (!(v & HPTE64_V_1TB_SEG)) { 19 va_low ^= v >> 12; 20 } else { 21 va_low ^= v >> 24; 22 } 23 va_low &= 0x7ff; 24 if (v & HPTE64_V_LARGE) { 25 rb |= 1; /* L field */ 26 #if 0 /* Disable that P7 specific bit for now */ 27 if (r & 0xff000) { 28 /* non-16MB large page, must be 64k */ 29 /* (masks depend on page size) */ 30 rb |= 0x1000; /* page encoding in LP field */ 31 rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */ 32 rb |= (va_low & 0xfe); /* AVAL field */ 33 } 34 #endif 35 } else { 36 /* 4kB page */ 37 rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ 38 } 39 rb |= (v >> 54) & 0x300; /* B field */ 40 return rb; 41 } 42 43 static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index) 44 { 45 /* 46 * hash value/pteg group index is normalized by htab_mask 47 */ 48 if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) { 49 return false; 50 } 51 return true; 52 } 53 54 static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr, 55 target_ulong opcode, target_ulong *args) 56 { 57 CPUPPCState *env = &cpu->env; 58 target_ulong flags = args[0]; 59 target_ulong pte_index = args[1]; 60 target_ulong pteh = args[2]; 61 target_ulong ptel = args[3]; 62 target_ulong page_shift = 12; 63 target_ulong raddr; 64 target_ulong index; 65 uint64_t token; 66 67 /* only handle 4k and 16M pages for now */ 68 if (pteh & HPTE64_V_LARGE) { 69 #if 0 /* We don't support 64k pages yet */ 70 if ((ptel & 0xf000) == 0x1000) { 71 /* 64k page */ 72 } else 73 #endif 74 if ((ptel & 0xff000) == 0) { 75 /* 16M page */ 76 page_shift = 24; 77 /* lowest AVA bit must be 0 for 16M pages */ 78 if (pteh & 0x80) { 79 return H_PARAMETER; 80 } 81 } else { 82 return H_PARAMETER; 83 } 84 } 85 86 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1); 87 88 if (raddr < spapr->ram_limit) { 89 /* Regular RAM - should have WIMG=0010 */ 90 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 91 return H_PARAMETER; 92 } 93 } else { 94 /* Looks like an IO address */ 95 /* FIXME: What WIMG combinations could be sensible for IO? 96 * For now we allow WIMG=010x, but are there others? */ 97 /* FIXME: Should we check against registered IO addresses? */ 98 if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) { 99 return H_PARAMETER; 100 } 101 } 102 103 pteh &= ~0x60ULL; 104 105 if (!valid_pte_index(env, pte_index)) { 106 return H_PARAMETER; 107 } 108 109 index = 0; 110 if (likely((flags & H_EXACT) == 0)) { 111 pte_index &= ~7ULL; 112 token = ppc_hash64_start_access(cpu, pte_index); 113 for (; index < 8; index++) { 114 if ((ppc_hash64_load_hpte0(env, token, index) & HPTE64_V_VALID) == 0) { 115 break; 116 } 117 } 118 ppc_hash64_stop_access(token); 119 if (index == 8) { 120 return H_PTEG_FULL; 121 } 122 } else { 123 token = ppc_hash64_start_access(cpu, pte_index); 124 if (ppc_hash64_load_hpte0(env, token, 0) & HPTE64_V_VALID) { 125 ppc_hash64_stop_access(token); 126 return H_PTEG_FULL; 127 } 128 ppc_hash64_stop_access(token); 129 } 130 131 ppc_hash64_store_hpte(env, pte_index + index, 132 pteh | HPTE64_V_HPTE_DIRTY, ptel); 133 134 args[0] = pte_index + index; 135 return H_SUCCESS; 136 } 137 138 typedef enum { 139 REMOVE_SUCCESS = 0, 140 REMOVE_NOT_FOUND = 1, 141 REMOVE_PARM = 2, 142 REMOVE_HW = 3, 143 } RemoveResult; 144 145 static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex, 146 target_ulong avpn, 147 target_ulong flags, 148 target_ulong *vp, target_ulong *rp) 149 { 150 uint64_t token; 151 target_ulong v, r, rb; 152 153 if (!valid_pte_index(env, ptex)) { 154 return REMOVE_PARM; 155 } 156 157 token = ppc_hash64_start_access(ppc_env_get_cpu(env), ptex); 158 v = ppc_hash64_load_hpte0(env, token, 0); 159 r = ppc_hash64_load_hpte1(env, token, 0); 160 ppc_hash64_stop_access(token); 161 162 if ((v & HPTE64_V_VALID) == 0 || 163 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 164 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 165 return REMOVE_NOT_FOUND; 166 } 167 *vp = v; 168 *rp = r; 169 ppc_hash64_store_hpte(env, ptex, HPTE64_V_HPTE_DIRTY, 0); 170 rb = compute_tlbie_rb(v, r, ptex); 171 ppc_tlb_invalidate_one(env, rb); 172 return REMOVE_SUCCESS; 173 } 174 175 static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, 176 target_ulong opcode, target_ulong *args) 177 { 178 CPUPPCState *env = &cpu->env; 179 target_ulong flags = args[0]; 180 target_ulong pte_index = args[1]; 181 target_ulong avpn = args[2]; 182 RemoveResult ret; 183 184 ret = remove_hpte(env, pte_index, avpn, flags, 185 &args[0], &args[1]); 186 187 switch (ret) { 188 case REMOVE_SUCCESS: 189 return H_SUCCESS; 190 191 case REMOVE_NOT_FOUND: 192 return H_NOT_FOUND; 193 194 case REMOVE_PARM: 195 return H_PARAMETER; 196 197 case REMOVE_HW: 198 return H_HARDWARE; 199 } 200 201 g_assert_not_reached(); 202 } 203 204 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 205 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 206 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 207 #define H_BULK_REMOVE_END 0xc000000000000000ULL 208 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 209 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 210 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 211 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 212 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 213 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 214 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 215 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 216 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 217 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 218 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 219 220 #define H_BULK_REMOVE_MAX_BATCH 4 221 222 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, 223 target_ulong opcode, target_ulong *args) 224 { 225 CPUPPCState *env = &cpu->env; 226 int i; 227 228 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 229 target_ulong *tsh = &args[i*2]; 230 target_ulong tsl = args[i*2 + 1]; 231 target_ulong v, r, ret; 232 233 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 234 break; 235 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 236 return H_PARAMETER; 237 } 238 239 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 240 *tsh |= H_BULK_REMOVE_RESPONSE; 241 242 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 243 *tsh |= H_BULK_REMOVE_PARM; 244 return H_PARAMETER; 245 } 246 247 ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl, 248 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 249 &v, &r); 250 251 *tsh |= ret << 60; 252 253 switch (ret) { 254 case REMOVE_SUCCESS: 255 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 256 break; 257 258 case REMOVE_PARM: 259 return H_PARAMETER; 260 261 case REMOVE_HW: 262 return H_HARDWARE; 263 } 264 } 265 266 return H_SUCCESS; 267 } 268 269 static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr, 270 target_ulong opcode, target_ulong *args) 271 { 272 CPUPPCState *env = &cpu->env; 273 target_ulong flags = args[0]; 274 target_ulong pte_index = args[1]; 275 target_ulong avpn = args[2]; 276 uint64_t token; 277 target_ulong v, r, rb; 278 279 if (!valid_pte_index(env, pte_index)) { 280 return H_PARAMETER; 281 } 282 283 token = ppc_hash64_start_access(cpu, pte_index); 284 v = ppc_hash64_load_hpte0(env, token, 0); 285 r = ppc_hash64_load_hpte1(env, token, 0); 286 ppc_hash64_stop_access(token); 287 288 if ((v & HPTE64_V_VALID) == 0 || 289 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 290 return H_NOT_FOUND; 291 } 292 293 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 294 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 295 r |= (flags << 55) & HPTE64_R_PP0; 296 r |= (flags << 48) & HPTE64_R_KEY_HI; 297 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 298 rb = compute_tlbie_rb(v, r, pte_index); 299 ppc_hash64_store_hpte(env, pte_index, 300 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 301 ppc_tlb_invalidate_one(env, rb); 302 /* Don't need a memory barrier, due to qemu's global lock */ 303 ppc_hash64_store_hpte(env, pte_index, v | HPTE64_V_HPTE_DIRTY, r); 304 return H_SUCCESS; 305 } 306 307 static target_ulong h_read(PowerPCCPU *cpu, sPAPREnvironment *spapr, 308 target_ulong opcode, target_ulong *args) 309 { 310 CPUPPCState *env = &cpu->env; 311 target_ulong flags = args[0]; 312 target_ulong pte_index = args[1]; 313 uint8_t *hpte; 314 int i, ridx, n_entries = 1; 315 316 if (!valid_pte_index(env, pte_index)) { 317 return H_PARAMETER; 318 } 319 320 if (flags & H_READ_4) { 321 /* Clear the two low order bits */ 322 pte_index &= ~(3ULL); 323 n_entries = 4; 324 } 325 326 hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); 327 328 for (i = 0, ridx = 0; i < n_entries; i++) { 329 args[ridx++] = ldq_p(hpte); 330 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 331 hpte += HASH_PTE_SIZE_64; 332 } 333 334 return H_SUCCESS; 335 } 336 337 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr, 338 target_ulong opcode, target_ulong *args) 339 { 340 /* FIXME: actually implement this */ 341 return H_HARDWARE; 342 } 343 344 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 345 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 346 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 347 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 348 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 349 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 350 351 #define VPA_MIN_SIZE 640 352 #define VPA_SIZE_OFFSET 0x4 353 #define VPA_SHARED_PROC_OFFSET 0x9 354 #define VPA_SHARED_PROC_VAL 0x2 355 356 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 357 { 358 CPUState *cs = CPU(ppc_env_get_cpu(env)); 359 uint16_t size; 360 uint8_t tmp; 361 362 if (vpa == 0) { 363 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 364 return H_HARDWARE; 365 } 366 367 if (vpa % env->dcache_line_size) { 368 return H_PARAMETER; 369 } 370 /* FIXME: bounds check the address */ 371 372 size = lduw_be_phys(cs->as, vpa + 0x4); 373 374 if (size < VPA_MIN_SIZE) { 375 return H_PARAMETER; 376 } 377 378 /* VPA is not allowed to cross a page boundary */ 379 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 380 return H_PARAMETER; 381 } 382 383 env->vpa_addr = vpa; 384 385 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 386 tmp |= VPA_SHARED_PROC_VAL; 387 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 388 389 return H_SUCCESS; 390 } 391 392 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 393 { 394 if (env->slb_shadow_addr) { 395 return H_RESOURCE; 396 } 397 398 if (env->dtl_addr) { 399 return H_RESOURCE; 400 } 401 402 env->vpa_addr = 0; 403 return H_SUCCESS; 404 } 405 406 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 407 { 408 CPUState *cs = CPU(ppc_env_get_cpu(env)); 409 uint32_t size; 410 411 if (addr == 0) { 412 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 413 return H_HARDWARE; 414 } 415 416 size = ldl_be_phys(cs->as, addr + 0x4); 417 if (size < 0x8) { 418 return H_PARAMETER; 419 } 420 421 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 422 return H_PARAMETER; 423 } 424 425 if (!env->vpa_addr) { 426 return H_RESOURCE; 427 } 428 429 env->slb_shadow_addr = addr; 430 env->slb_shadow_size = size; 431 432 return H_SUCCESS; 433 } 434 435 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 436 { 437 env->slb_shadow_addr = 0; 438 env->slb_shadow_size = 0; 439 return H_SUCCESS; 440 } 441 442 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 443 { 444 CPUState *cs = CPU(ppc_env_get_cpu(env)); 445 uint32_t size; 446 447 if (addr == 0) { 448 hcall_dprintf("Can't cope with DTL at logical 0\n"); 449 return H_HARDWARE; 450 } 451 452 size = ldl_be_phys(cs->as, addr + 0x4); 453 454 if (size < 48) { 455 return H_PARAMETER; 456 } 457 458 if (!env->vpa_addr) { 459 return H_RESOURCE; 460 } 461 462 env->dtl_addr = addr; 463 env->dtl_size = size; 464 465 return H_SUCCESS; 466 } 467 468 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 469 { 470 env->dtl_addr = 0; 471 env->dtl_size = 0; 472 473 return H_SUCCESS; 474 } 475 476 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr, 477 target_ulong opcode, target_ulong *args) 478 { 479 target_ulong flags = args[0]; 480 target_ulong procno = args[1]; 481 target_ulong vpa = args[2]; 482 target_ulong ret = H_PARAMETER; 483 CPUPPCState *tenv; 484 PowerPCCPU *tcpu; 485 486 tcpu = ppc_get_vcpu_by_dt_id(procno); 487 if (!tcpu) { 488 return H_PARAMETER; 489 } 490 tenv = &tcpu->env; 491 492 switch (flags) { 493 case FLAGS_REGISTER_VPA: 494 ret = register_vpa(tenv, vpa); 495 break; 496 497 case FLAGS_DEREGISTER_VPA: 498 ret = deregister_vpa(tenv, vpa); 499 break; 500 501 case FLAGS_REGISTER_SLBSHADOW: 502 ret = register_slb_shadow(tenv, vpa); 503 break; 504 505 case FLAGS_DEREGISTER_SLBSHADOW: 506 ret = deregister_slb_shadow(tenv, vpa); 507 break; 508 509 case FLAGS_REGISTER_DTL: 510 ret = register_dtl(tenv, vpa); 511 break; 512 513 case FLAGS_DEREGISTER_DTL: 514 ret = deregister_dtl(tenv, vpa); 515 break; 516 } 517 518 return ret; 519 } 520 521 static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, 522 target_ulong opcode, target_ulong *args) 523 { 524 CPUPPCState *env = &cpu->env; 525 CPUState *cs = CPU(cpu); 526 527 env->msr |= (1ULL << MSR_EE); 528 hreg_compute_hflags(env); 529 if (!cpu_has_work(cs)) { 530 cs->halted = 1; 531 cs->exception_index = EXCP_HLT; 532 cs->exit_request = 1; 533 } 534 return H_SUCCESS; 535 } 536 537 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr, 538 target_ulong opcode, target_ulong *args) 539 { 540 target_ulong rtas_r3 = args[0]; 541 uint32_t token = rtas_ld(rtas_r3, 0); 542 uint32_t nargs = rtas_ld(rtas_r3, 1); 543 uint32_t nret = rtas_ld(rtas_r3, 2); 544 545 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 546 nret, rtas_r3 + 12 + 4*nargs); 547 } 548 549 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr, 550 target_ulong opcode, target_ulong *args) 551 { 552 CPUState *cs = CPU(cpu); 553 target_ulong size = args[0]; 554 target_ulong addr = args[1]; 555 556 switch (size) { 557 case 1: 558 args[0] = ldub_phys(cs->as, addr); 559 return H_SUCCESS; 560 case 2: 561 args[0] = lduw_phys(cs->as, addr); 562 return H_SUCCESS; 563 case 4: 564 args[0] = ldl_phys(cs->as, addr); 565 return H_SUCCESS; 566 case 8: 567 args[0] = ldq_phys(cs->as, addr); 568 return H_SUCCESS; 569 } 570 return H_PARAMETER; 571 } 572 573 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr, 574 target_ulong opcode, target_ulong *args) 575 { 576 CPUState *cs = CPU(cpu); 577 578 target_ulong size = args[0]; 579 target_ulong addr = args[1]; 580 target_ulong val = args[2]; 581 582 switch (size) { 583 case 1: 584 stb_phys(cs->as, addr, val); 585 return H_SUCCESS; 586 case 2: 587 stw_phys(cs->as, addr, val); 588 return H_SUCCESS; 589 case 4: 590 stl_phys(cs->as, addr, val); 591 return H_SUCCESS; 592 case 8: 593 stq_phys(cs->as, addr, val); 594 return H_SUCCESS; 595 } 596 return H_PARAMETER; 597 } 598 599 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr, 600 target_ulong opcode, target_ulong *args) 601 { 602 CPUState *cs = CPU(cpu); 603 604 target_ulong dst = args[0]; /* Destination address */ 605 target_ulong src = args[1]; /* Source address */ 606 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 607 target_ulong count = args[3]; /* Element count */ 608 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 609 uint64_t tmp; 610 unsigned int mask = (1 << esize) - 1; 611 int step = 1 << esize; 612 613 if (count > 0x80000000) { 614 return H_PARAMETER; 615 } 616 617 if ((dst & mask) || (src & mask) || (op > 1)) { 618 return H_PARAMETER; 619 } 620 621 if (dst >= src && dst < (src + (count << esize))) { 622 dst = dst + ((count - 1) << esize); 623 src = src + ((count - 1) << esize); 624 step = -step; 625 } 626 627 while (count--) { 628 switch (esize) { 629 case 0: 630 tmp = ldub_phys(cs->as, src); 631 break; 632 case 1: 633 tmp = lduw_phys(cs->as, src); 634 break; 635 case 2: 636 tmp = ldl_phys(cs->as, src); 637 break; 638 case 3: 639 tmp = ldq_phys(cs->as, src); 640 break; 641 default: 642 return H_PARAMETER; 643 } 644 if (op == 1) { 645 tmp = ~tmp; 646 } 647 switch (esize) { 648 case 0: 649 stb_phys(cs->as, dst, tmp); 650 break; 651 case 1: 652 stw_phys(cs->as, dst, tmp); 653 break; 654 case 2: 655 stl_phys(cs->as, dst, tmp); 656 break; 657 case 3: 658 stq_phys(cs->as, dst, tmp); 659 break; 660 } 661 dst = dst + step; 662 src = src + step; 663 } 664 665 return H_SUCCESS; 666 } 667 668 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr, 669 target_ulong opcode, target_ulong *args) 670 { 671 /* Nothing to do on emulation, KVM will trap this in the kernel */ 672 return H_SUCCESS; 673 } 674 675 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr, 676 target_ulong opcode, target_ulong *args) 677 { 678 /* Nothing to do on emulation, KVM will trap this in the kernel */ 679 return H_SUCCESS; 680 } 681 682 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, 683 target_ulong opcode, target_ulong *args) 684 { 685 CPUState *cs; 686 target_ulong mflags = args[0]; 687 target_ulong resource = args[1]; 688 target_ulong value1 = args[2]; 689 target_ulong value2 = args[3]; 690 target_ulong ret = H_P2; 691 692 if (resource == H_SET_MODE_ENDIAN) { 693 if (value1) { 694 ret = H_P3; 695 goto out; 696 } 697 if (value2) { 698 ret = H_P4; 699 goto out; 700 } 701 702 switch (mflags) { 703 case H_SET_MODE_ENDIAN_BIG: 704 CPU_FOREACH(cs) { 705 PowerPCCPU *cp = POWERPC_CPU(cs); 706 CPUPPCState *env = &cp->env; 707 env->spr[SPR_LPCR] &= ~LPCR_ILE; 708 } 709 ret = H_SUCCESS; 710 break; 711 712 case H_SET_MODE_ENDIAN_LITTLE: 713 CPU_FOREACH(cs) { 714 PowerPCCPU *cp = POWERPC_CPU(cs); 715 CPUPPCState *env = &cp->env; 716 env->spr[SPR_LPCR] |= LPCR_ILE; 717 } 718 ret = H_SUCCESS; 719 break; 720 721 default: 722 ret = H_UNSUPPORTED_FLAG; 723 } 724 } 725 726 out: 727 return ret; 728 } 729 730 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 731 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 732 733 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 734 { 735 spapr_hcall_fn *slot; 736 737 if (opcode <= MAX_HCALL_OPCODE) { 738 assert((opcode & 0x3) == 0); 739 740 slot = &papr_hypercall_table[opcode / 4]; 741 } else { 742 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 743 744 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 745 } 746 747 assert(!(*slot)); 748 *slot = fn; 749 } 750 751 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 752 target_ulong *args) 753 { 754 if ((opcode <= MAX_HCALL_OPCODE) 755 && ((opcode & 0x3) == 0)) { 756 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 757 758 if (fn) { 759 return fn(cpu, spapr, opcode, args); 760 } 761 } else if ((opcode >= KVMPPC_HCALL_BASE) && 762 (opcode <= KVMPPC_HCALL_MAX)) { 763 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 764 765 if (fn) { 766 return fn(cpu, spapr, opcode, args); 767 } 768 } 769 770 hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); 771 return H_FUNCTION; 772 } 773 774 static void hypercall_register_types(void) 775 { 776 /* hcall-pft */ 777 spapr_register_hypercall(H_ENTER, h_enter); 778 spapr_register_hypercall(H_REMOVE, h_remove); 779 spapr_register_hypercall(H_PROTECT, h_protect); 780 spapr_register_hypercall(H_READ, h_read); 781 782 /* hcall-bulk */ 783 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 784 785 /* hcall-dabr */ 786 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 787 788 /* hcall-splpar */ 789 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 790 spapr_register_hypercall(H_CEDE, h_cede); 791 792 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 793 * here between the "CI" and the "CACHE" variants, they will use whatever 794 * mapping attributes qemu is using. When using KVM, the kernel will 795 * enforce the attributes more strongly 796 */ 797 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 798 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 799 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 800 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 801 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 802 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 803 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 804 805 /* qemu/KVM-PPC specific hcalls */ 806 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 807 808 spapr_register_hypercall(H_SET_MODE, h_set_mode); 809 } 810 811 type_init(hypercall_register_types) 812