1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/sysemu.h" 5 #include "qemu/log.h" 6 #include "cpu.h" 7 #include "exec/exec-all.h" 8 #include "helper_regs.h" 9 #include "hw/ppc/spapr.h" 10 #include "mmu-hash64.h" 11 #include "cpu-models.h" 12 #include "trace.h" 13 #include "kvm_ppc.h" 14 #include "hw/ppc/spapr_ovec.h" 15 16 struct SPRSyncState { 17 int spr; 18 target_ulong value; 19 target_ulong mask; 20 }; 21 22 static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 23 { 24 struct SPRSyncState *s = arg.host_ptr; 25 PowerPCCPU *cpu = POWERPC_CPU(cs); 26 CPUPPCState *env = &cpu->env; 27 28 cpu_synchronize_state(cs); 29 env->spr[s->spr] &= ~s->mask; 30 env->spr[s->spr] |= s->value; 31 } 32 33 static void set_spr(CPUState *cs, int spr, target_ulong value, 34 target_ulong mask) 35 { 36 struct SPRSyncState s = { 37 .spr = spr, 38 .value = value, 39 .mask = mask 40 }; 41 run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 42 } 43 44 static bool has_spr(PowerPCCPU *cpu, int spr) 45 { 46 /* We can test whether the SPR is defined by checking for a valid name */ 47 return cpu->env.spr_cb[spr].name != NULL; 48 } 49 50 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 51 { 52 /* 53 * hash value/pteg group index is normalized by HPT mask 54 */ 55 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 56 return false; 57 } 58 return true; 59 } 60 61 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 62 { 63 MachineState *machine = MACHINE(spapr); 64 MemoryHotplugState *hpms = &spapr->hotplug_memory; 65 66 if (addr < machine->ram_size) { 67 return true; 68 } 69 if ((addr >= hpms->base) 70 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 71 return true; 72 } 73 74 return false; 75 } 76 77 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 78 target_ulong opcode, target_ulong *args) 79 { 80 target_ulong flags = args[0]; 81 target_ulong ptex = args[1]; 82 target_ulong pteh = args[2]; 83 target_ulong ptel = args[3]; 84 unsigned apshift; 85 target_ulong raddr; 86 target_ulong slot; 87 const ppc_hash_pte64_t *hptes; 88 89 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 90 if (!apshift) { 91 /* Bad page size encoding */ 92 return H_PARAMETER; 93 } 94 95 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 96 97 if (is_ram_address(spapr, raddr)) { 98 /* Regular RAM - should have WIMG=0010 */ 99 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 100 return H_PARAMETER; 101 } 102 } else { 103 target_ulong wimg_flags; 104 /* Looks like an IO address */ 105 /* FIXME: What WIMG combinations could be sensible for IO? 106 * For now we allow WIMG=010x, but are there others? */ 107 /* FIXME: Should we check against registered IO addresses? */ 108 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 109 110 if (wimg_flags != HPTE64_R_I && 111 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 112 return H_PARAMETER; 113 } 114 } 115 116 pteh &= ~0x60ULL; 117 118 if (!valid_ptex(cpu, ptex)) { 119 return H_PARAMETER; 120 } 121 122 slot = ptex & 7ULL; 123 ptex = ptex & ~7ULL; 124 125 if (likely((flags & H_EXACT) == 0)) { 126 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 127 for (slot = 0; slot < 8; slot++) { 128 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 129 break; 130 } 131 } 132 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 133 if (slot == 8) { 134 return H_PTEG_FULL; 135 } 136 } else { 137 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 138 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 139 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 140 return H_PTEG_FULL; 141 } 142 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 143 } 144 145 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 146 147 args[0] = ptex + slot; 148 return H_SUCCESS; 149 } 150 151 typedef enum { 152 REMOVE_SUCCESS = 0, 153 REMOVE_NOT_FOUND = 1, 154 REMOVE_PARM = 2, 155 REMOVE_HW = 3, 156 } RemoveResult; 157 158 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 159 target_ulong avpn, 160 target_ulong flags, 161 target_ulong *vp, target_ulong *rp) 162 { 163 const ppc_hash_pte64_t *hptes; 164 target_ulong v, r; 165 166 if (!valid_ptex(cpu, ptex)) { 167 return REMOVE_PARM; 168 } 169 170 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 171 v = ppc_hash64_hpte0(cpu, hptes, 0); 172 r = ppc_hash64_hpte1(cpu, hptes, 0); 173 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 174 175 if ((v & HPTE64_V_VALID) == 0 || 176 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 177 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 178 return REMOVE_NOT_FOUND; 179 } 180 *vp = v; 181 *rp = r; 182 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 183 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 184 return REMOVE_SUCCESS; 185 } 186 187 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 188 target_ulong opcode, target_ulong *args) 189 { 190 CPUPPCState *env = &cpu->env; 191 target_ulong flags = args[0]; 192 target_ulong ptex = args[1]; 193 target_ulong avpn = args[2]; 194 RemoveResult ret; 195 196 ret = remove_hpte(cpu, ptex, avpn, flags, 197 &args[0], &args[1]); 198 199 switch (ret) { 200 case REMOVE_SUCCESS: 201 check_tlb_flush(env, true); 202 return H_SUCCESS; 203 204 case REMOVE_NOT_FOUND: 205 return H_NOT_FOUND; 206 207 case REMOVE_PARM: 208 return H_PARAMETER; 209 210 case REMOVE_HW: 211 return H_HARDWARE; 212 } 213 214 g_assert_not_reached(); 215 } 216 217 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 218 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 219 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 220 #define H_BULK_REMOVE_END 0xc000000000000000ULL 221 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 222 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 223 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 224 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 225 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 226 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 227 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 228 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 229 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 230 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 231 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 232 233 #define H_BULK_REMOVE_MAX_BATCH 4 234 235 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 236 target_ulong opcode, target_ulong *args) 237 { 238 CPUPPCState *env = &cpu->env; 239 int i; 240 target_ulong rc = H_SUCCESS; 241 242 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 243 target_ulong *tsh = &args[i*2]; 244 target_ulong tsl = args[i*2 + 1]; 245 target_ulong v, r, ret; 246 247 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 248 break; 249 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 250 return H_PARAMETER; 251 } 252 253 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 254 *tsh |= H_BULK_REMOVE_RESPONSE; 255 256 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 257 *tsh |= H_BULK_REMOVE_PARM; 258 return H_PARAMETER; 259 } 260 261 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 262 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 263 &v, &r); 264 265 *tsh |= ret << 60; 266 267 switch (ret) { 268 case REMOVE_SUCCESS: 269 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 270 break; 271 272 case REMOVE_PARM: 273 rc = H_PARAMETER; 274 goto exit; 275 276 case REMOVE_HW: 277 rc = H_HARDWARE; 278 goto exit; 279 } 280 } 281 exit: 282 check_tlb_flush(env, true); 283 284 return rc; 285 } 286 287 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 288 target_ulong opcode, target_ulong *args) 289 { 290 CPUPPCState *env = &cpu->env; 291 target_ulong flags = args[0]; 292 target_ulong ptex = args[1]; 293 target_ulong avpn = args[2]; 294 const ppc_hash_pte64_t *hptes; 295 target_ulong v, r; 296 297 if (!valid_ptex(cpu, ptex)) { 298 return H_PARAMETER; 299 } 300 301 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 302 v = ppc_hash64_hpte0(cpu, hptes, 0); 303 r = ppc_hash64_hpte1(cpu, hptes, 0); 304 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 305 306 if ((v & HPTE64_V_VALID) == 0 || 307 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 308 return H_NOT_FOUND; 309 } 310 311 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 312 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 313 r |= (flags << 55) & HPTE64_R_PP0; 314 r |= (flags << 48) & HPTE64_R_KEY_HI; 315 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 316 ppc_hash64_store_hpte(cpu, ptex, 317 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 318 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 319 /* Flush the tlb */ 320 check_tlb_flush(env, true); 321 /* Don't need a memory barrier, due to qemu's global lock */ 322 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 323 return H_SUCCESS; 324 } 325 326 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 327 target_ulong opcode, target_ulong *args) 328 { 329 CPUPPCState *env = &cpu->env; 330 target_ulong flags = args[0]; 331 target_ulong ptex = args[1]; 332 uint8_t *hpte; 333 int i, ridx, n_entries = 1; 334 335 if (!valid_ptex(cpu, ptex)) { 336 return H_PARAMETER; 337 } 338 339 if (flags & H_READ_4) { 340 /* Clear the two low order bits */ 341 ptex &= ~(3ULL); 342 n_entries = 4; 343 } 344 345 hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64); 346 347 for (i = 0, ridx = 0; i < n_entries; i++) { 348 args[ridx++] = ldq_p(hpte); 349 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 350 hpte += HASH_PTE_SIZE_64; 351 } 352 353 return H_SUCCESS; 354 } 355 356 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 357 target_ulong opcode, target_ulong *args) 358 { 359 cpu_synchronize_state(CPU(cpu)); 360 cpu->env.spr[SPR_SPRG0] = args[0]; 361 362 return H_SUCCESS; 363 } 364 365 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 366 target_ulong opcode, target_ulong *args) 367 { 368 if (!has_spr(cpu, SPR_DABR)) { 369 return H_HARDWARE; /* DABR register not available */ 370 } 371 cpu_synchronize_state(CPU(cpu)); 372 373 if (has_spr(cpu, SPR_DABRX)) { 374 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 375 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 376 return H_RESERVED_DABR; 377 } 378 379 cpu->env.spr[SPR_DABR] = args[0]; 380 return H_SUCCESS; 381 } 382 383 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 384 target_ulong opcode, target_ulong *args) 385 { 386 target_ulong dabrx = args[1]; 387 388 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 389 return H_HARDWARE; 390 } 391 392 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 393 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 394 return H_PARAMETER; 395 } 396 397 cpu_synchronize_state(CPU(cpu)); 398 cpu->env.spr[SPR_DABRX] = dabrx; 399 cpu->env.spr[SPR_DABR] = args[0]; 400 401 return H_SUCCESS; 402 } 403 404 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 405 target_ulong opcode, target_ulong *args) 406 { 407 target_ulong flags = args[0]; 408 hwaddr dst = args[1]; 409 hwaddr src = args[2]; 410 hwaddr len = TARGET_PAGE_SIZE; 411 uint8_t *pdst, *psrc; 412 target_long ret = H_SUCCESS; 413 414 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 415 | H_COPY_PAGE | H_ZERO_PAGE)) { 416 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 417 flags); 418 return H_PARAMETER; 419 } 420 421 /* Map-in destination */ 422 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 423 return H_PARAMETER; 424 } 425 pdst = cpu_physical_memory_map(dst, &len, 1); 426 if (!pdst || len != TARGET_PAGE_SIZE) { 427 return H_PARAMETER; 428 } 429 430 if (flags & H_COPY_PAGE) { 431 /* Map-in source, copy to destination, and unmap source again */ 432 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 433 ret = H_PARAMETER; 434 goto unmap_out; 435 } 436 psrc = cpu_physical_memory_map(src, &len, 0); 437 if (!psrc || len != TARGET_PAGE_SIZE) { 438 ret = H_PARAMETER; 439 goto unmap_out; 440 } 441 memcpy(pdst, psrc, len); 442 cpu_physical_memory_unmap(psrc, len, 0, len); 443 } else if (flags & H_ZERO_PAGE) { 444 memset(pdst, 0, len); /* Just clear the destination page */ 445 } 446 447 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 448 kvmppc_dcbst_range(cpu, pdst, len); 449 } 450 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 451 if (kvm_enabled()) { 452 kvmppc_icbi_range(cpu, pdst, len); 453 } else { 454 tb_flush(CPU(cpu)); 455 } 456 } 457 458 unmap_out: 459 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 460 return ret; 461 } 462 463 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 464 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 465 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 466 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 467 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 468 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 469 470 #define VPA_MIN_SIZE 640 471 #define VPA_SIZE_OFFSET 0x4 472 #define VPA_SHARED_PROC_OFFSET 0x9 473 #define VPA_SHARED_PROC_VAL 0x2 474 475 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 476 { 477 CPUState *cs = CPU(ppc_env_get_cpu(env)); 478 uint16_t size; 479 uint8_t tmp; 480 481 if (vpa == 0) { 482 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 483 return H_HARDWARE; 484 } 485 486 if (vpa % env->dcache_line_size) { 487 return H_PARAMETER; 488 } 489 /* FIXME: bounds check the address */ 490 491 size = lduw_be_phys(cs->as, vpa + 0x4); 492 493 if (size < VPA_MIN_SIZE) { 494 return H_PARAMETER; 495 } 496 497 /* VPA is not allowed to cross a page boundary */ 498 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 499 return H_PARAMETER; 500 } 501 502 env->vpa_addr = vpa; 503 504 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 505 tmp |= VPA_SHARED_PROC_VAL; 506 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 507 508 return H_SUCCESS; 509 } 510 511 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 512 { 513 if (env->slb_shadow_addr) { 514 return H_RESOURCE; 515 } 516 517 if (env->dtl_addr) { 518 return H_RESOURCE; 519 } 520 521 env->vpa_addr = 0; 522 return H_SUCCESS; 523 } 524 525 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 526 { 527 CPUState *cs = CPU(ppc_env_get_cpu(env)); 528 uint32_t size; 529 530 if (addr == 0) { 531 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 532 return H_HARDWARE; 533 } 534 535 size = ldl_be_phys(cs->as, addr + 0x4); 536 if (size < 0x8) { 537 return H_PARAMETER; 538 } 539 540 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 541 return H_PARAMETER; 542 } 543 544 if (!env->vpa_addr) { 545 return H_RESOURCE; 546 } 547 548 env->slb_shadow_addr = addr; 549 env->slb_shadow_size = size; 550 551 return H_SUCCESS; 552 } 553 554 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 555 { 556 env->slb_shadow_addr = 0; 557 env->slb_shadow_size = 0; 558 return H_SUCCESS; 559 } 560 561 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 562 { 563 CPUState *cs = CPU(ppc_env_get_cpu(env)); 564 uint32_t size; 565 566 if (addr == 0) { 567 hcall_dprintf("Can't cope with DTL at logical 0\n"); 568 return H_HARDWARE; 569 } 570 571 size = ldl_be_phys(cs->as, addr + 0x4); 572 573 if (size < 48) { 574 return H_PARAMETER; 575 } 576 577 if (!env->vpa_addr) { 578 return H_RESOURCE; 579 } 580 581 env->dtl_addr = addr; 582 env->dtl_size = size; 583 584 return H_SUCCESS; 585 } 586 587 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 588 { 589 env->dtl_addr = 0; 590 env->dtl_size = 0; 591 592 return H_SUCCESS; 593 } 594 595 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 596 target_ulong opcode, target_ulong *args) 597 { 598 target_ulong flags = args[0]; 599 target_ulong procno = args[1]; 600 target_ulong vpa = args[2]; 601 target_ulong ret = H_PARAMETER; 602 CPUPPCState *tenv; 603 PowerPCCPU *tcpu; 604 605 tcpu = ppc_get_vcpu_by_dt_id(procno); 606 if (!tcpu) { 607 return H_PARAMETER; 608 } 609 tenv = &tcpu->env; 610 611 switch (flags) { 612 case FLAGS_REGISTER_VPA: 613 ret = register_vpa(tenv, vpa); 614 break; 615 616 case FLAGS_DEREGISTER_VPA: 617 ret = deregister_vpa(tenv, vpa); 618 break; 619 620 case FLAGS_REGISTER_SLBSHADOW: 621 ret = register_slb_shadow(tenv, vpa); 622 break; 623 624 case FLAGS_DEREGISTER_SLBSHADOW: 625 ret = deregister_slb_shadow(tenv, vpa); 626 break; 627 628 case FLAGS_REGISTER_DTL: 629 ret = register_dtl(tenv, vpa); 630 break; 631 632 case FLAGS_DEREGISTER_DTL: 633 ret = deregister_dtl(tenv, vpa); 634 break; 635 } 636 637 return ret; 638 } 639 640 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 641 target_ulong opcode, target_ulong *args) 642 { 643 CPUPPCState *env = &cpu->env; 644 CPUState *cs = CPU(cpu); 645 646 env->msr |= (1ULL << MSR_EE); 647 hreg_compute_hflags(env); 648 if (!cpu_has_work(cs)) { 649 cs->halted = 1; 650 cs->exception_index = EXCP_HLT; 651 cs->exit_request = 1; 652 } 653 return H_SUCCESS; 654 } 655 656 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 657 target_ulong opcode, target_ulong *args) 658 { 659 target_ulong rtas_r3 = args[0]; 660 uint32_t token = rtas_ld(rtas_r3, 0); 661 uint32_t nargs = rtas_ld(rtas_r3, 1); 662 uint32_t nret = rtas_ld(rtas_r3, 2); 663 664 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 665 nret, rtas_r3 + 12 + 4*nargs); 666 } 667 668 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 669 target_ulong opcode, target_ulong *args) 670 { 671 CPUState *cs = CPU(cpu); 672 target_ulong size = args[0]; 673 target_ulong addr = args[1]; 674 675 switch (size) { 676 case 1: 677 args[0] = ldub_phys(cs->as, addr); 678 return H_SUCCESS; 679 case 2: 680 args[0] = lduw_phys(cs->as, addr); 681 return H_SUCCESS; 682 case 4: 683 args[0] = ldl_phys(cs->as, addr); 684 return H_SUCCESS; 685 case 8: 686 args[0] = ldq_phys(cs->as, addr); 687 return H_SUCCESS; 688 } 689 return H_PARAMETER; 690 } 691 692 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 693 target_ulong opcode, target_ulong *args) 694 { 695 CPUState *cs = CPU(cpu); 696 697 target_ulong size = args[0]; 698 target_ulong addr = args[1]; 699 target_ulong val = args[2]; 700 701 switch (size) { 702 case 1: 703 stb_phys(cs->as, addr, val); 704 return H_SUCCESS; 705 case 2: 706 stw_phys(cs->as, addr, val); 707 return H_SUCCESS; 708 case 4: 709 stl_phys(cs->as, addr, val); 710 return H_SUCCESS; 711 case 8: 712 stq_phys(cs->as, addr, val); 713 return H_SUCCESS; 714 } 715 return H_PARAMETER; 716 } 717 718 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 719 target_ulong opcode, target_ulong *args) 720 { 721 CPUState *cs = CPU(cpu); 722 723 target_ulong dst = args[0]; /* Destination address */ 724 target_ulong src = args[1]; /* Source address */ 725 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 726 target_ulong count = args[3]; /* Element count */ 727 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 728 uint64_t tmp; 729 unsigned int mask = (1 << esize) - 1; 730 int step = 1 << esize; 731 732 if (count > 0x80000000) { 733 return H_PARAMETER; 734 } 735 736 if ((dst & mask) || (src & mask) || (op > 1)) { 737 return H_PARAMETER; 738 } 739 740 if (dst >= src && dst < (src + (count << esize))) { 741 dst = dst + ((count - 1) << esize); 742 src = src + ((count - 1) << esize); 743 step = -step; 744 } 745 746 while (count--) { 747 switch (esize) { 748 case 0: 749 tmp = ldub_phys(cs->as, src); 750 break; 751 case 1: 752 tmp = lduw_phys(cs->as, src); 753 break; 754 case 2: 755 tmp = ldl_phys(cs->as, src); 756 break; 757 case 3: 758 tmp = ldq_phys(cs->as, src); 759 break; 760 default: 761 return H_PARAMETER; 762 } 763 if (op == 1) { 764 tmp = ~tmp; 765 } 766 switch (esize) { 767 case 0: 768 stb_phys(cs->as, dst, tmp); 769 break; 770 case 1: 771 stw_phys(cs->as, dst, tmp); 772 break; 773 case 2: 774 stl_phys(cs->as, dst, tmp); 775 break; 776 case 3: 777 stq_phys(cs->as, dst, tmp); 778 break; 779 } 780 dst = dst + step; 781 src = src + step; 782 } 783 784 return H_SUCCESS; 785 } 786 787 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 788 target_ulong opcode, target_ulong *args) 789 { 790 /* Nothing to do on emulation, KVM will trap this in the kernel */ 791 return H_SUCCESS; 792 } 793 794 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 795 target_ulong opcode, target_ulong *args) 796 { 797 /* Nothing to do on emulation, KVM will trap this in the kernel */ 798 return H_SUCCESS; 799 } 800 801 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 802 target_ulong mflags, 803 target_ulong value1, 804 target_ulong value2) 805 { 806 CPUState *cs; 807 808 if (value1) { 809 return H_P3; 810 } 811 if (value2) { 812 return H_P4; 813 } 814 815 switch (mflags) { 816 case H_SET_MODE_ENDIAN_BIG: 817 CPU_FOREACH(cs) { 818 set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 819 } 820 spapr_pci_switch_vga(true); 821 return H_SUCCESS; 822 823 case H_SET_MODE_ENDIAN_LITTLE: 824 CPU_FOREACH(cs) { 825 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 826 } 827 spapr_pci_switch_vga(false); 828 return H_SUCCESS; 829 } 830 831 return H_UNSUPPORTED_FLAG; 832 } 833 834 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 835 target_ulong mflags, 836 target_ulong value1, 837 target_ulong value2) 838 { 839 CPUState *cs; 840 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 841 842 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 843 return H_P2; 844 } 845 if (value1) { 846 return H_P3; 847 } 848 if (value2) { 849 return H_P4; 850 } 851 852 if (mflags == AIL_RESERVED) { 853 return H_UNSUPPORTED_FLAG; 854 } 855 856 CPU_FOREACH(cs) { 857 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 858 } 859 860 return H_SUCCESS; 861 } 862 863 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 864 target_ulong opcode, target_ulong *args) 865 { 866 target_ulong resource = args[1]; 867 target_ulong ret = H_P2; 868 869 switch (resource) { 870 case H_SET_MODE_RESOURCE_LE: 871 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 872 break; 873 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 874 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 875 args[2], args[3]); 876 break; 877 } 878 879 return ret; 880 } 881 882 #define H_SIGNAL_SYS_RESET_ALL -1 883 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 884 885 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 886 sPAPRMachineState *spapr, 887 target_ulong opcode, target_ulong *args) 888 { 889 target_long target = args[0]; 890 CPUState *cs; 891 892 if (target < 0) { 893 /* Broadcast */ 894 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 895 return H_PARAMETER; 896 } 897 898 CPU_FOREACH(cs) { 899 PowerPCCPU *c = POWERPC_CPU(cs); 900 901 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 902 if (c == cpu) { 903 continue; 904 } 905 } 906 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 907 } 908 return H_SUCCESS; 909 910 } else { 911 /* Unicast */ 912 CPU_FOREACH(cs) { 913 if (cpu->cpu_dt_id == target) { 914 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 915 return H_SUCCESS; 916 } 917 } 918 return H_PARAMETER; 919 } 920 } 921 922 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 923 sPAPRMachineState *spapr, 924 target_ulong opcode, 925 target_ulong *args) 926 { 927 target_ulong list = ppc64_phys_to_real(args[0]); 928 target_ulong ov_table; 929 bool explicit_match = false; /* Matched the CPU's real PVR */ 930 uint32_t max_compat = cpu->max_compat; 931 uint32_t best_compat = 0; 932 int i; 933 sPAPROptionVector *ov5_guest, *ov5_cas_old, *ov5_updates; 934 935 /* 936 * We scan the supplied table of PVRs looking for two things 937 * 1. Is our real CPU PVR in the list? 938 * 2. What's the "best" listed logical PVR 939 */ 940 for (i = 0; i < 512; ++i) { 941 uint32_t pvr, pvr_mask; 942 943 pvr_mask = ldl_be_phys(&address_space_memory, list); 944 pvr = ldl_be_phys(&address_space_memory, list + 4); 945 list += 8; 946 947 if (~pvr_mask & pvr) { 948 break; /* Terminator record */ 949 } 950 951 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 952 explicit_match = true; 953 } else { 954 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 955 best_compat = pvr; 956 } 957 } 958 } 959 960 if ((best_compat == 0) && (!explicit_match || max_compat)) { 961 /* We couldn't find a suitable compatibility mode, and either 962 * the guest doesn't support "raw" mode for this CPU, or raw 963 * mode is disabled because a maximum compat mode is set */ 964 return H_HARDWARE; 965 } 966 967 /* Parsing finished */ 968 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 969 970 /* Update CPUs */ 971 if (cpu->compat_pvr != best_compat) { 972 Error *local_err = NULL; 973 974 ppc_set_compat_all(best_compat, &local_err); 975 if (local_err) { 976 error_report_err(local_err); 977 return H_HARDWARE; 978 } 979 } 980 981 /* For the future use: here @ov_table points to the first option vector */ 982 ov_table = list; 983 984 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 985 986 /* NOTE: there are actually a number of ov5 bits where input from the 987 * guest is always zero, and the platform/QEMU enables them independently 988 * of guest input. To model these properly we'd want some sort of mask, 989 * but since they only currently apply to memory migration as defined 990 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 991 * to worry about this for now. 992 */ 993 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 994 /* full range of negotiated ov5 capabilities */ 995 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 996 spapr_ovec_cleanup(ov5_guest); 997 /* capabilities that have been added since CAS-generated guest reset. 998 * if capabilities have since been removed, generate another reset 999 */ 1000 ov5_updates = spapr_ovec_new(); 1001 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1002 ov5_cas_old, spapr->ov5_cas); 1003 1004 if (!spapr->cas_reboot) { 1005 spapr->cas_reboot = 1006 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1007 ov5_updates) != 0); 1008 } 1009 spapr_ovec_cleanup(ov5_updates); 1010 1011 if (spapr->cas_reboot) { 1012 qemu_system_reset_request(); 1013 } 1014 1015 return H_SUCCESS; 1016 } 1017 1018 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1019 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1020 1021 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1022 { 1023 spapr_hcall_fn *slot; 1024 1025 if (opcode <= MAX_HCALL_OPCODE) { 1026 assert((opcode & 0x3) == 0); 1027 1028 slot = &papr_hypercall_table[opcode / 4]; 1029 } else { 1030 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1031 1032 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1033 } 1034 1035 assert(!(*slot)); 1036 *slot = fn; 1037 } 1038 1039 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1040 target_ulong *args) 1041 { 1042 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1043 1044 if ((opcode <= MAX_HCALL_OPCODE) 1045 && ((opcode & 0x3) == 0)) { 1046 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1047 1048 if (fn) { 1049 return fn(cpu, spapr, opcode, args); 1050 } 1051 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1052 (opcode <= KVMPPC_HCALL_MAX)) { 1053 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1054 1055 if (fn) { 1056 return fn(cpu, spapr, opcode, args); 1057 } 1058 } 1059 1060 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1061 opcode); 1062 return H_FUNCTION; 1063 } 1064 1065 static void hypercall_register_types(void) 1066 { 1067 /* hcall-pft */ 1068 spapr_register_hypercall(H_ENTER, h_enter); 1069 spapr_register_hypercall(H_REMOVE, h_remove); 1070 spapr_register_hypercall(H_PROTECT, h_protect); 1071 spapr_register_hypercall(H_READ, h_read); 1072 1073 /* hcall-bulk */ 1074 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1075 1076 /* hcall-splpar */ 1077 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1078 spapr_register_hypercall(H_CEDE, h_cede); 1079 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1080 1081 /* processor register resource access h-calls */ 1082 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1083 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1084 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1085 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1086 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1087 1088 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1089 * here between the "CI" and the "CACHE" variants, they will use whatever 1090 * mapping attributes qemu is using. When using KVM, the kernel will 1091 * enforce the attributes more strongly 1092 */ 1093 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1094 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1095 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1096 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1097 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1098 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1099 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1100 1101 /* qemu/KVM-PPC specific hcalls */ 1102 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1103 1104 /* ibm,client-architecture-support support */ 1105 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1106 } 1107 1108 type_init(hypercall_register_types) 1109