1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "qapi/error.h" 4 #include "system/hw_accel.h" 5 #include "system/runstate.h" 6 #include "system/tcg.h" 7 #include "qemu/log.h" 8 #include "qemu/main-loop.h" 9 #include "qemu/module.h" 10 #include "qemu/error-report.h" 11 #include "exec/tb-flush.h" 12 #include "helper_regs.h" 13 #include "hw/ppc/ppc.h" 14 #include "hw/ppc/spapr.h" 15 #include "hw/ppc/spapr_cpu_core.h" 16 #include "hw/ppc/spapr_nested.h" 17 #include "mmu-hash64.h" 18 #include "cpu-models.h" 19 #include "trace.h" 20 #include "kvm_ppc.h" 21 #include "hw/ppc/fdt.h" 22 #include "hw/ppc/spapr_ovec.h" 23 #include "hw/ppc/spapr_numa.h" 24 #include "mmu-book3s-v3.h" 25 #include "hw/mem/memory-device.h" 26 27 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 28 { 29 MachineState *machine = MACHINE(spapr); 30 DeviceMemoryState *dms = machine->device_memory; 31 32 if (addr < machine->ram_size) { 33 return true; 34 } 35 if (dms && (addr >= dms->base) 36 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 37 return true; 38 } 39 40 return false; 41 } 42 43 /* Convert a return code from the KVM ioctl()s implementing resize HPT 44 * into a PAPR hypercall return code */ 45 static target_ulong resize_hpt_convert_rc(int ret) 46 { 47 if (ret >= 100000) { 48 return H_LONG_BUSY_ORDER_100_SEC; 49 } else if (ret >= 10000) { 50 return H_LONG_BUSY_ORDER_10_SEC; 51 } else if (ret >= 1000) { 52 return H_LONG_BUSY_ORDER_1_SEC; 53 } else if (ret >= 100) { 54 return H_LONG_BUSY_ORDER_100_MSEC; 55 } else if (ret >= 10) { 56 return H_LONG_BUSY_ORDER_10_MSEC; 57 } else if (ret > 0) { 58 return H_LONG_BUSY_ORDER_1_MSEC; 59 } 60 61 switch (ret) { 62 case 0: 63 return H_SUCCESS; 64 case -EPERM: 65 return H_AUTHORITY; 66 case -EINVAL: 67 return H_PARAMETER; 68 case -ENXIO: 69 return H_CLOSED; 70 case -ENOSPC: 71 return H_PTEG_FULL; 72 case -EBUSY: 73 return H_BUSY; 74 case -ENOMEM: 75 return H_NO_MEM; 76 default: 77 return H_HARDWARE; 78 } 79 } 80 81 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 82 SpaprMachineState *spapr, 83 target_ulong opcode, 84 target_ulong *args) 85 { 86 target_ulong flags = args[0]; 87 int shift = args[1]; 88 uint64_t current_ram_size; 89 int rc; 90 91 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 92 return H_AUTHORITY; 93 } 94 95 if (!spapr->htab_shift) { 96 /* Radix guest, no HPT */ 97 return H_NOT_AVAILABLE; 98 } 99 100 trace_spapr_h_resize_hpt_prepare(flags, shift); 101 102 if (flags != 0) { 103 return H_PARAMETER; 104 } 105 106 if (shift && ((shift < 18) || (shift > 46))) { 107 return H_PARAMETER; 108 } 109 110 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 111 112 /* We only allow the guest to allocate an HPT one order above what 113 * we'd normally give them (to stop a small guest claiming a huge 114 * chunk of resources in the HPT */ 115 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 116 return H_RESOURCE; 117 } 118 119 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 120 if (rc != -ENOSYS) { 121 return resize_hpt_convert_rc(rc); 122 } 123 124 if (kvm_enabled()) { 125 return H_HARDWARE; 126 } else if (tcg_enabled()) { 127 return vhyp_mmu_resize_hpt_prepare(cpu, spapr, shift); 128 } else { 129 g_assert_not_reached(); 130 } 131 } 132 133 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 134 { 135 int ret; 136 137 cpu_synchronize_state(cs); 138 139 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 140 if (ret < 0) { 141 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 142 exit(1); 143 } 144 } 145 146 void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 147 { 148 CPUState *cs; 149 150 /* 151 * This is a hack for the benefit of KVM PR - it abuses the SDR1 152 * slot in kvm_sregs to communicate the userspace address of the 153 * HPT 154 */ 155 if (!kvm_enabled() || !spapr->htab) { 156 return; 157 } 158 159 CPU_FOREACH(cs) { 160 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 161 } 162 } 163 164 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 165 SpaprMachineState *spapr, 166 target_ulong opcode, 167 target_ulong *args) 168 { 169 target_ulong flags = args[0]; 170 target_ulong shift = args[1]; 171 int rc; 172 173 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 174 return H_AUTHORITY; 175 } 176 177 if (!spapr->htab_shift) { 178 /* Radix guest, no HPT */ 179 return H_NOT_AVAILABLE; 180 } 181 182 trace_spapr_h_resize_hpt_commit(flags, shift); 183 184 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 185 if (rc != -ENOSYS) { 186 rc = resize_hpt_convert_rc(rc); 187 if (rc == H_SUCCESS) { 188 /* Need to set the new htab_shift in the machine state */ 189 spapr->htab_shift = shift; 190 } 191 return rc; 192 } 193 194 if (kvm_enabled()) { 195 return H_HARDWARE; 196 } else if (tcg_enabled()) { 197 return vhyp_mmu_resize_hpt_commit(cpu, spapr, flags, shift); 198 } else { 199 g_assert_not_reached(); 200 } 201 } 202 203 204 205 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 206 target_ulong opcode, target_ulong *args) 207 { 208 cpu_synchronize_state(CPU(cpu)); 209 cpu->env.spr[SPR_SPRG0] = args[0]; 210 211 return H_SUCCESS; 212 } 213 214 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 215 target_ulong opcode, target_ulong *args) 216 { 217 if (!ppc_has_spr(cpu, SPR_DABR)) { 218 return H_HARDWARE; /* DABR register not available */ 219 } 220 cpu_synchronize_state(CPU(cpu)); 221 222 if (ppc_has_spr(cpu, SPR_DABRX)) { 223 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 224 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 225 return H_RESERVED_DABR; 226 } 227 228 cpu->env.spr[SPR_DABR] = args[0]; 229 return H_SUCCESS; 230 } 231 232 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 233 target_ulong opcode, target_ulong *args) 234 { 235 target_ulong dabrx = args[1]; 236 237 if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 238 return H_HARDWARE; 239 } 240 241 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 242 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 243 return H_PARAMETER; 244 } 245 246 cpu_synchronize_state(CPU(cpu)); 247 cpu->env.spr[SPR_DABRX] = dabrx; 248 cpu->env.spr[SPR_DABR] = args[0]; 249 250 return H_SUCCESS; 251 } 252 253 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 254 target_ulong opcode, target_ulong *args) 255 { 256 target_ulong flags = args[0]; 257 hwaddr dst = args[1]; 258 hwaddr src = args[2]; 259 hwaddr len = TARGET_PAGE_SIZE; 260 uint8_t *pdst, *psrc; 261 target_long ret = H_SUCCESS; 262 263 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 264 | H_COPY_PAGE | H_ZERO_PAGE)) { 265 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 266 flags); 267 return H_PARAMETER; 268 } 269 270 /* Map-in destination */ 271 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 272 return H_PARAMETER; 273 } 274 pdst = cpu_physical_memory_map(dst, &len, true); 275 if (!pdst || len != TARGET_PAGE_SIZE) { 276 return H_PARAMETER; 277 } 278 279 if (flags & H_COPY_PAGE) { 280 /* Map-in source, copy to destination, and unmap source again */ 281 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 282 ret = H_PARAMETER; 283 goto unmap_out; 284 } 285 psrc = cpu_physical_memory_map(src, &len, false); 286 if (!psrc || len != TARGET_PAGE_SIZE) { 287 ret = H_PARAMETER; 288 goto unmap_out; 289 } 290 memcpy(pdst, psrc, len); 291 cpu_physical_memory_unmap(psrc, len, 0, len); 292 } else if (flags & H_ZERO_PAGE) { 293 memset(pdst, 0, len); /* Just clear the destination page */ 294 } 295 296 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 297 kvmppc_dcbst_range(cpu, pdst, len); 298 } 299 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 300 if (kvm_enabled()) { 301 kvmppc_icbi_range(cpu, pdst, len); 302 } else if (tcg_enabled()) { 303 tb_flush(CPU(cpu)); 304 } else { 305 g_assert_not_reached(); 306 } 307 } 308 309 unmap_out: 310 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 311 return ret; 312 } 313 314 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 315 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 316 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 317 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 318 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 319 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 320 321 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 322 { 323 CPUState *cs = CPU(cpu); 324 CPUPPCState *env = &cpu->env; 325 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 326 uint16_t size; 327 uint8_t tmp; 328 329 if (vpa == 0) { 330 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 331 return H_HARDWARE; 332 } 333 334 if (vpa % env->dcache_line_size) { 335 return H_PARAMETER; 336 } 337 /* FIXME: bounds check the address */ 338 339 size = lduw_be_phys(cs->as, vpa + 0x4); 340 341 if (size < VPA_MIN_SIZE) { 342 return H_PARAMETER; 343 } 344 345 /* VPA is not allowed to cross a page boundary */ 346 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 347 return H_PARAMETER; 348 } 349 350 spapr_cpu->vpa_addr = vpa; 351 352 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 353 tmp |= VPA_SHARED_PROC_VAL; 354 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 355 356 return H_SUCCESS; 357 } 358 359 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 360 { 361 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 362 363 if (spapr_cpu->slb_shadow_addr) { 364 return H_RESOURCE; 365 } 366 367 if (spapr_cpu->dtl_addr) { 368 return H_RESOURCE; 369 } 370 371 spapr_cpu->vpa_addr = 0; 372 return H_SUCCESS; 373 } 374 375 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 376 { 377 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 378 uint32_t size; 379 380 if (addr == 0) { 381 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 382 return H_HARDWARE; 383 } 384 385 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 386 if (size < 0x8) { 387 return H_PARAMETER; 388 } 389 390 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 391 return H_PARAMETER; 392 } 393 394 if (!spapr_cpu->vpa_addr) { 395 return H_RESOURCE; 396 } 397 398 spapr_cpu->slb_shadow_addr = addr; 399 spapr_cpu->slb_shadow_size = size; 400 401 return H_SUCCESS; 402 } 403 404 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 405 { 406 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 407 408 spapr_cpu->slb_shadow_addr = 0; 409 spapr_cpu->slb_shadow_size = 0; 410 return H_SUCCESS; 411 } 412 413 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 414 { 415 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 416 uint32_t size; 417 418 if (addr == 0) { 419 hcall_dprintf("Can't cope with DTL at logical 0\n"); 420 return H_HARDWARE; 421 } 422 423 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 424 425 if (size < 48) { 426 return H_PARAMETER; 427 } 428 429 if (!spapr_cpu->vpa_addr) { 430 return H_RESOURCE; 431 } 432 433 spapr_cpu->dtl_addr = addr; 434 spapr_cpu->dtl_size = size; 435 436 return H_SUCCESS; 437 } 438 439 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 440 { 441 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 442 443 spapr_cpu->dtl_addr = 0; 444 spapr_cpu->dtl_size = 0; 445 446 return H_SUCCESS; 447 } 448 449 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 450 target_ulong opcode, target_ulong *args) 451 { 452 target_ulong flags = args[0]; 453 target_ulong procno = args[1]; 454 target_ulong vpa = args[2]; 455 target_ulong ret = H_PARAMETER; 456 PowerPCCPU *tcpu; 457 458 tcpu = spapr_find_cpu(procno); 459 if (!tcpu) { 460 return H_PARAMETER; 461 } 462 463 switch (flags) { 464 case FLAGS_REGISTER_VPA: 465 ret = register_vpa(tcpu, vpa); 466 break; 467 468 case FLAGS_DEREGISTER_VPA: 469 ret = deregister_vpa(tcpu, vpa); 470 break; 471 472 case FLAGS_REGISTER_SLBSHADOW: 473 ret = register_slb_shadow(tcpu, vpa); 474 break; 475 476 case FLAGS_DEREGISTER_SLBSHADOW: 477 ret = deregister_slb_shadow(tcpu, vpa); 478 break; 479 480 case FLAGS_REGISTER_DTL: 481 ret = register_dtl(tcpu, vpa); 482 break; 483 484 case FLAGS_DEREGISTER_DTL: 485 ret = deregister_dtl(tcpu, vpa); 486 break; 487 } 488 489 return ret; 490 } 491 492 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 493 target_ulong opcode, target_ulong *args) 494 { 495 CPUPPCState *env = &cpu->env; 496 CPUState *cs = CPU(cpu); 497 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 498 499 env->msr |= (1ULL << MSR_EE); 500 hreg_compute_hflags(env); 501 ppc_maybe_interrupt(env); 502 503 if (spapr_cpu->prod) { 504 spapr_cpu->prod = false; 505 return H_SUCCESS; 506 } 507 508 if (!cpu_has_work(cs)) { 509 cs->halted = 1; 510 cs->exception_index = EXCP_HLT; 511 cs->exit_request = 1; 512 ppc_maybe_interrupt(env); 513 } 514 515 return H_SUCCESS; 516 } 517 518 /* 519 * Confer to self, aka join. Cede could use the same pattern as well, if 520 * EXCP_HLT can be changed to ECXP_HALTED. 521 */ 522 static target_ulong h_confer_self(PowerPCCPU *cpu) 523 { 524 CPUState *cs = CPU(cpu); 525 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 526 527 if (spapr_cpu->prod) { 528 spapr_cpu->prod = false; 529 return H_SUCCESS; 530 } 531 cs->halted = 1; 532 cs->exception_index = EXCP_HALTED; 533 cs->exit_request = 1; 534 ppc_maybe_interrupt(&cpu->env); 535 536 return H_SUCCESS; 537 } 538 539 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 540 target_ulong opcode, target_ulong *args) 541 { 542 CPUPPCState *env = &cpu->env; 543 CPUState *cs; 544 bool last_unjoined = true; 545 546 if (env->msr & (1ULL << MSR_EE)) { 547 return H_BAD_MODE; 548 } 549 550 /* 551 * Must not join the last CPU running. Interestingly, no such restriction 552 * for H_CONFER-to-self, but that is probably not intended to be used 553 * when H_JOIN is available. 554 */ 555 CPU_FOREACH(cs) { 556 PowerPCCPU *c = POWERPC_CPU(cs); 557 CPUPPCState *e = &c->env; 558 if (c == cpu) { 559 continue; 560 } 561 562 /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 563 if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 564 last_unjoined = false; 565 break; 566 } 567 } 568 if (last_unjoined) { 569 return H_CONTINUE; 570 } 571 572 return h_confer_self(cpu); 573 } 574 575 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 576 target_ulong opcode, target_ulong *args) 577 { 578 target_long target = args[0]; 579 uint32_t dispatch = args[1]; 580 CPUState *cs = CPU(cpu); 581 SpaprCpuState *spapr_cpu; 582 583 /* 584 * -1 means confer to all other CPUs without dispatch counter check, 585 * otherwise it's a targeted confer. 586 */ 587 if (target != -1) { 588 PowerPCCPU *target_cpu = spapr_find_cpu(target); 589 uint32_t target_dispatch; 590 591 if (!target_cpu) { 592 return H_PARAMETER; 593 } 594 595 /* 596 * target == self is a special case, we wait until prodded, without 597 * dispatch counter check. 598 */ 599 if (cpu == target_cpu) { 600 return h_confer_self(cpu); 601 } 602 603 spapr_cpu = spapr_cpu_state(target_cpu); 604 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 605 return H_SUCCESS; 606 } 607 608 target_dispatch = ldl_be_phys(cs->as, 609 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 610 if (target_dispatch != dispatch) { 611 return H_SUCCESS; 612 } 613 614 /* 615 * The targeted confer does not do anything special beyond yielding 616 * the current vCPU, but even this should be better than nothing. 617 * At least for single-threaded tcg, it gives the target a chance to 618 * run before we run again. Multi-threaded tcg does not really do 619 * anything with EXCP_YIELD yet. 620 */ 621 } 622 623 cs->exception_index = EXCP_YIELD; 624 cs->exit_request = 1; 625 cpu_loop_exit(cs); 626 627 return H_SUCCESS; 628 } 629 630 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 631 target_ulong opcode, target_ulong *args) 632 { 633 target_long target = args[0]; 634 PowerPCCPU *tcpu; 635 CPUState *cs; 636 SpaprCpuState *spapr_cpu; 637 638 tcpu = spapr_find_cpu(target); 639 cs = CPU(tcpu); 640 if (!cs) { 641 return H_PARAMETER; 642 } 643 644 spapr_cpu = spapr_cpu_state(tcpu); 645 spapr_cpu->prod = true; 646 cs->halted = 0; 647 ppc_maybe_interrupt(&cpu->env); 648 qemu_cpu_kick(cs); 649 650 return H_SUCCESS; 651 } 652 653 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 654 target_ulong opcode, target_ulong *args) 655 { 656 target_ulong rtas_r3 = args[0]; 657 uint32_t token = rtas_ld(rtas_r3, 0); 658 uint32_t nargs = rtas_ld(rtas_r3, 1); 659 uint32_t nret = rtas_ld(rtas_r3, 2); 660 661 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 662 nret, rtas_r3 + 12 + 4*nargs); 663 } 664 665 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 666 target_ulong opcode, target_ulong *args) 667 { 668 CPUState *cs = CPU(cpu); 669 target_ulong size = args[0]; 670 target_ulong addr = args[1]; 671 672 switch (size) { 673 case 1: 674 args[0] = ldub_phys(cs->as, addr); 675 return H_SUCCESS; 676 case 2: 677 args[0] = lduw_phys(cs->as, addr); 678 return H_SUCCESS; 679 case 4: 680 args[0] = ldl_phys(cs->as, addr); 681 return H_SUCCESS; 682 case 8: 683 args[0] = ldq_phys(cs->as, addr); 684 return H_SUCCESS; 685 } 686 return H_PARAMETER; 687 } 688 689 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 690 target_ulong opcode, target_ulong *args) 691 { 692 CPUState *cs = CPU(cpu); 693 694 target_ulong size = args[0]; 695 target_ulong addr = args[1]; 696 target_ulong val = args[2]; 697 698 switch (size) { 699 case 1: 700 stb_phys(cs->as, addr, val); 701 return H_SUCCESS; 702 case 2: 703 stw_phys(cs->as, addr, val); 704 return H_SUCCESS; 705 case 4: 706 stl_phys(cs->as, addr, val); 707 return H_SUCCESS; 708 case 8: 709 stq_phys(cs->as, addr, val); 710 return H_SUCCESS; 711 } 712 return H_PARAMETER; 713 } 714 715 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 716 target_ulong opcode, target_ulong *args) 717 { 718 CPUState *cs = CPU(cpu); 719 720 target_ulong dst = args[0]; /* Destination address */ 721 target_ulong src = args[1]; /* Source address */ 722 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 723 target_ulong count = args[3]; /* Element count */ 724 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 725 uint64_t tmp; 726 unsigned int mask = (1 << esize) - 1; 727 int step = 1 << esize; 728 729 if (count > 0x80000000) { 730 return H_PARAMETER; 731 } 732 733 if ((dst & mask) || (src & mask) || (op > 1)) { 734 return H_PARAMETER; 735 } 736 737 if (dst >= src && dst < (src + (count << esize))) { 738 dst = dst + ((count - 1) << esize); 739 src = src + ((count - 1) << esize); 740 step = -step; 741 } 742 743 while (count--) { 744 switch (esize) { 745 case 0: 746 tmp = ldub_phys(cs->as, src); 747 break; 748 case 1: 749 tmp = lduw_phys(cs->as, src); 750 break; 751 case 2: 752 tmp = ldl_phys(cs->as, src); 753 break; 754 case 3: 755 tmp = ldq_phys(cs->as, src); 756 break; 757 default: 758 return H_PARAMETER; 759 } 760 if (op == 1) { 761 tmp = ~tmp; 762 } 763 switch (esize) { 764 case 0: 765 stb_phys(cs->as, dst, tmp); 766 break; 767 case 1: 768 stw_phys(cs->as, dst, tmp); 769 break; 770 case 2: 771 stl_phys(cs->as, dst, tmp); 772 break; 773 case 3: 774 stq_phys(cs->as, dst, tmp); 775 break; 776 } 777 dst = dst + step; 778 src = src + step; 779 } 780 781 return H_SUCCESS; 782 } 783 784 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 785 target_ulong opcode, target_ulong *args) 786 { 787 /* Nothing to do on emulation, KVM will trap this in the kernel */ 788 return H_SUCCESS; 789 } 790 791 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 792 target_ulong opcode, target_ulong *args) 793 { 794 /* Nothing to do on emulation, KVM will trap this in the kernel */ 795 return H_SUCCESS; 796 } 797 798 static target_ulong h_set_mode_resource_set_ciabr(PowerPCCPU *cpu, 799 SpaprMachineState *spapr, 800 target_ulong mflags, 801 target_ulong value1, 802 target_ulong value2) 803 { 804 CPUPPCState *env = &cpu->env; 805 806 assert(tcg_enabled()); /* KVM will have handled this */ 807 808 if (mflags) { 809 return H_UNSUPPORTED_FLAG; 810 } 811 if (value2) { 812 return H_P4; 813 } 814 if ((value1 & PPC_BITMASK(62, 63)) == 0x3) { 815 return H_P3; 816 } 817 818 ppc_store_ciabr(env, value1); 819 820 return H_SUCCESS; 821 } 822 823 static target_ulong h_set_mode_resource_set_dawr0(PowerPCCPU *cpu, 824 SpaprMachineState *spapr, 825 target_ulong mflags, 826 target_ulong value1, 827 target_ulong value2) 828 { 829 CPUPPCState *env = &cpu->env; 830 831 assert(tcg_enabled()); /* KVM will have handled this */ 832 833 if (mflags) { 834 return H_UNSUPPORTED_FLAG; 835 } 836 if (value2 & PPC_BIT(61)) { 837 return H_P4; 838 } 839 840 ppc_store_dawr0(env, value1); 841 ppc_store_dawrx0(env, value2); 842 843 return H_SUCCESS; 844 } 845 846 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 847 SpaprMachineState *spapr, 848 target_ulong mflags, 849 target_ulong value1, 850 target_ulong value2) 851 { 852 if (value1) { 853 return H_P3; 854 } 855 if (value2) { 856 return H_P4; 857 } 858 859 switch (mflags) { 860 case H_SET_MODE_ENDIAN_BIG: 861 spapr_set_all_lpcrs(0, LPCR_ILE); 862 spapr_pci_switch_vga(spapr, true); 863 return H_SUCCESS; 864 865 case H_SET_MODE_ENDIAN_LITTLE: 866 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 867 spapr_pci_switch_vga(spapr, false); 868 return H_SUCCESS; 869 } 870 871 return H_UNSUPPORTED_FLAG; 872 } 873 874 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 875 SpaprMachineState *spapr, 876 target_ulong mflags, 877 target_ulong value1, 878 target_ulong value2) 879 { 880 if (value1) { 881 return H_P3; 882 } 883 884 if (value2) { 885 return H_P4; 886 } 887 888 /* 889 * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr. 890 * It is supported for faithful emulation of bare metal systems, but for 891 * compatibility concerns we leave it out of the pseries machine. 892 */ 893 if (mflags != 0 && mflags != 3) { 894 return H_UNSUPPORTED_FLAG; 895 } 896 897 if (mflags == 3) { 898 if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) { 899 return H_UNSUPPORTED_FLAG; 900 } 901 } 902 903 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 904 905 return H_SUCCESS; 906 } 907 908 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 909 target_ulong opcode, target_ulong *args) 910 { 911 target_ulong resource = args[1]; 912 target_ulong ret = H_P2; 913 914 switch (resource) { 915 case H_SET_MODE_RESOURCE_SET_CIABR: 916 ret = h_set_mode_resource_set_ciabr(cpu, spapr, args[0], args[2], 917 args[3]); 918 break; 919 case H_SET_MODE_RESOURCE_SET_DAWR0: 920 ret = h_set_mode_resource_set_dawr0(cpu, spapr, args[0], args[2], 921 args[3]); 922 break; 923 case H_SET_MODE_RESOURCE_LE: 924 ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 925 break; 926 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 927 ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0], 928 args[2], args[3]); 929 break; 930 } 931 932 return ret; 933 } 934 935 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 936 target_ulong opcode, target_ulong *args) 937 { 938 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 939 opcode, " (H_CLEAN_SLB)"); 940 return H_FUNCTION; 941 } 942 943 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 944 target_ulong opcode, target_ulong *args) 945 { 946 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 947 opcode, " (H_INVALIDATE_PID)"); 948 return H_FUNCTION; 949 } 950 951 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 952 uint64_t patbe_old, uint64_t patbe_new) 953 { 954 /* 955 * We have 4 Options: 956 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 957 * HASH->RADIX : Free HPT 958 * RADIX->HASH : Allocate HPT 959 * NOTHING->HASH : Allocate HPT 960 * Note: NOTHING implies the case where we said the guest could choose 961 * later and so assumed radix and now it's called H_REG_PROC_TBL 962 */ 963 964 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 965 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 966 } else if (!(patbe_old & PATE1_GR)) { 967 /* HASH->RADIX : Free HPT */ 968 spapr_free_hpt(spapr); 969 } else if (!(patbe_new & PATE1_GR)) { 970 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 971 spapr_setup_hpt(spapr); 972 } 973 return; 974 } 975 976 #define FLAGS_MASK 0x01FULL 977 #define FLAG_MODIFY 0x10 978 #define FLAG_REGISTER 0x08 979 #define FLAG_RADIX 0x04 980 #define FLAG_HASH_PROC_TBL 0x02 981 #define FLAG_GTSE 0x01 982 983 static target_ulong h_register_process_table(PowerPCCPU *cpu, 984 SpaprMachineState *spapr, 985 target_ulong opcode, 986 target_ulong *args) 987 { 988 target_ulong flags = args[0]; 989 target_ulong proc_tbl = args[1]; 990 target_ulong page_size = args[2]; 991 target_ulong table_size = args[3]; 992 target_ulong update_lpcr = 0; 993 target_ulong table_byte_size; 994 uint64_t cproc; 995 996 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 997 return H_PARAMETER; 998 } 999 if (flags & FLAG_MODIFY) { 1000 if (flags & FLAG_REGISTER) { 1001 /* Check process table alignment */ 1002 table_byte_size = 1ULL << (table_size + 12); 1003 if (proc_tbl & (table_byte_size - 1)) { 1004 qemu_log_mask(LOG_GUEST_ERROR, 1005 "%s: process table not properly aligned: proc_tbl 0x" 1006 TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", 1007 __func__, proc_tbl, table_byte_size); 1008 } 1009 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1010 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1011 return H_P2; 1012 } else if (page_size) { 1013 return H_P3; 1014 } else if (table_size > 24) { 1015 return H_P4; 1016 } 1017 cproc = PATE1_GR | proc_tbl | table_size; 1018 } else { /* Register new HPT process table */ 1019 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1020 /* TODO - Not Supported */ 1021 /* Technically caused by flag bits => H_PARAMETER */ 1022 return H_PARAMETER; 1023 } else { /* Hash with SLB */ 1024 if (proc_tbl >> 38) { 1025 return H_P2; 1026 } else if (page_size & ~0x7) { 1027 return H_P3; 1028 } else if (table_size > 24) { 1029 return H_P4; 1030 } 1031 } 1032 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1033 } 1034 1035 } else { /* Deregister current process table */ 1036 /* 1037 * Set to benign value: (current GR) | 0. This allows 1038 * deregistration in KVM to succeed even if the radix bit 1039 * in flags doesn't match the radix bit in the old PATE. 1040 */ 1041 cproc = spapr->patb_entry & PATE1_GR; 1042 } 1043 } else { /* Maintain current registration */ 1044 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1045 /* Technically caused by flag bits => H_PARAMETER */ 1046 return H_PARAMETER; /* Existing Process Table Mismatch */ 1047 } 1048 cproc = spapr->patb_entry; 1049 } 1050 1051 /* Check if we need to setup OR free the hpt */ 1052 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1053 1054 spapr->patb_entry = cproc; /* Save new process table */ 1055 1056 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1057 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1058 update_lpcr |= (LPCR_UPRT | LPCR_HR); 1059 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1060 update_lpcr |= LPCR_UPRT; 1061 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 1062 update_lpcr |= LPCR_GTSE; 1063 1064 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1065 1066 if (kvm_enabled()) { 1067 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1068 flags & FLAG_GTSE, cproc); 1069 } 1070 return H_SUCCESS; 1071 } 1072 1073 #define H_SIGNAL_SYS_RESET_ALL -1 1074 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1075 1076 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1077 SpaprMachineState *spapr, 1078 target_ulong opcode, target_ulong *args) 1079 { 1080 target_long target = args[0]; 1081 CPUState *cs; 1082 1083 if (target < 0) { 1084 /* Broadcast */ 1085 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1086 return H_PARAMETER; 1087 } 1088 1089 CPU_FOREACH(cs) { 1090 PowerPCCPU *c = POWERPC_CPU(cs); 1091 1092 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1093 if (c == cpu) { 1094 continue; 1095 } 1096 } 1097 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1098 } 1099 return H_SUCCESS; 1100 1101 } else { 1102 /* Unicast */ 1103 cs = CPU(spapr_find_cpu(target)); 1104 if (cs) { 1105 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1106 return H_SUCCESS; 1107 } 1108 return H_PARAMETER; 1109 } 1110 } 1111 1112 /* Returns either a logical PVR or zero if none was found */ 1113 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1114 target_ulong *addr, bool *raw_mode_supported) 1115 { 1116 bool explicit_match = false; /* Matched the CPU's real PVR */ 1117 uint32_t best_compat = 0; 1118 int i; 1119 1120 /* 1121 * We scan the supplied table of PVRs looking for two things 1122 * 1. Is our real CPU PVR in the list? 1123 * 2. What's the "best" listed logical PVR 1124 */ 1125 for (i = 0; i < 512; ++i) { 1126 uint32_t pvr, pvr_mask; 1127 1128 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1129 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1130 *addr += 8; 1131 1132 if (~pvr_mask & pvr) { 1133 break; /* Terminator record */ 1134 } 1135 1136 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1137 explicit_match = true; 1138 } else { 1139 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1140 best_compat = pvr; 1141 } 1142 } 1143 } 1144 1145 *raw_mode_supported = explicit_match; 1146 1147 /* Parsing finished */ 1148 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1149 1150 return best_compat; 1151 } 1152 1153 static 1154 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1155 SpaprMachineState *spapr, 1156 target_ulong vec, 1157 target_ulong fdt_bufsize) 1158 { 1159 target_ulong ov_table; /* Working address in data buffer */ 1160 uint32_t cas_pvr; 1161 SpaprOptionVector *ov1_guest, *ov5_guest; 1162 bool guest_radix; 1163 bool raw_mode_supported = false; 1164 bool guest_xive; 1165 CPUState *cs; 1166 void *fdt; 1167 uint32_t max_compat = spapr->max_compat_pvr; 1168 1169 /* CAS is supposed to be called early when only the boot vCPU is active. */ 1170 CPU_FOREACH(cs) { 1171 if (cs == CPU(cpu)) { 1172 continue; 1173 } 1174 if (!cs->halted) { 1175 warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 1176 return H_MULTI_THREADS_ACTIVE; 1177 } 1178 } 1179 1180 cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1181 if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1182 /* 1183 * We couldn't find a suitable compatibility mode, and either 1184 * the guest doesn't support "raw" mode for this CPU, or "raw" 1185 * mode is disabled because a maximum compat mode is set. 1186 */ 1187 error_report("Couldn't negotiate a suitable PVR during CAS"); 1188 return H_HARDWARE; 1189 } 1190 1191 /* Update CPUs */ 1192 if (cpu->compat_pvr != cas_pvr) { 1193 Error *local_err = NULL; 1194 1195 if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1196 /* We fail to set compat mode (likely because running with KVM PR), 1197 * but maybe we can fallback to raw mode if the guest supports it. 1198 */ 1199 if (!raw_mode_supported) { 1200 error_report_err(local_err); 1201 return H_HARDWARE; 1202 } 1203 error_free(local_err); 1204 } 1205 } 1206 1207 /* For the future use: here @ov_table points to the first option vector */ 1208 ov_table = vec; 1209 1210 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1211 if (!ov1_guest) { 1212 warn_report("guest didn't provide option vector 1"); 1213 return H_PARAMETER; 1214 } 1215 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1216 if (!ov5_guest) { 1217 spapr_ovec_cleanup(ov1_guest); 1218 warn_report("guest didn't provide option vector 5"); 1219 return H_PARAMETER; 1220 } 1221 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1222 error_report("guest requested hash and radix MMU, which is invalid."); 1223 exit(EXIT_FAILURE); 1224 } 1225 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1226 error_report("guest requested an invalid interrupt mode"); 1227 exit(EXIT_FAILURE); 1228 } 1229 1230 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1231 1232 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1233 1234 /* 1235 * HPT resizing is a bit of a special case, because when enabled 1236 * we assume an HPT guest will support it until it says it 1237 * doesn't, instead of assuming it won't support it until it says 1238 * it does. Strictly speaking that approach could break for 1239 * guests which don't make a CAS call, but those are so old we 1240 * don't care about them. Without that assumption we'd have to 1241 * make at least a temporary allocation of an HPT sized for max 1242 * memory, which could be impossibly difficult under KVM HV if 1243 * maxram is large. 1244 */ 1245 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1246 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1247 1248 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1249 error_report( 1250 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1251 exit(1); 1252 } 1253 1254 if (spapr->htab_shift < maxshift) { 1255 /* Guest doesn't know about HPT resizing, so we 1256 * pre-emptively resize for the maximum permitted RAM. At 1257 * the point this is called, nothing should have been 1258 * entered into the existing HPT */ 1259 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1260 push_sregs_to_kvm_pr(spapr); 1261 } 1262 } 1263 1264 /* NOTE: there are actually a number of ov5 bits where input from the 1265 * guest is always zero, and the platform/QEMU enables them independently 1266 * of guest input. To model these properly we'd want some sort of mask, 1267 * but since they only currently apply to memory migration as defined 1268 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1269 * to worry about this for now. 1270 */ 1271 1272 /* full range of negotiated ov5 capabilities */ 1273 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1274 spapr_ovec_cleanup(ov5_guest); 1275 1276 spapr_check_mmu_mode(guest_radix); 1277 1278 spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 1279 spapr_ovec_cleanup(ov1_guest); 1280 1281 /* 1282 * Check for NUMA affinity conditions now that we know which NUMA 1283 * affinity the guest will use. 1284 */ 1285 spapr_numa_associativity_check(spapr); 1286 1287 /* 1288 * Ensure the guest asks for an interrupt mode we support; 1289 * otherwise terminate the boot. 1290 */ 1291 if (guest_xive) { 1292 if (!spapr->irq->xive) { 1293 error_report( 1294 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1295 exit(EXIT_FAILURE); 1296 } 1297 } else { 1298 if (!spapr->irq->xics) { 1299 error_report( 1300 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1301 exit(EXIT_FAILURE); 1302 } 1303 } 1304 1305 spapr_irq_update_active_intc(spapr); 1306 1307 /* 1308 * Process all pending hot-plug/unplug requests now. An updated full 1309 * rendered FDT will be returned to the guest. 1310 */ 1311 spapr_drc_reset_all(spapr); 1312 spapr_clear_pending_hotplug_events(spapr); 1313 1314 /* 1315 * If spapr_machine_reset() did not set up a HPT but one is necessary 1316 * (because the guest isn't going to use radix) then set it up here. 1317 */ 1318 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1319 /* legacy hash or new hash: */ 1320 spapr_setup_hpt(spapr); 1321 } 1322 1323 fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 1324 g_free(spapr->fdt_blob); 1325 spapr->fdt_size = fdt_totalsize(fdt); 1326 spapr->fdt_initial_size = spapr->fdt_size; 1327 spapr->fdt_blob = fdt; 1328 1329 /* 1330 * Set the machine->fdt pointer again since we just freed 1331 * it above (by freeing spapr->fdt_blob). We set this 1332 * pointer to enable support for the 'dumpdtb' QMP/HMP 1333 * command. 1334 */ 1335 MACHINE(spapr)->fdt = fdt; 1336 1337 return H_SUCCESS; 1338 } 1339 1340 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1341 SpaprMachineState *spapr, 1342 target_ulong opcode, 1343 target_ulong *args) 1344 { 1345 target_ulong vec = ppc64_phys_to_real(args[0]); 1346 target_ulong fdt_buf = args[1]; 1347 target_ulong fdt_bufsize = args[2]; 1348 target_ulong ret; 1349 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1350 1351 if (fdt_bufsize < sizeof(hdr)) { 1352 error_report("SLOF provided insufficient CAS buffer " 1353 TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 1354 exit(EXIT_FAILURE); 1355 } 1356 1357 fdt_bufsize -= sizeof(hdr); 1358 1359 ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 1360 if (ret == H_SUCCESS) { 1361 _FDT((fdt_pack(spapr->fdt_blob))); 1362 spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 1363 spapr->fdt_initial_size = spapr->fdt_size; 1364 1365 cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 1366 cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 1367 spapr->fdt_size); 1368 trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 1369 } 1370 1371 return ret; 1372 } 1373 1374 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1375 CPUState *cs, 1376 target_ulong ovec_addr) 1377 { 1378 SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1379 1380 target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1381 ovec_addr, FDT_MAX_SIZE); 1382 1383 /* 1384 * This adds stdout and generates phandles for boottime and CAS FDTs. 1385 * It is alright to update the FDT here as do_client_architecture_support() 1386 * does not pack it. 1387 */ 1388 spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1389 1390 return ret; 1391 } 1392 1393 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1394 SpaprMachineState *spapr, 1395 target_ulong opcode, 1396 target_ulong *args) 1397 { 1398 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1399 ~H_CPU_CHAR_THR_RECONF_TRIG; 1400 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1401 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1402 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1403 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1404 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1405 SPAPR_CAP_CCF_ASSIST); 1406 1407 switch (safe_cache) { 1408 case SPAPR_CAP_WORKAROUND: 1409 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1410 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1411 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1412 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1413 break; 1414 case SPAPR_CAP_FIXED: 1415 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 1416 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1417 break; 1418 default: /* broken */ 1419 assert(safe_cache == SPAPR_CAP_BROKEN); 1420 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1421 break; 1422 } 1423 1424 switch (safe_bounds_check) { 1425 case SPAPR_CAP_WORKAROUND: 1426 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1427 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1428 break; 1429 case SPAPR_CAP_FIXED: 1430 break; 1431 default: /* broken */ 1432 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1433 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1434 break; 1435 } 1436 1437 switch (safe_indirect_branch) { 1438 case SPAPR_CAP_FIXED_NA: 1439 break; 1440 case SPAPR_CAP_FIXED_CCD: 1441 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1442 break; 1443 case SPAPR_CAP_FIXED_IBS: 1444 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1445 break; 1446 case SPAPR_CAP_WORKAROUND: 1447 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1448 if (count_cache_flush_assist) { 1449 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1450 } 1451 break; 1452 default: /* broken */ 1453 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1454 break; 1455 } 1456 1457 args[0] = characteristics; 1458 args[1] = behaviour; 1459 return H_SUCCESS; 1460 } 1461 1462 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1463 target_ulong opcode, target_ulong *args) 1464 { 1465 target_ulong dt = ppc64_phys_to_real(args[0]); 1466 struct fdt_header hdr = { 0 }; 1467 unsigned cb; 1468 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1469 void *fdt; 1470 1471 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1472 cb = fdt32_to_cpu(hdr.totalsize); 1473 1474 if (!smc->update_dt_enabled) { 1475 return H_SUCCESS; 1476 } 1477 1478 /* Check that the fdt did not grow out of proportion */ 1479 if (cb > spapr->fdt_initial_size * 2) { 1480 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1481 fdt32_to_cpu(hdr.magic)); 1482 return H_PARAMETER; 1483 } 1484 1485 fdt = g_malloc0(cb); 1486 cpu_physical_memory_read(dt, fdt, cb); 1487 1488 /* Check the fdt consistency */ 1489 if (fdt_check_full(fdt, cb)) { 1490 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1491 fdt32_to_cpu(hdr.magic)); 1492 return H_PARAMETER; 1493 } 1494 1495 g_free(spapr->fdt_blob); 1496 spapr->fdt_size = cb; 1497 spapr->fdt_blob = fdt; 1498 trace_spapr_update_dt(cb); 1499 1500 return H_SUCCESS; 1501 } 1502 1503 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1504 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1505 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 1506 1507 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1508 { 1509 spapr_hcall_fn *slot; 1510 1511 if (opcode <= MAX_HCALL_OPCODE) { 1512 assert((opcode & 0x3) == 0); 1513 1514 slot = &papr_hypercall_table[opcode / 4]; 1515 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1516 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1517 assert((opcode & 0x3) == 0); 1518 1519 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1520 } else { 1521 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1522 1523 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1524 } 1525 1526 assert(!(*slot)); 1527 *slot = fn; 1528 } 1529 1530 void spapr_unregister_hypercall(target_ulong opcode) 1531 { 1532 spapr_hcall_fn *slot; 1533 1534 if (opcode <= MAX_HCALL_OPCODE) { 1535 assert((opcode & 0x3) == 0); 1536 1537 slot = &papr_hypercall_table[opcode / 4]; 1538 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1539 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1540 assert((opcode & 0x3) == 0); 1541 1542 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1543 } else { 1544 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1545 1546 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1547 } 1548 1549 *slot = NULL; 1550 } 1551 1552 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1553 target_ulong *args) 1554 { 1555 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1556 1557 if ((opcode <= MAX_HCALL_OPCODE) 1558 && ((opcode & 0x3) == 0)) { 1559 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1560 1561 if (fn) { 1562 return fn(cpu, spapr, opcode, args); 1563 } 1564 } else if ((opcode >= SVM_HCALL_BASE) && 1565 (opcode <= SVM_HCALL_MAX)) { 1566 spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1567 1568 if (fn) { 1569 return fn(cpu, spapr, opcode, args); 1570 } 1571 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1572 (opcode <= KVMPPC_HCALL_MAX)) { 1573 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1574 1575 if (fn) { 1576 return fn(cpu, spapr, opcode, args); 1577 } 1578 } 1579 1580 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1581 opcode); 1582 return H_FUNCTION; 1583 } 1584 1585 #ifdef CONFIG_TCG 1586 static void hypercall_register_softmmu(void) 1587 { 1588 /* DO NOTHING */ 1589 } 1590 #else 1591 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1592 target_ulong opcode, target_ulong *args) 1593 { 1594 g_assert_not_reached(); 1595 } 1596 1597 static void hypercall_register_softmmu(void) 1598 { 1599 /* hcall-pft */ 1600 spapr_register_hypercall(H_ENTER, h_softmmu); 1601 spapr_register_hypercall(H_REMOVE, h_softmmu); 1602 spapr_register_hypercall(H_PROTECT, h_softmmu); 1603 spapr_register_hypercall(H_READ, h_softmmu); 1604 1605 /* hcall-bulk */ 1606 spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1607 } 1608 #endif 1609 1610 static void hypercall_register_types(void) 1611 { 1612 hypercall_register_softmmu(); 1613 1614 /* hcall-hpt-resize */ 1615 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1616 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1617 1618 /* hcall-splpar */ 1619 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1620 spapr_register_hypercall(H_CEDE, h_cede); 1621 spapr_register_hypercall(H_CONFER, h_confer); 1622 spapr_register_hypercall(H_PROD, h_prod); 1623 1624 /* hcall-join */ 1625 spapr_register_hypercall(H_JOIN, h_join); 1626 1627 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1628 1629 /* processor register resource access h-calls */ 1630 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1631 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1632 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1633 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1634 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1635 1636 /* In Memory Table MMU h-calls */ 1637 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1638 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1639 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1640 1641 /* hcall-get-cpu-characteristics */ 1642 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1643 h_get_cpu_characteristics); 1644 1645 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differentiate 1646 * here between the "CI" and the "CACHE" variants, they will use whatever 1647 * mapping attributes qemu is using. When using KVM, the kernel will 1648 * enforce the attributes more strongly 1649 */ 1650 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1651 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1652 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1653 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1654 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1655 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1656 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1657 1658 /* qemu/KVM-PPC specific hcalls */ 1659 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1660 1661 /* ibm,client-architecture-support support */ 1662 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1663 1664 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1665 } 1666 1667 type_init(hypercall_register_types) 1668