1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/sysemu.h" 5 #include "qemu/log.h" 6 #include "cpu.h" 7 #include "exec/exec-all.h" 8 #include "helper_regs.h" 9 #include "hw/ppc/spapr.h" 10 #include "mmu-hash64.h" 11 #include "cpu-models.h" 12 #include "trace.h" 13 #include "kvm_ppc.h" 14 #include "hw/ppc/spapr_ovec.h" 15 #include "qemu/error-report.h" 16 #include "mmu-book3s-v3.h" 17 18 struct SPRSyncState { 19 int spr; 20 target_ulong value; 21 target_ulong mask; 22 }; 23 24 static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 25 { 26 struct SPRSyncState *s = arg.host_ptr; 27 PowerPCCPU *cpu = POWERPC_CPU(cs); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_synchronize_state(cs); 31 env->spr[s->spr] &= ~s->mask; 32 env->spr[s->spr] |= s->value; 33 } 34 35 static void set_spr(CPUState *cs, int spr, target_ulong value, 36 target_ulong mask) 37 { 38 struct SPRSyncState s = { 39 .spr = spr, 40 .value = value, 41 .mask = mask 42 }; 43 run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 44 } 45 46 static bool has_spr(PowerPCCPU *cpu, int spr) 47 { 48 /* We can test whether the SPR is defined by checking for a valid name */ 49 return cpu->env.spr_cb[spr].name != NULL; 50 } 51 52 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 53 { 54 /* 55 * hash value/pteg group index is normalized by HPT mask 56 */ 57 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 58 return false; 59 } 60 return true; 61 } 62 63 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 64 { 65 MachineState *machine = MACHINE(spapr); 66 MemoryHotplugState *hpms = &spapr->hotplug_memory; 67 68 if (addr < machine->ram_size) { 69 return true; 70 } 71 if ((addr >= hpms->base) 72 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 73 return true; 74 } 75 76 return false; 77 } 78 79 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 80 target_ulong opcode, target_ulong *args) 81 { 82 target_ulong flags = args[0]; 83 target_ulong ptex = args[1]; 84 target_ulong pteh = args[2]; 85 target_ulong ptel = args[3]; 86 unsigned apshift; 87 target_ulong raddr; 88 target_ulong slot; 89 const ppc_hash_pte64_t *hptes; 90 91 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 92 if (!apshift) { 93 /* Bad page size encoding */ 94 return H_PARAMETER; 95 } 96 97 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 98 99 if (is_ram_address(spapr, raddr)) { 100 /* Regular RAM - should have WIMG=0010 */ 101 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 102 return H_PARAMETER; 103 } 104 } else { 105 target_ulong wimg_flags; 106 /* Looks like an IO address */ 107 /* FIXME: What WIMG combinations could be sensible for IO? 108 * For now we allow WIMG=010x, but are there others? */ 109 /* FIXME: Should we check against registered IO addresses? */ 110 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 111 112 if (wimg_flags != HPTE64_R_I && 113 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 114 return H_PARAMETER; 115 } 116 } 117 118 pteh &= ~0x60ULL; 119 120 if (!valid_ptex(cpu, ptex)) { 121 return H_PARAMETER; 122 } 123 124 slot = ptex & 7ULL; 125 ptex = ptex & ~7ULL; 126 127 if (likely((flags & H_EXACT) == 0)) { 128 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 129 for (slot = 0; slot < 8; slot++) { 130 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 131 break; 132 } 133 } 134 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 135 if (slot == 8) { 136 return H_PTEG_FULL; 137 } 138 } else { 139 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 140 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 141 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 142 return H_PTEG_FULL; 143 } 144 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 145 } 146 147 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 148 149 args[0] = ptex + slot; 150 return H_SUCCESS; 151 } 152 153 typedef enum { 154 REMOVE_SUCCESS = 0, 155 REMOVE_NOT_FOUND = 1, 156 REMOVE_PARM = 2, 157 REMOVE_HW = 3, 158 } RemoveResult; 159 160 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 161 target_ulong avpn, 162 target_ulong flags, 163 target_ulong *vp, target_ulong *rp) 164 { 165 const ppc_hash_pte64_t *hptes; 166 target_ulong v, r; 167 168 if (!valid_ptex(cpu, ptex)) { 169 return REMOVE_PARM; 170 } 171 172 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 173 v = ppc_hash64_hpte0(cpu, hptes, 0); 174 r = ppc_hash64_hpte1(cpu, hptes, 0); 175 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 176 177 if ((v & HPTE64_V_VALID) == 0 || 178 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 179 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 180 return REMOVE_NOT_FOUND; 181 } 182 *vp = v; 183 *rp = r; 184 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 185 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 186 return REMOVE_SUCCESS; 187 } 188 189 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 190 target_ulong opcode, target_ulong *args) 191 { 192 CPUPPCState *env = &cpu->env; 193 target_ulong flags = args[0]; 194 target_ulong ptex = args[1]; 195 target_ulong avpn = args[2]; 196 RemoveResult ret; 197 198 ret = remove_hpte(cpu, ptex, avpn, flags, 199 &args[0], &args[1]); 200 201 switch (ret) { 202 case REMOVE_SUCCESS: 203 check_tlb_flush(env, true); 204 return H_SUCCESS; 205 206 case REMOVE_NOT_FOUND: 207 return H_NOT_FOUND; 208 209 case REMOVE_PARM: 210 return H_PARAMETER; 211 212 case REMOVE_HW: 213 return H_HARDWARE; 214 } 215 216 g_assert_not_reached(); 217 } 218 219 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 220 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 221 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 222 #define H_BULK_REMOVE_END 0xc000000000000000ULL 223 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 224 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 225 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 226 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 227 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 228 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 229 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 230 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 231 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 232 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 233 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 234 235 #define H_BULK_REMOVE_MAX_BATCH 4 236 237 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 238 target_ulong opcode, target_ulong *args) 239 { 240 CPUPPCState *env = &cpu->env; 241 int i; 242 target_ulong rc = H_SUCCESS; 243 244 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 245 target_ulong *tsh = &args[i*2]; 246 target_ulong tsl = args[i*2 + 1]; 247 target_ulong v, r, ret; 248 249 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 250 break; 251 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 252 return H_PARAMETER; 253 } 254 255 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 256 *tsh |= H_BULK_REMOVE_RESPONSE; 257 258 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 259 *tsh |= H_BULK_REMOVE_PARM; 260 return H_PARAMETER; 261 } 262 263 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 264 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 265 &v, &r); 266 267 *tsh |= ret << 60; 268 269 switch (ret) { 270 case REMOVE_SUCCESS: 271 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 272 break; 273 274 case REMOVE_PARM: 275 rc = H_PARAMETER; 276 goto exit; 277 278 case REMOVE_HW: 279 rc = H_HARDWARE; 280 goto exit; 281 } 282 } 283 exit: 284 check_tlb_flush(env, true); 285 286 return rc; 287 } 288 289 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 290 target_ulong opcode, target_ulong *args) 291 { 292 CPUPPCState *env = &cpu->env; 293 target_ulong flags = args[0]; 294 target_ulong ptex = args[1]; 295 target_ulong avpn = args[2]; 296 const ppc_hash_pte64_t *hptes; 297 target_ulong v, r; 298 299 if (!valid_ptex(cpu, ptex)) { 300 return H_PARAMETER; 301 } 302 303 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 304 v = ppc_hash64_hpte0(cpu, hptes, 0); 305 r = ppc_hash64_hpte1(cpu, hptes, 0); 306 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 307 308 if ((v & HPTE64_V_VALID) == 0 || 309 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 310 return H_NOT_FOUND; 311 } 312 313 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 314 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 315 r |= (flags << 55) & HPTE64_R_PP0; 316 r |= (flags << 48) & HPTE64_R_KEY_HI; 317 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 318 ppc_hash64_store_hpte(cpu, ptex, 319 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 320 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 321 /* Flush the tlb */ 322 check_tlb_flush(env, true); 323 /* Don't need a memory barrier, due to qemu's global lock */ 324 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 325 return H_SUCCESS; 326 } 327 328 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 329 target_ulong opcode, target_ulong *args) 330 { 331 target_ulong flags = args[0]; 332 target_ulong ptex = args[1]; 333 uint8_t *hpte; 334 int i, ridx, n_entries = 1; 335 336 if (!valid_ptex(cpu, ptex)) { 337 return H_PARAMETER; 338 } 339 340 if (flags & H_READ_4) { 341 /* Clear the two low order bits */ 342 ptex &= ~(3ULL); 343 n_entries = 4; 344 } 345 346 hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 347 348 for (i = 0, ridx = 0; i < n_entries; i++) { 349 args[ridx++] = ldq_p(hpte); 350 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 351 hpte += HASH_PTE_SIZE_64; 352 } 353 354 return H_SUCCESS; 355 } 356 357 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 358 sPAPRMachineState *spapr, 359 target_ulong opcode, 360 target_ulong *args) 361 { 362 target_ulong flags = args[0]; 363 target_ulong shift = args[1]; 364 365 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 366 return H_AUTHORITY; 367 } 368 369 trace_spapr_h_resize_hpt_prepare(flags, shift); 370 return H_HARDWARE; 371 } 372 373 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 374 sPAPRMachineState *spapr, 375 target_ulong opcode, 376 target_ulong *args) 377 { 378 target_ulong flags = args[0]; 379 target_ulong shift = args[1]; 380 381 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 382 return H_AUTHORITY; 383 } 384 385 trace_spapr_h_resize_hpt_commit(flags, shift); 386 return H_HARDWARE; 387 } 388 389 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 390 target_ulong opcode, target_ulong *args) 391 { 392 cpu_synchronize_state(CPU(cpu)); 393 cpu->env.spr[SPR_SPRG0] = args[0]; 394 395 return H_SUCCESS; 396 } 397 398 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 399 target_ulong opcode, target_ulong *args) 400 { 401 if (!has_spr(cpu, SPR_DABR)) { 402 return H_HARDWARE; /* DABR register not available */ 403 } 404 cpu_synchronize_state(CPU(cpu)); 405 406 if (has_spr(cpu, SPR_DABRX)) { 407 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 408 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 409 return H_RESERVED_DABR; 410 } 411 412 cpu->env.spr[SPR_DABR] = args[0]; 413 return H_SUCCESS; 414 } 415 416 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 417 target_ulong opcode, target_ulong *args) 418 { 419 target_ulong dabrx = args[1]; 420 421 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 422 return H_HARDWARE; 423 } 424 425 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 426 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 427 return H_PARAMETER; 428 } 429 430 cpu_synchronize_state(CPU(cpu)); 431 cpu->env.spr[SPR_DABRX] = dabrx; 432 cpu->env.spr[SPR_DABR] = args[0]; 433 434 return H_SUCCESS; 435 } 436 437 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 438 target_ulong opcode, target_ulong *args) 439 { 440 target_ulong flags = args[0]; 441 hwaddr dst = args[1]; 442 hwaddr src = args[2]; 443 hwaddr len = TARGET_PAGE_SIZE; 444 uint8_t *pdst, *psrc; 445 target_long ret = H_SUCCESS; 446 447 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 448 | H_COPY_PAGE | H_ZERO_PAGE)) { 449 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 450 flags); 451 return H_PARAMETER; 452 } 453 454 /* Map-in destination */ 455 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 456 return H_PARAMETER; 457 } 458 pdst = cpu_physical_memory_map(dst, &len, 1); 459 if (!pdst || len != TARGET_PAGE_SIZE) { 460 return H_PARAMETER; 461 } 462 463 if (flags & H_COPY_PAGE) { 464 /* Map-in source, copy to destination, and unmap source again */ 465 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 466 ret = H_PARAMETER; 467 goto unmap_out; 468 } 469 psrc = cpu_physical_memory_map(src, &len, 0); 470 if (!psrc || len != TARGET_PAGE_SIZE) { 471 ret = H_PARAMETER; 472 goto unmap_out; 473 } 474 memcpy(pdst, psrc, len); 475 cpu_physical_memory_unmap(psrc, len, 0, len); 476 } else if (flags & H_ZERO_PAGE) { 477 memset(pdst, 0, len); /* Just clear the destination page */ 478 } 479 480 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 481 kvmppc_dcbst_range(cpu, pdst, len); 482 } 483 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 484 if (kvm_enabled()) { 485 kvmppc_icbi_range(cpu, pdst, len); 486 } else { 487 tb_flush(CPU(cpu)); 488 } 489 } 490 491 unmap_out: 492 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 493 return ret; 494 } 495 496 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 497 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 498 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 499 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 500 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 501 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 502 503 #define VPA_MIN_SIZE 640 504 #define VPA_SIZE_OFFSET 0x4 505 #define VPA_SHARED_PROC_OFFSET 0x9 506 #define VPA_SHARED_PROC_VAL 0x2 507 508 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 509 { 510 CPUState *cs = CPU(ppc_env_get_cpu(env)); 511 uint16_t size; 512 uint8_t tmp; 513 514 if (vpa == 0) { 515 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 516 return H_HARDWARE; 517 } 518 519 if (vpa % env->dcache_line_size) { 520 return H_PARAMETER; 521 } 522 /* FIXME: bounds check the address */ 523 524 size = lduw_be_phys(cs->as, vpa + 0x4); 525 526 if (size < VPA_MIN_SIZE) { 527 return H_PARAMETER; 528 } 529 530 /* VPA is not allowed to cross a page boundary */ 531 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 532 return H_PARAMETER; 533 } 534 535 env->vpa_addr = vpa; 536 537 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 538 tmp |= VPA_SHARED_PROC_VAL; 539 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 540 541 return H_SUCCESS; 542 } 543 544 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 545 { 546 if (env->slb_shadow_addr) { 547 return H_RESOURCE; 548 } 549 550 if (env->dtl_addr) { 551 return H_RESOURCE; 552 } 553 554 env->vpa_addr = 0; 555 return H_SUCCESS; 556 } 557 558 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 559 { 560 CPUState *cs = CPU(ppc_env_get_cpu(env)); 561 uint32_t size; 562 563 if (addr == 0) { 564 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 565 return H_HARDWARE; 566 } 567 568 size = ldl_be_phys(cs->as, addr + 0x4); 569 if (size < 0x8) { 570 return H_PARAMETER; 571 } 572 573 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 574 return H_PARAMETER; 575 } 576 577 if (!env->vpa_addr) { 578 return H_RESOURCE; 579 } 580 581 env->slb_shadow_addr = addr; 582 env->slb_shadow_size = size; 583 584 return H_SUCCESS; 585 } 586 587 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 588 { 589 env->slb_shadow_addr = 0; 590 env->slb_shadow_size = 0; 591 return H_SUCCESS; 592 } 593 594 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 595 { 596 CPUState *cs = CPU(ppc_env_get_cpu(env)); 597 uint32_t size; 598 599 if (addr == 0) { 600 hcall_dprintf("Can't cope with DTL at logical 0\n"); 601 return H_HARDWARE; 602 } 603 604 size = ldl_be_phys(cs->as, addr + 0x4); 605 606 if (size < 48) { 607 return H_PARAMETER; 608 } 609 610 if (!env->vpa_addr) { 611 return H_RESOURCE; 612 } 613 614 env->dtl_addr = addr; 615 env->dtl_size = size; 616 617 return H_SUCCESS; 618 } 619 620 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 621 { 622 env->dtl_addr = 0; 623 env->dtl_size = 0; 624 625 return H_SUCCESS; 626 } 627 628 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 629 target_ulong opcode, target_ulong *args) 630 { 631 target_ulong flags = args[0]; 632 target_ulong procno = args[1]; 633 target_ulong vpa = args[2]; 634 target_ulong ret = H_PARAMETER; 635 CPUPPCState *tenv; 636 PowerPCCPU *tcpu; 637 638 tcpu = ppc_get_vcpu_by_dt_id(procno); 639 if (!tcpu) { 640 return H_PARAMETER; 641 } 642 tenv = &tcpu->env; 643 644 switch (flags) { 645 case FLAGS_REGISTER_VPA: 646 ret = register_vpa(tenv, vpa); 647 break; 648 649 case FLAGS_DEREGISTER_VPA: 650 ret = deregister_vpa(tenv, vpa); 651 break; 652 653 case FLAGS_REGISTER_SLBSHADOW: 654 ret = register_slb_shadow(tenv, vpa); 655 break; 656 657 case FLAGS_DEREGISTER_SLBSHADOW: 658 ret = deregister_slb_shadow(tenv, vpa); 659 break; 660 661 case FLAGS_REGISTER_DTL: 662 ret = register_dtl(tenv, vpa); 663 break; 664 665 case FLAGS_DEREGISTER_DTL: 666 ret = deregister_dtl(tenv, vpa); 667 break; 668 } 669 670 return ret; 671 } 672 673 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 674 target_ulong opcode, target_ulong *args) 675 { 676 CPUPPCState *env = &cpu->env; 677 CPUState *cs = CPU(cpu); 678 679 env->msr |= (1ULL << MSR_EE); 680 hreg_compute_hflags(env); 681 if (!cpu_has_work(cs)) { 682 cs->halted = 1; 683 cs->exception_index = EXCP_HLT; 684 cs->exit_request = 1; 685 } 686 return H_SUCCESS; 687 } 688 689 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 690 target_ulong opcode, target_ulong *args) 691 { 692 target_ulong rtas_r3 = args[0]; 693 uint32_t token = rtas_ld(rtas_r3, 0); 694 uint32_t nargs = rtas_ld(rtas_r3, 1); 695 uint32_t nret = rtas_ld(rtas_r3, 2); 696 697 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 698 nret, rtas_r3 + 12 + 4*nargs); 699 } 700 701 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 702 target_ulong opcode, target_ulong *args) 703 { 704 CPUState *cs = CPU(cpu); 705 target_ulong size = args[0]; 706 target_ulong addr = args[1]; 707 708 switch (size) { 709 case 1: 710 args[0] = ldub_phys(cs->as, addr); 711 return H_SUCCESS; 712 case 2: 713 args[0] = lduw_phys(cs->as, addr); 714 return H_SUCCESS; 715 case 4: 716 args[0] = ldl_phys(cs->as, addr); 717 return H_SUCCESS; 718 case 8: 719 args[0] = ldq_phys(cs->as, addr); 720 return H_SUCCESS; 721 } 722 return H_PARAMETER; 723 } 724 725 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 726 target_ulong opcode, target_ulong *args) 727 { 728 CPUState *cs = CPU(cpu); 729 730 target_ulong size = args[0]; 731 target_ulong addr = args[1]; 732 target_ulong val = args[2]; 733 734 switch (size) { 735 case 1: 736 stb_phys(cs->as, addr, val); 737 return H_SUCCESS; 738 case 2: 739 stw_phys(cs->as, addr, val); 740 return H_SUCCESS; 741 case 4: 742 stl_phys(cs->as, addr, val); 743 return H_SUCCESS; 744 case 8: 745 stq_phys(cs->as, addr, val); 746 return H_SUCCESS; 747 } 748 return H_PARAMETER; 749 } 750 751 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 752 target_ulong opcode, target_ulong *args) 753 { 754 CPUState *cs = CPU(cpu); 755 756 target_ulong dst = args[0]; /* Destination address */ 757 target_ulong src = args[1]; /* Source address */ 758 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 759 target_ulong count = args[3]; /* Element count */ 760 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 761 uint64_t tmp; 762 unsigned int mask = (1 << esize) - 1; 763 int step = 1 << esize; 764 765 if (count > 0x80000000) { 766 return H_PARAMETER; 767 } 768 769 if ((dst & mask) || (src & mask) || (op > 1)) { 770 return H_PARAMETER; 771 } 772 773 if (dst >= src && dst < (src + (count << esize))) { 774 dst = dst + ((count - 1) << esize); 775 src = src + ((count - 1) << esize); 776 step = -step; 777 } 778 779 while (count--) { 780 switch (esize) { 781 case 0: 782 tmp = ldub_phys(cs->as, src); 783 break; 784 case 1: 785 tmp = lduw_phys(cs->as, src); 786 break; 787 case 2: 788 tmp = ldl_phys(cs->as, src); 789 break; 790 case 3: 791 tmp = ldq_phys(cs->as, src); 792 break; 793 default: 794 return H_PARAMETER; 795 } 796 if (op == 1) { 797 tmp = ~tmp; 798 } 799 switch (esize) { 800 case 0: 801 stb_phys(cs->as, dst, tmp); 802 break; 803 case 1: 804 stw_phys(cs->as, dst, tmp); 805 break; 806 case 2: 807 stl_phys(cs->as, dst, tmp); 808 break; 809 case 3: 810 stq_phys(cs->as, dst, tmp); 811 break; 812 } 813 dst = dst + step; 814 src = src + step; 815 } 816 817 return H_SUCCESS; 818 } 819 820 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 821 target_ulong opcode, target_ulong *args) 822 { 823 /* Nothing to do on emulation, KVM will trap this in the kernel */ 824 return H_SUCCESS; 825 } 826 827 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 828 target_ulong opcode, target_ulong *args) 829 { 830 /* Nothing to do on emulation, KVM will trap this in the kernel */ 831 return H_SUCCESS; 832 } 833 834 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 835 target_ulong mflags, 836 target_ulong value1, 837 target_ulong value2) 838 { 839 CPUState *cs; 840 841 if (value1) { 842 return H_P3; 843 } 844 if (value2) { 845 return H_P4; 846 } 847 848 switch (mflags) { 849 case H_SET_MODE_ENDIAN_BIG: 850 CPU_FOREACH(cs) { 851 set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 852 } 853 spapr_pci_switch_vga(true); 854 return H_SUCCESS; 855 856 case H_SET_MODE_ENDIAN_LITTLE: 857 CPU_FOREACH(cs) { 858 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 859 } 860 spapr_pci_switch_vga(false); 861 return H_SUCCESS; 862 } 863 864 return H_UNSUPPORTED_FLAG; 865 } 866 867 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 868 target_ulong mflags, 869 target_ulong value1, 870 target_ulong value2) 871 { 872 CPUState *cs; 873 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 874 875 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 876 return H_P2; 877 } 878 if (value1) { 879 return H_P3; 880 } 881 if (value2) { 882 return H_P4; 883 } 884 885 if (mflags == AIL_RESERVED) { 886 return H_UNSUPPORTED_FLAG; 887 } 888 889 CPU_FOREACH(cs) { 890 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 891 } 892 893 return H_SUCCESS; 894 } 895 896 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 897 target_ulong opcode, target_ulong *args) 898 { 899 target_ulong resource = args[1]; 900 target_ulong ret = H_P2; 901 902 switch (resource) { 903 case H_SET_MODE_RESOURCE_LE: 904 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 905 break; 906 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 907 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 908 args[2], args[3]); 909 break; 910 } 911 912 return ret; 913 } 914 915 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 916 target_ulong opcode, target_ulong *args) 917 { 918 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 919 opcode, " (H_CLEAN_SLB)"); 920 return H_FUNCTION; 921 } 922 923 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 924 target_ulong opcode, target_ulong *args) 925 { 926 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 927 opcode, " (H_INVALIDATE_PID)"); 928 return H_FUNCTION; 929 } 930 931 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 932 uint64_t patbe_old, uint64_t patbe_new) 933 { 934 /* 935 * We have 4 Options: 936 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 937 * HASH->RADIX : Free HPT 938 * RADIX->HASH : Allocate HPT 939 * NOTHING->HASH : Allocate HPT 940 * Note: NOTHING implies the case where we said the guest could choose 941 * later and so assumed radix and now it's called H_REG_PROC_TBL 942 */ 943 944 if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 945 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 946 } else if (!(patbe_old & PATBE1_GR)) { 947 /* HASH->RADIX : Free HPT */ 948 spapr_free_hpt(spapr); 949 } else if (!(patbe_new & PATBE1_GR)) { 950 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 951 spapr_setup_hpt_and_vrma(spapr); 952 } 953 return; 954 } 955 956 #define FLAGS_MASK 0x01FULL 957 #define FLAG_MODIFY 0x10 958 #define FLAG_REGISTER 0x08 959 #define FLAG_RADIX 0x04 960 #define FLAG_HASH_PROC_TBL 0x02 961 #define FLAG_GTSE 0x01 962 963 static target_ulong h_register_process_table(PowerPCCPU *cpu, 964 sPAPRMachineState *spapr, 965 target_ulong opcode, 966 target_ulong *args) 967 { 968 CPUState *cs; 969 target_ulong flags = args[0]; 970 target_ulong proc_tbl = args[1]; 971 target_ulong page_size = args[2]; 972 target_ulong table_size = args[3]; 973 uint64_t cproc; 974 975 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 976 return H_PARAMETER; 977 } 978 if (flags & FLAG_MODIFY) { 979 if (flags & FLAG_REGISTER) { 980 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 981 if (proc_tbl & 0xfff || proc_tbl >> 60) { 982 return H_P2; 983 } else if (page_size) { 984 return H_P3; 985 } else if (table_size > 24) { 986 return H_P4; 987 } 988 cproc = PATBE1_GR | proc_tbl | table_size; 989 } else { /* Register new HPT process table */ 990 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 991 /* TODO - Not Supported */ 992 /* Technically caused by flag bits => H_PARAMETER */ 993 return H_PARAMETER; 994 } else { /* Hash with SLB */ 995 if (proc_tbl >> 38) { 996 return H_P2; 997 } else if (page_size & ~0x7) { 998 return H_P3; 999 } else if (table_size > 24) { 1000 return H_P4; 1001 } 1002 } 1003 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1004 } 1005 1006 } else { /* Deregister current process table */ 1007 /* Set to benign value: (current GR) | 0. This allows 1008 * deregistration in KVM to succeed even if the radix bit in flags 1009 * doesn't match the radix bit in the old PATB. */ 1010 cproc = spapr->patb_entry & PATBE1_GR; 1011 } 1012 } else { /* Maintain current registration */ 1013 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 1014 /* Technically caused by flag bits => H_PARAMETER */ 1015 return H_PARAMETER; /* Existing Process Table Mismatch */ 1016 } 1017 cproc = spapr->patb_entry; 1018 } 1019 1020 /* Check if we need to setup OR free the hpt */ 1021 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1022 1023 spapr->patb_entry = cproc; /* Save new process table */ 1024 1025 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 1026 CPU_FOREACH(cs) { 1027 set_spr(cs, SPR_LPCR, 1028 ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 1029 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 1030 LPCR_UPRT | LPCR_GTSE); 1031 } 1032 1033 if (kvm_enabled()) { 1034 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1035 flags & FLAG_GTSE, cproc); 1036 } 1037 return H_SUCCESS; 1038 } 1039 1040 #define H_SIGNAL_SYS_RESET_ALL -1 1041 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1042 1043 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1044 sPAPRMachineState *spapr, 1045 target_ulong opcode, target_ulong *args) 1046 { 1047 target_long target = args[0]; 1048 CPUState *cs; 1049 1050 if (target < 0) { 1051 /* Broadcast */ 1052 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1053 return H_PARAMETER; 1054 } 1055 1056 CPU_FOREACH(cs) { 1057 PowerPCCPU *c = POWERPC_CPU(cs); 1058 1059 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1060 if (c == cpu) { 1061 continue; 1062 } 1063 } 1064 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1065 } 1066 return H_SUCCESS; 1067 1068 } else { 1069 /* Unicast */ 1070 CPU_FOREACH(cs) { 1071 if (cpu->cpu_dt_id == target) { 1072 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1073 return H_SUCCESS; 1074 } 1075 } 1076 return H_PARAMETER; 1077 } 1078 } 1079 1080 static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1081 target_ulong *addr, Error **errp) 1082 { 1083 bool explicit_match = false; /* Matched the CPU's real PVR */ 1084 uint32_t max_compat = spapr->max_compat_pvr; 1085 uint32_t best_compat = 0; 1086 int i; 1087 1088 /* 1089 * We scan the supplied table of PVRs looking for two things 1090 * 1. Is our real CPU PVR in the list? 1091 * 2. What's the "best" listed logical PVR 1092 */ 1093 for (i = 0; i < 512; ++i) { 1094 uint32_t pvr, pvr_mask; 1095 1096 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1097 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1098 *addr += 8; 1099 1100 if (~pvr_mask & pvr) { 1101 break; /* Terminator record */ 1102 } 1103 1104 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1105 explicit_match = true; 1106 } else { 1107 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1108 best_compat = pvr; 1109 } 1110 } 1111 } 1112 1113 if ((best_compat == 0) && (!explicit_match || max_compat)) { 1114 /* We couldn't find a suitable compatibility mode, and either 1115 * the guest doesn't support "raw" mode for this CPU, or raw 1116 * mode is disabled because a maximum compat mode is set */ 1117 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 1118 return 0; 1119 } 1120 1121 /* Parsing finished */ 1122 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1123 1124 return best_compat; 1125 } 1126 1127 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1128 sPAPRMachineState *spapr, 1129 target_ulong opcode, 1130 target_ulong *args) 1131 { 1132 /* Working address in data buffer */ 1133 target_ulong addr = ppc64_phys_to_real(args[0]); 1134 target_ulong ov_table; 1135 uint32_t cas_pvr; 1136 sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 1137 bool guest_radix; 1138 Error *local_err = NULL; 1139 1140 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &local_err); 1141 if (local_err) { 1142 error_report_err(local_err); 1143 return H_HARDWARE; 1144 } 1145 1146 /* Update CPUs */ 1147 if (cpu->compat_pvr != cas_pvr) { 1148 ppc_set_compat_all(cas_pvr, &local_err); 1149 if (local_err) { 1150 error_report_err(local_err); 1151 return H_HARDWARE; 1152 } 1153 } 1154 1155 /* For the future use: here @ov_table points to the first option vector */ 1156 ov_table = addr; 1157 1158 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1159 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1160 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1161 error_report("guest requested hash and radix MMU, which is invalid."); 1162 exit(EXIT_FAILURE); 1163 } 1164 /* The radix/hash bit in byte 24 requires special handling: */ 1165 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1166 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 1167 1168 /* NOTE: there are actually a number of ov5 bits where input from the 1169 * guest is always zero, and the platform/QEMU enables them independently 1170 * of guest input. To model these properly we'd want some sort of mask, 1171 * but since they only currently apply to memory migration as defined 1172 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1173 * to worry about this for now. 1174 */ 1175 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1176 /* full range of negotiated ov5 capabilities */ 1177 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1178 spapr_ovec_cleanup(ov5_guest); 1179 /* capabilities that have been added since CAS-generated guest reset. 1180 * if capabilities have since been removed, generate another reset 1181 */ 1182 ov5_updates = spapr_ovec_new(); 1183 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1184 ov5_cas_old, spapr->ov5_cas); 1185 /* Now that processing is finished, set the radix/hash bit for the 1186 * guest if it requested a valid mode; otherwise terminate the boot. */ 1187 if (guest_radix) { 1188 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1189 error_report("Guest requested unavailable MMU mode (radix)."); 1190 exit(EXIT_FAILURE); 1191 } 1192 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 1193 } else { 1194 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1195 && !kvmppc_has_cap_mmu_hash_v3()) { 1196 error_report("Guest requested unavailable MMU mode (hash)."); 1197 exit(EXIT_FAILURE); 1198 } 1199 } 1200 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1201 OV1_PPC_3_00); 1202 if (!spapr->cas_reboot) { 1203 spapr->cas_reboot = 1204 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1205 ov5_updates) != 0); 1206 } 1207 spapr_ovec_cleanup(ov5_updates); 1208 1209 if (spapr->cas_reboot) { 1210 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1211 } else { 1212 /* If ppc_spapr_reset() did not set up a HPT but one is necessary 1213 * (because the guest isn't going to use radix) then set it up here. */ 1214 if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 1215 /* legacy hash or new hash: */ 1216 spapr_setup_hpt_and_vrma(spapr); 1217 } 1218 } 1219 1220 return H_SUCCESS; 1221 } 1222 1223 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1224 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1225 1226 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1227 { 1228 spapr_hcall_fn *slot; 1229 1230 if (opcode <= MAX_HCALL_OPCODE) { 1231 assert((opcode & 0x3) == 0); 1232 1233 slot = &papr_hypercall_table[opcode / 4]; 1234 } else { 1235 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1236 1237 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1238 } 1239 1240 assert(!(*slot)); 1241 *slot = fn; 1242 } 1243 1244 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1245 target_ulong *args) 1246 { 1247 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1248 1249 if ((opcode <= MAX_HCALL_OPCODE) 1250 && ((opcode & 0x3) == 0)) { 1251 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1252 1253 if (fn) { 1254 return fn(cpu, spapr, opcode, args); 1255 } 1256 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1257 (opcode <= KVMPPC_HCALL_MAX)) { 1258 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1259 1260 if (fn) { 1261 return fn(cpu, spapr, opcode, args); 1262 } 1263 } 1264 1265 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1266 opcode); 1267 return H_FUNCTION; 1268 } 1269 1270 static void hypercall_register_types(void) 1271 { 1272 /* hcall-pft */ 1273 spapr_register_hypercall(H_ENTER, h_enter); 1274 spapr_register_hypercall(H_REMOVE, h_remove); 1275 spapr_register_hypercall(H_PROTECT, h_protect); 1276 spapr_register_hypercall(H_READ, h_read); 1277 1278 /* hcall-bulk */ 1279 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1280 1281 /* hcall-hpt-resize */ 1282 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1283 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1284 1285 /* hcall-splpar */ 1286 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1287 spapr_register_hypercall(H_CEDE, h_cede); 1288 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1289 1290 /* processor register resource access h-calls */ 1291 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1292 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1293 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1294 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1295 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1296 1297 /* In Memory Table MMU h-calls */ 1298 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1299 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1300 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1301 1302 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1303 * here between the "CI" and the "CACHE" variants, they will use whatever 1304 * mapping attributes qemu is using. When using KVM, the kernel will 1305 * enforce the attributes more strongly 1306 */ 1307 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1308 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1309 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1310 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1311 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1312 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1313 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1314 1315 /* qemu/KVM-PPC specific hcalls */ 1316 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1317 1318 /* ibm,client-architecture-support support */ 1319 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1320 } 1321 1322 type_init(hypercall_register_types) 1323