1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/sysemu.h" 5 #include "qemu/log.h" 6 #include "qemu/error-report.h" 7 #include "cpu.h" 8 #include "exec/exec-all.h" 9 #include "helper_regs.h" 10 #include "hw/ppc/spapr.h" 11 #include "mmu-hash64.h" 12 #include "cpu-models.h" 13 #include "trace.h" 14 #include "kvm_ppc.h" 15 #include "hw/ppc/spapr_ovec.h" 16 #include "qemu/error-report.h" 17 #include "mmu-book3s-v3.h" 18 19 struct SPRSyncState { 20 int spr; 21 target_ulong value; 22 target_ulong mask; 23 }; 24 25 static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 26 { 27 struct SPRSyncState *s = arg.host_ptr; 28 PowerPCCPU *cpu = POWERPC_CPU(cs); 29 CPUPPCState *env = &cpu->env; 30 31 cpu_synchronize_state(cs); 32 env->spr[s->spr] &= ~s->mask; 33 env->spr[s->spr] |= s->value; 34 } 35 36 static void set_spr(CPUState *cs, int spr, target_ulong value, 37 target_ulong mask) 38 { 39 struct SPRSyncState s = { 40 .spr = spr, 41 .value = value, 42 .mask = mask 43 }; 44 run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 45 } 46 47 static bool has_spr(PowerPCCPU *cpu, int spr) 48 { 49 /* We can test whether the SPR is defined by checking for a valid name */ 50 return cpu->env.spr_cb[spr].name != NULL; 51 } 52 53 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 54 { 55 /* 56 * hash value/pteg group index is normalized by HPT mask 57 */ 58 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 59 return false; 60 } 61 return true; 62 } 63 64 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 65 { 66 MachineState *machine = MACHINE(spapr); 67 MemoryHotplugState *hpms = &spapr->hotplug_memory; 68 69 if (addr < machine->ram_size) { 70 return true; 71 } 72 if ((addr >= hpms->base) 73 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 74 return true; 75 } 76 77 return false; 78 } 79 80 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 81 target_ulong opcode, target_ulong *args) 82 { 83 target_ulong flags = args[0]; 84 target_ulong ptex = args[1]; 85 target_ulong pteh = args[2]; 86 target_ulong ptel = args[3]; 87 unsigned apshift; 88 target_ulong raddr; 89 target_ulong slot; 90 const ppc_hash_pte64_t *hptes; 91 92 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 93 if (!apshift) { 94 /* Bad page size encoding */ 95 return H_PARAMETER; 96 } 97 98 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 99 100 if (is_ram_address(spapr, raddr)) { 101 /* Regular RAM - should have WIMG=0010 */ 102 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 103 return H_PARAMETER; 104 } 105 } else { 106 target_ulong wimg_flags; 107 /* Looks like an IO address */ 108 /* FIXME: What WIMG combinations could be sensible for IO? 109 * For now we allow WIMG=010x, but are there others? */ 110 /* FIXME: Should we check against registered IO addresses? */ 111 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 112 113 if (wimg_flags != HPTE64_R_I && 114 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 115 return H_PARAMETER; 116 } 117 } 118 119 pteh &= ~0x60ULL; 120 121 if (!valid_ptex(cpu, ptex)) { 122 return H_PARAMETER; 123 } 124 125 slot = ptex & 7ULL; 126 ptex = ptex & ~7ULL; 127 128 if (likely((flags & H_EXACT) == 0)) { 129 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 130 for (slot = 0; slot < 8; slot++) { 131 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 132 break; 133 } 134 } 135 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 136 if (slot == 8) { 137 return H_PTEG_FULL; 138 } 139 } else { 140 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 141 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 142 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 143 return H_PTEG_FULL; 144 } 145 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 146 } 147 148 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 149 150 args[0] = ptex + slot; 151 return H_SUCCESS; 152 } 153 154 typedef enum { 155 REMOVE_SUCCESS = 0, 156 REMOVE_NOT_FOUND = 1, 157 REMOVE_PARM = 2, 158 REMOVE_HW = 3, 159 } RemoveResult; 160 161 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 162 target_ulong avpn, 163 target_ulong flags, 164 target_ulong *vp, target_ulong *rp) 165 { 166 const ppc_hash_pte64_t *hptes; 167 target_ulong v, r; 168 169 if (!valid_ptex(cpu, ptex)) { 170 return REMOVE_PARM; 171 } 172 173 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 174 v = ppc_hash64_hpte0(cpu, hptes, 0); 175 r = ppc_hash64_hpte1(cpu, hptes, 0); 176 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 177 178 if ((v & HPTE64_V_VALID) == 0 || 179 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 180 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 181 return REMOVE_NOT_FOUND; 182 } 183 *vp = v; 184 *rp = r; 185 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 186 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 187 return REMOVE_SUCCESS; 188 } 189 190 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 191 target_ulong opcode, target_ulong *args) 192 { 193 CPUPPCState *env = &cpu->env; 194 target_ulong flags = args[0]; 195 target_ulong ptex = args[1]; 196 target_ulong avpn = args[2]; 197 RemoveResult ret; 198 199 ret = remove_hpte(cpu, ptex, avpn, flags, 200 &args[0], &args[1]); 201 202 switch (ret) { 203 case REMOVE_SUCCESS: 204 check_tlb_flush(env, true); 205 return H_SUCCESS; 206 207 case REMOVE_NOT_FOUND: 208 return H_NOT_FOUND; 209 210 case REMOVE_PARM: 211 return H_PARAMETER; 212 213 case REMOVE_HW: 214 return H_HARDWARE; 215 } 216 217 g_assert_not_reached(); 218 } 219 220 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 221 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 222 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 223 #define H_BULK_REMOVE_END 0xc000000000000000ULL 224 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 225 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 226 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 227 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 228 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 229 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 230 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 231 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 232 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 233 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 234 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 235 236 #define H_BULK_REMOVE_MAX_BATCH 4 237 238 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 239 target_ulong opcode, target_ulong *args) 240 { 241 CPUPPCState *env = &cpu->env; 242 int i; 243 target_ulong rc = H_SUCCESS; 244 245 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 246 target_ulong *tsh = &args[i*2]; 247 target_ulong tsl = args[i*2 + 1]; 248 target_ulong v, r, ret; 249 250 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 251 break; 252 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 253 return H_PARAMETER; 254 } 255 256 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 257 *tsh |= H_BULK_REMOVE_RESPONSE; 258 259 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 260 *tsh |= H_BULK_REMOVE_PARM; 261 return H_PARAMETER; 262 } 263 264 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 265 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 266 &v, &r); 267 268 *tsh |= ret << 60; 269 270 switch (ret) { 271 case REMOVE_SUCCESS: 272 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 273 break; 274 275 case REMOVE_PARM: 276 rc = H_PARAMETER; 277 goto exit; 278 279 case REMOVE_HW: 280 rc = H_HARDWARE; 281 goto exit; 282 } 283 } 284 exit: 285 check_tlb_flush(env, true); 286 287 return rc; 288 } 289 290 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 291 target_ulong opcode, target_ulong *args) 292 { 293 CPUPPCState *env = &cpu->env; 294 target_ulong flags = args[0]; 295 target_ulong ptex = args[1]; 296 target_ulong avpn = args[2]; 297 const ppc_hash_pte64_t *hptes; 298 target_ulong v, r; 299 300 if (!valid_ptex(cpu, ptex)) { 301 return H_PARAMETER; 302 } 303 304 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 305 v = ppc_hash64_hpte0(cpu, hptes, 0); 306 r = ppc_hash64_hpte1(cpu, hptes, 0); 307 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 308 309 if ((v & HPTE64_V_VALID) == 0 || 310 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 311 return H_NOT_FOUND; 312 } 313 314 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 315 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 316 r |= (flags << 55) & HPTE64_R_PP0; 317 r |= (flags << 48) & HPTE64_R_KEY_HI; 318 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 319 ppc_hash64_store_hpte(cpu, ptex, 320 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 321 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 322 /* Flush the tlb */ 323 check_tlb_flush(env, true); 324 /* Don't need a memory barrier, due to qemu's global lock */ 325 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 326 return H_SUCCESS; 327 } 328 329 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 330 target_ulong opcode, target_ulong *args) 331 { 332 target_ulong flags = args[0]; 333 target_ulong ptex = args[1]; 334 uint8_t *hpte; 335 int i, ridx, n_entries = 1; 336 337 if (!valid_ptex(cpu, ptex)) { 338 return H_PARAMETER; 339 } 340 341 if (flags & H_READ_4) { 342 /* Clear the two low order bits */ 343 ptex &= ~(3ULL); 344 n_entries = 4; 345 } 346 347 hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 348 349 for (i = 0, ridx = 0; i < n_entries; i++) { 350 args[ridx++] = ldq_p(hpte); 351 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 352 hpte += HASH_PTE_SIZE_64; 353 } 354 355 return H_SUCCESS; 356 } 357 358 struct sPAPRPendingHPT { 359 /* These fields are read-only after initialization */ 360 int shift; 361 QemuThread thread; 362 363 /* These fields are protected by the BQL */ 364 bool complete; 365 366 /* These fields are private to the preparation thread if 367 * !complete, otherwise protected by the BQL */ 368 int ret; 369 void *hpt; 370 }; 371 372 static void free_pending_hpt(sPAPRPendingHPT *pending) 373 { 374 if (pending->hpt) { 375 qemu_vfree(pending->hpt); 376 } 377 378 g_free(pending); 379 } 380 381 static void *hpt_prepare_thread(void *opaque) 382 { 383 sPAPRPendingHPT *pending = opaque; 384 size_t size = 1ULL << pending->shift; 385 386 pending->hpt = qemu_memalign(size, size); 387 if (pending->hpt) { 388 memset(pending->hpt, 0, size); 389 pending->ret = H_SUCCESS; 390 } else { 391 pending->ret = H_NO_MEM; 392 } 393 394 qemu_mutex_lock_iothread(); 395 396 if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 397 /* Ready to go */ 398 pending->complete = true; 399 } else { 400 /* We've been cancelled, clean ourselves up */ 401 free_pending_hpt(pending); 402 } 403 404 qemu_mutex_unlock_iothread(); 405 return NULL; 406 } 407 408 /* Must be called with BQL held */ 409 static void cancel_hpt_prepare(sPAPRMachineState *spapr) 410 { 411 sPAPRPendingHPT *pending = spapr->pending_hpt; 412 413 /* Let the thread know it's cancelled */ 414 spapr->pending_hpt = NULL; 415 416 if (!pending) { 417 /* Nothing to do */ 418 return; 419 } 420 421 if (!pending->complete) { 422 /* thread will clean itself up */ 423 return; 424 } 425 426 free_pending_hpt(pending); 427 } 428 429 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 430 sPAPRMachineState *spapr, 431 target_ulong opcode, 432 target_ulong *args) 433 { 434 target_ulong flags = args[0]; 435 int shift = args[1]; 436 sPAPRPendingHPT *pending = spapr->pending_hpt; 437 uint64_t current_ram_size = MACHINE(spapr)->ram_size; 438 439 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 440 return H_AUTHORITY; 441 } 442 443 if (!spapr->htab_shift) { 444 /* Radix guest, no HPT */ 445 return H_NOT_AVAILABLE; 446 } 447 448 trace_spapr_h_resize_hpt_prepare(flags, shift); 449 450 if (flags != 0) { 451 return H_PARAMETER; 452 } 453 454 if (shift && ((shift < 18) || (shift > 46))) { 455 return H_PARAMETER; 456 } 457 458 current_ram_size = pc_existing_dimms_capacity(&error_fatal); 459 460 /* We only allow the guest to allocate an HPT one order above what 461 * we'd normally give them (to stop a small guest claiming a huge 462 * chunk of resources in the HPT */ 463 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 464 return H_RESOURCE; 465 } 466 467 if (pending) { 468 /* something already in progress */ 469 if (pending->shift == shift) { 470 /* and it's suitable */ 471 if (pending->complete) { 472 return pending->ret; 473 } else { 474 return H_LONG_BUSY_ORDER_100_MSEC; 475 } 476 } 477 478 /* not suitable, cancel and replace */ 479 cancel_hpt_prepare(spapr); 480 } 481 482 if (!shift) { 483 /* nothing to do */ 484 return H_SUCCESS; 485 } 486 487 /* start new prepare */ 488 489 pending = g_new0(sPAPRPendingHPT, 1); 490 pending->shift = shift; 491 pending->ret = H_HARDWARE; 492 493 qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 494 hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 495 496 spapr->pending_hpt = pending; 497 498 /* In theory we could estimate the time more accurately based on 499 * the new size, but there's not much point */ 500 return H_LONG_BUSY_ORDER_100_MSEC; 501 } 502 503 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 504 { 505 uint8_t *addr = htab; 506 507 addr += pteg * HASH_PTEG_SIZE_64; 508 addr += slot * HASH_PTE_SIZE_64; 509 return ldq_p(addr); 510 } 511 512 static void new_hpte_store(void *htab, uint64_t pteg, int slot, 513 uint64_t pte0, uint64_t pte1) 514 { 515 uint8_t *addr = htab; 516 517 addr += pteg * HASH_PTEG_SIZE_64; 518 addr += slot * HASH_PTE_SIZE_64; 519 520 stq_p(addr, pte0); 521 stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 522 } 523 524 static int rehash_hpte(PowerPCCPU *cpu, 525 const ppc_hash_pte64_t *hptes, 526 void *old_hpt, uint64_t oldsize, 527 void *new_hpt, uint64_t newsize, 528 uint64_t pteg, int slot) 529 { 530 uint64_t old_hash_mask = (oldsize >> 7) - 1; 531 uint64_t new_hash_mask = (newsize >> 7) - 1; 532 target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 533 target_ulong pte1; 534 uint64_t avpn; 535 unsigned base_pg_shift; 536 uint64_t hash, new_pteg, replace_pte0; 537 538 if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 539 return H_SUCCESS; 540 } 541 542 pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 543 544 base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 545 assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 546 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 547 548 if (pte0 & HPTE64_V_SECONDARY) { 549 pteg = ~pteg; 550 } 551 552 if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 553 uint64_t offset, vsid; 554 555 /* We only have 28 - 23 bits of offset in avpn */ 556 offset = (avpn & 0x1f) << 23; 557 vsid = avpn >> 5; 558 /* We can find more bits from the pteg value */ 559 if (base_pg_shift < 23) { 560 offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 561 } 562 563 hash = vsid ^ (offset >> base_pg_shift); 564 } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 565 uint64_t offset, vsid; 566 567 /* We only have 40 - 23 bits of seg_off in avpn */ 568 offset = (avpn & 0x1ffff) << 23; 569 vsid = avpn >> 17; 570 if (base_pg_shift < 23) { 571 offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 572 << base_pg_shift; 573 } 574 575 hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 576 } else { 577 error_report("rehash_pte: Bad segment size in HPTE"); 578 return H_HARDWARE; 579 } 580 581 new_pteg = hash & new_hash_mask; 582 if (pte0 & HPTE64_V_SECONDARY) { 583 assert(~pteg == (hash & old_hash_mask)); 584 new_pteg = ~new_pteg; 585 } else { 586 assert(pteg == (hash & old_hash_mask)); 587 } 588 assert((oldsize != newsize) || (pteg == new_pteg)); 589 replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 590 /* 591 * Strictly speaking, we don't need all these tests, since we only 592 * ever rehash bolted HPTEs. We might in future handle non-bolted 593 * HPTEs, though so make the logic correct for those cases as 594 * well. 595 */ 596 if (replace_pte0 & HPTE64_V_VALID) { 597 assert(newsize < oldsize); 598 if (replace_pte0 & HPTE64_V_BOLTED) { 599 if (pte0 & HPTE64_V_BOLTED) { 600 /* Bolted collision, nothing we can do */ 601 return H_PTEG_FULL; 602 } else { 603 /* Discard this hpte */ 604 return H_SUCCESS; 605 } 606 } 607 } 608 609 new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 610 return H_SUCCESS; 611 } 612 613 static int rehash_hpt(PowerPCCPU *cpu, 614 void *old_hpt, uint64_t oldsize, 615 void *new_hpt, uint64_t newsize) 616 { 617 uint64_t n_ptegs = oldsize >> 7; 618 uint64_t pteg; 619 int slot; 620 int rc; 621 622 for (pteg = 0; pteg < n_ptegs; pteg++) { 623 hwaddr ptex = pteg * HPTES_PER_GROUP; 624 const ppc_hash_pte64_t *hptes 625 = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 626 627 if (!hptes) { 628 return H_HARDWARE; 629 } 630 631 for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 632 rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 633 pteg, slot); 634 if (rc != H_SUCCESS) { 635 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 636 return rc; 637 } 638 } 639 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 640 } 641 642 return H_SUCCESS; 643 } 644 645 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 646 sPAPRMachineState *spapr, 647 target_ulong opcode, 648 target_ulong *args) 649 { 650 target_ulong flags = args[0]; 651 target_ulong shift = args[1]; 652 sPAPRPendingHPT *pending = spapr->pending_hpt; 653 int rc; 654 size_t newsize; 655 656 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 657 return H_AUTHORITY; 658 } 659 660 trace_spapr_h_resize_hpt_commit(flags, shift); 661 662 if (flags != 0) { 663 return H_PARAMETER; 664 } 665 666 if (!pending || (pending->shift != shift)) { 667 /* no matching prepare */ 668 return H_CLOSED; 669 } 670 671 if (!pending->complete) { 672 /* prepare has not completed */ 673 return H_BUSY; 674 } 675 676 /* Shouldn't have got past PREPARE without an HPT */ 677 g_assert(spapr->htab_shift); 678 679 newsize = 1ULL << pending->shift; 680 rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 681 pending->hpt, newsize); 682 if (rc == H_SUCCESS) { 683 qemu_vfree(spapr->htab); 684 spapr->htab = pending->hpt; 685 spapr->htab_shift = pending->shift; 686 687 pending->hpt = NULL; /* so it's not free()d */ 688 } 689 690 /* Clean up */ 691 spapr->pending_hpt = NULL; 692 free_pending_hpt(pending); 693 694 return rc; 695 } 696 697 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 698 target_ulong opcode, target_ulong *args) 699 { 700 cpu_synchronize_state(CPU(cpu)); 701 cpu->env.spr[SPR_SPRG0] = args[0]; 702 703 return H_SUCCESS; 704 } 705 706 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 707 target_ulong opcode, target_ulong *args) 708 { 709 if (!has_spr(cpu, SPR_DABR)) { 710 return H_HARDWARE; /* DABR register not available */ 711 } 712 cpu_synchronize_state(CPU(cpu)); 713 714 if (has_spr(cpu, SPR_DABRX)) { 715 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 716 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 717 return H_RESERVED_DABR; 718 } 719 720 cpu->env.spr[SPR_DABR] = args[0]; 721 return H_SUCCESS; 722 } 723 724 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 725 target_ulong opcode, target_ulong *args) 726 { 727 target_ulong dabrx = args[1]; 728 729 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 730 return H_HARDWARE; 731 } 732 733 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 734 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 735 return H_PARAMETER; 736 } 737 738 cpu_synchronize_state(CPU(cpu)); 739 cpu->env.spr[SPR_DABRX] = dabrx; 740 cpu->env.spr[SPR_DABR] = args[0]; 741 742 return H_SUCCESS; 743 } 744 745 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 746 target_ulong opcode, target_ulong *args) 747 { 748 target_ulong flags = args[0]; 749 hwaddr dst = args[1]; 750 hwaddr src = args[2]; 751 hwaddr len = TARGET_PAGE_SIZE; 752 uint8_t *pdst, *psrc; 753 target_long ret = H_SUCCESS; 754 755 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 756 | H_COPY_PAGE | H_ZERO_PAGE)) { 757 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 758 flags); 759 return H_PARAMETER; 760 } 761 762 /* Map-in destination */ 763 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 764 return H_PARAMETER; 765 } 766 pdst = cpu_physical_memory_map(dst, &len, 1); 767 if (!pdst || len != TARGET_PAGE_SIZE) { 768 return H_PARAMETER; 769 } 770 771 if (flags & H_COPY_PAGE) { 772 /* Map-in source, copy to destination, and unmap source again */ 773 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 774 ret = H_PARAMETER; 775 goto unmap_out; 776 } 777 psrc = cpu_physical_memory_map(src, &len, 0); 778 if (!psrc || len != TARGET_PAGE_SIZE) { 779 ret = H_PARAMETER; 780 goto unmap_out; 781 } 782 memcpy(pdst, psrc, len); 783 cpu_physical_memory_unmap(psrc, len, 0, len); 784 } else if (flags & H_ZERO_PAGE) { 785 memset(pdst, 0, len); /* Just clear the destination page */ 786 } 787 788 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 789 kvmppc_dcbst_range(cpu, pdst, len); 790 } 791 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 792 if (kvm_enabled()) { 793 kvmppc_icbi_range(cpu, pdst, len); 794 } else { 795 tb_flush(CPU(cpu)); 796 } 797 } 798 799 unmap_out: 800 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 801 return ret; 802 } 803 804 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 805 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 806 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 807 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 808 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 809 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 810 811 #define VPA_MIN_SIZE 640 812 #define VPA_SIZE_OFFSET 0x4 813 #define VPA_SHARED_PROC_OFFSET 0x9 814 #define VPA_SHARED_PROC_VAL 0x2 815 816 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 817 { 818 CPUState *cs = CPU(ppc_env_get_cpu(env)); 819 uint16_t size; 820 uint8_t tmp; 821 822 if (vpa == 0) { 823 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 824 return H_HARDWARE; 825 } 826 827 if (vpa % env->dcache_line_size) { 828 return H_PARAMETER; 829 } 830 /* FIXME: bounds check the address */ 831 832 size = lduw_be_phys(cs->as, vpa + 0x4); 833 834 if (size < VPA_MIN_SIZE) { 835 return H_PARAMETER; 836 } 837 838 /* VPA is not allowed to cross a page boundary */ 839 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 840 return H_PARAMETER; 841 } 842 843 env->vpa_addr = vpa; 844 845 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 846 tmp |= VPA_SHARED_PROC_VAL; 847 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 848 849 return H_SUCCESS; 850 } 851 852 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 853 { 854 if (env->slb_shadow_addr) { 855 return H_RESOURCE; 856 } 857 858 if (env->dtl_addr) { 859 return H_RESOURCE; 860 } 861 862 env->vpa_addr = 0; 863 return H_SUCCESS; 864 } 865 866 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 867 { 868 CPUState *cs = CPU(ppc_env_get_cpu(env)); 869 uint32_t size; 870 871 if (addr == 0) { 872 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 873 return H_HARDWARE; 874 } 875 876 size = ldl_be_phys(cs->as, addr + 0x4); 877 if (size < 0x8) { 878 return H_PARAMETER; 879 } 880 881 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 882 return H_PARAMETER; 883 } 884 885 if (!env->vpa_addr) { 886 return H_RESOURCE; 887 } 888 889 env->slb_shadow_addr = addr; 890 env->slb_shadow_size = size; 891 892 return H_SUCCESS; 893 } 894 895 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 896 { 897 env->slb_shadow_addr = 0; 898 env->slb_shadow_size = 0; 899 return H_SUCCESS; 900 } 901 902 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 903 { 904 CPUState *cs = CPU(ppc_env_get_cpu(env)); 905 uint32_t size; 906 907 if (addr == 0) { 908 hcall_dprintf("Can't cope with DTL at logical 0\n"); 909 return H_HARDWARE; 910 } 911 912 size = ldl_be_phys(cs->as, addr + 0x4); 913 914 if (size < 48) { 915 return H_PARAMETER; 916 } 917 918 if (!env->vpa_addr) { 919 return H_RESOURCE; 920 } 921 922 env->dtl_addr = addr; 923 env->dtl_size = size; 924 925 return H_SUCCESS; 926 } 927 928 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 929 { 930 env->dtl_addr = 0; 931 env->dtl_size = 0; 932 933 return H_SUCCESS; 934 } 935 936 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 937 target_ulong opcode, target_ulong *args) 938 { 939 target_ulong flags = args[0]; 940 target_ulong procno = args[1]; 941 target_ulong vpa = args[2]; 942 target_ulong ret = H_PARAMETER; 943 CPUPPCState *tenv; 944 PowerPCCPU *tcpu; 945 946 tcpu = ppc_get_vcpu_by_dt_id(procno); 947 if (!tcpu) { 948 return H_PARAMETER; 949 } 950 tenv = &tcpu->env; 951 952 switch (flags) { 953 case FLAGS_REGISTER_VPA: 954 ret = register_vpa(tenv, vpa); 955 break; 956 957 case FLAGS_DEREGISTER_VPA: 958 ret = deregister_vpa(tenv, vpa); 959 break; 960 961 case FLAGS_REGISTER_SLBSHADOW: 962 ret = register_slb_shadow(tenv, vpa); 963 break; 964 965 case FLAGS_DEREGISTER_SLBSHADOW: 966 ret = deregister_slb_shadow(tenv, vpa); 967 break; 968 969 case FLAGS_REGISTER_DTL: 970 ret = register_dtl(tenv, vpa); 971 break; 972 973 case FLAGS_DEREGISTER_DTL: 974 ret = deregister_dtl(tenv, vpa); 975 break; 976 } 977 978 return ret; 979 } 980 981 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 982 target_ulong opcode, target_ulong *args) 983 { 984 CPUPPCState *env = &cpu->env; 985 CPUState *cs = CPU(cpu); 986 987 env->msr |= (1ULL << MSR_EE); 988 hreg_compute_hflags(env); 989 if (!cpu_has_work(cs)) { 990 cs->halted = 1; 991 cs->exception_index = EXCP_HLT; 992 cs->exit_request = 1; 993 } 994 return H_SUCCESS; 995 } 996 997 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 998 target_ulong opcode, target_ulong *args) 999 { 1000 target_ulong rtas_r3 = args[0]; 1001 uint32_t token = rtas_ld(rtas_r3, 0); 1002 uint32_t nargs = rtas_ld(rtas_r3, 1); 1003 uint32_t nret = rtas_ld(rtas_r3, 2); 1004 1005 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 1006 nret, rtas_r3 + 12 + 4*nargs); 1007 } 1008 1009 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1010 target_ulong opcode, target_ulong *args) 1011 { 1012 CPUState *cs = CPU(cpu); 1013 target_ulong size = args[0]; 1014 target_ulong addr = args[1]; 1015 1016 switch (size) { 1017 case 1: 1018 args[0] = ldub_phys(cs->as, addr); 1019 return H_SUCCESS; 1020 case 2: 1021 args[0] = lduw_phys(cs->as, addr); 1022 return H_SUCCESS; 1023 case 4: 1024 args[0] = ldl_phys(cs->as, addr); 1025 return H_SUCCESS; 1026 case 8: 1027 args[0] = ldq_phys(cs->as, addr); 1028 return H_SUCCESS; 1029 } 1030 return H_PARAMETER; 1031 } 1032 1033 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1034 target_ulong opcode, target_ulong *args) 1035 { 1036 CPUState *cs = CPU(cpu); 1037 1038 target_ulong size = args[0]; 1039 target_ulong addr = args[1]; 1040 target_ulong val = args[2]; 1041 1042 switch (size) { 1043 case 1: 1044 stb_phys(cs->as, addr, val); 1045 return H_SUCCESS; 1046 case 2: 1047 stw_phys(cs->as, addr, val); 1048 return H_SUCCESS; 1049 case 4: 1050 stl_phys(cs->as, addr, val); 1051 return H_SUCCESS; 1052 case 8: 1053 stq_phys(cs->as, addr, val); 1054 return H_SUCCESS; 1055 } 1056 return H_PARAMETER; 1057 } 1058 1059 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1060 target_ulong opcode, target_ulong *args) 1061 { 1062 CPUState *cs = CPU(cpu); 1063 1064 target_ulong dst = args[0]; /* Destination address */ 1065 target_ulong src = args[1]; /* Source address */ 1066 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 1067 target_ulong count = args[3]; /* Element count */ 1068 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 1069 uint64_t tmp; 1070 unsigned int mask = (1 << esize) - 1; 1071 int step = 1 << esize; 1072 1073 if (count > 0x80000000) { 1074 return H_PARAMETER; 1075 } 1076 1077 if ((dst & mask) || (src & mask) || (op > 1)) { 1078 return H_PARAMETER; 1079 } 1080 1081 if (dst >= src && dst < (src + (count << esize))) { 1082 dst = dst + ((count - 1) << esize); 1083 src = src + ((count - 1) << esize); 1084 step = -step; 1085 } 1086 1087 while (count--) { 1088 switch (esize) { 1089 case 0: 1090 tmp = ldub_phys(cs->as, src); 1091 break; 1092 case 1: 1093 tmp = lduw_phys(cs->as, src); 1094 break; 1095 case 2: 1096 tmp = ldl_phys(cs->as, src); 1097 break; 1098 case 3: 1099 tmp = ldq_phys(cs->as, src); 1100 break; 1101 default: 1102 return H_PARAMETER; 1103 } 1104 if (op == 1) { 1105 tmp = ~tmp; 1106 } 1107 switch (esize) { 1108 case 0: 1109 stb_phys(cs->as, dst, tmp); 1110 break; 1111 case 1: 1112 stw_phys(cs->as, dst, tmp); 1113 break; 1114 case 2: 1115 stl_phys(cs->as, dst, tmp); 1116 break; 1117 case 3: 1118 stq_phys(cs->as, dst, tmp); 1119 break; 1120 } 1121 dst = dst + step; 1122 src = src + step; 1123 } 1124 1125 return H_SUCCESS; 1126 } 1127 1128 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1129 target_ulong opcode, target_ulong *args) 1130 { 1131 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1132 return H_SUCCESS; 1133 } 1134 1135 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1136 target_ulong opcode, target_ulong *args) 1137 { 1138 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1139 return H_SUCCESS; 1140 } 1141 1142 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1143 target_ulong mflags, 1144 target_ulong value1, 1145 target_ulong value2) 1146 { 1147 CPUState *cs; 1148 1149 if (value1) { 1150 return H_P3; 1151 } 1152 if (value2) { 1153 return H_P4; 1154 } 1155 1156 switch (mflags) { 1157 case H_SET_MODE_ENDIAN_BIG: 1158 CPU_FOREACH(cs) { 1159 set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 1160 } 1161 spapr_pci_switch_vga(true); 1162 return H_SUCCESS; 1163 1164 case H_SET_MODE_ENDIAN_LITTLE: 1165 CPU_FOREACH(cs) { 1166 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 1167 } 1168 spapr_pci_switch_vga(false); 1169 return H_SUCCESS; 1170 } 1171 1172 return H_UNSUPPORTED_FLAG; 1173 } 1174 1175 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1176 target_ulong mflags, 1177 target_ulong value1, 1178 target_ulong value2) 1179 { 1180 CPUState *cs; 1181 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1182 1183 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1184 return H_P2; 1185 } 1186 if (value1) { 1187 return H_P3; 1188 } 1189 if (value2) { 1190 return H_P4; 1191 } 1192 1193 if (mflags == AIL_RESERVED) { 1194 return H_UNSUPPORTED_FLAG; 1195 } 1196 1197 CPU_FOREACH(cs) { 1198 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1199 } 1200 1201 return H_SUCCESS; 1202 } 1203 1204 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1205 target_ulong opcode, target_ulong *args) 1206 { 1207 target_ulong resource = args[1]; 1208 target_ulong ret = H_P2; 1209 1210 switch (resource) { 1211 case H_SET_MODE_RESOURCE_LE: 1212 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 1213 break; 1214 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 1215 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1216 args[2], args[3]); 1217 break; 1218 } 1219 1220 return ret; 1221 } 1222 1223 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1224 target_ulong opcode, target_ulong *args) 1225 { 1226 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1227 opcode, " (H_CLEAN_SLB)"); 1228 return H_FUNCTION; 1229 } 1230 1231 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1232 target_ulong opcode, target_ulong *args) 1233 { 1234 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1235 opcode, " (H_INVALIDATE_PID)"); 1236 return H_FUNCTION; 1237 } 1238 1239 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 1240 uint64_t patbe_old, uint64_t patbe_new) 1241 { 1242 /* 1243 * We have 4 Options: 1244 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1245 * HASH->RADIX : Free HPT 1246 * RADIX->HASH : Allocate HPT 1247 * NOTHING->HASH : Allocate HPT 1248 * Note: NOTHING implies the case where we said the guest could choose 1249 * later and so assumed radix and now it's called H_REG_PROC_TBL 1250 */ 1251 1252 if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 1253 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 1254 } else if (!(patbe_old & PATBE1_GR)) { 1255 /* HASH->RADIX : Free HPT */ 1256 spapr_free_hpt(spapr); 1257 } else if (!(patbe_new & PATBE1_GR)) { 1258 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1259 spapr_setup_hpt_and_vrma(spapr); 1260 } 1261 return; 1262 } 1263 1264 #define FLAGS_MASK 0x01FULL 1265 #define FLAG_MODIFY 0x10 1266 #define FLAG_REGISTER 0x08 1267 #define FLAG_RADIX 0x04 1268 #define FLAG_HASH_PROC_TBL 0x02 1269 #define FLAG_GTSE 0x01 1270 1271 static target_ulong h_register_process_table(PowerPCCPU *cpu, 1272 sPAPRMachineState *spapr, 1273 target_ulong opcode, 1274 target_ulong *args) 1275 { 1276 CPUState *cs; 1277 target_ulong flags = args[0]; 1278 target_ulong proc_tbl = args[1]; 1279 target_ulong page_size = args[2]; 1280 target_ulong table_size = args[3]; 1281 uint64_t cproc; 1282 1283 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1284 return H_PARAMETER; 1285 } 1286 if (flags & FLAG_MODIFY) { 1287 if (flags & FLAG_REGISTER) { 1288 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1289 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1290 return H_P2; 1291 } else if (page_size) { 1292 return H_P3; 1293 } else if (table_size > 24) { 1294 return H_P4; 1295 } 1296 cproc = PATBE1_GR | proc_tbl | table_size; 1297 } else { /* Register new HPT process table */ 1298 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1299 /* TODO - Not Supported */ 1300 /* Technically caused by flag bits => H_PARAMETER */ 1301 return H_PARAMETER; 1302 } else { /* Hash with SLB */ 1303 if (proc_tbl >> 38) { 1304 return H_P2; 1305 } else if (page_size & ~0x7) { 1306 return H_P3; 1307 } else if (table_size > 24) { 1308 return H_P4; 1309 } 1310 } 1311 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1312 } 1313 1314 } else { /* Deregister current process table */ 1315 /* Set to benign value: (current GR) | 0. This allows 1316 * deregistration in KVM to succeed even if the radix bit in flags 1317 * doesn't match the radix bit in the old PATB. */ 1318 cproc = spapr->patb_entry & PATBE1_GR; 1319 } 1320 } else { /* Maintain current registration */ 1321 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 1322 /* Technically caused by flag bits => H_PARAMETER */ 1323 return H_PARAMETER; /* Existing Process Table Mismatch */ 1324 } 1325 cproc = spapr->patb_entry; 1326 } 1327 1328 /* Check if we need to setup OR free the hpt */ 1329 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1330 1331 spapr->patb_entry = cproc; /* Save new process table */ 1332 1333 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 1334 CPU_FOREACH(cs) { 1335 set_spr(cs, SPR_LPCR, 1336 ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 1337 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 1338 LPCR_UPRT | LPCR_GTSE); 1339 } 1340 1341 if (kvm_enabled()) { 1342 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1343 flags & FLAG_GTSE, cproc); 1344 } 1345 return H_SUCCESS; 1346 } 1347 1348 #define H_SIGNAL_SYS_RESET_ALL -1 1349 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1350 1351 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1352 sPAPRMachineState *spapr, 1353 target_ulong opcode, target_ulong *args) 1354 { 1355 target_long target = args[0]; 1356 CPUState *cs; 1357 1358 if (target < 0) { 1359 /* Broadcast */ 1360 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1361 return H_PARAMETER; 1362 } 1363 1364 CPU_FOREACH(cs) { 1365 PowerPCCPU *c = POWERPC_CPU(cs); 1366 1367 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1368 if (c == cpu) { 1369 continue; 1370 } 1371 } 1372 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1373 } 1374 return H_SUCCESS; 1375 1376 } else { 1377 /* Unicast */ 1378 CPU_FOREACH(cs) { 1379 if (cpu->cpu_dt_id == target) { 1380 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1381 return H_SUCCESS; 1382 } 1383 } 1384 return H_PARAMETER; 1385 } 1386 } 1387 1388 static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1389 target_ulong *addr, Error **errp) 1390 { 1391 bool explicit_match = false; /* Matched the CPU's real PVR */ 1392 uint32_t max_compat = spapr->max_compat_pvr; 1393 uint32_t best_compat = 0; 1394 int i; 1395 1396 /* 1397 * We scan the supplied table of PVRs looking for two things 1398 * 1. Is our real CPU PVR in the list? 1399 * 2. What's the "best" listed logical PVR 1400 */ 1401 for (i = 0; i < 512; ++i) { 1402 uint32_t pvr, pvr_mask; 1403 1404 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1405 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1406 *addr += 8; 1407 1408 if (~pvr_mask & pvr) { 1409 break; /* Terminator record */ 1410 } 1411 1412 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1413 explicit_match = true; 1414 } else { 1415 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1416 best_compat = pvr; 1417 } 1418 } 1419 } 1420 1421 if ((best_compat == 0) && (!explicit_match || max_compat)) { 1422 /* We couldn't find a suitable compatibility mode, and either 1423 * the guest doesn't support "raw" mode for this CPU, or raw 1424 * mode is disabled because a maximum compat mode is set */ 1425 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 1426 return 0; 1427 } 1428 1429 /* Parsing finished */ 1430 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1431 1432 return best_compat; 1433 } 1434 1435 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1436 sPAPRMachineState *spapr, 1437 target_ulong opcode, 1438 target_ulong *args) 1439 { 1440 /* Working address in data buffer */ 1441 target_ulong addr = ppc64_phys_to_real(args[0]); 1442 target_ulong ov_table; 1443 uint32_t cas_pvr; 1444 sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 1445 bool guest_radix; 1446 Error *local_err = NULL; 1447 1448 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &local_err); 1449 if (local_err) { 1450 error_report_err(local_err); 1451 return H_HARDWARE; 1452 } 1453 1454 /* Update CPUs */ 1455 if (cpu->compat_pvr != cas_pvr) { 1456 ppc_set_compat_all(cas_pvr, &local_err); 1457 if (local_err) { 1458 error_report_err(local_err); 1459 return H_HARDWARE; 1460 } 1461 } 1462 1463 /* For the future use: here @ov_table points to the first option vector */ 1464 ov_table = addr; 1465 1466 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1467 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1468 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1469 error_report("guest requested hash and radix MMU, which is invalid."); 1470 exit(EXIT_FAILURE); 1471 } 1472 /* The radix/hash bit in byte 24 requires special handling: */ 1473 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1474 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 1475 1476 /* NOTE: there are actually a number of ov5 bits where input from the 1477 * guest is always zero, and the platform/QEMU enables them independently 1478 * of guest input. To model these properly we'd want some sort of mask, 1479 * but since they only currently apply to memory migration as defined 1480 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1481 * to worry about this for now. 1482 */ 1483 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1484 /* full range of negotiated ov5 capabilities */ 1485 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1486 spapr_ovec_cleanup(ov5_guest); 1487 /* capabilities that have been added since CAS-generated guest reset. 1488 * if capabilities have since been removed, generate another reset 1489 */ 1490 ov5_updates = spapr_ovec_new(); 1491 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1492 ov5_cas_old, spapr->ov5_cas); 1493 /* Now that processing is finished, set the radix/hash bit for the 1494 * guest if it requested a valid mode; otherwise terminate the boot. */ 1495 if (guest_radix) { 1496 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1497 error_report("Guest requested unavailable MMU mode (radix)."); 1498 exit(EXIT_FAILURE); 1499 } 1500 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 1501 } else { 1502 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1503 && !kvmppc_has_cap_mmu_hash_v3()) { 1504 error_report("Guest requested unavailable MMU mode (hash)."); 1505 exit(EXIT_FAILURE); 1506 } 1507 } 1508 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1509 OV1_PPC_3_00); 1510 if (!spapr->cas_reboot) { 1511 spapr->cas_reboot = 1512 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1513 ov5_updates) != 0); 1514 } 1515 spapr_ovec_cleanup(ov5_updates); 1516 1517 if (spapr->cas_reboot) { 1518 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1519 } else { 1520 /* If ppc_spapr_reset() did not set up a HPT but one is necessary 1521 * (because the guest isn't going to use radix) then set it up here. */ 1522 if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 1523 /* legacy hash or new hash: */ 1524 spapr_setup_hpt_and_vrma(spapr); 1525 } 1526 } 1527 1528 return H_SUCCESS; 1529 } 1530 1531 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1532 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1533 1534 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1535 { 1536 spapr_hcall_fn *slot; 1537 1538 if (opcode <= MAX_HCALL_OPCODE) { 1539 assert((opcode & 0x3) == 0); 1540 1541 slot = &papr_hypercall_table[opcode / 4]; 1542 } else { 1543 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1544 1545 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1546 } 1547 1548 assert(!(*slot)); 1549 *slot = fn; 1550 } 1551 1552 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1553 target_ulong *args) 1554 { 1555 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1556 1557 if ((opcode <= MAX_HCALL_OPCODE) 1558 && ((opcode & 0x3) == 0)) { 1559 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1560 1561 if (fn) { 1562 return fn(cpu, spapr, opcode, args); 1563 } 1564 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1565 (opcode <= KVMPPC_HCALL_MAX)) { 1566 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1567 1568 if (fn) { 1569 return fn(cpu, spapr, opcode, args); 1570 } 1571 } 1572 1573 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1574 opcode); 1575 return H_FUNCTION; 1576 } 1577 1578 static void hypercall_register_types(void) 1579 { 1580 /* hcall-pft */ 1581 spapr_register_hypercall(H_ENTER, h_enter); 1582 spapr_register_hypercall(H_REMOVE, h_remove); 1583 spapr_register_hypercall(H_PROTECT, h_protect); 1584 spapr_register_hypercall(H_READ, h_read); 1585 1586 /* hcall-bulk */ 1587 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1588 1589 /* hcall-hpt-resize */ 1590 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1591 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1592 1593 /* hcall-splpar */ 1594 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1595 spapr_register_hypercall(H_CEDE, h_cede); 1596 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1597 1598 /* processor register resource access h-calls */ 1599 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1600 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1601 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1602 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1603 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1604 1605 /* In Memory Table MMU h-calls */ 1606 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1607 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1608 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1609 1610 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1611 * here between the "CI" and the "CACHE" variants, they will use whatever 1612 * mapping attributes qemu is using. When using KVM, the kernel will 1613 * enforce the attributes more strongly 1614 */ 1615 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1616 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1617 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1618 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1619 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1620 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1621 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1622 1623 /* qemu/KVM-PPC specific hcalls */ 1624 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1625 1626 /* ibm,client-architecture-support support */ 1627 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1628 } 1629 1630 type_init(hypercall_register_types) 1631