1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "hw/cpu/core.h" 10 #include "hw/ppc/spapr_cpu_core.h" 11 #include "target/ppc/cpu.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/boards.h" 14 #include "qapi/error.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/kvm.h" 17 #include "target/ppc/kvm_ppc.h" 18 #include "hw/ppc/ppc.h" 19 #include "target/ppc/mmu-hash64.h" 20 #include "sysemu/numa.h" 21 #include "qemu/error-report.h" 22 23 static void spapr_cpu_reset(void *opaque) 24 { 25 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 26 PowerPCCPU *cpu = opaque; 27 CPUState *cs = CPU(cpu); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_reset(cs); 31 32 /* All CPUs start halted. CPU0 is unhalted from the machine level 33 * reset code and the rest are explicitly started up by the guest 34 * using an RTAS call */ 35 cs->halted = 1; 36 37 env->spr[SPR_HIOR] = 0; 38 39 /* 40 * This is a hack for the benefit of KVM PR - it abuses the SDR1 41 * slot in kvm_sregs to communicate the userspace address of the 42 * HPT 43 */ 44 if (kvm_enabled()) { 45 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab 46 | (spapr->htab_shift - 18); 47 if (kvmppc_put_books_sregs(cpu) < 0) { 48 error_report("Unable to update SDR1 in KVM"); 49 exit(1); 50 } 51 } 52 } 53 54 static void spapr_cpu_destroy(PowerPCCPU *cpu) 55 { 56 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 57 58 xics_cpu_destroy(XICS_FABRIC(spapr), cpu); 59 qemu_unregister_reset(spapr_cpu_reset, cpu); 60 } 61 62 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 63 Error **errp) 64 { 65 CPUPPCState *env = &cpu->env; 66 CPUState *cs = CPU(cpu); 67 int i; 68 69 /* Set time-base frequency to 512 MHz */ 70 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 71 72 /* Enable PAPR mode in TCG or KVM */ 73 cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 74 75 if (cpu->max_compat) { 76 Error *local_err = NULL; 77 78 ppc_set_compat(cpu, cpu->max_compat, &local_err); 79 if (local_err) { 80 error_propagate(errp, local_err); 81 return; 82 } 83 } 84 85 /* Set NUMA node for the added CPUs */ 86 i = numa_get_node_for_cpu(cs->cpu_index); 87 if (i < nb_numa_nodes) { 88 cs->numa_node = i; 89 } 90 91 xics_cpu_setup(XICS_FABRIC(spapr), cpu); 92 93 qemu_register_reset(spapr_cpu_reset, cpu); 94 spapr_cpu_reset(cpu); 95 } 96 97 /* 98 * Return the sPAPR CPU core type for @model which essentially is the CPU 99 * model specified with -cpu cmdline option. 100 */ 101 char *spapr_get_cpu_core_type(const char *model) 102 { 103 char *core_type; 104 gchar **model_pieces = g_strsplit(model, ",", 2); 105 106 core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE); 107 108 /* Check whether it exists or whether we have to look up an alias name */ 109 if (!object_class_by_name(core_type)) { 110 const char *realmodel; 111 112 g_free(core_type); 113 core_type = NULL; 114 realmodel = ppc_cpu_lookup_alias(model_pieces[0]); 115 if (realmodel) { 116 core_type = spapr_get_cpu_core_type(realmodel); 117 } 118 } 119 120 g_strfreev(model_pieces); 121 return core_type; 122 } 123 124 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) 125 { 126 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 127 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 128 const char *typename = object_class_get_name(scc->cpu_class); 129 size_t size = object_type_get_instance_size(typename); 130 CPUCore *cc = CPU_CORE(dev); 131 int i; 132 133 for (i = 0; i < cc->nr_threads; i++) { 134 void *obj = sc->threads + i * size; 135 DeviceState *dev = DEVICE(obj); 136 CPUState *cs = CPU(dev); 137 PowerPCCPU *cpu = POWERPC_CPU(cs); 138 139 spapr_cpu_destroy(cpu); 140 cpu_remove_sync(cs); 141 object_unparent(obj); 142 } 143 g_free(sc->threads); 144 } 145 146 static void spapr_cpu_core_realize_child(Object *child, Error **errp) 147 { 148 Error *local_err = NULL; 149 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 150 CPUState *cs = CPU(child); 151 PowerPCCPU *cpu = POWERPC_CPU(cs); 152 153 object_property_set_bool(child, true, "realized", &local_err); 154 if (local_err) { 155 error_propagate(errp, local_err); 156 return; 157 } 158 159 spapr_cpu_init(spapr, cpu, &local_err); 160 if (local_err) { 161 error_propagate(errp, local_err); 162 return; 163 } 164 } 165 166 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 167 { 168 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 169 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 170 CPUCore *cc = CPU_CORE(OBJECT(dev)); 171 const char *typename = object_class_get_name(scc->cpu_class); 172 size_t size = object_type_get_instance_size(typename); 173 Error *local_err = NULL; 174 void *obj; 175 int i, j; 176 177 sc->threads = g_malloc0(size * cc->nr_threads); 178 for (i = 0; i < cc->nr_threads; i++) { 179 char id[32]; 180 CPUState *cs; 181 182 obj = sc->threads + i * size; 183 184 object_initialize(obj, size, typename); 185 cs = CPU(obj); 186 cs->cpu_index = cc->core_id + i; 187 snprintf(id, sizeof(id), "thread[%d]", i); 188 object_property_add_child(OBJECT(sc), id, obj, &local_err); 189 if (local_err) { 190 goto err; 191 } 192 object_unref(obj); 193 } 194 195 for (j = 0; j < cc->nr_threads; j++) { 196 obj = sc->threads + j * size; 197 198 spapr_cpu_core_realize_child(obj, &local_err); 199 if (local_err) { 200 goto err; 201 } 202 } 203 return; 204 205 err: 206 while (--i >= 0) { 207 obj = sc->threads + i * size; 208 object_unparent(obj); 209 } 210 g_free(sc->threads); 211 error_propagate(errp, local_err); 212 } 213 214 static const char *spapr_core_models[] = { 215 /* 970 */ 216 "970_v2.2", 217 218 /* 970MP variants */ 219 "970MP_v1.0", 220 "970mp_v1.0", 221 "970MP_v1.1", 222 "970mp_v1.1", 223 224 /* POWER5+ */ 225 "POWER5+_v2.1", 226 227 /* POWER7 */ 228 "POWER7_v2.3", 229 230 /* POWER7+ */ 231 "POWER7+_v2.1", 232 233 /* POWER8 */ 234 "POWER8_v2.0", 235 236 /* POWER8E */ 237 "POWER8E_v2.1", 238 239 /* POWER8NVL */ 240 "POWER8NVL_v1.0", 241 }; 242 243 void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 244 { 245 DeviceClass *dc = DEVICE_CLASS(oc); 246 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 247 248 dc->realize = spapr_cpu_core_realize; 249 dc->unrealize = spapr_cpu_core_unrealizefn; 250 scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data); 251 g_assert(scc->cpu_class); 252 } 253 254 static const TypeInfo spapr_cpu_core_type_info = { 255 .name = TYPE_SPAPR_CPU_CORE, 256 .parent = TYPE_CPU_CORE, 257 .abstract = true, 258 .instance_size = sizeof(sPAPRCPUCore), 259 .class_size = sizeof(sPAPRCPUCoreClass), 260 }; 261 262 static void spapr_cpu_core_register_types(void) 263 { 264 int i; 265 266 type_register_static(&spapr_cpu_core_type_info); 267 268 for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) { 269 TypeInfo type_info = { 270 .parent = TYPE_SPAPR_CPU_CORE, 271 .instance_size = sizeof(sPAPRCPUCore), 272 .class_init = spapr_cpu_core_class_init, 273 .class_data = (void *) spapr_core_models[i], 274 }; 275 276 type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, 277 spapr_core_models[i]); 278 type_register(&type_info); 279 g_free((void *)type_info.name); 280 } 281 } 282 283 type_init(spapr_cpu_core_register_types) 284