1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/qapi-events-qdev.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hostmem.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "qemu/log.h" 41 #include "hw/fw-path-provider.h" 42 #include "elf.h" 43 #include "net/net.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/cpus.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_ppc.h" 48 #include "migration/misc.h" 49 #include "migration/qemu-file-types.h" 50 #include "migration/global_state.h" 51 #include "migration/register.h" 52 #include "migration/blocker.h" 53 #include "mmu-hash64.h" 54 #include "mmu-book3s-v3.h" 55 #include "cpu-models.h" 56 #include "hw/core/cpu.h" 57 58 #include "hw/ppc/ppc.h" 59 #include "hw/loader.h" 60 61 #include "hw/ppc/fdt.h" 62 #include "hw/ppc/spapr.h" 63 #include "hw/ppc/spapr_vio.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/pci-host/spapr.h" 66 #include "hw/pci/msi.h" 67 68 #include "hw/pci/pci.h" 69 #include "hw/scsi/scsi.h" 70 #include "hw/virtio/virtio-scsi.h" 71 #include "hw/virtio/vhost-scsi-common.h" 72 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_FILE_NAME_VOF "vof.bin" 106 #define FW_OVERHEAD 0x2800000 107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 108 109 #define MIN_RMA_SLOF (128 * MiB) 110 111 #define PHANDLE_INTC 0x00001111 112 113 /* These two functions implement the VCPU id numbering: one to compute them 114 * all and one to identify thread 0 of a VCORE. Any change to the first one 115 * is likely to have an impact on the second one, so let's keep them close. 116 */ 117 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 118 { 119 MachineState *ms = MACHINE(spapr); 120 unsigned int smp_threads = ms->smp.threads; 121 122 assert(spapr->vsmt); 123 return 124 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 125 } 126 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 127 PowerPCCPU *cpu) 128 { 129 assert(spapr->vsmt); 130 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 131 } 132 133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 134 { 135 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 136 * and newer QEMUs don't even have them. In both cases, we don't want 137 * to send anything on the wire. 138 */ 139 return false; 140 } 141 142 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 143 .name = "icp/server", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .needed = pre_2_10_vmstate_dummy_icp_needed, 147 .fields = (VMStateField[]) { 148 VMSTATE_UNUSED(4), /* uint32_t xirr */ 149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 150 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 151 VMSTATE_END_OF_LIST() 152 }, 153 }; 154 155 static void pre_2_10_vmstate_register_dummy_icp(int i) 156 { 157 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 158 (void *)(uintptr_t) i); 159 } 160 161 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 162 { 163 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 164 (void *)(uintptr_t) i); 165 } 166 167 int spapr_max_server_number(SpaprMachineState *spapr) 168 { 169 MachineState *ms = MACHINE(spapr); 170 171 assert(spapr->vsmt); 172 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 173 } 174 175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 176 int smt_threads) 177 { 178 int i, ret = 0; 179 uint32_t servers_prop[smt_threads]; 180 uint32_t gservers_prop[smt_threads * 2]; 181 int index = spapr_get_vcpu_id(cpu); 182 183 if (cpu->compat_pvr) { 184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 185 if (ret < 0) { 186 return ret; 187 } 188 } 189 190 /* Build interrupt servers and gservers properties */ 191 for (i = 0; i < smt_threads; i++) { 192 servers_prop[i] = cpu_to_be32(index + i); 193 /* Hack, direct the group queues back to cpu 0 */ 194 gservers_prop[i*2] = cpu_to_be32(index + i); 195 gservers_prop[i*2 + 1] = 0; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 198 servers_prop, sizeof(servers_prop)); 199 if (ret < 0) { 200 return ret; 201 } 202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 203 gservers_prop, sizeof(gservers_prop)); 204 205 return ret; 206 } 207 208 static void spapr_dt_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static hwaddr spapr_node0_size(MachineState *machine) 287 { 288 if (machine->numa_state->num_nodes) { 289 int i; 290 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 291 if (machine->numa_state->nodes[i].node_mem) { 292 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 293 machine->ram_size); 294 } 295 } 296 } 297 return machine->ram_size; 298 } 299 300 static void add_str(GString *s, const gchar *s1) 301 { 302 g_string_append_len(s, s1, strlen(s1) + 1); 303 } 304 305 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 306 hwaddr start, hwaddr size) 307 { 308 char mem_name[32]; 309 uint64_t mem_reg_property[2]; 310 int off; 311 312 mem_reg_property[0] = cpu_to_be64(start); 313 mem_reg_property[1] = cpu_to_be64(size); 314 315 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 316 off = fdt_add_subnode(fdt, 0, mem_name); 317 _FDT(off); 318 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 319 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 320 sizeof(mem_reg_property)))); 321 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 322 return off; 323 } 324 325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 326 { 327 MemoryDeviceInfoList *info; 328 329 for (info = list; info; info = info->next) { 330 MemoryDeviceInfo *value = info->value; 331 332 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 333 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 334 335 if (addr >= pcdimm_info->addr && 336 addr < (pcdimm_info->addr + pcdimm_info->size)) { 337 return pcdimm_info->node; 338 } 339 } 340 } 341 342 return -1; 343 } 344 345 struct sPAPRDrconfCellV2 { 346 uint32_t seq_lmbs; 347 uint64_t base_addr; 348 uint32_t drc_index; 349 uint32_t aa_index; 350 uint32_t flags; 351 } QEMU_PACKED; 352 353 typedef struct DrconfCellQueue { 354 struct sPAPRDrconfCellV2 cell; 355 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 356 } DrconfCellQueue; 357 358 static DrconfCellQueue * 359 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 360 uint32_t drc_index, uint32_t aa_index, 361 uint32_t flags) 362 { 363 DrconfCellQueue *elem; 364 365 elem = g_malloc0(sizeof(*elem)); 366 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 367 elem->cell.base_addr = cpu_to_be64(base_addr); 368 elem->cell.drc_index = cpu_to_be32(drc_index); 369 elem->cell.aa_index = cpu_to_be32(aa_index); 370 elem->cell.flags = cpu_to_be32(flags); 371 372 return elem; 373 } 374 375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 376 int offset, MemoryDeviceInfoList *dimms) 377 { 378 MachineState *machine = MACHINE(spapr); 379 uint8_t *int_buf, *cur_index; 380 int ret; 381 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 382 uint64_t addr, cur_addr, size; 383 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 384 uint64_t mem_end = machine->device_memory->base + 385 memory_region_size(&machine->device_memory->mr); 386 uint32_t node, buf_len, nr_entries = 0; 387 SpaprDrc *drc; 388 DrconfCellQueue *elem, *next; 389 MemoryDeviceInfoList *info; 390 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 392 393 /* Entry to cover RAM and the gap area */ 394 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 395 SPAPR_LMB_FLAGS_RESERVED | 396 SPAPR_LMB_FLAGS_DRC_INVALID); 397 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 398 nr_entries++; 399 400 cur_addr = machine->device_memory->base; 401 for (info = dimms; info; info = info->next) { 402 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 403 404 addr = di->addr; 405 size = di->size; 406 node = di->node; 407 408 /* 409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 410 * area is marked hotpluggable in the next iteration for the bigger 411 * chunk including the NVDIMM occupied area. 412 */ 413 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 414 continue; 415 416 /* Entry for hot-pluggable area */ 417 if (cur_addr < addr) { 418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 419 g_assert(drc); 420 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 421 cur_addr, spapr_drc_index(drc), -1, 0); 422 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 423 nr_entries++; 424 } 425 426 /* Entry for DIMM */ 427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 428 g_assert(drc); 429 elem = spapr_get_drconf_cell(size / lmb_size, addr, 430 spapr_drc_index(drc), node, 431 (SPAPR_LMB_FLAGS_ASSIGNED | 432 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 433 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 434 nr_entries++; 435 cur_addr = addr + size; 436 } 437 438 /* Entry for remaining hotpluggable area */ 439 if (cur_addr < mem_end) { 440 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 441 g_assert(drc); 442 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 443 cur_addr, spapr_drc_index(drc), -1, 0); 444 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 445 nr_entries++; 446 } 447 448 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 449 int_buf = cur_index = g_malloc0(buf_len); 450 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 451 cur_index += sizeof(nr_entries); 452 453 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 454 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 455 cur_index += sizeof(elem->cell); 456 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 457 g_free(elem); 458 } 459 460 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 461 g_free(int_buf); 462 if (ret < 0) { 463 return -1; 464 } 465 return 0; 466 } 467 468 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 469 int offset, MemoryDeviceInfoList *dimms) 470 { 471 MachineState *machine = MACHINE(spapr); 472 int i, ret; 473 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 474 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 475 uint32_t nr_lmbs = (machine->device_memory->base + 476 memory_region_size(&machine->device_memory->mr)) / 477 lmb_size; 478 uint32_t *int_buf, *cur_index, buf_len; 479 480 /* 481 * Allocate enough buffer size to fit in ibm,dynamic-memory 482 */ 483 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 484 cur_index = int_buf = g_malloc0(buf_len); 485 int_buf[0] = cpu_to_be32(nr_lmbs); 486 cur_index++; 487 for (i = 0; i < nr_lmbs; i++) { 488 uint64_t addr = i * lmb_size; 489 uint32_t *dynamic_memory = cur_index; 490 491 if (i >= device_lmb_start) { 492 SpaprDrc *drc; 493 494 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 495 g_assert(drc); 496 497 dynamic_memory[0] = cpu_to_be32(addr >> 32); 498 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 499 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 500 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 501 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 502 if (memory_region_present(get_system_memory(), addr)) { 503 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 504 } else { 505 dynamic_memory[5] = cpu_to_be32(0); 506 } 507 } else { 508 /* 509 * LMB information for RMA, boot time RAM and gap b/n RAM and 510 * device memory region -- all these are marked as reserved 511 * and as having no valid DRC. 512 */ 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(0); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(-1); 518 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 519 SPAPR_LMB_FLAGS_DRC_INVALID); 520 } 521 522 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 523 } 524 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 525 g_free(int_buf); 526 if (ret < 0) { 527 return -1; 528 } 529 return 0; 530 } 531 532 /* 533 * Adds ibm,dynamic-reconfiguration-memory node. 534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 535 * of this device tree node. 536 */ 537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 538 void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int ret, offset; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 544 cpu_to_be32(lmb_size & 0xffffffff)}; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 586 587 return ret; 588 } 589 590 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 591 { 592 MachineState *machine = MACHINE(spapr); 593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 594 hwaddr mem_start, node_size; 595 int i, nb_nodes = machine->numa_state->num_nodes; 596 NodeInfo *nodes = machine->numa_state->nodes; 597 598 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 599 if (!nodes[i].node_mem) { 600 continue; 601 } 602 if (mem_start >= machine->ram_size) { 603 node_size = 0; 604 } else { 605 node_size = nodes[i].node_mem; 606 if (node_size > machine->ram_size - mem_start) { 607 node_size = machine->ram_size - mem_start; 608 } 609 } 610 if (!mem_start) { 611 /* spapr_machine_init() checks for rma_size <= node0_size 612 * already */ 613 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 614 mem_start += spapr->rma_size; 615 node_size -= spapr->rma_size; 616 } 617 for ( ; node_size; ) { 618 hwaddr sizetmp = pow2floor(node_size); 619 620 /* mem_start != 0 here */ 621 if (ctzl(mem_start) < ctzl(sizetmp)) { 622 sizetmp = 1ULL << ctzl(mem_start); 623 } 624 625 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 626 node_size -= sizetmp; 627 mem_start += sizetmp; 628 } 629 } 630 631 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 632 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 633 int ret; 634 635 g_assert(smc->dr_lmb_enabled); 636 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 637 if (ret) { 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 646 SpaprMachineState *spapr) 647 { 648 MachineState *ms = MACHINE(spapr); 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 CPUPPCState *env = &cpu->env; 651 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 652 int index = spapr_get_vcpu_id(cpu); 653 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 654 0xffffffff, 0xffffffff}; 655 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 656 : SPAPR_TIMEBASE_FREQ; 657 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 658 uint32_t page_sizes_prop[64]; 659 size_t page_sizes_prop_size; 660 unsigned int smp_threads = ms->smp.threads; 661 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 662 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 663 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 664 SpaprDrc *drc; 665 int drc_index; 666 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 667 int i; 668 669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 670 if (drc) { 671 drc_index = spapr_drc_index(drc); 672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 673 } 674 675 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 676 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 677 678 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 682 env->dcache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 684 env->icache_line_size))); 685 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 686 env->icache_line_size))); 687 688 if (pcc->l1_dcache_size) { 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 690 pcc->l1_dcache_size))); 691 } else { 692 warn_report("Unknown L1 dcache size for cpu"); 693 } 694 if (pcc->l1_icache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 696 pcc->l1_icache_size))); 697 } else { 698 warn_report("Unknown L1 icache size for cpu"); 699 } 700 701 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 706 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 707 708 if (ppc_has_spr(cpu, SPR_PURR)) { 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 710 } 711 if (ppc_has_spr(cpu, SPR_PURR)) { 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 713 } 714 715 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 716 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 717 segs, sizeof(segs)))); 718 } 719 720 /* Advertise VSX (vector extensions) if available 721 * 1 == VMX / Altivec available 722 * 2 == VSX available 723 * 724 * Only CPUs for which we create core types in spapr_cpu_core.c 725 * are possible, and all of those have VMX */ 726 if (env->insns_flags & PPC_ALTIVEC) { 727 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 728 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 729 } else { 730 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 731 } 732 } 733 734 /* Advertise DFP (Decimal Floating Point) if available 735 * 0 / no property == no DFP 736 * 1 == DFP available */ 737 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 738 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 739 } 740 741 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 742 sizeof(page_sizes_prop)); 743 if (page_sizes_prop_size) { 744 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 745 page_sizes_prop, page_sizes_prop_size))); 746 } 747 748 spapr_dt_pa_features(spapr, cpu, fdt, offset); 749 750 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 751 cs->cpu_index / vcpus_per_socket))); 752 753 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 754 pft_size_prop, sizeof(pft_size_prop)))); 755 756 if (ms->numa_state->num_nodes > 1) { 757 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 758 } 759 760 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 761 762 if (pcc->radix_page_info) { 763 for (i = 0; i < pcc->radix_page_info->count; i++) { 764 radix_AP_encodings[i] = 765 cpu_to_be32(pcc->radix_page_info->entries[i]); 766 } 767 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 768 radix_AP_encodings, 769 pcc->radix_page_info->count * 770 sizeof(radix_AP_encodings[0])))); 771 } 772 773 /* 774 * We set this property to let the guest know that it can use the large 775 * decrementer and its width in bits. 776 */ 777 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 778 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 779 pcc->lrg_decr_bits))); 780 } 781 782 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 783 { 784 CPUState **rev; 785 CPUState *cs; 786 int n_cpus; 787 int cpus_offset; 788 int i; 789 790 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 791 _FDT(cpus_offset); 792 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 793 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 794 795 /* 796 * We walk the CPUs in reverse order to ensure that CPU DT nodes 797 * created by fdt_add_subnode() end up in the right order in FDT 798 * for the guest kernel the enumerate the CPUs correctly. 799 * 800 * The CPU list cannot be traversed in reverse order, so we need 801 * to do extra work. 802 */ 803 n_cpus = 0; 804 rev = NULL; 805 CPU_FOREACH(cs) { 806 rev = g_renew(CPUState *, rev, n_cpus + 1); 807 rev[n_cpus++] = cs; 808 } 809 810 for (i = n_cpus - 1; i >= 0; i--) { 811 CPUState *cs = rev[i]; 812 PowerPCCPU *cpu = POWERPC_CPU(cs); 813 int index = spapr_get_vcpu_id(cpu); 814 DeviceClass *dc = DEVICE_GET_CLASS(cs); 815 g_autofree char *nodename = NULL; 816 int offset; 817 818 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 819 continue; 820 } 821 822 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 823 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 824 _FDT(offset); 825 spapr_dt_cpu(cs, fdt, offset, spapr); 826 } 827 828 g_free(rev); 829 } 830 831 static int spapr_dt_rng(void *fdt) 832 { 833 int node; 834 int ret; 835 836 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 837 if (node <= 0) { 838 return -1; 839 } 840 ret = fdt_setprop_string(fdt, node, "device_type", 841 "ibm,platform-facilities"); 842 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 843 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 844 845 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 846 if (node <= 0) { 847 return -1; 848 } 849 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 850 851 return ret ? -1 : 0; 852 } 853 854 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 855 { 856 MachineState *ms = MACHINE(spapr); 857 int rtas; 858 GString *hypertas = g_string_sized_new(256); 859 GString *qemu_hypertas = g_string_sized_new(256); 860 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 861 memory_region_size(&MACHINE(spapr)->device_memory->mr); 862 uint32_t lrdr_capacity[] = { 863 cpu_to_be32(max_device_addr >> 32), 864 cpu_to_be32(max_device_addr & 0xffffffff), 865 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 866 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 867 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 868 }; 869 870 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 871 872 /* hypertas */ 873 add_str(hypertas, "hcall-pft"); 874 add_str(hypertas, "hcall-term"); 875 add_str(hypertas, "hcall-dabr"); 876 add_str(hypertas, "hcall-interrupt"); 877 add_str(hypertas, "hcall-tce"); 878 add_str(hypertas, "hcall-vio"); 879 add_str(hypertas, "hcall-splpar"); 880 add_str(hypertas, "hcall-join"); 881 add_str(hypertas, "hcall-bulk"); 882 add_str(hypertas, "hcall-set-mode"); 883 add_str(hypertas, "hcall-sprg0"); 884 add_str(hypertas, "hcall-copy"); 885 add_str(hypertas, "hcall-debug"); 886 add_str(hypertas, "hcall-vphn"); 887 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 888 add_str(hypertas, "hcall-rpt-invalidate"); 889 } 890 891 add_str(qemu_hypertas, "hcall-memop1"); 892 893 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 894 add_str(hypertas, "hcall-multi-tce"); 895 } 896 897 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 898 add_str(hypertas, "hcall-hpt-resize"); 899 } 900 901 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 902 hypertas->str, hypertas->len)); 903 g_string_free(hypertas, TRUE); 904 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 905 qemu_hypertas->str, qemu_hypertas->len)); 906 g_string_free(qemu_hypertas, TRUE); 907 908 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 909 910 /* 911 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 912 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 913 * 914 * The system reset requirements are driven by existing Linux and PowerVM 915 * implementation which (contrary to PAPR) saves r3 in the error log 916 * structure like machine check, so Linux expects to find the saved r3 917 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 918 * does not look at the error value). 919 * 920 * System reset interrupts are not subject to interlock like machine 921 * check, so this memory area could be corrupted if the sreset is 922 * interrupted by a machine check (or vice versa) if it was shared. To 923 * prevent this, system reset uses per-CPU areas for the sreset save 924 * area. A system reset that interrupts a system reset handler could 925 * still overwrite this area, but Linux doesn't try to recover in that 926 * case anyway. 927 * 928 * The extra 8 bytes is required because Linux's FWNMI error log check 929 * is off-by-one. 930 * 931 * RTAS_MIN_SIZE is required for the RTAS blob itself. 932 */ 933 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 934 RTAS_ERROR_LOG_MAX + 935 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 936 sizeof(uint64_t))); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 938 RTAS_ERROR_LOG_MAX)); 939 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 940 RTAS_EVENT_SCAN_RATE)); 941 942 g_assert(msi_nonbroken); 943 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 944 945 /* 946 * According to PAPR, rtas ibm,os-term does not guarantee a return 947 * back to the guest cpu. 948 * 949 * While an additional ibm,extended-os-term property indicates 950 * that rtas call return will always occur. Set this property. 951 */ 952 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 953 954 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 955 lrdr_capacity, sizeof(lrdr_capacity))); 956 957 spapr_dt_rtas_tokens(fdt, rtas); 958 } 959 960 /* 961 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 962 * and the XIVE features that the guest may request and thus the valid 963 * values for bytes 23..26 of option vector 5: 964 */ 965 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 966 int chosen) 967 { 968 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 969 970 char val[2 * 4] = { 971 23, 0x00, /* XICS / XIVE mode */ 972 24, 0x00, /* Hash/Radix, filled in below. */ 973 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 974 26, 0x40, /* Radix options: GTSE == yes. */ 975 }; 976 977 if (spapr->irq->xics && spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_BOTH; 979 } else if (spapr->irq->xive) { 980 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 981 } else { 982 assert(spapr->irq->xics); 983 val[1] = SPAPR_OV5_XIVE_LEGACY; 984 } 985 986 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 987 first_ppc_cpu->compat_pvr)) { 988 /* 989 * If we're in a pre POWER9 compat mode then the guest should 990 * do hash and use the legacy interrupt mode 991 */ 992 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 993 val[3] = 0x00; /* Hash */ 994 spapr_check_mmu_mode(false); 995 } else if (kvm_enabled()) { 996 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 997 val[3] = 0x80; /* OV5_MMU_BOTH */ 998 } else if (kvmppc_has_cap_mmu_radix()) { 999 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1000 } else { 1001 val[3] = 0x00; /* Hash */ 1002 } 1003 } else { 1004 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1005 val[3] = 0xC0; 1006 } 1007 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1008 val, sizeof(val))); 1009 } 1010 1011 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1012 { 1013 MachineState *machine = MACHINE(spapr); 1014 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1015 int chosen; 1016 1017 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1018 1019 if (reset) { 1020 const char *boot_device = spapr->boot_device; 1021 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1022 size_t cb = 0; 1023 char *bootlist = get_boot_devices_list(&cb); 1024 1025 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1026 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1027 machine->kernel_cmdline)); 1028 } 1029 1030 if (spapr->initrd_size) { 1031 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1032 spapr->initrd_base)); 1033 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1034 spapr->initrd_base + spapr->initrd_size)); 1035 } 1036 1037 if (spapr->kernel_size) { 1038 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1039 cpu_to_be64(spapr->kernel_size) }; 1040 1041 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1042 &kprop, sizeof(kprop))); 1043 if (spapr->kernel_le) { 1044 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1045 } 1046 } 1047 if (boot_menu) { 1048 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1049 } 1050 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1051 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1052 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1053 1054 if (cb && bootlist) { 1055 int i; 1056 1057 for (i = 0; i < cb; i++) { 1058 if (bootlist[i] == '\n') { 1059 bootlist[i] = ' '; 1060 } 1061 } 1062 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1063 } 1064 1065 if (boot_device && strlen(boot_device)) { 1066 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1067 } 1068 1069 if (!spapr->has_graphics && stdout_path) { 1070 /* 1071 * "linux,stdout-path" and "stdout" properties are 1072 * deprecated by linux kernel. New platforms should only 1073 * use the "stdout-path" property. Set the new property 1074 * and continue using older property to remain compatible 1075 * with the existing firmware. 1076 */ 1077 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1078 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1079 } 1080 1081 /* 1082 * We can deal with BAR reallocation just fine, advertise it 1083 * to the guest 1084 */ 1085 if (smc->linux_pci_probe) { 1086 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1087 } 1088 1089 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1090 1091 g_free(stdout_path); 1092 g_free(bootlist); 1093 } 1094 1095 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1096 } 1097 1098 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1099 { 1100 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1101 * KVM to work under pHyp with some guest co-operation */ 1102 int hypervisor; 1103 uint8_t hypercall[16]; 1104 1105 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1106 /* indicate KVM hypercall interface */ 1107 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1108 if (kvmppc_has_cap_fixup_hcalls()) { 1109 /* 1110 * Older KVM versions with older guest kernels were broken 1111 * with the magic page, don't allow the guest to map it. 1112 */ 1113 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1114 sizeof(hypercall))) { 1115 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1116 hypercall, sizeof(hypercall))); 1117 } 1118 } 1119 } 1120 1121 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1122 { 1123 MachineState *machine = MACHINE(spapr); 1124 MachineClass *mc = MACHINE_GET_CLASS(machine); 1125 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1126 uint32_t root_drc_type_mask = 0; 1127 int ret; 1128 void *fdt; 1129 SpaprPhbState *phb; 1130 char *buf; 1131 1132 fdt = g_malloc0(space); 1133 _FDT((fdt_create_empty_tree(fdt, space))); 1134 1135 /* Root node */ 1136 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1137 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1138 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1139 1140 /* Guest UUID & Name*/ 1141 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1142 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1143 if (qemu_uuid_set) { 1144 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1145 } 1146 g_free(buf); 1147 1148 if (qemu_get_vm_name()) { 1149 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1150 qemu_get_vm_name())); 1151 } 1152 1153 /* Host Model & Serial Number */ 1154 if (spapr->host_model) { 1155 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1156 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1157 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1158 g_free(buf); 1159 } 1160 1161 if (spapr->host_serial) { 1162 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1163 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1164 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1165 g_free(buf); 1166 } 1167 1168 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1169 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1170 1171 /* /interrupt controller */ 1172 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1173 1174 ret = spapr_dt_memory(spapr, fdt); 1175 if (ret < 0) { 1176 error_report("couldn't setup memory nodes in fdt"); 1177 exit(1); 1178 } 1179 1180 /* /vdevice */ 1181 spapr_dt_vdevice(spapr->vio_bus, fdt); 1182 1183 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1184 ret = spapr_dt_rng(fdt); 1185 if (ret < 0) { 1186 error_report("could not set up rng device in the fdt"); 1187 exit(1); 1188 } 1189 } 1190 1191 QLIST_FOREACH(phb, &spapr->phbs, list) { 1192 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1193 if (ret < 0) { 1194 error_report("couldn't setup PCI devices in fdt"); 1195 exit(1); 1196 } 1197 } 1198 1199 spapr_dt_cpus(fdt, spapr); 1200 1201 /* ibm,drc-indexes and friends */ 1202 if (smc->dr_lmb_enabled) { 1203 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1204 } 1205 if (smc->dr_phb_enabled) { 1206 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1207 } 1208 if (mc->nvdimm_supported) { 1209 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1210 } 1211 if (root_drc_type_mask) { 1212 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1213 } 1214 1215 if (mc->has_hotpluggable_cpus) { 1216 int offset = fdt_path_offset(fdt, "/cpus"); 1217 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1218 if (ret < 0) { 1219 error_report("Couldn't set up CPU DR device tree properties"); 1220 exit(1); 1221 } 1222 } 1223 1224 /* /event-sources */ 1225 spapr_dt_events(spapr, fdt); 1226 1227 /* /rtas */ 1228 spapr_dt_rtas(spapr, fdt); 1229 1230 /* /chosen */ 1231 spapr_dt_chosen(spapr, fdt, reset); 1232 1233 /* /hypervisor */ 1234 if (kvm_enabled()) { 1235 spapr_dt_hypervisor(spapr, fdt); 1236 } 1237 1238 /* Build memory reserve map */ 1239 if (reset) { 1240 if (spapr->kernel_size) { 1241 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1242 spapr->kernel_size))); 1243 } 1244 if (spapr->initrd_size) { 1245 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1246 spapr->initrd_size))); 1247 } 1248 } 1249 1250 /* NVDIMM devices */ 1251 if (mc->nvdimm_supported) { 1252 spapr_dt_persistent_memory(spapr, fdt); 1253 } 1254 1255 return fdt; 1256 } 1257 1258 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1259 { 1260 SpaprMachineState *spapr = opaque; 1261 1262 return (addr & 0x0fffffff) + spapr->kernel_addr; 1263 } 1264 1265 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1266 PowerPCCPU *cpu) 1267 { 1268 CPUPPCState *env = &cpu->env; 1269 1270 /* The TCG path should also be holding the BQL at this point */ 1271 g_assert(qemu_mutex_iothread_locked()); 1272 1273 if (msr_pr) { 1274 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1275 env->gpr[3] = H_PRIVILEGE; 1276 } else { 1277 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1278 } 1279 } 1280 1281 struct LPCRSyncState { 1282 target_ulong value; 1283 target_ulong mask; 1284 }; 1285 1286 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1287 { 1288 struct LPCRSyncState *s = arg.host_ptr; 1289 PowerPCCPU *cpu = POWERPC_CPU(cs); 1290 CPUPPCState *env = &cpu->env; 1291 target_ulong lpcr; 1292 1293 cpu_synchronize_state(cs); 1294 lpcr = env->spr[SPR_LPCR]; 1295 lpcr &= ~s->mask; 1296 lpcr |= s->value; 1297 ppc_store_lpcr(cpu, lpcr); 1298 } 1299 1300 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1301 { 1302 CPUState *cs; 1303 struct LPCRSyncState s = { 1304 .value = value, 1305 .mask = mask 1306 }; 1307 CPU_FOREACH(cs) { 1308 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1309 } 1310 } 1311 1312 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1313 target_ulong lpid, ppc_v3_pate_t *entry) 1314 { 1315 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1316 1317 assert(lpid == 0); 1318 1319 /* Copy PATE1:GR into PATE0:HR */ 1320 entry->dw0 = spapr->patb_entry & PATE0_HR; 1321 entry->dw1 = spapr->patb_entry; 1322 1323 return true; 1324 } 1325 1326 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1327 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1328 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1329 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1330 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1331 1332 /* 1333 * Get the fd to access the kernel htab, re-opening it if necessary 1334 */ 1335 static int get_htab_fd(SpaprMachineState *spapr) 1336 { 1337 Error *local_err = NULL; 1338 1339 if (spapr->htab_fd >= 0) { 1340 return spapr->htab_fd; 1341 } 1342 1343 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1344 if (spapr->htab_fd < 0) { 1345 error_report_err(local_err); 1346 } 1347 1348 return spapr->htab_fd; 1349 } 1350 1351 void close_htab_fd(SpaprMachineState *spapr) 1352 { 1353 if (spapr->htab_fd >= 0) { 1354 close(spapr->htab_fd); 1355 } 1356 spapr->htab_fd = -1; 1357 } 1358 1359 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1360 { 1361 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1362 1363 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1364 } 1365 1366 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1367 { 1368 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1369 1370 assert(kvm_enabled()); 1371 1372 if (!spapr->htab) { 1373 return 0; 1374 } 1375 1376 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1377 } 1378 1379 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1380 hwaddr ptex, int n) 1381 { 1382 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1383 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1384 1385 if (!spapr->htab) { 1386 /* 1387 * HTAB is controlled by KVM. Fetch into temporary buffer 1388 */ 1389 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1390 kvmppc_read_hptes(hptes, ptex, n); 1391 return hptes; 1392 } 1393 1394 /* 1395 * HTAB is controlled by QEMU. Just point to the internally 1396 * accessible PTEG. 1397 */ 1398 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1399 } 1400 1401 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1402 const ppc_hash_pte64_t *hptes, 1403 hwaddr ptex, int n) 1404 { 1405 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1406 1407 if (!spapr->htab) { 1408 g_free((void *)hptes); 1409 } 1410 1411 /* Nothing to do for qemu managed HPT */ 1412 } 1413 1414 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1415 uint64_t pte0, uint64_t pte1) 1416 { 1417 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1418 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1419 1420 if (!spapr->htab) { 1421 kvmppc_write_hpte(ptex, pte0, pte1); 1422 } else { 1423 if (pte0 & HPTE64_V_VALID) { 1424 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1425 /* 1426 * When setting valid, we write PTE1 first. This ensures 1427 * proper synchronization with the reading code in 1428 * ppc_hash64_pteg_search() 1429 */ 1430 smp_wmb(); 1431 stq_p(spapr->htab + offset, pte0); 1432 } else { 1433 stq_p(spapr->htab + offset, pte0); 1434 /* 1435 * When clearing it we set PTE0 first. This ensures proper 1436 * synchronization with the reading code in 1437 * ppc_hash64_pteg_search() 1438 */ 1439 smp_wmb(); 1440 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1441 } 1442 } 1443 } 1444 1445 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1446 uint64_t pte1) 1447 { 1448 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1449 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1450 1451 if (!spapr->htab) { 1452 /* There should always be a hash table when this is called */ 1453 error_report("spapr_hpte_set_c called with no hash table !"); 1454 return; 1455 } 1456 1457 /* The HW performs a non-atomic byte update */ 1458 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1459 } 1460 1461 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1462 uint64_t pte1) 1463 { 1464 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1465 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1466 1467 if (!spapr->htab) { 1468 /* There should always be a hash table when this is called */ 1469 error_report("spapr_hpte_set_r called with no hash table !"); 1470 return; 1471 } 1472 1473 /* The HW performs a non-atomic byte update */ 1474 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1475 } 1476 1477 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1478 { 1479 int shift; 1480 1481 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1482 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1483 * that's much more than is needed for Linux guests */ 1484 shift = ctz64(pow2ceil(ramsize)) - 7; 1485 shift = MAX(shift, 18); /* Minimum architected size */ 1486 shift = MIN(shift, 46); /* Maximum architected size */ 1487 return shift; 1488 } 1489 1490 void spapr_free_hpt(SpaprMachineState *spapr) 1491 { 1492 g_free(spapr->htab); 1493 spapr->htab = NULL; 1494 spapr->htab_shift = 0; 1495 close_htab_fd(spapr); 1496 } 1497 1498 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1499 { 1500 ERRP_GUARD(); 1501 long rc; 1502 1503 /* Clean up any HPT info from a previous boot */ 1504 spapr_free_hpt(spapr); 1505 1506 rc = kvmppc_reset_htab(shift); 1507 1508 if (rc == -EOPNOTSUPP) { 1509 error_setg(errp, "HPT not supported in nested guests"); 1510 return -EOPNOTSUPP; 1511 } 1512 1513 if (rc < 0) { 1514 /* kernel-side HPT needed, but couldn't allocate one */ 1515 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1516 shift); 1517 error_append_hint(errp, "Try smaller maxmem?\n"); 1518 return -errno; 1519 } else if (rc > 0) { 1520 /* kernel-side HPT allocated */ 1521 if (rc != shift) { 1522 error_setg(errp, 1523 "Requested order %d HPT, but kernel allocated order %ld", 1524 shift, rc); 1525 error_append_hint(errp, "Try smaller maxmem?\n"); 1526 return -ENOSPC; 1527 } 1528 1529 spapr->htab_shift = shift; 1530 spapr->htab = NULL; 1531 } else { 1532 /* kernel-side HPT not needed, allocate in userspace instead */ 1533 size_t size = 1ULL << shift; 1534 int i; 1535 1536 spapr->htab = qemu_memalign(size, size); 1537 memset(spapr->htab, 0, size); 1538 spapr->htab_shift = shift; 1539 1540 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1541 DIRTY_HPTE(HPTE(spapr->htab, i)); 1542 } 1543 } 1544 /* We're setting up a hash table, so that means we're not radix */ 1545 spapr->patb_entry = 0; 1546 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1547 return 0; 1548 } 1549 1550 void spapr_setup_hpt(SpaprMachineState *spapr) 1551 { 1552 int hpt_shift; 1553 1554 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1555 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1556 } else { 1557 uint64_t current_ram_size; 1558 1559 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1560 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1561 } 1562 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1563 1564 if (kvm_enabled()) { 1565 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1566 1567 /* Check our RMA fits in the possible VRMA */ 1568 if (vrma_limit < spapr->rma_size) { 1569 error_report("Unable to create %" HWADDR_PRIu 1570 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1571 spapr->rma_size / MiB, vrma_limit / MiB); 1572 exit(EXIT_FAILURE); 1573 } 1574 } 1575 } 1576 1577 void spapr_check_mmu_mode(bool guest_radix) 1578 { 1579 if (guest_radix) { 1580 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1581 error_report("Guest requested unavailable MMU mode (radix)."); 1582 exit(EXIT_FAILURE); 1583 } 1584 } else { 1585 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1586 && !kvmppc_has_cap_mmu_hash_v3()) { 1587 error_report("Guest requested unavailable MMU mode (hash)."); 1588 exit(EXIT_FAILURE); 1589 } 1590 } 1591 } 1592 1593 static void spapr_machine_reset(MachineState *machine) 1594 { 1595 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1596 PowerPCCPU *first_ppc_cpu; 1597 hwaddr fdt_addr; 1598 void *fdt; 1599 int rc; 1600 1601 pef_kvm_reset(machine->cgs, &error_fatal); 1602 spapr_caps_apply(spapr); 1603 1604 first_ppc_cpu = POWERPC_CPU(first_cpu); 1605 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1606 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1607 spapr->max_compat_pvr)) { 1608 /* 1609 * If using KVM with radix mode available, VCPUs can be started 1610 * without a HPT because KVM will start them in radix mode. 1611 * Set the GR bit in PATE so that we know there is no HPT. 1612 */ 1613 spapr->patb_entry = PATE1_GR; 1614 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1615 } else { 1616 spapr_setup_hpt(spapr); 1617 } 1618 1619 qemu_devices_reset(); 1620 1621 spapr_ovec_cleanup(spapr->ov5_cas); 1622 spapr->ov5_cas = spapr_ovec_new(); 1623 1624 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1625 1626 /* 1627 * This is fixing some of the default configuration of the XIVE 1628 * devices. To be called after the reset of the machine devices. 1629 */ 1630 spapr_irq_reset(spapr, &error_fatal); 1631 1632 /* 1633 * There is no CAS under qtest. Simulate one to please the code that 1634 * depends on spapr->ov5_cas. This is especially needed to test device 1635 * unplug, so we do that before resetting the DRCs. 1636 */ 1637 if (qtest_enabled()) { 1638 spapr_ovec_cleanup(spapr->ov5_cas); 1639 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1640 } 1641 1642 spapr_nvdimm_finish_flushes(); 1643 1644 /* DRC reset may cause a device to be unplugged. This will cause troubles 1645 * if this device is used by another device (eg, a running vhost backend 1646 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1647 * situations, we reset DRCs after all devices have been reset. 1648 */ 1649 spapr_drc_reset_all(spapr); 1650 1651 spapr_clear_pending_events(spapr); 1652 1653 /* 1654 * We place the device tree just below either the top of the RMA, 1655 * or just below 2GB, whichever is lower, so that it can be 1656 * processed with 32-bit real mode code if necessary 1657 */ 1658 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1659 1660 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1661 if (spapr->vof) { 1662 spapr_vof_reset(spapr, fdt, &error_fatal); 1663 /* 1664 * Do not pack the FDT as the client may change properties. 1665 * VOF client does not expect the FDT so we do not load it to the VM. 1666 */ 1667 } else { 1668 rc = fdt_pack(fdt); 1669 /* Should only fail if we've built a corrupted tree */ 1670 assert(rc == 0); 1671 1672 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1673 0, fdt_addr, 0); 1674 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1675 } 1676 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1677 1678 g_free(spapr->fdt_blob); 1679 spapr->fdt_size = fdt_totalsize(fdt); 1680 spapr->fdt_initial_size = spapr->fdt_size; 1681 spapr->fdt_blob = fdt; 1682 1683 /* Set up the entry state */ 1684 first_ppc_cpu->env.gpr[5] = 0; 1685 1686 spapr->fwnmi_system_reset_addr = -1; 1687 spapr->fwnmi_machine_check_addr = -1; 1688 spapr->fwnmi_machine_check_interlock = -1; 1689 1690 /* Signal all vCPUs waiting on this condition */ 1691 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1692 1693 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1694 } 1695 1696 static void spapr_create_nvram(SpaprMachineState *spapr) 1697 { 1698 DeviceState *dev = qdev_new("spapr-nvram"); 1699 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1700 1701 if (dinfo) { 1702 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1703 &error_fatal); 1704 } 1705 1706 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1707 1708 spapr->nvram = (struct SpaprNvram *)dev; 1709 } 1710 1711 static void spapr_rtc_create(SpaprMachineState *spapr) 1712 { 1713 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1714 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1715 &error_fatal, NULL); 1716 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1717 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1718 "date"); 1719 } 1720 1721 /* Returns whether we want to use VGA or not */ 1722 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1723 { 1724 switch (vga_interface_type) { 1725 case VGA_NONE: 1726 return false; 1727 case VGA_DEVICE: 1728 return true; 1729 case VGA_STD: 1730 case VGA_VIRTIO: 1731 case VGA_CIRRUS: 1732 return pci_vga_init(pci_bus) != NULL; 1733 default: 1734 error_setg(errp, 1735 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1736 return false; 1737 } 1738 } 1739 1740 static int spapr_pre_load(void *opaque) 1741 { 1742 int rc; 1743 1744 rc = spapr_caps_pre_load(opaque); 1745 if (rc) { 1746 return rc; 1747 } 1748 1749 return 0; 1750 } 1751 1752 static int spapr_post_load(void *opaque, int version_id) 1753 { 1754 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1755 int err = 0; 1756 1757 err = spapr_caps_post_migration(spapr); 1758 if (err) { 1759 return err; 1760 } 1761 1762 /* 1763 * In earlier versions, there was no separate qdev for the PAPR 1764 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1765 * So when migrating from those versions, poke the incoming offset 1766 * value into the RTC device 1767 */ 1768 if (version_id < 3) { 1769 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1770 if (err) { 1771 return err; 1772 } 1773 } 1774 1775 if (kvm_enabled() && spapr->patb_entry) { 1776 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1777 bool radix = !!(spapr->patb_entry & PATE1_GR); 1778 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1779 1780 /* 1781 * Update LPCR:HR and UPRT as they may not be set properly in 1782 * the stream 1783 */ 1784 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1785 LPCR_HR | LPCR_UPRT); 1786 1787 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1788 if (err) { 1789 error_report("Process table config unsupported by the host"); 1790 return -EINVAL; 1791 } 1792 } 1793 1794 err = spapr_irq_post_load(spapr, version_id); 1795 if (err) { 1796 return err; 1797 } 1798 1799 return err; 1800 } 1801 1802 static int spapr_pre_save(void *opaque) 1803 { 1804 int rc; 1805 1806 rc = spapr_caps_pre_save(opaque); 1807 if (rc) { 1808 return rc; 1809 } 1810 1811 return 0; 1812 } 1813 1814 static bool version_before_3(void *opaque, int version_id) 1815 { 1816 return version_id < 3; 1817 } 1818 1819 static bool spapr_pending_events_needed(void *opaque) 1820 { 1821 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1822 return !QTAILQ_EMPTY(&spapr->pending_events); 1823 } 1824 1825 static const VMStateDescription vmstate_spapr_event_entry = { 1826 .name = "spapr_event_log_entry", 1827 .version_id = 1, 1828 .minimum_version_id = 1, 1829 .fields = (VMStateField[]) { 1830 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1831 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1832 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1833 NULL, extended_length), 1834 VMSTATE_END_OF_LIST() 1835 }, 1836 }; 1837 1838 static const VMStateDescription vmstate_spapr_pending_events = { 1839 .name = "spapr_pending_events", 1840 .version_id = 1, 1841 .minimum_version_id = 1, 1842 .needed = spapr_pending_events_needed, 1843 .fields = (VMStateField[]) { 1844 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1845 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1846 VMSTATE_END_OF_LIST() 1847 }, 1848 }; 1849 1850 static bool spapr_ov5_cas_needed(void *opaque) 1851 { 1852 SpaprMachineState *spapr = opaque; 1853 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1854 bool cas_needed; 1855 1856 /* Prior to the introduction of SpaprOptionVector, we had two option 1857 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1858 * Both of these options encode machine topology into the device-tree 1859 * in such a way that the now-booted OS should still be able to interact 1860 * appropriately with QEMU regardless of what options were actually 1861 * negotiatied on the source side. 1862 * 1863 * As such, we can avoid migrating the CAS-negotiated options if these 1864 * are the only options available on the current machine/platform. 1865 * Since these are the only options available for pseries-2.7 and 1866 * earlier, this allows us to maintain old->new/new->old migration 1867 * compatibility. 1868 * 1869 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1870 * via default pseries-2.8 machines and explicit command-line parameters. 1871 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1872 * of the actual CAS-negotiated values to continue working properly. For 1873 * example, availability of memory unplug depends on knowing whether 1874 * OV5_HP_EVT was negotiated via CAS. 1875 * 1876 * Thus, for any cases where the set of available CAS-negotiatable 1877 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1878 * include the CAS-negotiated options in the migration stream, unless 1879 * if they affect boot time behaviour only. 1880 */ 1881 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1882 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1883 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1884 1885 /* We need extra information if we have any bits outside the mask 1886 * defined above */ 1887 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1888 1889 spapr_ovec_cleanup(ov5_mask); 1890 1891 return cas_needed; 1892 } 1893 1894 static const VMStateDescription vmstate_spapr_ov5_cas = { 1895 .name = "spapr_option_vector_ov5_cas", 1896 .version_id = 1, 1897 .minimum_version_id = 1, 1898 .needed = spapr_ov5_cas_needed, 1899 .fields = (VMStateField[]) { 1900 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1901 vmstate_spapr_ovec, SpaprOptionVector), 1902 VMSTATE_END_OF_LIST() 1903 }, 1904 }; 1905 1906 static bool spapr_patb_entry_needed(void *opaque) 1907 { 1908 SpaprMachineState *spapr = opaque; 1909 1910 return !!spapr->patb_entry; 1911 } 1912 1913 static const VMStateDescription vmstate_spapr_patb_entry = { 1914 .name = "spapr_patb_entry", 1915 .version_id = 1, 1916 .minimum_version_id = 1, 1917 .needed = spapr_patb_entry_needed, 1918 .fields = (VMStateField[]) { 1919 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1920 VMSTATE_END_OF_LIST() 1921 }, 1922 }; 1923 1924 static bool spapr_irq_map_needed(void *opaque) 1925 { 1926 SpaprMachineState *spapr = opaque; 1927 1928 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1929 } 1930 1931 static const VMStateDescription vmstate_spapr_irq_map = { 1932 .name = "spapr_irq_map", 1933 .version_id = 1, 1934 .minimum_version_id = 1, 1935 .needed = spapr_irq_map_needed, 1936 .fields = (VMStateField[]) { 1937 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1938 VMSTATE_END_OF_LIST() 1939 }, 1940 }; 1941 1942 static bool spapr_dtb_needed(void *opaque) 1943 { 1944 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1945 1946 return smc->update_dt_enabled; 1947 } 1948 1949 static int spapr_dtb_pre_load(void *opaque) 1950 { 1951 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1952 1953 g_free(spapr->fdt_blob); 1954 spapr->fdt_blob = NULL; 1955 spapr->fdt_size = 0; 1956 1957 return 0; 1958 } 1959 1960 static const VMStateDescription vmstate_spapr_dtb = { 1961 .name = "spapr_dtb", 1962 .version_id = 1, 1963 .minimum_version_id = 1, 1964 .needed = spapr_dtb_needed, 1965 .pre_load = spapr_dtb_pre_load, 1966 .fields = (VMStateField[]) { 1967 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1968 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1969 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1970 fdt_size), 1971 VMSTATE_END_OF_LIST() 1972 }, 1973 }; 1974 1975 static bool spapr_fwnmi_needed(void *opaque) 1976 { 1977 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1978 1979 return spapr->fwnmi_machine_check_addr != -1; 1980 } 1981 1982 static int spapr_fwnmi_pre_save(void *opaque) 1983 { 1984 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1985 1986 /* 1987 * Check if machine check handling is in progress and print a 1988 * warning message. 1989 */ 1990 if (spapr->fwnmi_machine_check_interlock != -1) { 1991 warn_report("A machine check is being handled during migration. The" 1992 "handler may run and log hardware error on the destination"); 1993 } 1994 1995 return 0; 1996 } 1997 1998 static const VMStateDescription vmstate_spapr_fwnmi = { 1999 .name = "spapr_fwnmi", 2000 .version_id = 1, 2001 .minimum_version_id = 1, 2002 .needed = spapr_fwnmi_needed, 2003 .pre_save = spapr_fwnmi_pre_save, 2004 .fields = (VMStateField[]) { 2005 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2006 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2007 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2008 VMSTATE_END_OF_LIST() 2009 }, 2010 }; 2011 2012 static const VMStateDescription vmstate_spapr = { 2013 .name = "spapr", 2014 .version_id = 3, 2015 .minimum_version_id = 1, 2016 .pre_load = spapr_pre_load, 2017 .post_load = spapr_post_load, 2018 .pre_save = spapr_pre_save, 2019 .fields = (VMStateField[]) { 2020 /* used to be @next_irq */ 2021 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2022 2023 /* RTC offset */ 2024 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2025 2026 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2027 VMSTATE_END_OF_LIST() 2028 }, 2029 .subsections = (const VMStateDescription*[]) { 2030 &vmstate_spapr_ov5_cas, 2031 &vmstate_spapr_patb_entry, 2032 &vmstate_spapr_pending_events, 2033 &vmstate_spapr_cap_htm, 2034 &vmstate_spapr_cap_vsx, 2035 &vmstate_spapr_cap_dfp, 2036 &vmstate_spapr_cap_cfpc, 2037 &vmstate_spapr_cap_sbbc, 2038 &vmstate_spapr_cap_ibs, 2039 &vmstate_spapr_cap_hpt_maxpagesize, 2040 &vmstate_spapr_irq_map, 2041 &vmstate_spapr_cap_nested_kvm_hv, 2042 &vmstate_spapr_dtb, 2043 &vmstate_spapr_cap_large_decr, 2044 &vmstate_spapr_cap_ccf_assist, 2045 &vmstate_spapr_cap_fwnmi, 2046 &vmstate_spapr_fwnmi, 2047 &vmstate_spapr_cap_rpt_invalidate, 2048 NULL 2049 } 2050 }; 2051 2052 static int htab_save_setup(QEMUFile *f, void *opaque) 2053 { 2054 SpaprMachineState *spapr = opaque; 2055 2056 /* "Iteration" header */ 2057 if (!spapr->htab_shift) { 2058 qemu_put_be32(f, -1); 2059 } else { 2060 qemu_put_be32(f, spapr->htab_shift); 2061 } 2062 2063 if (spapr->htab) { 2064 spapr->htab_save_index = 0; 2065 spapr->htab_first_pass = true; 2066 } else { 2067 if (spapr->htab_shift) { 2068 assert(kvm_enabled()); 2069 } 2070 } 2071 2072 2073 return 0; 2074 } 2075 2076 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2077 int chunkstart, int n_valid, int n_invalid) 2078 { 2079 qemu_put_be32(f, chunkstart); 2080 qemu_put_be16(f, n_valid); 2081 qemu_put_be16(f, n_invalid); 2082 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2083 HASH_PTE_SIZE_64 * n_valid); 2084 } 2085 2086 static void htab_save_end_marker(QEMUFile *f) 2087 { 2088 qemu_put_be32(f, 0); 2089 qemu_put_be16(f, 0); 2090 qemu_put_be16(f, 0); 2091 } 2092 2093 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2094 int64_t max_ns) 2095 { 2096 bool has_timeout = max_ns != -1; 2097 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2098 int index = spapr->htab_save_index; 2099 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2100 2101 assert(spapr->htab_first_pass); 2102 2103 do { 2104 int chunkstart; 2105 2106 /* Consume invalid HPTEs */ 2107 while ((index < htabslots) 2108 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2109 CLEAN_HPTE(HPTE(spapr->htab, index)); 2110 index++; 2111 } 2112 2113 /* Consume valid HPTEs */ 2114 chunkstart = index; 2115 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2116 && HPTE_VALID(HPTE(spapr->htab, index))) { 2117 CLEAN_HPTE(HPTE(spapr->htab, index)); 2118 index++; 2119 } 2120 2121 if (index > chunkstart) { 2122 int n_valid = index - chunkstart; 2123 2124 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2125 2126 if (has_timeout && 2127 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2128 break; 2129 } 2130 } 2131 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2132 2133 if (index >= htabslots) { 2134 assert(index == htabslots); 2135 index = 0; 2136 spapr->htab_first_pass = false; 2137 } 2138 spapr->htab_save_index = index; 2139 } 2140 2141 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2142 int64_t max_ns) 2143 { 2144 bool final = max_ns < 0; 2145 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2146 int examined = 0, sent = 0; 2147 int index = spapr->htab_save_index; 2148 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2149 2150 assert(!spapr->htab_first_pass); 2151 2152 do { 2153 int chunkstart, invalidstart; 2154 2155 /* Consume non-dirty HPTEs */ 2156 while ((index < htabslots) 2157 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2158 index++; 2159 examined++; 2160 } 2161 2162 chunkstart = index; 2163 /* Consume valid dirty HPTEs */ 2164 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2165 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2166 && HPTE_VALID(HPTE(spapr->htab, index))) { 2167 CLEAN_HPTE(HPTE(spapr->htab, index)); 2168 index++; 2169 examined++; 2170 } 2171 2172 invalidstart = index; 2173 /* Consume invalid dirty HPTEs */ 2174 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2175 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2176 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2177 CLEAN_HPTE(HPTE(spapr->htab, index)); 2178 index++; 2179 examined++; 2180 } 2181 2182 if (index > chunkstart) { 2183 int n_valid = invalidstart - chunkstart; 2184 int n_invalid = index - invalidstart; 2185 2186 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2187 sent += index - chunkstart; 2188 2189 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2190 break; 2191 } 2192 } 2193 2194 if (examined >= htabslots) { 2195 break; 2196 } 2197 2198 if (index >= htabslots) { 2199 assert(index == htabslots); 2200 index = 0; 2201 } 2202 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2203 2204 if (index >= htabslots) { 2205 assert(index == htabslots); 2206 index = 0; 2207 } 2208 2209 spapr->htab_save_index = index; 2210 2211 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2212 } 2213 2214 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2215 #define MAX_KVM_BUF_SIZE 2048 2216 2217 static int htab_save_iterate(QEMUFile *f, void *opaque) 2218 { 2219 SpaprMachineState *spapr = opaque; 2220 int fd; 2221 int rc = 0; 2222 2223 /* Iteration header */ 2224 if (!spapr->htab_shift) { 2225 qemu_put_be32(f, -1); 2226 return 1; 2227 } else { 2228 qemu_put_be32(f, 0); 2229 } 2230 2231 if (!spapr->htab) { 2232 assert(kvm_enabled()); 2233 2234 fd = get_htab_fd(spapr); 2235 if (fd < 0) { 2236 return fd; 2237 } 2238 2239 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2240 if (rc < 0) { 2241 return rc; 2242 } 2243 } else if (spapr->htab_first_pass) { 2244 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2245 } else { 2246 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2247 } 2248 2249 htab_save_end_marker(f); 2250 2251 return rc; 2252 } 2253 2254 static int htab_save_complete(QEMUFile *f, void *opaque) 2255 { 2256 SpaprMachineState *spapr = opaque; 2257 int fd; 2258 2259 /* Iteration header */ 2260 if (!spapr->htab_shift) { 2261 qemu_put_be32(f, -1); 2262 return 0; 2263 } else { 2264 qemu_put_be32(f, 0); 2265 } 2266 2267 if (!spapr->htab) { 2268 int rc; 2269 2270 assert(kvm_enabled()); 2271 2272 fd = get_htab_fd(spapr); 2273 if (fd < 0) { 2274 return fd; 2275 } 2276 2277 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2278 if (rc < 0) { 2279 return rc; 2280 } 2281 } else { 2282 if (spapr->htab_first_pass) { 2283 htab_save_first_pass(f, spapr, -1); 2284 } 2285 htab_save_later_pass(f, spapr, -1); 2286 } 2287 2288 /* End marker */ 2289 htab_save_end_marker(f); 2290 2291 return 0; 2292 } 2293 2294 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2295 { 2296 SpaprMachineState *spapr = opaque; 2297 uint32_t section_hdr; 2298 int fd = -1; 2299 Error *local_err = NULL; 2300 2301 if (version_id < 1 || version_id > 1) { 2302 error_report("htab_load() bad version"); 2303 return -EINVAL; 2304 } 2305 2306 section_hdr = qemu_get_be32(f); 2307 2308 if (section_hdr == -1) { 2309 spapr_free_hpt(spapr); 2310 return 0; 2311 } 2312 2313 if (section_hdr) { 2314 int ret; 2315 2316 /* First section gives the htab size */ 2317 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2318 if (ret < 0) { 2319 error_report_err(local_err); 2320 return ret; 2321 } 2322 return 0; 2323 } 2324 2325 if (!spapr->htab) { 2326 assert(kvm_enabled()); 2327 2328 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2329 if (fd < 0) { 2330 error_report_err(local_err); 2331 return fd; 2332 } 2333 } 2334 2335 while (true) { 2336 uint32_t index; 2337 uint16_t n_valid, n_invalid; 2338 2339 index = qemu_get_be32(f); 2340 n_valid = qemu_get_be16(f); 2341 n_invalid = qemu_get_be16(f); 2342 2343 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2344 /* End of Stream */ 2345 break; 2346 } 2347 2348 if ((index + n_valid + n_invalid) > 2349 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2350 /* Bad index in stream */ 2351 error_report( 2352 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2353 index, n_valid, n_invalid, spapr->htab_shift); 2354 return -EINVAL; 2355 } 2356 2357 if (spapr->htab) { 2358 if (n_valid) { 2359 qemu_get_buffer(f, HPTE(spapr->htab, index), 2360 HASH_PTE_SIZE_64 * n_valid); 2361 } 2362 if (n_invalid) { 2363 memset(HPTE(spapr->htab, index + n_valid), 0, 2364 HASH_PTE_SIZE_64 * n_invalid); 2365 } 2366 } else { 2367 int rc; 2368 2369 assert(fd >= 0); 2370 2371 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2372 &local_err); 2373 if (rc < 0) { 2374 error_report_err(local_err); 2375 return rc; 2376 } 2377 } 2378 } 2379 2380 if (!spapr->htab) { 2381 assert(fd >= 0); 2382 close(fd); 2383 } 2384 2385 return 0; 2386 } 2387 2388 static void htab_save_cleanup(void *opaque) 2389 { 2390 SpaprMachineState *spapr = opaque; 2391 2392 close_htab_fd(spapr); 2393 } 2394 2395 static SaveVMHandlers savevm_htab_handlers = { 2396 .save_setup = htab_save_setup, 2397 .save_live_iterate = htab_save_iterate, 2398 .save_live_complete_precopy = htab_save_complete, 2399 .save_cleanup = htab_save_cleanup, 2400 .load_state = htab_load, 2401 }; 2402 2403 static void spapr_boot_set(void *opaque, const char *boot_device, 2404 Error **errp) 2405 { 2406 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2407 2408 g_free(spapr->boot_device); 2409 spapr->boot_device = g_strdup(boot_device); 2410 } 2411 2412 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2413 { 2414 MachineState *machine = MACHINE(spapr); 2415 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2416 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2417 int i; 2418 2419 for (i = 0; i < nr_lmbs; i++) { 2420 uint64_t addr; 2421 2422 addr = i * lmb_size + machine->device_memory->base; 2423 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2424 addr / lmb_size); 2425 } 2426 } 2427 2428 /* 2429 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2430 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2431 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2432 */ 2433 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2434 { 2435 int i; 2436 2437 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2438 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2439 " is not aligned to %" PRIu64 " MiB", 2440 machine->ram_size, 2441 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2442 return; 2443 } 2444 2445 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2446 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2447 " is not aligned to %" PRIu64 " MiB", 2448 machine->ram_size, 2449 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2450 return; 2451 } 2452 2453 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2454 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2455 error_setg(errp, 2456 "Node %d memory size 0x%" PRIx64 2457 " is not aligned to %" PRIu64 " MiB", 2458 i, machine->numa_state->nodes[i].node_mem, 2459 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2460 return; 2461 } 2462 } 2463 } 2464 2465 /* find cpu slot in machine->possible_cpus by core_id */ 2466 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2467 { 2468 int index = id / ms->smp.threads; 2469 2470 if (index >= ms->possible_cpus->len) { 2471 return NULL; 2472 } 2473 if (idx) { 2474 *idx = index; 2475 } 2476 return &ms->possible_cpus->cpus[index]; 2477 } 2478 2479 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2480 { 2481 MachineState *ms = MACHINE(spapr); 2482 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2483 Error *local_err = NULL; 2484 bool vsmt_user = !!spapr->vsmt; 2485 int kvm_smt = kvmppc_smt_threads(); 2486 int ret; 2487 unsigned int smp_threads = ms->smp.threads; 2488 2489 if (!kvm_enabled() && (smp_threads > 1)) { 2490 error_setg(errp, "TCG cannot support more than 1 thread/core " 2491 "on a pseries machine"); 2492 return; 2493 } 2494 if (!is_power_of_2(smp_threads)) { 2495 error_setg(errp, "Cannot support %d threads/core on a pseries " 2496 "machine because it must be a power of 2", smp_threads); 2497 return; 2498 } 2499 2500 /* Detemine the VSMT mode to use: */ 2501 if (vsmt_user) { 2502 if (spapr->vsmt < smp_threads) { 2503 error_setg(errp, "Cannot support VSMT mode %d" 2504 " because it must be >= threads/core (%d)", 2505 spapr->vsmt, smp_threads); 2506 return; 2507 } 2508 /* In this case, spapr->vsmt has been set by the command line */ 2509 } else if (!smc->smp_threads_vsmt) { 2510 /* 2511 * Default VSMT value is tricky, because we need it to be as 2512 * consistent as possible (for migration), but this requires 2513 * changing it for at least some existing cases. We pick 8 as 2514 * the value that we'd get with KVM on POWER8, the 2515 * overwhelmingly common case in production systems. 2516 */ 2517 spapr->vsmt = MAX(8, smp_threads); 2518 } else { 2519 spapr->vsmt = smp_threads; 2520 } 2521 2522 /* KVM: If necessary, set the SMT mode: */ 2523 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2524 ret = kvmppc_set_smt_threads(spapr->vsmt); 2525 if (ret) { 2526 /* Looks like KVM isn't able to change VSMT mode */ 2527 error_setg(&local_err, 2528 "Failed to set KVM's VSMT mode to %d (errno %d)", 2529 spapr->vsmt, ret); 2530 /* We can live with that if the default one is big enough 2531 * for the number of threads, and a submultiple of the one 2532 * we want. In this case we'll waste some vcpu ids, but 2533 * behaviour will be correct */ 2534 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2535 warn_report_err(local_err); 2536 } else { 2537 if (!vsmt_user) { 2538 error_append_hint(&local_err, 2539 "On PPC, a VM with %d threads/core" 2540 " on a host with %d threads/core" 2541 " requires the use of VSMT mode %d.\n", 2542 smp_threads, kvm_smt, spapr->vsmt); 2543 } 2544 kvmppc_error_append_smt_possible_hint(&local_err); 2545 error_propagate(errp, local_err); 2546 } 2547 } 2548 } 2549 /* else TCG: nothing to do currently */ 2550 } 2551 2552 static void spapr_init_cpus(SpaprMachineState *spapr) 2553 { 2554 MachineState *machine = MACHINE(spapr); 2555 MachineClass *mc = MACHINE_GET_CLASS(machine); 2556 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2557 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2558 const CPUArchIdList *possible_cpus; 2559 unsigned int smp_cpus = machine->smp.cpus; 2560 unsigned int smp_threads = machine->smp.threads; 2561 unsigned int max_cpus = machine->smp.max_cpus; 2562 int boot_cores_nr = smp_cpus / smp_threads; 2563 int i; 2564 2565 possible_cpus = mc->possible_cpu_arch_ids(machine); 2566 if (mc->has_hotpluggable_cpus) { 2567 if (smp_cpus % smp_threads) { 2568 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2569 smp_cpus, smp_threads); 2570 exit(1); 2571 } 2572 if (max_cpus % smp_threads) { 2573 error_report("max_cpus (%u) must be multiple of threads (%u)", 2574 max_cpus, smp_threads); 2575 exit(1); 2576 } 2577 } else { 2578 if (max_cpus != smp_cpus) { 2579 error_report("This machine version does not support CPU hotplug"); 2580 exit(1); 2581 } 2582 boot_cores_nr = possible_cpus->len; 2583 } 2584 2585 if (smc->pre_2_10_has_unused_icps) { 2586 int i; 2587 2588 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2589 /* Dummy entries get deregistered when real ICPState objects 2590 * are registered during CPU core hotplug. 2591 */ 2592 pre_2_10_vmstate_register_dummy_icp(i); 2593 } 2594 } 2595 2596 for (i = 0; i < possible_cpus->len; i++) { 2597 int core_id = i * smp_threads; 2598 2599 if (mc->has_hotpluggable_cpus) { 2600 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2601 spapr_vcpu_id(spapr, core_id)); 2602 } 2603 2604 if (i < boot_cores_nr) { 2605 Object *core = object_new(type); 2606 int nr_threads = smp_threads; 2607 2608 /* Handle the partially filled core for older machine types */ 2609 if ((i + 1) * smp_threads >= smp_cpus) { 2610 nr_threads = smp_cpus - i * smp_threads; 2611 } 2612 2613 object_property_set_int(core, "nr-threads", nr_threads, 2614 &error_fatal); 2615 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2616 &error_fatal); 2617 qdev_realize(DEVICE(core), NULL, &error_fatal); 2618 2619 object_unref(core); 2620 } 2621 } 2622 } 2623 2624 static PCIHostState *spapr_create_default_phb(void) 2625 { 2626 DeviceState *dev; 2627 2628 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2629 qdev_prop_set_uint32(dev, "index", 0); 2630 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2631 2632 return PCI_HOST_BRIDGE(dev); 2633 } 2634 2635 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2636 { 2637 MachineState *machine = MACHINE(spapr); 2638 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2639 hwaddr rma_size = machine->ram_size; 2640 hwaddr node0_size = spapr_node0_size(machine); 2641 2642 /* RMA has to fit in the first NUMA node */ 2643 rma_size = MIN(rma_size, node0_size); 2644 2645 /* 2646 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2647 * never exceed that 2648 */ 2649 rma_size = MIN(rma_size, 1 * TiB); 2650 2651 /* 2652 * Clamp the RMA size based on machine type. This is for 2653 * migration compatibility with older qemu versions, which limited 2654 * the RMA size for complicated and mostly bad reasons. 2655 */ 2656 if (smc->rma_limit) { 2657 rma_size = MIN(rma_size, smc->rma_limit); 2658 } 2659 2660 if (rma_size < MIN_RMA_SLOF) { 2661 error_setg(errp, 2662 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2663 "ldMiB guest RMA (Real Mode Area memory)", 2664 MIN_RMA_SLOF / MiB); 2665 return 0; 2666 } 2667 2668 return rma_size; 2669 } 2670 2671 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2672 { 2673 MachineState *machine = MACHINE(spapr); 2674 int i; 2675 2676 for (i = 0; i < machine->ram_slots; i++) { 2677 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2678 } 2679 } 2680 2681 /* pSeries LPAR / sPAPR hardware init */ 2682 static void spapr_machine_init(MachineState *machine) 2683 { 2684 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2685 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2686 MachineClass *mc = MACHINE_GET_CLASS(machine); 2687 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2688 const char *bios_name = machine->firmware ?: bios_default; 2689 const char *kernel_filename = machine->kernel_filename; 2690 const char *initrd_filename = machine->initrd_filename; 2691 PCIHostState *phb; 2692 int i; 2693 MemoryRegion *sysmem = get_system_memory(); 2694 long load_limit, fw_size; 2695 char *filename; 2696 Error *resize_hpt_err = NULL; 2697 2698 /* 2699 * if Secure VM (PEF) support is configured, then initialize it 2700 */ 2701 pef_kvm_init(machine->cgs, &error_fatal); 2702 2703 msi_nonbroken = true; 2704 2705 QLIST_INIT(&spapr->phbs); 2706 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2707 2708 /* Determine capabilities to run with */ 2709 spapr_caps_init(spapr); 2710 2711 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2712 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2713 /* 2714 * If the user explicitly requested a mode we should either 2715 * supply it, or fail completely (which we do below). But if 2716 * it's not set explicitly, we reset our mode to something 2717 * that works 2718 */ 2719 if (resize_hpt_err) { 2720 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2721 error_free(resize_hpt_err); 2722 resize_hpt_err = NULL; 2723 } else { 2724 spapr->resize_hpt = smc->resize_hpt_default; 2725 } 2726 } 2727 2728 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2729 2730 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2731 /* 2732 * User requested HPT resize, but this host can't supply it. Bail out 2733 */ 2734 error_report_err(resize_hpt_err); 2735 exit(1); 2736 } 2737 error_free(resize_hpt_err); 2738 2739 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2740 2741 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2742 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2743 2744 /* 2745 * VSMT must be set in order to be able to compute VCPU ids, ie to 2746 * call spapr_max_server_number() or spapr_vcpu_id(). 2747 */ 2748 spapr_set_vsmt_mode(spapr, &error_fatal); 2749 2750 /* Set up Interrupt Controller before we create the VCPUs */ 2751 spapr_irq_init(spapr, &error_fatal); 2752 2753 /* Set up containers for ibm,client-architecture-support negotiated options 2754 */ 2755 spapr->ov5 = spapr_ovec_new(); 2756 spapr->ov5_cas = spapr_ovec_new(); 2757 2758 if (smc->dr_lmb_enabled) { 2759 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2760 spapr_validate_node_memory(machine, &error_fatal); 2761 } 2762 2763 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2764 2765 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2766 if (!smc->pre_6_2_numa_affinity) { 2767 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2768 } 2769 2770 /* advertise support for dedicated HP event source to guests */ 2771 if (spapr->use_hotplug_event_source) { 2772 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2773 } 2774 2775 /* advertise support for HPT resizing */ 2776 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2777 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2778 } 2779 2780 /* advertise support for ibm,dyamic-memory-v2 */ 2781 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2782 2783 /* advertise XIVE on POWER9 machines */ 2784 if (spapr->irq->xive) { 2785 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2786 } 2787 2788 /* init CPUs */ 2789 spapr_init_cpus(spapr); 2790 2791 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2792 2793 /* Init numa_assoc_array */ 2794 spapr_numa_associativity_init(spapr, machine); 2795 2796 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2797 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2798 spapr->max_compat_pvr)) { 2799 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2800 /* KVM and TCG always allow GTSE with radix... */ 2801 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2802 } 2803 /* ... but not with hash (currently). */ 2804 2805 if (kvm_enabled()) { 2806 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2807 kvmppc_enable_logical_ci_hcalls(); 2808 kvmppc_enable_set_mode_hcall(); 2809 2810 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2811 kvmppc_enable_clear_ref_mod_hcalls(); 2812 2813 /* Enable H_PAGE_INIT */ 2814 kvmppc_enable_h_page_init(); 2815 } 2816 2817 /* map RAM */ 2818 memory_region_add_subregion(sysmem, 0, machine->ram); 2819 2820 /* always allocate the device memory information */ 2821 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2822 2823 /* initialize hotplug memory address space */ 2824 if (machine->ram_size < machine->maxram_size) { 2825 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2826 /* 2827 * Limit the number of hotpluggable memory slots to half the number 2828 * slots that KVM supports, leaving the other half for PCI and other 2829 * devices. However ensure that number of slots doesn't drop below 32. 2830 */ 2831 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2832 SPAPR_MAX_RAM_SLOTS; 2833 2834 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2835 max_memslots = SPAPR_MAX_RAM_SLOTS; 2836 } 2837 if (machine->ram_slots > max_memslots) { 2838 error_report("Specified number of memory slots %" 2839 PRIu64" exceeds max supported %d", 2840 machine->ram_slots, max_memslots); 2841 exit(1); 2842 } 2843 2844 machine->device_memory->base = ROUND_UP(machine->ram_size, 2845 SPAPR_DEVICE_MEM_ALIGN); 2846 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2847 "device-memory", device_mem_size); 2848 memory_region_add_subregion(sysmem, machine->device_memory->base, 2849 &machine->device_memory->mr); 2850 } 2851 2852 if (smc->dr_lmb_enabled) { 2853 spapr_create_lmb_dr_connectors(spapr); 2854 } 2855 2856 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2857 /* Create the error string for live migration blocker */ 2858 error_setg(&spapr->fwnmi_migration_blocker, 2859 "A machine check is being handled during migration. The handler" 2860 "may run and log hardware error on the destination"); 2861 } 2862 2863 if (mc->nvdimm_supported) { 2864 spapr_create_nvdimm_dr_connectors(spapr); 2865 } 2866 2867 /* Set up RTAS event infrastructure */ 2868 spapr_events_init(spapr); 2869 2870 /* Set up the RTC RTAS interfaces */ 2871 spapr_rtc_create(spapr); 2872 2873 /* Set up VIO bus */ 2874 spapr->vio_bus = spapr_vio_bus_init(); 2875 2876 for (i = 0; serial_hd(i); i++) { 2877 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2878 } 2879 2880 /* We always have at least the nvram device on VIO */ 2881 spapr_create_nvram(spapr); 2882 2883 /* 2884 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2885 * connectors (described in root DT node's "ibm,drc-types" property) 2886 * are pre-initialized here. additional child connectors (such as 2887 * connectors for a PHBs PCI slots) are added as needed during their 2888 * parent's realization. 2889 */ 2890 if (smc->dr_phb_enabled) { 2891 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2892 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2893 } 2894 } 2895 2896 /* Set up PCI */ 2897 spapr_pci_rtas_init(); 2898 2899 phb = spapr_create_default_phb(); 2900 2901 for (i = 0; i < nb_nics; i++) { 2902 NICInfo *nd = &nd_table[i]; 2903 2904 if (!nd->model) { 2905 nd->model = g_strdup("spapr-vlan"); 2906 } 2907 2908 if (g_str_equal(nd->model, "spapr-vlan") || 2909 g_str_equal(nd->model, "ibmveth")) { 2910 spapr_vlan_create(spapr->vio_bus, nd); 2911 } else { 2912 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2913 } 2914 } 2915 2916 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2917 spapr_vscsi_create(spapr->vio_bus); 2918 } 2919 2920 /* Graphics */ 2921 if (spapr_vga_init(phb->bus, &error_fatal)) { 2922 spapr->has_graphics = true; 2923 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2924 } 2925 2926 if (machine->usb) { 2927 if (smc->use_ohci_by_default) { 2928 pci_create_simple(phb->bus, -1, "pci-ohci"); 2929 } else { 2930 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2931 } 2932 2933 if (spapr->has_graphics) { 2934 USBBus *usb_bus = usb_bus_find(-1); 2935 2936 usb_create_simple(usb_bus, "usb-kbd"); 2937 usb_create_simple(usb_bus, "usb-mouse"); 2938 } 2939 } 2940 2941 if (kernel_filename) { 2942 spapr->kernel_size = load_elf(kernel_filename, NULL, 2943 translate_kernel_address, spapr, 2944 NULL, NULL, NULL, NULL, 1, 2945 PPC_ELF_MACHINE, 0, 0); 2946 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2947 spapr->kernel_size = load_elf(kernel_filename, NULL, 2948 translate_kernel_address, spapr, 2949 NULL, NULL, NULL, NULL, 0, 2950 PPC_ELF_MACHINE, 0, 0); 2951 spapr->kernel_le = spapr->kernel_size > 0; 2952 } 2953 if (spapr->kernel_size < 0) { 2954 error_report("error loading %s: %s", kernel_filename, 2955 load_elf_strerror(spapr->kernel_size)); 2956 exit(1); 2957 } 2958 2959 /* load initrd */ 2960 if (initrd_filename) { 2961 /* Try to locate the initrd in the gap between the kernel 2962 * and the firmware. Add a bit of space just in case 2963 */ 2964 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2965 + 0x1ffff) & ~0xffff; 2966 spapr->initrd_size = load_image_targphys(initrd_filename, 2967 spapr->initrd_base, 2968 load_limit 2969 - spapr->initrd_base); 2970 if (spapr->initrd_size < 0) { 2971 error_report("could not load initial ram disk '%s'", 2972 initrd_filename); 2973 exit(1); 2974 } 2975 } 2976 } 2977 2978 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2979 if (!filename) { 2980 error_report("Could not find LPAR firmware '%s'", bios_name); 2981 exit(1); 2982 } 2983 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2984 if (fw_size <= 0) { 2985 error_report("Could not load LPAR firmware '%s'", filename); 2986 exit(1); 2987 } 2988 g_free(filename); 2989 2990 /* FIXME: Should register things through the MachineState's qdev 2991 * interface, this is a legacy from the sPAPREnvironment structure 2992 * which predated MachineState but had a similar function */ 2993 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2994 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2995 &savevm_htab_handlers, spapr); 2996 2997 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2998 2999 qemu_register_boot_set(spapr_boot_set, spapr); 3000 3001 /* 3002 * Nothing needs to be done to resume a suspended guest because 3003 * suspending does not change the machine state, so no need for 3004 * a ->wakeup method. 3005 */ 3006 qemu_register_wakeup_support(); 3007 3008 if (kvm_enabled()) { 3009 /* to stop and start vmclock */ 3010 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3011 &spapr->tb); 3012 3013 kvmppc_spapr_enable_inkernel_multitce(); 3014 } 3015 3016 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3017 if (spapr->vof) { 3018 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3019 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3020 } 3021 } 3022 3023 #define DEFAULT_KVM_TYPE "auto" 3024 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3025 { 3026 /* 3027 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3028 * accomodate the 'HV' and 'PV' formats that exists in the 3029 * wild. The 'auto' mode is being introduced already as 3030 * lower-case, thus we don't need to bother checking for 3031 * "AUTO". 3032 */ 3033 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3034 return 0; 3035 } 3036 3037 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3038 return 1; 3039 } 3040 3041 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3042 return 2; 3043 } 3044 3045 error_report("Unknown kvm-type specified '%s'", vm_type); 3046 exit(1); 3047 } 3048 3049 /* 3050 * Implementation of an interface to adjust firmware path 3051 * for the bootindex property handling. 3052 */ 3053 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3054 DeviceState *dev) 3055 { 3056 #define CAST(type, obj, name) \ 3057 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3058 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3059 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3060 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3061 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3062 3063 if (d && bus) { 3064 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3065 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3066 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3067 3068 if (spapr) { 3069 /* 3070 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3071 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3072 * 0x8000 | (target << 8) | (bus << 5) | lun 3073 * (see the "Logical unit addressing format" table in SAM5) 3074 */ 3075 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3076 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3077 (uint64_t)id << 48); 3078 } else if (virtio) { 3079 /* 3080 * We use SRP luns of the form 01000000 | (target << 8) | lun 3081 * in the top 32 bits of the 64-bit LUN 3082 * Note: the quote above is from SLOF and it is wrong, 3083 * the actual binding is: 3084 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3085 */ 3086 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3087 if (d->lun >= 256) { 3088 /* Use the LUN "flat space addressing method" */ 3089 id |= 0x4000; 3090 } 3091 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3092 (uint64_t)id << 32); 3093 } else if (usb) { 3094 /* 3095 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3096 * in the top 32 bits of the 64-bit LUN 3097 */ 3098 unsigned usb_port = atoi(usb->port->path); 3099 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3100 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3101 (uint64_t)id << 32); 3102 } 3103 } 3104 3105 /* 3106 * SLOF probes the USB devices, and if it recognizes that the device is a 3107 * storage device, it changes its name to "storage" instead of "usb-host", 3108 * and additionally adds a child node for the SCSI LUN, so the correct 3109 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3110 */ 3111 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3112 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3113 if (usb_device_is_scsi_storage(usbdev)) { 3114 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3115 } 3116 } 3117 3118 if (phb) { 3119 /* Replace "pci" with "pci@800000020000000" */ 3120 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3121 } 3122 3123 if (vsc) { 3124 /* Same logic as virtio above */ 3125 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3126 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3127 } 3128 3129 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3130 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3131 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3132 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3133 } 3134 3135 if (pcidev) { 3136 return spapr_pci_fw_dev_name(pcidev); 3137 } 3138 3139 return NULL; 3140 } 3141 3142 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3143 { 3144 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3145 3146 return g_strdup(spapr->kvm_type); 3147 } 3148 3149 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3150 { 3151 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3152 3153 g_free(spapr->kvm_type); 3154 spapr->kvm_type = g_strdup(value); 3155 } 3156 3157 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3158 { 3159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3160 3161 return spapr->use_hotplug_event_source; 3162 } 3163 3164 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3165 Error **errp) 3166 { 3167 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3168 3169 spapr->use_hotplug_event_source = value; 3170 } 3171 3172 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3173 { 3174 return true; 3175 } 3176 3177 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3178 { 3179 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3180 3181 switch (spapr->resize_hpt) { 3182 case SPAPR_RESIZE_HPT_DEFAULT: 3183 return g_strdup("default"); 3184 case SPAPR_RESIZE_HPT_DISABLED: 3185 return g_strdup("disabled"); 3186 case SPAPR_RESIZE_HPT_ENABLED: 3187 return g_strdup("enabled"); 3188 case SPAPR_RESIZE_HPT_REQUIRED: 3189 return g_strdup("required"); 3190 } 3191 g_assert_not_reached(); 3192 } 3193 3194 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3195 { 3196 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3197 3198 if (strcmp(value, "default") == 0) { 3199 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3200 } else if (strcmp(value, "disabled") == 0) { 3201 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3202 } else if (strcmp(value, "enabled") == 0) { 3203 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3204 } else if (strcmp(value, "required") == 0) { 3205 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3206 } else { 3207 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3208 } 3209 } 3210 3211 static bool spapr_get_vof(Object *obj, Error **errp) 3212 { 3213 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3214 3215 return spapr->vof != NULL; 3216 } 3217 3218 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3219 { 3220 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3221 3222 if (spapr->vof) { 3223 vof_cleanup(spapr->vof); 3224 g_free(spapr->vof); 3225 spapr->vof = NULL; 3226 } 3227 if (!value) { 3228 return; 3229 } 3230 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3231 } 3232 3233 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3234 { 3235 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3236 3237 if (spapr->irq == &spapr_irq_xics_legacy) { 3238 return g_strdup("legacy"); 3239 } else if (spapr->irq == &spapr_irq_xics) { 3240 return g_strdup("xics"); 3241 } else if (spapr->irq == &spapr_irq_xive) { 3242 return g_strdup("xive"); 3243 } else if (spapr->irq == &spapr_irq_dual) { 3244 return g_strdup("dual"); 3245 } 3246 g_assert_not_reached(); 3247 } 3248 3249 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3250 { 3251 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3252 3253 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3254 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3255 return; 3256 } 3257 3258 /* The legacy IRQ backend can not be set */ 3259 if (strcmp(value, "xics") == 0) { 3260 spapr->irq = &spapr_irq_xics; 3261 } else if (strcmp(value, "xive") == 0) { 3262 spapr->irq = &spapr_irq_xive; 3263 } else if (strcmp(value, "dual") == 0) { 3264 spapr->irq = &spapr_irq_dual; 3265 } else { 3266 error_setg(errp, "Bad value for \"ic-mode\" property"); 3267 } 3268 } 3269 3270 static char *spapr_get_host_model(Object *obj, Error **errp) 3271 { 3272 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3273 3274 return g_strdup(spapr->host_model); 3275 } 3276 3277 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3278 { 3279 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3280 3281 g_free(spapr->host_model); 3282 spapr->host_model = g_strdup(value); 3283 } 3284 3285 static char *spapr_get_host_serial(Object *obj, Error **errp) 3286 { 3287 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3288 3289 return g_strdup(spapr->host_serial); 3290 } 3291 3292 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3293 { 3294 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3295 3296 g_free(spapr->host_serial); 3297 spapr->host_serial = g_strdup(value); 3298 } 3299 3300 static void spapr_instance_init(Object *obj) 3301 { 3302 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3303 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3304 MachineState *ms = MACHINE(spapr); 3305 MachineClass *mc = MACHINE_GET_CLASS(ms); 3306 3307 /* 3308 * NVDIMM support went live in 5.1 without considering that, in 3309 * other archs, the user needs to enable NVDIMM support with the 3310 * 'nvdimm' machine option and the default behavior is NVDIMM 3311 * support disabled. It is too late to roll back to the standard 3312 * behavior without breaking 5.1 guests. 3313 */ 3314 if (mc->nvdimm_supported) { 3315 ms->nvdimms_state->is_enabled = true; 3316 } 3317 3318 spapr->htab_fd = -1; 3319 spapr->use_hotplug_event_source = true; 3320 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3321 object_property_add_str(obj, "kvm-type", 3322 spapr_get_kvm_type, spapr_set_kvm_type); 3323 object_property_set_description(obj, "kvm-type", 3324 "Specifies the KVM virtualization mode (auto," 3325 " hv, pr). Defaults to 'auto'. This mode will use" 3326 " any available KVM module loaded in the host," 3327 " where kvm_hv takes precedence if both kvm_hv and" 3328 " kvm_pr are loaded."); 3329 object_property_add_bool(obj, "modern-hotplug-events", 3330 spapr_get_modern_hotplug_events, 3331 spapr_set_modern_hotplug_events); 3332 object_property_set_description(obj, "modern-hotplug-events", 3333 "Use dedicated hotplug event mechanism in" 3334 " place of standard EPOW events when possible" 3335 " (required for memory hot-unplug support)"); 3336 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3337 "Maximum permitted CPU compatibility mode"); 3338 3339 object_property_add_str(obj, "resize-hpt", 3340 spapr_get_resize_hpt, spapr_set_resize_hpt); 3341 object_property_set_description(obj, "resize-hpt", 3342 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3343 object_property_add_uint32_ptr(obj, "vsmt", 3344 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3345 object_property_set_description(obj, "vsmt", 3346 "Virtual SMT: KVM behaves as if this were" 3347 " the host's SMT mode"); 3348 3349 object_property_add_bool(obj, "vfio-no-msix-emulation", 3350 spapr_get_msix_emulation, NULL); 3351 3352 object_property_add_uint64_ptr(obj, "kernel-addr", 3353 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3354 object_property_set_description(obj, "kernel-addr", 3355 stringify(KERNEL_LOAD_ADDR) 3356 " for -kernel is the default"); 3357 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3358 3359 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3360 object_property_set_description(obj, "x-vof", 3361 "Enable Virtual Open Firmware (experimental)"); 3362 3363 /* The machine class defines the default interrupt controller mode */ 3364 spapr->irq = smc->irq; 3365 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3366 spapr_set_ic_mode); 3367 object_property_set_description(obj, "ic-mode", 3368 "Specifies the interrupt controller mode (xics, xive, dual)"); 3369 3370 object_property_add_str(obj, "host-model", 3371 spapr_get_host_model, spapr_set_host_model); 3372 object_property_set_description(obj, "host-model", 3373 "Host model to advertise in guest device tree"); 3374 object_property_add_str(obj, "host-serial", 3375 spapr_get_host_serial, spapr_set_host_serial); 3376 object_property_set_description(obj, "host-serial", 3377 "Host serial number to advertise in guest device tree"); 3378 } 3379 3380 static void spapr_machine_finalizefn(Object *obj) 3381 { 3382 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3383 3384 g_free(spapr->kvm_type); 3385 } 3386 3387 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3388 { 3389 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3390 PowerPCCPU *cpu = POWERPC_CPU(cs); 3391 CPUPPCState *env = &cpu->env; 3392 3393 cpu_synchronize_state(cs); 3394 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3395 if (spapr->fwnmi_system_reset_addr != -1) { 3396 uint64_t rtas_addr, addr; 3397 3398 /* get rtas addr from fdt */ 3399 rtas_addr = spapr_get_rtas_addr(); 3400 if (!rtas_addr) { 3401 qemu_system_guest_panicked(NULL); 3402 return; 3403 } 3404 3405 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3406 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3407 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3408 env->gpr[3] = addr; 3409 } 3410 ppc_cpu_do_system_reset(cs); 3411 if (spapr->fwnmi_system_reset_addr != -1) { 3412 env->nip = spapr->fwnmi_system_reset_addr; 3413 } 3414 } 3415 3416 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3417 { 3418 CPUState *cs; 3419 3420 CPU_FOREACH(cs) { 3421 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3422 } 3423 } 3424 3425 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3426 void *fdt, int *fdt_start_offset, Error **errp) 3427 { 3428 uint64_t addr; 3429 uint32_t node; 3430 3431 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3432 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3433 &error_abort); 3434 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3435 SPAPR_MEMORY_BLOCK_SIZE); 3436 return 0; 3437 } 3438 3439 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3440 bool dedicated_hp_event_source) 3441 { 3442 SpaprDrc *drc; 3443 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3444 int i; 3445 uint64_t addr = addr_start; 3446 bool hotplugged = spapr_drc_hotplugged(dev); 3447 3448 for (i = 0; i < nr_lmbs; i++) { 3449 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3450 addr / SPAPR_MEMORY_BLOCK_SIZE); 3451 g_assert(drc); 3452 3453 /* 3454 * memory_device_get_free_addr() provided a range of free addresses 3455 * that doesn't overlap with any existing mapping at pre-plug. The 3456 * corresponding LMB DRCs are thus assumed to be all attachable. 3457 */ 3458 spapr_drc_attach(drc, dev); 3459 if (!hotplugged) { 3460 spapr_drc_reset(drc); 3461 } 3462 addr += SPAPR_MEMORY_BLOCK_SIZE; 3463 } 3464 /* send hotplug notification to the 3465 * guest only in case of hotplugged memory 3466 */ 3467 if (hotplugged) { 3468 if (dedicated_hp_event_source) { 3469 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3470 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3471 g_assert(drc); 3472 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3473 nr_lmbs, 3474 spapr_drc_index(drc)); 3475 } else { 3476 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3477 nr_lmbs); 3478 } 3479 } 3480 } 3481 3482 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3483 { 3484 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3485 PCDIMMDevice *dimm = PC_DIMM(dev); 3486 uint64_t size, addr; 3487 int64_t slot; 3488 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3489 3490 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3491 3492 pc_dimm_plug(dimm, MACHINE(ms)); 3493 3494 if (!is_nvdimm) { 3495 addr = object_property_get_uint(OBJECT(dimm), 3496 PC_DIMM_ADDR_PROP, &error_abort); 3497 spapr_add_lmbs(dev, addr, size, 3498 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3499 } else { 3500 slot = object_property_get_int(OBJECT(dimm), 3501 PC_DIMM_SLOT_PROP, &error_abort); 3502 /* We should have valid slot number at this point */ 3503 g_assert(slot >= 0); 3504 spapr_add_nvdimm(dev, slot); 3505 } 3506 } 3507 3508 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3509 Error **errp) 3510 { 3511 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3512 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3513 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3514 PCDIMMDevice *dimm = PC_DIMM(dev); 3515 Error *local_err = NULL; 3516 uint64_t size; 3517 Object *memdev; 3518 hwaddr pagesize; 3519 3520 if (!smc->dr_lmb_enabled) { 3521 error_setg(errp, "Memory hotplug not supported for this machine"); 3522 return; 3523 } 3524 3525 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3526 if (local_err) { 3527 error_propagate(errp, local_err); 3528 return; 3529 } 3530 3531 if (is_nvdimm) { 3532 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3533 return; 3534 } 3535 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3536 error_setg(errp, "Hotplugged memory size must be a multiple of " 3537 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3538 return; 3539 } 3540 3541 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3542 &error_abort); 3543 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3544 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3545 return; 3546 } 3547 3548 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3549 } 3550 3551 struct SpaprDimmState { 3552 PCDIMMDevice *dimm; 3553 uint32_t nr_lmbs; 3554 QTAILQ_ENTRY(SpaprDimmState) next; 3555 }; 3556 3557 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3558 PCDIMMDevice *dimm) 3559 { 3560 SpaprDimmState *dimm_state = NULL; 3561 3562 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3563 if (dimm_state->dimm == dimm) { 3564 break; 3565 } 3566 } 3567 return dimm_state; 3568 } 3569 3570 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3571 uint32_t nr_lmbs, 3572 PCDIMMDevice *dimm) 3573 { 3574 SpaprDimmState *ds = NULL; 3575 3576 /* 3577 * If this request is for a DIMM whose removal had failed earlier 3578 * (due to guest's refusal to remove the LMBs), we would have this 3579 * dimm already in the pending_dimm_unplugs list. In that 3580 * case don't add again. 3581 */ 3582 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3583 if (!ds) { 3584 ds = g_malloc0(sizeof(SpaprDimmState)); 3585 ds->nr_lmbs = nr_lmbs; 3586 ds->dimm = dimm; 3587 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3588 } 3589 return ds; 3590 } 3591 3592 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3593 SpaprDimmState *dimm_state) 3594 { 3595 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3596 g_free(dimm_state); 3597 } 3598 3599 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3600 PCDIMMDevice *dimm) 3601 { 3602 SpaprDrc *drc; 3603 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3604 &error_abort); 3605 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3606 uint32_t avail_lmbs = 0; 3607 uint64_t addr_start, addr; 3608 int i; 3609 3610 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3611 &error_abort); 3612 3613 addr = addr_start; 3614 for (i = 0; i < nr_lmbs; i++) { 3615 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3616 addr / SPAPR_MEMORY_BLOCK_SIZE); 3617 g_assert(drc); 3618 if (drc->dev) { 3619 avail_lmbs++; 3620 } 3621 addr += SPAPR_MEMORY_BLOCK_SIZE; 3622 } 3623 3624 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3625 } 3626 3627 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3628 { 3629 SpaprDimmState *ds; 3630 PCDIMMDevice *dimm; 3631 SpaprDrc *drc; 3632 uint32_t nr_lmbs; 3633 uint64_t size, addr_start, addr; 3634 g_autofree char *qapi_error = NULL; 3635 int i; 3636 3637 if (!dev) { 3638 return; 3639 } 3640 3641 dimm = PC_DIMM(dev); 3642 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3643 3644 /* 3645 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3646 * unplug state, but one of its DRC is marked as unplug_requested. 3647 * This is bad and weird enough to g_assert() out. 3648 */ 3649 g_assert(ds); 3650 3651 spapr_pending_dimm_unplugs_remove(spapr, ds); 3652 3653 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3654 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3655 3656 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3657 &error_abort); 3658 3659 addr = addr_start; 3660 for (i = 0; i < nr_lmbs; i++) { 3661 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3662 addr / SPAPR_MEMORY_BLOCK_SIZE); 3663 g_assert(drc); 3664 3665 drc->unplug_requested = false; 3666 addr += SPAPR_MEMORY_BLOCK_SIZE; 3667 } 3668 3669 /* 3670 * Tell QAPI that something happened and the memory 3671 * hotunplug wasn't successful. Keep sending 3672 * MEM_UNPLUG_ERROR even while sending 3673 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3674 * MEM_UNPLUG_ERROR is due. 3675 */ 3676 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3677 "for device %s", dev->id); 3678 3679 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3680 3681 qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id, 3682 dev->canonical_path); 3683 } 3684 3685 /* Callback to be called during DRC release. */ 3686 void spapr_lmb_release(DeviceState *dev) 3687 { 3688 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3689 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3690 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3691 3692 /* This information will get lost if a migration occurs 3693 * during the unplug process. In this case recover it. */ 3694 if (ds == NULL) { 3695 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3696 g_assert(ds); 3697 /* The DRC being examined by the caller at least must be counted */ 3698 g_assert(ds->nr_lmbs); 3699 } 3700 3701 if (--ds->nr_lmbs) { 3702 return; 3703 } 3704 3705 /* 3706 * Now that all the LMBs have been removed by the guest, call the 3707 * unplug handler chain. This can never fail. 3708 */ 3709 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3710 object_unparent(OBJECT(dev)); 3711 } 3712 3713 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3714 { 3715 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3716 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3717 3718 /* We really shouldn't get this far without anything to unplug */ 3719 g_assert(ds); 3720 3721 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3722 qdev_unrealize(dev); 3723 spapr_pending_dimm_unplugs_remove(spapr, ds); 3724 } 3725 3726 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3727 DeviceState *dev, Error **errp) 3728 { 3729 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3730 PCDIMMDevice *dimm = PC_DIMM(dev); 3731 uint32_t nr_lmbs; 3732 uint64_t size, addr_start, addr; 3733 int i; 3734 SpaprDrc *drc; 3735 3736 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3737 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3738 return; 3739 } 3740 3741 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3742 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3743 3744 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3745 &error_abort); 3746 3747 /* 3748 * An existing pending dimm state for this DIMM means that there is an 3749 * unplug operation in progress, waiting for the spapr_lmb_release 3750 * callback to complete the job (BQL can't cover that far). In this case, 3751 * bail out to avoid detaching DRCs that were already released. 3752 */ 3753 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3754 error_setg(errp, "Memory unplug already in progress for device %s", 3755 dev->id); 3756 return; 3757 } 3758 3759 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3760 3761 addr = addr_start; 3762 for (i = 0; i < nr_lmbs; i++) { 3763 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3764 addr / SPAPR_MEMORY_BLOCK_SIZE); 3765 g_assert(drc); 3766 3767 spapr_drc_unplug_request(drc); 3768 addr += SPAPR_MEMORY_BLOCK_SIZE; 3769 } 3770 3771 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3772 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3773 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3774 nr_lmbs, spapr_drc_index(drc)); 3775 } 3776 3777 /* Callback to be called during DRC release. */ 3778 void spapr_core_release(DeviceState *dev) 3779 { 3780 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3781 3782 /* Call the unplug handler chain. This can never fail. */ 3783 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3784 object_unparent(OBJECT(dev)); 3785 } 3786 3787 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3788 { 3789 MachineState *ms = MACHINE(hotplug_dev); 3790 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3791 CPUCore *cc = CPU_CORE(dev); 3792 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3793 3794 if (smc->pre_2_10_has_unused_icps) { 3795 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3796 int i; 3797 3798 for (i = 0; i < cc->nr_threads; i++) { 3799 CPUState *cs = CPU(sc->threads[i]); 3800 3801 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3802 } 3803 } 3804 3805 assert(core_slot); 3806 core_slot->cpu = NULL; 3807 qdev_unrealize(dev); 3808 } 3809 3810 static 3811 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3812 Error **errp) 3813 { 3814 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3815 int index; 3816 SpaprDrc *drc; 3817 CPUCore *cc = CPU_CORE(dev); 3818 3819 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3820 error_setg(errp, "Unable to find CPU core with core-id: %d", 3821 cc->core_id); 3822 return; 3823 } 3824 if (index == 0) { 3825 error_setg(errp, "Boot CPU core may not be unplugged"); 3826 return; 3827 } 3828 3829 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3830 spapr_vcpu_id(spapr, cc->core_id)); 3831 g_assert(drc); 3832 3833 if (!spapr_drc_unplug_requested(drc)) { 3834 spapr_drc_unplug_request(drc); 3835 } 3836 3837 /* 3838 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3839 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3840 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3841 * attempt (e.g. the kernel will refuse to remove the last online 3842 * CPU), we will never attempt it again because unplug_requested 3843 * will still be 'true' in that case. 3844 */ 3845 spapr_hotplug_req_remove_by_index(drc); 3846 } 3847 3848 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3849 void *fdt, int *fdt_start_offset, Error **errp) 3850 { 3851 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3852 CPUState *cs = CPU(core->threads[0]); 3853 PowerPCCPU *cpu = POWERPC_CPU(cs); 3854 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3855 int id = spapr_get_vcpu_id(cpu); 3856 g_autofree char *nodename = NULL; 3857 int offset; 3858 3859 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3860 offset = fdt_add_subnode(fdt, 0, nodename); 3861 3862 spapr_dt_cpu(cs, fdt, offset, spapr); 3863 3864 /* 3865 * spapr_dt_cpu() does not fill the 'name' property in the 3866 * CPU node. The function is called during boot process, before 3867 * and after CAS, and overwriting the 'name' property written 3868 * by SLOF is not allowed. 3869 * 3870 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3871 * CPUs more compatible with the coldplugged ones, which have 3872 * the 'name' property. Linux Kernel also relies on this 3873 * property to identify CPU nodes. 3874 */ 3875 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3876 3877 *fdt_start_offset = offset; 3878 return 0; 3879 } 3880 3881 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3882 { 3883 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3884 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3885 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3886 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3887 CPUCore *cc = CPU_CORE(dev); 3888 CPUState *cs; 3889 SpaprDrc *drc; 3890 CPUArchId *core_slot; 3891 int index; 3892 bool hotplugged = spapr_drc_hotplugged(dev); 3893 int i; 3894 3895 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3896 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3897 3898 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3899 spapr_vcpu_id(spapr, cc->core_id)); 3900 3901 g_assert(drc || !mc->has_hotpluggable_cpus); 3902 3903 if (drc) { 3904 /* 3905 * spapr_core_pre_plug() already buys us this is a brand new 3906 * core being plugged into a free slot. Nothing should already 3907 * be attached to the corresponding DRC. 3908 */ 3909 spapr_drc_attach(drc, dev); 3910 3911 if (hotplugged) { 3912 /* 3913 * Send hotplug notification interrupt to the guest only 3914 * in case of hotplugged CPUs. 3915 */ 3916 spapr_hotplug_req_add_by_index(drc); 3917 } else { 3918 spapr_drc_reset(drc); 3919 } 3920 } 3921 3922 core_slot->cpu = OBJECT(dev); 3923 3924 /* 3925 * Set compatibility mode to match the boot CPU, which was either set 3926 * by the machine reset code or by CAS. This really shouldn't fail at 3927 * this point. 3928 */ 3929 if (hotplugged) { 3930 for (i = 0; i < cc->nr_threads; i++) { 3931 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3932 &error_abort); 3933 } 3934 } 3935 3936 if (smc->pre_2_10_has_unused_icps) { 3937 for (i = 0; i < cc->nr_threads; i++) { 3938 cs = CPU(core->threads[i]); 3939 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3940 } 3941 } 3942 } 3943 3944 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3945 Error **errp) 3946 { 3947 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3948 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3949 CPUCore *cc = CPU_CORE(dev); 3950 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3951 const char *type = object_get_typename(OBJECT(dev)); 3952 CPUArchId *core_slot; 3953 int index; 3954 unsigned int smp_threads = machine->smp.threads; 3955 3956 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3957 error_setg(errp, "CPU hotplug not supported for this machine"); 3958 return; 3959 } 3960 3961 if (strcmp(base_core_type, type)) { 3962 error_setg(errp, "CPU core type should be %s", base_core_type); 3963 return; 3964 } 3965 3966 if (cc->core_id % smp_threads) { 3967 error_setg(errp, "invalid core id %d", cc->core_id); 3968 return; 3969 } 3970 3971 /* 3972 * In general we should have homogeneous threads-per-core, but old 3973 * (pre hotplug support) machine types allow the last core to have 3974 * reduced threads as a compatibility hack for when we allowed 3975 * total vcpus not a multiple of threads-per-core. 3976 */ 3977 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3978 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3979 smp_threads); 3980 return; 3981 } 3982 3983 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3984 if (!core_slot) { 3985 error_setg(errp, "core id %d out of range", cc->core_id); 3986 return; 3987 } 3988 3989 if (core_slot->cpu) { 3990 error_setg(errp, "core %d already populated", cc->core_id); 3991 return; 3992 } 3993 3994 numa_cpu_pre_plug(core_slot, dev, errp); 3995 } 3996 3997 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3998 void *fdt, int *fdt_start_offset, Error **errp) 3999 { 4000 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4001 int intc_phandle; 4002 4003 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4004 if (intc_phandle <= 0) { 4005 return -1; 4006 } 4007 4008 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4009 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4010 return -1; 4011 } 4012 4013 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4014 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4015 4016 return 0; 4017 } 4018 4019 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4020 Error **errp) 4021 { 4022 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4023 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4024 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4025 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4026 SpaprDrc *drc; 4027 4028 if (dev->hotplugged && !smc->dr_phb_enabled) { 4029 error_setg(errp, "PHB hotplug not supported for this machine"); 4030 return false; 4031 } 4032 4033 if (sphb->index == (uint32_t)-1) { 4034 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4035 return false; 4036 } 4037 4038 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4039 if (drc && drc->dev) { 4040 error_setg(errp, "PHB %d already attached", sphb->index); 4041 return false; 4042 } 4043 4044 /* 4045 * This will check that sphb->index doesn't exceed the maximum number of 4046 * PHBs for the current machine type. 4047 */ 4048 return 4049 smc->phb_placement(spapr, sphb->index, 4050 &sphb->buid, &sphb->io_win_addr, 4051 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4052 windows_supported, sphb->dma_liobn, 4053 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4054 errp); 4055 } 4056 4057 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4058 { 4059 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4060 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4061 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4062 SpaprDrc *drc; 4063 bool hotplugged = spapr_drc_hotplugged(dev); 4064 4065 if (!smc->dr_phb_enabled) { 4066 return; 4067 } 4068 4069 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4070 /* hotplug hooks should check it's enabled before getting this far */ 4071 assert(drc); 4072 4073 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4074 spapr_drc_attach(drc, dev); 4075 4076 if (hotplugged) { 4077 spapr_hotplug_req_add_by_index(drc); 4078 } else { 4079 spapr_drc_reset(drc); 4080 } 4081 } 4082 4083 void spapr_phb_release(DeviceState *dev) 4084 { 4085 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4086 4087 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4088 object_unparent(OBJECT(dev)); 4089 } 4090 4091 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4092 { 4093 qdev_unrealize(dev); 4094 } 4095 4096 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4097 DeviceState *dev, Error **errp) 4098 { 4099 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4100 SpaprDrc *drc; 4101 4102 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4103 assert(drc); 4104 4105 if (!spapr_drc_unplug_requested(drc)) { 4106 spapr_drc_unplug_request(drc); 4107 spapr_hotplug_req_remove_by_index(drc); 4108 } else { 4109 error_setg(errp, 4110 "PCI Host Bridge unplug already in progress for device %s", 4111 dev->id); 4112 } 4113 } 4114 4115 static 4116 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4117 Error **errp) 4118 { 4119 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4120 4121 if (spapr->tpm_proxy != NULL) { 4122 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4123 return false; 4124 } 4125 4126 return true; 4127 } 4128 4129 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4130 { 4131 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4132 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4133 4134 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4135 g_assert(spapr->tpm_proxy == NULL); 4136 4137 spapr->tpm_proxy = tpm_proxy; 4138 } 4139 4140 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4141 { 4142 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4143 4144 qdev_unrealize(dev); 4145 object_unparent(OBJECT(dev)); 4146 spapr->tpm_proxy = NULL; 4147 } 4148 4149 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4150 DeviceState *dev, Error **errp) 4151 { 4152 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4153 spapr_memory_plug(hotplug_dev, dev); 4154 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4155 spapr_core_plug(hotplug_dev, dev); 4156 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4157 spapr_phb_plug(hotplug_dev, dev); 4158 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4159 spapr_tpm_proxy_plug(hotplug_dev, dev); 4160 } 4161 } 4162 4163 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4164 DeviceState *dev, Error **errp) 4165 { 4166 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4167 spapr_memory_unplug(hotplug_dev, dev); 4168 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4169 spapr_core_unplug(hotplug_dev, dev); 4170 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4171 spapr_phb_unplug(hotplug_dev, dev); 4172 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4173 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4174 } 4175 } 4176 4177 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4178 { 4179 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4180 /* 4181 * CAS will process all pending unplug requests. 4182 * 4183 * HACK: a guest could theoretically have cleared all bits in OV5, 4184 * but none of the guests we care for do. 4185 */ 4186 spapr_ovec_empty(spapr->ov5_cas); 4187 } 4188 4189 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4190 DeviceState *dev, Error **errp) 4191 { 4192 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4193 MachineClass *mc = MACHINE_GET_CLASS(sms); 4194 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4195 4196 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4197 if (spapr_memory_hot_unplug_supported(sms)) { 4198 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4199 } else { 4200 error_setg(errp, "Memory hot unplug not supported for this guest"); 4201 } 4202 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4203 if (!mc->has_hotpluggable_cpus) { 4204 error_setg(errp, "CPU hot unplug not supported on this machine"); 4205 return; 4206 } 4207 spapr_core_unplug_request(hotplug_dev, dev, errp); 4208 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4209 if (!smc->dr_phb_enabled) { 4210 error_setg(errp, "PHB hot unplug not supported on this machine"); 4211 return; 4212 } 4213 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4214 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4215 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4216 } 4217 } 4218 4219 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4220 DeviceState *dev, Error **errp) 4221 { 4222 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4223 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4224 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4225 spapr_core_pre_plug(hotplug_dev, dev, errp); 4226 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4227 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4228 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4229 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4230 } 4231 } 4232 4233 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4234 DeviceState *dev) 4235 { 4236 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4237 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4238 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4239 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4240 return HOTPLUG_HANDLER(machine); 4241 } 4242 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4243 PCIDevice *pcidev = PCI_DEVICE(dev); 4244 PCIBus *root = pci_device_root_bus(pcidev); 4245 SpaprPhbState *phb = 4246 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4247 TYPE_SPAPR_PCI_HOST_BRIDGE); 4248 4249 if (phb) { 4250 return HOTPLUG_HANDLER(phb); 4251 } 4252 } 4253 return NULL; 4254 } 4255 4256 static CpuInstanceProperties 4257 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4258 { 4259 CPUArchId *core_slot; 4260 MachineClass *mc = MACHINE_GET_CLASS(machine); 4261 4262 /* make sure possible_cpu are intialized */ 4263 mc->possible_cpu_arch_ids(machine); 4264 /* get CPU core slot containing thread that matches cpu_index */ 4265 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4266 assert(core_slot); 4267 return core_slot->props; 4268 } 4269 4270 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4271 { 4272 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4273 } 4274 4275 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4276 { 4277 int i; 4278 unsigned int smp_threads = machine->smp.threads; 4279 unsigned int smp_cpus = machine->smp.cpus; 4280 const char *core_type; 4281 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4282 MachineClass *mc = MACHINE_GET_CLASS(machine); 4283 4284 if (!mc->has_hotpluggable_cpus) { 4285 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4286 } 4287 if (machine->possible_cpus) { 4288 assert(machine->possible_cpus->len == spapr_max_cores); 4289 return machine->possible_cpus; 4290 } 4291 4292 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4293 if (!core_type) { 4294 error_report("Unable to find sPAPR CPU Core definition"); 4295 exit(1); 4296 } 4297 4298 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4299 sizeof(CPUArchId) * spapr_max_cores); 4300 machine->possible_cpus->len = spapr_max_cores; 4301 for (i = 0; i < machine->possible_cpus->len; i++) { 4302 int core_id = i * smp_threads; 4303 4304 machine->possible_cpus->cpus[i].type = core_type; 4305 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4306 machine->possible_cpus->cpus[i].arch_id = core_id; 4307 machine->possible_cpus->cpus[i].props.has_core_id = true; 4308 machine->possible_cpus->cpus[i].props.core_id = core_id; 4309 } 4310 return machine->possible_cpus; 4311 } 4312 4313 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4314 uint64_t *buid, hwaddr *pio, 4315 hwaddr *mmio32, hwaddr *mmio64, 4316 unsigned n_dma, uint32_t *liobns, 4317 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4318 { 4319 /* 4320 * New-style PHB window placement. 4321 * 4322 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4323 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4324 * windows. 4325 * 4326 * Some guest kernels can't work with MMIO windows above 1<<46 4327 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4328 * 4329 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4330 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4331 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4332 * 1TiB 64-bit MMIO windows for each PHB. 4333 */ 4334 const uint64_t base_buid = 0x800000020000000ULL; 4335 int i; 4336 4337 /* Sanity check natural alignments */ 4338 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4339 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4340 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4341 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4342 /* Sanity check bounds */ 4343 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4344 SPAPR_PCI_MEM32_WIN_SIZE); 4345 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4346 SPAPR_PCI_MEM64_WIN_SIZE); 4347 4348 if (index >= SPAPR_MAX_PHBS) { 4349 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4350 SPAPR_MAX_PHBS - 1); 4351 return false; 4352 } 4353 4354 *buid = base_buid + index; 4355 for (i = 0; i < n_dma; ++i) { 4356 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4357 } 4358 4359 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4360 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4361 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4362 4363 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4364 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4365 return true; 4366 } 4367 4368 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4369 { 4370 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4371 4372 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4373 } 4374 4375 static void spapr_ics_resend(XICSFabric *dev) 4376 { 4377 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4378 4379 ics_resend(spapr->ics); 4380 } 4381 4382 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4383 { 4384 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4385 4386 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4387 } 4388 4389 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4390 Monitor *mon) 4391 { 4392 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4393 4394 spapr_irq_print_info(spapr, mon); 4395 monitor_printf(mon, "irqchip: %s\n", 4396 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4397 } 4398 4399 /* 4400 * This is a XIVE only operation 4401 */ 4402 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4403 uint8_t nvt_blk, uint32_t nvt_idx, 4404 bool cam_ignore, uint8_t priority, 4405 uint32_t logic_serv, XiveTCTXMatch *match) 4406 { 4407 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4408 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4409 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4410 int count; 4411 4412 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4413 priority, logic_serv, match); 4414 if (count < 0) { 4415 return count; 4416 } 4417 4418 /* 4419 * When we implement the save and restore of the thread interrupt 4420 * contexts in the enter/exit CPU handlers of the machine and the 4421 * escalations in QEMU, we should be able to handle non dispatched 4422 * vCPUs. 4423 * 4424 * Until this is done, the sPAPR machine should find at least one 4425 * matching context always. 4426 */ 4427 if (count == 0) { 4428 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4429 nvt_blk, nvt_idx); 4430 } 4431 4432 return count; 4433 } 4434 4435 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4436 { 4437 return cpu->vcpu_id; 4438 } 4439 4440 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4441 { 4442 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4443 MachineState *ms = MACHINE(spapr); 4444 int vcpu_id; 4445 4446 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4447 4448 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4449 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4450 error_append_hint(errp, "Adjust the number of cpus to %d " 4451 "or try to raise the number of threads per core\n", 4452 vcpu_id * ms->smp.threads / spapr->vsmt); 4453 return false; 4454 } 4455 4456 cpu->vcpu_id = vcpu_id; 4457 return true; 4458 } 4459 4460 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4461 { 4462 CPUState *cs; 4463 4464 CPU_FOREACH(cs) { 4465 PowerPCCPU *cpu = POWERPC_CPU(cs); 4466 4467 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4468 return cpu; 4469 } 4470 } 4471 4472 return NULL; 4473 } 4474 4475 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4476 { 4477 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4478 4479 /* These are only called by TCG, KVM maintains dispatch state */ 4480 4481 spapr_cpu->prod = false; 4482 if (spapr_cpu->vpa_addr) { 4483 CPUState *cs = CPU(cpu); 4484 uint32_t dispatch; 4485 4486 dispatch = ldl_be_phys(cs->as, 4487 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4488 dispatch++; 4489 if ((dispatch & 1) != 0) { 4490 qemu_log_mask(LOG_GUEST_ERROR, 4491 "VPA: incorrect dispatch counter value for " 4492 "dispatched partition %u, correcting.\n", dispatch); 4493 dispatch++; 4494 } 4495 stl_be_phys(cs->as, 4496 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4497 } 4498 } 4499 4500 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4501 { 4502 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4503 4504 if (spapr_cpu->vpa_addr) { 4505 CPUState *cs = CPU(cpu); 4506 uint32_t dispatch; 4507 4508 dispatch = ldl_be_phys(cs->as, 4509 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4510 dispatch++; 4511 if ((dispatch & 1) != 1) { 4512 qemu_log_mask(LOG_GUEST_ERROR, 4513 "VPA: incorrect dispatch counter value for " 4514 "preempted partition %u, correcting.\n", dispatch); 4515 dispatch++; 4516 } 4517 stl_be_phys(cs->as, 4518 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4519 } 4520 } 4521 4522 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4523 { 4524 MachineClass *mc = MACHINE_CLASS(oc); 4525 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4526 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4527 NMIClass *nc = NMI_CLASS(oc); 4528 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4529 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4530 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4531 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4532 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4533 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4534 4535 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4536 mc->ignore_boot_device_suffixes = true; 4537 4538 /* 4539 * We set up the default / latest behaviour here. The class_init 4540 * functions for the specific versioned machine types can override 4541 * these details for backwards compatibility 4542 */ 4543 mc->init = spapr_machine_init; 4544 mc->reset = spapr_machine_reset; 4545 mc->block_default_type = IF_SCSI; 4546 4547 /* 4548 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4549 * should be limited by the host capability instead of hardcoded. 4550 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4551 * guests are welcome to have as many CPUs as the host are capable 4552 * of emulate. 4553 */ 4554 mc->max_cpus = INT32_MAX; 4555 4556 mc->no_parallel = 1; 4557 mc->default_boot_order = ""; 4558 mc->default_ram_size = 512 * MiB; 4559 mc->default_ram_id = "ppc_spapr.ram"; 4560 mc->default_display = "std"; 4561 mc->kvm_type = spapr_kvm_type; 4562 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4563 mc->pci_allow_0_address = true; 4564 assert(!mc->get_hotplug_handler); 4565 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4566 hc->pre_plug = spapr_machine_device_pre_plug; 4567 hc->plug = spapr_machine_device_plug; 4568 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4569 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4570 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4571 hc->unplug_request = spapr_machine_device_unplug_request; 4572 hc->unplug = spapr_machine_device_unplug; 4573 4574 smc->dr_lmb_enabled = true; 4575 smc->update_dt_enabled = true; 4576 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4577 mc->has_hotpluggable_cpus = true; 4578 mc->nvdimm_supported = true; 4579 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4580 fwc->get_dev_path = spapr_get_fw_dev_path; 4581 nc->nmi_monitor_handler = spapr_nmi; 4582 smc->phb_placement = spapr_phb_placement; 4583 vhc->hypercall = emulate_spapr_hypercall; 4584 vhc->hpt_mask = spapr_hpt_mask; 4585 vhc->map_hptes = spapr_map_hptes; 4586 vhc->unmap_hptes = spapr_unmap_hptes; 4587 vhc->hpte_set_c = spapr_hpte_set_c; 4588 vhc->hpte_set_r = spapr_hpte_set_r; 4589 vhc->get_pate = spapr_get_pate; 4590 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4591 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4592 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4593 xic->ics_get = spapr_ics_get; 4594 xic->ics_resend = spapr_ics_resend; 4595 xic->icp_get = spapr_icp_get; 4596 ispc->print_info = spapr_pic_print_info; 4597 /* Force NUMA node memory size to be a multiple of 4598 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4599 * in which LMBs are represented and hot-added 4600 */ 4601 mc->numa_mem_align_shift = 28; 4602 mc->auto_enable_numa = true; 4603 4604 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4605 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4606 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4607 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4608 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4609 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4610 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4611 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4612 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4613 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4614 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4615 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4616 spapr_caps_add_properties(smc); 4617 smc->irq = &spapr_irq_dual; 4618 smc->dr_phb_enabled = true; 4619 smc->linux_pci_probe = true; 4620 smc->smp_threads_vsmt = true; 4621 smc->nr_xirqs = SPAPR_NR_XIRQS; 4622 xfc->match_nvt = spapr_match_nvt; 4623 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4624 vmc->quiesce = spapr_vof_quiesce; 4625 vmc->setprop = spapr_vof_setprop; 4626 } 4627 4628 static const TypeInfo spapr_machine_info = { 4629 .name = TYPE_SPAPR_MACHINE, 4630 .parent = TYPE_MACHINE, 4631 .abstract = true, 4632 .instance_size = sizeof(SpaprMachineState), 4633 .instance_init = spapr_instance_init, 4634 .instance_finalize = spapr_machine_finalizefn, 4635 .class_size = sizeof(SpaprMachineClass), 4636 .class_init = spapr_machine_class_init, 4637 .interfaces = (InterfaceInfo[]) { 4638 { TYPE_FW_PATH_PROVIDER }, 4639 { TYPE_NMI }, 4640 { TYPE_HOTPLUG_HANDLER }, 4641 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4642 { TYPE_XICS_FABRIC }, 4643 { TYPE_INTERRUPT_STATS_PROVIDER }, 4644 { TYPE_XIVE_FABRIC }, 4645 { TYPE_VOF_MACHINE_IF }, 4646 { } 4647 }, 4648 }; 4649 4650 static void spapr_machine_latest_class_options(MachineClass *mc) 4651 { 4652 mc->alias = "pseries"; 4653 mc->is_default = true; 4654 } 4655 4656 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4657 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4658 void *data) \ 4659 { \ 4660 MachineClass *mc = MACHINE_CLASS(oc); \ 4661 spapr_machine_##suffix##_class_options(mc); \ 4662 if (latest) { \ 4663 spapr_machine_latest_class_options(mc); \ 4664 } \ 4665 } \ 4666 static const TypeInfo spapr_machine_##suffix##_info = { \ 4667 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4668 .parent = TYPE_SPAPR_MACHINE, \ 4669 .class_init = spapr_machine_##suffix##_class_init, \ 4670 }; \ 4671 static void spapr_machine_register_##suffix(void) \ 4672 { \ 4673 type_register(&spapr_machine_##suffix##_info); \ 4674 } \ 4675 type_init(spapr_machine_register_##suffix) 4676 4677 /* 4678 * pseries-7.0 4679 */ 4680 static void spapr_machine_7_0_class_options(MachineClass *mc) 4681 { 4682 /* Defaults for the latest behaviour inherited from the base class */ 4683 } 4684 4685 DEFINE_SPAPR_MACHINE(7_0, "7.0", true); 4686 4687 /* 4688 * pseries-6.2 4689 */ 4690 static void spapr_machine_6_2_class_options(MachineClass *mc) 4691 { 4692 spapr_machine_7_0_class_options(mc); 4693 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4694 } 4695 4696 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4697 4698 /* 4699 * pseries-6.1 4700 */ 4701 static void spapr_machine_6_1_class_options(MachineClass *mc) 4702 { 4703 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4704 4705 spapr_machine_6_2_class_options(mc); 4706 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4707 smc->pre_6_2_numa_affinity = true; 4708 mc->smp_props.prefer_sockets = true; 4709 } 4710 4711 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4712 4713 /* 4714 * pseries-6.0 4715 */ 4716 static void spapr_machine_6_0_class_options(MachineClass *mc) 4717 { 4718 spapr_machine_6_1_class_options(mc); 4719 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4720 } 4721 4722 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4723 4724 /* 4725 * pseries-5.2 4726 */ 4727 static void spapr_machine_5_2_class_options(MachineClass *mc) 4728 { 4729 spapr_machine_6_0_class_options(mc); 4730 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4731 } 4732 4733 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4734 4735 /* 4736 * pseries-5.1 4737 */ 4738 static void spapr_machine_5_1_class_options(MachineClass *mc) 4739 { 4740 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4741 4742 spapr_machine_5_2_class_options(mc); 4743 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4744 smc->pre_5_2_numa_associativity = true; 4745 } 4746 4747 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4748 4749 /* 4750 * pseries-5.0 4751 */ 4752 static void spapr_machine_5_0_class_options(MachineClass *mc) 4753 { 4754 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4755 static GlobalProperty compat[] = { 4756 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4757 }; 4758 4759 spapr_machine_5_1_class_options(mc); 4760 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4761 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4762 mc->numa_mem_supported = true; 4763 smc->pre_5_1_assoc_refpoints = true; 4764 } 4765 4766 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4767 4768 /* 4769 * pseries-4.2 4770 */ 4771 static void spapr_machine_4_2_class_options(MachineClass *mc) 4772 { 4773 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4774 4775 spapr_machine_5_0_class_options(mc); 4776 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4777 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4778 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4779 smc->rma_limit = 16 * GiB; 4780 mc->nvdimm_supported = false; 4781 } 4782 4783 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4784 4785 /* 4786 * pseries-4.1 4787 */ 4788 static void spapr_machine_4_1_class_options(MachineClass *mc) 4789 { 4790 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4791 static GlobalProperty compat[] = { 4792 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4793 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4794 }; 4795 4796 spapr_machine_4_2_class_options(mc); 4797 smc->linux_pci_probe = false; 4798 smc->smp_threads_vsmt = false; 4799 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4800 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4801 } 4802 4803 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4804 4805 /* 4806 * pseries-4.0 4807 */ 4808 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4809 uint64_t *buid, hwaddr *pio, 4810 hwaddr *mmio32, hwaddr *mmio64, 4811 unsigned n_dma, uint32_t *liobns, 4812 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4813 { 4814 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4815 liobns, nv2gpa, nv2atsd, errp)) { 4816 return false; 4817 } 4818 4819 *nv2gpa = 0; 4820 *nv2atsd = 0; 4821 return true; 4822 } 4823 static void spapr_machine_4_0_class_options(MachineClass *mc) 4824 { 4825 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4826 4827 spapr_machine_4_1_class_options(mc); 4828 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4829 smc->phb_placement = phb_placement_4_0; 4830 smc->irq = &spapr_irq_xics; 4831 smc->pre_4_1_migration = true; 4832 } 4833 4834 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4835 4836 /* 4837 * pseries-3.1 4838 */ 4839 static void spapr_machine_3_1_class_options(MachineClass *mc) 4840 { 4841 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4842 4843 spapr_machine_4_0_class_options(mc); 4844 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4845 4846 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4847 smc->update_dt_enabled = false; 4848 smc->dr_phb_enabled = false; 4849 smc->broken_host_serial_model = true; 4850 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4851 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4852 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4853 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4854 } 4855 4856 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4857 4858 /* 4859 * pseries-3.0 4860 */ 4861 4862 static void spapr_machine_3_0_class_options(MachineClass *mc) 4863 { 4864 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4865 4866 spapr_machine_3_1_class_options(mc); 4867 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4868 4869 smc->legacy_irq_allocation = true; 4870 smc->nr_xirqs = 0x400; 4871 smc->irq = &spapr_irq_xics_legacy; 4872 } 4873 4874 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4875 4876 /* 4877 * pseries-2.12 4878 */ 4879 static void spapr_machine_2_12_class_options(MachineClass *mc) 4880 { 4881 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4882 static GlobalProperty compat[] = { 4883 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4884 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4885 }; 4886 4887 spapr_machine_3_0_class_options(mc); 4888 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4889 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4890 4891 /* We depend on kvm_enabled() to choose a default value for the 4892 * hpt-max-page-size capability. Of course we can't do it here 4893 * because this is too early and the HW accelerator isn't initialzed 4894 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4895 */ 4896 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4897 } 4898 4899 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4900 4901 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4902 { 4903 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4904 4905 spapr_machine_2_12_class_options(mc); 4906 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4907 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4908 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4909 } 4910 4911 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4912 4913 /* 4914 * pseries-2.11 4915 */ 4916 4917 static void spapr_machine_2_11_class_options(MachineClass *mc) 4918 { 4919 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4920 4921 spapr_machine_2_12_class_options(mc); 4922 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4923 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4924 } 4925 4926 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4927 4928 /* 4929 * pseries-2.10 4930 */ 4931 4932 static void spapr_machine_2_10_class_options(MachineClass *mc) 4933 { 4934 spapr_machine_2_11_class_options(mc); 4935 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4936 } 4937 4938 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4939 4940 /* 4941 * pseries-2.9 4942 */ 4943 4944 static void spapr_machine_2_9_class_options(MachineClass *mc) 4945 { 4946 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4947 static GlobalProperty compat[] = { 4948 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4949 }; 4950 4951 spapr_machine_2_10_class_options(mc); 4952 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4953 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4954 smc->pre_2_10_has_unused_icps = true; 4955 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4956 } 4957 4958 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4959 4960 /* 4961 * pseries-2.8 4962 */ 4963 4964 static void spapr_machine_2_8_class_options(MachineClass *mc) 4965 { 4966 static GlobalProperty compat[] = { 4967 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4968 }; 4969 4970 spapr_machine_2_9_class_options(mc); 4971 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4972 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4973 mc->numa_mem_align_shift = 23; 4974 } 4975 4976 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4977 4978 /* 4979 * pseries-2.7 4980 */ 4981 4982 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4983 uint64_t *buid, hwaddr *pio, 4984 hwaddr *mmio32, hwaddr *mmio64, 4985 unsigned n_dma, uint32_t *liobns, 4986 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4987 { 4988 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4989 const uint64_t base_buid = 0x800000020000000ULL; 4990 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4991 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4992 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4993 const uint32_t max_index = 255; 4994 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4995 4996 uint64_t ram_top = MACHINE(spapr)->ram_size; 4997 hwaddr phb0_base, phb_base; 4998 int i; 4999 5000 /* Do we have device memory? */ 5001 if (MACHINE(spapr)->maxram_size > ram_top) { 5002 /* Can't just use maxram_size, because there may be an 5003 * alignment gap between normal and device memory regions 5004 */ 5005 ram_top = MACHINE(spapr)->device_memory->base + 5006 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5007 } 5008 5009 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5010 5011 if (index > max_index) { 5012 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5013 max_index); 5014 return false; 5015 } 5016 5017 *buid = base_buid + index; 5018 for (i = 0; i < n_dma; ++i) { 5019 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5020 } 5021 5022 phb_base = phb0_base + index * phb_spacing; 5023 *pio = phb_base + pio_offset; 5024 *mmio32 = phb_base + mmio_offset; 5025 /* 5026 * We don't set the 64-bit MMIO window, relying on the PHB's 5027 * fallback behaviour of automatically splitting a large "32-bit" 5028 * window into contiguous 32-bit and 64-bit windows 5029 */ 5030 5031 *nv2gpa = 0; 5032 *nv2atsd = 0; 5033 return true; 5034 } 5035 5036 static void spapr_machine_2_7_class_options(MachineClass *mc) 5037 { 5038 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5039 static GlobalProperty compat[] = { 5040 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5041 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5042 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5043 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5044 }; 5045 5046 spapr_machine_2_8_class_options(mc); 5047 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5048 mc->default_machine_opts = "modern-hotplug-events=off"; 5049 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5050 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5051 smc->phb_placement = phb_placement_2_7; 5052 } 5053 5054 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5055 5056 /* 5057 * pseries-2.6 5058 */ 5059 5060 static void spapr_machine_2_6_class_options(MachineClass *mc) 5061 { 5062 static GlobalProperty compat[] = { 5063 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5064 }; 5065 5066 spapr_machine_2_7_class_options(mc); 5067 mc->has_hotpluggable_cpus = false; 5068 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5069 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5070 } 5071 5072 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5073 5074 /* 5075 * pseries-2.5 5076 */ 5077 5078 static void spapr_machine_2_5_class_options(MachineClass *mc) 5079 { 5080 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5081 static GlobalProperty compat[] = { 5082 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5083 }; 5084 5085 spapr_machine_2_6_class_options(mc); 5086 smc->use_ohci_by_default = true; 5087 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5088 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5089 } 5090 5091 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5092 5093 /* 5094 * pseries-2.4 5095 */ 5096 5097 static void spapr_machine_2_4_class_options(MachineClass *mc) 5098 { 5099 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5100 5101 spapr_machine_2_5_class_options(mc); 5102 smc->dr_lmb_enabled = false; 5103 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5104 } 5105 5106 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5107 5108 /* 5109 * pseries-2.3 5110 */ 5111 5112 static void spapr_machine_2_3_class_options(MachineClass *mc) 5113 { 5114 static GlobalProperty compat[] = { 5115 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5116 }; 5117 spapr_machine_2_4_class_options(mc); 5118 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5119 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5120 } 5121 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5122 5123 /* 5124 * pseries-2.2 5125 */ 5126 5127 static void spapr_machine_2_2_class_options(MachineClass *mc) 5128 { 5129 static GlobalProperty compat[] = { 5130 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5131 }; 5132 5133 spapr_machine_2_3_class_options(mc); 5134 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5135 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5136 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5137 } 5138 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5139 5140 /* 5141 * pseries-2.1 5142 */ 5143 5144 static void spapr_machine_2_1_class_options(MachineClass *mc) 5145 { 5146 spapr_machine_2_2_class_options(mc); 5147 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5148 } 5149 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5150 5151 static void spapr_machine_register_types(void) 5152 { 5153 type_register_static(&spapr_machine_info); 5154 } 5155 5156 type_init(spapr_machine_register_types) 5157