1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define FDT_MAX_SIZE 0x100000 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 static void spapr_dt_pa_features(SpaprMachineState *spapr, 221 PowerPCCPU *cpu, 222 void *fdt, int offset) 223 { 224 uint8_t pa_features_206[] = { 6, 0, 225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 226 uint8_t pa_features_207[] = { 24, 0, 227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 231 uint8_t pa_features_300[] = { 66, 0, 232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 235 /* 6: DS207 */ 236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 237 /* 16: Vector */ 238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 247 /* 42: PM, 44: PC RA, 46: SC vec'd */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 249 /* 48: SIMD, 50: QP BFP, 52: String */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 251 /* 54: DecFP, 56: DecI, 58: SHA */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 253 /* 60: NM atomic, 62: RNG */ 254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (!pa_features) { 272 return; 273 } 274 275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 276 /* 277 * Note: we keep CI large pages off by default because a 64K capable 278 * guest provisioned with large pages might otherwise try to map a qemu 279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 280 * even if that qemu runs on a 4k host. 281 * We dd this bit back here if we are confident this is not an issue 282 */ 283 pa_features[3] |= 0x20; 284 } 285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 286 pa_features[24] |= 0x80; /* Transactional memory support */ 287 } 288 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 289 /* Workaround for broken kernels that attempt (guest) radix 290 * mode when they can't handle it, if they see the radix bit set 291 * in pa-features. So hide it from them. */ 292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 293 } 294 295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 296 } 297 298 static hwaddr spapr_node0_size(MachineState *machine) 299 { 300 if (machine->numa_state->num_nodes) { 301 int i; 302 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 303 if (machine->numa_state->nodes[i].node_mem) { 304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 305 machine->ram_size); 306 } 307 } 308 } 309 return machine->ram_size; 310 } 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start, 318 hwaddr size) 319 { 320 uint32_t associativity[] = { 321 cpu_to_be32(0x4), /* length */ 322 cpu_to_be32(0x0), cpu_to_be32(0x0), 323 cpu_to_be32(0x0), cpu_to_be32(nodeid) 324 }; 325 char mem_name[32]; 326 uint64_t mem_reg_property[2]; 327 int off; 328 329 mem_reg_property[0] = cpu_to_be64(start); 330 mem_reg_property[1] = cpu_to_be64(size); 331 332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 333 off = fdt_add_subnode(fdt, 0, mem_name); 334 _FDT(off); 335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 337 sizeof(mem_reg_property)))); 338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 339 sizeof(associativity)))); 340 return off; 341 } 342 343 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 344 { 345 MemoryDeviceInfoList *info; 346 347 for (info = list; info; info = info->next) { 348 MemoryDeviceInfo *value = info->value; 349 350 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 351 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 352 353 if (addr >= pcdimm_info->addr && 354 addr < (pcdimm_info->addr + pcdimm_info->size)) { 355 return pcdimm_info->node; 356 } 357 } 358 } 359 360 return -1; 361 } 362 363 struct sPAPRDrconfCellV2 { 364 uint32_t seq_lmbs; 365 uint64_t base_addr; 366 uint32_t drc_index; 367 uint32_t aa_index; 368 uint32_t flags; 369 } QEMU_PACKED; 370 371 typedef struct DrconfCellQueue { 372 struct sPAPRDrconfCellV2 cell; 373 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 374 } DrconfCellQueue; 375 376 static DrconfCellQueue * 377 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 378 uint32_t drc_index, uint32_t aa_index, 379 uint32_t flags) 380 { 381 DrconfCellQueue *elem; 382 383 elem = g_malloc0(sizeof(*elem)); 384 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 385 elem->cell.base_addr = cpu_to_be64(base_addr); 386 elem->cell.drc_index = cpu_to_be32(drc_index); 387 elem->cell.aa_index = cpu_to_be32(aa_index); 388 elem->cell.flags = cpu_to_be32(flags); 389 390 return elem; 391 } 392 393 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 394 int offset, MemoryDeviceInfoList *dimms) 395 { 396 MachineState *machine = MACHINE(spapr); 397 uint8_t *int_buf, *cur_index; 398 int ret; 399 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 400 uint64_t addr, cur_addr, size; 401 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 402 uint64_t mem_end = machine->device_memory->base + 403 memory_region_size(&machine->device_memory->mr); 404 uint32_t node, buf_len, nr_entries = 0; 405 SpaprDrc *drc; 406 DrconfCellQueue *elem, *next; 407 MemoryDeviceInfoList *info; 408 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 409 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 410 411 /* Entry to cover RAM and the gap area */ 412 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 413 SPAPR_LMB_FLAGS_RESERVED | 414 SPAPR_LMB_FLAGS_DRC_INVALID); 415 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 416 nr_entries++; 417 418 cur_addr = machine->device_memory->base; 419 for (info = dimms; info; info = info->next) { 420 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 421 422 addr = di->addr; 423 size = di->size; 424 node = di->node; 425 426 /* 427 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 428 * area is marked hotpluggable in the next iteration for the bigger 429 * chunk including the NVDIMM occupied area. 430 */ 431 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 432 continue; 433 434 /* Entry for hot-pluggable area */ 435 if (cur_addr < addr) { 436 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 437 g_assert(drc); 438 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 439 cur_addr, spapr_drc_index(drc), -1, 0); 440 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 441 nr_entries++; 442 } 443 444 /* Entry for DIMM */ 445 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 446 g_assert(drc); 447 elem = spapr_get_drconf_cell(size / lmb_size, addr, 448 spapr_drc_index(drc), node, 449 SPAPR_LMB_FLAGS_ASSIGNED); 450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 451 nr_entries++; 452 cur_addr = addr + size; 453 } 454 455 /* Entry for remaining hotpluggable area */ 456 if (cur_addr < mem_end) { 457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 458 g_assert(drc); 459 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 460 cur_addr, spapr_drc_index(drc), -1, 0); 461 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 462 nr_entries++; 463 } 464 465 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 466 int_buf = cur_index = g_malloc0(buf_len); 467 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 468 cur_index += sizeof(nr_entries); 469 470 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 471 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 472 cur_index += sizeof(elem->cell); 473 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 474 g_free(elem); 475 } 476 477 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 478 g_free(int_buf); 479 if (ret < 0) { 480 return -1; 481 } 482 return 0; 483 } 484 485 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 486 int offset, MemoryDeviceInfoList *dimms) 487 { 488 MachineState *machine = MACHINE(spapr); 489 int i, ret; 490 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 491 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 492 uint32_t nr_lmbs = (machine->device_memory->base + 493 memory_region_size(&machine->device_memory->mr)) / 494 lmb_size; 495 uint32_t *int_buf, *cur_index, buf_len; 496 497 /* 498 * Allocate enough buffer size to fit in ibm,dynamic-memory 499 */ 500 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 501 cur_index = int_buf = g_malloc0(buf_len); 502 int_buf[0] = cpu_to_be32(nr_lmbs); 503 cur_index++; 504 for (i = 0; i < nr_lmbs; i++) { 505 uint64_t addr = i * lmb_size; 506 uint32_t *dynamic_memory = cur_index; 507 508 if (i >= device_lmb_start) { 509 SpaprDrc *drc; 510 511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 512 g_assert(drc); 513 514 dynamic_memory[0] = cpu_to_be32(addr >> 32); 515 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 516 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 517 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 518 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 519 if (memory_region_present(get_system_memory(), addr)) { 520 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 521 } else { 522 dynamic_memory[5] = cpu_to_be32(0); 523 } 524 } else { 525 /* 526 * LMB information for RMA, boot time RAM and gap b/n RAM and 527 * device memory region -- all these are marked as reserved 528 * and as having no valid DRC. 529 */ 530 dynamic_memory[0] = cpu_to_be32(addr >> 32); 531 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 532 dynamic_memory[2] = cpu_to_be32(0); 533 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 534 dynamic_memory[4] = cpu_to_be32(-1); 535 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 536 SPAPR_LMB_FLAGS_DRC_INVALID); 537 } 538 539 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 540 } 541 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 542 g_free(int_buf); 543 if (ret < 0) { 544 return -1; 545 } 546 return 0; 547 } 548 549 /* 550 * Adds ibm,dynamic-reconfiguration-memory node. 551 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 552 * of this device tree node. 553 */ 554 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 555 void *fdt) 556 { 557 MachineState *machine = MACHINE(spapr); 558 int nb_numa_nodes = machine->numa_state->num_nodes; 559 int ret, i, offset; 560 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 561 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 562 uint32_t *int_buf, *cur_index, buf_len; 563 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 564 MemoryDeviceInfoList *dimms = NULL; 565 566 /* 567 * Don't create the node if there is no device memory 568 */ 569 if (machine->ram_size == machine->maxram_size) { 570 return 0; 571 } 572 573 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 574 575 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 576 sizeof(prop_lmb_size)); 577 if (ret < 0) { 578 return ret; 579 } 580 581 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 582 if (ret < 0) { 583 return ret; 584 } 585 586 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 587 if (ret < 0) { 588 return ret; 589 } 590 591 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 592 dimms = qmp_memory_device_list(); 593 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 594 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 595 } else { 596 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 597 } 598 qapi_free_MemoryDeviceInfoList(dimms); 599 600 if (ret < 0) { 601 return ret; 602 } 603 604 /* ibm,associativity-lookup-arrays */ 605 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 606 cur_index = int_buf = g_malloc0(buf_len); 607 int_buf[0] = cpu_to_be32(nr_nodes); 608 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 609 cur_index += 2; 610 for (i = 0; i < nr_nodes; i++) { 611 uint32_t associativity[] = { 612 cpu_to_be32(0x0), 613 cpu_to_be32(0x0), 614 cpu_to_be32(0x0), 615 cpu_to_be32(i) 616 }; 617 memcpy(cur_index, associativity, sizeof(associativity)); 618 cur_index += 4; 619 } 620 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 621 (cur_index - int_buf) * sizeof(uint32_t)); 622 g_free(int_buf); 623 624 return ret; 625 } 626 627 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 628 { 629 MachineState *machine = MACHINE(spapr); 630 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 631 hwaddr mem_start, node_size; 632 int i, nb_nodes = machine->numa_state->num_nodes; 633 NodeInfo *nodes = machine->numa_state->nodes; 634 635 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 636 if (!nodes[i].node_mem) { 637 continue; 638 } 639 if (mem_start >= machine->ram_size) { 640 node_size = 0; 641 } else { 642 node_size = nodes[i].node_mem; 643 if (node_size > machine->ram_size - mem_start) { 644 node_size = machine->ram_size - mem_start; 645 } 646 } 647 if (!mem_start) { 648 /* spapr_machine_init() checks for rma_size <= node0_size 649 * already */ 650 spapr_dt_memory_node(fdt, i, 0, spapr->rma_size); 651 mem_start += spapr->rma_size; 652 node_size -= spapr->rma_size; 653 } 654 for ( ; node_size; ) { 655 hwaddr sizetmp = pow2floor(node_size); 656 657 /* mem_start != 0 here */ 658 if (ctzl(mem_start) < ctzl(sizetmp)) { 659 sizetmp = 1ULL << ctzl(mem_start); 660 } 661 662 spapr_dt_memory_node(fdt, i, mem_start, sizetmp); 663 node_size -= sizetmp; 664 mem_start += sizetmp; 665 } 666 } 667 668 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 669 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 670 int ret; 671 672 g_assert(smc->dr_lmb_enabled); 673 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 674 if (ret) { 675 return ret; 676 } 677 } 678 679 return 0; 680 } 681 682 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 683 SpaprMachineState *spapr) 684 { 685 MachineState *ms = MACHINE(spapr); 686 PowerPCCPU *cpu = POWERPC_CPU(cs); 687 CPUPPCState *env = &cpu->env; 688 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 689 int index = spapr_get_vcpu_id(cpu); 690 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 691 0xffffffff, 0xffffffff}; 692 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 693 : SPAPR_TIMEBASE_FREQ; 694 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 695 uint32_t page_sizes_prop[64]; 696 size_t page_sizes_prop_size; 697 unsigned int smp_threads = ms->smp.threads; 698 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 699 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 700 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 701 SpaprDrc *drc; 702 int drc_index; 703 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 704 int i; 705 706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 707 if (drc) { 708 drc_index = spapr_drc_index(drc); 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 710 } 711 712 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 713 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 714 715 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 716 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 717 env->dcache_line_size))); 718 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 719 env->dcache_line_size))); 720 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 721 env->icache_line_size))); 722 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 723 env->icache_line_size))); 724 725 if (pcc->l1_dcache_size) { 726 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 727 pcc->l1_dcache_size))); 728 } else { 729 warn_report("Unknown L1 dcache size for cpu"); 730 } 731 if (pcc->l1_icache_size) { 732 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 733 pcc->l1_icache_size))); 734 } else { 735 warn_report("Unknown L1 icache size for cpu"); 736 } 737 738 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 739 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 740 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 741 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 742 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 743 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 744 745 if (env->spr_cb[SPR_PURR].oea_read) { 746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 747 } 748 if (env->spr_cb[SPR_SPURR].oea_read) { 749 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 750 } 751 752 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 753 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 754 segs, sizeof(segs)))); 755 } 756 757 /* Advertise VSX (vector extensions) if available 758 * 1 == VMX / Altivec available 759 * 2 == VSX available 760 * 761 * Only CPUs for which we create core types in spapr_cpu_core.c 762 * are possible, and all of those have VMX */ 763 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 764 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 765 } else { 766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 767 } 768 769 /* Advertise DFP (Decimal Floating Point) if available 770 * 0 / no property == no DFP 771 * 1 == DFP available */ 772 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 773 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 774 } 775 776 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 777 sizeof(page_sizes_prop)); 778 if (page_sizes_prop_size) { 779 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 780 page_sizes_prop, page_sizes_prop_size))); 781 } 782 783 spapr_dt_pa_features(spapr, cpu, fdt, offset); 784 785 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 786 cs->cpu_index / vcpus_per_socket))); 787 788 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 789 pft_size_prop, sizeof(pft_size_prop)))); 790 791 if (ms->numa_state->num_nodes > 1) { 792 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 793 } 794 795 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 796 797 if (pcc->radix_page_info) { 798 for (i = 0; i < pcc->radix_page_info->count; i++) { 799 radix_AP_encodings[i] = 800 cpu_to_be32(pcc->radix_page_info->entries[i]); 801 } 802 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 803 radix_AP_encodings, 804 pcc->radix_page_info->count * 805 sizeof(radix_AP_encodings[0])))); 806 } 807 808 /* 809 * We set this property to let the guest know that it can use the large 810 * decrementer and its width in bits. 811 */ 812 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 813 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 814 pcc->lrg_decr_bits))); 815 } 816 817 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 818 { 819 CPUState **rev; 820 CPUState *cs; 821 int n_cpus; 822 int cpus_offset; 823 char *nodename; 824 int i; 825 826 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 827 _FDT(cpus_offset); 828 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 829 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 830 831 /* 832 * We walk the CPUs in reverse order to ensure that CPU DT nodes 833 * created by fdt_add_subnode() end up in the right order in FDT 834 * for the guest kernel the enumerate the CPUs correctly. 835 * 836 * The CPU list cannot be traversed in reverse order, so we need 837 * to do extra work. 838 */ 839 n_cpus = 0; 840 rev = NULL; 841 CPU_FOREACH(cs) { 842 rev = g_renew(CPUState *, rev, n_cpus + 1); 843 rev[n_cpus++] = cs; 844 } 845 846 for (i = n_cpus - 1; i >= 0; i--) { 847 CPUState *cs = rev[i]; 848 PowerPCCPU *cpu = POWERPC_CPU(cs); 849 int index = spapr_get_vcpu_id(cpu); 850 DeviceClass *dc = DEVICE_GET_CLASS(cs); 851 int offset; 852 853 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 854 continue; 855 } 856 857 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 858 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 859 g_free(nodename); 860 _FDT(offset); 861 spapr_dt_cpu(cs, fdt, offset, spapr); 862 } 863 864 g_free(rev); 865 } 866 867 static int spapr_dt_rng(void *fdt) 868 { 869 int node; 870 int ret; 871 872 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 873 if (node <= 0) { 874 return -1; 875 } 876 ret = fdt_setprop_string(fdt, node, "device_type", 877 "ibm,platform-facilities"); 878 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 879 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 880 881 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 882 if (node <= 0) { 883 return -1; 884 } 885 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 886 887 return ret ? -1 : 0; 888 } 889 890 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 891 { 892 MachineState *ms = MACHINE(spapr); 893 int rtas; 894 GString *hypertas = g_string_sized_new(256); 895 GString *qemu_hypertas = g_string_sized_new(256); 896 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 897 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 898 memory_region_size(&MACHINE(spapr)->device_memory->mr); 899 uint32_t lrdr_capacity[] = { 900 cpu_to_be32(max_device_addr >> 32), 901 cpu_to_be32(max_device_addr & 0xffffffff), 902 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 903 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 904 }; 905 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 906 uint32_t maxdomains[] = { 907 cpu_to_be32(4), 908 maxdomain, 909 maxdomain, 910 maxdomain, 911 cpu_to_be32(spapr->gpu_numa_id), 912 }; 913 914 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 915 916 /* hypertas */ 917 add_str(hypertas, "hcall-pft"); 918 add_str(hypertas, "hcall-term"); 919 add_str(hypertas, "hcall-dabr"); 920 add_str(hypertas, "hcall-interrupt"); 921 add_str(hypertas, "hcall-tce"); 922 add_str(hypertas, "hcall-vio"); 923 add_str(hypertas, "hcall-splpar"); 924 add_str(hypertas, "hcall-join"); 925 add_str(hypertas, "hcall-bulk"); 926 add_str(hypertas, "hcall-set-mode"); 927 add_str(hypertas, "hcall-sprg0"); 928 add_str(hypertas, "hcall-copy"); 929 add_str(hypertas, "hcall-debug"); 930 add_str(hypertas, "hcall-vphn"); 931 add_str(qemu_hypertas, "hcall-memop1"); 932 933 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 934 add_str(hypertas, "hcall-multi-tce"); 935 } 936 937 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 938 add_str(hypertas, "hcall-hpt-resize"); 939 } 940 941 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 942 hypertas->str, hypertas->len)); 943 g_string_free(hypertas, TRUE); 944 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 945 qemu_hypertas->str, qemu_hypertas->len)); 946 g_string_free(qemu_hypertas, TRUE); 947 948 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 949 refpoints, sizeof(refpoints))); 950 951 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 952 maxdomains, sizeof(maxdomains))); 953 954 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_SIZE)); 955 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 956 RTAS_ERROR_LOG_MAX)); 957 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 958 RTAS_EVENT_SCAN_RATE)); 959 960 g_assert(msi_nonbroken); 961 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 962 963 /* 964 * According to PAPR, rtas ibm,os-term does not guarantee a return 965 * back to the guest cpu. 966 * 967 * While an additional ibm,extended-os-term property indicates 968 * that rtas call return will always occur. Set this property. 969 */ 970 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 971 972 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 973 lrdr_capacity, sizeof(lrdr_capacity))); 974 975 spapr_dt_rtas_tokens(fdt, rtas); 976 } 977 978 /* 979 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 980 * and the XIVE features that the guest may request and thus the valid 981 * values for bytes 23..26 of option vector 5: 982 */ 983 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 984 int chosen) 985 { 986 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 987 988 char val[2 * 4] = { 989 23, 0x00, /* XICS / XIVE mode */ 990 24, 0x00, /* Hash/Radix, filled in below. */ 991 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 992 26, 0x40, /* Radix options: GTSE == yes. */ 993 }; 994 995 if (spapr->irq->xics && spapr->irq->xive) { 996 val[1] = SPAPR_OV5_XIVE_BOTH; 997 } else if (spapr->irq->xive) { 998 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 999 } else { 1000 assert(spapr->irq->xics); 1001 val[1] = SPAPR_OV5_XIVE_LEGACY; 1002 } 1003 1004 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1005 first_ppc_cpu->compat_pvr)) { 1006 /* 1007 * If we're in a pre POWER9 compat mode then the guest should 1008 * do hash and use the legacy interrupt mode 1009 */ 1010 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1011 val[3] = 0x00; /* Hash */ 1012 } else if (kvm_enabled()) { 1013 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1014 val[3] = 0x80; /* OV5_MMU_BOTH */ 1015 } else if (kvmppc_has_cap_mmu_radix()) { 1016 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1017 } else { 1018 val[3] = 0x00; /* Hash */ 1019 } 1020 } else { 1021 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1022 val[3] = 0xC0; 1023 } 1024 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1025 val, sizeof(val))); 1026 } 1027 1028 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1029 { 1030 MachineState *machine = MACHINE(spapr); 1031 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1032 int chosen; 1033 1034 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1035 1036 if (reset) { 1037 const char *boot_device = machine->boot_order; 1038 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1039 size_t cb = 0; 1040 char *bootlist = get_boot_devices_list(&cb); 1041 1042 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1043 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1044 machine->kernel_cmdline)); 1045 } 1046 1047 if (spapr->initrd_size) { 1048 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1049 spapr->initrd_base)); 1050 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1051 spapr->initrd_base + spapr->initrd_size)); 1052 } 1053 1054 if (spapr->kernel_size) { 1055 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1056 cpu_to_be64(spapr->kernel_size) }; 1057 1058 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1059 &kprop, sizeof(kprop))); 1060 if (spapr->kernel_le) { 1061 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1062 } 1063 } 1064 if (boot_menu) { 1065 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1066 } 1067 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1068 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1069 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1070 1071 if (cb && bootlist) { 1072 int i; 1073 1074 for (i = 0; i < cb; i++) { 1075 if (bootlist[i] == '\n') { 1076 bootlist[i] = ' '; 1077 } 1078 } 1079 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1080 } 1081 1082 if (boot_device && strlen(boot_device)) { 1083 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1084 } 1085 1086 if (!spapr->has_graphics && stdout_path) { 1087 /* 1088 * "linux,stdout-path" and "stdout" properties are 1089 * deprecated by linux kernel. New platforms should only 1090 * use the "stdout-path" property. Set the new property 1091 * and continue using older property to remain compatible 1092 * with the existing firmware. 1093 */ 1094 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1095 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1096 } 1097 1098 /* 1099 * We can deal with BAR reallocation just fine, advertise it 1100 * to the guest 1101 */ 1102 if (smc->linux_pci_probe) { 1103 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1104 } 1105 1106 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1107 1108 g_free(stdout_path); 1109 g_free(bootlist); 1110 } 1111 1112 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1113 } 1114 1115 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1116 { 1117 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1118 * KVM to work under pHyp with some guest co-operation */ 1119 int hypervisor; 1120 uint8_t hypercall[16]; 1121 1122 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1123 /* indicate KVM hypercall interface */ 1124 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1125 if (kvmppc_has_cap_fixup_hcalls()) { 1126 /* 1127 * Older KVM versions with older guest kernels were broken 1128 * with the magic page, don't allow the guest to map it. 1129 */ 1130 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1131 sizeof(hypercall))) { 1132 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1133 hypercall, sizeof(hypercall))); 1134 } 1135 } 1136 } 1137 1138 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1139 { 1140 MachineState *machine = MACHINE(spapr); 1141 MachineClass *mc = MACHINE_GET_CLASS(machine); 1142 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1143 int ret; 1144 void *fdt; 1145 SpaprPhbState *phb; 1146 char *buf; 1147 1148 fdt = g_malloc0(space); 1149 _FDT((fdt_create_empty_tree(fdt, space))); 1150 1151 /* Root node */ 1152 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1153 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1154 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1155 1156 /* Guest UUID & Name*/ 1157 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1158 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1159 if (qemu_uuid_set) { 1160 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1161 } 1162 g_free(buf); 1163 1164 if (qemu_get_vm_name()) { 1165 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1166 qemu_get_vm_name())); 1167 } 1168 1169 /* Host Model & Serial Number */ 1170 if (spapr->host_model) { 1171 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1172 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1173 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1174 g_free(buf); 1175 } 1176 1177 if (spapr->host_serial) { 1178 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1179 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1180 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1181 g_free(buf); 1182 } 1183 1184 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1185 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1186 1187 /* /interrupt controller */ 1188 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1189 1190 ret = spapr_dt_memory(spapr, fdt); 1191 if (ret < 0) { 1192 error_report("couldn't setup memory nodes in fdt"); 1193 exit(1); 1194 } 1195 1196 /* /vdevice */ 1197 spapr_dt_vdevice(spapr->vio_bus, fdt); 1198 1199 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1200 ret = spapr_dt_rng(fdt); 1201 if (ret < 0) { 1202 error_report("could not set up rng device in the fdt"); 1203 exit(1); 1204 } 1205 } 1206 1207 QLIST_FOREACH(phb, &spapr->phbs, list) { 1208 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1209 if (ret < 0) { 1210 error_report("couldn't setup PCI devices in fdt"); 1211 exit(1); 1212 } 1213 } 1214 1215 spapr_dt_cpus(fdt, spapr); 1216 1217 if (smc->dr_lmb_enabled) { 1218 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1219 } 1220 1221 if (mc->has_hotpluggable_cpus) { 1222 int offset = fdt_path_offset(fdt, "/cpus"); 1223 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1224 if (ret < 0) { 1225 error_report("Couldn't set up CPU DR device tree properties"); 1226 exit(1); 1227 } 1228 } 1229 1230 /* /event-sources */ 1231 spapr_dt_events(spapr, fdt); 1232 1233 /* /rtas */ 1234 spapr_dt_rtas(spapr, fdt); 1235 1236 /* /chosen */ 1237 spapr_dt_chosen(spapr, fdt, reset); 1238 1239 /* /hypervisor */ 1240 if (kvm_enabled()) { 1241 spapr_dt_hypervisor(spapr, fdt); 1242 } 1243 1244 /* Build memory reserve map */ 1245 if (reset) { 1246 if (spapr->kernel_size) { 1247 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1248 spapr->kernel_size))); 1249 } 1250 if (spapr->initrd_size) { 1251 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1252 spapr->initrd_size))); 1253 } 1254 } 1255 1256 if (smc->dr_phb_enabled) { 1257 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1258 if (ret < 0) { 1259 error_report("Couldn't set up PHB DR device tree properties"); 1260 exit(1); 1261 } 1262 } 1263 1264 /* NVDIMM devices */ 1265 if (mc->nvdimm_supported) { 1266 spapr_dt_persistent_memory(fdt); 1267 } 1268 1269 return fdt; 1270 } 1271 1272 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1273 { 1274 SpaprMachineState *spapr = opaque; 1275 1276 return (addr & 0x0fffffff) + spapr->kernel_addr; 1277 } 1278 1279 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1280 PowerPCCPU *cpu) 1281 { 1282 CPUPPCState *env = &cpu->env; 1283 1284 /* The TCG path should also be holding the BQL at this point */ 1285 g_assert(qemu_mutex_iothread_locked()); 1286 1287 if (msr_pr) { 1288 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1289 env->gpr[3] = H_PRIVILEGE; 1290 } else { 1291 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1292 } 1293 } 1294 1295 struct LPCRSyncState { 1296 target_ulong value; 1297 target_ulong mask; 1298 }; 1299 1300 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1301 { 1302 struct LPCRSyncState *s = arg.host_ptr; 1303 PowerPCCPU *cpu = POWERPC_CPU(cs); 1304 CPUPPCState *env = &cpu->env; 1305 target_ulong lpcr; 1306 1307 cpu_synchronize_state(cs); 1308 lpcr = env->spr[SPR_LPCR]; 1309 lpcr &= ~s->mask; 1310 lpcr |= s->value; 1311 ppc_store_lpcr(cpu, lpcr); 1312 } 1313 1314 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1315 { 1316 CPUState *cs; 1317 struct LPCRSyncState s = { 1318 .value = value, 1319 .mask = mask 1320 }; 1321 CPU_FOREACH(cs) { 1322 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1323 } 1324 } 1325 1326 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1327 { 1328 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1329 1330 /* Copy PATE1:GR into PATE0:HR */ 1331 entry->dw0 = spapr->patb_entry & PATE0_HR; 1332 entry->dw1 = spapr->patb_entry; 1333 } 1334 1335 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1336 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1337 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1338 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1339 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1340 1341 /* 1342 * Get the fd to access the kernel htab, re-opening it if necessary 1343 */ 1344 static int get_htab_fd(SpaprMachineState *spapr) 1345 { 1346 Error *local_err = NULL; 1347 1348 if (spapr->htab_fd >= 0) { 1349 return spapr->htab_fd; 1350 } 1351 1352 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1353 if (spapr->htab_fd < 0) { 1354 error_report_err(local_err); 1355 } 1356 1357 return spapr->htab_fd; 1358 } 1359 1360 void close_htab_fd(SpaprMachineState *spapr) 1361 { 1362 if (spapr->htab_fd >= 0) { 1363 close(spapr->htab_fd); 1364 } 1365 spapr->htab_fd = -1; 1366 } 1367 1368 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1369 { 1370 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1371 1372 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1373 } 1374 1375 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1376 { 1377 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1378 1379 assert(kvm_enabled()); 1380 1381 if (!spapr->htab) { 1382 return 0; 1383 } 1384 1385 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1386 } 1387 1388 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1389 hwaddr ptex, int n) 1390 { 1391 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1392 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1393 1394 if (!spapr->htab) { 1395 /* 1396 * HTAB is controlled by KVM. Fetch into temporary buffer 1397 */ 1398 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1399 kvmppc_read_hptes(hptes, ptex, n); 1400 return hptes; 1401 } 1402 1403 /* 1404 * HTAB is controlled by QEMU. Just point to the internally 1405 * accessible PTEG. 1406 */ 1407 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1408 } 1409 1410 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1411 const ppc_hash_pte64_t *hptes, 1412 hwaddr ptex, int n) 1413 { 1414 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1415 1416 if (!spapr->htab) { 1417 g_free((void *)hptes); 1418 } 1419 1420 /* Nothing to do for qemu managed HPT */ 1421 } 1422 1423 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1424 uint64_t pte0, uint64_t pte1) 1425 { 1426 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1427 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1428 1429 if (!spapr->htab) { 1430 kvmppc_write_hpte(ptex, pte0, pte1); 1431 } else { 1432 if (pte0 & HPTE64_V_VALID) { 1433 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1434 /* 1435 * When setting valid, we write PTE1 first. This ensures 1436 * proper synchronization with the reading code in 1437 * ppc_hash64_pteg_search() 1438 */ 1439 smp_wmb(); 1440 stq_p(spapr->htab + offset, pte0); 1441 } else { 1442 stq_p(spapr->htab + offset, pte0); 1443 /* 1444 * When clearing it we set PTE0 first. This ensures proper 1445 * synchronization with the reading code in 1446 * ppc_hash64_pteg_search() 1447 */ 1448 smp_wmb(); 1449 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1450 } 1451 } 1452 } 1453 1454 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1455 uint64_t pte1) 1456 { 1457 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1458 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1459 1460 if (!spapr->htab) { 1461 /* There should always be a hash table when this is called */ 1462 error_report("spapr_hpte_set_c called with no hash table !"); 1463 return; 1464 } 1465 1466 /* The HW performs a non-atomic byte update */ 1467 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1468 } 1469 1470 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1471 uint64_t pte1) 1472 { 1473 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1474 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1475 1476 if (!spapr->htab) { 1477 /* There should always be a hash table when this is called */ 1478 error_report("spapr_hpte_set_r called with no hash table !"); 1479 return; 1480 } 1481 1482 /* The HW performs a non-atomic byte update */ 1483 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1484 } 1485 1486 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1487 { 1488 int shift; 1489 1490 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1491 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1492 * that's much more than is needed for Linux guests */ 1493 shift = ctz64(pow2ceil(ramsize)) - 7; 1494 shift = MAX(shift, 18); /* Minimum architected size */ 1495 shift = MIN(shift, 46); /* Maximum architected size */ 1496 return shift; 1497 } 1498 1499 void spapr_free_hpt(SpaprMachineState *spapr) 1500 { 1501 g_free(spapr->htab); 1502 spapr->htab = NULL; 1503 spapr->htab_shift = 0; 1504 close_htab_fd(spapr); 1505 } 1506 1507 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1508 Error **errp) 1509 { 1510 long rc; 1511 1512 /* Clean up any HPT info from a previous boot */ 1513 spapr_free_hpt(spapr); 1514 1515 rc = kvmppc_reset_htab(shift); 1516 if (rc < 0) { 1517 /* kernel-side HPT needed, but couldn't allocate one */ 1518 error_setg_errno(errp, errno, 1519 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1520 shift); 1521 /* This is almost certainly fatal, but if the caller really 1522 * wants to carry on with shift == 0, it's welcome to try */ 1523 } else if (rc > 0) { 1524 /* kernel-side HPT allocated */ 1525 if (rc != shift) { 1526 error_setg(errp, 1527 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1528 shift, rc); 1529 } 1530 1531 spapr->htab_shift = shift; 1532 spapr->htab = NULL; 1533 } else { 1534 /* kernel-side HPT not needed, allocate in userspace instead */ 1535 size_t size = 1ULL << shift; 1536 int i; 1537 1538 spapr->htab = qemu_memalign(size, size); 1539 if (!spapr->htab) { 1540 error_setg_errno(errp, errno, 1541 "Could not allocate HPT of order %d", shift); 1542 return; 1543 } 1544 1545 memset(spapr->htab, 0, size); 1546 spapr->htab_shift = shift; 1547 1548 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1549 DIRTY_HPTE(HPTE(spapr->htab, i)); 1550 } 1551 } 1552 /* We're setting up a hash table, so that means we're not radix */ 1553 spapr->patb_entry = 0; 1554 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1555 } 1556 1557 void spapr_setup_hpt(SpaprMachineState *spapr) 1558 { 1559 int hpt_shift; 1560 1561 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1562 || (spapr->cas_reboot 1563 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1564 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1565 } else { 1566 uint64_t current_ram_size; 1567 1568 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1569 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1570 } 1571 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1572 1573 if (kvm_enabled()) { 1574 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1575 1576 /* Check our RMA fits in the possible VRMA */ 1577 if (vrma_limit < spapr->rma_size) { 1578 error_report("Unable to create %" HWADDR_PRIu 1579 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1580 spapr->rma_size / MiB, vrma_limit / MiB); 1581 exit(EXIT_FAILURE); 1582 } 1583 } 1584 } 1585 1586 static int spapr_reset_drcs(Object *child, void *opaque) 1587 { 1588 SpaprDrc *drc = 1589 (SpaprDrc *) object_dynamic_cast(child, 1590 TYPE_SPAPR_DR_CONNECTOR); 1591 1592 if (drc) { 1593 spapr_drc_reset(drc); 1594 } 1595 1596 return 0; 1597 } 1598 1599 static void spapr_machine_reset(MachineState *machine) 1600 { 1601 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1602 PowerPCCPU *first_ppc_cpu; 1603 hwaddr fdt_addr; 1604 void *fdt; 1605 int rc; 1606 1607 kvmppc_svm_off(&error_fatal); 1608 spapr_caps_apply(spapr); 1609 1610 first_ppc_cpu = POWERPC_CPU(first_cpu); 1611 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1612 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1613 spapr->max_compat_pvr)) { 1614 /* 1615 * If using KVM with radix mode available, VCPUs can be started 1616 * without a HPT because KVM will start them in radix mode. 1617 * Set the GR bit in PATE so that we know there is no HPT. 1618 */ 1619 spapr->patb_entry = PATE1_GR; 1620 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1621 } else { 1622 spapr_setup_hpt(spapr); 1623 } 1624 1625 qemu_devices_reset(); 1626 1627 /* 1628 * If this reset wasn't generated by CAS, we should reset our 1629 * negotiated options and start from scratch 1630 */ 1631 if (!spapr->cas_reboot) { 1632 spapr_ovec_cleanup(spapr->ov5_cas); 1633 spapr->ov5_cas = spapr_ovec_new(); 1634 1635 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1636 } 1637 1638 /* 1639 * This is fixing some of the default configuration of the XIVE 1640 * devices. To be called after the reset of the machine devices. 1641 */ 1642 spapr_irq_reset(spapr, &error_fatal); 1643 1644 /* 1645 * There is no CAS under qtest. Simulate one to please the code that 1646 * depends on spapr->ov5_cas. This is especially needed to test device 1647 * unplug, so we do that before resetting the DRCs. 1648 */ 1649 if (qtest_enabled()) { 1650 spapr_ovec_cleanup(spapr->ov5_cas); 1651 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1652 } 1653 1654 /* DRC reset may cause a device to be unplugged. This will cause troubles 1655 * if this device is used by another device (eg, a running vhost backend 1656 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1657 * situations, we reset DRCs after all devices have been reset. 1658 */ 1659 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1660 1661 spapr_clear_pending_events(spapr); 1662 1663 /* 1664 * We place the device tree and RTAS just below either the top of the RMA, 1665 * or just below 2GB, whichever is lower, so that it can be 1666 * processed with 32-bit real mode code if necessary 1667 */ 1668 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1669 1670 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1671 1672 rc = fdt_pack(fdt); 1673 1674 /* Should only fail if we've built a corrupted tree */ 1675 assert(rc == 0); 1676 1677 /* Load the fdt */ 1678 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1679 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1680 g_free(spapr->fdt_blob); 1681 spapr->fdt_size = fdt_totalsize(fdt); 1682 spapr->fdt_initial_size = spapr->fdt_size; 1683 spapr->fdt_blob = fdt; 1684 1685 /* Set up the entry state */ 1686 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1687 first_ppc_cpu->env.gpr[5] = 0; 1688 1689 spapr->cas_reboot = false; 1690 1691 spapr->fwnmi_system_reset_addr = -1; 1692 spapr->fwnmi_machine_check_addr = -1; 1693 spapr->fwnmi_machine_check_interlock = -1; 1694 1695 /* Signal all vCPUs waiting on this condition */ 1696 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1697 1698 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1699 } 1700 1701 static void spapr_create_nvram(SpaprMachineState *spapr) 1702 { 1703 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1704 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1705 1706 if (dinfo) { 1707 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1708 &error_fatal); 1709 } 1710 1711 qdev_init_nofail(dev); 1712 1713 spapr->nvram = (struct SpaprNvram *)dev; 1714 } 1715 1716 static void spapr_rtc_create(SpaprMachineState *spapr) 1717 { 1718 object_initialize_child(OBJECT(spapr), "rtc", 1719 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1720 &error_fatal, NULL); 1721 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1722 &error_fatal); 1723 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1724 "date", &error_fatal); 1725 } 1726 1727 /* Returns whether we want to use VGA or not */ 1728 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1729 { 1730 switch (vga_interface_type) { 1731 case VGA_NONE: 1732 return false; 1733 case VGA_DEVICE: 1734 return true; 1735 case VGA_STD: 1736 case VGA_VIRTIO: 1737 case VGA_CIRRUS: 1738 return pci_vga_init(pci_bus) != NULL; 1739 default: 1740 error_setg(errp, 1741 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1742 return false; 1743 } 1744 } 1745 1746 static int spapr_pre_load(void *opaque) 1747 { 1748 int rc; 1749 1750 rc = spapr_caps_pre_load(opaque); 1751 if (rc) { 1752 return rc; 1753 } 1754 1755 return 0; 1756 } 1757 1758 static int spapr_post_load(void *opaque, int version_id) 1759 { 1760 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1761 int err = 0; 1762 1763 err = spapr_caps_post_migration(spapr); 1764 if (err) { 1765 return err; 1766 } 1767 1768 /* 1769 * In earlier versions, there was no separate qdev for the PAPR 1770 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1771 * So when migrating from those versions, poke the incoming offset 1772 * value into the RTC device 1773 */ 1774 if (version_id < 3) { 1775 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1776 if (err) { 1777 return err; 1778 } 1779 } 1780 1781 if (kvm_enabled() && spapr->patb_entry) { 1782 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1783 bool radix = !!(spapr->patb_entry & PATE1_GR); 1784 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1785 1786 /* 1787 * Update LPCR:HR and UPRT as they may not be set properly in 1788 * the stream 1789 */ 1790 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1791 LPCR_HR | LPCR_UPRT); 1792 1793 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1794 if (err) { 1795 error_report("Process table config unsupported by the host"); 1796 return -EINVAL; 1797 } 1798 } 1799 1800 err = spapr_irq_post_load(spapr, version_id); 1801 if (err) { 1802 return err; 1803 } 1804 1805 return err; 1806 } 1807 1808 static int spapr_pre_save(void *opaque) 1809 { 1810 int rc; 1811 1812 rc = spapr_caps_pre_save(opaque); 1813 if (rc) { 1814 return rc; 1815 } 1816 1817 return 0; 1818 } 1819 1820 static bool version_before_3(void *opaque, int version_id) 1821 { 1822 return version_id < 3; 1823 } 1824 1825 static bool spapr_pending_events_needed(void *opaque) 1826 { 1827 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1828 return !QTAILQ_EMPTY(&spapr->pending_events); 1829 } 1830 1831 static const VMStateDescription vmstate_spapr_event_entry = { 1832 .name = "spapr_event_log_entry", 1833 .version_id = 1, 1834 .minimum_version_id = 1, 1835 .fields = (VMStateField[]) { 1836 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1837 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1838 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1839 NULL, extended_length), 1840 VMSTATE_END_OF_LIST() 1841 }, 1842 }; 1843 1844 static const VMStateDescription vmstate_spapr_pending_events = { 1845 .name = "spapr_pending_events", 1846 .version_id = 1, 1847 .minimum_version_id = 1, 1848 .needed = spapr_pending_events_needed, 1849 .fields = (VMStateField[]) { 1850 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1851 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1852 VMSTATE_END_OF_LIST() 1853 }, 1854 }; 1855 1856 static bool spapr_ov5_cas_needed(void *opaque) 1857 { 1858 SpaprMachineState *spapr = opaque; 1859 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1860 bool cas_needed; 1861 1862 /* Prior to the introduction of SpaprOptionVector, we had two option 1863 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1864 * Both of these options encode machine topology into the device-tree 1865 * in such a way that the now-booted OS should still be able to interact 1866 * appropriately with QEMU regardless of what options were actually 1867 * negotiatied on the source side. 1868 * 1869 * As such, we can avoid migrating the CAS-negotiated options if these 1870 * are the only options available on the current machine/platform. 1871 * Since these are the only options available for pseries-2.7 and 1872 * earlier, this allows us to maintain old->new/new->old migration 1873 * compatibility. 1874 * 1875 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1876 * via default pseries-2.8 machines and explicit command-line parameters. 1877 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1878 * of the actual CAS-negotiated values to continue working properly. For 1879 * example, availability of memory unplug depends on knowing whether 1880 * OV5_HP_EVT was negotiated via CAS. 1881 * 1882 * Thus, for any cases where the set of available CAS-negotiatable 1883 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1884 * include the CAS-negotiated options in the migration stream, unless 1885 * if they affect boot time behaviour only. 1886 */ 1887 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1888 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1889 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1890 1891 /* We need extra information if we have any bits outside the mask 1892 * defined above */ 1893 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1894 1895 spapr_ovec_cleanup(ov5_mask); 1896 1897 return cas_needed; 1898 } 1899 1900 static const VMStateDescription vmstate_spapr_ov5_cas = { 1901 .name = "spapr_option_vector_ov5_cas", 1902 .version_id = 1, 1903 .minimum_version_id = 1, 1904 .needed = spapr_ov5_cas_needed, 1905 .fields = (VMStateField[]) { 1906 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1907 vmstate_spapr_ovec, SpaprOptionVector), 1908 VMSTATE_END_OF_LIST() 1909 }, 1910 }; 1911 1912 static bool spapr_patb_entry_needed(void *opaque) 1913 { 1914 SpaprMachineState *spapr = opaque; 1915 1916 return !!spapr->patb_entry; 1917 } 1918 1919 static const VMStateDescription vmstate_spapr_patb_entry = { 1920 .name = "spapr_patb_entry", 1921 .version_id = 1, 1922 .minimum_version_id = 1, 1923 .needed = spapr_patb_entry_needed, 1924 .fields = (VMStateField[]) { 1925 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1926 VMSTATE_END_OF_LIST() 1927 }, 1928 }; 1929 1930 static bool spapr_irq_map_needed(void *opaque) 1931 { 1932 SpaprMachineState *spapr = opaque; 1933 1934 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1935 } 1936 1937 static const VMStateDescription vmstate_spapr_irq_map = { 1938 .name = "spapr_irq_map", 1939 .version_id = 1, 1940 .minimum_version_id = 1, 1941 .needed = spapr_irq_map_needed, 1942 .fields = (VMStateField[]) { 1943 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1944 VMSTATE_END_OF_LIST() 1945 }, 1946 }; 1947 1948 static bool spapr_dtb_needed(void *opaque) 1949 { 1950 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1951 1952 return smc->update_dt_enabled; 1953 } 1954 1955 static int spapr_dtb_pre_load(void *opaque) 1956 { 1957 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1958 1959 g_free(spapr->fdt_blob); 1960 spapr->fdt_blob = NULL; 1961 spapr->fdt_size = 0; 1962 1963 return 0; 1964 } 1965 1966 static const VMStateDescription vmstate_spapr_dtb = { 1967 .name = "spapr_dtb", 1968 .version_id = 1, 1969 .minimum_version_id = 1, 1970 .needed = spapr_dtb_needed, 1971 .pre_load = spapr_dtb_pre_load, 1972 .fields = (VMStateField[]) { 1973 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1974 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1975 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1976 fdt_size), 1977 VMSTATE_END_OF_LIST() 1978 }, 1979 }; 1980 1981 static bool spapr_fwnmi_needed(void *opaque) 1982 { 1983 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1984 1985 return spapr->fwnmi_machine_check_addr != -1; 1986 } 1987 1988 static int spapr_fwnmi_pre_save(void *opaque) 1989 { 1990 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1991 1992 /* 1993 * Check if machine check handling is in progress and print a 1994 * warning message. 1995 */ 1996 if (spapr->fwnmi_machine_check_interlock != -1) { 1997 warn_report("A machine check is being handled during migration. The" 1998 "handler may run and log hardware error on the destination"); 1999 } 2000 2001 return 0; 2002 } 2003 2004 static const VMStateDescription vmstate_spapr_fwnmi = { 2005 .name = "spapr_fwnmi", 2006 .version_id = 1, 2007 .minimum_version_id = 1, 2008 .needed = spapr_fwnmi_needed, 2009 .pre_save = spapr_fwnmi_pre_save, 2010 .fields = (VMStateField[]) { 2011 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2012 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2013 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2014 VMSTATE_END_OF_LIST() 2015 }, 2016 }; 2017 2018 static const VMStateDescription vmstate_spapr = { 2019 .name = "spapr", 2020 .version_id = 3, 2021 .minimum_version_id = 1, 2022 .pre_load = spapr_pre_load, 2023 .post_load = spapr_post_load, 2024 .pre_save = spapr_pre_save, 2025 .fields = (VMStateField[]) { 2026 /* used to be @next_irq */ 2027 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2028 2029 /* RTC offset */ 2030 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2031 2032 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2033 VMSTATE_END_OF_LIST() 2034 }, 2035 .subsections = (const VMStateDescription*[]) { 2036 &vmstate_spapr_ov5_cas, 2037 &vmstate_spapr_patb_entry, 2038 &vmstate_spapr_pending_events, 2039 &vmstate_spapr_cap_htm, 2040 &vmstate_spapr_cap_vsx, 2041 &vmstate_spapr_cap_dfp, 2042 &vmstate_spapr_cap_cfpc, 2043 &vmstate_spapr_cap_sbbc, 2044 &vmstate_spapr_cap_ibs, 2045 &vmstate_spapr_cap_hpt_maxpagesize, 2046 &vmstate_spapr_irq_map, 2047 &vmstate_spapr_cap_nested_kvm_hv, 2048 &vmstate_spapr_dtb, 2049 &vmstate_spapr_cap_large_decr, 2050 &vmstate_spapr_cap_ccf_assist, 2051 &vmstate_spapr_cap_fwnmi, 2052 &vmstate_spapr_fwnmi, 2053 NULL 2054 } 2055 }; 2056 2057 static int htab_save_setup(QEMUFile *f, void *opaque) 2058 { 2059 SpaprMachineState *spapr = opaque; 2060 2061 /* "Iteration" header */ 2062 if (!spapr->htab_shift) { 2063 qemu_put_be32(f, -1); 2064 } else { 2065 qemu_put_be32(f, spapr->htab_shift); 2066 } 2067 2068 if (spapr->htab) { 2069 spapr->htab_save_index = 0; 2070 spapr->htab_first_pass = true; 2071 } else { 2072 if (spapr->htab_shift) { 2073 assert(kvm_enabled()); 2074 } 2075 } 2076 2077 2078 return 0; 2079 } 2080 2081 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2082 int chunkstart, int n_valid, int n_invalid) 2083 { 2084 qemu_put_be32(f, chunkstart); 2085 qemu_put_be16(f, n_valid); 2086 qemu_put_be16(f, n_invalid); 2087 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2088 HASH_PTE_SIZE_64 * n_valid); 2089 } 2090 2091 static void htab_save_end_marker(QEMUFile *f) 2092 { 2093 qemu_put_be32(f, 0); 2094 qemu_put_be16(f, 0); 2095 qemu_put_be16(f, 0); 2096 } 2097 2098 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2099 int64_t max_ns) 2100 { 2101 bool has_timeout = max_ns != -1; 2102 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2103 int index = spapr->htab_save_index; 2104 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2105 2106 assert(spapr->htab_first_pass); 2107 2108 do { 2109 int chunkstart; 2110 2111 /* Consume invalid HPTEs */ 2112 while ((index < htabslots) 2113 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2114 CLEAN_HPTE(HPTE(spapr->htab, index)); 2115 index++; 2116 } 2117 2118 /* Consume valid HPTEs */ 2119 chunkstart = index; 2120 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2121 && HPTE_VALID(HPTE(spapr->htab, index))) { 2122 CLEAN_HPTE(HPTE(spapr->htab, index)); 2123 index++; 2124 } 2125 2126 if (index > chunkstart) { 2127 int n_valid = index - chunkstart; 2128 2129 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2130 2131 if (has_timeout && 2132 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2133 break; 2134 } 2135 } 2136 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2137 2138 if (index >= htabslots) { 2139 assert(index == htabslots); 2140 index = 0; 2141 spapr->htab_first_pass = false; 2142 } 2143 spapr->htab_save_index = index; 2144 } 2145 2146 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2147 int64_t max_ns) 2148 { 2149 bool final = max_ns < 0; 2150 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2151 int examined = 0, sent = 0; 2152 int index = spapr->htab_save_index; 2153 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2154 2155 assert(!spapr->htab_first_pass); 2156 2157 do { 2158 int chunkstart, invalidstart; 2159 2160 /* Consume non-dirty HPTEs */ 2161 while ((index < htabslots) 2162 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2163 index++; 2164 examined++; 2165 } 2166 2167 chunkstart = index; 2168 /* Consume valid dirty HPTEs */ 2169 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2170 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2171 && HPTE_VALID(HPTE(spapr->htab, index))) { 2172 CLEAN_HPTE(HPTE(spapr->htab, index)); 2173 index++; 2174 examined++; 2175 } 2176 2177 invalidstart = index; 2178 /* Consume invalid dirty HPTEs */ 2179 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2180 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2181 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2182 CLEAN_HPTE(HPTE(spapr->htab, index)); 2183 index++; 2184 examined++; 2185 } 2186 2187 if (index > chunkstart) { 2188 int n_valid = invalidstart - chunkstart; 2189 int n_invalid = index - invalidstart; 2190 2191 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2192 sent += index - chunkstart; 2193 2194 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2195 break; 2196 } 2197 } 2198 2199 if (examined >= htabslots) { 2200 break; 2201 } 2202 2203 if (index >= htabslots) { 2204 assert(index == htabslots); 2205 index = 0; 2206 } 2207 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2208 2209 if (index >= htabslots) { 2210 assert(index == htabslots); 2211 index = 0; 2212 } 2213 2214 spapr->htab_save_index = index; 2215 2216 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2217 } 2218 2219 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2220 #define MAX_KVM_BUF_SIZE 2048 2221 2222 static int htab_save_iterate(QEMUFile *f, void *opaque) 2223 { 2224 SpaprMachineState *spapr = opaque; 2225 int fd; 2226 int rc = 0; 2227 2228 /* Iteration header */ 2229 if (!spapr->htab_shift) { 2230 qemu_put_be32(f, -1); 2231 return 1; 2232 } else { 2233 qemu_put_be32(f, 0); 2234 } 2235 2236 if (!spapr->htab) { 2237 assert(kvm_enabled()); 2238 2239 fd = get_htab_fd(spapr); 2240 if (fd < 0) { 2241 return fd; 2242 } 2243 2244 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2245 if (rc < 0) { 2246 return rc; 2247 } 2248 } else if (spapr->htab_first_pass) { 2249 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2250 } else { 2251 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2252 } 2253 2254 htab_save_end_marker(f); 2255 2256 return rc; 2257 } 2258 2259 static int htab_save_complete(QEMUFile *f, void *opaque) 2260 { 2261 SpaprMachineState *spapr = opaque; 2262 int fd; 2263 2264 /* Iteration header */ 2265 if (!spapr->htab_shift) { 2266 qemu_put_be32(f, -1); 2267 return 0; 2268 } else { 2269 qemu_put_be32(f, 0); 2270 } 2271 2272 if (!spapr->htab) { 2273 int rc; 2274 2275 assert(kvm_enabled()); 2276 2277 fd = get_htab_fd(spapr); 2278 if (fd < 0) { 2279 return fd; 2280 } 2281 2282 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2283 if (rc < 0) { 2284 return rc; 2285 } 2286 } else { 2287 if (spapr->htab_first_pass) { 2288 htab_save_first_pass(f, spapr, -1); 2289 } 2290 htab_save_later_pass(f, spapr, -1); 2291 } 2292 2293 /* End marker */ 2294 htab_save_end_marker(f); 2295 2296 return 0; 2297 } 2298 2299 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2300 { 2301 SpaprMachineState *spapr = opaque; 2302 uint32_t section_hdr; 2303 int fd = -1; 2304 Error *local_err = NULL; 2305 2306 if (version_id < 1 || version_id > 1) { 2307 error_report("htab_load() bad version"); 2308 return -EINVAL; 2309 } 2310 2311 section_hdr = qemu_get_be32(f); 2312 2313 if (section_hdr == -1) { 2314 spapr_free_hpt(spapr); 2315 return 0; 2316 } 2317 2318 if (section_hdr) { 2319 /* First section gives the htab size */ 2320 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2321 if (local_err) { 2322 error_report_err(local_err); 2323 return -EINVAL; 2324 } 2325 return 0; 2326 } 2327 2328 if (!spapr->htab) { 2329 assert(kvm_enabled()); 2330 2331 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2332 if (fd < 0) { 2333 error_report_err(local_err); 2334 return fd; 2335 } 2336 } 2337 2338 while (true) { 2339 uint32_t index; 2340 uint16_t n_valid, n_invalid; 2341 2342 index = qemu_get_be32(f); 2343 n_valid = qemu_get_be16(f); 2344 n_invalid = qemu_get_be16(f); 2345 2346 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2347 /* End of Stream */ 2348 break; 2349 } 2350 2351 if ((index + n_valid + n_invalid) > 2352 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2353 /* Bad index in stream */ 2354 error_report( 2355 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2356 index, n_valid, n_invalid, spapr->htab_shift); 2357 return -EINVAL; 2358 } 2359 2360 if (spapr->htab) { 2361 if (n_valid) { 2362 qemu_get_buffer(f, HPTE(spapr->htab, index), 2363 HASH_PTE_SIZE_64 * n_valid); 2364 } 2365 if (n_invalid) { 2366 memset(HPTE(spapr->htab, index + n_valid), 0, 2367 HASH_PTE_SIZE_64 * n_invalid); 2368 } 2369 } else { 2370 int rc; 2371 2372 assert(fd >= 0); 2373 2374 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2375 if (rc < 0) { 2376 return rc; 2377 } 2378 } 2379 } 2380 2381 if (!spapr->htab) { 2382 assert(fd >= 0); 2383 close(fd); 2384 } 2385 2386 return 0; 2387 } 2388 2389 static void htab_save_cleanup(void *opaque) 2390 { 2391 SpaprMachineState *spapr = opaque; 2392 2393 close_htab_fd(spapr); 2394 } 2395 2396 static SaveVMHandlers savevm_htab_handlers = { 2397 .save_setup = htab_save_setup, 2398 .save_live_iterate = htab_save_iterate, 2399 .save_live_complete_precopy = htab_save_complete, 2400 .save_cleanup = htab_save_cleanup, 2401 .load_state = htab_load, 2402 }; 2403 2404 static void spapr_boot_set(void *opaque, const char *boot_device, 2405 Error **errp) 2406 { 2407 MachineState *machine = MACHINE(opaque); 2408 machine->boot_order = g_strdup(boot_device); 2409 } 2410 2411 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2412 { 2413 MachineState *machine = MACHINE(spapr); 2414 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2415 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2416 int i; 2417 2418 for (i = 0; i < nr_lmbs; i++) { 2419 uint64_t addr; 2420 2421 addr = i * lmb_size + machine->device_memory->base; 2422 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2423 addr / lmb_size); 2424 } 2425 } 2426 2427 /* 2428 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2429 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2430 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2431 */ 2432 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2433 { 2434 int i; 2435 2436 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2437 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2438 " is not aligned to %" PRIu64 " MiB", 2439 machine->ram_size, 2440 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2441 return; 2442 } 2443 2444 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2445 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2446 " is not aligned to %" PRIu64 " MiB", 2447 machine->ram_size, 2448 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2449 return; 2450 } 2451 2452 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2453 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2454 error_setg(errp, 2455 "Node %d memory size 0x%" PRIx64 2456 " is not aligned to %" PRIu64 " MiB", 2457 i, machine->numa_state->nodes[i].node_mem, 2458 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2459 return; 2460 } 2461 } 2462 } 2463 2464 /* find cpu slot in machine->possible_cpus by core_id */ 2465 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2466 { 2467 int index = id / ms->smp.threads; 2468 2469 if (index >= ms->possible_cpus->len) { 2470 return NULL; 2471 } 2472 if (idx) { 2473 *idx = index; 2474 } 2475 return &ms->possible_cpus->cpus[index]; 2476 } 2477 2478 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2479 { 2480 MachineState *ms = MACHINE(spapr); 2481 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2482 Error *local_err = NULL; 2483 bool vsmt_user = !!spapr->vsmt; 2484 int kvm_smt = kvmppc_smt_threads(); 2485 int ret; 2486 unsigned int smp_threads = ms->smp.threads; 2487 2488 if (!kvm_enabled() && (smp_threads > 1)) { 2489 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2490 "on a pseries machine"); 2491 goto out; 2492 } 2493 if (!is_power_of_2(smp_threads)) { 2494 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2495 "machine because it must be a power of 2", smp_threads); 2496 goto out; 2497 } 2498 2499 /* Detemine the VSMT mode to use: */ 2500 if (vsmt_user) { 2501 if (spapr->vsmt < smp_threads) { 2502 error_setg(&local_err, "Cannot support VSMT mode %d" 2503 " because it must be >= threads/core (%d)", 2504 spapr->vsmt, smp_threads); 2505 goto out; 2506 } 2507 /* In this case, spapr->vsmt has been set by the command line */ 2508 } else if (!smc->smp_threads_vsmt) { 2509 /* 2510 * Default VSMT value is tricky, because we need it to be as 2511 * consistent as possible (for migration), but this requires 2512 * changing it for at least some existing cases. We pick 8 as 2513 * the value that we'd get with KVM on POWER8, the 2514 * overwhelmingly common case in production systems. 2515 */ 2516 spapr->vsmt = MAX(8, smp_threads); 2517 } else { 2518 spapr->vsmt = smp_threads; 2519 } 2520 2521 /* KVM: If necessary, set the SMT mode: */ 2522 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2523 ret = kvmppc_set_smt_threads(spapr->vsmt); 2524 if (ret) { 2525 /* Looks like KVM isn't able to change VSMT mode */ 2526 error_setg(&local_err, 2527 "Failed to set KVM's VSMT mode to %d (errno %d)", 2528 spapr->vsmt, ret); 2529 /* We can live with that if the default one is big enough 2530 * for the number of threads, and a submultiple of the one 2531 * we want. In this case we'll waste some vcpu ids, but 2532 * behaviour will be correct */ 2533 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2534 warn_report_err(local_err); 2535 local_err = NULL; 2536 goto out; 2537 } else { 2538 if (!vsmt_user) { 2539 error_append_hint(&local_err, 2540 "On PPC, a VM with %d threads/core" 2541 " on a host with %d threads/core" 2542 " requires the use of VSMT mode %d.\n", 2543 smp_threads, kvm_smt, spapr->vsmt); 2544 } 2545 kvmppc_error_append_smt_possible_hint(&local_err); 2546 goto out; 2547 } 2548 } 2549 } 2550 /* else TCG: nothing to do currently */ 2551 out: 2552 error_propagate(errp, local_err); 2553 } 2554 2555 static void spapr_init_cpus(SpaprMachineState *spapr) 2556 { 2557 MachineState *machine = MACHINE(spapr); 2558 MachineClass *mc = MACHINE_GET_CLASS(machine); 2559 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2560 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2561 const CPUArchIdList *possible_cpus; 2562 unsigned int smp_cpus = machine->smp.cpus; 2563 unsigned int smp_threads = machine->smp.threads; 2564 unsigned int max_cpus = machine->smp.max_cpus; 2565 int boot_cores_nr = smp_cpus / smp_threads; 2566 int i; 2567 2568 possible_cpus = mc->possible_cpu_arch_ids(machine); 2569 if (mc->has_hotpluggable_cpus) { 2570 if (smp_cpus % smp_threads) { 2571 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2572 smp_cpus, smp_threads); 2573 exit(1); 2574 } 2575 if (max_cpus % smp_threads) { 2576 error_report("max_cpus (%u) must be multiple of threads (%u)", 2577 max_cpus, smp_threads); 2578 exit(1); 2579 } 2580 } else { 2581 if (max_cpus != smp_cpus) { 2582 error_report("This machine version does not support CPU hotplug"); 2583 exit(1); 2584 } 2585 boot_cores_nr = possible_cpus->len; 2586 } 2587 2588 if (smc->pre_2_10_has_unused_icps) { 2589 int i; 2590 2591 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2592 /* Dummy entries get deregistered when real ICPState objects 2593 * are registered during CPU core hotplug. 2594 */ 2595 pre_2_10_vmstate_register_dummy_icp(i); 2596 } 2597 } 2598 2599 for (i = 0; i < possible_cpus->len; i++) { 2600 int core_id = i * smp_threads; 2601 2602 if (mc->has_hotpluggable_cpus) { 2603 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2604 spapr_vcpu_id(spapr, core_id)); 2605 } 2606 2607 if (i < boot_cores_nr) { 2608 Object *core = object_new(type); 2609 int nr_threads = smp_threads; 2610 2611 /* Handle the partially filled core for older machine types */ 2612 if ((i + 1) * smp_threads >= smp_cpus) { 2613 nr_threads = smp_cpus - i * smp_threads; 2614 } 2615 2616 object_property_set_int(core, nr_threads, "nr-threads", 2617 &error_fatal); 2618 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2619 &error_fatal); 2620 object_property_set_bool(core, true, "realized", &error_fatal); 2621 2622 object_unref(core); 2623 } 2624 } 2625 } 2626 2627 static PCIHostState *spapr_create_default_phb(void) 2628 { 2629 DeviceState *dev; 2630 2631 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2632 qdev_prop_set_uint32(dev, "index", 0); 2633 qdev_init_nofail(dev); 2634 2635 return PCI_HOST_BRIDGE(dev); 2636 } 2637 2638 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2639 { 2640 MachineState *machine = MACHINE(spapr); 2641 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2642 hwaddr rma_size = machine->ram_size; 2643 hwaddr node0_size = spapr_node0_size(machine); 2644 2645 /* RMA has to fit in the first NUMA node */ 2646 rma_size = MIN(rma_size, node0_size); 2647 2648 /* 2649 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2650 * never exceed that 2651 */ 2652 rma_size = MIN(rma_size, 1 * TiB); 2653 2654 /* 2655 * Clamp the RMA size based on machine type. This is for 2656 * migration compatibility with older qemu versions, which limited 2657 * the RMA size for complicated and mostly bad reasons. 2658 */ 2659 if (smc->rma_limit) { 2660 rma_size = MIN(rma_size, smc->rma_limit); 2661 } 2662 2663 if (rma_size < MIN_RMA_SLOF) { 2664 error_setg(errp, 2665 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2666 "ldMiB guest RMA (Real Mode Area memory)", 2667 MIN_RMA_SLOF / MiB); 2668 return 0; 2669 } 2670 2671 return rma_size; 2672 } 2673 2674 /* pSeries LPAR / sPAPR hardware init */ 2675 static void spapr_machine_init(MachineState *machine) 2676 { 2677 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2678 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2679 MachineClass *mc = MACHINE_GET_CLASS(machine); 2680 const char *kernel_filename = machine->kernel_filename; 2681 const char *initrd_filename = machine->initrd_filename; 2682 PCIHostState *phb; 2683 int i; 2684 MemoryRegion *sysmem = get_system_memory(); 2685 long load_limit, fw_size; 2686 char *filename; 2687 Error *resize_hpt_err = NULL; 2688 2689 msi_nonbroken = true; 2690 2691 QLIST_INIT(&spapr->phbs); 2692 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2693 2694 /* Determine capabilities to run with */ 2695 spapr_caps_init(spapr); 2696 2697 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2698 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2699 /* 2700 * If the user explicitly requested a mode we should either 2701 * supply it, or fail completely (which we do below). But if 2702 * it's not set explicitly, we reset our mode to something 2703 * that works 2704 */ 2705 if (resize_hpt_err) { 2706 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2707 error_free(resize_hpt_err); 2708 resize_hpt_err = NULL; 2709 } else { 2710 spapr->resize_hpt = smc->resize_hpt_default; 2711 } 2712 } 2713 2714 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2715 2716 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2717 /* 2718 * User requested HPT resize, but this host can't supply it. Bail out 2719 */ 2720 error_report_err(resize_hpt_err); 2721 exit(1); 2722 } 2723 2724 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2725 2726 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2727 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2728 2729 /* 2730 * VSMT must be set in order to be able to compute VCPU ids, ie to 2731 * call spapr_max_server_number() or spapr_vcpu_id(). 2732 */ 2733 spapr_set_vsmt_mode(spapr, &error_fatal); 2734 2735 /* Set up Interrupt Controller before we create the VCPUs */ 2736 spapr_irq_init(spapr, &error_fatal); 2737 2738 /* Set up containers for ibm,client-architecture-support negotiated options 2739 */ 2740 spapr->ov5 = spapr_ovec_new(); 2741 spapr->ov5_cas = spapr_ovec_new(); 2742 2743 if (smc->dr_lmb_enabled) { 2744 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2745 spapr_validate_node_memory(machine, &error_fatal); 2746 } 2747 2748 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2749 2750 /* advertise support for dedicated HP event source to guests */ 2751 if (spapr->use_hotplug_event_source) { 2752 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2753 } 2754 2755 /* advertise support for HPT resizing */ 2756 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2757 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2758 } 2759 2760 /* advertise support for ibm,dyamic-memory-v2 */ 2761 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2762 2763 /* advertise XIVE on POWER9 machines */ 2764 if (spapr->irq->xive) { 2765 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2766 } 2767 2768 /* init CPUs */ 2769 spapr_init_cpus(spapr); 2770 2771 /* 2772 * check we don't have a memory-less/cpu-less NUMA node 2773 * Firmware relies on the existing memory/cpu topology to provide the 2774 * NUMA topology to the kernel. 2775 * And the linux kernel needs to know the NUMA topology at start 2776 * to be able to hotplug CPUs later. 2777 */ 2778 if (machine->numa_state->num_nodes) { 2779 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2780 /* check for memory-less node */ 2781 if (machine->numa_state->nodes[i].node_mem == 0) { 2782 CPUState *cs; 2783 int found = 0; 2784 /* check for cpu-less node */ 2785 CPU_FOREACH(cs) { 2786 PowerPCCPU *cpu = POWERPC_CPU(cs); 2787 if (cpu->node_id == i) { 2788 found = 1; 2789 break; 2790 } 2791 } 2792 /* memory-less and cpu-less node */ 2793 if (!found) { 2794 error_report( 2795 "Memory-less/cpu-less nodes are not supported (node %d)", 2796 i); 2797 exit(1); 2798 } 2799 } 2800 } 2801 2802 } 2803 2804 /* 2805 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2806 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2807 * called from vPHB reset handler so we initialize the counter here. 2808 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2809 * must be equally distant from any other node. 2810 * The final value of spapr->gpu_numa_id is going to be written to 2811 * max-associativity-domains in spapr_build_fdt(). 2812 */ 2813 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2814 2815 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2816 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2817 spapr->max_compat_pvr)) { 2818 /* KVM and TCG always allow GTSE with radix... */ 2819 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2820 } 2821 /* ... but not with hash (currently). */ 2822 2823 if (kvm_enabled()) { 2824 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2825 kvmppc_enable_logical_ci_hcalls(); 2826 kvmppc_enable_set_mode_hcall(); 2827 2828 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2829 kvmppc_enable_clear_ref_mod_hcalls(); 2830 2831 /* Enable H_PAGE_INIT */ 2832 kvmppc_enable_h_page_init(); 2833 } 2834 2835 /* map RAM */ 2836 memory_region_add_subregion(sysmem, 0, machine->ram); 2837 2838 /* always allocate the device memory information */ 2839 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2840 2841 /* initialize hotplug memory address space */ 2842 if (machine->ram_size < machine->maxram_size) { 2843 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2844 /* 2845 * Limit the number of hotpluggable memory slots to half the number 2846 * slots that KVM supports, leaving the other half for PCI and other 2847 * devices. However ensure that number of slots doesn't drop below 32. 2848 */ 2849 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2850 SPAPR_MAX_RAM_SLOTS; 2851 2852 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2853 max_memslots = SPAPR_MAX_RAM_SLOTS; 2854 } 2855 if (machine->ram_slots > max_memslots) { 2856 error_report("Specified number of memory slots %" 2857 PRIu64" exceeds max supported %d", 2858 machine->ram_slots, max_memslots); 2859 exit(1); 2860 } 2861 2862 machine->device_memory->base = ROUND_UP(machine->ram_size, 2863 SPAPR_DEVICE_MEM_ALIGN); 2864 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2865 "device-memory", device_mem_size); 2866 memory_region_add_subregion(sysmem, machine->device_memory->base, 2867 &machine->device_memory->mr); 2868 } 2869 2870 if (smc->dr_lmb_enabled) { 2871 spapr_create_lmb_dr_connectors(spapr); 2872 } 2873 2874 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2875 /* Create the error string for live migration blocker */ 2876 error_setg(&spapr->fwnmi_migration_blocker, 2877 "A machine check is being handled during migration. The handler" 2878 "may run and log hardware error on the destination"); 2879 } 2880 2881 if (mc->nvdimm_supported) { 2882 spapr_create_nvdimm_dr_connectors(spapr); 2883 } 2884 2885 /* Set up RTAS event infrastructure */ 2886 spapr_events_init(spapr); 2887 2888 /* Set up the RTC RTAS interfaces */ 2889 spapr_rtc_create(spapr); 2890 2891 /* Set up VIO bus */ 2892 spapr->vio_bus = spapr_vio_bus_init(); 2893 2894 for (i = 0; i < serial_max_hds(); i++) { 2895 if (serial_hd(i)) { 2896 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2897 } 2898 } 2899 2900 /* We always have at least the nvram device on VIO */ 2901 spapr_create_nvram(spapr); 2902 2903 /* 2904 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2905 * connectors (described in root DT node's "ibm,drc-types" property) 2906 * are pre-initialized here. additional child connectors (such as 2907 * connectors for a PHBs PCI slots) are added as needed during their 2908 * parent's realization. 2909 */ 2910 if (smc->dr_phb_enabled) { 2911 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2912 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2913 } 2914 } 2915 2916 /* Set up PCI */ 2917 spapr_pci_rtas_init(); 2918 2919 phb = spapr_create_default_phb(); 2920 2921 for (i = 0; i < nb_nics; i++) { 2922 NICInfo *nd = &nd_table[i]; 2923 2924 if (!nd->model) { 2925 nd->model = g_strdup("spapr-vlan"); 2926 } 2927 2928 if (g_str_equal(nd->model, "spapr-vlan") || 2929 g_str_equal(nd->model, "ibmveth")) { 2930 spapr_vlan_create(spapr->vio_bus, nd); 2931 } else { 2932 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2933 } 2934 } 2935 2936 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2937 spapr_vscsi_create(spapr->vio_bus); 2938 } 2939 2940 /* Graphics */ 2941 if (spapr_vga_init(phb->bus, &error_fatal)) { 2942 spapr->has_graphics = true; 2943 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2944 } 2945 2946 if (machine->usb) { 2947 if (smc->use_ohci_by_default) { 2948 pci_create_simple(phb->bus, -1, "pci-ohci"); 2949 } else { 2950 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2951 } 2952 2953 if (spapr->has_graphics) { 2954 USBBus *usb_bus = usb_bus_find(-1); 2955 2956 usb_create_simple(usb_bus, "usb-kbd"); 2957 usb_create_simple(usb_bus, "usb-mouse"); 2958 } 2959 } 2960 2961 if (kernel_filename) { 2962 uint64_t lowaddr = 0; 2963 2964 spapr->kernel_size = load_elf(kernel_filename, NULL, 2965 translate_kernel_address, spapr, 2966 NULL, &lowaddr, NULL, NULL, 1, 2967 PPC_ELF_MACHINE, 0, 0); 2968 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2969 spapr->kernel_size = load_elf(kernel_filename, NULL, 2970 translate_kernel_address, spapr, NULL, 2971 &lowaddr, NULL, NULL, 0, 2972 PPC_ELF_MACHINE, 2973 0, 0); 2974 spapr->kernel_le = spapr->kernel_size > 0; 2975 } 2976 if (spapr->kernel_size < 0) { 2977 error_report("error loading %s: %s", kernel_filename, 2978 load_elf_strerror(spapr->kernel_size)); 2979 exit(1); 2980 } 2981 2982 /* load initrd */ 2983 if (initrd_filename) { 2984 /* Try to locate the initrd in the gap between the kernel 2985 * and the firmware. Add a bit of space just in case 2986 */ 2987 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2988 + 0x1ffff) & ~0xffff; 2989 spapr->initrd_size = load_image_targphys(initrd_filename, 2990 spapr->initrd_base, 2991 load_limit 2992 - spapr->initrd_base); 2993 if (spapr->initrd_size < 0) { 2994 error_report("could not load initial ram disk '%s'", 2995 initrd_filename); 2996 exit(1); 2997 } 2998 } 2999 } 3000 3001 if (bios_name == NULL) { 3002 bios_name = FW_FILE_NAME; 3003 } 3004 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3005 if (!filename) { 3006 error_report("Could not find LPAR firmware '%s'", bios_name); 3007 exit(1); 3008 } 3009 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3010 if (fw_size <= 0) { 3011 error_report("Could not load LPAR firmware '%s'", filename); 3012 exit(1); 3013 } 3014 g_free(filename); 3015 3016 /* FIXME: Should register things through the MachineState's qdev 3017 * interface, this is a legacy from the sPAPREnvironment structure 3018 * which predated MachineState but had a similar function */ 3019 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3020 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3021 &savevm_htab_handlers, spapr); 3022 3023 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3024 &error_fatal); 3025 3026 qemu_register_boot_set(spapr_boot_set, spapr); 3027 3028 /* 3029 * Nothing needs to be done to resume a suspended guest because 3030 * suspending does not change the machine state, so no need for 3031 * a ->wakeup method. 3032 */ 3033 qemu_register_wakeup_support(); 3034 3035 if (kvm_enabled()) { 3036 /* to stop and start vmclock */ 3037 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3038 &spapr->tb); 3039 3040 kvmppc_spapr_enable_inkernel_multitce(); 3041 } 3042 3043 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3044 } 3045 3046 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3047 { 3048 if (!vm_type) { 3049 return 0; 3050 } 3051 3052 if (!strcmp(vm_type, "HV")) { 3053 return 1; 3054 } 3055 3056 if (!strcmp(vm_type, "PR")) { 3057 return 2; 3058 } 3059 3060 error_report("Unknown kvm-type specified '%s'", vm_type); 3061 exit(1); 3062 } 3063 3064 /* 3065 * Implementation of an interface to adjust firmware path 3066 * for the bootindex property handling. 3067 */ 3068 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3069 DeviceState *dev) 3070 { 3071 #define CAST(type, obj, name) \ 3072 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3073 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3074 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3075 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3076 3077 if (d) { 3078 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3079 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3080 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3081 3082 if (spapr) { 3083 /* 3084 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3085 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3086 * 0x8000 | (target << 8) | (bus << 5) | lun 3087 * (see the "Logical unit addressing format" table in SAM5) 3088 */ 3089 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3090 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3091 (uint64_t)id << 48); 3092 } else if (virtio) { 3093 /* 3094 * We use SRP luns of the form 01000000 | (target << 8) | lun 3095 * in the top 32 bits of the 64-bit LUN 3096 * Note: the quote above is from SLOF and it is wrong, 3097 * the actual binding is: 3098 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3099 */ 3100 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3101 if (d->lun >= 256) { 3102 /* Use the LUN "flat space addressing method" */ 3103 id |= 0x4000; 3104 } 3105 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3106 (uint64_t)id << 32); 3107 } else if (usb) { 3108 /* 3109 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3110 * in the top 32 bits of the 64-bit LUN 3111 */ 3112 unsigned usb_port = atoi(usb->port->path); 3113 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3114 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3115 (uint64_t)id << 32); 3116 } 3117 } 3118 3119 /* 3120 * SLOF probes the USB devices, and if it recognizes that the device is a 3121 * storage device, it changes its name to "storage" instead of "usb-host", 3122 * and additionally adds a child node for the SCSI LUN, so the correct 3123 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3124 */ 3125 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3126 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3127 if (usb_host_dev_is_scsi_storage(usbdev)) { 3128 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3129 } 3130 } 3131 3132 if (phb) { 3133 /* Replace "pci" with "pci@800000020000000" */ 3134 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3135 } 3136 3137 if (vsc) { 3138 /* Same logic as virtio above */ 3139 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3140 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3141 } 3142 3143 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3144 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3145 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3146 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3147 } 3148 3149 return NULL; 3150 } 3151 3152 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3153 { 3154 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3155 3156 return g_strdup(spapr->kvm_type); 3157 } 3158 3159 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3160 { 3161 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3162 3163 g_free(spapr->kvm_type); 3164 spapr->kvm_type = g_strdup(value); 3165 } 3166 3167 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3168 { 3169 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3170 3171 return spapr->use_hotplug_event_source; 3172 } 3173 3174 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3175 Error **errp) 3176 { 3177 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3178 3179 spapr->use_hotplug_event_source = value; 3180 } 3181 3182 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3183 { 3184 return true; 3185 } 3186 3187 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3188 { 3189 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3190 3191 switch (spapr->resize_hpt) { 3192 case SPAPR_RESIZE_HPT_DEFAULT: 3193 return g_strdup("default"); 3194 case SPAPR_RESIZE_HPT_DISABLED: 3195 return g_strdup("disabled"); 3196 case SPAPR_RESIZE_HPT_ENABLED: 3197 return g_strdup("enabled"); 3198 case SPAPR_RESIZE_HPT_REQUIRED: 3199 return g_strdup("required"); 3200 } 3201 g_assert_not_reached(); 3202 } 3203 3204 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3205 { 3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3207 3208 if (strcmp(value, "default") == 0) { 3209 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3210 } else if (strcmp(value, "disabled") == 0) { 3211 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3212 } else if (strcmp(value, "enabled") == 0) { 3213 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3214 } else if (strcmp(value, "required") == 0) { 3215 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3216 } else { 3217 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3218 } 3219 } 3220 3221 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3222 void *opaque, Error **errp) 3223 { 3224 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3225 } 3226 3227 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3228 void *opaque, Error **errp) 3229 { 3230 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3231 } 3232 3233 static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name, 3234 void *opaque, Error **errp) 3235 { 3236 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3237 } 3238 3239 static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name, 3240 void *opaque, Error **errp) 3241 { 3242 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3243 } 3244 3245 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3246 { 3247 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3248 3249 if (spapr->irq == &spapr_irq_xics_legacy) { 3250 return g_strdup("legacy"); 3251 } else if (spapr->irq == &spapr_irq_xics) { 3252 return g_strdup("xics"); 3253 } else if (spapr->irq == &spapr_irq_xive) { 3254 return g_strdup("xive"); 3255 } else if (spapr->irq == &spapr_irq_dual) { 3256 return g_strdup("dual"); 3257 } 3258 g_assert_not_reached(); 3259 } 3260 3261 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3262 { 3263 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3264 3265 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3266 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3267 return; 3268 } 3269 3270 /* The legacy IRQ backend can not be set */ 3271 if (strcmp(value, "xics") == 0) { 3272 spapr->irq = &spapr_irq_xics; 3273 } else if (strcmp(value, "xive") == 0) { 3274 spapr->irq = &spapr_irq_xive; 3275 } else if (strcmp(value, "dual") == 0) { 3276 spapr->irq = &spapr_irq_dual; 3277 } else { 3278 error_setg(errp, "Bad value for \"ic-mode\" property"); 3279 } 3280 } 3281 3282 static char *spapr_get_host_model(Object *obj, Error **errp) 3283 { 3284 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3285 3286 return g_strdup(spapr->host_model); 3287 } 3288 3289 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3290 { 3291 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3292 3293 g_free(spapr->host_model); 3294 spapr->host_model = g_strdup(value); 3295 } 3296 3297 static char *spapr_get_host_serial(Object *obj, Error **errp) 3298 { 3299 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3300 3301 return g_strdup(spapr->host_serial); 3302 } 3303 3304 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3305 { 3306 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3307 3308 g_free(spapr->host_serial); 3309 spapr->host_serial = g_strdup(value); 3310 } 3311 3312 static void spapr_instance_init(Object *obj) 3313 { 3314 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3315 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3316 3317 spapr->htab_fd = -1; 3318 spapr->use_hotplug_event_source = true; 3319 object_property_add_str(obj, "kvm-type", 3320 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3321 object_property_set_description(obj, "kvm-type", 3322 "Specifies the KVM virtualization mode (HV, PR)", 3323 NULL); 3324 object_property_add_bool(obj, "modern-hotplug-events", 3325 spapr_get_modern_hotplug_events, 3326 spapr_set_modern_hotplug_events, 3327 NULL); 3328 object_property_set_description(obj, "modern-hotplug-events", 3329 "Use dedicated hotplug event mechanism in" 3330 " place of standard EPOW events when possible" 3331 " (required for memory hot-unplug support)", 3332 NULL); 3333 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3334 "Maximum permitted CPU compatibility mode", 3335 &error_fatal); 3336 3337 object_property_add_str(obj, "resize-hpt", 3338 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3339 object_property_set_description(obj, "resize-hpt", 3340 "Resizing of the Hash Page Table (enabled, disabled, required)", 3341 NULL); 3342 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3343 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3344 object_property_set_description(obj, "vsmt", 3345 "Virtual SMT: KVM behaves as if this were" 3346 " the host's SMT mode", &error_abort); 3347 object_property_add_bool(obj, "vfio-no-msix-emulation", 3348 spapr_get_msix_emulation, NULL, NULL); 3349 3350 object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr, 3351 spapr_set_kernel_addr, NULL, &spapr->kernel_addr, 3352 &error_abort); 3353 object_property_set_description(obj, "kernel-addr", 3354 stringify(KERNEL_LOAD_ADDR) 3355 " for -kernel is the default", 3356 NULL); 3357 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3358 /* The machine class defines the default interrupt controller mode */ 3359 spapr->irq = smc->irq; 3360 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3361 spapr_set_ic_mode, NULL); 3362 object_property_set_description(obj, "ic-mode", 3363 "Specifies the interrupt controller mode (xics, xive, dual)", 3364 NULL); 3365 3366 object_property_add_str(obj, "host-model", 3367 spapr_get_host_model, spapr_set_host_model, 3368 &error_abort); 3369 object_property_set_description(obj, "host-model", 3370 "Host model to advertise in guest device tree", &error_abort); 3371 object_property_add_str(obj, "host-serial", 3372 spapr_get_host_serial, spapr_set_host_serial, 3373 &error_abort); 3374 object_property_set_description(obj, "host-serial", 3375 "Host serial number to advertise in guest device tree", &error_abort); 3376 } 3377 3378 static void spapr_machine_finalizefn(Object *obj) 3379 { 3380 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3381 3382 g_free(spapr->kvm_type); 3383 } 3384 3385 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3386 { 3387 cpu_synchronize_state(cs); 3388 ppc_cpu_do_system_reset(cs); 3389 } 3390 3391 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3392 { 3393 CPUState *cs; 3394 3395 CPU_FOREACH(cs) { 3396 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3397 } 3398 } 3399 3400 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3401 void *fdt, int *fdt_start_offset, Error **errp) 3402 { 3403 uint64_t addr; 3404 uint32_t node; 3405 3406 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3407 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3408 &error_abort); 3409 *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr, 3410 SPAPR_MEMORY_BLOCK_SIZE); 3411 return 0; 3412 } 3413 3414 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3415 bool dedicated_hp_event_source, Error **errp) 3416 { 3417 SpaprDrc *drc; 3418 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3419 int i; 3420 uint64_t addr = addr_start; 3421 bool hotplugged = spapr_drc_hotplugged(dev); 3422 Error *local_err = NULL; 3423 3424 for (i = 0; i < nr_lmbs; i++) { 3425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3426 addr / SPAPR_MEMORY_BLOCK_SIZE); 3427 g_assert(drc); 3428 3429 spapr_drc_attach(drc, dev, &local_err); 3430 if (local_err) { 3431 while (addr > addr_start) { 3432 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3433 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3434 addr / SPAPR_MEMORY_BLOCK_SIZE); 3435 spapr_drc_detach(drc); 3436 } 3437 error_propagate(errp, local_err); 3438 return; 3439 } 3440 if (!hotplugged) { 3441 spapr_drc_reset(drc); 3442 } 3443 addr += SPAPR_MEMORY_BLOCK_SIZE; 3444 } 3445 /* send hotplug notification to the 3446 * guest only in case of hotplugged memory 3447 */ 3448 if (hotplugged) { 3449 if (dedicated_hp_event_source) { 3450 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3451 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3452 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3453 nr_lmbs, 3454 spapr_drc_index(drc)); 3455 } else { 3456 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3457 nr_lmbs); 3458 } 3459 } 3460 } 3461 3462 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3463 Error **errp) 3464 { 3465 Error *local_err = NULL; 3466 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3467 PCDIMMDevice *dimm = PC_DIMM(dev); 3468 uint64_t size, addr, slot; 3469 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3470 3471 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3472 3473 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3474 if (local_err) { 3475 goto out; 3476 } 3477 3478 if (!is_nvdimm) { 3479 addr = object_property_get_uint(OBJECT(dimm), 3480 PC_DIMM_ADDR_PROP, &local_err); 3481 if (local_err) { 3482 goto out_unplug; 3483 } 3484 spapr_add_lmbs(dev, addr, size, 3485 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3486 &local_err); 3487 } else { 3488 slot = object_property_get_uint(OBJECT(dimm), 3489 PC_DIMM_SLOT_PROP, &local_err); 3490 if (local_err) { 3491 goto out_unplug; 3492 } 3493 spapr_add_nvdimm(dev, slot, &local_err); 3494 } 3495 3496 if (local_err) { 3497 goto out_unplug; 3498 } 3499 3500 return; 3501 3502 out_unplug: 3503 pc_dimm_unplug(dimm, MACHINE(ms)); 3504 out: 3505 error_propagate(errp, local_err); 3506 } 3507 3508 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3509 Error **errp) 3510 { 3511 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3512 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3513 const MachineClass *mc = MACHINE_CLASS(smc); 3514 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3515 PCDIMMDevice *dimm = PC_DIMM(dev); 3516 Error *local_err = NULL; 3517 uint64_t size; 3518 Object *memdev; 3519 hwaddr pagesize; 3520 3521 if (!smc->dr_lmb_enabled) { 3522 error_setg(errp, "Memory hotplug not supported for this machine"); 3523 return; 3524 } 3525 3526 if (is_nvdimm && !mc->nvdimm_supported) { 3527 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3528 return; 3529 } 3530 3531 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3532 if (local_err) { 3533 error_propagate(errp, local_err); 3534 return; 3535 } 3536 3537 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3538 error_setg(errp, "Hotplugged memory size must be a multiple of " 3539 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3540 return; 3541 } else if (is_nvdimm) { 3542 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3543 if (local_err) { 3544 error_propagate(errp, local_err); 3545 return; 3546 } 3547 } 3548 3549 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3550 &error_abort); 3551 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3552 spapr_check_pagesize(spapr, pagesize, &local_err); 3553 if (local_err) { 3554 error_propagate(errp, local_err); 3555 return; 3556 } 3557 3558 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3559 } 3560 3561 struct SpaprDimmState { 3562 PCDIMMDevice *dimm; 3563 uint32_t nr_lmbs; 3564 QTAILQ_ENTRY(SpaprDimmState) next; 3565 }; 3566 3567 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3568 PCDIMMDevice *dimm) 3569 { 3570 SpaprDimmState *dimm_state = NULL; 3571 3572 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3573 if (dimm_state->dimm == dimm) { 3574 break; 3575 } 3576 } 3577 return dimm_state; 3578 } 3579 3580 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3581 uint32_t nr_lmbs, 3582 PCDIMMDevice *dimm) 3583 { 3584 SpaprDimmState *ds = NULL; 3585 3586 /* 3587 * If this request is for a DIMM whose removal had failed earlier 3588 * (due to guest's refusal to remove the LMBs), we would have this 3589 * dimm already in the pending_dimm_unplugs list. In that 3590 * case don't add again. 3591 */ 3592 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3593 if (!ds) { 3594 ds = g_malloc0(sizeof(SpaprDimmState)); 3595 ds->nr_lmbs = nr_lmbs; 3596 ds->dimm = dimm; 3597 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3598 } 3599 return ds; 3600 } 3601 3602 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3603 SpaprDimmState *dimm_state) 3604 { 3605 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3606 g_free(dimm_state); 3607 } 3608 3609 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3610 PCDIMMDevice *dimm) 3611 { 3612 SpaprDrc *drc; 3613 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3614 &error_abort); 3615 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3616 uint32_t avail_lmbs = 0; 3617 uint64_t addr_start, addr; 3618 int i; 3619 3620 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3621 &error_abort); 3622 3623 addr = addr_start; 3624 for (i = 0; i < nr_lmbs; i++) { 3625 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3626 addr / SPAPR_MEMORY_BLOCK_SIZE); 3627 g_assert(drc); 3628 if (drc->dev) { 3629 avail_lmbs++; 3630 } 3631 addr += SPAPR_MEMORY_BLOCK_SIZE; 3632 } 3633 3634 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3635 } 3636 3637 /* Callback to be called during DRC release. */ 3638 void spapr_lmb_release(DeviceState *dev) 3639 { 3640 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3641 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3642 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3643 3644 /* This information will get lost if a migration occurs 3645 * during the unplug process. In this case recover it. */ 3646 if (ds == NULL) { 3647 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3648 g_assert(ds); 3649 /* The DRC being examined by the caller at least must be counted */ 3650 g_assert(ds->nr_lmbs); 3651 } 3652 3653 if (--ds->nr_lmbs) { 3654 return; 3655 } 3656 3657 /* 3658 * Now that all the LMBs have been removed by the guest, call the 3659 * unplug handler chain. This can never fail. 3660 */ 3661 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3662 object_unparent(OBJECT(dev)); 3663 } 3664 3665 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3666 { 3667 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3668 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3669 3670 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3671 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3672 spapr_pending_dimm_unplugs_remove(spapr, ds); 3673 } 3674 3675 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3676 DeviceState *dev, Error **errp) 3677 { 3678 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3679 Error *local_err = NULL; 3680 PCDIMMDevice *dimm = PC_DIMM(dev); 3681 uint32_t nr_lmbs; 3682 uint64_t size, addr_start, addr; 3683 int i; 3684 SpaprDrc *drc; 3685 3686 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3687 error_setg(&local_err, 3688 "nvdimm device hot unplug is not supported yet."); 3689 goto out; 3690 } 3691 3692 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3693 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3694 3695 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3696 &local_err); 3697 if (local_err) { 3698 goto out; 3699 } 3700 3701 /* 3702 * An existing pending dimm state for this DIMM means that there is an 3703 * unplug operation in progress, waiting for the spapr_lmb_release 3704 * callback to complete the job (BQL can't cover that far). In this case, 3705 * bail out to avoid detaching DRCs that were already released. 3706 */ 3707 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3708 error_setg(&local_err, 3709 "Memory unplug already in progress for device %s", 3710 dev->id); 3711 goto out; 3712 } 3713 3714 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3715 3716 addr = addr_start; 3717 for (i = 0; i < nr_lmbs; i++) { 3718 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3719 addr / SPAPR_MEMORY_BLOCK_SIZE); 3720 g_assert(drc); 3721 3722 spapr_drc_detach(drc); 3723 addr += SPAPR_MEMORY_BLOCK_SIZE; 3724 } 3725 3726 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3727 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3728 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3729 nr_lmbs, spapr_drc_index(drc)); 3730 out: 3731 error_propagate(errp, local_err); 3732 } 3733 3734 /* Callback to be called during DRC release. */ 3735 void spapr_core_release(DeviceState *dev) 3736 { 3737 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3738 3739 /* Call the unplug handler chain. This can never fail. */ 3740 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3741 object_unparent(OBJECT(dev)); 3742 } 3743 3744 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3745 { 3746 MachineState *ms = MACHINE(hotplug_dev); 3747 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3748 CPUCore *cc = CPU_CORE(dev); 3749 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3750 3751 if (smc->pre_2_10_has_unused_icps) { 3752 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3753 int i; 3754 3755 for (i = 0; i < cc->nr_threads; i++) { 3756 CPUState *cs = CPU(sc->threads[i]); 3757 3758 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3759 } 3760 } 3761 3762 assert(core_slot); 3763 core_slot->cpu = NULL; 3764 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3765 } 3766 3767 static 3768 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3769 Error **errp) 3770 { 3771 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3772 int index; 3773 SpaprDrc *drc; 3774 CPUCore *cc = CPU_CORE(dev); 3775 3776 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3777 error_setg(errp, "Unable to find CPU core with core-id: %d", 3778 cc->core_id); 3779 return; 3780 } 3781 if (index == 0) { 3782 error_setg(errp, "Boot CPU core may not be unplugged"); 3783 return; 3784 } 3785 3786 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3787 spapr_vcpu_id(spapr, cc->core_id)); 3788 g_assert(drc); 3789 3790 if (!spapr_drc_unplug_requested(drc)) { 3791 spapr_drc_detach(drc); 3792 spapr_hotplug_req_remove_by_index(drc); 3793 } 3794 } 3795 3796 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3797 void *fdt, int *fdt_start_offset, Error **errp) 3798 { 3799 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3800 CPUState *cs = CPU(core->threads[0]); 3801 PowerPCCPU *cpu = POWERPC_CPU(cs); 3802 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3803 int id = spapr_get_vcpu_id(cpu); 3804 char *nodename; 3805 int offset; 3806 3807 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3808 offset = fdt_add_subnode(fdt, 0, nodename); 3809 g_free(nodename); 3810 3811 spapr_dt_cpu(cs, fdt, offset, spapr); 3812 3813 *fdt_start_offset = offset; 3814 return 0; 3815 } 3816 3817 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3818 Error **errp) 3819 { 3820 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3821 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3822 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3823 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3824 CPUCore *cc = CPU_CORE(dev); 3825 CPUState *cs; 3826 SpaprDrc *drc; 3827 Error *local_err = NULL; 3828 CPUArchId *core_slot; 3829 int index; 3830 bool hotplugged = spapr_drc_hotplugged(dev); 3831 int i; 3832 3833 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3834 if (!core_slot) { 3835 error_setg(errp, "Unable to find CPU core with core-id: %d", 3836 cc->core_id); 3837 return; 3838 } 3839 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3840 spapr_vcpu_id(spapr, cc->core_id)); 3841 3842 g_assert(drc || !mc->has_hotpluggable_cpus); 3843 3844 if (drc) { 3845 spapr_drc_attach(drc, dev, &local_err); 3846 if (local_err) { 3847 error_propagate(errp, local_err); 3848 return; 3849 } 3850 3851 if (hotplugged) { 3852 /* 3853 * Send hotplug notification interrupt to the guest only 3854 * in case of hotplugged CPUs. 3855 */ 3856 spapr_hotplug_req_add_by_index(drc); 3857 } else { 3858 spapr_drc_reset(drc); 3859 } 3860 } 3861 3862 core_slot->cpu = OBJECT(dev); 3863 3864 if (smc->pre_2_10_has_unused_icps) { 3865 for (i = 0; i < cc->nr_threads; i++) { 3866 cs = CPU(core->threads[i]); 3867 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3868 } 3869 } 3870 3871 /* 3872 * Set compatibility mode to match the boot CPU, which was either set 3873 * by the machine reset code or by CAS. 3874 */ 3875 if (hotplugged) { 3876 for (i = 0; i < cc->nr_threads; i++) { 3877 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3878 &local_err); 3879 if (local_err) { 3880 error_propagate(errp, local_err); 3881 return; 3882 } 3883 } 3884 } 3885 } 3886 3887 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3888 Error **errp) 3889 { 3890 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3891 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3892 Error *local_err = NULL; 3893 CPUCore *cc = CPU_CORE(dev); 3894 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3895 const char *type = object_get_typename(OBJECT(dev)); 3896 CPUArchId *core_slot; 3897 int index; 3898 unsigned int smp_threads = machine->smp.threads; 3899 3900 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3901 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3902 goto out; 3903 } 3904 3905 if (strcmp(base_core_type, type)) { 3906 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3907 goto out; 3908 } 3909 3910 if (cc->core_id % smp_threads) { 3911 error_setg(&local_err, "invalid core id %d", cc->core_id); 3912 goto out; 3913 } 3914 3915 /* 3916 * In general we should have homogeneous threads-per-core, but old 3917 * (pre hotplug support) machine types allow the last core to have 3918 * reduced threads as a compatibility hack for when we allowed 3919 * total vcpus not a multiple of threads-per-core. 3920 */ 3921 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3922 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3923 cc->nr_threads, smp_threads); 3924 goto out; 3925 } 3926 3927 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3928 if (!core_slot) { 3929 error_setg(&local_err, "core id %d out of range", cc->core_id); 3930 goto out; 3931 } 3932 3933 if (core_slot->cpu) { 3934 error_setg(&local_err, "core %d already populated", cc->core_id); 3935 goto out; 3936 } 3937 3938 numa_cpu_pre_plug(core_slot, dev, &local_err); 3939 3940 out: 3941 error_propagate(errp, local_err); 3942 } 3943 3944 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3945 void *fdt, int *fdt_start_offset, Error **errp) 3946 { 3947 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3948 int intc_phandle; 3949 3950 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3951 if (intc_phandle <= 0) { 3952 return -1; 3953 } 3954 3955 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3956 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3957 return -1; 3958 } 3959 3960 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3961 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3962 3963 return 0; 3964 } 3965 3966 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3967 Error **errp) 3968 { 3969 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3970 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3971 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3972 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3973 3974 if (dev->hotplugged && !smc->dr_phb_enabled) { 3975 error_setg(errp, "PHB hotplug not supported for this machine"); 3976 return; 3977 } 3978 3979 if (sphb->index == (uint32_t)-1) { 3980 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3981 return; 3982 } 3983 3984 /* 3985 * This will check that sphb->index doesn't exceed the maximum number of 3986 * PHBs for the current machine type. 3987 */ 3988 smc->phb_placement(spapr, sphb->index, 3989 &sphb->buid, &sphb->io_win_addr, 3990 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3991 windows_supported, sphb->dma_liobn, 3992 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3993 errp); 3994 } 3995 3996 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3997 Error **errp) 3998 { 3999 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4000 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4001 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4002 SpaprDrc *drc; 4003 bool hotplugged = spapr_drc_hotplugged(dev); 4004 Error *local_err = NULL; 4005 4006 if (!smc->dr_phb_enabled) { 4007 return; 4008 } 4009 4010 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4011 /* hotplug hooks should check it's enabled before getting this far */ 4012 assert(drc); 4013 4014 spapr_drc_attach(drc, DEVICE(dev), &local_err); 4015 if (local_err) { 4016 error_propagate(errp, local_err); 4017 return; 4018 } 4019 4020 if (hotplugged) { 4021 spapr_hotplug_req_add_by_index(drc); 4022 } else { 4023 spapr_drc_reset(drc); 4024 } 4025 } 4026 4027 void spapr_phb_release(DeviceState *dev) 4028 { 4029 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4030 4031 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4032 object_unparent(OBJECT(dev)); 4033 } 4034 4035 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4036 { 4037 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4038 } 4039 4040 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4041 DeviceState *dev, Error **errp) 4042 { 4043 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4044 SpaprDrc *drc; 4045 4046 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4047 assert(drc); 4048 4049 if (!spapr_drc_unplug_requested(drc)) { 4050 spapr_drc_detach(drc); 4051 spapr_hotplug_req_remove_by_index(drc); 4052 } 4053 } 4054 4055 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4056 Error **errp) 4057 { 4058 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4059 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4060 4061 if (spapr->tpm_proxy != NULL) { 4062 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4063 return; 4064 } 4065 4066 spapr->tpm_proxy = tpm_proxy; 4067 } 4068 4069 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4070 { 4071 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4072 4073 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4074 object_unparent(OBJECT(dev)); 4075 spapr->tpm_proxy = NULL; 4076 } 4077 4078 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4079 DeviceState *dev, Error **errp) 4080 { 4081 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4082 spapr_memory_plug(hotplug_dev, dev, errp); 4083 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4084 spapr_core_plug(hotplug_dev, dev, errp); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4086 spapr_phb_plug(hotplug_dev, dev, errp); 4087 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4088 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4089 } 4090 } 4091 4092 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4093 DeviceState *dev, Error **errp) 4094 { 4095 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4096 spapr_memory_unplug(hotplug_dev, dev); 4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4098 spapr_core_unplug(hotplug_dev, dev); 4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4100 spapr_phb_unplug(hotplug_dev, dev); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4102 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4103 } 4104 } 4105 4106 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4107 DeviceState *dev, Error **errp) 4108 { 4109 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4110 MachineClass *mc = MACHINE_GET_CLASS(sms); 4111 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4112 4113 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4114 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4115 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4116 } else { 4117 /* NOTE: this means there is a window after guest reset, prior to 4118 * CAS negotiation, where unplug requests will fail due to the 4119 * capability not being detected yet. This is a bit different than 4120 * the case with PCI unplug, where the events will be queued and 4121 * eventually handled by the guest after boot 4122 */ 4123 error_setg(errp, "Memory hot unplug not supported for this guest"); 4124 } 4125 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4126 if (!mc->has_hotpluggable_cpus) { 4127 error_setg(errp, "CPU hot unplug not supported on this machine"); 4128 return; 4129 } 4130 spapr_core_unplug_request(hotplug_dev, dev, errp); 4131 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4132 if (!smc->dr_phb_enabled) { 4133 error_setg(errp, "PHB hot unplug not supported on this machine"); 4134 return; 4135 } 4136 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4137 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4138 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4139 } 4140 } 4141 4142 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4143 DeviceState *dev, Error **errp) 4144 { 4145 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4146 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4147 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4148 spapr_core_pre_plug(hotplug_dev, dev, errp); 4149 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4150 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4151 } 4152 } 4153 4154 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4155 DeviceState *dev) 4156 { 4157 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4158 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4159 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4160 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4161 return HOTPLUG_HANDLER(machine); 4162 } 4163 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4164 PCIDevice *pcidev = PCI_DEVICE(dev); 4165 PCIBus *root = pci_device_root_bus(pcidev); 4166 SpaprPhbState *phb = 4167 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4168 TYPE_SPAPR_PCI_HOST_BRIDGE); 4169 4170 if (phb) { 4171 return HOTPLUG_HANDLER(phb); 4172 } 4173 } 4174 return NULL; 4175 } 4176 4177 static CpuInstanceProperties 4178 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4179 { 4180 CPUArchId *core_slot; 4181 MachineClass *mc = MACHINE_GET_CLASS(machine); 4182 4183 /* make sure possible_cpu are intialized */ 4184 mc->possible_cpu_arch_ids(machine); 4185 /* get CPU core slot containing thread that matches cpu_index */ 4186 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4187 assert(core_slot); 4188 return core_slot->props; 4189 } 4190 4191 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4192 { 4193 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4194 } 4195 4196 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4197 { 4198 int i; 4199 unsigned int smp_threads = machine->smp.threads; 4200 unsigned int smp_cpus = machine->smp.cpus; 4201 const char *core_type; 4202 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4203 MachineClass *mc = MACHINE_GET_CLASS(machine); 4204 4205 if (!mc->has_hotpluggable_cpus) { 4206 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4207 } 4208 if (machine->possible_cpus) { 4209 assert(machine->possible_cpus->len == spapr_max_cores); 4210 return machine->possible_cpus; 4211 } 4212 4213 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4214 if (!core_type) { 4215 error_report("Unable to find sPAPR CPU Core definition"); 4216 exit(1); 4217 } 4218 4219 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4220 sizeof(CPUArchId) * spapr_max_cores); 4221 machine->possible_cpus->len = spapr_max_cores; 4222 for (i = 0; i < machine->possible_cpus->len; i++) { 4223 int core_id = i * smp_threads; 4224 4225 machine->possible_cpus->cpus[i].type = core_type; 4226 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4227 machine->possible_cpus->cpus[i].arch_id = core_id; 4228 machine->possible_cpus->cpus[i].props.has_core_id = true; 4229 machine->possible_cpus->cpus[i].props.core_id = core_id; 4230 } 4231 return machine->possible_cpus; 4232 } 4233 4234 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4235 uint64_t *buid, hwaddr *pio, 4236 hwaddr *mmio32, hwaddr *mmio64, 4237 unsigned n_dma, uint32_t *liobns, 4238 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4239 { 4240 /* 4241 * New-style PHB window placement. 4242 * 4243 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4244 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4245 * windows. 4246 * 4247 * Some guest kernels can't work with MMIO windows above 1<<46 4248 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4249 * 4250 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4251 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4252 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4253 * 1TiB 64-bit MMIO windows for each PHB. 4254 */ 4255 const uint64_t base_buid = 0x800000020000000ULL; 4256 int i; 4257 4258 /* Sanity check natural alignments */ 4259 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4260 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4261 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4262 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4263 /* Sanity check bounds */ 4264 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4265 SPAPR_PCI_MEM32_WIN_SIZE); 4266 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4267 SPAPR_PCI_MEM64_WIN_SIZE); 4268 4269 if (index >= SPAPR_MAX_PHBS) { 4270 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4271 SPAPR_MAX_PHBS - 1); 4272 return; 4273 } 4274 4275 *buid = base_buid + index; 4276 for (i = 0; i < n_dma; ++i) { 4277 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4278 } 4279 4280 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4281 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4282 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4283 4284 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4285 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4286 } 4287 4288 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4289 { 4290 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4291 4292 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4293 } 4294 4295 static void spapr_ics_resend(XICSFabric *dev) 4296 { 4297 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4298 4299 ics_resend(spapr->ics); 4300 } 4301 4302 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4303 { 4304 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4305 4306 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4307 } 4308 4309 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4310 Monitor *mon) 4311 { 4312 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4313 4314 spapr_irq_print_info(spapr, mon); 4315 monitor_printf(mon, "irqchip: %s\n", 4316 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4317 } 4318 4319 /* 4320 * This is a XIVE only operation 4321 */ 4322 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4323 uint8_t nvt_blk, uint32_t nvt_idx, 4324 bool cam_ignore, uint8_t priority, 4325 uint32_t logic_serv, XiveTCTXMatch *match) 4326 { 4327 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4328 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4329 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4330 int count; 4331 4332 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4333 priority, logic_serv, match); 4334 if (count < 0) { 4335 return count; 4336 } 4337 4338 /* 4339 * When we implement the save and restore of the thread interrupt 4340 * contexts in the enter/exit CPU handlers of the machine and the 4341 * escalations in QEMU, we should be able to handle non dispatched 4342 * vCPUs. 4343 * 4344 * Until this is done, the sPAPR machine should find at least one 4345 * matching context always. 4346 */ 4347 if (count == 0) { 4348 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4349 nvt_blk, nvt_idx); 4350 } 4351 4352 return count; 4353 } 4354 4355 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4356 { 4357 return cpu->vcpu_id; 4358 } 4359 4360 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4361 { 4362 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4363 MachineState *ms = MACHINE(spapr); 4364 int vcpu_id; 4365 4366 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4367 4368 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4369 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4370 error_append_hint(errp, "Adjust the number of cpus to %d " 4371 "or try to raise the number of threads per core\n", 4372 vcpu_id * ms->smp.threads / spapr->vsmt); 4373 return; 4374 } 4375 4376 cpu->vcpu_id = vcpu_id; 4377 } 4378 4379 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4380 { 4381 CPUState *cs; 4382 4383 CPU_FOREACH(cs) { 4384 PowerPCCPU *cpu = POWERPC_CPU(cs); 4385 4386 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4387 return cpu; 4388 } 4389 } 4390 4391 return NULL; 4392 } 4393 4394 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4395 { 4396 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4397 4398 /* These are only called by TCG, KVM maintains dispatch state */ 4399 4400 spapr_cpu->prod = false; 4401 if (spapr_cpu->vpa_addr) { 4402 CPUState *cs = CPU(cpu); 4403 uint32_t dispatch; 4404 4405 dispatch = ldl_be_phys(cs->as, 4406 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4407 dispatch++; 4408 if ((dispatch & 1) != 0) { 4409 qemu_log_mask(LOG_GUEST_ERROR, 4410 "VPA: incorrect dispatch counter value for " 4411 "dispatched partition %u, correcting.\n", dispatch); 4412 dispatch++; 4413 } 4414 stl_be_phys(cs->as, 4415 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4416 } 4417 } 4418 4419 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4420 { 4421 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4422 4423 if (spapr_cpu->vpa_addr) { 4424 CPUState *cs = CPU(cpu); 4425 uint32_t dispatch; 4426 4427 dispatch = ldl_be_phys(cs->as, 4428 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4429 dispatch++; 4430 if ((dispatch & 1) != 1) { 4431 qemu_log_mask(LOG_GUEST_ERROR, 4432 "VPA: incorrect dispatch counter value for " 4433 "preempted partition %u, correcting.\n", dispatch); 4434 dispatch++; 4435 } 4436 stl_be_phys(cs->as, 4437 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4438 } 4439 } 4440 4441 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4442 { 4443 MachineClass *mc = MACHINE_CLASS(oc); 4444 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4445 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4446 NMIClass *nc = NMI_CLASS(oc); 4447 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4448 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4449 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4450 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4451 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4452 4453 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4454 mc->ignore_boot_device_suffixes = true; 4455 4456 /* 4457 * We set up the default / latest behaviour here. The class_init 4458 * functions for the specific versioned machine types can override 4459 * these details for backwards compatibility 4460 */ 4461 mc->init = spapr_machine_init; 4462 mc->reset = spapr_machine_reset; 4463 mc->block_default_type = IF_SCSI; 4464 mc->max_cpus = 1024; 4465 mc->no_parallel = 1; 4466 mc->default_boot_order = ""; 4467 mc->default_ram_size = 512 * MiB; 4468 mc->default_ram_id = "ppc_spapr.ram"; 4469 mc->default_display = "std"; 4470 mc->kvm_type = spapr_kvm_type; 4471 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4472 mc->pci_allow_0_address = true; 4473 assert(!mc->get_hotplug_handler); 4474 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4475 hc->pre_plug = spapr_machine_device_pre_plug; 4476 hc->plug = spapr_machine_device_plug; 4477 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4478 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4479 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4480 hc->unplug_request = spapr_machine_device_unplug_request; 4481 hc->unplug = spapr_machine_device_unplug; 4482 4483 smc->dr_lmb_enabled = true; 4484 smc->update_dt_enabled = true; 4485 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4486 mc->has_hotpluggable_cpus = true; 4487 mc->nvdimm_supported = true; 4488 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4489 fwc->get_dev_path = spapr_get_fw_dev_path; 4490 nc->nmi_monitor_handler = spapr_nmi; 4491 smc->phb_placement = spapr_phb_placement; 4492 vhc->hypercall = emulate_spapr_hypercall; 4493 vhc->hpt_mask = spapr_hpt_mask; 4494 vhc->map_hptes = spapr_map_hptes; 4495 vhc->unmap_hptes = spapr_unmap_hptes; 4496 vhc->hpte_set_c = spapr_hpte_set_c; 4497 vhc->hpte_set_r = spapr_hpte_set_r; 4498 vhc->get_pate = spapr_get_pate; 4499 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4500 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4501 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4502 xic->ics_get = spapr_ics_get; 4503 xic->ics_resend = spapr_ics_resend; 4504 xic->icp_get = spapr_icp_get; 4505 ispc->print_info = spapr_pic_print_info; 4506 /* Force NUMA node memory size to be a multiple of 4507 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4508 * in which LMBs are represented and hot-added 4509 */ 4510 mc->numa_mem_align_shift = 28; 4511 mc->numa_mem_supported = true; 4512 mc->auto_enable_numa = true; 4513 4514 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4515 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4516 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4517 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4518 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4519 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4520 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4521 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4522 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4523 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4524 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4525 spapr_caps_add_properties(smc, &error_abort); 4526 smc->irq = &spapr_irq_dual; 4527 smc->dr_phb_enabled = true; 4528 smc->linux_pci_probe = true; 4529 smc->smp_threads_vsmt = true; 4530 smc->nr_xirqs = SPAPR_NR_XIRQS; 4531 xfc->match_nvt = spapr_match_nvt; 4532 } 4533 4534 static const TypeInfo spapr_machine_info = { 4535 .name = TYPE_SPAPR_MACHINE, 4536 .parent = TYPE_MACHINE, 4537 .abstract = true, 4538 .instance_size = sizeof(SpaprMachineState), 4539 .instance_init = spapr_instance_init, 4540 .instance_finalize = spapr_machine_finalizefn, 4541 .class_size = sizeof(SpaprMachineClass), 4542 .class_init = spapr_machine_class_init, 4543 .interfaces = (InterfaceInfo[]) { 4544 { TYPE_FW_PATH_PROVIDER }, 4545 { TYPE_NMI }, 4546 { TYPE_HOTPLUG_HANDLER }, 4547 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4548 { TYPE_XICS_FABRIC }, 4549 { TYPE_INTERRUPT_STATS_PROVIDER }, 4550 { TYPE_XIVE_FABRIC }, 4551 { } 4552 }, 4553 }; 4554 4555 static void spapr_machine_latest_class_options(MachineClass *mc) 4556 { 4557 mc->alias = "pseries"; 4558 mc->is_default = true; 4559 } 4560 4561 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4562 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4563 void *data) \ 4564 { \ 4565 MachineClass *mc = MACHINE_CLASS(oc); \ 4566 spapr_machine_##suffix##_class_options(mc); \ 4567 if (latest) { \ 4568 spapr_machine_latest_class_options(mc); \ 4569 } \ 4570 } \ 4571 static const TypeInfo spapr_machine_##suffix##_info = { \ 4572 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4573 .parent = TYPE_SPAPR_MACHINE, \ 4574 .class_init = spapr_machine_##suffix##_class_init, \ 4575 }; \ 4576 static void spapr_machine_register_##suffix(void) \ 4577 { \ 4578 type_register(&spapr_machine_##suffix##_info); \ 4579 } \ 4580 type_init(spapr_machine_register_##suffix) 4581 4582 /* 4583 * pseries-5.0 4584 */ 4585 static void spapr_machine_5_0_class_options(MachineClass *mc) 4586 { 4587 /* Defaults for the latest behaviour inherited from the base class */ 4588 } 4589 4590 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4591 4592 /* 4593 * pseries-4.2 4594 */ 4595 static void spapr_machine_4_2_class_options(MachineClass *mc) 4596 { 4597 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4598 4599 spapr_machine_5_0_class_options(mc); 4600 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4601 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4602 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4603 smc->rma_limit = 16 * GiB; 4604 mc->nvdimm_supported = false; 4605 } 4606 4607 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4608 4609 /* 4610 * pseries-4.1 4611 */ 4612 static void spapr_machine_4_1_class_options(MachineClass *mc) 4613 { 4614 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4615 static GlobalProperty compat[] = { 4616 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4617 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4618 }; 4619 4620 spapr_machine_4_2_class_options(mc); 4621 smc->linux_pci_probe = false; 4622 smc->smp_threads_vsmt = false; 4623 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4624 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4625 } 4626 4627 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4628 4629 /* 4630 * pseries-4.0 4631 */ 4632 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4633 uint64_t *buid, hwaddr *pio, 4634 hwaddr *mmio32, hwaddr *mmio64, 4635 unsigned n_dma, uint32_t *liobns, 4636 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4637 { 4638 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4639 nv2gpa, nv2atsd, errp); 4640 *nv2gpa = 0; 4641 *nv2atsd = 0; 4642 } 4643 4644 static void spapr_machine_4_0_class_options(MachineClass *mc) 4645 { 4646 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4647 4648 spapr_machine_4_1_class_options(mc); 4649 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4650 smc->phb_placement = phb_placement_4_0; 4651 smc->irq = &spapr_irq_xics; 4652 smc->pre_4_1_migration = true; 4653 } 4654 4655 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4656 4657 /* 4658 * pseries-3.1 4659 */ 4660 static void spapr_machine_3_1_class_options(MachineClass *mc) 4661 { 4662 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4663 4664 spapr_machine_4_0_class_options(mc); 4665 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4666 4667 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4668 smc->update_dt_enabled = false; 4669 smc->dr_phb_enabled = false; 4670 smc->broken_host_serial_model = true; 4671 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4672 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4673 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4674 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4675 } 4676 4677 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4678 4679 /* 4680 * pseries-3.0 4681 */ 4682 4683 static void spapr_machine_3_0_class_options(MachineClass *mc) 4684 { 4685 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4686 4687 spapr_machine_3_1_class_options(mc); 4688 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4689 4690 smc->legacy_irq_allocation = true; 4691 smc->nr_xirqs = 0x400; 4692 smc->irq = &spapr_irq_xics_legacy; 4693 } 4694 4695 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4696 4697 /* 4698 * pseries-2.12 4699 */ 4700 static void spapr_machine_2_12_class_options(MachineClass *mc) 4701 { 4702 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4703 static GlobalProperty compat[] = { 4704 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4705 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4706 }; 4707 4708 spapr_machine_3_0_class_options(mc); 4709 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4710 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4711 4712 /* We depend on kvm_enabled() to choose a default value for the 4713 * hpt-max-page-size capability. Of course we can't do it here 4714 * because this is too early and the HW accelerator isn't initialzed 4715 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4716 */ 4717 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4718 } 4719 4720 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4721 4722 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4723 { 4724 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4725 4726 spapr_machine_2_12_class_options(mc); 4727 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4728 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4729 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4730 } 4731 4732 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4733 4734 /* 4735 * pseries-2.11 4736 */ 4737 4738 static void spapr_machine_2_11_class_options(MachineClass *mc) 4739 { 4740 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4741 4742 spapr_machine_2_12_class_options(mc); 4743 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4744 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4745 } 4746 4747 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4748 4749 /* 4750 * pseries-2.10 4751 */ 4752 4753 static void spapr_machine_2_10_class_options(MachineClass *mc) 4754 { 4755 spapr_machine_2_11_class_options(mc); 4756 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4757 } 4758 4759 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4760 4761 /* 4762 * pseries-2.9 4763 */ 4764 4765 static void spapr_machine_2_9_class_options(MachineClass *mc) 4766 { 4767 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4768 static GlobalProperty compat[] = { 4769 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4770 }; 4771 4772 spapr_machine_2_10_class_options(mc); 4773 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4774 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4775 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4776 smc->pre_2_10_has_unused_icps = true; 4777 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4778 } 4779 4780 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4781 4782 /* 4783 * pseries-2.8 4784 */ 4785 4786 static void spapr_machine_2_8_class_options(MachineClass *mc) 4787 { 4788 static GlobalProperty compat[] = { 4789 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4790 }; 4791 4792 spapr_machine_2_9_class_options(mc); 4793 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4794 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4795 mc->numa_mem_align_shift = 23; 4796 } 4797 4798 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4799 4800 /* 4801 * pseries-2.7 4802 */ 4803 4804 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4805 uint64_t *buid, hwaddr *pio, 4806 hwaddr *mmio32, hwaddr *mmio64, 4807 unsigned n_dma, uint32_t *liobns, 4808 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4809 { 4810 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4811 const uint64_t base_buid = 0x800000020000000ULL; 4812 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4813 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4814 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4815 const uint32_t max_index = 255; 4816 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4817 4818 uint64_t ram_top = MACHINE(spapr)->ram_size; 4819 hwaddr phb0_base, phb_base; 4820 int i; 4821 4822 /* Do we have device memory? */ 4823 if (MACHINE(spapr)->maxram_size > ram_top) { 4824 /* Can't just use maxram_size, because there may be an 4825 * alignment gap between normal and device memory regions 4826 */ 4827 ram_top = MACHINE(spapr)->device_memory->base + 4828 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4829 } 4830 4831 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4832 4833 if (index > max_index) { 4834 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4835 max_index); 4836 return; 4837 } 4838 4839 *buid = base_buid + index; 4840 for (i = 0; i < n_dma; ++i) { 4841 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4842 } 4843 4844 phb_base = phb0_base + index * phb_spacing; 4845 *pio = phb_base + pio_offset; 4846 *mmio32 = phb_base + mmio_offset; 4847 /* 4848 * We don't set the 64-bit MMIO window, relying on the PHB's 4849 * fallback behaviour of automatically splitting a large "32-bit" 4850 * window into contiguous 32-bit and 64-bit windows 4851 */ 4852 4853 *nv2gpa = 0; 4854 *nv2atsd = 0; 4855 } 4856 4857 static void spapr_machine_2_7_class_options(MachineClass *mc) 4858 { 4859 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4860 static GlobalProperty compat[] = { 4861 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4862 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4863 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4864 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4865 }; 4866 4867 spapr_machine_2_8_class_options(mc); 4868 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4869 mc->default_machine_opts = "modern-hotplug-events=off"; 4870 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4871 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4872 smc->phb_placement = phb_placement_2_7; 4873 } 4874 4875 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4876 4877 /* 4878 * pseries-2.6 4879 */ 4880 4881 static void spapr_machine_2_6_class_options(MachineClass *mc) 4882 { 4883 static GlobalProperty compat[] = { 4884 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4885 }; 4886 4887 spapr_machine_2_7_class_options(mc); 4888 mc->has_hotpluggable_cpus = false; 4889 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4890 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4891 } 4892 4893 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4894 4895 /* 4896 * pseries-2.5 4897 */ 4898 4899 static void spapr_machine_2_5_class_options(MachineClass *mc) 4900 { 4901 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4902 static GlobalProperty compat[] = { 4903 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4904 }; 4905 4906 spapr_machine_2_6_class_options(mc); 4907 smc->use_ohci_by_default = true; 4908 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4909 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4910 } 4911 4912 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4913 4914 /* 4915 * pseries-2.4 4916 */ 4917 4918 static void spapr_machine_2_4_class_options(MachineClass *mc) 4919 { 4920 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4921 4922 spapr_machine_2_5_class_options(mc); 4923 smc->dr_lmb_enabled = false; 4924 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4925 } 4926 4927 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4928 4929 /* 4930 * pseries-2.3 4931 */ 4932 4933 static void spapr_machine_2_3_class_options(MachineClass *mc) 4934 { 4935 static GlobalProperty compat[] = { 4936 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4937 }; 4938 spapr_machine_2_4_class_options(mc); 4939 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4940 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4941 } 4942 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4943 4944 /* 4945 * pseries-2.2 4946 */ 4947 4948 static void spapr_machine_2_2_class_options(MachineClass *mc) 4949 { 4950 static GlobalProperty compat[] = { 4951 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4952 }; 4953 4954 spapr_machine_2_3_class_options(mc); 4955 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4956 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4957 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4958 } 4959 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4960 4961 /* 4962 * pseries-2.1 4963 */ 4964 4965 static void spapr_machine_2_1_class_options(MachineClass *mc) 4966 { 4967 spapr_machine_2_2_class_options(mc); 4968 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4969 } 4970 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4971 4972 static void spapr_machine_register_types(void) 4973 { 4974 type_register_static(&spapr_machine_info); 4975 } 4976 4977 type_init(spapr_machine_register_types) 4978