1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "qemu/log.h" 42 #include "hw/fw-path-provider.h" 43 #include "elf.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/cpus.h" 47 #include "sysemu/hw_accel.h" 48 #include "kvm_ppc.h" 49 #include "migration/misc.h" 50 #include "migration/qemu-file-types.h" 51 #include "migration/global_state.h" 52 #include "migration/register.h" 53 #include "migration/blocker.h" 54 #include "mmu-hash64.h" 55 #include "mmu-book3s-v3.h" 56 #include "cpu-models.h" 57 #include "hw/core/cpu.h" 58 59 #include "hw/ppc/ppc.h" 60 #include "hw/loader.h" 61 62 #include "hw/ppc/fdt.h" 63 #include "hw/ppc/spapr.h" 64 #include "hw/ppc/spapr_nested.h" 65 #include "hw/ppc/spapr_vio.h" 66 #include "hw/ppc/vof.h" 67 #include "hw/qdev-properties.h" 68 #include "hw/pci-host/spapr.h" 69 #include "hw/pci/msi.h" 70 71 #include "hw/pci/pci.h" 72 #include "hw/scsi/scsi.h" 73 #include "hw/virtio/virtio-scsi.h" 74 #include "hw/virtio/vhost-scsi-common.h" 75 76 #include "exec/ram_addr.h" 77 #include "hw/usb.h" 78 #include "qemu/config-file.h" 79 #include "qemu/error-report.h" 80 #include "trace.h" 81 #include "hw/nmi.h" 82 #include "hw/intc/intc.h" 83 84 #include "hw/ppc/spapr_cpu_core.h" 85 #include "hw/mem/memory-device.h" 86 #include "hw/ppc/spapr_tpm_proxy.h" 87 #include "hw/ppc/spapr_nvdimm.h" 88 #include "hw/ppc/spapr_numa.h" 89 #include "hw/ppc/pef.h" 90 91 #include "monitor/monitor.h" 92 93 #include <libfdt.h> 94 95 /* SLOF memory layout: 96 * 97 * SLOF raw image loaded at 0, copies its romfs right below the flat 98 * device-tree, then position SLOF itself 31M below that 99 * 100 * So we set FW_OVERHEAD to 40MB which should account for all of that 101 * and more 102 * 103 * We load our kernel at 4M, leaving space for SLOF initial image 104 */ 105 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 106 #define FW_MAX_SIZE 0x400000 107 #define FW_FILE_NAME "slof.bin" 108 #define FW_FILE_NAME_VOF "vof.bin" 109 #define FW_OVERHEAD 0x2800000 110 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 111 112 #define MIN_RMA_SLOF (128 * MiB) 113 114 #define PHANDLE_INTC 0x00001111 115 116 /* These two functions implement the VCPU id numbering: one to compute them 117 * all and one to identify thread 0 of a VCORE. Any change to the first one 118 * is likely to have an impact on the second one, so let's keep them close. 119 */ 120 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 121 { 122 MachineState *ms = MACHINE(spapr); 123 unsigned int smp_threads = ms->smp.threads; 124 125 assert(spapr->vsmt); 126 return 127 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 128 } 129 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 130 PowerPCCPU *cpu) 131 { 132 assert(spapr->vsmt); 133 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 134 } 135 136 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 137 { 138 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 139 * and newer QEMUs don't even have them. In both cases, we don't want 140 * to send anything on the wire. 141 */ 142 return false; 143 } 144 145 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 146 /* 147 * Hack ahead. We can't have two devices with the same name and 148 * instance id. So I rename this to pass make check. 149 * Real help from people who knows the hardware is needed. 150 */ 151 .name = "icp/server", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .needed = pre_2_10_vmstate_dummy_icp_needed, 155 .fields = (const VMStateField[]) { 156 VMSTATE_UNUSED(4), /* uint32_t xirr */ 157 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 158 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 159 VMSTATE_END_OF_LIST() 160 }, 161 }; 162 163 /* 164 * See comment in hw/intc/xics.c:icp_realize() 165 * 166 * You have to remove vmstate_replace_hack_for_ppc() when you remove 167 * the machine types that need the following function. 168 */ 169 static void pre_2_10_vmstate_register_dummy_icp(int i) 170 { 171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 172 (void *)(uintptr_t) i); 173 } 174 175 /* 176 * See comment in hw/intc/xics.c:icp_realize() 177 * 178 * You have to remove vmstate_replace_hack_for_ppc() when you remove 179 * the machine types that need the following function. 180 */ 181 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 182 { 183 /* 184 * This used to be: 185 * 186 * vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 187 * (void *)(uintptr_t) i); 188 */ 189 } 190 191 int spapr_max_server_number(SpaprMachineState *spapr) 192 { 193 MachineState *ms = MACHINE(spapr); 194 195 assert(spapr->vsmt); 196 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 197 } 198 199 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 200 int smt_threads) 201 { 202 int i, ret = 0; 203 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 204 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 205 int index = spapr_get_vcpu_id(cpu); 206 207 if (cpu->compat_pvr) { 208 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 209 if (ret < 0) { 210 return ret; 211 } 212 } 213 214 /* Build interrupt servers and gservers properties */ 215 for (i = 0; i < smt_threads; i++) { 216 servers_prop[i] = cpu_to_be32(index + i); 217 /* Hack, direct the group queues back to cpu 0 */ 218 gservers_prop[i*2] = cpu_to_be32(index + i); 219 gservers_prop[i*2 + 1] = 0; 220 } 221 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 222 servers_prop, sizeof(*servers_prop) * smt_threads); 223 if (ret < 0) { 224 return ret; 225 } 226 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 227 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 228 229 return ret; 230 } 231 232 static void spapr_dt_pa_features(SpaprMachineState *spapr, 233 PowerPCCPU *cpu, 234 void *fdt, int offset) 235 { 236 /* 237 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 238 * but not MTTCG, so disable it. To advertise it, a cap would have 239 * to be added, or support implemented for MTTCG. 240 * 241 * Copy/paste is not supported by TCG, so it is not advertised. KVM 242 * can execute them but it has no accelerator drivers which are usable, 243 * so there isn't much need for it anyway. 244 */ 245 246 uint8_t pa_features_206[] = { 6, 0, 247 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 248 uint8_t pa_features_207[] = { 24, 0, 249 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 250 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 251 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 252 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 253 uint8_t pa_features_300[] = { 66, 0, 254 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 255 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 256 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 257 /* 6: DS207 */ 258 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 259 /* 16: Vector */ 260 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 261 /* 18: Vec. Scalar, 20: Vec. XOR */ 262 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 263 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 264 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 265 /* 32: LE atomic, 34: EBB + ext EBB */ 266 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 267 /* 40: Radix MMU */ 268 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 269 /* 42: PM, 44: PC RA, 46: SC vec'd */ 270 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 271 /* 48: SIMD, 50: QP BFP, 52: String */ 272 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 273 /* 54: DecFP, 56: DecI, 58: SHA */ 274 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 275 /* 60: NM atomic, 62: RNG */ 276 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 277 }; 278 /* 3.1 removes SAO, HTM support */ 279 uint8_t pa_features_31[] = { 74, 0, 280 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 281 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 282 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 283 /* 6: DS207 */ 284 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 285 /* 16: Vector */ 286 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 287 /* 18: Vec. Scalar, 20: Vec. XOR */ 288 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 289 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 291 /* 32: LE atomic, 34: EBB + ext EBB */ 292 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 293 /* 40: Radix MMU */ 294 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 295 /* 42: PM, 44: PC RA, 46: SC vec'd */ 296 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 297 /* 48: SIMD, 50: QP BFP, 52: String */ 298 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 299 /* 54: DecFP, 56: DecI, 58: SHA */ 300 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 301 /* 60: NM atomic, 62: RNG */ 302 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 303 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 304 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 305 /* 72: [P]HASHST/[P]HASHCHK */ 306 0x80, 0x00, /* 72 - 73 */ 307 }; 308 uint8_t *pa_features = NULL; 309 size_t pa_size; 310 311 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 312 pa_features = pa_features_206; 313 pa_size = sizeof(pa_features_206); 314 } 315 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 316 pa_features = pa_features_207; 317 pa_size = sizeof(pa_features_207); 318 } 319 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 320 pa_features = pa_features_300; 321 pa_size = sizeof(pa_features_300); 322 } 323 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) { 324 pa_features = pa_features_31; 325 pa_size = sizeof(pa_features_31); 326 } 327 if (!pa_features) { 328 return; 329 } 330 331 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 332 /* 333 * Note: we keep CI large pages off by default because a 64K capable 334 * guest provisioned with large pages might otherwise try to map a qemu 335 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 336 * even if that qemu runs on a 4k host. 337 * We dd this bit back here if we are confident this is not an issue 338 */ 339 pa_features[3] |= 0x20; 340 } 341 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 342 pa_features[24] |= 0x80; /* Transactional memory support */ 343 } 344 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 345 /* Workaround for broken kernels that attempt (guest) radix 346 * mode when they can't handle it, if they see the radix bit set 347 * in pa-features. So hide it from them. */ 348 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 349 } 350 351 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 352 } 353 354 static hwaddr spapr_node0_size(MachineState *machine) 355 { 356 if (machine->numa_state->num_nodes) { 357 int i; 358 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 359 if (machine->numa_state->nodes[i].node_mem) { 360 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 361 machine->ram_size); 362 } 363 } 364 } 365 return machine->ram_size; 366 } 367 368 static void add_str(GString *s, const gchar *s1) 369 { 370 g_string_append_len(s, s1, strlen(s1) + 1); 371 } 372 373 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 374 hwaddr start, hwaddr size) 375 { 376 char mem_name[32]; 377 uint64_t mem_reg_property[2]; 378 int off; 379 380 mem_reg_property[0] = cpu_to_be64(start); 381 mem_reg_property[1] = cpu_to_be64(size); 382 383 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 384 off = fdt_add_subnode(fdt, 0, mem_name); 385 _FDT(off); 386 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 387 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 388 sizeof(mem_reg_property)))); 389 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 390 return off; 391 } 392 393 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 394 { 395 MemoryDeviceInfoList *info; 396 397 for (info = list; info; info = info->next) { 398 MemoryDeviceInfo *value = info->value; 399 400 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 401 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 402 403 if (addr >= pcdimm_info->addr && 404 addr < (pcdimm_info->addr + pcdimm_info->size)) { 405 return pcdimm_info->node; 406 } 407 } 408 } 409 410 return -1; 411 } 412 413 struct sPAPRDrconfCellV2 { 414 uint32_t seq_lmbs; 415 uint64_t base_addr; 416 uint32_t drc_index; 417 uint32_t aa_index; 418 uint32_t flags; 419 } QEMU_PACKED; 420 421 typedef struct DrconfCellQueue { 422 struct sPAPRDrconfCellV2 cell; 423 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 424 } DrconfCellQueue; 425 426 static DrconfCellQueue * 427 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 428 uint32_t drc_index, uint32_t aa_index, 429 uint32_t flags) 430 { 431 DrconfCellQueue *elem; 432 433 elem = g_malloc0(sizeof(*elem)); 434 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 435 elem->cell.base_addr = cpu_to_be64(base_addr); 436 elem->cell.drc_index = cpu_to_be32(drc_index); 437 elem->cell.aa_index = cpu_to_be32(aa_index); 438 elem->cell.flags = cpu_to_be32(flags); 439 440 return elem; 441 } 442 443 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 444 int offset, MemoryDeviceInfoList *dimms) 445 { 446 MachineState *machine = MACHINE(spapr); 447 uint8_t *int_buf, *cur_index; 448 int ret; 449 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 450 uint64_t addr, cur_addr, size; 451 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 452 uint64_t mem_end = machine->device_memory->base + 453 memory_region_size(&machine->device_memory->mr); 454 uint32_t node, buf_len, nr_entries = 0; 455 SpaprDrc *drc; 456 DrconfCellQueue *elem, *next; 457 MemoryDeviceInfoList *info; 458 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 459 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 460 461 /* Entry to cover RAM and the gap area */ 462 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 463 SPAPR_LMB_FLAGS_RESERVED | 464 SPAPR_LMB_FLAGS_DRC_INVALID); 465 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 466 nr_entries++; 467 468 cur_addr = machine->device_memory->base; 469 for (info = dimms; info; info = info->next) { 470 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 471 472 addr = di->addr; 473 size = di->size; 474 node = di->node; 475 476 /* 477 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 478 * area is marked hotpluggable in the next iteration for the bigger 479 * chunk including the NVDIMM occupied area. 480 */ 481 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 482 continue; 483 484 /* Entry for hot-pluggable area */ 485 if (cur_addr < addr) { 486 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 487 g_assert(drc); 488 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 489 cur_addr, spapr_drc_index(drc), -1, 0); 490 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 491 nr_entries++; 492 } 493 494 /* Entry for DIMM */ 495 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 496 g_assert(drc); 497 elem = spapr_get_drconf_cell(size / lmb_size, addr, 498 spapr_drc_index(drc), node, 499 (SPAPR_LMB_FLAGS_ASSIGNED | 500 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 501 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 502 nr_entries++; 503 cur_addr = addr + size; 504 } 505 506 /* Entry for remaining hotpluggable area */ 507 if (cur_addr < mem_end) { 508 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 509 g_assert(drc); 510 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 511 cur_addr, spapr_drc_index(drc), -1, 0); 512 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 513 nr_entries++; 514 } 515 516 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 517 int_buf = cur_index = g_malloc0(buf_len); 518 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 519 cur_index += sizeof(nr_entries); 520 521 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 522 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 523 cur_index += sizeof(elem->cell); 524 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 525 g_free(elem); 526 } 527 528 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 529 g_free(int_buf); 530 if (ret < 0) { 531 return -1; 532 } 533 return 0; 534 } 535 536 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 537 int offset, MemoryDeviceInfoList *dimms) 538 { 539 MachineState *machine = MACHINE(spapr); 540 int i, ret; 541 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 542 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 543 uint32_t nr_lmbs = (machine->device_memory->base + 544 memory_region_size(&machine->device_memory->mr)) / 545 lmb_size; 546 uint32_t *int_buf, *cur_index, buf_len; 547 548 /* 549 * Allocate enough buffer size to fit in ibm,dynamic-memory 550 */ 551 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 552 cur_index = int_buf = g_malloc0(buf_len); 553 int_buf[0] = cpu_to_be32(nr_lmbs); 554 cur_index++; 555 for (i = 0; i < nr_lmbs; i++) { 556 uint64_t addr = i * lmb_size; 557 uint32_t *dynamic_memory = cur_index; 558 559 if (i >= device_lmb_start) { 560 SpaprDrc *drc; 561 562 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 563 g_assert(drc); 564 565 dynamic_memory[0] = cpu_to_be32(addr >> 32); 566 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 567 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 568 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 569 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 570 if (memory_region_present(get_system_memory(), addr)) { 571 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 572 } else { 573 dynamic_memory[5] = cpu_to_be32(0); 574 } 575 } else { 576 /* 577 * LMB information for RMA, boot time RAM and gap b/n RAM and 578 * device memory region -- all these are marked as reserved 579 * and as having no valid DRC. 580 */ 581 dynamic_memory[0] = cpu_to_be32(addr >> 32); 582 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 583 dynamic_memory[2] = cpu_to_be32(0); 584 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 585 dynamic_memory[4] = cpu_to_be32(-1); 586 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 587 SPAPR_LMB_FLAGS_DRC_INVALID); 588 } 589 590 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 591 } 592 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 593 g_free(int_buf); 594 if (ret < 0) { 595 return -1; 596 } 597 return 0; 598 } 599 600 /* 601 * Adds ibm,dynamic-reconfiguration-memory node. 602 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 603 * of this device tree node. 604 */ 605 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 606 void *fdt) 607 { 608 MachineState *machine = MACHINE(spapr); 609 int ret, offset; 610 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 611 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 612 cpu_to_be32(lmb_size & 0xffffffff)}; 613 MemoryDeviceInfoList *dimms = NULL; 614 615 /* Don't create the node if there is no device memory. */ 616 if (!machine->device_memory) { 617 return 0; 618 } 619 620 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 621 622 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 623 sizeof(prop_lmb_size)); 624 if (ret < 0) { 625 return ret; 626 } 627 628 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 629 if (ret < 0) { 630 return ret; 631 } 632 633 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 634 if (ret < 0) { 635 return ret; 636 } 637 638 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 639 dimms = qmp_memory_device_list(); 640 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 641 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 642 } else { 643 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 644 } 645 qapi_free_MemoryDeviceInfoList(dimms); 646 647 if (ret < 0) { 648 return ret; 649 } 650 651 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 652 653 return ret; 654 } 655 656 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 657 { 658 MachineState *machine = MACHINE(spapr); 659 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 660 hwaddr mem_start, node_size; 661 int i, nb_nodes = machine->numa_state->num_nodes; 662 NodeInfo *nodes = machine->numa_state->nodes; 663 664 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 665 if (!nodes[i].node_mem) { 666 continue; 667 } 668 if (mem_start >= machine->ram_size) { 669 node_size = 0; 670 } else { 671 node_size = nodes[i].node_mem; 672 if (node_size > machine->ram_size - mem_start) { 673 node_size = machine->ram_size - mem_start; 674 } 675 } 676 if (!mem_start) { 677 /* spapr_machine_init() checks for rma_size <= node0_size 678 * already */ 679 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 680 mem_start += spapr->rma_size; 681 node_size -= spapr->rma_size; 682 } 683 for ( ; node_size; ) { 684 hwaddr sizetmp = pow2floor(node_size); 685 686 /* mem_start != 0 here */ 687 if (ctzl(mem_start) < ctzl(sizetmp)) { 688 sizetmp = 1ULL << ctzl(mem_start); 689 } 690 691 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 692 node_size -= sizetmp; 693 mem_start += sizetmp; 694 } 695 } 696 697 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 698 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 699 int ret; 700 701 g_assert(smc->dr_lmb_enabled); 702 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 703 if (ret) { 704 return ret; 705 } 706 } 707 708 return 0; 709 } 710 711 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 712 SpaprMachineState *spapr) 713 { 714 MachineState *ms = MACHINE(spapr); 715 PowerPCCPU *cpu = POWERPC_CPU(cs); 716 CPUPPCState *env = &cpu->env; 717 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 718 int index = spapr_get_vcpu_id(cpu); 719 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 720 0xffffffff, 0xffffffff}; 721 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 722 : SPAPR_TIMEBASE_FREQ; 723 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 724 uint32_t page_sizes_prop[64]; 725 size_t page_sizes_prop_size; 726 unsigned int smp_threads = ms->smp.threads; 727 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 728 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 729 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 730 SpaprDrc *drc; 731 int drc_index; 732 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 733 int i; 734 735 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 736 if (drc) { 737 drc_index = spapr_drc_index(drc); 738 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 739 } 740 741 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 742 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 743 744 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 745 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 746 env->dcache_line_size))); 747 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 748 env->dcache_line_size))); 749 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 750 env->icache_line_size))); 751 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 752 env->icache_line_size))); 753 754 if (pcc->l1_dcache_size) { 755 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 756 pcc->l1_dcache_size))); 757 } else { 758 warn_report("Unknown L1 dcache size for cpu"); 759 } 760 if (pcc->l1_icache_size) { 761 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 762 pcc->l1_icache_size))); 763 } else { 764 warn_report("Unknown L1 icache size for cpu"); 765 } 766 767 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 768 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 769 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 770 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 771 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 772 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 773 774 if (ppc_has_spr(cpu, SPR_PURR)) { 775 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 776 } 777 if (ppc_has_spr(cpu, SPR_PURR)) { 778 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 779 } 780 781 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 782 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 783 segs, sizeof(segs)))); 784 } 785 786 /* Advertise VSX (vector extensions) if available 787 * 1 == VMX / Altivec available 788 * 2 == VSX available 789 * 790 * Only CPUs for which we create core types in spapr_cpu_core.c 791 * are possible, and all of those have VMX */ 792 if (env->insns_flags & PPC_ALTIVEC) { 793 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 794 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 795 } else { 796 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 797 } 798 } 799 800 /* Advertise DFP (Decimal Floating Point) if available 801 * 0 / no property == no DFP 802 * 1 == DFP available */ 803 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 804 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 805 } 806 807 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 808 sizeof(page_sizes_prop)); 809 if (page_sizes_prop_size) { 810 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 811 page_sizes_prop, page_sizes_prop_size))); 812 } 813 814 spapr_dt_pa_features(spapr, cpu, fdt, offset); 815 816 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 817 cs->cpu_index / vcpus_per_socket))); 818 819 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 820 pft_size_prop, sizeof(pft_size_prop)))); 821 822 if (ms->numa_state->num_nodes > 1) { 823 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 824 } 825 826 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 827 828 if (pcc->radix_page_info) { 829 for (i = 0; i < pcc->radix_page_info->count; i++) { 830 radix_AP_encodings[i] = 831 cpu_to_be32(pcc->radix_page_info->entries[i]); 832 } 833 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 834 radix_AP_encodings, 835 pcc->radix_page_info->count * 836 sizeof(radix_AP_encodings[0])))); 837 } 838 839 /* 840 * We set this property to let the guest know that it can use the large 841 * decrementer and its width in bits. 842 */ 843 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 844 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 845 pcc->lrg_decr_bits))); 846 } 847 848 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 849 int cpus_offset) 850 { 851 PowerPCCPU *cpu = POWERPC_CPU(cs); 852 int index = spapr_get_vcpu_id(cpu); 853 DeviceClass *dc = DEVICE_GET_CLASS(cs); 854 g_autofree char *nodename = NULL; 855 int offset; 856 857 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 858 return; 859 } 860 861 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 862 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 863 _FDT(offset); 864 spapr_dt_cpu(cs, fdt, offset, spapr); 865 } 866 867 868 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 869 { 870 CPUState **rev; 871 CPUState *cs; 872 int n_cpus; 873 int cpus_offset; 874 int i; 875 876 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 877 _FDT(cpus_offset); 878 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 879 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 880 881 /* 882 * We walk the CPUs in reverse order to ensure that CPU DT nodes 883 * created by fdt_add_subnode() end up in the right order in FDT 884 * for the guest kernel the enumerate the CPUs correctly. 885 * 886 * The CPU list cannot be traversed in reverse order, so we need 887 * to do extra work. 888 */ 889 n_cpus = 0; 890 rev = NULL; 891 CPU_FOREACH(cs) { 892 rev = g_renew(CPUState *, rev, n_cpus + 1); 893 rev[n_cpus++] = cs; 894 } 895 896 for (i = n_cpus - 1; i >= 0; i--) { 897 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 898 } 899 900 g_free(rev); 901 } 902 903 static int spapr_dt_rng(void *fdt) 904 { 905 int node; 906 int ret; 907 908 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 909 if (node <= 0) { 910 return -1; 911 } 912 ret = fdt_setprop_string(fdt, node, "device_type", 913 "ibm,platform-facilities"); 914 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 915 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 916 917 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 918 if (node <= 0) { 919 return -1; 920 } 921 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 922 923 return ret ? -1 : 0; 924 } 925 926 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 927 { 928 MachineState *ms = MACHINE(spapr); 929 int rtas; 930 GString *hypertas = g_string_sized_new(256); 931 GString *qemu_hypertas = g_string_sized_new(256); 932 uint32_t lrdr_capacity[] = { 933 0, 934 0, 935 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 936 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 937 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 938 }; 939 940 /* Do we have device memory? */ 941 if (MACHINE(spapr)->device_memory) { 942 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 943 memory_region_size(&MACHINE(spapr)->device_memory->mr); 944 945 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 946 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 947 } 948 949 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 950 951 /* hypertas */ 952 add_str(hypertas, "hcall-pft"); 953 add_str(hypertas, "hcall-term"); 954 add_str(hypertas, "hcall-dabr"); 955 add_str(hypertas, "hcall-interrupt"); 956 add_str(hypertas, "hcall-tce"); 957 add_str(hypertas, "hcall-vio"); 958 add_str(hypertas, "hcall-splpar"); 959 add_str(hypertas, "hcall-join"); 960 add_str(hypertas, "hcall-bulk"); 961 add_str(hypertas, "hcall-set-mode"); 962 add_str(hypertas, "hcall-sprg0"); 963 add_str(hypertas, "hcall-copy"); 964 add_str(hypertas, "hcall-debug"); 965 add_str(hypertas, "hcall-vphn"); 966 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 967 add_str(hypertas, "hcall-rpt-invalidate"); 968 } 969 970 add_str(qemu_hypertas, "hcall-memop1"); 971 972 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 973 add_str(hypertas, "hcall-multi-tce"); 974 } 975 976 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 977 add_str(hypertas, "hcall-hpt-resize"); 978 } 979 980 add_str(hypertas, "hcall-watchdog"); 981 982 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 983 hypertas->str, hypertas->len)); 984 g_string_free(hypertas, TRUE); 985 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 986 qemu_hypertas->str, qemu_hypertas->len)); 987 g_string_free(qemu_hypertas, TRUE); 988 989 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 990 991 /* 992 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 993 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 994 * 995 * The system reset requirements are driven by existing Linux and PowerVM 996 * implementation which (contrary to PAPR) saves r3 in the error log 997 * structure like machine check, so Linux expects to find the saved r3 998 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 999 * does not look at the error value). 1000 * 1001 * System reset interrupts are not subject to interlock like machine 1002 * check, so this memory area could be corrupted if the sreset is 1003 * interrupted by a machine check (or vice versa) if it was shared. To 1004 * prevent this, system reset uses per-CPU areas for the sreset save 1005 * area. A system reset that interrupts a system reset handler could 1006 * still overwrite this area, but Linux doesn't try to recover in that 1007 * case anyway. 1008 * 1009 * The extra 8 bytes is required because Linux's FWNMI error log check 1010 * is off-by-one. 1011 * 1012 * RTAS_MIN_SIZE is required for the RTAS blob itself. 1013 */ 1014 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 1015 RTAS_ERROR_LOG_MAX + 1016 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 1017 sizeof(uint64_t))); 1018 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1019 RTAS_ERROR_LOG_MAX)); 1020 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1021 RTAS_EVENT_SCAN_RATE)); 1022 1023 g_assert(msi_nonbroken); 1024 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1025 1026 /* 1027 * According to PAPR, rtas ibm,os-term does not guarantee a return 1028 * back to the guest cpu. 1029 * 1030 * While an additional ibm,extended-os-term property indicates 1031 * that rtas call return will always occur. Set this property. 1032 */ 1033 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1034 1035 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1036 lrdr_capacity, sizeof(lrdr_capacity))); 1037 1038 spapr_dt_rtas_tokens(fdt, rtas); 1039 } 1040 1041 /* 1042 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1043 * and the XIVE features that the guest may request and thus the valid 1044 * values for bytes 23..26 of option vector 5: 1045 */ 1046 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1047 int chosen) 1048 { 1049 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1050 1051 char val[2 * 4] = { 1052 23, 0x00, /* XICS / XIVE mode */ 1053 24, 0x00, /* Hash/Radix, filled in below. */ 1054 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1055 26, 0x40, /* Radix options: GTSE == yes. */ 1056 }; 1057 1058 if (spapr->irq->xics && spapr->irq->xive) { 1059 val[1] = SPAPR_OV5_XIVE_BOTH; 1060 } else if (spapr->irq->xive) { 1061 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1062 } else { 1063 assert(spapr->irq->xics); 1064 val[1] = SPAPR_OV5_XIVE_LEGACY; 1065 } 1066 1067 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1068 first_ppc_cpu->compat_pvr)) { 1069 /* 1070 * If we're in a pre POWER9 compat mode then the guest should 1071 * do hash and use the legacy interrupt mode 1072 */ 1073 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1074 val[3] = 0x00; /* Hash */ 1075 spapr_check_mmu_mode(false); 1076 } else if (kvm_enabled()) { 1077 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1078 val[3] = 0x80; /* OV5_MMU_BOTH */ 1079 } else if (kvmppc_has_cap_mmu_radix()) { 1080 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1081 } else { 1082 val[3] = 0x00; /* Hash */ 1083 } 1084 } else { 1085 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1086 val[3] = 0xC0; 1087 } 1088 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1089 val, sizeof(val))); 1090 } 1091 1092 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1093 { 1094 MachineState *machine = MACHINE(spapr); 1095 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1096 int chosen; 1097 1098 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1099 1100 if (reset) { 1101 const char *boot_device = spapr->boot_device; 1102 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1103 size_t cb = 0; 1104 g_autofree char *bootlist = get_boot_devices_list(&cb); 1105 1106 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1107 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1108 machine->kernel_cmdline)); 1109 } 1110 1111 if (spapr->initrd_size) { 1112 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1113 spapr->initrd_base)); 1114 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1115 spapr->initrd_base + spapr->initrd_size)); 1116 } 1117 1118 if (spapr->kernel_size) { 1119 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1120 cpu_to_be64(spapr->kernel_size) }; 1121 1122 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1123 &kprop, sizeof(kprop))); 1124 if (spapr->kernel_le) { 1125 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1126 } 1127 } 1128 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1129 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1130 } 1131 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1132 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1133 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1134 1135 if (cb && bootlist) { 1136 int i; 1137 1138 for (i = 0; i < cb; i++) { 1139 if (bootlist[i] == '\n') { 1140 bootlist[i] = ' '; 1141 } 1142 } 1143 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1144 } 1145 1146 if (boot_device && strlen(boot_device)) { 1147 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1148 } 1149 1150 if (spapr->want_stdout_path && stdout_path) { 1151 /* 1152 * "linux,stdout-path" and "stdout" properties are 1153 * deprecated by linux kernel. New platforms should only 1154 * use the "stdout-path" property. Set the new property 1155 * and continue using older property to remain compatible 1156 * with the existing firmware. 1157 */ 1158 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1159 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1160 } 1161 1162 /* 1163 * We can deal with BAR reallocation just fine, advertise it 1164 * to the guest 1165 */ 1166 if (smc->linux_pci_probe) { 1167 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1168 } 1169 1170 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1171 } 1172 1173 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1174 1175 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1176 } 1177 1178 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1179 { 1180 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1181 * KVM to work under pHyp with some guest co-operation */ 1182 int hypervisor; 1183 uint8_t hypercall[16]; 1184 1185 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1186 /* indicate KVM hypercall interface */ 1187 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1188 if (kvmppc_has_cap_fixup_hcalls()) { 1189 /* 1190 * Older KVM versions with older guest kernels were broken 1191 * with the magic page, don't allow the guest to map it. 1192 */ 1193 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1194 sizeof(hypercall))) { 1195 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1196 hypercall, sizeof(hypercall))); 1197 } 1198 } 1199 } 1200 1201 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1202 { 1203 MachineState *machine = MACHINE(spapr); 1204 MachineClass *mc = MACHINE_GET_CLASS(machine); 1205 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1206 uint32_t root_drc_type_mask = 0; 1207 int ret; 1208 void *fdt; 1209 SpaprPhbState *phb; 1210 char *buf; 1211 1212 fdt = g_malloc0(space); 1213 _FDT((fdt_create_empty_tree(fdt, space))); 1214 1215 /* Root node */ 1216 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1217 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1218 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1219 1220 /* Guest UUID & Name*/ 1221 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1222 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1223 if (qemu_uuid_set) { 1224 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1225 } 1226 g_free(buf); 1227 1228 if (qemu_get_vm_name()) { 1229 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1230 qemu_get_vm_name())); 1231 } 1232 1233 /* Host Model & Serial Number */ 1234 if (spapr->host_model) { 1235 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1236 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1237 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1238 g_free(buf); 1239 } 1240 1241 if (spapr->host_serial) { 1242 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1243 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1244 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1245 g_free(buf); 1246 } 1247 1248 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1249 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1250 1251 /* /interrupt controller */ 1252 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1253 1254 ret = spapr_dt_memory(spapr, fdt); 1255 if (ret < 0) { 1256 error_report("couldn't setup memory nodes in fdt"); 1257 exit(1); 1258 } 1259 1260 /* /vdevice */ 1261 spapr_dt_vdevice(spapr->vio_bus, fdt); 1262 1263 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1264 ret = spapr_dt_rng(fdt); 1265 if (ret < 0) { 1266 error_report("could not set up rng device in the fdt"); 1267 exit(1); 1268 } 1269 } 1270 1271 QLIST_FOREACH(phb, &spapr->phbs, list) { 1272 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1273 if (ret < 0) { 1274 error_report("couldn't setup PCI devices in fdt"); 1275 exit(1); 1276 } 1277 } 1278 1279 spapr_dt_cpus(fdt, spapr); 1280 1281 /* ibm,drc-indexes and friends */ 1282 if (smc->dr_lmb_enabled) { 1283 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1284 } 1285 if (smc->dr_phb_enabled) { 1286 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1287 } 1288 if (mc->nvdimm_supported) { 1289 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1290 } 1291 if (root_drc_type_mask) { 1292 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1293 } 1294 1295 if (mc->has_hotpluggable_cpus) { 1296 int offset = fdt_path_offset(fdt, "/cpus"); 1297 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1298 if (ret < 0) { 1299 error_report("Couldn't set up CPU DR device tree properties"); 1300 exit(1); 1301 } 1302 } 1303 1304 /* /event-sources */ 1305 spapr_dt_events(spapr, fdt); 1306 1307 /* /rtas */ 1308 spapr_dt_rtas(spapr, fdt); 1309 1310 /* /chosen */ 1311 spapr_dt_chosen(spapr, fdt, reset); 1312 1313 /* /hypervisor */ 1314 if (kvm_enabled()) { 1315 spapr_dt_hypervisor(spapr, fdt); 1316 } 1317 1318 /* Build memory reserve map */ 1319 if (reset) { 1320 if (spapr->kernel_size) { 1321 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1322 spapr->kernel_size))); 1323 } 1324 if (spapr->initrd_size) { 1325 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1326 spapr->initrd_size))); 1327 } 1328 } 1329 1330 /* NVDIMM devices */ 1331 if (mc->nvdimm_supported) { 1332 spapr_dt_persistent_memory(spapr, fdt); 1333 } 1334 1335 return fdt; 1336 } 1337 1338 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1339 { 1340 SpaprMachineState *spapr = opaque; 1341 1342 return (addr & 0x0fffffff) + spapr->kernel_addr; 1343 } 1344 1345 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1346 PowerPCCPU *cpu) 1347 { 1348 CPUPPCState *env = &cpu->env; 1349 1350 /* The TCG path should also be holding the BQL at this point */ 1351 g_assert(bql_locked()); 1352 1353 g_assert(!vhyp_cpu_in_nested(cpu)); 1354 1355 if (FIELD_EX64(env->msr, MSR, PR)) { 1356 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1357 env->gpr[3] = H_PRIVILEGE; 1358 } else { 1359 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1360 } 1361 } 1362 1363 struct LPCRSyncState { 1364 target_ulong value; 1365 target_ulong mask; 1366 }; 1367 1368 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1369 { 1370 struct LPCRSyncState *s = arg.host_ptr; 1371 PowerPCCPU *cpu = POWERPC_CPU(cs); 1372 CPUPPCState *env = &cpu->env; 1373 target_ulong lpcr; 1374 1375 cpu_synchronize_state(cs); 1376 lpcr = env->spr[SPR_LPCR]; 1377 lpcr &= ~s->mask; 1378 lpcr |= s->value; 1379 ppc_store_lpcr(cpu, lpcr); 1380 } 1381 1382 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1383 { 1384 CPUState *cs; 1385 struct LPCRSyncState s = { 1386 .value = value, 1387 .mask = mask 1388 }; 1389 CPU_FOREACH(cs) { 1390 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1391 } 1392 } 1393 1394 /* May be used when the machine is not running */ 1395 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1396 { 1397 CPUState *cs; 1398 CPU_FOREACH(cs) { 1399 PowerPCCPU *cpu = POWERPC_CPU(cs); 1400 CPUPPCState *env = &cpu->env; 1401 target_ulong lpcr; 1402 1403 lpcr = env->spr[SPR_LPCR]; 1404 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1405 ppc_store_lpcr(cpu, lpcr); 1406 } 1407 } 1408 1409 1410 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1411 target_ulong lpid, ppc_v3_pate_t *entry) 1412 { 1413 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1414 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1415 1416 if (!spapr_cpu->in_nested) { 1417 assert(lpid == 0); 1418 1419 /* Copy PATE1:GR into PATE0:HR */ 1420 entry->dw0 = spapr->patb_entry & PATE0_HR; 1421 entry->dw1 = spapr->patb_entry; 1422 1423 } else { 1424 uint64_t patb, pats; 1425 1426 assert(lpid != 0); 1427 1428 patb = spapr->nested_ptcr & PTCR_PATB; 1429 pats = spapr->nested_ptcr & PTCR_PATS; 1430 1431 /* Check if partition table is properly aligned */ 1432 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 1433 return false; 1434 } 1435 1436 /* Calculate number of entries */ 1437 pats = 1ull << (pats + 12 - 4); 1438 if (pats <= lpid) { 1439 return false; 1440 } 1441 1442 /* Grab entry */ 1443 patb += 16 * lpid; 1444 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1445 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1446 } 1447 1448 return true; 1449 } 1450 1451 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1452 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1453 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1454 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1455 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1456 1457 /* 1458 * Get the fd to access the kernel htab, re-opening it if necessary 1459 */ 1460 static int get_htab_fd(SpaprMachineState *spapr) 1461 { 1462 Error *local_err = NULL; 1463 1464 if (spapr->htab_fd >= 0) { 1465 return spapr->htab_fd; 1466 } 1467 1468 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1469 if (spapr->htab_fd < 0) { 1470 error_report_err(local_err); 1471 } 1472 1473 return spapr->htab_fd; 1474 } 1475 1476 void close_htab_fd(SpaprMachineState *spapr) 1477 { 1478 if (spapr->htab_fd >= 0) { 1479 close(spapr->htab_fd); 1480 } 1481 spapr->htab_fd = -1; 1482 } 1483 1484 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1485 { 1486 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1487 1488 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1489 } 1490 1491 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1492 { 1493 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1494 1495 assert(kvm_enabled()); 1496 1497 if (!spapr->htab) { 1498 return 0; 1499 } 1500 1501 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1502 } 1503 1504 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1505 hwaddr ptex, int n) 1506 { 1507 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1508 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1509 1510 if (!spapr->htab) { 1511 /* 1512 * HTAB is controlled by KVM. Fetch into temporary buffer 1513 */ 1514 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1515 kvmppc_read_hptes(hptes, ptex, n); 1516 return hptes; 1517 } 1518 1519 /* 1520 * HTAB is controlled by QEMU. Just point to the internally 1521 * accessible PTEG. 1522 */ 1523 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1524 } 1525 1526 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1527 const ppc_hash_pte64_t *hptes, 1528 hwaddr ptex, int n) 1529 { 1530 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1531 1532 if (!spapr->htab) { 1533 g_free((void *)hptes); 1534 } 1535 1536 /* Nothing to do for qemu managed HPT */ 1537 } 1538 1539 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1540 uint64_t pte0, uint64_t pte1) 1541 { 1542 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1543 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1544 1545 if (!spapr->htab) { 1546 kvmppc_write_hpte(ptex, pte0, pte1); 1547 } else { 1548 if (pte0 & HPTE64_V_VALID) { 1549 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1550 /* 1551 * When setting valid, we write PTE1 first. This ensures 1552 * proper synchronization with the reading code in 1553 * ppc_hash64_pteg_search() 1554 */ 1555 smp_wmb(); 1556 stq_p(spapr->htab + offset, pte0); 1557 } else { 1558 stq_p(spapr->htab + offset, pte0); 1559 /* 1560 * When clearing it we set PTE0 first. This ensures proper 1561 * synchronization with the reading code in 1562 * ppc_hash64_pteg_search() 1563 */ 1564 smp_wmb(); 1565 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1566 } 1567 } 1568 } 1569 1570 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1571 uint64_t pte1) 1572 { 1573 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1574 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1575 1576 if (!spapr->htab) { 1577 /* There should always be a hash table when this is called */ 1578 error_report("spapr_hpte_set_c called with no hash table !"); 1579 return; 1580 } 1581 1582 /* The HW performs a non-atomic byte update */ 1583 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1584 } 1585 1586 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1587 uint64_t pte1) 1588 { 1589 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1590 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1591 1592 if (!spapr->htab) { 1593 /* There should always be a hash table when this is called */ 1594 error_report("spapr_hpte_set_r called with no hash table !"); 1595 return; 1596 } 1597 1598 /* The HW performs a non-atomic byte update */ 1599 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1600 } 1601 1602 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1603 { 1604 int shift; 1605 1606 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1607 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1608 * that's much more than is needed for Linux guests */ 1609 shift = ctz64(pow2ceil(ramsize)) - 7; 1610 shift = MAX(shift, 18); /* Minimum architected size */ 1611 shift = MIN(shift, 46); /* Maximum architected size */ 1612 return shift; 1613 } 1614 1615 void spapr_free_hpt(SpaprMachineState *spapr) 1616 { 1617 qemu_vfree(spapr->htab); 1618 spapr->htab = NULL; 1619 spapr->htab_shift = 0; 1620 close_htab_fd(spapr); 1621 } 1622 1623 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1624 { 1625 ERRP_GUARD(); 1626 long rc; 1627 1628 /* Clean up any HPT info from a previous boot */ 1629 spapr_free_hpt(spapr); 1630 1631 rc = kvmppc_reset_htab(shift); 1632 1633 if (rc == -EOPNOTSUPP) { 1634 error_setg(errp, "HPT not supported in nested guests"); 1635 return -EOPNOTSUPP; 1636 } 1637 1638 if (rc < 0) { 1639 /* kernel-side HPT needed, but couldn't allocate one */ 1640 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1641 shift); 1642 error_append_hint(errp, "Try smaller maxmem?\n"); 1643 return -errno; 1644 } else if (rc > 0) { 1645 /* kernel-side HPT allocated */ 1646 if (rc != shift) { 1647 error_setg(errp, 1648 "Requested order %d HPT, but kernel allocated order %ld", 1649 shift, rc); 1650 error_append_hint(errp, "Try smaller maxmem?\n"); 1651 return -ENOSPC; 1652 } 1653 1654 spapr->htab_shift = shift; 1655 spapr->htab = NULL; 1656 } else { 1657 /* kernel-side HPT not needed, allocate in userspace instead */ 1658 size_t size = 1ULL << shift; 1659 int i; 1660 1661 spapr->htab = qemu_memalign(size, size); 1662 memset(spapr->htab, 0, size); 1663 spapr->htab_shift = shift; 1664 1665 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1666 DIRTY_HPTE(HPTE(spapr->htab, i)); 1667 } 1668 } 1669 /* We're setting up a hash table, so that means we're not radix */ 1670 spapr->patb_entry = 0; 1671 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1672 return 0; 1673 } 1674 1675 void spapr_setup_hpt(SpaprMachineState *spapr) 1676 { 1677 int hpt_shift; 1678 1679 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1680 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1681 } else { 1682 uint64_t current_ram_size; 1683 1684 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1685 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1686 } 1687 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1688 1689 if (kvm_enabled()) { 1690 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1691 1692 /* Check our RMA fits in the possible VRMA */ 1693 if (vrma_limit < spapr->rma_size) { 1694 error_report("Unable to create %" HWADDR_PRIu 1695 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1696 spapr->rma_size / MiB, vrma_limit / MiB); 1697 exit(EXIT_FAILURE); 1698 } 1699 } 1700 } 1701 1702 void spapr_check_mmu_mode(bool guest_radix) 1703 { 1704 if (guest_radix) { 1705 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1706 error_report("Guest requested unavailable MMU mode (radix)."); 1707 exit(EXIT_FAILURE); 1708 } 1709 } else { 1710 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1711 && !kvmppc_has_cap_mmu_hash_v3()) { 1712 error_report("Guest requested unavailable MMU mode (hash)."); 1713 exit(EXIT_FAILURE); 1714 } 1715 } 1716 } 1717 1718 static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) 1719 { 1720 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1721 PowerPCCPU *first_ppc_cpu; 1722 hwaddr fdt_addr; 1723 void *fdt; 1724 int rc; 1725 1726 if (reason != SHUTDOWN_CAUSE_SNAPSHOT_LOAD) { 1727 /* 1728 * Record-replay snapshot load must not consume random, this was 1729 * already replayed from initial machine reset. 1730 */ 1731 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1732 } 1733 1734 pef_kvm_reset(machine->cgs, &error_fatal); 1735 spapr_caps_apply(spapr); 1736 1737 first_ppc_cpu = POWERPC_CPU(first_cpu); 1738 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1739 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1740 spapr->max_compat_pvr)) { 1741 /* 1742 * If using KVM with radix mode available, VCPUs can be started 1743 * without a HPT because KVM will start them in radix mode. 1744 * Set the GR bit in PATE so that we know there is no HPT. 1745 */ 1746 spapr->patb_entry = PATE1_GR; 1747 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1748 } else { 1749 spapr_setup_hpt(spapr); 1750 } 1751 1752 qemu_devices_reset(reason); 1753 1754 spapr_ovec_cleanup(spapr->ov5_cas); 1755 spapr->ov5_cas = spapr_ovec_new(); 1756 1757 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1758 1759 /* 1760 * This is fixing some of the default configuration of the XIVE 1761 * devices. To be called after the reset of the machine devices. 1762 */ 1763 spapr_irq_reset(spapr, &error_fatal); 1764 1765 /* 1766 * There is no CAS under qtest. Simulate one to please the code that 1767 * depends on spapr->ov5_cas. This is especially needed to test device 1768 * unplug, so we do that before resetting the DRCs. 1769 */ 1770 if (qtest_enabled()) { 1771 spapr_ovec_cleanup(spapr->ov5_cas); 1772 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1773 } 1774 1775 spapr_nvdimm_finish_flushes(); 1776 1777 /* DRC reset may cause a device to be unplugged. This will cause troubles 1778 * if this device is used by another device (eg, a running vhost backend 1779 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1780 * situations, we reset DRCs after all devices have been reset. 1781 */ 1782 spapr_drc_reset_all(spapr); 1783 1784 spapr_clear_pending_events(spapr); 1785 1786 /* 1787 * We place the device tree just below either the top of the RMA, 1788 * or just below 2GB, whichever is lower, so that it can be 1789 * processed with 32-bit real mode code if necessary 1790 */ 1791 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1792 1793 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1794 if (spapr->vof) { 1795 spapr_vof_reset(spapr, fdt, &error_fatal); 1796 /* 1797 * Do not pack the FDT as the client may change properties. 1798 * VOF client does not expect the FDT so we do not load it to the VM. 1799 */ 1800 } else { 1801 rc = fdt_pack(fdt); 1802 /* Should only fail if we've built a corrupted tree */ 1803 assert(rc == 0); 1804 1805 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1806 0, fdt_addr, 0); 1807 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1808 } 1809 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1810 1811 g_free(spapr->fdt_blob); 1812 spapr->fdt_size = fdt_totalsize(fdt); 1813 spapr->fdt_initial_size = spapr->fdt_size; 1814 spapr->fdt_blob = fdt; 1815 1816 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1817 machine->fdt = fdt; 1818 1819 /* Set up the entry state */ 1820 first_ppc_cpu->env.gpr[5] = 0; 1821 1822 spapr->fwnmi_system_reset_addr = -1; 1823 spapr->fwnmi_machine_check_addr = -1; 1824 spapr->fwnmi_machine_check_interlock = -1; 1825 1826 /* Signal all vCPUs waiting on this condition */ 1827 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1828 1829 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1830 } 1831 1832 static void spapr_create_nvram(SpaprMachineState *spapr) 1833 { 1834 DeviceState *dev = qdev_new("spapr-nvram"); 1835 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1836 1837 if (dinfo) { 1838 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1839 &error_fatal); 1840 } 1841 1842 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1843 1844 spapr->nvram = (struct SpaprNvram *)dev; 1845 } 1846 1847 static void spapr_rtc_create(SpaprMachineState *spapr) 1848 { 1849 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1850 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1851 &error_fatal, NULL); 1852 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1853 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1854 "date"); 1855 } 1856 1857 /* Returns whether we want to use VGA or not */ 1858 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1859 { 1860 vga_interface_created = true; 1861 switch (vga_interface_type) { 1862 case VGA_NONE: 1863 return false; 1864 case VGA_DEVICE: 1865 return true; 1866 case VGA_STD: 1867 case VGA_VIRTIO: 1868 case VGA_CIRRUS: 1869 return pci_vga_init(pci_bus) != NULL; 1870 default: 1871 error_setg(errp, 1872 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1873 return false; 1874 } 1875 } 1876 1877 static int spapr_pre_load(void *opaque) 1878 { 1879 int rc; 1880 1881 rc = spapr_caps_pre_load(opaque); 1882 if (rc) { 1883 return rc; 1884 } 1885 1886 return 0; 1887 } 1888 1889 static int spapr_post_load(void *opaque, int version_id) 1890 { 1891 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1892 int err = 0; 1893 1894 err = spapr_caps_post_migration(spapr); 1895 if (err) { 1896 return err; 1897 } 1898 1899 /* 1900 * In earlier versions, there was no separate qdev for the PAPR 1901 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1902 * So when migrating from those versions, poke the incoming offset 1903 * value into the RTC device 1904 */ 1905 if (version_id < 3) { 1906 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1907 if (err) { 1908 return err; 1909 } 1910 } 1911 1912 if (kvm_enabled() && spapr->patb_entry) { 1913 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1914 bool radix = !!(spapr->patb_entry & PATE1_GR); 1915 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1916 1917 /* 1918 * Update LPCR:HR and UPRT as they may not be set properly in 1919 * the stream 1920 */ 1921 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1922 LPCR_HR | LPCR_UPRT); 1923 1924 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1925 if (err) { 1926 error_report("Process table config unsupported by the host"); 1927 return -EINVAL; 1928 } 1929 } 1930 1931 err = spapr_irq_post_load(spapr, version_id); 1932 if (err) { 1933 return err; 1934 } 1935 1936 return err; 1937 } 1938 1939 static int spapr_pre_save(void *opaque) 1940 { 1941 int rc; 1942 1943 rc = spapr_caps_pre_save(opaque); 1944 if (rc) { 1945 return rc; 1946 } 1947 1948 return 0; 1949 } 1950 1951 static bool version_before_3(void *opaque, int version_id) 1952 { 1953 return version_id < 3; 1954 } 1955 1956 static bool spapr_pending_events_needed(void *opaque) 1957 { 1958 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1959 return !QTAILQ_EMPTY(&spapr->pending_events); 1960 } 1961 1962 static const VMStateDescription vmstate_spapr_event_entry = { 1963 .name = "spapr_event_log_entry", 1964 .version_id = 1, 1965 .minimum_version_id = 1, 1966 .fields = (const VMStateField[]) { 1967 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1968 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1969 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1970 NULL, extended_length), 1971 VMSTATE_END_OF_LIST() 1972 }, 1973 }; 1974 1975 static const VMStateDescription vmstate_spapr_pending_events = { 1976 .name = "spapr_pending_events", 1977 .version_id = 1, 1978 .minimum_version_id = 1, 1979 .needed = spapr_pending_events_needed, 1980 .fields = (const VMStateField[]) { 1981 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1982 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1983 VMSTATE_END_OF_LIST() 1984 }, 1985 }; 1986 1987 static bool spapr_ov5_cas_needed(void *opaque) 1988 { 1989 SpaprMachineState *spapr = opaque; 1990 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1991 bool cas_needed; 1992 1993 /* Prior to the introduction of SpaprOptionVector, we had two option 1994 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1995 * Both of these options encode machine topology into the device-tree 1996 * in such a way that the now-booted OS should still be able to interact 1997 * appropriately with QEMU regardless of what options were actually 1998 * negotiatied on the source side. 1999 * 2000 * As such, we can avoid migrating the CAS-negotiated options if these 2001 * are the only options available on the current machine/platform. 2002 * Since these are the only options available for pseries-2.7 and 2003 * earlier, this allows us to maintain old->new/new->old migration 2004 * compatibility. 2005 * 2006 * For QEMU 2.8+, there are additional CAS-negotiatable options available 2007 * via default pseries-2.8 machines and explicit command-line parameters. 2008 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 2009 * of the actual CAS-negotiated values to continue working properly. For 2010 * example, availability of memory unplug depends on knowing whether 2011 * OV5_HP_EVT was negotiated via CAS. 2012 * 2013 * Thus, for any cases where the set of available CAS-negotiatable 2014 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 2015 * include the CAS-negotiated options in the migration stream, unless 2016 * if they affect boot time behaviour only. 2017 */ 2018 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 2019 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 2020 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 2021 2022 /* We need extra information if we have any bits outside the mask 2023 * defined above */ 2024 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 2025 2026 spapr_ovec_cleanup(ov5_mask); 2027 2028 return cas_needed; 2029 } 2030 2031 static const VMStateDescription vmstate_spapr_ov5_cas = { 2032 .name = "spapr_option_vector_ov5_cas", 2033 .version_id = 1, 2034 .minimum_version_id = 1, 2035 .needed = spapr_ov5_cas_needed, 2036 .fields = (const VMStateField[]) { 2037 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 2038 vmstate_spapr_ovec, SpaprOptionVector), 2039 VMSTATE_END_OF_LIST() 2040 }, 2041 }; 2042 2043 static bool spapr_patb_entry_needed(void *opaque) 2044 { 2045 SpaprMachineState *spapr = opaque; 2046 2047 return !!spapr->patb_entry; 2048 } 2049 2050 static const VMStateDescription vmstate_spapr_patb_entry = { 2051 .name = "spapr_patb_entry", 2052 .version_id = 1, 2053 .minimum_version_id = 1, 2054 .needed = spapr_patb_entry_needed, 2055 .fields = (const VMStateField[]) { 2056 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2057 VMSTATE_END_OF_LIST() 2058 }, 2059 }; 2060 2061 static bool spapr_irq_map_needed(void *opaque) 2062 { 2063 SpaprMachineState *spapr = opaque; 2064 2065 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2066 } 2067 2068 static const VMStateDescription vmstate_spapr_irq_map = { 2069 .name = "spapr_irq_map", 2070 .version_id = 1, 2071 .minimum_version_id = 1, 2072 .needed = spapr_irq_map_needed, 2073 .fields = (const VMStateField[]) { 2074 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2075 VMSTATE_END_OF_LIST() 2076 }, 2077 }; 2078 2079 static bool spapr_dtb_needed(void *opaque) 2080 { 2081 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2082 2083 return smc->update_dt_enabled; 2084 } 2085 2086 static int spapr_dtb_pre_load(void *opaque) 2087 { 2088 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2089 2090 g_free(spapr->fdt_blob); 2091 spapr->fdt_blob = NULL; 2092 spapr->fdt_size = 0; 2093 2094 return 0; 2095 } 2096 2097 static const VMStateDescription vmstate_spapr_dtb = { 2098 .name = "spapr_dtb", 2099 .version_id = 1, 2100 .minimum_version_id = 1, 2101 .needed = spapr_dtb_needed, 2102 .pre_load = spapr_dtb_pre_load, 2103 .fields = (const VMStateField[]) { 2104 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2105 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2106 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2107 fdt_size), 2108 VMSTATE_END_OF_LIST() 2109 }, 2110 }; 2111 2112 static bool spapr_fwnmi_needed(void *opaque) 2113 { 2114 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2115 2116 return spapr->fwnmi_machine_check_addr != -1; 2117 } 2118 2119 static int spapr_fwnmi_pre_save(void *opaque) 2120 { 2121 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2122 2123 /* 2124 * Check if machine check handling is in progress and print a 2125 * warning message. 2126 */ 2127 if (spapr->fwnmi_machine_check_interlock != -1) { 2128 warn_report("A machine check is being handled during migration. The" 2129 "handler may run and log hardware error on the destination"); 2130 } 2131 2132 return 0; 2133 } 2134 2135 static const VMStateDescription vmstate_spapr_fwnmi = { 2136 .name = "spapr_fwnmi", 2137 .version_id = 1, 2138 .minimum_version_id = 1, 2139 .needed = spapr_fwnmi_needed, 2140 .pre_save = spapr_fwnmi_pre_save, 2141 .fields = (const VMStateField[]) { 2142 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2143 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2144 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2145 VMSTATE_END_OF_LIST() 2146 }, 2147 }; 2148 2149 static const VMStateDescription vmstate_spapr = { 2150 .name = "spapr", 2151 .version_id = 3, 2152 .minimum_version_id = 1, 2153 .pre_load = spapr_pre_load, 2154 .post_load = spapr_post_load, 2155 .pre_save = spapr_pre_save, 2156 .fields = (const VMStateField[]) { 2157 /* used to be @next_irq */ 2158 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2159 2160 /* RTC offset */ 2161 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2162 2163 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2164 VMSTATE_END_OF_LIST() 2165 }, 2166 .subsections = (const VMStateDescription * const []) { 2167 &vmstate_spapr_ov5_cas, 2168 &vmstate_spapr_patb_entry, 2169 &vmstate_spapr_pending_events, 2170 &vmstate_spapr_cap_htm, 2171 &vmstate_spapr_cap_vsx, 2172 &vmstate_spapr_cap_dfp, 2173 &vmstate_spapr_cap_cfpc, 2174 &vmstate_spapr_cap_sbbc, 2175 &vmstate_spapr_cap_ibs, 2176 &vmstate_spapr_cap_hpt_maxpagesize, 2177 &vmstate_spapr_irq_map, 2178 &vmstate_spapr_cap_nested_kvm_hv, 2179 &vmstate_spapr_dtb, 2180 &vmstate_spapr_cap_large_decr, 2181 &vmstate_spapr_cap_ccf_assist, 2182 &vmstate_spapr_cap_fwnmi, 2183 &vmstate_spapr_fwnmi, 2184 &vmstate_spapr_cap_rpt_invalidate, 2185 NULL 2186 } 2187 }; 2188 2189 static int htab_save_setup(QEMUFile *f, void *opaque) 2190 { 2191 SpaprMachineState *spapr = opaque; 2192 2193 /* "Iteration" header */ 2194 if (!spapr->htab_shift) { 2195 qemu_put_be32(f, -1); 2196 } else { 2197 qemu_put_be32(f, spapr->htab_shift); 2198 } 2199 2200 if (spapr->htab) { 2201 spapr->htab_save_index = 0; 2202 spapr->htab_first_pass = true; 2203 } else { 2204 if (spapr->htab_shift) { 2205 assert(kvm_enabled()); 2206 } 2207 } 2208 2209 2210 return 0; 2211 } 2212 2213 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2214 int chunkstart, int n_valid, int n_invalid) 2215 { 2216 qemu_put_be32(f, chunkstart); 2217 qemu_put_be16(f, n_valid); 2218 qemu_put_be16(f, n_invalid); 2219 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2220 HASH_PTE_SIZE_64 * n_valid); 2221 } 2222 2223 static void htab_save_end_marker(QEMUFile *f) 2224 { 2225 qemu_put_be32(f, 0); 2226 qemu_put_be16(f, 0); 2227 qemu_put_be16(f, 0); 2228 } 2229 2230 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2231 int64_t max_ns) 2232 { 2233 bool has_timeout = max_ns != -1; 2234 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2235 int index = spapr->htab_save_index; 2236 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2237 2238 assert(spapr->htab_first_pass); 2239 2240 do { 2241 int chunkstart; 2242 2243 /* Consume invalid HPTEs */ 2244 while ((index < htabslots) 2245 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2246 CLEAN_HPTE(HPTE(spapr->htab, index)); 2247 index++; 2248 } 2249 2250 /* Consume valid HPTEs */ 2251 chunkstart = index; 2252 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2253 && HPTE_VALID(HPTE(spapr->htab, index))) { 2254 CLEAN_HPTE(HPTE(spapr->htab, index)); 2255 index++; 2256 } 2257 2258 if (index > chunkstart) { 2259 int n_valid = index - chunkstart; 2260 2261 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2262 2263 if (has_timeout && 2264 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2265 break; 2266 } 2267 } 2268 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2269 2270 if (index >= htabslots) { 2271 assert(index == htabslots); 2272 index = 0; 2273 spapr->htab_first_pass = false; 2274 } 2275 spapr->htab_save_index = index; 2276 } 2277 2278 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2279 int64_t max_ns) 2280 { 2281 bool final = max_ns < 0; 2282 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2283 int examined = 0, sent = 0; 2284 int index = spapr->htab_save_index; 2285 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2286 2287 assert(!spapr->htab_first_pass); 2288 2289 do { 2290 int chunkstart, invalidstart; 2291 2292 /* Consume non-dirty HPTEs */ 2293 while ((index < htabslots) 2294 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2295 index++; 2296 examined++; 2297 } 2298 2299 chunkstart = index; 2300 /* Consume valid dirty HPTEs */ 2301 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2302 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2303 && HPTE_VALID(HPTE(spapr->htab, index))) { 2304 CLEAN_HPTE(HPTE(spapr->htab, index)); 2305 index++; 2306 examined++; 2307 } 2308 2309 invalidstart = index; 2310 /* Consume invalid dirty HPTEs */ 2311 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2312 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2313 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2314 CLEAN_HPTE(HPTE(spapr->htab, index)); 2315 index++; 2316 examined++; 2317 } 2318 2319 if (index > chunkstart) { 2320 int n_valid = invalidstart - chunkstart; 2321 int n_invalid = index - invalidstart; 2322 2323 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2324 sent += index - chunkstart; 2325 2326 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2327 break; 2328 } 2329 } 2330 2331 if (examined >= htabslots) { 2332 break; 2333 } 2334 2335 if (index >= htabslots) { 2336 assert(index == htabslots); 2337 index = 0; 2338 } 2339 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2340 2341 if (index >= htabslots) { 2342 assert(index == htabslots); 2343 index = 0; 2344 } 2345 2346 spapr->htab_save_index = index; 2347 2348 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2349 } 2350 2351 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2352 #define MAX_KVM_BUF_SIZE 2048 2353 2354 static int htab_save_iterate(QEMUFile *f, void *opaque) 2355 { 2356 SpaprMachineState *spapr = opaque; 2357 int fd; 2358 int rc = 0; 2359 2360 /* Iteration header */ 2361 if (!spapr->htab_shift) { 2362 qemu_put_be32(f, -1); 2363 return 1; 2364 } else { 2365 qemu_put_be32(f, 0); 2366 } 2367 2368 if (!spapr->htab) { 2369 assert(kvm_enabled()); 2370 2371 fd = get_htab_fd(spapr); 2372 if (fd < 0) { 2373 return fd; 2374 } 2375 2376 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2377 if (rc < 0) { 2378 return rc; 2379 } 2380 } else if (spapr->htab_first_pass) { 2381 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2382 } else { 2383 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2384 } 2385 2386 htab_save_end_marker(f); 2387 2388 return rc; 2389 } 2390 2391 static int htab_save_complete(QEMUFile *f, void *opaque) 2392 { 2393 SpaprMachineState *spapr = opaque; 2394 int fd; 2395 2396 /* Iteration header */ 2397 if (!spapr->htab_shift) { 2398 qemu_put_be32(f, -1); 2399 return 0; 2400 } else { 2401 qemu_put_be32(f, 0); 2402 } 2403 2404 if (!spapr->htab) { 2405 int rc; 2406 2407 assert(kvm_enabled()); 2408 2409 fd = get_htab_fd(spapr); 2410 if (fd < 0) { 2411 return fd; 2412 } 2413 2414 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2415 if (rc < 0) { 2416 return rc; 2417 } 2418 } else { 2419 if (spapr->htab_first_pass) { 2420 htab_save_first_pass(f, spapr, -1); 2421 } 2422 htab_save_later_pass(f, spapr, -1); 2423 } 2424 2425 /* End marker */ 2426 htab_save_end_marker(f); 2427 2428 return 0; 2429 } 2430 2431 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2432 { 2433 SpaprMachineState *spapr = opaque; 2434 uint32_t section_hdr; 2435 int fd = -1; 2436 Error *local_err = NULL; 2437 2438 if (version_id < 1 || version_id > 1) { 2439 error_report("htab_load() bad version"); 2440 return -EINVAL; 2441 } 2442 2443 section_hdr = qemu_get_be32(f); 2444 2445 if (section_hdr == -1) { 2446 spapr_free_hpt(spapr); 2447 return 0; 2448 } 2449 2450 if (section_hdr) { 2451 int ret; 2452 2453 /* First section gives the htab size */ 2454 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2455 if (ret < 0) { 2456 error_report_err(local_err); 2457 return ret; 2458 } 2459 return 0; 2460 } 2461 2462 if (!spapr->htab) { 2463 assert(kvm_enabled()); 2464 2465 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2466 if (fd < 0) { 2467 error_report_err(local_err); 2468 return fd; 2469 } 2470 } 2471 2472 while (true) { 2473 uint32_t index; 2474 uint16_t n_valid, n_invalid; 2475 2476 index = qemu_get_be32(f); 2477 n_valid = qemu_get_be16(f); 2478 n_invalid = qemu_get_be16(f); 2479 2480 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2481 /* End of Stream */ 2482 break; 2483 } 2484 2485 if ((index + n_valid + n_invalid) > 2486 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2487 /* Bad index in stream */ 2488 error_report( 2489 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2490 index, n_valid, n_invalid, spapr->htab_shift); 2491 return -EINVAL; 2492 } 2493 2494 if (spapr->htab) { 2495 if (n_valid) { 2496 qemu_get_buffer(f, HPTE(spapr->htab, index), 2497 HASH_PTE_SIZE_64 * n_valid); 2498 } 2499 if (n_invalid) { 2500 memset(HPTE(spapr->htab, index + n_valid), 0, 2501 HASH_PTE_SIZE_64 * n_invalid); 2502 } 2503 } else { 2504 int rc; 2505 2506 assert(fd >= 0); 2507 2508 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2509 &local_err); 2510 if (rc < 0) { 2511 error_report_err(local_err); 2512 return rc; 2513 } 2514 } 2515 } 2516 2517 if (!spapr->htab) { 2518 assert(fd >= 0); 2519 close(fd); 2520 } 2521 2522 return 0; 2523 } 2524 2525 static void htab_save_cleanup(void *opaque) 2526 { 2527 SpaprMachineState *spapr = opaque; 2528 2529 close_htab_fd(spapr); 2530 } 2531 2532 static SaveVMHandlers savevm_htab_handlers = { 2533 .save_setup = htab_save_setup, 2534 .save_live_iterate = htab_save_iterate, 2535 .save_live_complete_precopy = htab_save_complete, 2536 .save_cleanup = htab_save_cleanup, 2537 .load_state = htab_load, 2538 }; 2539 2540 static void spapr_boot_set(void *opaque, const char *boot_device, 2541 Error **errp) 2542 { 2543 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2544 2545 g_free(spapr->boot_device); 2546 spapr->boot_device = g_strdup(boot_device); 2547 } 2548 2549 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2550 { 2551 MachineState *machine = MACHINE(spapr); 2552 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2553 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2554 int i; 2555 2556 g_assert(!nr_lmbs || machine->device_memory); 2557 for (i = 0; i < nr_lmbs; i++) { 2558 uint64_t addr; 2559 2560 addr = i * lmb_size + machine->device_memory->base; 2561 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2562 addr / lmb_size); 2563 } 2564 } 2565 2566 /* 2567 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2568 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2569 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2570 */ 2571 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2572 { 2573 int i; 2574 2575 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2576 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2577 " is not aligned to %" PRIu64 " MiB", 2578 machine->ram_size, 2579 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2580 return; 2581 } 2582 2583 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2584 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2585 " is not aligned to %" PRIu64 " MiB", 2586 machine->ram_size, 2587 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2588 return; 2589 } 2590 2591 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2592 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2593 error_setg(errp, 2594 "Node %d memory size 0x%" PRIx64 2595 " is not aligned to %" PRIu64 " MiB", 2596 i, machine->numa_state->nodes[i].node_mem, 2597 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2598 return; 2599 } 2600 } 2601 } 2602 2603 /* find cpu slot in machine->possible_cpus by core_id */ 2604 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2605 { 2606 int index = id / ms->smp.threads; 2607 2608 if (index >= ms->possible_cpus->len) { 2609 return NULL; 2610 } 2611 if (idx) { 2612 *idx = index; 2613 } 2614 return &ms->possible_cpus->cpus[index]; 2615 } 2616 2617 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2618 { 2619 MachineState *ms = MACHINE(spapr); 2620 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2621 Error *local_err = NULL; 2622 bool vsmt_user = !!spapr->vsmt; 2623 int kvm_smt = kvmppc_smt_threads(); 2624 int ret; 2625 unsigned int smp_threads = ms->smp.threads; 2626 2627 if (tcg_enabled()) { 2628 if (smp_threads > 1 && 2629 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2630 spapr->max_compat_pvr)) { 2631 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2632 return; 2633 } 2634 2635 if (smp_threads > 8) { 2636 error_setg(errp, "TCG cannot support more than 8 threads/core " 2637 "on a pseries machine"); 2638 return; 2639 } 2640 } 2641 if (!is_power_of_2(smp_threads)) { 2642 error_setg(errp, "Cannot support %d threads/core on a pseries " 2643 "machine because it must be a power of 2", smp_threads); 2644 return; 2645 } 2646 2647 /* Determine the VSMT mode to use: */ 2648 if (vsmt_user) { 2649 if (spapr->vsmt < smp_threads) { 2650 error_setg(errp, "Cannot support VSMT mode %d" 2651 " because it must be >= threads/core (%d)", 2652 spapr->vsmt, smp_threads); 2653 return; 2654 } 2655 /* In this case, spapr->vsmt has been set by the command line */ 2656 } else if (!smc->smp_threads_vsmt) { 2657 /* 2658 * Default VSMT value is tricky, because we need it to be as 2659 * consistent as possible (for migration), but this requires 2660 * changing it for at least some existing cases. We pick 8 as 2661 * the value that we'd get with KVM on POWER8, the 2662 * overwhelmingly common case in production systems. 2663 */ 2664 spapr->vsmt = MAX(8, smp_threads); 2665 } else { 2666 spapr->vsmt = smp_threads; 2667 } 2668 2669 /* KVM: If necessary, set the SMT mode: */ 2670 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2671 ret = kvmppc_set_smt_threads(spapr->vsmt); 2672 if (ret) { 2673 /* Looks like KVM isn't able to change VSMT mode */ 2674 error_setg(&local_err, 2675 "Failed to set KVM's VSMT mode to %d (errno %d)", 2676 spapr->vsmt, ret); 2677 /* We can live with that if the default one is big enough 2678 * for the number of threads, and a submultiple of the one 2679 * we want. In this case we'll waste some vcpu ids, but 2680 * behaviour will be correct */ 2681 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2682 warn_report_err(local_err); 2683 } else { 2684 if (!vsmt_user) { 2685 error_append_hint(&local_err, 2686 "On PPC, a VM with %d threads/core" 2687 " on a host with %d threads/core" 2688 " requires the use of VSMT mode %d.\n", 2689 smp_threads, kvm_smt, spapr->vsmt); 2690 } 2691 kvmppc_error_append_smt_possible_hint(&local_err); 2692 error_propagate(errp, local_err); 2693 } 2694 } 2695 } 2696 /* else TCG: nothing to do currently */ 2697 } 2698 2699 static void spapr_init_cpus(SpaprMachineState *spapr) 2700 { 2701 MachineState *machine = MACHINE(spapr); 2702 MachineClass *mc = MACHINE_GET_CLASS(machine); 2703 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2704 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2705 const CPUArchIdList *possible_cpus; 2706 unsigned int smp_cpus = machine->smp.cpus; 2707 unsigned int smp_threads = machine->smp.threads; 2708 unsigned int max_cpus = machine->smp.max_cpus; 2709 int boot_cores_nr = smp_cpus / smp_threads; 2710 int i; 2711 2712 possible_cpus = mc->possible_cpu_arch_ids(machine); 2713 if (mc->has_hotpluggable_cpus) { 2714 if (smp_cpus % smp_threads) { 2715 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2716 smp_cpus, smp_threads); 2717 exit(1); 2718 } 2719 if (max_cpus % smp_threads) { 2720 error_report("max_cpus (%u) must be multiple of threads (%u)", 2721 max_cpus, smp_threads); 2722 exit(1); 2723 } 2724 } else { 2725 if (max_cpus != smp_cpus) { 2726 error_report("This machine version does not support CPU hotplug"); 2727 exit(1); 2728 } 2729 boot_cores_nr = possible_cpus->len; 2730 } 2731 2732 if (smc->pre_2_10_has_unused_icps) { 2733 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2734 /* Dummy entries get deregistered when real ICPState objects 2735 * are registered during CPU core hotplug. 2736 */ 2737 pre_2_10_vmstate_register_dummy_icp(i); 2738 } 2739 } 2740 2741 for (i = 0; i < possible_cpus->len; i++) { 2742 int core_id = i * smp_threads; 2743 2744 if (mc->has_hotpluggable_cpus) { 2745 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2746 spapr_vcpu_id(spapr, core_id)); 2747 } 2748 2749 if (i < boot_cores_nr) { 2750 Object *core = object_new(type); 2751 int nr_threads = smp_threads; 2752 2753 /* Handle the partially filled core for older machine types */ 2754 if ((i + 1) * smp_threads >= smp_cpus) { 2755 nr_threads = smp_cpus - i * smp_threads; 2756 } 2757 2758 object_property_set_int(core, "nr-threads", nr_threads, 2759 &error_fatal); 2760 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2761 &error_fatal); 2762 qdev_realize(DEVICE(core), NULL, &error_fatal); 2763 2764 object_unref(core); 2765 } 2766 } 2767 } 2768 2769 static PCIHostState *spapr_create_default_phb(void) 2770 { 2771 DeviceState *dev; 2772 2773 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2774 qdev_prop_set_uint32(dev, "index", 0); 2775 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2776 2777 return PCI_HOST_BRIDGE(dev); 2778 } 2779 2780 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2781 { 2782 MachineState *machine = MACHINE(spapr); 2783 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2784 hwaddr rma_size = machine->ram_size; 2785 hwaddr node0_size = spapr_node0_size(machine); 2786 2787 /* RMA has to fit in the first NUMA node */ 2788 rma_size = MIN(rma_size, node0_size); 2789 2790 /* 2791 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2792 * never exceed that 2793 */ 2794 rma_size = MIN(rma_size, 1 * TiB); 2795 2796 /* 2797 * Clamp the RMA size based on machine type. This is for 2798 * migration compatibility with older qemu versions, which limited 2799 * the RMA size for complicated and mostly bad reasons. 2800 */ 2801 if (smc->rma_limit) { 2802 rma_size = MIN(rma_size, smc->rma_limit); 2803 } 2804 2805 if (rma_size < MIN_RMA_SLOF) { 2806 error_setg(errp, 2807 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2808 "ldMiB guest RMA (Real Mode Area memory)", 2809 MIN_RMA_SLOF / MiB); 2810 return 0; 2811 } 2812 2813 return rma_size; 2814 } 2815 2816 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2817 { 2818 MachineState *machine = MACHINE(spapr); 2819 int i; 2820 2821 for (i = 0; i < machine->ram_slots; i++) { 2822 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2823 } 2824 } 2825 2826 /* pSeries LPAR / sPAPR hardware init */ 2827 static void spapr_machine_init(MachineState *machine) 2828 { 2829 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2830 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2831 MachineClass *mc = MACHINE_GET_CLASS(machine); 2832 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2833 const char *bios_name = machine->firmware ?: bios_default; 2834 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2835 const char *kernel_filename = machine->kernel_filename; 2836 const char *initrd_filename = machine->initrd_filename; 2837 PCIHostState *phb; 2838 bool has_vga; 2839 int i; 2840 MemoryRegion *sysmem = get_system_memory(); 2841 long load_limit, fw_size; 2842 Error *resize_hpt_err = NULL; 2843 NICInfo *nd; 2844 2845 if (!filename) { 2846 error_report("Could not find LPAR firmware '%s'", bios_name); 2847 exit(1); 2848 } 2849 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2850 if (fw_size <= 0) { 2851 error_report("Could not load LPAR firmware '%s'", filename); 2852 exit(1); 2853 } 2854 2855 /* 2856 * if Secure VM (PEF) support is configured, then initialize it 2857 */ 2858 pef_kvm_init(machine->cgs, &error_fatal); 2859 2860 msi_nonbroken = true; 2861 2862 QLIST_INIT(&spapr->phbs); 2863 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2864 2865 /* Determine capabilities to run with */ 2866 spapr_caps_init(spapr); 2867 2868 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2869 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2870 /* 2871 * If the user explicitly requested a mode we should either 2872 * supply it, or fail completely (which we do below). But if 2873 * it's not set explicitly, we reset our mode to something 2874 * that works 2875 */ 2876 if (resize_hpt_err) { 2877 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2878 error_free(resize_hpt_err); 2879 resize_hpt_err = NULL; 2880 } else { 2881 spapr->resize_hpt = smc->resize_hpt_default; 2882 } 2883 } 2884 2885 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2886 2887 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2888 /* 2889 * User requested HPT resize, but this host can't supply it. Bail out 2890 */ 2891 error_report_err(resize_hpt_err); 2892 exit(1); 2893 } 2894 error_free(resize_hpt_err); 2895 2896 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2897 2898 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2899 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2900 2901 /* 2902 * VSMT must be set in order to be able to compute VCPU ids, ie to 2903 * call spapr_max_server_number() or spapr_vcpu_id(). 2904 */ 2905 spapr_set_vsmt_mode(spapr, &error_fatal); 2906 2907 /* Set up Interrupt Controller before we create the VCPUs */ 2908 spapr_irq_init(spapr, &error_fatal); 2909 2910 /* Set up containers for ibm,client-architecture-support negotiated options 2911 */ 2912 spapr->ov5 = spapr_ovec_new(); 2913 spapr->ov5_cas = spapr_ovec_new(); 2914 2915 if (smc->dr_lmb_enabled) { 2916 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2917 spapr_validate_node_memory(machine, &error_fatal); 2918 } 2919 2920 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2921 2922 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2923 if (!smc->pre_6_2_numa_affinity) { 2924 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2925 } 2926 2927 /* advertise support for dedicated HP event source to guests */ 2928 if (spapr->use_hotplug_event_source) { 2929 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2930 } 2931 2932 /* advertise support for HPT resizing */ 2933 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2934 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2935 } 2936 2937 /* advertise support for ibm,dyamic-memory-v2 */ 2938 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2939 2940 /* advertise XIVE on POWER9 machines */ 2941 if (spapr->irq->xive) { 2942 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2943 } 2944 2945 /* init CPUs */ 2946 spapr_init_cpus(spapr); 2947 2948 /* Init numa_assoc_array */ 2949 spapr_numa_associativity_init(spapr, machine); 2950 2951 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2952 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2953 spapr->max_compat_pvr)) { 2954 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2955 /* KVM and TCG always allow GTSE with radix... */ 2956 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2957 } 2958 /* ... but not with hash (currently). */ 2959 2960 if (kvm_enabled()) { 2961 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2962 kvmppc_enable_logical_ci_hcalls(); 2963 kvmppc_enable_set_mode_hcall(); 2964 2965 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2966 kvmppc_enable_clear_ref_mod_hcalls(); 2967 2968 /* Enable H_PAGE_INIT */ 2969 kvmppc_enable_h_page_init(); 2970 } 2971 2972 /* map RAM */ 2973 memory_region_add_subregion(sysmem, 0, machine->ram); 2974 2975 /* initialize hotplug memory address space */ 2976 if (machine->ram_size < machine->maxram_size) { 2977 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2978 hwaddr device_mem_base; 2979 2980 /* 2981 * Limit the number of hotpluggable memory slots to half the number 2982 * slots that KVM supports, leaving the other half for PCI and other 2983 * devices. However ensure that number of slots doesn't drop below 32. 2984 */ 2985 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2986 SPAPR_MAX_RAM_SLOTS; 2987 2988 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2989 max_memslots = SPAPR_MAX_RAM_SLOTS; 2990 } 2991 if (machine->ram_slots > max_memslots) { 2992 error_report("Specified number of memory slots %" 2993 PRIu64" exceeds max supported %d", 2994 machine->ram_slots, max_memslots); 2995 exit(1); 2996 } 2997 2998 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 2999 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 3000 } 3001 3002 if (smc->dr_lmb_enabled) { 3003 spapr_create_lmb_dr_connectors(spapr); 3004 } 3005 3006 if (mc->nvdimm_supported) { 3007 spapr_create_nvdimm_dr_connectors(spapr); 3008 } 3009 3010 /* Set up RTAS event infrastructure */ 3011 spapr_events_init(spapr); 3012 3013 /* Set up the RTC RTAS interfaces */ 3014 spapr_rtc_create(spapr); 3015 3016 /* Set up VIO bus */ 3017 spapr->vio_bus = spapr_vio_bus_init(); 3018 3019 for (i = 0; serial_hd(i); i++) { 3020 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 3021 } 3022 3023 /* We always have at least the nvram device on VIO */ 3024 spapr_create_nvram(spapr); 3025 3026 /* 3027 * Setup hotplug / dynamic-reconfiguration connectors. top-level 3028 * connectors (described in root DT node's "ibm,drc-types" property) 3029 * are pre-initialized here. additional child connectors (such as 3030 * connectors for a PHBs PCI slots) are added as needed during their 3031 * parent's realization. 3032 */ 3033 if (smc->dr_phb_enabled) { 3034 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 3035 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 3036 } 3037 } 3038 3039 /* Set up PCI */ 3040 spapr_pci_rtas_init(); 3041 3042 phb = spapr_create_default_phb(); 3043 3044 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 3045 spapr_vlan_create(spapr->vio_bus, nd); 3046 } 3047 3048 pci_init_nic_devices(phb->bus, NULL); 3049 3050 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 3051 spapr_vscsi_create(spapr->vio_bus); 3052 } 3053 3054 /* Graphics */ 3055 has_vga = spapr_vga_init(phb->bus, &error_fatal); 3056 if (has_vga) { 3057 spapr->want_stdout_path = !machine->enable_graphics; 3058 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3059 } else { 3060 spapr->want_stdout_path = true; 3061 } 3062 3063 if (machine->usb) { 3064 if (smc->use_ohci_by_default) { 3065 pci_create_simple(phb->bus, -1, "pci-ohci"); 3066 } else { 3067 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3068 } 3069 3070 if (has_vga) { 3071 USBBus *usb_bus; 3072 3073 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3074 &error_abort)); 3075 usb_create_simple(usb_bus, "usb-kbd"); 3076 usb_create_simple(usb_bus, "usb-mouse"); 3077 } 3078 } 3079 3080 if (kernel_filename) { 3081 uint64_t loaded_addr = 0; 3082 3083 spapr->kernel_size = load_elf(kernel_filename, NULL, 3084 translate_kernel_address, spapr, 3085 NULL, &loaded_addr, NULL, NULL, 1, 3086 PPC_ELF_MACHINE, 0, 0); 3087 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3088 spapr->kernel_size = load_elf(kernel_filename, NULL, 3089 translate_kernel_address, spapr, 3090 NULL, &loaded_addr, NULL, NULL, 0, 3091 PPC_ELF_MACHINE, 0, 0); 3092 spapr->kernel_le = spapr->kernel_size > 0; 3093 } 3094 if (spapr->kernel_size < 0) { 3095 error_report("error loading %s: %s", kernel_filename, 3096 load_elf_strerror(spapr->kernel_size)); 3097 exit(1); 3098 } 3099 3100 if (spapr->kernel_addr != loaded_addr) { 3101 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3102 " to 0x%"PRIx64, 3103 spapr->kernel_addr, loaded_addr); 3104 spapr->kernel_addr = loaded_addr; 3105 } 3106 3107 /* load initrd */ 3108 if (initrd_filename) { 3109 /* Try to locate the initrd in the gap between the kernel 3110 * and the firmware. Add a bit of space just in case 3111 */ 3112 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3113 + 0x1ffff) & ~0xffff; 3114 spapr->initrd_size = load_image_targphys(initrd_filename, 3115 spapr->initrd_base, 3116 load_limit 3117 - spapr->initrd_base); 3118 if (spapr->initrd_size < 0) { 3119 error_report("could not load initial ram disk '%s'", 3120 initrd_filename); 3121 exit(1); 3122 } 3123 } 3124 } 3125 3126 /* FIXME: Should register things through the MachineState's qdev 3127 * interface, this is a legacy from the sPAPREnvironment structure 3128 * which predated MachineState but had a similar function */ 3129 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3130 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3131 &savevm_htab_handlers, spapr); 3132 3133 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3134 3135 qemu_register_boot_set(spapr_boot_set, spapr); 3136 3137 /* 3138 * Nothing needs to be done to resume a suspended guest because 3139 * suspending does not change the machine state, so no need for 3140 * a ->wakeup method. 3141 */ 3142 qemu_register_wakeup_support(); 3143 3144 if (kvm_enabled()) { 3145 /* to stop and start vmclock */ 3146 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3147 &spapr->tb); 3148 3149 kvmppc_spapr_enable_inkernel_multitce(); 3150 } 3151 3152 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3153 if (spapr->vof) { 3154 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3155 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3156 } 3157 3158 spapr_watchdog_init(spapr); 3159 } 3160 3161 #define DEFAULT_KVM_TYPE "auto" 3162 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3163 { 3164 /* 3165 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3166 * accommodate the 'HV' and 'PV' formats that exists in the 3167 * wild. The 'auto' mode is being introduced already as 3168 * lower-case, thus we don't need to bother checking for 3169 * "AUTO". 3170 */ 3171 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3172 return 0; 3173 } 3174 3175 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3176 return 1; 3177 } 3178 3179 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3180 return 2; 3181 } 3182 3183 error_report("Unknown kvm-type specified '%s'", vm_type); 3184 return -1; 3185 } 3186 3187 /* 3188 * Implementation of an interface to adjust firmware path 3189 * for the bootindex property handling. 3190 */ 3191 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3192 DeviceState *dev) 3193 { 3194 #define CAST(type, obj, name) \ 3195 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3196 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3197 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3198 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3199 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3200 3201 if (d && bus) { 3202 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3203 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3204 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3205 3206 if (spapr) { 3207 /* 3208 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3209 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3210 * 0x8000 | (target << 8) | (bus << 5) | lun 3211 * (see the "Logical unit addressing format" table in SAM5) 3212 */ 3213 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3214 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3215 (uint64_t)id << 48); 3216 } else if (virtio) { 3217 /* 3218 * We use SRP luns of the form 01000000 | (target << 8) | lun 3219 * in the top 32 bits of the 64-bit LUN 3220 * Note: the quote above is from SLOF and it is wrong, 3221 * the actual binding is: 3222 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3223 */ 3224 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3225 if (d->lun >= 256) { 3226 /* Use the LUN "flat space addressing method" */ 3227 id |= 0x4000; 3228 } 3229 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3230 (uint64_t)id << 32); 3231 } else if (usb) { 3232 /* 3233 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3234 * in the top 32 bits of the 64-bit LUN 3235 */ 3236 unsigned usb_port = atoi(usb->port->path); 3237 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3238 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3239 (uint64_t)id << 32); 3240 } 3241 } 3242 3243 /* 3244 * SLOF probes the USB devices, and if it recognizes that the device is a 3245 * storage device, it changes its name to "storage" instead of "usb-host", 3246 * and additionally adds a child node for the SCSI LUN, so the correct 3247 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3248 */ 3249 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3250 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3251 if (usb_device_is_scsi_storage(usbdev)) { 3252 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3253 } 3254 } 3255 3256 if (phb) { 3257 /* Replace "pci" with "pci@800000020000000" */ 3258 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3259 } 3260 3261 if (vsc) { 3262 /* Same logic as virtio above */ 3263 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3264 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3265 } 3266 3267 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3268 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3269 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3270 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3271 } 3272 3273 if (pcidev) { 3274 return spapr_pci_fw_dev_name(pcidev); 3275 } 3276 3277 return NULL; 3278 } 3279 3280 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3281 { 3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3283 3284 return g_strdup(spapr->kvm_type); 3285 } 3286 3287 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3288 { 3289 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3290 3291 g_free(spapr->kvm_type); 3292 spapr->kvm_type = g_strdup(value); 3293 } 3294 3295 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3296 { 3297 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3298 3299 return spapr->use_hotplug_event_source; 3300 } 3301 3302 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3303 Error **errp) 3304 { 3305 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3306 3307 spapr->use_hotplug_event_source = value; 3308 } 3309 3310 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3311 { 3312 return true; 3313 } 3314 3315 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3316 { 3317 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3318 3319 switch (spapr->resize_hpt) { 3320 case SPAPR_RESIZE_HPT_DEFAULT: 3321 return g_strdup("default"); 3322 case SPAPR_RESIZE_HPT_DISABLED: 3323 return g_strdup("disabled"); 3324 case SPAPR_RESIZE_HPT_ENABLED: 3325 return g_strdup("enabled"); 3326 case SPAPR_RESIZE_HPT_REQUIRED: 3327 return g_strdup("required"); 3328 } 3329 g_assert_not_reached(); 3330 } 3331 3332 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3333 { 3334 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3335 3336 if (strcmp(value, "default") == 0) { 3337 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3338 } else if (strcmp(value, "disabled") == 0) { 3339 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3340 } else if (strcmp(value, "enabled") == 0) { 3341 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3342 } else if (strcmp(value, "required") == 0) { 3343 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3344 } else { 3345 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3346 } 3347 } 3348 3349 static bool spapr_get_vof(Object *obj, Error **errp) 3350 { 3351 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3352 3353 return spapr->vof != NULL; 3354 } 3355 3356 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3357 { 3358 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3359 3360 if (spapr->vof) { 3361 vof_cleanup(spapr->vof); 3362 g_free(spapr->vof); 3363 spapr->vof = NULL; 3364 } 3365 if (!value) { 3366 return; 3367 } 3368 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3369 } 3370 3371 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3372 { 3373 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3374 3375 if (spapr->irq == &spapr_irq_xics_legacy) { 3376 return g_strdup("legacy"); 3377 } else if (spapr->irq == &spapr_irq_xics) { 3378 return g_strdup("xics"); 3379 } else if (spapr->irq == &spapr_irq_xive) { 3380 return g_strdup("xive"); 3381 } else if (spapr->irq == &spapr_irq_dual) { 3382 return g_strdup("dual"); 3383 } 3384 g_assert_not_reached(); 3385 } 3386 3387 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3388 { 3389 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3390 3391 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3392 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3393 return; 3394 } 3395 3396 /* The legacy IRQ backend can not be set */ 3397 if (strcmp(value, "xics") == 0) { 3398 spapr->irq = &spapr_irq_xics; 3399 } else if (strcmp(value, "xive") == 0) { 3400 spapr->irq = &spapr_irq_xive; 3401 } else if (strcmp(value, "dual") == 0) { 3402 spapr->irq = &spapr_irq_dual; 3403 } else { 3404 error_setg(errp, "Bad value for \"ic-mode\" property"); 3405 } 3406 } 3407 3408 static char *spapr_get_host_model(Object *obj, Error **errp) 3409 { 3410 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3411 3412 return g_strdup(spapr->host_model); 3413 } 3414 3415 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3416 { 3417 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3418 3419 g_free(spapr->host_model); 3420 spapr->host_model = g_strdup(value); 3421 } 3422 3423 static char *spapr_get_host_serial(Object *obj, Error **errp) 3424 { 3425 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3426 3427 return g_strdup(spapr->host_serial); 3428 } 3429 3430 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3431 { 3432 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3433 3434 g_free(spapr->host_serial); 3435 spapr->host_serial = g_strdup(value); 3436 } 3437 3438 static void spapr_instance_init(Object *obj) 3439 { 3440 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3441 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3442 MachineState *ms = MACHINE(spapr); 3443 MachineClass *mc = MACHINE_GET_CLASS(ms); 3444 3445 /* 3446 * NVDIMM support went live in 5.1 without considering that, in 3447 * other archs, the user needs to enable NVDIMM support with the 3448 * 'nvdimm' machine option and the default behavior is NVDIMM 3449 * support disabled. It is too late to roll back to the standard 3450 * behavior without breaking 5.1 guests. 3451 */ 3452 if (mc->nvdimm_supported) { 3453 ms->nvdimms_state->is_enabled = true; 3454 } 3455 3456 spapr->htab_fd = -1; 3457 spapr->use_hotplug_event_source = true; 3458 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3459 object_property_add_str(obj, "kvm-type", 3460 spapr_get_kvm_type, spapr_set_kvm_type); 3461 object_property_set_description(obj, "kvm-type", 3462 "Specifies the KVM virtualization mode (auto," 3463 " hv, pr). Defaults to 'auto'. This mode will use" 3464 " any available KVM module loaded in the host," 3465 " where kvm_hv takes precedence if both kvm_hv and" 3466 " kvm_pr are loaded."); 3467 object_property_add_bool(obj, "modern-hotplug-events", 3468 spapr_get_modern_hotplug_events, 3469 spapr_set_modern_hotplug_events); 3470 object_property_set_description(obj, "modern-hotplug-events", 3471 "Use dedicated hotplug event mechanism in" 3472 " place of standard EPOW events when possible" 3473 " (required for memory hot-unplug support)"); 3474 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3475 "Maximum permitted CPU compatibility mode"); 3476 3477 object_property_add_str(obj, "resize-hpt", 3478 spapr_get_resize_hpt, spapr_set_resize_hpt); 3479 object_property_set_description(obj, "resize-hpt", 3480 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3481 object_property_add_uint32_ptr(obj, "vsmt", 3482 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3483 object_property_set_description(obj, "vsmt", 3484 "Virtual SMT: KVM behaves as if this were" 3485 " the host's SMT mode"); 3486 3487 object_property_add_bool(obj, "vfio-no-msix-emulation", 3488 spapr_get_msix_emulation, NULL); 3489 3490 object_property_add_uint64_ptr(obj, "kernel-addr", 3491 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3492 object_property_set_description(obj, "kernel-addr", 3493 stringify(KERNEL_LOAD_ADDR) 3494 " for -kernel is the default"); 3495 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3496 3497 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3498 object_property_set_description(obj, "x-vof", 3499 "Enable Virtual Open Firmware (experimental)"); 3500 3501 /* The machine class defines the default interrupt controller mode */ 3502 spapr->irq = smc->irq; 3503 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3504 spapr_set_ic_mode); 3505 object_property_set_description(obj, "ic-mode", 3506 "Specifies the interrupt controller mode (xics, xive, dual)"); 3507 3508 object_property_add_str(obj, "host-model", 3509 spapr_get_host_model, spapr_set_host_model); 3510 object_property_set_description(obj, "host-model", 3511 "Host model to advertise in guest device tree"); 3512 object_property_add_str(obj, "host-serial", 3513 spapr_get_host_serial, spapr_set_host_serial); 3514 object_property_set_description(obj, "host-serial", 3515 "Host serial number to advertise in guest device tree"); 3516 } 3517 3518 static void spapr_machine_finalizefn(Object *obj) 3519 { 3520 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3521 3522 g_free(spapr->kvm_type); 3523 } 3524 3525 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3526 { 3527 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3528 PowerPCCPU *cpu = POWERPC_CPU(cs); 3529 CPUPPCState *env = &cpu->env; 3530 3531 cpu_synchronize_state(cs); 3532 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3533 if (spapr->fwnmi_system_reset_addr != -1) { 3534 uint64_t rtas_addr, addr; 3535 3536 /* get rtas addr from fdt */ 3537 rtas_addr = spapr_get_rtas_addr(); 3538 if (!rtas_addr) { 3539 qemu_system_guest_panicked(NULL); 3540 return; 3541 } 3542 3543 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3544 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3545 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3546 env->gpr[3] = addr; 3547 } 3548 ppc_cpu_do_system_reset(cs); 3549 if (spapr->fwnmi_system_reset_addr != -1) { 3550 env->nip = spapr->fwnmi_system_reset_addr; 3551 } 3552 } 3553 3554 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3555 { 3556 CPUState *cs; 3557 3558 CPU_FOREACH(cs) { 3559 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3560 } 3561 } 3562 3563 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3564 void *fdt, int *fdt_start_offset, Error **errp) 3565 { 3566 uint64_t addr; 3567 uint32_t node; 3568 3569 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3570 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3571 &error_abort); 3572 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3573 SPAPR_MEMORY_BLOCK_SIZE); 3574 return 0; 3575 } 3576 3577 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3578 bool dedicated_hp_event_source) 3579 { 3580 SpaprDrc *drc; 3581 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3582 int i; 3583 uint64_t addr = addr_start; 3584 bool hotplugged = spapr_drc_hotplugged(dev); 3585 3586 for (i = 0; i < nr_lmbs; i++) { 3587 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3588 addr / SPAPR_MEMORY_BLOCK_SIZE); 3589 g_assert(drc); 3590 3591 /* 3592 * memory_device_get_free_addr() provided a range of free addresses 3593 * that doesn't overlap with any existing mapping at pre-plug. The 3594 * corresponding LMB DRCs are thus assumed to be all attachable. 3595 */ 3596 spapr_drc_attach(drc, dev); 3597 if (!hotplugged) { 3598 spapr_drc_reset(drc); 3599 } 3600 addr += SPAPR_MEMORY_BLOCK_SIZE; 3601 } 3602 /* send hotplug notification to the 3603 * guest only in case of hotplugged memory 3604 */ 3605 if (hotplugged) { 3606 if (dedicated_hp_event_source) { 3607 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3608 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3609 g_assert(drc); 3610 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3611 nr_lmbs, 3612 spapr_drc_index(drc)); 3613 } else { 3614 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3615 nr_lmbs); 3616 } 3617 } 3618 } 3619 3620 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3621 { 3622 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3623 PCDIMMDevice *dimm = PC_DIMM(dev); 3624 uint64_t size, addr; 3625 int64_t slot; 3626 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3627 3628 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3629 3630 pc_dimm_plug(dimm, MACHINE(ms)); 3631 3632 if (!is_nvdimm) { 3633 addr = object_property_get_uint(OBJECT(dimm), 3634 PC_DIMM_ADDR_PROP, &error_abort); 3635 spapr_add_lmbs(dev, addr, size, 3636 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3637 } else { 3638 slot = object_property_get_int(OBJECT(dimm), 3639 PC_DIMM_SLOT_PROP, &error_abort); 3640 /* We should have valid slot number at this point */ 3641 g_assert(slot >= 0); 3642 spapr_add_nvdimm(dev, slot); 3643 } 3644 } 3645 3646 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3647 Error **errp) 3648 { 3649 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3650 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3651 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3652 PCDIMMDevice *dimm = PC_DIMM(dev); 3653 Error *local_err = NULL; 3654 uint64_t size; 3655 Object *memdev; 3656 hwaddr pagesize; 3657 3658 if (!smc->dr_lmb_enabled) { 3659 error_setg(errp, "Memory hotplug not supported for this machine"); 3660 return; 3661 } 3662 3663 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3664 if (local_err) { 3665 error_propagate(errp, local_err); 3666 return; 3667 } 3668 3669 if (is_nvdimm) { 3670 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3671 return; 3672 } 3673 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3674 error_setg(errp, "Hotplugged memory size must be a multiple of " 3675 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3676 return; 3677 } 3678 3679 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3680 &error_abort); 3681 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3682 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3683 return; 3684 } 3685 3686 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3687 } 3688 3689 struct SpaprDimmState { 3690 PCDIMMDevice *dimm; 3691 uint32_t nr_lmbs; 3692 QTAILQ_ENTRY(SpaprDimmState) next; 3693 }; 3694 3695 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3696 PCDIMMDevice *dimm) 3697 { 3698 SpaprDimmState *dimm_state = NULL; 3699 3700 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3701 if (dimm_state->dimm == dimm) { 3702 break; 3703 } 3704 } 3705 return dimm_state; 3706 } 3707 3708 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3709 uint32_t nr_lmbs, 3710 PCDIMMDevice *dimm) 3711 { 3712 SpaprDimmState *ds = NULL; 3713 3714 /* 3715 * If this request is for a DIMM whose removal had failed earlier 3716 * (due to guest's refusal to remove the LMBs), we would have this 3717 * dimm already in the pending_dimm_unplugs list. In that 3718 * case don't add again. 3719 */ 3720 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3721 if (!ds) { 3722 ds = g_new0(SpaprDimmState, 1); 3723 ds->nr_lmbs = nr_lmbs; 3724 ds->dimm = dimm; 3725 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3726 } 3727 return ds; 3728 } 3729 3730 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3731 SpaprDimmState *dimm_state) 3732 { 3733 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3734 g_free(dimm_state); 3735 } 3736 3737 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3738 PCDIMMDevice *dimm) 3739 { 3740 SpaprDrc *drc; 3741 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3742 &error_abort); 3743 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3744 uint32_t avail_lmbs = 0; 3745 uint64_t addr_start, addr; 3746 int i; 3747 3748 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3749 &error_abort); 3750 3751 addr = addr_start; 3752 for (i = 0; i < nr_lmbs; i++) { 3753 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3754 addr / SPAPR_MEMORY_BLOCK_SIZE); 3755 g_assert(drc); 3756 if (drc->dev) { 3757 avail_lmbs++; 3758 } 3759 addr += SPAPR_MEMORY_BLOCK_SIZE; 3760 } 3761 3762 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3763 } 3764 3765 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3766 { 3767 SpaprDimmState *ds; 3768 PCDIMMDevice *dimm; 3769 SpaprDrc *drc; 3770 uint32_t nr_lmbs; 3771 uint64_t size, addr_start, addr; 3772 g_autofree char *qapi_error = NULL; 3773 int i; 3774 3775 if (!dev) { 3776 return; 3777 } 3778 3779 dimm = PC_DIMM(dev); 3780 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3781 3782 /* 3783 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3784 * unplug state, but one of its DRC is marked as unplug_requested. 3785 * This is bad and weird enough to g_assert() out. 3786 */ 3787 g_assert(ds); 3788 3789 spapr_pending_dimm_unplugs_remove(spapr, ds); 3790 3791 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3792 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3793 3794 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3795 &error_abort); 3796 3797 addr = addr_start; 3798 for (i = 0; i < nr_lmbs; i++) { 3799 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3800 addr / SPAPR_MEMORY_BLOCK_SIZE); 3801 g_assert(drc); 3802 3803 drc->unplug_requested = false; 3804 addr += SPAPR_MEMORY_BLOCK_SIZE; 3805 } 3806 3807 /* 3808 * Tell QAPI that something happened and the memory 3809 * hotunplug wasn't successful. Keep sending 3810 * MEM_UNPLUG_ERROR even while sending 3811 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3812 * MEM_UNPLUG_ERROR is due. 3813 */ 3814 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3815 "for device %s", dev->id); 3816 3817 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3818 3819 qapi_event_send_device_unplug_guest_error(dev->id, 3820 dev->canonical_path); 3821 } 3822 3823 /* Callback to be called during DRC release. */ 3824 void spapr_lmb_release(DeviceState *dev) 3825 { 3826 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3827 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3828 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3829 3830 /* This information will get lost if a migration occurs 3831 * during the unplug process. In this case recover it. */ 3832 if (ds == NULL) { 3833 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3834 g_assert(ds); 3835 /* The DRC being examined by the caller at least must be counted */ 3836 g_assert(ds->nr_lmbs); 3837 } 3838 3839 if (--ds->nr_lmbs) { 3840 return; 3841 } 3842 3843 /* 3844 * Now that all the LMBs have been removed by the guest, call the 3845 * unplug handler chain. This can never fail. 3846 */ 3847 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3848 object_unparent(OBJECT(dev)); 3849 } 3850 3851 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3852 { 3853 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3854 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3855 3856 /* We really shouldn't get this far without anything to unplug */ 3857 g_assert(ds); 3858 3859 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3860 qdev_unrealize(dev); 3861 spapr_pending_dimm_unplugs_remove(spapr, ds); 3862 } 3863 3864 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3865 DeviceState *dev, Error **errp) 3866 { 3867 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3868 PCDIMMDevice *dimm = PC_DIMM(dev); 3869 uint32_t nr_lmbs; 3870 uint64_t size, addr_start, addr; 3871 int i; 3872 SpaprDrc *drc; 3873 3874 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3875 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3876 return; 3877 } 3878 3879 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3880 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3881 3882 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3883 &error_abort); 3884 3885 /* 3886 * An existing pending dimm state for this DIMM means that there is an 3887 * unplug operation in progress, waiting for the spapr_lmb_release 3888 * callback to complete the job (BQL can't cover that far). In this case, 3889 * bail out to avoid detaching DRCs that were already released. 3890 */ 3891 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3892 error_setg(errp, "Memory unplug already in progress for device %s", 3893 dev->id); 3894 return; 3895 } 3896 3897 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3898 3899 addr = addr_start; 3900 for (i = 0; i < nr_lmbs; i++) { 3901 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3902 addr / SPAPR_MEMORY_BLOCK_SIZE); 3903 g_assert(drc); 3904 3905 spapr_drc_unplug_request(drc); 3906 addr += SPAPR_MEMORY_BLOCK_SIZE; 3907 } 3908 3909 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3910 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3911 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3912 nr_lmbs, spapr_drc_index(drc)); 3913 } 3914 3915 /* Callback to be called during DRC release. */ 3916 void spapr_core_release(DeviceState *dev) 3917 { 3918 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3919 3920 /* Call the unplug handler chain. This can never fail. */ 3921 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3922 object_unparent(OBJECT(dev)); 3923 } 3924 3925 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3926 { 3927 MachineState *ms = MACHINE(hotplug_dev); 3928 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3929 CPUCore *cc = CPU_CORE(dev); 3930 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3931 3932 if (smc->pre_2_10_has_unused_icps) { 3933 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3934 int i; 3935 3936 for (i = 0; i < cc->nr_threads; i++) { 3937 CPUState *cs = CPU(sc->threads[i]); 3938 3939 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3940 } 3941 } 3942 3943 assert(core_slot); 3944 core_slot->cpu = NULL; 3945 qdev_unrealize(dev); 3946 } 3947 3948 static 3949 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3950 Error **errp) 3951 { 3952 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3953 int index; 3954 SpaprDrc *drc; 3955 CPUCore *cc = CPU_CORE(dev); 3956 3957 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3958 error_setg(errp, "Unable to find CPU core with core-id: %d", 3959 cc->core_id); 3960 return; 3961 } 3962 if (index == 0) { 3963 error_setg(errp, "Boot CPU core may not be unplugged"); 3964 return; 3965 } 3966 3967 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3968 spapr_vcpu_id(spapr, cc->core_id)); 3969 g_assert(drc); 3970 3971 if (!spapr_drc_unplug_requested(drc)) { 3972 spapr_drc_unplug_request(drc); 3973 } 3974 3975 /* 3976 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3977 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3978 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3979 * attempt (e.g. the kernel will refuse to remove the last online 3980 * CPU), we will never attempt it again because unplug_requested 3981 * will still be 'true' in that case. 3982 */ 3983 spapr_hotplug_req_remove_by_index(drc); 3984 } 3985 3986 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3987 void *fdt, int *fdt_start_offset, Error **errp) 3988 { 3989 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3990 CPUState *cs = CPU(core->threads[0]); 3991 PowerPCCPU *cpu = POWERPC_CPU(cs); 3992 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3993 int id = spapr_get_vcpu_id(cpu); 3994 g_autofree char *nodename = NULL; 3995 int offset; 3996 3997 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3998 offset = fdt_add_subnode(fdt, 0, nodename); 3999 4000 spapr_dt_cpu(cs, fdt, offset, spapr); 4001 4002 /* 4003 * spapr_dt_cpu() does not fill the 'name' property in the 4004 * CPU node. The function is called during boot process, before 4005 * and after CAS, and overwriting the 'name' property written 4006 * by SLOF is not allowed. 4007 * 4008 * Write it manually after spapr_dt_cpu(). This makes the hotplug 4009 * CPUs more compatible with the coldplugged ones, which have 4010 * the 'name' property. Linux Kernel also relies on this 4011 * property to identify CPU nodes. 4012 */ 4013 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 4014 4015 *fdt_start_offset = offset; 4016 return 0; 4017 } 4018 4019 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4020 { 4021 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4022 MachineClass *mc = MACHINE_GET_CLASS(spapr); 4023 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4024 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 4025 CPUCore *cc = CPU_CORE(dev); 4026 CPUState *cs; 4027 SpaprDrc *drc; 4028 CPUArchId *core_slot; 4029 int index; 4030 bool hotplugged = spapr_drc_hotplugged(dev); 4031 int i; 4032 4033 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4034 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 4035 4036 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 4037 spapr_vcpu_id(spapr, cc->core_id)); 4038 4039 g_assert(drc || !mc->has_hotpluggable_cpus); 4040 4041 if (drc) { 4042 /* 4043 * spapr_core_pre_plug() already buys us this is a brand new 4044 * core being plugged into a free slot. Nothing should already 4045 * be attached to the corresponding DRC. 4046 */ 4047 spapr_drc_attach(drc, dev); 4048 4049 if (hotplugged) { 4050 /* 4051 * Send hotplug notification interrupt to the guest only 4052 * in case of hotplugged CPUs. 4053 */ 4054 spapr_hotplug_req_add_by_index(drc); 4055 } else { 4056 spapr_drc_reset(drc); 4057 } 4058 } 4059 4060 core_slot->cpu = OBJECT(dev); 4061 4062 /* 4063 * Set compatibility mode to match the boot CPU, which was either set 4064 * by the machine reset code or by CAS. This really shouldn't fail at 4065 * this point. 4066 */ 4067 if (hotplugged) { 4068 for (i = 0; i < cc->nr_threads; i++) { 4069 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 4070 &error_abort); 4071 } 4072 } 4073 4074 if (smc->pre_2_10_has_unused_icps) { 4075 for (i = 0; i < cc->nr_threads; i++) { 4076 cs = CPU(core->threads[i]); 4077 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 4078 } 4079 } 4080 } 4081 4082 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4083 Error **errp) 4084 { 4085 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 4086 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 4087 CPUCore *cc = CPU_CORE(dev); 4088 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4089 const char *type = object_get_typename(OBJECT(dev)); 4090 CPUArchId *core_slot; 4091 int index; 4092 unsigned int smp_threads = machine->smp.threads; 4093 4094 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4095 error_setg(errp, "CPU hotplug not supported for this machine"); 4096 return; 4097 } 4098 4099 if (strcmp(base_core_type, type)) { 4100 error_setg(errp, "CPU core type should be %s", base_core_type); 4101 return; 4102 } 4103 4104 if (cc->core_id % smp_threads) { 4105 error_setg(errp, "invalid core id %d", cc->core_id); 4106 return; 4107 } 4108 4109 /* 4110 * In general we should have homogeneous threads-per-core, but old 4111 * (pre hotplug support) machine types allow the last core to have 4112 * reduced threads as a compatibility hack for when we allowed 4113 * total vcpus not a multiple of threads-per-core. 4114 */ 4115 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4116 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4117 smp_threads); 4118 return; 4119 } 4120 4121 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4122 if (!core_slot) { 4123 error_setg(errp, "core id %d out of range", cc->core_id); 4124 return; 4125 } 4126 4127 if (core_slot->cpu) { 4128 error_setg(errp, "core %d already populated", cc->core_id); 4129 return; 4130 } 4131 4132 numa_cpu_pre_plug(core_slot, dev, errp); 4133 } 4134 4135 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4136 void *fdt, int *fdt_start_offset, Error **errp) 4137 { 4138 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4139 int intc_phandle; 4140 4141 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4142 if (intc_phandle <= 0) { 4143 return -1; 4144 } 4145 4146 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4147 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4148 return -1; 4149 } 4150 4151 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4152 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4153 4154 return 0; 4155 } 4156 4157 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4158 Error **errp) 4159 { 4160 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4161 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4162 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4163 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4164 SpaprDrc *drc; 4165 4166 if (dev->hotplugged && !smc->dr_phb_enabled) { 4167 error_setg(errp, "PHB hotplug not supported for this machine"); 4168 return false; 4169 } 4170 4171 if (sphb->index == (uint32_t)-1) { 4172 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4173 return false; 4174 } 4175 4176 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4177 if (drc && drc->dev) { 4178 error_setg(errp, "PHB %d already attached", sphb->index); 4179 return false; 4180 } 4181 4182 /* 4183 * This will check that sphb->index doesn't exceed the maximum number of 4184 * PHBs for the current machine type. 4185 */ 4186 return 4187 smc->phb_placement(spapr, sphb->index, 4188 &sphb->buid, &sphb->io_win_addr, 4189 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4190 windows_supported, sphb->dma_liobn, 4191 errp); 4192 } 4193 4194 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4195 { 4196 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4197 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4198 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4199 SpaprDrc *drc; 4200 bool hotplugged = spapr_drc_hotplugged(dev); 4201 4202 if (!smc->dr_phb_enabled) { 4203 return; 4204 } 4205 4206 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4207 /* hotplug hooks should check it's enabled before getting this far */ 4208 assert(drc); 4209 4210 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4211 spapr_drc_attach(drc, dev); 4212 4213 if (hotplugged) { 4214 spapr_hotplug_req_add_by_index(drc); 4215 } else { 4216 spapr_drc_reset(drc); 4217 } 4218 } 4219 4220 void spapr_phb_release(DeviceState *dev) 4221 { 4222 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4223 4224 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4225 object_unparent(OBJECT(dev)); 4226 } 4227 4228 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4229 { 4230 qdev_unrealize(dev); 4231 } 4232 4233 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4234 DeviceState *dev, Error **errp) 4235 { 4236 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4237 SpaprDrc *drc; 4238 4239 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4240 assert(drc); 4241 4242 if (!spapr_drc_unplug_requested(drc)) { 4243 spapr_drc_unplug_request(drc); 4244 spapr_hotplug_req_remove_by_index(drc); 4245 } else { 4246 error_setg(errp, 4247 "PCI Host Bridge unplug already in progress for device %s", 4248 dev->id); 4249 } 4250 } 4251 4252 static 4253 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4254 Error **errp) 4255 { 4256 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4257 4258 if (spapr->tpm_proxy != NULL) { 4259 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4260 return false; 4261 } 4262 4263 return true; 4264 } 4265 4266 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4267 { 4268 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4269 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4270 4271 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4272 g_assert(spapr->tpm_proxy == NULL); 4273 4274 spapr->tpm_proxy = tpm_proxy; 4275 } 4276 4277 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4278 { 4279 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4280 4281 qdev_unrealize(dev); 4282 object_unparent(OBJECT(dev)); 4283 spapr->tpm_proxy = NULL; 4284 } 4285 4286 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4287 DeviceState *dev, Error **errp) 4288 { 4289 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4290 spapr_memory_plug(hotplug_dev, dev); 4291 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4292 spapr_core_plug(hotplug_dev, dev); 4293 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4294 spapr_phb_plug(hotplug_dev, dev); 4295 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4296 spapr_tpm_proxy_plug(hotplug_dev, dev); 4297 } 4298 } 4299 4300 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4301 DeviceState *dev, Error **errp) 4302 { 4303 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4304 spapr_memory_unplug(hotplug_dev, dev); 4305 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4306 spapr_core_unplug(hotplug_dev, dev); 4307 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4308 spapr_phb_unplug(hotplug_dev, dev); 4309 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4310 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4311 } 4312 } 4313 4314 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4315 { 4316 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4317 /* 4318 * CAS will process all pending unplug requests. 4319 * 4320 * HACK: a guest could theoretically have cleared all bits in OV5, 4321 * but none of the guests we care for do. 4322 */ 4323 spapr_ovec_empty(spapr->ov5_cas); 4324 } 4325 4326 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4327 DeviceState *dev, Error **errp) 4328 { 4329 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4330 MachineClass *mc = MACHINE_GET_CLASS(sms); 4331 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4332 4333 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4334 if (spapr_memory_hot_unplug_supported(sms)) { 4335 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4336 } else { 4337 error_setg(errp, "Memory hot unplug not supported for this guest"); 4338 } 4339 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4340 if (!mc->has_hotpluggable_cpus) { 4341 error_setg(errp, "CPU hot unplug not supported on this machine"); 4342 return; 4343 } 4344 spapr_core_unplug_request(hotplug_dev, dev, errp); 4345 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4346 if (!smc->dr_phb_enabled) { 4347 error_setg(errp, "PHB hot unplug not supported on this machine"); 4348 return; 4349 } 4350 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4351 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4352 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4353 } 4354 } 4355 4356 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4357 DeviceState *dev, Error **errp) 4358 { 4359 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4360 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4361 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4362 spapr_core_pre_plug(hotplug_dev, dev, errp); 4363 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4364 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4365 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4366 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4367 } 4368 } 4369 4370 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4371 DeviceState *dev) 4372 { 4373 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4374 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4375 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4376 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4377 return HOTPLUG_HANDLER(machine); 4378 } 4379 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4380 PCIDevice *pcidev = PCI_DEVICE(dev); 4381 PCIBus *root = pci_device_root_bus(pcidev); 4382 SpaprPhbState *phb = 4383 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4384 TYPE_SPAPR_PCI_HOST_BRIDGE); 4385 4386 if (phb) { 4387 return HOTPLUG_HANDLER(phb); 4388 } 4389 } 4390 return NULL; 4391 } 4392 4393 static CpuInstanceProperties 4394 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4395 { 4396 CPUArchId *core_slot; 4397 MachineClass *mc = MACHINE_GET_CLASS(machine); 4398 4399 /* make sure possible_cpu are initialized */ 4400 mc->possible_cpu_arch_ids(machine); 4401 /* get CPU core slot containing thread that matches cpu_index */ 4402 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4403 assert(core_slot); 4404 return core_slot->props; 4405 } 4406 4407 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4408 { 4409 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4410 } 4411 4412 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4413 { 4414 int i; 4415 unsigned int smp_threads = machine->smp.threads; 4416 unsigned int smp_cpus = machine->smp.cpus; 4417 const char *core_type; 4418 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4419 MachineClass *mc = MACHINE_GET_CLASS(machine); 4420 4421 if (!mc->has_hotpluggable_cpus) { 4422 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4423 } 4424 if (machine->possible_cpus) { 4425 assert(machine->possible_cpus->len == spapr_max_cores); 4426 return machine->possible_cpus; 4427 } 4428 4429 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4430 if (!core_type) { 4431 error_report("Unable to find sPAPR CPU Core definition"); 4432 exit(1); 4433 } 4434 4435 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4436 sizeof(CPUArchId) * spapr_max_cores); 4437 machine->possible_cpus->len = spapr_max_cores; 4438 for (i = 0; i < machine->possible_cpus->len; i++) { 4439 int core_id = i * smp_threads; 4440 4441 machine->possible_cpus->cpus[i].type = core_type; 4442 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4443 machine->possible_cpus->cpus[i].arch_id = core_id; 4444 machine->possible_cpus->cpus[i].props.has_core_id = true; 4445 machine->possible_cpus->cpus[i].props.core_id = core_id; 4446 } 4447 return machine->possible_cpus; 4448 } 4449 4450 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4451 uint64_t *buid, hwaddr *pio, 4452 hwaddr *mmio32, hwaddr *mmio64, 4453 unsigned n_dma, uint32_t *liobns, Error **errp) 4454 { 4455 /* 4456 * New-style PHB window placement. 4457 * 4458 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4459 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4460 * windows. 4461 * 4462 * Some guest kernels can't work with MMIO windows above 1<<46 4463 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4464 * 4465 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4466 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4467 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4468 * 1TiB 64-bit MMIO windows for each PHB. 4469 */ 4470 const uint64_t base_buid = 0x800000020000000ULL; 4471 int i; 4472 4473 /* Sanity check natural alignments */ 4474 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4475 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4476 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4477 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4478 /* Sanity check bounds */ 4479 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4480 SPAPR_PCI_MEM32_WIN_SIZE); 4481 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4482 SPAPR_PCI_MEM64_WIN_SIZE); 4483 4484 if (index >= SPAPR_MAX_PHBS) { 4485 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4486 SPAPR_MAX_PHBS - 1); 4487 return false; 4488 } 4489 4490 *buid = base_buid + index; 4491 for (i = 0; i < n_dma; ++i) { 4492 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4493 } 4494 4495 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4496 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4497 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4498 return true; 4499 } 4500 4501 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4502 { 4503 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4504 4505 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4506 } 4507 4508 static void spapr_ics_resend(XICSFabric *dev) 4509 { 4510 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4511 4512 ics_resend(spapr->ics); 4513 } 4514 4515 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4516 { 4517 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4518 4519 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4520 } 4521 4522 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4523 Monitor *mon) 4524 { 4525 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4526 4527 spapr_irq_print_info(spapr, mon); 4528 monitor_printf(mon, "irqchip: %s\n", 4529 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4530 } 4531 4532 /* 4533 * This is a XIVE only operation 4534 */ 4535 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4536 uint8_t nvt_blk, uint32_t nvt_idx, 4537 bool cam_ignore, uint8_t priority, 4538 uint32_t logic_serv, XiveTCTXMatch *match) 4539 { 4540 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4541 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4542 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4543 int count; 4544 4545 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4546 priority, logic_serv, match); 4547 if (count < 0) { 4548 return count; 4549 } 4550 4551 /* 4552 * When we implement the save and restore of the thread interrupt 4553 * contexts in the enter/exit CPU handlers of the machine and the 4554 * escalations in QEMU, we should be able to handle non dispatched 4555 * vCPUs. 4556 * 4557 * Until this is done, the sPAPR machine should find at least one 4558 * matching context always. 4559 */ 4560 if (count == 0) { 4561 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4562 nvt_blk, nvt_idx); 4563 } 4564 4565 return count; 4566 } 4567 4568 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4569 { 4570 return cpu->vcpu_id; 4571 } 4572 4573 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4574 { 4575 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4576 MachineState *ms = MACHINE(spapr); 4577 int vcpu_id; 4578 4579 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4580 4581 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4582 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4583 error_append_hint(errp, "Adjust the number of cpus to %d " 4584 "or try to raise the number of threads per core\n", 4585 vcpu_id * ms->smp.threads / spapr->vsmt); 4586 return false; 4587 } 4588 4589 cpu->vcpu_id = vcpu_id; 4590 return true; 4591 } 4592 4593 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4594 { 4595 CPUState *cs; 4596 4597 CPU_FOREACH(cs) { 4598 PowerPCCPU *cpu = POWERPC_CPU(cs); 4599 4600 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4601 return cpu; 4602 } 4603 } 4604 4605 return NULL; 4606 } 4607 4608 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4609 { 4610 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4611 4612 return spapr_cpu->in_nested; 4613 } 4614 4615 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4616 { 4617 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4618 4619 /* These are only called by TCG, KVM maintains dispatch state */ 4620 4621 spapr_cpu->prod = false; 4622 if (spapr_cpu->vpa_addr) { 4623 CPUState *cs = CPU(cpu); 4624 uint32_t dispatch; 4625 4626 dispatch = ldl_be_phys(cs->as, 4627 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4628 dispatch++; 4629 if ((dispatch & 1) != 0) { 4630 qemu_log_mask(LOG_GUEST_ERROR, 4631 "VPA: incorrect dispatch counter value for " 4632 "dispatched partition %u, correcting.\n", dispatch); 4633 dispatch++; 4634 } 4635 stl_be_phys(cs->as, 4636 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4637 } 4638 } 4639 4640 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4641 { 4642 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4643 4644 if (spapr_cpu->vpa_addr) { 4645 CPUState *cs = CPU(cpu); 4646 uint32_t dispatch; 4647 4648 dispatch = ldl_be_phys(cs->as, 4649 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4650 dispatch++; 4651 if ((dispatch & 1) != 1) { 4652 qemu_log_mask(LOG_GUEST_ERROR, 4653 "VPA: incorrect dispatch counter value for " 4654 "preempted partition %u, correcting.\n", dispatch); 4655 dispatch++; 4656 } 4657 stl_be_phys(cs->as, 4658 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4659 } 4660 } 4661 4662 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4663 { 4664 MachineClass *mc = MACHINE_CLASS(oc); 4665 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4666 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4667 NMIClass *nc = NMI_CLASS(oc); 4668 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4669 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4670 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4671 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4672 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4673 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4674 4675 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4676 mc->ignore_boot_device_suffixes = true; 4677 4678 /* 4679 * We set up the default / latest behaviour here. The class_init 4680 * functions for the specific versioned machine types can override 4681 * these details for backwards compatibility 4682 */ 4683 mc->init = spapr_machine_init; 4684 mc->reset = spapr_machine_reset; 4685 mc->block_default_type = IF_SCSI; 4686 4687 /* 4688 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4689 * In TCG the limit is restricted by the range of CPU IPIs available. 4690 */ 4691 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4692 4693 mc->no_parallel = 1; 4694 mc->default_boot_order = ""; 4695 mc->default_ram_size = 512 * MiB; 4696 mc->default_ram_id = "ppc_spapr.ram"; 4697 mc->default_display = "std"; 4698 mc->kvm_type = spapr_kvm_type; 4699 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4700 mc->pci_allow_0_address = true; 4701 assert(!mc->get_hotplug_handler); 4702 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4703 hc->pre_plug = spapr_machine_device_pre_plug; 4704 hc->plug = spapr_machine_device_plug; 4705 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4706 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4707 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4708 hc->unplug_request = spapr_machine_device_unplug_request; 4709 hc->unplug = spapr_machine_device_unplug; 4710 4711 smc->dr_lmb_enabled = true; 4712 smc->update_dt_enabled = true; 4713 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4714 mc->has_hotpluggable_cpus = true; 4715 mc->nvdimm_supported = true; 4716 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4717 fwc->get_dev_path = spapr_get_fw_dev_path; 4718 nc->nmi_monitor_handler = spapr_nmi; 4719 smc->phb_placement = spapr_phb_placement; 4720 vhc->cpu_in_nested = spapr_cpu_in_nested; 4721 vhc->deliver_hv_excp = spapr_exit_nested; 4722 vhc->hypercall = emulate_spapr_hypercall; 4723 vhc->hpt_mask = spapr_hpt_mask; 4724 vhc->map_hptes = spapr_map_hptes; 4725 vhc->unmap_hptes = spapr_unmap_hptes; 4726 vhc->hpte_set_c = spapr_hpte_set_c; 4727 vhc->hpte_set_r = spapr_hpte_set_r; 4728 vhc->get_pate = spapr_get_pate; 4729 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4730 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4731 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4732 xic->ics_get = spapr_ics_get; 4733 xic->ics_resend = spapr_ics_resend; 4734 xic->icp_get = spapr_icp_get; 4735 ispc->print_info = spapr_pic_print_info; 4736 /* Force NUMA node memory size to be a multiple of 4737 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4738 * in which LMBs are represented and hot-added 4739 */ 4740 mc->numa_mem_align_shift = 28; 4741 mc->auto_enable_numa = true; 4742 4743 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4744 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4745 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4746 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4747 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4748 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4749 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4750 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4751 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4752 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4753 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4754 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4755 4756 /* 4757 * This cap specifies whether the AIL 3 mode for 4758 * H_SET_RESOURCE is supported. The default is modified 4759 * by default_caps_with_cpu(). 4760 */ 4761 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4762 spapr_caps_add_properties(smc); 4763 smc->irq = &spapr_irq_dual; 4764 smc->dr_phb_enabled = true; 4765 smc->linux_pci_probe = true; 4766 smc->smp_threads_vsmt = true; 4767 smc->nr_xirqs = SPAPR_NR_XIRQS; 4768 xfc->match_nvt = spapr_match_nvt; 4769 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4770 vmc->quiesce = spapr_vof_quiesce; 4771 vmc->setprop = spapr_vof_setprop; 4772 } 4773 4774 static const TypeInfo spapr_machine_info = { 4775 .name = TYPE_SPAPR_MACHINE, 4776 .parent = TYPE_MACHINE, 4777 .abstract = true, 4778 .instance_size = sizeof(SpaprMachineState), 4779 .instance_init = spapr_instance_init, 4780 .instance_finalize = spapr_machine_finalizefn, 4781 .class_size = sizeof(SpaprMachineClass), 4782 .class_init = spapr_machine_class_init, 4783 .interfaces = (InterfaceInfo[]) { 4784 { TYPE_FW_PATH_PROVIDER }, 4785 { TYPE_NMI }, 4786 { TYPE_HOTPLUG_HANDLER }, 4787 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4788 { TYPE_XICS_FABRIC }, 4789 { TYPE_INTERRUPT_STATS_PROVIDER }, 4790 { TYPE_XIVE_FABRIC }, 4791 { TYPE_VOF_MACHINE_IF }, 4792 { } 4793 }, 4794 }; 4795 4796 static void spapr_machine_latest_class_options(MachineClass *mc) 4797 { 4798 mc->alias = "pseries"; 4799 mc->is_default = true; 4800 } 4801 4802 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4803 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4804 void *data) \ 4805 { \ 4806 MachineClass *mc = MACHINE_CLASS(oc); \ 4807 spapr_machine_##suffix##_class_options(mc); \ 4808 if (latest) { \ 4809 spapr_machine_latest_class_options(mc); \ 4810 } \ 4811 } \ 4812 static const TypeInfo spapr_machine_##suffix##_info = { \ 4813 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4814 .parent = TYPE_SPAPR_MACHINE, \ 4815 .class_init = spapr_machine_##suffix##_class_init, \ 4816 }; \ 4817 static void spapr_machine_register_##suffix(void) \ 4818 { \ 4819 type_register(&spapr_machine_##suffix##_info); \ 4820 } \ 4821 type_init(spapr_machine_register_##suffix) 4822 4823 /* 4824 * pseries-9.0 4825 */ 4826 static void spapr_machine_9_0_class_options(MachineClass *mc) 4827 { 4828 /* Defaults for the latest behaviour inherited from the base class */ 4829 } 4830 4831 DEFINE_SPAPR_MACHINE(9_0, "9.0", true); 4832 4833 /* 4834 * pseries-8.2 4835 */ 4836 static void spapr_machine_8_2_class_options(MachineClass *mc) 4837 { 4838 spapr_machine_9_0_class_options(mc); 4839 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4840 } 4841 4842 DEFINE_SPAPR_MACHINE(8_2, "8.2", false); 4843 4844 /* 4845 * pseries-8.1 4846 */ 4847 static void spapr_machine_8_1_class_options(MachineClass *mc) 4848 { 4849 spapr_machine_8_2_class_options(mc); 4850 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4851 } 4852 4853 DEFINE_SPAPR_MACHINE(8_1, "8.1", false); 4854 4855 /* 4856 * pseries-8.0 4857 */ 4858 static void spapr_machine_8_0_class_options(MachineClass *mc) 4859 { 4860 spapr_machine_8_1_class_options(mc); 4861 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4862 } 4863 4864 DEFINE_SPAPR_MACHINE(8_0, "8.0", false); 4865 4866 /* 4867 * pseries-7.2 4868 */ 4869 static void spapr_machine_7_2_class_options(MachineClass *mc) 4870 { 4871 spapr_machine_8_0_class_options(mc); 4872 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4873 } 4874 4875 DEFINE_SPAPR_MACHINE(7_2, "7.2", false); 4876 4877 /* 4878 * pseries-7.1 4879 */ 4880 static void spapr_machine_7_1_class_options(MachineClass *mc) 4881 { 4882 spapr_machine_7_2_class_options(mc); 4883 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4884 } 4885 4886 DEFINE_SPAPR_MACHINE(7_1, "7.1", false); 4887 4888 /* 4889 * pseries-7.0 4890 */ 4891 static void spapr_machine_7_0_class_options(MachineClass *mc) 4892 { 4893 spapr_machine_7_1_class_options(mc); 4894 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4895 } 4896 4897 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4898 4899 /* 4900 * pseries-6.2 4901 */ 4902 static void spapr_machine_6_2_class_options(MachineClass *mc) 4903 { 4904 spapr_machine_7_0_class_options(mc); 4905 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4906 } 4907 4908 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4909 4910 /* 4911 * pseries-6.1 4912 */ 4913 static void spapr_machine_6_1_class_options(MachineClass *mc) 4914 { 4915 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4916 4917 spapr_machine_6_2_class_options(mc); 4918 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4919 smc->pre_6_2_numa_affinity = true; 4920 mc->smp_props.prefer_sockets = true; 4921 } 4922 4923 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4924 4925 /* 4926 * pseries-6.0 4927 */ 4928 static void spapr_machine_6_0_class_options(MachineClass *mc) 4929 { 4930 spapr_machine_6_1_class_options(mc); 4931 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4932 } 4933 4934 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4935 4936 /* 4937 * pseries-5.2 4938 */ 4939 static void spapr_machine_5_2_class_options(MachineClass *mc) 4940 { 4941 spapr_machine_6_0_class_options(mc); 4942 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4943 } 4944 4945 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4946 4947 /* 4948 * pseries-5.1 4949 */ 4950 static void spapr_machine_5_1_class_options(MachineClass *mc) 4951 { 4952 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4953 4954 spapr_machine_5_2_class_options(mc); 4955 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4956 smc->pre_5_2_numa_associativity = true; 4957 } 4958 4959 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4960 4961 /* 4962 * pseries-5.0 4963 */ 4964 static void spapr_machine_5_0_class_options(MachineClass *mc) 4965 { 4966 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4967 static GlobalProperty compat[] = { 4968 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4969 }; 4970 4971 spapr_machine_5_1_class_options(mc); 4972 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4973 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4974 mc->numa_mem_supported = true; 4975 smc->pre_5_1_assoc_refpoints = true; 4976 } 4977 4978 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4979 4980 /* 4981 * pseries-4.2 4982 */ 4983 static void spapr_machine_4_2_class_options(MachineClass *mc) 4984 { 4985 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4986 4987 spapr_machine_5_0_class_options(mc); 4988 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4989 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4990 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4991 smc->rma_limit = 16 * GiB; 4992 mc->nvdimm_supported = false; 4993 } 4994 4995 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4996 4997 /* 4998 * pseries-4.1 4999 */ 5000 static void spapr_machine_4_1_class_options(MachineClass *mc) 5001 { 5002 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5003 static GlobalProperty compat[] = { 5004 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 5005 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 5006 }; 5007 5008 spapr_machine_4_2_class_options(mc); 5009 smc->linux_pci_probe = false; 5010 smc->smp_threads_vsmt = false; 5011 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 5012 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5013 } 5014 5015 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 5016 5017 /* 5018 * pseries-4.0 5019 */ 5020 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 5021 uint64_t *buid, hwaddr *pio, 5022 hwaddr *mmio32, hwaddr *mmio64, 5023 unsigned n_dma, uint32_t *liobns, Error **errp) 5024 { 5025 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 5026 liobns, errp)) { 5027 return false; 5028 } 5029 return true; 5030 } 5031 static void spapr_machine_4_0_class_options(MachineClass *mc) 5032 { 5033 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5034 5035 spapr_machine_4_1_class_options(mc); 5036 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 5037 smc->phb_placement = phb_placement_4_0; 5038 smc->irq = &spapr_irq_xics; 5039 smc->pre_4_1_migration = true; 5040 } 5041 5042 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 5043 5044 /* 5045 * pseries-3.1 5046 */ 5047 static void spapr_machine_3_1_class_options(MachineClass *mc) 5048 { 5049 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5050 5051 spapr_machine_4_0_class_options(mc); 5052 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 5053 5054 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 5055 smc->update_dt_enabled = false; 5056 smc->dr_phb_enabled = false; 5057 smc->broken_host_serial_model = true; 5058 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5059 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5060 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5061 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5062 } 5063 5064 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 5065 5066 /* 5067 * pseries-3.0 5068 */ 5069 5070 static void spapr_machine_3_0_class_options(MachineClass *mc) 5071 { 5072 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5073 5074 spapr_machine_3_1_class_options(mc); 5075 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5076 5077 smc->legacy_irq_allocation = true; 5078 smc->nr_xirqs = 0x400; 5079 smc->irq = &spapr_irq_xics_legacy; 5080 } 5081 5082 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 5083 5084 /* 5085 * pseries-2.12 5086 */ 5087 static void spapr_machine_2_12_class_options(MachineClass *mc) 5088 { 5089 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5090 static GlobalProperty compat[] = { 5091 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 5092 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 5093 }; 5094 5095 spapr_machine_3_0_class_options(mc); 5096 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 5097 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5098 5099 /* We depend on kvm_enabled() to choose a default value for the 5100 * hpt-max-page-size capability. Of course we can't do it here 5101 * because this is too early and the HW accelerator isn't initialized 5102 * yet. Postpone this to machine init (see default_caps_with_cpu()). 5103 */ 5104 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 5105 } 5106 5107 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 5108 5109 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 5110 { 5111 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5112 5113 spapr_machine_2_12_class_options(mc); 5114 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 5115 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 5116 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 5117 } 5118 5119 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 5120 5121 /* 5122 * pseries-2.11 5123 */ 5124 5125 static void spapr_machine_2_11_class_options(MachineClass *mc) 5126 { 5127 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5128 5129 spapr_machine_2_12_class_options(mc); 5130 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5131 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5132 mc->deprecation_reason = "old and not maintained - use a 2.12+ version"; 5133 } 5134 5135 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 5136 5137 /* 5138 * pseries-2.10 5139 */ 5140 5141 static void spapr_machine_2_10_class_options(MachineClass *mc) 5142 { 5143 spapr_machine_2_11_class_options(mc); 5144 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5145 } 5146 5147 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 5148 5149 /* 5150 * pseries-2.9 5151 */ 5152 5153 static void spapr_machine_2_9_class_options(MachineClass *mc) 5154 { 5155 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5156 static GlobalProperty compat[] = { 5157 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5158 }; 5159 5160 spapr_machine_2_10_class_options(mc); 5161 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5162 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5163 smc->pre_2_10_has_unused_icps = true; 5164 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5165 } 5166 5167 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5168 5169 /* 5170 * pseries-2.8 5171 */ 5172 5173 static void spapr_machine_2_8_class_options(MachineClass *mc) 5174 { 5175 static GlobalProperty compat[] = { 5176 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5177 }; 5178 5179 spapr_machine_2_9_class_options(mc); 5180 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5181 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5182 mc->numa_mem_align_shift = 23; 5183 } 5184 5185 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5186 5187 /* 5188 * pseries-2.7 5189 */ 5190 5191 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5192 uint64_t *buid, hwaddr *pio, 5193 hwaddr *mmio32, hwaddr *mmio64, 5194 unsigned n_dma, uint32_t *liobns, Error **errp) 5195 { 5196 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5197 const uint64_t base_buid = 0x800000020000000ULL; 5198 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5199 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5200 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5201 const uint32_t max_index = 255; 5202 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5203 5204 uint64_t ram_top = MACHINE(spapr)->ram_size; 5205 hwaddr phb0_base, phb_base; 5206 int i; 5207 5208 /* Do we have device memory? */ 5209 if (MACHINE(spapr)->device_memory) { 5210 /* Can't just use maxram_size, because there may be an 5211 * alignment gap between normal and device memory regions 5212 */ 5213 ram_top = MACHINE(spapr)->device_memory->base + 5214 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5215 } 5216 5217 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5218 5219 if (index > max_index) { 5220 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5221 max_index); 5222 return false; 5223 } 5224 5225 *buid = base_buid + index; 5226 for (i = 0; i < n_dma; ++i) { 5227 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5228 } 5229 5230 phb_base = phb0_base + index * phb_spacing; 5231 *pio = phb_base + pio_offset; 5232 *mmio32 = phb_base + mmio_offset; 5233 /* 5234 * We don't set the 64-bit MMIO window, relying on the PHB's 5235 * fallback behaviour of automatically splitting a large "32-bit" 5236 * window into contiguous 32-bit and 64-bit windows 5237 */ 5238 5239 return true; 5240 } 5241 5242 static void spapr_machine_2_7_class_options(MachineClass *mc) 5243 { 5244 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5245 static GlobalProperty compat[] = { 5246 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5247 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5248 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5249 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5250 }; 5251 5252 spapr_machine_2_8_class_options(mc); 5253 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5254 mc->default_machine_opts = "modern-hotplug-events=off"; 5255 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5256 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5257 smc->phb_placement = phb_placement_2_7; 5258 } 5259 5260 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5261 5262 /* 5263 * pseries-2.6 5264 */ 5265 5266 static void spapr_machine_2_6_class_options(MachineClass *mc) 5267 { 5268 static GlobalProperty compat[] = { 5269 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5270 }; 5271 5272 spapr_machine_2_7_class_options(mc); 5273 mc->has_hotpluggable_cpus = false; 5274 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5275 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5276 } 5277 5278 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5279 5280 /* 5281 * pseries-2.5 5282 */ 5283 5284 static void spapr_machine_2_5_class_options(MachineClass *mc) 5285 { 5286 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5287 static GlobalProperty compat[] = { 5288 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5289 }; 5290 5291 spapr_machine_2_6_class_options(mc); 5292 smc->use_ohci_by_default = true; 5293 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5294 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5295 } 5296 5297 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5298 5299 /* 5300 * pseries-2.4 5301 */ 5302 5303 static void spapr_machine_2_4_class_options(MachineClass *mc) 5304 { 5305 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5306 5307 spapr_machine_2_5_class_options(mc); 5308 smc->dr_lmb_enabled = false; 5309 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5310 } 5311 5312 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5313 5314 /* 5315 * pseries-2.3 5316 */ 5317 5318 static void spapr_machine_2_3_class_options(MachineClass *mc) 5319 { 5320 static GlobalProperty compat[] = { 5321 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5322 }; 5323 spapr_machine_2_4_class_options(mc); 5324 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5325 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5326 } 5327 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5328 5329 /* 5330 * pseries-2.2 5331 */ 5332 5333 static void spapr_machine_2_2_class_options(MachineClass *mc) 5334 { 5335 static GlobalProperty compat[] = { 5336 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5337 }; 5338 5339 spapr_machine_2_3_class_options(mc); 5340 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5341 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5342 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5343 } 5344 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5345 5346 /* 5347 * pseries-2.1 5348 */ 5349 5350 static void spapr_machine_2_1_class_options(MachineClass *mc) 5351 { 5352 spapr_machine_2_2_class_options(mc); 5353 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5354 } 5355 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5356 5357 static void spapr_machine_register_types(void) 5358 { 5359 type_register_static(&spapr_machine_info); 5360 } 5361 5362 type_init(spapr_machine_register_types) 5363