1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * Copyright (c) 2010-2024, IBM Corporation.. 8 * 9 * SPDX-License-Identifier: GPL-2.0-or-later 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a copy 12 * of this software and associated documentation files (the "Software"), to deal 13 * in the Software without restriction, including without limitation the rights 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 * copies of the Software, and to permit persons to whom the Software is 16 * furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 * THE SOFTWARE. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "qemu/datadir.h" 32 #include "qemu/memalign.h" 33 #include "qemu/guest-random.h" 34 #include "qapi/error.h" 35 #include "qapi/qapi-events-machine.h" 36 #include "qapi/qapi-events-qdev.h" 37 #include "qapi/visitor.h" 38 #include "system/system.h" 39 #include "system/hostmem.h" 40 #include "system/numa.h" 41 #include "system/tcg.h" 42 #include "system/qtest.h" 43 #include "system/reset.h" 44 #include "system/runstate.h" 45 #include "qemu/log.h" 46 #include "hw/fw-path-provider.h" 47 #include "elf.h" 48 #include "net/net.h" 49 #include "system/device_tree.h" 50 #include "system/cpus.h" 51 #include "system/hw_accel.h" 52 #include "kvm_ppc.h" 53 #include "migration/misc.h" 54 #include "migration/qemu-file-types.h" 55 #include "migration/global_state.h" 56 #include "migration/register.h" 57 #include "migration/blocker.h" 58 #include "mmu-hash64.h" 59 #include "mmu-book3s-v3.h" 60 #include "cpu-models.h" 61 #include "hw/core/cpu.h" 62 63 #include "hw/ppc/ppc.h" 64 #include "hw/loader.h" 65 66 #include "hw/ppc/fdt.h" 67 #include "hw/ppc/spapr.h" 68 #include "hw/ppc/spapr_nested.h" 69 #include "hw/ppc/spapr_vio.h" 70 #include "hw/ppc/vof.h" 71 #include "hw/qdev-properties.h" 72 #include "hw/pci-host/spapr.h" 73 #include "hw/pci/msi.h" 74 75 #include "hw/pci/pci.h" 76 #include "hw/scsi/scsi.h" 77 #include "hw/virtio/virtio-scsi.h" 78 #include "hw/virtio/vhost-scsi-common.h" 79 80 #include "exec/ram_addr.h" 81 #include "system/confidential-guest-support.h" 82 #include "hw/usb.h" 83 #include "qemu/config-file.h" 84 #include "qemu/error-report.h" 85 #include "trace.h" 86 #include "hw/nmi.h" 87 #include "hw/intc/intc.h" 88 89 #include "hw/ppc/spapr_cpu_core.h" 90 #include "hw/mem/memory-device.h" 91 #include "hw/ppc/spapr_tpm_proxy.h" 92 #include "hw/ppc/spapr_nvdimm.h" 93 #include "hw/ppc/spapr_numa.h" 94 95 #include <libfdt.h> 96 97 /* SLOF memory layout: 98 * 99 * SLOF raw image loaded at 0, copies its romfs right below the flat 100 * device-tree, then position SLOF itself 31M below that 101 * 102 * So we set FW_OVERHEAD to 40MB which should account for all of that 103 * and more 104 * 105 * We load our kernel at 4M, leaving space for SLOF initial image 106 */ 107 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 108 #define FW_MAX_SIZE 0x400000 109 #define FW_FILE_NAME "slof.bin" 110 #define FW_FILE_NAME_VOF "vof.bin" 111 #define FW_OVERHEAD 0x2800000 112 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 113 114 #define MIN_RMA_SLOF (128 * MiB) 115 116 #define PHANDLE_INTC 0x00001111 117 118 /* These two functions implement the VCPU id numbering: one to compute them 119 * all and one to identify thread 0 of a VCORE. Any change to the first one 120 * is likely to have an impact on the second one, so let's keep them close. 121 */ 122 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 123 { 124 MachineState *ms = MACHINE(spapr); 125 unsigned int smp_threads = ms->smp.threads; 126 127 assert(spapr->vsmt); 128 return 129 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 130 } 131 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 132 PowerPCCPU *cpu) 133 { 134 assert(spapr->vsmt); 135 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 136 } 137 138 int spapr_max_server_number(SpaprMachineState *spapr) 139 { 140 MachineState *ms = MACHINE(spapr); 141 142 assert(spapr->vsmt); 143 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 144 } 145 146 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 147 int smt_threads) 148 { 149 int i, ret = 0; 150 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 151 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 152 int index = spapr_get_vcpu_id(cpu); 153 154 if (cpu->compat_pvr) { 155 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 156 if (ret < 0) { 157 return ret; 158 } 159 } 160 161 /* Build interrupt servers and gservers properties */ 162 for (i = 0; i < smt_threads; i++) { 163 servers_prop[i] = cpu_to_be32(index + i); 164 /* Hack, direct the group queues back to cpu 0 */ 165 gservers_prop[i*2] = cpu_to_be32(index + i); 166 gservers_prop[i*2 + 1] = 0; 167 } 168 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 169 servers_prop, sizeof(*servers_prop) * smt_threads); 170 if (ret < 0) { 171 return ret; 172 } 173 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 174 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 175 176 return ret; 177 } 178 179 static void spapr_dt_pa_features(SpaprMachineState *spapr, 180 PowerPCCPU *cpu, 181 void *fdt, int offset) 182 { 183 /* 184 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 185 * but not MTTCG, so disable it. To advertise it, a cap would have 186 * to be added, or support implemented for MTTCG. 187 * 188 * Copy/paste is not supported by TCG, so it is not advertised. KVM 189 * can execute them but it has no accelerator drivers which are usable, 190 * so there isn't much need for it anyway. 191 */ 192 193 /* These should be kept in sync with pnv */ 194 uint8_t pa_features_206[] = { 6, 0, 195 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 196 uint8_t pa_features_207[] = { 24, 0, 197 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 198 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 199 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 200 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 201 uint8_t pa_features_300[] = { 66, 0, 202 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 203 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 204 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 205 /* 6: DS207 */ 206 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 207 /* 16: Vector */ 208 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 209 /* 18: Vec. Scalar, 20: Vec. XOR */ 210 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 211 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 212 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 213 /* 32: LE atomic, 34: EBB + ext EBB */ 214 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 215 /* 40: Radix MMU */ 216 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 217 /* 42: PM, 44: PC RA, 46: SC vec'd */ 218 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 219 /* 48: SIMD, 50: QP BFP, 52: String */ 220 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 221 /* 54: DecFP, 56: DecI, 58: SHA */ 222 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 223 /* 60: NM atomic, 62: RNG */ 224 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 225 }; 226 /* 3.1 removes SAO, HTM support */ 227 uint8_t pa_features_31[] = { 74, 0, 228 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 229 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 230 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 231 /* 6: DS207 */ 232 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 233 /* 16: Vector */ 234 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 235 /* 18: Vec. Scalar, 20: Vec. XOR */ 236 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 237 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 239 /* 32: LE atomic, 34: EBB + ext EBB */ 240 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 241 /* 40: Radix MMU */ 242 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 243 /* 42: PM, 44: PC RA, 46: SC vec'd */ 244 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 245 /* 48: SIMD, 50: QP BFP, 52: String */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 247 /* 54: DecFP, 56: DecI, 58: SHA */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 249 /* 60: NM atomic, 62: RNG */ 250 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 251 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 252 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 253 /* 72: [P]HASHST/[P]HASHCHK */ 254 0x80, 0x00, /* 72 - 73 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) { 272 pa_features = pa_features_31; 273 pa_size = sizeof(pa_features_31); 274 } 275 if (!pa_features) { 276 return; 277 } 278 279 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 280 /* 281 * Note: we keep CI large pages off by default because a 64K capable 282 * guest provisioned with large pages might otherwise try to map a qemu 283 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 284 * even if that qemu runs on a 4k host. 285 * We dd this bit back here if we are confident this is not an issue 286 */ 287 pa_features[3] |= 0x20; 288 } 289 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 290 pa_features[24] |= 0x80; /* Transactional memory support */ 291 } 292 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 293 /* Workaround for broken kernels that attempt (guest) radix 294 * mode when they can't handle it, if they see the radix bit set 295 * in pa-features. So hide it from them. */ 296 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 297 } 298 299 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 300 } 301 302 static void spapr_dt_pi_features(SpaprMachineState *spapr, 303 PowerPCCPU *cpu, 304 void *fdt, int offset) 305 { 306 uint8_t pi_features[] = { 1, 0, 307 0x00 }; 308 309 if (kvm_enabled() && ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 310 0, cpu->compat_pvr)) { 311 /* 312 * POWER9 and later CPUs with KVM run in LPAR-per-thread mode where 313 * all threads are essentially independent CPUs, and msgsndp does not 314 * work (because it is physically-addressed) and therefore is 315 * emulated by KVM, so disable it here to ensure XIVE will be used. 316 * This is both KVM and CPU implementation-specific behaviour so a KVM 317 * cap would be cleanest, but for now this works. If KVM ever permits 318 * native msgsndp execution by guests, a cap could be added at that 319 * time. 320 */ 321 pi_features[2] |= 0x08; /* 4: No msgsndp */ 322 } 323 324 _FDT((fdt_setprop(fdt, offset, "ibm,pi-features", pi_features, 325 sizeof(pi_features)))); 326 } 327 328 static hwaddr spapr_node0_size(MachineState *machine) 329 { 330 if (machine->numa_state->num_nodes) { 331 int i; 332 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 333 if (machine->numa_state->nodes[i].node_mem) { 334 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 335 machine->ram_size); 336 } 337 } 338 } 339 return machine->ram_size; 340 } 341 342 static void add_str(GString *s, const gchar *s1) 343 { 344 g_string_append_len(s, s1, strlen(s1) + 1); 345 } 346 347 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 348 hwaddr start, hwaddr size) 349 { 350 char mem_name[32]; 351 uint64_t mem_reg_property[2]; 352 int off; 353 354 mem_reg_property[0] = cpu_to_be64(start); 355 mem_reg_property[1] = cpu_to_be64(size); 356 357 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 358 off = fdt_add_subnode(fdt, 0, mem_name); 359 _FDT(off); 360 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 361 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 362 sizeof(mem_reg_property)))); 363 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 364 return off; 365 } 366 367 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 368 { 369 MemoryDeviceInfoList *info; 370 371 for (info = list; info; info = info->next) { 372 MemoryDeviceInfo *value = info->value; 373 374 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 375 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 376 377 if (addr >= pcdimm_info->addr && 378 addr < (pcdimm_info->addr + pcdimm_info->size)) { 379 return pcdimm_info->node; 380 } 381 } 382 } 383 384 return -1; 385 } 386 387 struct sPAPRDrconfCellV2 { 388 uint32_t seq_lmbs; 389 uint64_t base_addr; 390 uint32_t drc_index; 391 uint32_t aa_index; 392 uint32_t flags; 393 } QEMU_PACKED; 394 395 typedef struct DrconfCellQueue { 396 struct sPAPRDrconfCellV2 cell; 397 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 398 } DrconfCellQueue; 399 400 static DrconfCellQueue * 401 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 402 uint32_t drc_index, uint32_t aa_index, 403 uint32_t flags) 404 { 405 DrconfCellQueue *elem; 406 407 elem = g_malloc0(sizeof(*elem)); 408 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 409 elem->cell.base_addr = cpu_to_be64(base_addr); 410 elem->cell.drc_index = cpu_to_be32(drc_index); 411 elem->cell.aa_index = cpu_to_be32(aa_index); 412 elem->cell.flags = cpu_to_be32(flags); 413 414 return elem; 415 } 416 417 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 418 int offset, MemoryDeviceInfoList *dimms) 419 { 420 MachineState *machine = MACHINE(spapr); 421 uint8_t *int_buf, *cur_index; 422 int ret; 423 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 424 uint64_t addr, cur_addr, size; 425 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 426 uint64_t mem_end = machine->device_memory->base + 427 memory_region_size(&machine->device_memory->mr); 428 uint32_t node, buf_len, nr_entries = 0; 429 SpaprDrc *drc; 430 DrconfCellQueue *elem, *next; 431 MemoryDeviceInfoList *info; 432 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 433 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 434 435 /* Entry to cover RAM and the gap area */ 436 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 437 SPAPR_LMB_FLAGS_RESERVED | 438 SPAPR_LMB_FLAGS_DRC_INVALID); 439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 440 nr_entries++; 441 442 cur_addr = machine->device_memory->base; 443 for (info = dimms; info; info = info->next) { 444 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 445 446 addr = di->addr; 447 size = di->size; 448 node = di->node; 449 450 /* 451 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 452 * area is marked hotpluggable in the next iteration for the bigger 453 * chunk including the NVDIMM occupied area. 454 */ 455 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 456 continue; 457 458 /* Entry for hot-pluggable area */ 459 if (cur_addr < addr) { 460 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 461 g_assert(drc); 462 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 463 cur_addr, spapr_drc_index(drc), -1, 0); 464 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 465 nr_entries++; 466 } 467 468 /* Entry for DIMM */ 469 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 470 g_assert(drc); 471 elem = spapr_get_drconf_cell(size / lmb_size, addr, 472 spapr_drc_index(drc), node, 473 (SPAPR_LMB_FLAGS_ASSIGNED | 474 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 475 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 476 nr_entries++; 477 cur_addr = addr + size; 478 } 479 480 /* Entry for remaining hotpluggable area */ 481 if (cur_addr < mem_end) { 482 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 483 g_assert(drc); 484 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 485 cur_addr, spapr_drc_index(drc), -1, 0); 486 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 487 nr_entries++; 488 } 489 490 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 491 int_buf = cur_index = g_malloc0(buf_len); 492 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 493 cur_index += sizeof(nr_entries); 494 495 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 496 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 497 cur_index += sizeof(elem->cell); 498 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 499 g_free(elem); 500 } 501 502 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 503 g_free(int_buf); 504 if (ret < 0) { 505 return -1; 506 } 507 return 0; 508 } 509 510 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 511 int offset, MemoryDeviceInfoList *dimms) 512 { 513 MachineState *machine = MACHINE(spapr); 514 int i, ret; 515 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 516 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 517 uint32_t nr_lmbs = (machine->device_memory->base + 518 memory_region_size(&machine->device_memory->mr)) / 519 lmb_size; 520 uint32_t *int_buf, *cur_index, buf_len; 521 522 /* 523 * Allocate enough buffer size to fit in ibm,dynamic-memory 524 */ 525 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 526 cur_index = int_buf = g_malloc0(buf_len); 527 int_buf[0] = cpu_to_be32(nr_lmbs); 528 cur_index++; 529 for (i = 0; i < nr_lmbs; i++) { 530 uint64_t addr = i * lmb_size; 531 uint32_t *dynamic_memory = cur_index; 532 533 if (i >= device_lmb_start) { 534 SpaprDrc *drc; 535 536 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 537 g_assert(drc); 538 539 dynamic_memory[0] = cpu_to_be32(addr >> 32); 540 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 541 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 542 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 543 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 544 if (memory_region_present(get_system_memory(), addr)) { 545 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 546 } else { 547 dynamic_memory[5] = cpu_to_be32(0); 548 } 549 } else { 550 /* 551 * LMB information for RMA, boot time RAM and gap b/n RAM and 552 * device memory region -- all these are marked as reserved 553 * and as having no valid DRC. 554 */ 555 dynamic_memory[0] = cpu_to_be32(addr >> 32); 556 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 557 dynamic_memory[2] = cpu_to_be32(0); 558 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 559 dynamic_memory[4] = cpu_to_be32(-1); 560 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 561 SPAPR_LMB_FLAGS_DRC_INVALID); 562 } 563 564 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 565 } 566 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 567 g_free(int_buf); 568 if (ret < 0) { 569 return -1; 570 } 571 return 0; 572 } 573 574 /* 575 * Adds ibm,dynamic-reconfiguration-memory node. 576 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 577 * of this device tree node. 578 */ 579 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 580 void *fdt) 581 { 582 MachineState *machine = MACHINE(spapr); 583 int ret, offset; 584 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 585 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 586 cpu_to_be32(lmb_size & 0xffffffff)}; 587 MemoryDeviceInfoList *dimms = NULL; 588 589 /* Don't create the node if there is no device memory. */ 590 if (!machine->device_memory) { 591 return 0; 592 } 593 594 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 595 596 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 597 sizeof(prop_lmb_size)); 598 if (ret < 0) { 599 return ret; 600 } 601 602 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 603 if (ret < 0) { 604 return ret; 605 } 606 607 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 608 if (ret < 0) { 609 return ret; 610 } 611 612 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 613 dimms = qmp_memory_device_list(); 614 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 615 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 616 } else { 617 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 618 } 619 qapi_free_MemoryDeviceInfoList(dimms); 620 621 if (ret < 0) { 622 return ret; 623 } 624 625 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 626 627 return ret; 628 } 629 630 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 631 { 632 MachineState *machine = MACHINE(spapr); 633 hwaddr mem_start, node_size; 634 int i, nb_nodes = machine->numa_state->num_nodes; 635 NodeInfo *nodes = machine->numa_state->nodes; 636 637 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 638 if (!nodes[i].node_mem) { 639 continue; 640 } 641 if (mem_start >= machine->ram_size) { 642 node_size = 0; 643 } else { 644 node_size = nodes[i].node_mem; 645 if (node_size > machine->ram_size - mem_start) { 646 node_size = machine->ram_size - mem_start; 647 } 648 } 649 if (!mem_start) { 650 /* spapr_machine_init() checks for rma_size <= node0_size 651 * already */ 652 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 653 mem_start += spapr->rma_size; 654 node_size -= spapr->rma_size; 655 } 656 for ( ; node_size; ) { 657 hwaddr sizetmp = pow2floor(node_size); 658 659 /* mem_start != 0 here */ 660 if (ctzl(mem_start) < ctzl(sizetmp)) { 661 sizetmp = 1ULL << ctzl(mem_start); 662 } 663 664 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 665 node_size -= sizetmp; 666 mem_start += sizetmp; 667 } 668 } 669 670 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 671 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 672 int ret; 673 674 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 675 if (ret) { 676 return ret; 677 } 678 } 679 680 return 0; 681 } 682 683 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 684 SpaprMachineState *spapr) 685 { 686 MachineState *ms = MACHINE(spapr); 687 PowerPCCPU *cpu = POWERPC_CPU(cs); 688 CPUPPCState *env = &cpu->env; 689 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 690 int index = spapr_get_vcpu_id(cpu); 691 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 692 0xffffffff, 0xffffffff}; 693 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 694 : SPAPR_TIMEBASE_FREQ; 695 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 696 uint32_t page_sizes_prop[64]; 697 size_t page_sizes_prop_size; 698 unsigned int smp_threads = ms->smp.threads; 699 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 700 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 701 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 702 SpaprDrc *drc; 703 int drc_index; 704 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 705 int i; 706 707 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, env->core_index); 708 if (drc) { 709 drc_index = spapr_drc_index(drc); 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 711 } 712 713 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 714 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 715 716 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 717 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 718 env->dcache_line_size))); 719 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 720 env->dcache_line_size))); 721 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 722 env->icache_line_size))); 723 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 724 env->icache_line_size))); 725 726 if (pcc->l1_dcache_size) { 727 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 728 pcc->l1_dcache_size))); 729 } else { 730 warn_report("Unknown L1 dcache size for cpu"); 731 } 732 if (pcc->l1_icache_size) { 733 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 734 pcc->l1_icache_size))); 735 } else { 736 warn_report("Unknown L1 icache size for cpu"); 737 } 738 739 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 740 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 741 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 742 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 743 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 744 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 745 746 if (ppc_has_spr(cpu, SPR_PURR)) { 747 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 748 } 749 if (ppc_has_spr(cpu, SPR_PURR)) { 750 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 751 } 752 753 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 754 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 755 segs, sizeof(segs)))); 756 } 757 758 /* Advertise VSX (vector extensions) if available 759 * 1 == VMX / Altivec available 760 * 2 == VSX available 761 * 762 * Only CPUs for which we create core types in spapr_cpu_core.c 763 * are possible, and all of those have VMX */ 764 if (env->insns_flags & PPC_ALTIVEC) { 765 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 767 } else { 768 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 769 } 770 } 771 772 /* Advertise DFP (Decimal Floating Point) if available 773 * 0 / no property == no DFP 774 * 1 == DFP available */ 775 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 776 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 777 } 778 779 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 780 sizeof(page_sizes_prop)); 781 if (page_sizes_prop_size) { 782 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 783 page_sizes_prop, page_sizes_prop_size))); 784 } 785 786 spapr_dt_pa_features(spapr, cpu, fdt, offset); 787 788 spapr_dt_pi_features(spapr, cpu, fdt, offset); 789 790 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 791 cs->cpu_index / vcpus_per_socket))); 792 793 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 794 pft_size_prop, sizeof(pft_size_prop)))); 795 796 if (ms->numa_state->num_nodes > 1) { 797 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 798 } 799 800 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 801 802 if (pcc->radix_page_info) { 803 for (i = 0; i < pcc->radix_page_info->count; i++) { 804 radix_AP_encodings[i] = 805 cpu_to_be32(pcc->radix_page_info->entries[i]); 806 } 807 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 808 radix_AP_encodings, 809 pcc->radix_page_info->count * 810 sizeof(radix_AP_encodings[0])))); 811 } 812 813 /* 814 * We set this property to let the guest know that it can use the large 815 * decrementer and its width in bits. 816 */ 817 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 818 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 819 pcc->lrg_decr_bits))); 820 } 821 822 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 823 int cpus_offset) 824 { 825 PowerPCCPU *cpu = POWERPC_CPU(cs); 826 int index = spapr_get_vcpu_id(cpu); 827 DeviceClass *dc = DEVICE_GET_CLASS(cs); 828 g_autofree char *nodename = NULL; 829 int offset; 830 831 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 832 return; 833 } 834 835 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 836 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 837 _FDT(offset); 838 spapr_dt_cpu(cs, fdt, offset, spapr); 839 } 840 841 842 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 843 { 844 CPUState **rev; 845 CPUState *cs; 846 int n_cpus; 847 int cpus_offset; 848 int i; 849 850 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 851 _FDT(cpus_offset); 852 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 853 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 854 855 /* 856 * We walk the CPUs in reverse order to ensure that CPU DT nodes 857 * created by fdt_add_subnode() end up in the right order in FDT 858 * for the guest kernel the enumerate the CPUs correctly. 859 * 860 * The CPU list cannot be traversed in reverse order, so we need 861 * to do extra work. 862 */ 863 n_cpus = 0; 864 rev = NULL; 865 CPU_FOREACH(cs) { 866 rev = g_renew(CPUState *, rev, n_cpus + 1); 867 rev[n_cpus++] = cs; 868 } 869 870 for (i = n_cpus - 1; i >= 0; i--) { 871 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 872 } 873 874 g_free(rev); 875 } 876 877 static int spapr_dt_rng(void *fdt) 878 { 879 int node; 880 int ret; 881 882 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 883 if (node <= 0) { 884 return -1; 885 } 886 ret = fdt_setprop_string(fdt, node, "device_type", 887 "ibm,platform-facilities"); 888 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 889 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 890 891 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 892 if (node <= 0) { 893 return -1; 894 } 895 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 896 897 return ret ? -1 : 0; 898 } 899 900 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 901 { 902 MachineState *ms = MACHINE(spapr); 903 int rtas; 904 GString *hypertas = g_string_sized_new(256); 905 GString *qemu_hypertas = g_string_sized_new(256); 906 uint32_t lrdr_capacity[] = { 907 0, 908 0, 909 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 910 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 911 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 912 }; 913 914 /* Do we have device memory? */ 915 if (MACHINE(spapr)->device_memory) { 916 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 917 memory_region_size(&MACHINE(spapr)->device_memory->mr); 918 919 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 920 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 921 } 922 923 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 924 925 /* hypertas */ 926 add_str(hypertas, "hcall-pft"); 927 add_str(hypertas, "hcall-term"); 928 add_str(hypertas, "hcall-dabr"); 929 add_str(hypertas, "hcall-interrupt"); 930 add_str(hypertas, "hcall-tce"); 931 add_str(hypertas, "hcall-vio"); 932 add_str(hypertas, "hcall-splpar"); 933 add_str(hypertas, "hcall-join"); 934 add_str(hypertas, "hcall-bulk"); 935 add_str(hypertas, "hcall-set-mode"); 936 add_str(hypertas, "hcall-sprg0"); 937 add_str(hypertas, "hcall-copy"); 938 add_str(hypertas, "hcall-debug"); 939 add_str(hypertas, "hcall-vphn"); 940 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 941 add_str(hypertas, "hcall-rpt-invalidate"); 942 } 943 944 add_str(qemu_hypertas, "hcall-memop1"); 945 946 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 947 add_str(hypertas, "hcall-multi-tce"); 948 } 949 950 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 951 add_str(hypertas, "hcall-hpt-resize"); 952 } 953 954 add_str(hypertas, "hcall-watchdog"); 955 956 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 957 hypertas->str, hypertas->len)); 958 g_string_free(hypertas, TRUE); 959 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 960 qemu_hypertas->str, qemu_hypertas->len)); 961 g_string_free(qemu_hypertas, TRUE); 962 963 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 964 965 /* 966 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 967 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 968 * 969 * The system reset requirements are driven by existing Linux and PowerVM 970 * implementation which (contrary to PAPR) saves r3 in the error log 971 * structure like machine check, so Linux expects to find the saved r3 972 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 973 * does not look at the error value). 974 * 975 * System reset interrupts are not subject to interlock like machine 976 * check, so this memory area could be corrupted if the sreset is 977 * interrupted by a machine check (or vice versa) if it was shared. To 978 * prevent this, system reset uses per-CPU areas for the sreset save 979 * area. A system reset that interrupts a system reset handler could 980 * still overwrite this area, but Linux doesn't try to recover in that 981 * case anyway. 982 * 983 * The extra 8 bytes is required because Linux's FWNMI error log check 984 * is off-by-one. 985 * 986 * RTAS_MIN_SIZE is required for the RTAS blob itself. 987 */ 988 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 989 RTAS_ERROR_LOG_MAX + 990 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 991 sizeof(uint64_t))); 992 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 993 RTAS_ERROR_LOG_MAX)); 994 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 995 RTAS_EVENT_SCAN_RATE)); 996 997 g_assert(msi_nonbroken); 998 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 999 1000 /* 1001 * According to PAPR, rtas ibm,os-term does not guarantee a return 1002 * back to the guest cpu. 1003 * 1004 * While an additional ibm,extended-os-term property indicates 1005 * that rtas call return will always occur. Set this property. 1006 */ 1007 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1008 1009 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1010 lrdr_capacity, sizeof(lrdr_capacity))); 1011 1012 spapr_dt_rtas_tokens(fdt, rtas); 1013 } 1014 1015 /* 1016 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1017 * and the XIVE features that the guest may request and thus the valid 1018 * values for bytes 23..26 of option vector 5: 1019 */ 1020 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1021 int chosen) 1022 { 1023 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1024 1025 char val[2 * 4] = { 1026 23, 0x00, /* XICS / XIVE mode */ 1027 24, 0x00, /* Hash/Radix, filled in below. */ 1028 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1029 26, 0x40, /* Radix options: GTSE == yes. */ 1030 }; 1031 1032 if (spapr->irq->xics && spapr->irq->xive) { 1033 val[1] = SPAPR_OV5_XIVE_BOTH; 1034 } else if (spapr->irq->xive) { 1035 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1036 } else { 1037 assert(spapr->irq->xics); 1038 val[1] = SPAPR_OV5_XIVE_LEGACY; 1039 } 1040 1041 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1042 first_ppc_cpu->compat_pvr)) { 1043 /* 1044 * If we're in a pre POWER9 compat mode then the guest should 1045 * do hash and use the legacy interrupt mode 1046 */ 1047 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1048 val[3] = 0x00; /* Hash */ 1049 spapr_check_mmu_mode(false); 1050 } else if (kvm_enabled()) { 1051 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1052 val[3] = 0x80; /* OV5_MMU_BOTH */ 1053 } else if (kvmppc_has_cap_mmu_radix()) { 1054 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1055 } else { 1056 val[3] = 0x00; /* Hash */ 1057 } 1058 } else { 1059 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1060 val[3] = 0xC0; 1061 } 1062 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1063 val, sizeof(val))); 1064 } 1065 1066 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1067 { 1068 MachineState *machine = MACHINE(spapr); 1069 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1070 int chosen; 1071 1072 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1073 1074 if (reset) { 1075 const char *boot_device = spapr->boot_device; 1076 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1077 size_t cb = 0; 1078 g_autofree char *bootlist = get_boot_devices_list(&cb); 1079 1080 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1081 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1082 machine->kernel_cmdline)); 1083 } 1084 1085 if (spapr->initrd_size) { 1086 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1087 spapr->initrd_base)); 1088 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1089 spapr->initrd_base + spapr->initrd_size)); 1090 } 1091 1092 if (spapr->kernel_size) { 1093 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1094 cpu_to_be64(spapr->kernel_size) }; 1095 1096 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1097 &kprop, sizeof(kprop))); 1098 if (spapr->kernel_le) { 1099 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1100 } 1101 } 1102 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1103 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1104 } 1105 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1106 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1107 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1108 1109 if (cb && bootlist) { 1110 int i; 1111 1112 for (i = 0; i < cb; i++) { 1113 if (bootlist[i] == '\n') { 1114 bootlist[i] = ' '; 1115 } 1116 } 1117 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1118 } 1119 1120 if (boot_device && strlen(boot_device)) { 1121 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1122 } 1123 1124 if (spapr->want_stdout_path && stdout_path) { 1125 /* 1126 * "linux,stdout-path" and "stdout" properties are 1127 * deprecated by linux kernel. New platforms should only 1128 * use the "stdout-path" property. Set the new property 1129 * and continue using older property to remain compatible 1130 * with the existing firmware. 1131 */ 1132 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1133 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1134 } 1135 1136 /* 1137 * We can deal with BAR reallocation just fine, advertise it 1138 * to the guest 1139 */ 1140 if (smc->linux_pci_probe) { 1141 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1142 } 1143 1144 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1145 } 1146 1147 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1148 1149 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1150 } 1151 1152 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1153 { 1154 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1155 * KVM to work under pHyp with some guest co-operation */ 1156 int hypervisor; 1157 uint8_t hypercall[16]; 1158 1159 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1160 /* indicate KVM hypercall interface */ 1161 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1162 if (kvmppc_has_cap_fixup_hcalls()) { 1163 /* 1164 * Older KVM versions with older guest kernels were broken 1165 * with the magic page, don't allow the guest to map it. 1166 */ 1167 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1168 sizeof(hypercall))) { 1169 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1170 hypercall, sizeof(hypercall))); 1171 } 1172 } 1173 } 1174 1175 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1176 { 1177 MachineState *machine = MACHINE(spapr); 1178 MachineClass *mc = MACHINE_GET_CLASS(machine); 1179 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1180 uint32_t root_drc_type_mask = 0; 1181 int ret; 1182 void *fdt; 1183 SpaprPhbState *phb; 1184 char *buf; 1185 1186 fdt = g_malloc0(space); 1187 _FDT((fdt_create_empty_tree(fdt, space))); 1188 1189 /* Root node */ 1190 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1191 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1192 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1193 1194 /* Guest UUID & Name*/ 1195 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1196 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1197 if (qemu_uuid_set) { 1198 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1199 } 1200 g_free(buf); 1201 1202 if (qemu_get_vm_name()) { 1203 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1204 qemu_get_vm_name())); 1205 } 1206 1207 /* Host Model & Serial Number */ 1208 if (spapr->host_model) { 1209 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1210 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1211 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1212 g_free(buf); 1213 } 1214 1215 if (spapr->host_serial) { 1216 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1217 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1218 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1219 g_free(buf); 1220 } 1221 1222 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1223 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1224 1225 /* /interrupt controller */ 1226 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1227 1228 ret = spapr_dt_memory(spapr, fdt); 1229 if (ret < 0) { 1230 error_report("couldn't setup memory nodes in fdt"); 1231 exit(1); 1232 } 1233 1234 /* /vdevice */ 1235 spapr_dt_vdevice(spapr->vio_bus, fdt); 1236 1237 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1238 ret = spapr_dt_rng(fdt); 1239 if (ret < 0) { 1240 error_report("could not set up rng device in the fdt"); 1241 exit(1); 1242 } 1243 } 1244 1245 QLIST_FOREACH(phb, &spapr->phbs, list) { 1246 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1247 if (ret < 0) { 1248 error_report("couldn't setup PCI devices in fdt"); 1249 exit(1); 1250 } 1251 } 1252 1253 spapr_dt_cpus(fdt, spapr); 1254 1255 /* ibm,drc-indexes and friends */ 1256 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1257 if (smc->dr_phb_enabled) { 1258 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1259 } 1260 if (mc->nvdimm_supported) { 1261 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1262 } 1263 if (root_drc_type_mask) { 1264 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1265 } 1266 1267 if (mc->has_hotpluggable_cpus) { 1268 int offset = fdt_path_offset(fdt, "/cpus"); 1269 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1270 if (ret < 0) { 1271 error_report("Couldn't set up CPU DR device tree properties"); 1272 exit(1); 1273 } 1274 } 1275 1276 /* /event-sources */ 1277 spapr_dt_events(spapr, fdt); 1278 1279 /* /rtas */ 1280 spapr_dt_rtas(spapr, fdt); 1281 1282 /* /chosen */ 1283 spapr_dt_chosen(spapr, fdt, reset); 1284 1285 /* /hypervisor */ 1286 if (kvm_enabled()) { 1287 spapr_dt_hypervisor(spapr, fdt); 1288 } 1289 1290 /* Build memory reserve map */ 1291 if (reset) { 1292 if (spapr->kernel_size) { 1293 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1294 spapr->kernel_size))); 1295 } 1296 if (spapr->initrd_size) { 1297 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1298 spapr->initrd_size))); 1299 } 1300 } 1301 1302 /* NVDIMM devices */ 1303 if (mc->nvdimm_supported) { 1304 spapr_dt_persistent_memory(spapr, fdt); 1305 } 1306 1307 return fdt; 1308 } 1309 1310 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1311 { 1312 SpaprMachineState *spapr = opaque; 1313 1314 return (addr & 0x0fffffff) + spapr->kernel_addr; 1315 } 1316 1317 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1318 PowerPCCPU *cpu) 1319 { 1320 CPUPPCState *env = &cpu->env; 1321 1322 /* The TCG path should also be holding the BQL at this point */ 1323 g_assert(bql_locked()); 1324 1325 g_assert(!vhyp_cpu_in_nested(cpu)); 1326 1327 if (FIELD_EX64(env->msr, MSR, PR)) { 1328 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1329 env->gpr[3] = H_PRIVILEGE; 1330 } else { 1331 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1332 } 1333 } 1334 1335 struct LPCRSyncState { 1336 target_ulong value; 1337 target_ulong mask; 1338 }; 1339 1340 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1341 { 1342 struct LPCRSyncState *s = arg.host_ptr; 1343 PowerPCCPU *cpu = POWERPC_CPU(cs); 1344 CPUPPCState *env = &cpu->env; 1345 target_ulong lpcr; 1346 1347 cpu_synchronize_state(cs); 1348 lpcr = env->spr[SPR_LPCR]; 1349 lpcr &= ~s->mask; 1350 lpcr |= s->value; 1351 ppc_store_lpcr(cpu, lpcr); 1352 } 1353 1354 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1355 { 1356 CPUState *cs; 1357 struct LPCRSyncState s = { 1358 .value = value, 1359 .mask = mask 1360 }; 1361 CPU_FOREACH(cs) { 1362 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1363 } 1364 } 1365 1366 /* May be used when the machine is not running */ 1367 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1368 { 1369 CPUState *cs; 1370 CPU_FOREACH(cs) { 1371 PowerPCCPU *cpu = POWERPC_CPU(cs); 1372 CPUPPCState *env = &cpu->env; 1373 target_ulong lpcr; 1374 1375 lpcr = env->spr[SPR_LPCR]; 1376 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1377 ppc_store_lpcr(cpu, lpcr); 1378 } 1379 } 1380 1381 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1382 target_ulong lpid, ppc_v3_pate_t *entry) 1383 { 1384 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1385 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1386 1387 if (!spapr_cpu->in_nested) { 1388 assert(lpid == 0); 1389 1390 /* Copy PATE1:GR into PATE0:HR */ 1391 entry->dw0 = spapr->patb_entry & PATE0_HR; 1392 entry->dw1 = spapr->patb_entry; 1393 return true; 1394 } else { 1395 if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) { 1396 return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); 1397 } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) { 1398 return spapr_get_pate_nested_papr(spapr, cpu, lpid, entry); 1399 } else { 1400 g_assert_not_reached(); 1401 } 1402 } 1403 } 1404 1405 static uint64_t *hpte_get_ptr(SpaprMachineState *s, unsigned index) 1406 { 1407 uint64_t *table = s->htab; 1408 1409 return &table[2 * index]; 1410 } 1411 1412 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1413 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1414 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1415 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1416 1417 /* 1418 * Get the fd to access the kernel htab, re-opening it if necessary 1419 */ 1420 static int get_htab_fd(SpaprMachineState *spapr) 1421 { 1422 Error *local_err = NULL; 1423 1424 if (spapr->htab_fd >= 0) { 1425 return spapr->htab_fd; 1426 } 1427 1428 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1429 if (spapr->htab_fd < 0) { 1430 error_report_err(local_err); 1431 } 1432 1433 return spapr->htab_fd; 1434 } 1435 1436 void close_htab_fd(SpaprMachineState *spapr) 1437 { 1438 if (spapr->htab_fd >= 0) { 1439 close(spapr->htab_fd); 1440 } 1441 spapr->htab_fd = -1; 1442 } 1443 1444 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1445 { 1446 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1447 1448 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1449 } 1450 1451 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1452 { 1453 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1454 1455 assert(kvm_enabled()); 1456 1457 if (!spapr->htab) { 1458 return 0; 1459 } 1460 1461 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1462 } 1463 1464 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1465 hwaddr ptex, int n) 1466 { 1467 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1468 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1469 1470 if (!spapr->htab) { 1471 /* 1472 * HTAB is controlled by KVM. Fetch into temporary buffer 1473 */ 1474 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1475 kvmppc_read_hptes(hptes, ptex, n); 1476 return hptes; 1477 } 1478 1479 /* 1480 * HTAB is controlled by QEMU. Just point to the internally 1481 * accessible PTEG. 1482 */ 1483 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1484 } 1485 1486 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1487 const ppc_hash_pte64_t *hptes, 1488 hwaddr ptex, int n) 1489 { 1490 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1491 1492 if (!spapr->htab) { 1493 g_free((void *)hptes); 1494 } 1495 1496 /* Nothing to do for qemu managed HPT */ 1497 } 1498 1499 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1500 uint64_t pte0, uint64_t pte1) 1501 { 1502 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1503 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1504 1505 if (!spapr->htab) { 1506 kvmppc_write_hpte(ptex, pte0, pte1); 1507 } else { 1508 if (pte0 & HPTE64_V_VALID) { 1509 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1510 /* 1511 * When setting valid, we write PTE1 first. This ensures 1512 * proper synchronization with the reading code in 1513 * ppc_hash64_pteg_search() 1514 */ 1515 smp_wmb(); 1516 stq_p(spapr->htab + offset, pte0); 1517 } else { 1518 stq_p(spapr->htab + offset, pte0); 1519 /* 1520 * When clearing it we set PTE0 first. This ensures proper 1521 * synchronization with the reading code in 1522 * ppc_hash64_pteg_search() 1523 */ 1524 smp_wmb(); 1525 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1526 } 1527 } 1528 } 1529 1530 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1531 uint64_t pte1) 1532 { 1533 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1534 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1535 1536 if (!spapr->htab) { 1537 /* There should always be a hash table when this is called */ 1538 error_report("spapr_hpte_set_c called with no hash table !"); 1539 return; 1540 } 1541 1542 /* The HW performs a non-atomic byte update */ 1543 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1544 } 1545 1546 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1547 uint64_t pte1) 1548 { 1549 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1550 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1551 1552 if (!spapr->htab) { 1553 /* There should always be a hash table when this is called */ 1554 error_report("spapr_hpte_set_r called with no hash table !"); 1555 return; 1556 } 1557 1558 /* The HW performs a non-atomic byte update */ 1559 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1560 } 1561 1562 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1563 { 1564 int shift; 1565 1566 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1567 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1568 * that's much more than is needed for Linux guests */ 1569 shift = ctz64(pow2ceil(ramsize)) - 7; 1570 shift = MAX(shift, 18); /* Minimum architected size */ 1571 shift = MIN(shift, 46); /* Maximum architected size */ 1572 return shift; 1573 } 1574 1575 void spapr_free_hpt(SpaprMachineState *spapr) 1576 { 1577 qemu_vfree(spapr->htab); 1578 spapr->htab = NULL; 1579 spapr->htab_shift = 0; 1580 close_htab_fd(spapr); 1581 } 1582 1583 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1584 { 1585 ERRP_GUARD(); 1586 long rc; 1587 1588 /* Clean up any HPT info from a previous boot */ 1589 spapr_free_hpt(spapr); 1590 1591 rc = kvmppc_reset_htab(shift); 1592 1593 if (rc == -EOPNOTSUPP) { 1594 error_setg(errp, "HPT not supported in nested guests"); 1595 return -EOPNOTSUPP; 1596 } 1597 1598 if (rc < 0) { 1599 /* kernel-side HPT needed, but couldn't allocate one */ 1600 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1601 shift); 1602 error_append_hint(errp, "Try smaller maxmem?\n"); 1603 return -errno; 1604 } else if (rc > 0) { 1605 /* kernel-side HPT allocated */ 1606 if (rc != shift) { 1607 error_setg(errp, 1608 "Requested order %d HPT, but kernel allocated order %ld", 1609 shift, rc); 1610 error_append_hint(errp, "Try smaller maxmem?\n"); 1611 return -ENOSPC; 1612 } 1613 1614 spapr->htab_shift = shift; 1615 spapr->htab = NULL; 1616 } else { 1617 /* kernel-side HPT not needed, allocate in userspace instead */ 1618 size_t size = 1ULL << shift; 1619 int i; 1620 1621 spapr->htab = qemu_memalign(size, size); 1622 memset(spapr->htab, 0, size); 1623 spapr->htab_shift = shift; 1624 1625 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1626 DIRTY_HPTE(hpte_get_ptr(spapr, i)); 1627 } 1628 } 1629 /* We're setting up a hash table, so that means we're not radix */ 1630 spapr->patb_entry = 0; 1631 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1632 return 0; 1633 } 1634 1635 void spapr_setup_hpt(SpaprMachineState *spapr) 1636 { 1637 int hpt_shift; 1638 1639 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1640 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1641 } else { 1642 uint64_t current_ram_size; 1643 1644 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1645 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1646 } 1647 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1648 1649 if (kvm_enabled()) { 1650 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1651 1652 /* Check our RMA fits in the possible VRMA */ 1653 if (vrma_limit < spapr->rma_size) { 1654 error_report("Unable to create %" HWADDR_PRIu 1655 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1656 spapr->rma_size / MiB, vrma_limit / MiB); 1657 exit(EXIT_FAILURE); 1658 } 1659 } 1660 } 1661 1662 void spapr_check_mmu_mode(bool guest_radix) 1663 { 1664 if (guest_radix) { 1665 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1666 error_report("Guest requested unavailable MMU mode (radix)."); 1667 exit(EXIT_FAILURE); 1668 } 1669 } else { 1670 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1671 && !kvmppc_has_cap_mmu_hash_v3()) { 1672 error_report("Guest requested unavailable MMU mode (hash)."); 1673 exit(EXIT_FAILURE); 1674 } 1675 } 1676 } 1677 1678 static void spapr_machine_reset(MachineState *machine, ResetType type) 1679 { 1680 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1681 PowerPCCPU *first_ppc_cpu; 1682 hwaddr fdt_addr; 1683 void *fdt; 1684 int rc; 1685 1686 if (type != RESET_TYPE_SNAPSHOT_LOAD) { 1687 /* 1688 * Record-replay snapshot load must not consume random, this was 1689 * already replayed from initial machine reset. 1690 */ 1691 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1692 } 1693 1694 if (machine->cgs) { 1695 confidential_guest_kvm_reset(machine->cgs, &error_fatal); 1696 } 1697 spapr_caps_apply(spapr); 1698 spapr_nested_reset(spapr); 1699 1700 first_ppc_cpu = POWERPC_CPU(first_cpu); 1701 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1702 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1703 spapr->max_compat_pvr)) { 1704 /* 1705 * If using KVM with radix mode available, VCPUs can be started 1706 * without a HPT because KVM will start them in radix mode. 1707 * Set the GR bit in PATE so that we know there is no HPT. 1708 */ 1709 spapr->patb_entry = PATE1_GR; 1710 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1711 } else { 1712 spapr_setup_hpt(spapr); 1713 } 1714 1715 qemu_devices_reset(type); 1716 1717 spapr_ovec_cleanup(spapr->ov5_cas); 1718 spapr->ov5_cas = spapr_ovec_new(); 1719 1720 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1721 1722 /* 1723 * This is fixing some of the default configuration of the XIVE 1724 * devices. To be called after the reset of the machine devices. 1725 */ 1726 spapr_irq_reset(spapr, &error_fatal); 1727 1728 /* 1729 * There is no CAS under qtest. Simulate one to please the code that 1730 * depends on spapr->ov5_cas. This is especially needed to test device 1731 * unplug, so we do that before resetting the DRCs. 1732 */ 1733 if (qtest_enabled()) { 1734 spapr_ovec_cleanup(spapr->ov5_cas); 1735 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1736 } 1737 1738 spapr_nvdimm_finish_flushes(); 1739 1740 /* DRC reset may cause a device to be unplugged. This will cause troubles 1741 * if this device is used by another device (eg, a running vhost backend 1742 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1743 * situations, we reset DRCs after all devices have been reset. 1744 */ 1745 spapr_drc_reset_all(spapr); 1746 1747 spapr_clear_pending_events(spapr); 1748 1749 /* 1750 * We place the device tree just below either the top of the RMA, 1751 * or just below 2GB, whichever is lower, so that it can be 1752 * processed with 32-bit real mode code if necessary 1753 */ 1754 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1755 1756 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1757 if (spapr->vof) { 1758 spapr_vof_reset(spapr, fdt, &error_fatal); 1759 /* 1760 * Do not pack the FDT as the client may change properties. 1761 * VOF client does not expect the FDT so we do not load it to the VM. 1762 */ 1763 } else { 1764 rc = fdt_pack(fdt); 1765 /* Should only fail if we've built a corrupted tree */ 1766 assert(rc == 0); 1767 1768 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1769 0, fdt_addr, 0); 1770 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1771 } 1772 1773 g_free(spapr->fdt_blob); 1774 spapr->fdt_size = fdt_totalsize(fdt); 1775 spapr->fdt_initial_size = spapr->fdt_size; 1776 spapr->fdt_blob = fdt; 1777 1778 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1779 machine->fdt = fdt; 1780 1781 /* Set up the entry state */ 1782 first_ppc_cpu->env.gpr[5] = 0; 1783 1784 spapr->fwnmi_system_reset_addr = -1; 1785 spapr->fwnmi_machine_check_addr = -1; 1786 spapr->fwnmi_machine_check_interlock = -1; 1787 1788 /* Signal all vCPUs waiting on this condition */ 1789 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1790 1791 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1792 } 1793 1794 static void spapr_create_nvram(SpaprMachineState *spapr) 1795 { 1796 DeviceState *dev = qdev_new("spapr-nvram"); 1797 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1798 1799 if (dinfo) { 1800 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1801 &error_fatal); 1802 } 1803 1804 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1805 1806 spapr->nvram = (struct SpaprNvram *)dev; 1807 } 1808 1809 static void spapr_rtc_create(SpaprMachineState *spapr) 1810 { 1811 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1812 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1813 &error_fatal, NULL); 1814 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1815 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1816 "date"); 1817 } 1818 1819 /* Returns whether we want to use VGA or not */ 1820 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1821 { 1822 vga_interface_created = true; 1823 switch (vga_interface_type) { 1824 case VGA_NONE: 1825 return false; 1826 case VGA_DEVICE: 1827 return true; 1828 case VGA_STD: 1829 case VGA_VIRTIO: 1830 case VGA_CIRRUS: 1831 return pci_vga_init(pci_bus) != NULL; 1832 default: 1833 error_setg(errp, 1834 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1835 return false; 1836 } 1837 } 1838 1839 static int spapr_pre_load(void *opaque) 1840 { 1841 int rc; 1842 1843 rc = spapr_caps_pre_load(opaque); 1844 if (rc) { 1845 return rc; 1846 } 1847 1848 return 0; 1849 } 1850 1851 static int spapr_post_load(void *opaque, int version_id) 1852 { 1853 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1854 int err = 0; 1855 1856 err = spapr_caps_post_migration(spapr); 1857 if (err) { 1858 return err; 1859 } 1860 1861 /* 1862 * In earlier versions, there was no separate qdev for the PAPR 1863 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1864 * So when migrating from those versions, poke the incoming offset 1865 * value into the RTC device 1866 */ 1867 if (version_id < 3) { 1868 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1869 if (err) { 1870 return err; 1871 } 1872 } 1873 1874 if (kvm_enabled() && spapr->patb_entry) { 1875 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1876 bool radix = !!(spapr->patb_entry & PATE1_GR); 1877 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1878 1879 /* 1880 * Update LPCR:HR and UPRT as they may not be set properly in 1881 * the stream 1882 */ 1883 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1884 LPCR_HR | LPCR_UPRT); 1885 1886 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1887 if (err) { 1888 error_report("Process table config unsupported by the host"); 1889 return -EINVAL; 1890 } 1891 } 1892 1893 err = spapr_irq_post_load(spapr, version_id); 1894 if (err) { 1895 return err; 1896 } 1897 1898 return err; 1899 } 1900 1901 static int spapr_pre_save(void *opaque) 1902 { 1903 int rc; 1904 1905 rc = spapr_caps_pre_save(opaque); 1906 if (rc) { 1907 return rc; 1908 } 1909 1910 return 0; 1911 } 1912 1913 static bool version_before_3(void *opaque, int version_id) 1914 { 1915 return version_id < 3; 1916 } 1917 1918 static bool spapr_pending_events_needed(void *opaque) 1919 { 1920 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1921 return !QTAILQ_EMPTY(&spapr->pending_events); 1922 } 1923 1924 static const VMStateDescription vmstate_spapr_event_entry = { 1925 .name = "spapr_event_log_entry", 1926 .version_id = 1, 1927 .minimum_version_id = 1, 1928 .fields = (const VMStateField[]) { 1929 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1930 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1931 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1932 NULL, extended_length), 1933 VMSTATE_END_OF_LIST() 1934 }, 1935 }; 1936 1937 static const VMStateDescription vmstate_spapr_pending_events = { 1938 .name = "spapr_pending_events", 1939 .version_id = 1, 1940 .minimum_version_id = 1, 1941 .needed = spapr_pending_events_needed, 1942 .fields = (const VMStateField[]) { 1943 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1944 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1945 VMSTATE_END_OF_LIST() 1946 }, 1947 }; 1948 1949 static bool spapr_ov5_cas_needed(void *opaque) 1950 { 1951 SpaprMachineState *spapr = opaque; 1952 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1953 bool cas_needed; 1954 1955 /* Prior to the introduction of SpaprOptionVector, we had two option 1956 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1957 * Both of these options encode machine topology into the device-tree 1958 * in such a way that the now-booted OS should still be able to interact 1959 * appropriately with QEMU regardless of what options were actually 1960 * negotiatied on the source side. 1961 * 1962 * As such, we can avoid migrating the CAS-negotiated options if these 1963 * are the only options available on the current machine/platform. 1964 * Since these are the only options available for pseries-2.7 and 1965 * earlier, this allows us to maintain old->new/new->old migration 1966 * compatibility. 1967 * 1968 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1969 * via default pseries-2.8 machines and explicit command-line parameters. 1970 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1971 * of the actual CAS-negotiated values to continue working properly. For 1972 * example, availability of memory unplug depends on knowing whether 1973 * OV5_HP_EVT was negotiated via CAS. 1974 * 1975 * Thus, for any cases where the set of available CAS-negotiatable 1976 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1977 * include the CAS-negotiated options in the migration stream, unless 1978 * if they affect boot time behaviour only. 1979 */ 1980 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1981 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1982 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1983 1984 /* We need extra information if we have any bits outside the mask 1985 * defined above */ 1986 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1987 1988 spapr_ovec_cleanup(ov5_mask); 1989 1990 return cas_needed; 1991 } 1992 1993 static const VMStateDescription vmstate_spapr_ov5_cas = { 1994 .name = "spapr_option_vector_ov5_cas", 1995 .version_id = 1, 1996 .minimum_version_id = 1, 1997 .needed = spapr_ov5_cas_needed, 1998 .fields = (const VMStateField[]) { 1999 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 2000 vmstate_spapr_ovec, SpaprOptionVector), 2001 VMSTATE_END_OF_LIST() 2002 }, 2003 }; 2004 2005 static bool spapr_patb_entry_needed(void *opaque) 2006 { 2007 SpaprMachineState *spapr = opaque; 2008 2009 return !!spapr->patb_entry; 2010 } 2011 2012 static const VMStateDescription vmstate_spapr_patb_entry = { 2013 .name = "spapr_patb_entry", 2014 .version_id = 1, 2015 .minimum_version_id = 1, 2016 .needed = spapr_patb_entry_needed, 2017 .fields = (const VMStateField[]) { 2018 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2019 VMSTATE_END_OF_LIST() 2020 }, 2021 }; 2022 2023 static bool spapr_irq_map_needed(void *opaque) 2024 { 2025 SpaprMachineState *spapr = opaque; 2026 2027 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2028 } 2029 2030 static const VMStateDescription vmstate_spapr_irq_map = { 2031 .name = "spapr_irq_map", 2032 .version_id = 1, 2033 .minimum_version_id = 1, 2034 .needed = spapr_irq_map_needed, 2035 .fields = (const VMStateField[]) { 2036 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2037 VMSTATE_END_OF_LIST() 2038 }, 2039 }; 2040 2041 static bool spapr_dtb_needed(void *opaque) 2042 { 2043 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2044 2045 return smc->update_dt_enabled; 2046 } 2047 2048 static int spapr_dtb_pre_load(void *opaque) 2049 { 2050 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2051 2052 g_free(spapr->fdt_blob); 2053 spapr->fdt_blob = NULL; 2054 spapr->fdt_size = 0; 2055 2056 return 0; 2057 } 2058 2059 static const VMStateDescription vmstate_spapr_dtb = { 2060 .name = "spapr_dtb", 2061 .version_id = 1, 2062 .minimum_version_id = 1, 2063 .needed = spapr_dtb_needed, 2064 .pre_load = spapr_dtb_pre_load, 2065 .fields = (const VMStateField[]) { 2066 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2067 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2068 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2069 fdt_size), 2070 VMSTATE_END_OF_LIST() 2071 }, 2072 }; 2073 2074 static bool spapr_fwnmi_needed(void *opaque) 2075 { 2076 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2077 2078 return spapr->fwnmi_machine_check_addr != -1; 2079 } 2080 2081 static int spapr_fwnmi_pre_save(void *opaque) 2082 { 2083 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2084 2085 /* 2086 * Check if machine check handling is in progress and print a 2087 * warning message. 2088 */ 2089 if (spapr->fwnmi_machine_check_interlock != -1) { 2090 warn_report("A machine check is being handled during migration. The" 2091 "handler may run and log hardware error on the destination"); 2092 } 2093 2094 return 0; 2095 } 2096 2097 static const VMStateDescription vmstate_spapr_fwnmi = { 2098 .name = "spapr_fwnmi", 2099 .version_id = 1, 2100 .minimum_version_id = 1, 2101 .needed = spapr_fwnmi_needed, 2102 .pre_save = spapr_fwnmi_pre_save, 2103 .fields = (const VMStateField[]) { 2104 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2105 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2106 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2107 VMSTATE_END_OF_LIST() 2108 }, 2109 }; 2110 2111 static const VMStateDescription vmstate_spapr = { 2112 .name = "spapr", 2113 .version_id = 3, 2114 .minimum_version_id = 1, 2115 .pre_load = spapr_pre_load, 2116 .post_load = spapr_post_load, 2117 .pre_save = spapr_pre_save, 2118 .fields = (const VMStateField[]) { 2119 /* used to be @next_irq */ 2120 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2121 2122 /* RTC offset */ 2123 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2124 2125 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2126 VMSTATE_END_OF_LIST() 2127 }, 2128 .subsections = (const VMStateDescription * const []) { 2129 &vmstate_spapr_ov5_cas, 2130 &vmstate_spapr_patb_entry, 2131 &vmstate_spapr_pending_events, 2132 &vmstate_spapr_cap_htm, 2133 &vmstate_spapr_cap_vsx, 2134 &vmstate_spapr_cap_dfp, 2135 &vmstate_spapr_cap_cfpc, 2136 &vmstate_spapr_cap_sbbc, 2137 &vmstate_spapr_cap_ibs, 2138 &vmstate_spapr_cap_hpt_maxpagesize, 2139 &vmstate_spapr_irq_map, 2140 &vmstate_spapr_cap_nested_kvm_hv, 2141 &vmstate_spapr_dtb, 2142 &vmstate_spapr_cap_large_decr, 2143 &vmstate_spapr_cap_ccf_assist, 2144 &vmstate_spapr_cap_fwnmi, 2145 &vmstate_spapr_fwnmi, 2146 &vmstate_spapr_cap_rpt_invalidate, 2147 &vmstate_spapr_cap_ail_mode_3, 2148 &vmstate_spapr_cap_nested_papr, 2149 NULL 2150 } 2151 }; 2152 2153 static int htab_save_setup(QEMUFile *f, void *opaque, Error **errp) 2154 { 2155 SpaprMachineState *spapr = opaque; 2156 2157 /* "Iteration" header */ 2158 if (!spapr->htab_shift) { 2159 qemu_put_be32(f, -1); 2160 } else { 2161 qemu_put_be32(f, spapr->htab_shift); 2162 } 2163 2164 if (spapr->htab) { 2165 spapr->htab_save_index = 0; 2166 spapr->htab_first_pass = true; 2167 } else { 2168 if (spapr->htab_shift) { 2169 assert(kvm_enabled()); 2170 } 2171 } 2172 2173 2174 return 0; 2175 } 2176 2177 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2178 int chunkstart, int n_valid, int n_invalid) 2179 { 2180 qemu_put_be32(f, chunkstart); 2181 qemu_put_be16(f, n_valid); 2182 qemu_put_be16(f, n_invalid); 2183 qemu_put_buffer(f, (void *)hpte_get_ptr(spapr, chunkstart), 2184 HASH_PTE_SIZE_64 * n_valid); 2185 } 2186 2187 static void htab_save_end_marker(QEMUFile *f) 2188 { 2189 qemu_put_be32(f, 0); 2190 qemu_put_be16(f, 0); 2191 qemu_put_be16(f, 0); 2192 } 2193 2194 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2195 int64_t max_ns) 2196 { 2197 bool has_timeout = max_ns != -1; 2198 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2199 int index = spapr->htab_save_index; 2200 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2201 2202 assert(spapr->htab_first_pass); 2203 2204 do { 2205 int chunkstart; 2206 2207 /* Consume invalid HPTEs */ 2208 while ((index < htabslots) 2209 && !HPTE_VALID(hpte_get_ptr(spapr, index))) { 2210 CLEAN_HPTE(hpte_get_ptr(spapr, index)); 2211 index++; 2212 } 2213 2214 /* Consume valid HPTEs */ 2215 chunkstart = index; 2216 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2217 && HPTE_VALID(hpte_get_ptr(spapr, index))) { 2218 CLEAN_HPTE(hpte_get_ptr(spapr, index)); 2219 index++; 2220 } 2221 2222 if (index > chunkstart) { 2223 int n_valid = index - chunkstart; 2224 2225 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2226 2227 if (has_timeout && 2228 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2229 break; 2230 } 2231 } 2232 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2233 2234 if (index >= htabslots) { 2235 assert(index == htabslots); 2236 index = 0; 2237 spapr->htab_first_pass = false; 2238 } 2239 spapr->htab_save_index = index; 2240 } 2241 2242 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2243 int64_t max_ns) 2244 { 2245 bool final = max_ns < 0; 2246 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2247 int examined = 0, sent = 0; 2248 int index = spapr->htab_save_index; 2249 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2250 2251 assert(!spapr->htab_first_pass); 2252 2253 do { 2254 int chunkstart, invalidstart; 2255 2256 /* Consume non-dirty HPTEs */ 2257 while ((index < htabslots) 2258 && !HPTE_DIRTY(hpte_get_ptr(spapr, index))) { 2259 index++; 2260 examined++; 2261 } 2262 2263 chunkstart = index; 2264 /* Consume valid dirty HPTEs */ 2265 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2266 && HPTE_DIRTY(hpte_get_ptr(spapr, index)) 2267 && HPTE_VALID(hpte_get_ptr(spapr, index))) { 2268 CLEAN_HPTE(hpte_get_ptr(spapr, index)); 2269 index++; 2270 examined++; 2271 } 2272 2273 invalidstart = index; 2274 /* Consume invalid dirty HPTEs */ 2275 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2276 && HPTE_DIRTY(hpte_get_ptr(spapr, index)) 2277 && !HPTE_VALID(hpte_get_ptr(spapr, index))) { 2278 CLEAN_HPTE(hpte_get_ptr(spapr, index)); 2279 index++; 2280 examined++; 2281 } 2282 2283 if (index > chunkstart) { 2284 int n_valid = invalidstart - chunkstart; 2285 int n_invalid = index - invalidstart; 2286 2287 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2288 sent += index - chunkstart; 2289 2290 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2291 break; 2292 } 2293 } 2294 2295 if (examined >= htabslots) { 2296 break; 2297 } 2298 2299 if (index >= htabslots) { 2300 assert(index == htabslots); 2301 index = 0; 2302 } 2303 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2304 2305 if (index >= htabslots) { 2306 assert(index == htabslots); 2307 index = 0; 2308 } 2309 2310 spapr->htab_save_index = index; 2311 2312 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2313 } 2314 2315 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2316 #define MAX_KVM_BUF_SIZE 2048 2317 2318 static int htab_save_iterate(QEMUFile *f, void *opaque) 2319 { 2320 SpaprMachineState *spapr = opaque; 2321 int fd; 2322 int rc = 0; 2323 2324 /* Iteration header */ 2325 if (!spapr->htab_shift) { 2326 qemu_put_be32(f, -1); 2327 return 1; 2328 } else { 2329 qemu_put_be32(f, 0); 2330 } 2331 2332 if (!spapr->htab) { 2333 assert(kvm_enabled()); 2334 2335 fd = get_htab_fd(spapr); 2336 if (fd < 0) { 2337 return fd; 2338 } 2339 2340 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2341 if (rc < 0) { 2342 return rc; 2343 } 2344 } else if (spapr->htab_first_pass) { 2345 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2346 } else { 2347 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2348 } 2349 2350 htab_save_end_marker(f); 2351 2352 return rc; 2353 } 2354 2355 static int htab_save_complete(QEMUFile *f, void *opaque) 2356 { 2357 SpaprMachineState *spapr = opaque; 2358 int fd; 2359 2360 /* Iteration header */ 2361 if (!spapr->htab_shift) { 2362 qemu_put_be32(f, -1); 2363 return 0; 2364 } else { 2365 qemu_put_be32(f, 0); 2366 } 2367 2368 if (!spapr->htab) { 2369 int rc; 2370 2371 assert(kvm_enabled()); 2372 2373 fd = get_htab_fd(spapr); 2374 if (fd < 0) { 2375 return fd; 2376 } 2377 2378 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2379 if (rc < 0) { 2380 return rc; 2381 } 2382 } else { 2383 if (spapr->htab_first_pass) { 2384 htab_save_first_pass(f, spapr, -1); 2385 } 2386 htab_save_later_pass(f, spapr, -1); 2387 } 2388 2389 /* End marker */ 2390 htab_save_end_marker(f); 2391 2392 return 0; 2393 } 2394 2395 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2396 { 2397 SpaprMachineState *spapr = opaque; 2398 uint32_t section_hdr; 2399 int fd = -1; 2400 Error *local_err = NULL; 2401 2402 if (version_id < 1 || version_id > 1) { 2403 error_report("htab_load() bad version"); 2404 return -EINVAL; 2405 } 2406 2407 section_hdr = qemu_get_be32(f); 2408 2409 if (section_hdr == -1) { 2410 spapr_free_hpt(spapr); 2411 return 0; 2412 } 2413 2414 if (section_hdr) { 2415 int ret; 2416 2417 /* First section gives the htab size */ 2418 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2419 if (ret < 0) { 2420 error_report_err(local_err); 2421 return ret; 2422 } 2423 return 0; 2424 } 2425 2426 if (!spapr->htab) { 2427 assert(kvm_enabled()); 2428 2429 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2430 if (fd < 0) { 2431 error_report_err(local_err); 2432 return fd; 2433 } 2434 } 2435 2436 while (true) { 2437 uint32_t index; 2438 uint16_t n_valid, n_invalid; 2439 2440 index = qemu_get_be32(f); 2441 n_valid = qemu_get_be16(f); 2442 n_invalid = qemu_get_be16(f); 2443 2444 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2445 /* End of Stream */ 2446 break; 2447 } 2448 2449 if ((index + n_valid + n_invalid) > 2450 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2451 /* Bad index in stream */ 2452 error_report( 2453 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2454 index, n_valid, n_invalid, spapr->htab_shift); 2455 return -EINVAL; 2456 } 2457 2458 if (spapr->htab) { 2459 if (n_valid) { 2460 qemu_get_buffer(f, (void *)hpte_get_ptr(spapr, index), 2461 HASH_PTE_SIZE_64 * n_valid); 2462 } 2463 if (n_invalid) { 2464 memset(hpte_get_ptr(spapr, index + n_valid), 0, 2465 HASH_PTE_SIZE_64 * n_invalid); 2466 } 2467 } else { 2468 int rc; 2469 2470 assert(fd >= 0); 2471 2472 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2473 &local_err); 2474 if (rc < 0) { 2475 error_report_err(local_err); 2476 return rc; 2477 } 2478 } 2479 } 2480 2481 if (!spapr->htab) { 2482 assert(fd >= 0); 2483 close(fd); 2484 } 2485 2486 return 0; 2487 } 2488 2489 static void htab_save_cleanup(void *opaque) 2490 { 2491 SpaprMachineState *spapr = opaque; 2492 2493 close_htab_fd(spapr); 2494 } 2495 2496 static SaveVMHandlers savevm_htab_handlers = { 2497 .save_setup = htab_save_setup, 2498 .save_live_iterate = htab_save_iterate, 2499 .save_live_complete_precopy = htab_save_complete, 2500 .save_cleanup = htab_save_cleanup, 2501 .load_state = htab_load, 2502 }; 2503 2504 static void spapr_boot_set(void *opaque, const char *boot_device, 2505 Error **errp) 2506 { 2507 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2508 2509 g_free(spapr->boot_device); 2510 spapr->boot_device = g_strdup(boot_device); 2511 } 2512 2513 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2514 { 2515 MachineState *machine = MACHINE(spapr); 2516 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2517 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2518 int i; 2519 2520 g_assert(!nr_lmbs || machine->device_memory); 2521 for (i = 0; i < nr_lmbs; i++) { 2522 uint64_t addr; 2523 2524 addr = i * lmb_size + machine->device_memory->base; 2525 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2526 addr / lmb_size); 2527 } 2528 } 2529 2530 /* 2531 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2532 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2533 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2534 */ 2535 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2536 { 2537 int i; 2538 2539 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2540 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2541 " is not aligned to %" PRIu64 " MiB", 2542 machine->ram_size, 2543 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2544 return; 2545 } 2546 2547 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2548 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2549 " is not aligned to %" PRIu64 " MiB", 2550 machine->ram_size, 2551 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2552 return; 2553 } 2554 2555 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2556 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2557 error_setg(errp, 2558 "Node %d memory size 0x%" PRIx64 2559 " is not aligned to %" PRIu64 " MiB", 2560 i, machine->numa_state->nodes[i].node_mem, 2561 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2562 return; 2563 } 2564 } 2565 } 2566 2567 /* find cpu slot in machine->possible_cpus by core_id */ 2568 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2569 { 2570 int index = id / ms->smp.threads; 2571 2572 if (index >= ms->possible_cpus->len) { 2573 return NULL; 2574 } 2575 if (idx) { 2576 *idx = index; 2577 } 2578 return &ms->possible_cpus->cpus[index]; 2579 } 2580 2581 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2582 { 2583 MachineState *ms = MACHINE(spapr); 2584 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2585 Error *local_err = NULL; 2586 bool vsmt_user = !!spapr->vsmt; 2587 int kvm_smt = kvmppc_smt_threads(); 2588 int ret; 2589 unsigned int smp_threads = ms->smp.threads; 2590 2591 if (tcg_enabled()) { 2592 if (smp_threads > 1 && 2593 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2594 spapr->max_compat_pvr)) { 2595 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2596 return; 2597 } 2598 2599 if (smp_threads > 8) { 2600 error_setg(errp, "TCG cannot support more than 8 threads/core " 2601 "on a pseries machine"); 2602 return; 2603 } 2604 } 2605 if (!is_power_of_2(smp_threads)) { 2606 error_setg(errp, "Cannot support %d threads/core on a pseries " 2607 "machine because it must be a power of 2", smp_threads); 2608 return; 2609 } 2610 2611 /* Determine the VSMT mode to use: */ 2612 if (vsmt_user) { 2613 if (spapr->vsmt < smp_threads) { 2614 error_setg(errp, "Cannot support VSMT mode %d" 2615 " because it must be >= threads/core (%d)", 2616 spapr->vsmt, smp_threads); 2617 return; 2618 } 2619 /* In this case, spapr->vsmt has been set by the command line */ 2620 } else if (!smc->smp_threads_vsmt) { 2621 /* 2622 * Default VSMT value is tricky, because we need it to be as 2623 * consistent as possible (for migration), but this requires 2624 * changing it for at least some existing cases. We pick 8 as 2625 * the value that we'd get with KVM on POWER8, the 2626 * overwhelmingly common case in production systems. 2627 */ 2628 spapr->vsmt = MAX(8, smp_threads); 2629 } else { 2630 spapr->vsmt = smp_threads; 2631 } 2632 2633 /* KVM: If necessary, set the SMT mode: */ 2634 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2635 ret = kvmppc_set_smt_threads(spapr->vsmt); 2636 if (ret) { 2637 /* Looks like KVM isn't able to change VSMT mode */ 2638 error_setg(&local_err, 2639 "Failed to set KVM's VSMT mode to %d (errno %d)", 2640 spapr->vsmt, ret); 2641 /* We can live with that if the default one is big enough 2642 * for the number of threads, and a submultiple of the one 2643 * we want. In this case we'll waste some vcpu ids, but 2644 * behaviour will be correct */ 2645 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2646 warn_report_err(local_err); 2647 } else { 2648 if (!vsmt_user) { 2649 error_append_hint(&local_err, 2650 "On PPC, a VM with %d threads/core" 2651 " on a host with %d threads/core" 2652 " requires the use of VSMT mode %d.\n", 2653 smp_threads, kvm_smt, spapr->vsmt); 2654 } 2655 kvmppc_error_append_smt_possible_hint(&local_err); 2656 error_propagate(errp, local_err); 2657 } 2658 } 2659 } 2660 /* else TCG: nothing to do currently */ 2661 } 2662 2663 static void spapr_init_cpus(SpaprMachineState *spapr) 2664 { 2665 MachineState *machine = MACHINE(spapr); 2666 MachineClass *mc = MACHINE_GET_CLASS(machine); 2667 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2668 const CPUArchIdList *possible_cpus; 2669 unsigned int smp_cpus = machine->smp.cpus; 2670 unsigned int smp_threads = machine->smp.threads; 2671 unsigned int max_cpus = machine->smp.max_cpus; 2672 int boot_cores_nr = smp_cpus / smp_threads; 2673 int i; 2674 2675 possible_cpus = mc->possible_cpu_arch_ids(machine); 2676 if (mc->has_hotpluggable_cpus) { 2677 if (smp_cpus % smp_threads) { 2678 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2679 smp_cpus, smp_threads); 2680 exit(1); 2681 } 2682 if (max_cpus % smp_threads) { 2683 error_report("max_cpus (%u) must be multiple of threads (%u)", 2684 max_cpus, smp_threads); 2685 exit(1); 2686 } 2687 } else { 2688 if (max_cpus != smp_cpus) { 2689 error_report("This machine version does not support CPU hotplug"); 2690 exit(1); 2691 } 2692 boot_cores_nr = possible_cpus->len; 2693 } 2694 2695 for (i = 0; i < possible_cpus->len; i++) { 2696 int core_id = i * smp_threads; 2697 2698 if (mc->has_hotpluggable_cpus) { 2699 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2700 spapr_vcpu_id(spapr, core_id)); 2701 } 2702 2703 if (i < boot_cores_nr) { 2704 Object *core = object_new(type); 2705 int nr_threads = smp_threads; 2706 2707 /* Handle the partially filled core for older machine types */ 2708 if ((i + 1) * smp_threads >= smp_cpus) { 2709 nr_threads = smp_cpus - i * smp_threads; 2710 } 2711 2712 object_property_set_int(core, "nr-threads", nr_threads, 2713 &error_fatal); 2714 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2715 &error_fatal); 2716 qdev_realize(DEVICE(core), NULL, &error_fatal); 2717 2718 object_unref(core); 2719 } 2720 } 2721 } 2722 2723 static PCIHostState *spapr_create_default_phb(void) 2724 { 2725 DeviceState *dev; 2726 2727 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2728 qdev_prop_set_uint32(dev, "index", 0); 2729 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2730 2731 return PCI_HOST_BRIDGE(dev); 2732 } 2733 2734 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2735 { 2736 MachineState *machine = MACHINE(spapr); 2737 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2738 hwaddr rma_size = machine->ram_size; 2739 hwaddr node0_size = spapr_node0_size(machine); 2740 2741 /* RMA has to fit in the first NUMA node */ 2742 rma_size = MIN(rma_size, node0_size); 2743 2744 /* 2745 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2746 * never exceed that 2747 */ 2748 rma_size = MIN(rma_size, 1 * TiB); 2749 2750 /* 2751 * Clamp the RMA size based on machine type. This is for 2752 * migration compatibility with older qemu versions, which limited 2753 * the RMA size for complicated and mostly bad reasons. 2754 */ 2755 if (smc->rma_limit) { 2756 rma_size = MIN(rma_size, smc->rma_limit); 2757 } 2758 2759 if (rma_size < MIN_RMA_SLOF) { 2760 error_setg(errp, 2761 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2762 "ldMiB guest RMA (Real Mode Area memory)", 2763 MIN_RMA_SLOF / MiB); 2764 return 0; 2765 } 2766 2767 return rma_size; 2768 } 2769 2770 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2771 { 2772 MachineState *machine = MACHINE(spapr); 2773 int i; 2774 2775 for (i = 0; i < machine->ram_slots; i++) { 2776 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2777 } 2778 } 2779 2780 /* pSeries LPAR / sPAPR hardware init */ 2781 static void spapr_machine_init(MachineState *machine) 2782 { 2783 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2784 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2785 MachineClass *mc = MACHINE_GET_CLASS(machine); 2786 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2787 const char *bios_name = machine->firmware ?: bios_default; 2788 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2789 const char *kernel_filename = machine->kernel_filename; 2790 const char *initrd_filename = machine->initrd_filename; 2791 PCIHostState *phb; 2792 bool has_vga; 2793 int i; 2794 MemoryRegion *sysmem = get_system_memory(); 2795 long load_limit, fw_size; 2796 Error *resize_hpt_err = NULL; 2797 NICInfo *nd; 2798 2799 if (!filename) { 2800 error_report("Could not find LPAR firmware '%s'", bios_name); 2801 exit(1); 2802 } 2803 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2804 if (fw_size <= 0) { 2805 error_report("Could not load LPAR firmware '%s'", filename); 2806 exit(1); 2807 } 2808 2809 /* 2810 * if Secure VM (PEF) support is configured, then initialize it 2811 */ 2812 if (machine->cgs) { 2813 confidential_guest_kvm_init(machine->cgs, &error_fatal); 2814 } 2815 2816 msi_nonbroken = true; 2817 2818 QLIST_INIT(&spapr->phbs); 2819 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2820 2821 /* Determine capabilities to run with */ 2822 spapr_caps_init(spapr); 2823 2824 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2825 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2826 /* 2827 * If the user explicitly requested a mode we should either 2828 * supply it, or fail completely (which we do below). But if 2829 * it's not set explicitly, we reset our mode to something 2830 * that works 2831 */ 2832 if (resize_hpt_err) { 2833 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2834 error_free(resize_hpt_err); 2835 resize_hpt_err = NULL; 2836 } else { 2837 spapr->resize_hpt = smc->resize_hpt_default; 2838 } 2839 } 2840 2841 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2842 2843 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2844 /* 2845 * User requested HPT resize, but this host can't supply it. Bail out 2846 */ 2847 error_report_err(resize_hpt_err); 2848 exit(1); 2849 } 2850 error_free(resize_hpt_err); 2851 2852 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2853 2854 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2855 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2856 2857 /* 2858 * VSMT must be set in order to be able to compute VCPU ids, ie to 2859 * call spapr_max_server_number() or spapr_vcpu_id(). 2860 */ 2861 spapr_set_vsmt_mode(spapr, &error_fatal); 2862 2863 /* Set up Interrupt Controller before we create the VCPUs */ 2864 spapr_irq_init(spapr, &error_fatal); 2865 2866 /* Set up containers for ibm,client-architecture-support negotiated options 2867 */ 2868 spapr->ov5 = spapr_ovec_new(); 2869 spapr->ov5_cas = spapr_ovec_new(); 2870 2871 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2872 spapr_validate_node_memory(machine, &error_fatal); 2873 2874 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2875 2876 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2877 if (!smc->pre_6_2_numa_affinity) { 2878 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2879 } 2880 2881 /* advertise support for dedicated HP event source to guests */ 2882 if (spapr->use_hotplug_event_source) { 2883 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2884 } 2885 2886 /* advertise support for HPT resizing */ 2887 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2888 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2889 } 2890 2891 /* advertise support for ibm,dyamic-memory-v2 */ 2892 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2893 2894 /* advertise XIVE on POWER9 machines */ 2895 if (spapr->irq->xive) { 2896 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2897 } 2898 2899 /* init CPUs */ 2900 spapr_init_cpus(spapr); 2901 2902 /* Init numa_assoc_array */ 2903 spapr_numa_associativity_init(spapr, machine); 2904 2905 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2906 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2907 spapr->max_compat_pvr)) { 2908 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2909 /* KVM and TCG always allow GTSE with radix... */ 2910 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2911 } 2912 /* ... but not with hash (currently). */ 2913 2914 if (kvm_enabled()) { 2915 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2916 kvmppc_enable_logical_ci_hcalls(); 2917 kvmppc_enable_set_mode_hcall(); 2918 2919 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2920 kvmppc_enable_clear_ref_mod_hcalls(); 2921 2922 /* Enable H_PAGE_INIT */ 2923 kvmppc_enable_h_page_init(); 2924 } 2925 2926 /* map RAM */ 2927 memory_region_add_subregion(sysmem, 0, machine->ram); 2928 2929 /* initialize hotplug memory address space */ 2930 if (machine->ram_size < machine->maxram_size) { 2931 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2932 hwaddr device_mem_base; 2933 2934 /* 2935 * Limit the number of hotpluggable memory slots to half the number 2936 * slots that KVM supports, leaving the other half for PCI and other 2937 * devices. However ensure that number of slots doesn't drop below 32. 2938 */ 2939 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2940 SPAPR_MAX_RAM_SLOTS; 2941 2942 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2943 max_memslots = SPAPR_MAX_RAM_SLOTS; 2944 } 2945 if (machine->ram_slots > max_memslots) { 2946 error_report("Specified number of memory slots %" 2947 PRIu64" exceeds max supported %d", 2948 machine->ram_slots, max_memslots); 2949 exit(1); 2950 } 2951 2952 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 2953 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 2954 } 2955 2956 spapr_create_lmb_dr_connectors(spapr); 2957 2958 if (mc->nvdimm_supported) { 2959 spapr_create_nvdimm_dr_connectors(spapr); 2960 } 2961 2962 /* Set up RTAS event infrastructure */ 2963 spapr_events_init(spapr); 2964 2965 /* Set up the RTC RTAS interfaces */ 2966 spapr_rtc_create(spapr); 2967 2968 /* Set up VIO bus */ 2969 spapr->vio_bus = spapr_vio_bus_init(); 2970 2971 for (i = 0; serial_hd(i); i++) { 2972 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2973 } 2974 2975 /* We always have at least the nvram device on VIO */ 2976 spapr_create_nvram(spapr); 2977 2978 /* 2979 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2980 * connectors (described in root DT node's "ibm,drc-types" property) 2981 * are pre-initialized here. additional child connectors (such as 2982 * connectors for a PHBs PCI slots) are added as needed during their 2983 * parent's realization. 2984 */ 2985 if (smc->dr_phb_enabled) { 2986 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2987 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2988 } 2989 } 2990 2991 /* Set up PCI */ 2992 spapr_pci_rtas_init(); 2993 2994 phb = spapr_create_default_phb(); 2995 2996 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 2997 spapr_vlan_create(spapr->vio_bus, nd); 2998 } 2999 3000 pci_init_nic_devices(phb->bus, NULL); 3001 3002 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 3003 spapr_vscsi_create(spapr->vio_bus); 3004 } 3005 3006 /* Graphics */ 3007 has_vga = spapr_vga_init(phb->bus, &error_fatal); 3008 if (has_vga) { 3009 spapr->want_stdout_path = !machine->enable_graphics; 3010 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3011 } else { 3012 spapr->want_stdout_path = true; 3013 } 3014 3015 if (machine->usb) { 3016 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3017 3018 if (has_vga) { 3019 USBBus *usb_bus; 3020 3021 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3022 &error_abort)); 3023 usb_create_simple(usb_bus, "usb-kbd"); 3024 usb_create_simple(usb_bus, "usb-mouse"); 3025 } 3026 } 3027 3028 if (kernel_filename) { 3029 uint64_t loaded_addr = 0; 3030 3031 spapr->kernel_size = load_elf(kernel_filename, NULL, 3032 translate_kernel_address, spapr, 3033 NULL, &loaded_addr, NULL, NULL, 3034 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); 3035 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3036 spapr->kernel_size = load_elf(kernel_filename, NULL, 3037 translate_kernel_address, spapr, 3038 NULL, &loaded_addr, NULL, NULL, 3039 ELFDATA2LSB, PPC_ELF_MACHINE, 0, 0); 3040 spapr->kernel_le = spapr->kernel_size > 0; 3041 } 3042 if (spapr->kernel_size < 0) { 3043 error_report("error loading %s: %s", kernel_filename, 3044 load_elf_strerror(spapr->kernel_size)); 3045 exit(1); 3046 } 3047 3048 if (spapr->kernel_addr != loaded_addr) { 3049 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3050 " to 0x%"PRIx64, 3051 spapr->kernel_addr, loaded_addr); 3052 spapr->kernel_addr = loaded_addr; 3053 } 3054 3055 /* load initrd */ 3056 if (initrd_filename) { 3057 /* Try to locate the initrd in the gap between the kernel 3058 * and the firmware. Add a bit of space just in case 3059 */ 3060 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3061 + 0x1ffff) & ~0xffff; 3062 spapr->initrd_size = load_image_targphys(initrd_filename, 3063 spapr->initrd_base, 3064 load_limit 3065 - spapr->initrd_base); 3066 if (spapr->initrd_size < 0) { 3067 error_report("could not load initial ram disk '%s'", 3068 initrd_filename); 3069 exit(1); 3070 } 3071 } 3072 } 3073 3074 /* FIXME: Should register things through the MachineState's qdev 3075 * interface, this is a legacy from the sPAPREnvironment structure 3076 * which predated MachineState but had a similar function */ 3077 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3078 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3079 &savevm_htab_handlers, spapr); 3080 3081 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3082 3083 qemu_register_boot_set(spapr_boot_set, spapr); 3084 3085 /* 3086 * Nothing needs to be done to resume a suspended guest because 3087 * suspending does not change the machine state, so no need for 3088 * a ->wakeup method. 3089 */ 3090 qemu_register_wakeup_support(); 3091 3092 if (kvm_enabled()) { 3093 /* to stop and start vmclock */ 3094 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3095 &spapr->tb); 3096 3097 kvmppc_spapr_enable_inkernel_multitce(); 3098 } 3099 3100 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3101 if (spapr->vof) { 3102 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3103 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3104 } 3105 3106 spapr_watchdog_init(spapr); 3107 } 3108 3109 #define DEFAULT_KVM_TYPE "auto" 3110 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3111 { 3112 /* 3113 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3114 * accommodate the 'HV' and 'PV' formats that exists in the 3115 * wild. The 'auto' mode is being introduced already as 3116 * lower-case, thus we don't need to bother checking for 3117 * "AUTO". 3118 */ 3119 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3120 return 0; 3121 } 3122 3123 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3124 return 1; 3125 } 3126 3127 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3128 return 2; 3129 } 3130 3131 error_report("Unknown kvm-type specified '%s'", vm_type); 3132 return -1; 3133 } 3134 3135 /* 3136 * Implementation of an interface to adjust firmware path 3137 * for the bootindex property handling. 3138 */ 3139 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3140 DeviceState *dev) 3141 { 3142 #define CAST(type, obj, name) \ 3143 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3144 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3145 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3146 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3147 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3148 3149 if (d && bus) { 3150 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3151 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3152 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3153 3154 if (spapr) { 3155 /* 3156 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3157 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3158 * 0x8000 | (target << 8) | (bus << 5) | lun 3159 * (see the "Logical unit addressing format" table in SAM5) 3160 */ 3161 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3162 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3163 (uint64_t)id << 48); 3164 } else if (virtio) { 3165 /* 3166 * We use SRP luns of the form 01000000 | (target << 8) | lun 3167 * in the top 32 bits of the 64-bit LUN 3168 * Note: the quote above is from SLOF and it is wrong, 3169 * the actual binding is: 3170 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3171 */ 3172 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3173 if (d->lun >= 256) { 3174 /* Use the LUN "flat space addressing method" */ 3175 id |= 0x4000; 3176 } 3177 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3178 (uint64_t)id << 32); 3179 } else if (usb) { 3180 /* 3181 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3182 * in the top 32 bits of the 64-bit LUN 3183 */ 3184 unsigned usb_port = atoi(usb->port->path); 3185 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3186 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3187 (uint64_t)id << 32); 3188 } 3189 } 3190 3191 /* 3192 * SLOF probes the USB devices, and if it recognizes that the device is a 3193 * storage device, it changes its name to "storage" instead of "usb-host", 3194 * and additionally adds a child node for the SCSI LUN, so the correct 3195 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3196 */ 3197 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3198 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3199 if (usb_device_is_scsi_storage(usbdev)) { 3200 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3201 } 3202 } 3203 3204 if (phb) { 3205 /* Replace "pci" with "pci@800000020000000" */ 3206 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3207 } 3208 3209 if (vsc) { 3210 /* Same logic as virtio above */ 3211 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3212 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3213 } 3214 3215 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3216 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3217 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3218 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3219 } 3220 3221 if (pcidev) { 3222 return spapr_pci_fw_dev_name(pcidev); 3223 } 3224 3225 return NULL; 3226 } 3227 3228 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3229 { 3230 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3231 3232 return g_strdup(spapr->kvm_type); 3233 } 3234 3235 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3236 { 3237 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3238 3239 g_free(spapr->kvm_type); 3240 spapr->kvm_type = g_strdup(value); 3241 } 3242 3243 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3244 { 3245 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3246 3247 return spapr->use_hotplug_event_source; 3248 } 3249 3250 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3251 Error **errp) 3252 { 3253 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3254 3255 spapr->use_hotplug_event_source = value; 3256 } 3257 3258 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3259 { 3260 return true; 3261 } 3262 3263 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3264 { 3265 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3266 3267 switch (spapr->resize_hpt) { 3268 case SPAPR_RESIZE_HPT_DEFAULT: 3269 return g_strdup("default"); 3270 case SPAPR_RESIZE_HPT_DISABLED: 3271 return g_strdup("disabled"); 3272 case SPAPR_RESIZE_HPT_ENABLED: 3273 return g_strdup("enabled"); 3274 case SPAPR_RESIZE_HPT_REQUIRED: 3275 return g_strdup("required"); 3276 } 3277 g_assert_not_reached(); 3278 } 3279 3280 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3281 { 3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3283 3284 if (strcmp(value, "default") == 0) { 3285 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3286 } else if (strcmp(value, "disabled") == 0) { 3287 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3288 } else if (strcmp(value, "enabled") == 0) { 3289 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3290 } else if (strcmp(value, "required") == 0) { 3291 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3292 } else { 3293 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3294 } 3295 } 3296 3297 static bool spapr_get_vof(Object *obj, Error **errp) 3298 { 3299 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3300 3301 return spapr->vof != NULL; 3302 } 3303 3304 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3305 { 3306 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3307 3308 if (spapr->vof) { 3309 vof_cleanup(spapr->vof); 3310 g_free(spapr->vof); 3311 spapr->vof = NULL; 3312 } 3313 if (!value) { 3314 return; 3315 } 3316 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3317 } 3318 3319 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3320 { 3321 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3322 3323 if (spapr->irq == &spapr_irq_xics_legacy) { 3324 return g_strdup("legacy"); 3325 } else if (spapr->irq == &spapr_irq_xics) { 3326 return g_strdup("xics"); 3327 } else if (spapr->irq == &spapr_irq_xive) { 3328 return g_strdup("xive"); 3329 } else if (spapr->irq == &spapr_irq_dual) { 3330 return g_strdup("dual"); 3331 } 3332 g_assert_not_reached(); 3333 } 3334 3335 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3336 { 3337 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3338 3339 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3340 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3341 return; 3342 } 3343 3344 /* The legacy IRQ backend can not be set */ 3345 if (strcmp(value, "xics") == 0) { 3346 spapr->irq = &spapr_irq_xics; 3347 } else if (strcmp(value, "xive") == 0) { 3348 spapr->irq = &spapr_irq_xive; 3349 } else if (strcmp(value, "dual") == 0) { 3350 spapr->irq = &spapr_irq_dual; 3351 } else { 3352 error_setg(errp, "Bad value for \"ic-mode\" property"); 3353 } 3354 } 3355 3356 static char *spapr_get_host_model(Object *obj, Error **errp) 3357 { 3358 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3359 3360 return g_strdup(spapr->host_model); 3361 } 3362 3363 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3364 { 3365 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3366 3367 g_free(spapr->host_model); 3368 spapr->host_model = g_strdup(value); 3369 } 3370 3371 static char *spapr_get_host_serial(Object *obj, Error **errp) 3372 { 3373 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3374 3375 return g_strdup(spapr->host_serial); 3376 } 3377 3378 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3379 { 3380 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3381 3382 g_free(spapr->host_serial); 3383 spapr->host_serial = g_strdup(value); 3384 } 3385 3386 static void spapr_instance_init(Object *obj) 3387 { 3388 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3389 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3390 MachineState *ms = MACHINE(spapr); 3391 MachineClass *mc = MACHINE_GET_CLASS(ms); 3392 3393 /* 3394 * NVDIMM support went live in 5.1 without considering that, in 3395 * other archs, the user needs to enable NVDIMM support with the 3396 * 'nvdimm' machine option and the default behavior is NVDIMM 3397 * support disabled. It is too late to roll back to the standard 3398 * behavior without breaking 5.1 guests. 3399 */ 3400 if (mc->nvdimm_supported) { 3401 ms->nvdimms_state->is_enabled = true; 3402 } 3403 3404 spapr->htab_fd = -1; 3405 spapr->use_hotplug_event_source = true; 3406 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3407 object_property_add_str(obj, "kvm-type", 3408 spapr_get_kvm_type, spapr_set_kvm_type); 3409 object_property_set_description(obj, "kvm-type", 3410 "Specifies the KVM virtualization mode (auto," 3411 " hv, pr). Defaults to 'auto'. This mode will use" 3412 " any available KVM module loaded in the host," 3413 " where kvm_hv takes precedence if both kvm_hv and" 3414 " kvm_pr are loaded."); 3415 object_property_add_bool(obj, "modern-hotplug-events", 3416 spapr_get_modern_hotplug_events, 3417 spapr_set_modern_hotplug_events); 3418 object_property_set_description(obj, "modern-hotplug-events", 3419 "Use dedicated hotplug event mechanism in" 3420 " place of standard EPOW events when possible" 3421 " (required for memory hot-unplug support)"); 3422 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3423 "Maximum permitted CPU compatibility mode"); 3424 3425 object_property_add_str(obj, "resize-hpt", 3426 spapr_get_resize_hpt, spapr_set_resize_hpt); 3427 object_property_set_description(obj, "resize-hpt", 3428 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3429 object_property_add_uint32_ptr(obj, "vsmt", 3430 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3431 object_property_set_description(obj, "vsmt", 3432 "Virtual SMT: KVM behaves as if this were" 3433 " the host's SMT mode"); 3434 3435 object_property_add_bool(obj, "vfio-no-msix-emulation", 3436 spapr_get_msix_emulation, NULL); 3437 3438 object_property_add_uint64_ptr(obj, "kernel-addr", 3439 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3440 object_property_set_description(obj, "kernel-addr", 3441 stringify(KERNEL_LOAD_ADDR) 3442 " for -kernel is the default"); 3443 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3444 3445 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3446 object_property_set_description(obj, "x-vof", 3447 "Enable Virtual Open Firmware (experimental)"); 3448 3449 /* The machine class defines the default interrupt controller mode */ 3450 spapr->irq = smc->irq; 3451 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3452 spapr_set_ic_mode); 3453 object_property_set_description(obj, "ic-mode", 3454 "Specifies the interrupt controller mode (xics, xive, dual)"); 3455 3456 object_property_add_str(obj, "host-model", 3457 spapr_get_host_model, spapr_set_host_model); 3458 object_property_set_description(obj, "host-model", 3459 "Host model to advertise in guest device tree"); 3460 object_property_add_str(obj, "host-serial", 3461 spapr_get_host_serial, spapr_set_host_serial); 3462 object_property_set_description(obj, "host-serial", 3463 "Host serial number to advertise in guest device tree"); 3464 } 3465 3466 static void spapr_machine_finalizefn(Object *obj) 3467 { 3468 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3469 3470 g_free(spapr->kvm_type); 3471 } 3472 3473 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3474 { 3475 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3476 CPUPPCState *env = cpu_env(cs); 3477 3478 cpu_synchronize_state(cs); 3479 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3480 if (spapr->fwnmi_system_reset_addr != -1) { 3481 uint64_t rtas_addr, addr; 3482 3483 /* get rtas addr from fdt */ 3484 rtas_addr = spapr_get_rtas_addr(); 3485 if (!rtas_addr) { 3486 qemu_system_guest_panicked(NULL); 3487 return; 3488 } 3489 3490 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3491 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3492 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3493 env->gpr[3] = addr; 3494 } 3495 ppc_cpu_do_system_reset(cs); 3496 if (spapr->fwnmi_system_reset_addr != -1) { 3497 env->nip = spapr->fwnmi_system_reset_addr; 3498 } 3499 } 3500 3501 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3502 { 3503 CPUState *cs; 3504 3505 CPU_FOREACH(cs) { 3506 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3507 } 3508 } 3509 3510 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3511 void *fdt, int *fdt_start_offset, Error **errp) 3512 { 3513 uint64_t addr; 3514 uint32_t node; 3515 3516 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3517 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3518 &error_abort); 3519 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3520 SPAPR_MEMORY_BLOCK_SIZE); 3521 return 0; 3522 } 3523 3524 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3525 bool dedicated_hp_event_source) 3526 { 3527 SpaprDrc *drc; 3528 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3529 int i; 3530 uint64_t addr = addr_start; 3531 bool hotplugged = spapr_drc_hotplugged(dev); 3532 3533 for (i = 0; i < nr_lmbs; i++) { 3534 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3535 addr / SPAPR_MEMORY_BLOCK_SIZE); 3536 g_assert(drc); 3537 3538 /* 3539 * memory_device_get_free_addr() provided a range of free addresses 3540 * that doesn't overlap with any existing mapping at pre-plug. The 3541 * corresponding LMB DRCs are thus assumed to be all attachable. 3542 */ 3543 spapr_drc_attach(drc, dev); 3544 if (!hotplugged) { 3545 spapr_drc_reset(drc); 3546 } 3547 addr += SPAPR_MEMORY_BLOCK_SIZE; 3548 } 3549 /* send hotplug notification to the 3550 * guest only in case of hotplugged memory 3551 */ 3552 if (hotplugged) { 3553 if (dedicated_hp_event_source) { 3554 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3555 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3556 g_assert(drc); 3557 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3558 nr_lmbs, 3559 spapr_drc_index(drc)); 3560 } else { 3561 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3562 nr_lmbs); 3563 } 3564 } 3565 } 3566 3567 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3568 { 3569 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3570 PCDIMMDevice *dimm = PC_DIMM(dev); 3571 uint64_t size, addr; 3572 int64_t slot; 3573 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3574 3575 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3576 3577 pc_dimm_plug(dimm, MACHINE(ms)); 3578 3579 if (!is_nvdimm) { 3580 addr = object_property_get_uint(OBJECT(dimm), 3581 PC_DIMM_ADDR_PROP, &error_abort); 3582 spapr_add_lmbs(dev, addr, size, 3583 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3584 } else { 3585 slot = object_property_get_int(OBJECT(dimm), 3586 PC_DIMM_SLOT_PROP, &error_abort); 3587 /* We should have valid slot number at this point */ 3588 g_assert(slot >= 0); 3589 spapr_add_nvdimm(dev, slot); 3590 } 3591 } 3592 3593 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3594 Error **errp) 3595 { 3596 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3597 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3598 PCDIMMDevice *dimm = PC_DIMM(dev); 3599 Error *local_err = NULL; 3600 uint64_t size; 3601 Object *memdev; 3602 hwaddr pagesize; 3603 3604 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3605 if (local_err) { 3606 error_propagate(errp, local_err); 3607 return; 3608 } 3609 3610 if (is_nvdimm) { 3611 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3612 return; 3613 } 3614 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3615 error_setg(errp, "Hotplugged memory size must be a multiple of " 3616 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3617 return; 3618 } 3619 3620 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3621 &error_abort); 3622 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3623 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3624 return; 3625 } 3626 3627 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), errp); 3628 } 3629 3630 struct SpaprDimmState { 3631 PCDIMMDevice *dimm; 3632 uint32_t nr_lmbs; 3633 QTAILQ_ENTRY(SpaprDimmState) next; 3634 }; 3635 3636 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3637 PCDIMMDevice *dimm) 3638 { 3639 SpaprDimmState *dimm_state = NULL; 3640 3641 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3642 if (dimm_state->dimm == dimm) { 3643 break; 3644 } 3645 } 3646 return dimm_state; 3647 } 3648 3649 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3650 uint32_t nr_lmbs, 3651 PCDIMMDevice *dimm) 3652 { 3653 SpaprDimmState *ds = NULL; 3654 3655 /* 3656 * If this request is for a DIMM whose removal had failed earlier 3657 * (due to guest's refusal to remove the LMBs), we would have this 3658 * dimm already in the pending_dimm_unplugs list. In that 3659 * case don't add again. 3660 */ 3661 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3662 if (!ds) { 3663 ds = g_new0(SpaprDimmState, 1); 3664 ds->nr_lmbs = nr_lmbs; 3665 ds->dimm = dimm; 3666 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3667 } 3668 return ds; 3669 } 3670 3671 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3672 SpaprDimmState *dimm_state) 3673 { 3674 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3675 g_free(dimm_state); 3676 } 3677 3678 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3679 PCDIMMDevice *dimm) 3680 { 3681 SpaprDrc *drc; 3682 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3683 &error_abort); 3684 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3685 uint32_t avail_lmbs = 0; 3686 uint64_t addr_start, addr; 3687 int i; 3688 3689 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3690 &error_abort); 3691 3692 addr = addr_start; 3693 for (i = 0; i < nr_lmbs; i++) { 3694 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3695 addr / SPAPR_MEMORY_BLOCK_SIZE); 3696 g_assert(drc); 3697 if (drc->dev) { 3698 avail_lmbs++; 3699 } 3700 addr += SPAPR_MEMORY_BLOCK_SIZE; 3701 } 3702 3703 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3704 } 3705 3706 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3707 { 3708 SpaprDimmState *ds; 3709 PCDIMMDevice *dimm; 3710 SpaprDrc *drc; 3711 uint32_t nr_lmbs; 3712 uint64_t size, addr_start, addr; 3713 int i; 3714 3715 if (!dev) { 3716 return; 3717 } 3718 3719 dimm = PC_DIMM(dev); 3720 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3721 3722 /* 3723 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3724 * unplug state, but one of its DRC is marked as unplug_requested. 3725 * This is bad and weird enough to g_assert() out. 3726 */ 3727 g_assert(ds); 3728 3729 spapr_pending_dimm_unplugs_remove(spapr, ds); 3730 3731 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3732 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3733 3734 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3735 &error_abort); 3736 3737 addr = addr_start; 3738 for (i = 0; i < nr_lmbs; i++) { 3739 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3740 addr / SPAPR_MEMORY_BLOCK_SIZE); 3741 g_assert(drc); 3742 3743 drc->unplug_requested = false; 3744 addr += SPAPR_MEMORY_BLOCK_SIZE; 3745 } 3746 3747 /* 3748 * Tell QAPI that something happened and the memory 3749 * hotunplug wasn't successful. 3750 */ 3751 qapi_event_send_device_unplug_guest_error(dev->id, 3752 dev->canonical_path); 3753 } 3754 3755 /* Callback to be called during DRC release. */ 3756 void spapr_lmb_release(DeviceState *dev) 3757 { 3758 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3759 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3760 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3761 3762 /* This information will get lost if a migration occurs 3763 * during the unplug process. In this case recover it. */ 3764 if (ds == NULL) { 3765 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3766 g_assert(ds); 3767 /* The DRC being examined by the caller at least must be counted */ 3768 g_assert(ds->nr_lmbs); 3769 } 3770 3771 if (--ds->nr_lmbs) { 3772 return; 3773 } 3774 3775 /* 3776 * Now that all the LMBs have been removed by the guest, call the 3777 * unplug handler chain. This can never fail. 3778 */ 3779 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3780 object_unparent(OBJECT(dev)); 3781 } 3782 3783 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3784 { 3785 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3786 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3787 3788 /* We really shouldn't get this far without anything to unplug */ 3789 g_assert(ds); 3790 3791 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3792 qdev_unrealize(dev); 3793 spapr_pending_dimm_unplugs_remove(spapr, ds); 3794 } 3795 3796 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3797 DeviceState *dev, Error **errp) 3798 { 3799 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3800 PCDIMMDevice *dimm = PC_DIMM(dev); 3801 uint32_t nr_lmbs; 3802 uint64_t size, addr_start, addr; 3803 int i; 3804 SpaprDrc *drc; 3805 3806 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3807 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3808 return; 3809 } 3810 3811 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3812 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3813 3814 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3815 &error_abort); 3816 3817 /* 3818 * An existing pending dimm state for this DIMM means that there is an 3819 * unplug operation in progress, waiting for the spapr_lmb_release 3820 * callback to complete the job (BQL can't cover that far). In this case, 3821 * bail out to avoid detaching DRCs that were already released. 3822 */ 3823 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3824 error_setg(errp, "Memory unplug already in progress for device %s", 3825 dev->id); 3826 return; 3827 } 3828 3829 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3830 3831 addr = addr_start; 3832 for (i = 0; i < nr_lmbs; i++) { 3833 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3834 addr / SPAPR_MEMORY_BLOCK_SIZE); 3835 g_assert(drc); 3836 3837 spapr_drc_unplug_request(drc); 3838 addr += SPAPR_MEMORY_BLOCK_SIZE; 3839 } 3840 3841 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3842 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3843 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3844 nr_lmbs, spapr_drc_index(drc)); 3845 } 3846 3847 /* Callback to be called during DRC release. */ 3848 void spapr_core_release(DeviceState *dev) 3849 { 3850 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3851 3852 /* Call the unplug handler chain. This can never fail. */ 3853 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3854 object_unparent(OBJECT(dev)); 3855 } 3856 3857 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3858 { 3859 MachineState *ms = MACHINE(hotplug_dev); 3860 CPUCore *cc = CPU_CORE(dev); 3861 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3862 3863 assert(core_slot); 3864 core_slot->cpu = NULL; 3865 qdev_unrealize(dev); 3866 } 3867 3868 static 3869 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3870 Error **errp) 3871 { 3872 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3873 int index; 3874 SpaprDrc *drc; 3875 CPUCore *cc = CPU_CORE(dev); 3876 3877 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3878 error_setg(errp, "Unable to find CPU core with core-id: %d", 3879 cc->core_id); 3880 return; 3881 } 3882 if (index == 0) { 3883 error_setg(errp, "Boot CPU core may not be unplugged"); 3884 return; 3885 } 3886 3887 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3888 spapr_vcpu_id(spapr, cc->core_id)); 3889 g_assert(drc); 3890 3891 if (!spapr_drc_unplug_requested(drc)) { 3892 spapr_drc_unplug_request(drc); 3893 } 3894 3895 /* 3896 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3897 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3898 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3899 * attempt (e.g. the kernel will refuse to remove the last online 3900 * CPU), we will never attempt it again because unplug_requested 3901 * will still be 'true' in that case. 3902 */ 3903 spapr_hotplug_req_remove_by_index(drc); 3904 } 3905 3906 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3907 void *fdt, int *fdt_start_offset, Error **errp) 3908 { 3909 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3910 CPUState *cs = CPU(core->threads[0]); 3911 PowerPCCPU *cpu = POWERPC_CPU(cs); 3912 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3913 int id = spapr_get_vcpu_id(cpu); 3914 g_autofree char *nodename = NULL; 3915 int offset; 3916 3917 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3918 offset = fdt_add_subnode(fdt, 0, nodename); 3919 3920 spapr_dt_cpu(cs, fdt, offset, spapr); 3921 3922 /* 3923 * spapr_dt_cpu() does not fill the 'name' property in the 3924 * CPU node. The function is called during boot process, before 3925 * and after CAS, and overwriting the 'name' property written 3926 * by SLOF is not allowed. 3927 * 3928 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3929 * CPUs more compatible with the coldplugged ones, which have 3930 * the 'name' property. Linux Kernel also relies on this 3931 * property to identify CPU nodes. 3932 */ 3933 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3934 3935 *fdt_start_offset = offset; 3936 return 0; 3937 } 3938 3939 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3940 { 3941 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3942 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3943 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3944 CPUCore *cc = CPU_CORE(dev); 3945 SpaprDrc *drc; 3946 CPUArchId *core_slot; 3947 int index; 3948 bool hotplugged = spapr_drc_hotplugged(dev); 3949 int i; 3950 3951 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3952 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3953 3954 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3955 spapr_vcpu_id(spapr, cc->core_id)); 3956 3957 g_assert(drc || !mc->has_hotpluggable_cpus); 3958 3959 if (drc) { 3960 /* 3961 * spapr_core_pre_plug() already buys us this is a brand new 3962 * core being plugged into a free slot. Nothing should already 3963 * be attached to the corresponding DRC. 3964 */ 3965 spapr_drc_attach(drc, dev); 3966 3967 if (hotplugged) { 3968 /* 3969 * Send hotplug notification interrupt to the guest only 3970 * in case of hotplugged CPUs. 3971 */ 3972 spapr_hotplug_req_add_by_index(drc); 3973 } else { 3974 spapr_drc_reset(drc); 3975 } 3976 } 3977 3978 core_slot->cpu = CPU(dev); 3979 3980 /* 3981 * Set compatibility mode to match the boot CPU, which was either set 3982 * by the machine reset code or by CAS. This really shouldn't fail at 3983 * this point. 3984 */ 3985 if (hotplugged) { 3986 for (i = 0; i < cc->nr_threads; i++) { 3987 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3988 &error_abort); 3989 } 3990 } 3991 3992 } 3993 3994 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3995 Error **errp) 3996 { 3997 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3998 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3999 CPUCore *cc = CPU_CORE(dev); 4000 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4001 const char *type = object_get_typename(OBJECT(dev)); 4002 CPUArchId *core_slot; 4003 int index; 4004 unsigned int smp_threads = machine->smp.threads; 4005 4006 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4007 error_setg(errp, "CPU hotplug not supported for this machine"); 4008 return; 4009 } 4010 4011 if (strcmp(base_core_type, type)) { 4012 error_setg(errp, "CPU core type should be %s", base_core_type); 4013 return; 4014 } 4015 4016 if (cc->core_id % smp_threads) { 4017 error_setg(errp, "invalid core id %d", cc->core_id); 4018 return; 4019 } 4020 4021 /* 4022 * In general we should have homogeneous threads-per-core, but old 4023 * (pre hotplug support) machine types allow the last core to have 4024 * reduced threads as a compatibility hack for when we allowed 4025 * total vcpus not a multiple of threads-per-core. 4026 */ 4027 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4028 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4029 smp_threads); 4030 return; 4031 } 4032 4033 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4034 if (!core_slot) { 4035 error_setg(errp, "core id %d out of range", cc->core_id); 4036 return; 4037 } 4038 4039 if (core_slot->cpu) { 4040 error_setg(errp, "core %d already populated", cc->core_id); 4041 return; 4042 } 4043 4044 numa_cpu_pre_plug(core_slot, dev, errp); 4045 } 4046 4047 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4048 void *fdt, int *fdt_start_offset, Error **errp) 4049 { 4050 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4051 int intc_phandle; 4052 4053 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4054 if (intc_phandle <= 0) { 4055 return -1; 4056 } 4057 4058 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4059 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4060 return -1; 4061 } 4062 4063 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4064 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4065 4066 return 0; 4067 } 4068 4069 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4070 Error **errp) 4071 { 4072 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4073 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4074 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4075 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4076 SpaprDrc *drc; 4077 4078 if (dev->hotplugged && !smc->dr_phb_enabled) { 4079 error_setg(errp, "PHB hotplug not supported for this machine"); 4080 return false; 4081 } 4082 4083 if (sphb->index == (uint32_t)-1) { 4084 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4085 return false; 4086 } 4087 4088 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4089 if (drc && drc->dev) { 4090 error_setg(errp, "PHB %d already attached", sphb->index); 4091 return false; 4092 } 4093 4094 /* 4095 * This will check that sphb->index doesn't exceed the maximum number of 4096 * PHBs for the current machine type. 4097 */ 4098 return 4099 smc->phb_placement(spapr, sphb->index, 4100 &sphb->buid, &sphb->io_win_addr, 4101 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4102 windows_supported, sphb->dma_liobn, 4103 errp); 4104 } 4105 4106 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4107 { 4108 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4109 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4110 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4111 SpaprDrc *drc; 4112 bool hotplugged = spapr_drc_hotplugged(dev); 4113 4114 if (!smc->dr_phb_enabled) { 4115 return; 4116 } 4117 4118 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4119 /* hotplug hooks should check it's enabled before getting this far */ 4120 assert(drc); 4121 4122 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4123 spapr_drc_attach(drc, dev); 4124 4125 if (hotplugged) { 4126 spapr_hotplug_req_add_by_index(drc); 4127 } else { 4128 spapr_drc_reset(drc); 4129 } 4130 } 4131 4132 void spapr_phb_release(DeviceState *dev) 4133 { 4134 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4135 4136 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4137 object_unparent(OBJECT(dev)); 4138 } 4139 4140 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4141 { 4142 qdev_unrealize(dev); 4143 } 4144 4145 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4146 DeviceState *dev, Error **errp) 4147 { 4148 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4149 SpaprDrc *drc; 4150 4151 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4152 assert(drc); 4153 4154 if (!spapr_drc_unplug_requested(drc)) { 4155 spapr_drc_unplug_request(drc); 4156 spapr_hotplug_req_remove_by_index(drc); 4157 } else { 4158 error_setg(errp, 4159 "PCI Host Bridge unplug already in progress for device %s", 4160 dev->id); 4161 } 4162 } 4163 4164 static 4165 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4166 Error **errp) 4167 { 4168 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4169 4170 if (spapr->tpm_proxy != NULL) { 4171 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4172 return false; 4173 } 4174 4175 return true; 4176 } 4177 4178 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4179 { 4180 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4181 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4182 4183 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4184 g_assert(spapr->tpm_proxy == NULL); 4185 4186 spapr->tpm_proxy = tpm_proxy; 4187 } 4188 4189 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4190 { 4191 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4192 4193 qdev_unrealize(dev); 4194 object_unparent(OBJECT(dev)); 4195 spapr->tpm_proxy = NULL; 4196 } 4197 4198 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4199 DeviceState *dev, Error **errp) 4200 { 4201 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4202 spapr_memory_plug(hotplug_dev, dev); 4203 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4204 spapr_core_plug(hotplug_dev, dev); 4205 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4206 spapr_phb_plug(hotplug_dev, dev); 4207 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4208 spapr_tpm_proxy_plug(hotplug_dev, dev); 4209 } 4210 } 4211 4212 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4213 DeviceState *dev, Error **errp) 4214 { 4215 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4216 spapr_memory_unplug(hotplug_dev, dev); 4217 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4218 spapr_core_unplug(hotplug_dev, dev); 4219 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4220 spapr_phb_unplug(hotplug_dev, dev); 4221 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4222 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4223 } 4224 } 4225 4226 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4227 { 4228 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4229 /* 4230 * CAS will process all pending unplug requests. 4231 * 4232 * HACK: a guest could theoretically have cleared all bits in OV5, 4233 * but none of the guests we care for do. 4234 */ 4235 spapr_ovec_empty(spapr->ov5_cas); 4236 } 4237 4238 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4239 DeviceState *dev, Error **errp) 4240 { 4241 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4242 MachineClass *mc = MACHINE_GET_CLASS(sms); 4243 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4244 4245 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4246 if (spapr_memory_hot_unplug_supported(sms)) { 4247 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4248 } else { 4249 error_setg(errp, "Memory hot unplug not supported for this guest"); 4250 } 4251 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4252 if (!mc->has_hotpluggable_cpus) { 4253 error_setg(errp, "CPU hot unplug not supported on this machine"); 4254 return; 4255 } 4256 spapr_core_unplug_request(hotplug_dev, dev, errp); 4257 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4258 if (!smc->dr_phb_enabled) { 4259 error_setg(errp, "PHB hot unplug not supported on this machine"); 4260 return; 4261 } 4262 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4263 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4264 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4265 } 4266 } 4267 4268 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4269 DeviceState *dev, Error **errp) 4270 { 4271 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4272 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4273 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4274 spapr_core_pre_plug(hotplug_dev, dev, errp); 4275 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4276 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4277 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4278 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4279 } 4280 } 4281 4282 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4283 DeviceState *dev) 4284 { 4285 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4286 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4287 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4288 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4289 return HOTPLUG_HANDLER(machine); 4290 } 4291 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4292 PCIDevice *pcidev = PCI_DEVICE(dev); 4293 PCIBus *root = pci_device_root_bus(pcidev); 4294 SpaprPhbState *phb = 4295 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4296 TYPE_SPAPR_PCI_HOST_BRIDGE); 4297 4298 if (phb) { 4299 return HOTPLUG_HANDLER(phb); 4300 } 4301 } 4302 return NULL; 4303 } 4304 4305 static CpuInstanceProperties 4306 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4307 { 4308 CPUArchId *core_slot; 4309 MachineClass *mc = MACHINE_GET_CLASS(machine); 4310 4311 /* make sure possible_cpu are initialized */ 4312 mc->possible_cpu_arch_ids(machine); 4313 /* get CPU core slot containing thread that matches cpu_index */ 4314 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4315 assert(core_slot); 4316 return core_slot->props; 4317 } 4318 4319 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4320 { 4321 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4322 } 4323 4324 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4325 { 4326 int i; 4327 unsigned int smp_threads = machine->smp.threads; 4328 unsigned int smp_cpus = machine->smp.cpus; 4329 const char *core_type; 4330 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4331 MachineClass *mc = MACHINE_GET_CLASS(machine); 4332 4333 if (!mc->has_hotpluggable_cpus) { 4334 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4335 } 4336 if (machine->possible_cpus) { 4337 assert(machine->possible_cpus->len == spapr_max_cores); 4338 return machine->possible_cpus; 4339 } 4340 4341 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4342 if (!core_type) { 4343 error_report("Unable to find sPAPR CPU Core definition"); 4344 exit(1); 4345 } 4346 4347 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4348 sizeof(CPUArchId) * spapr_max_cores); 4349 machine->possible_cpus->len = spapr_max_cores; 4350 for (i = 0; i < machine->possible_cpus->len; i++) { 4351 int core_id = i * smp_threads; 4352 4353 machine->possible_cpus->cpus[i].type = core_type; 4354 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4355 machine->possible_cpus->cpus[i].arch_id = core_id; 4356 machine->possible_cpus->cpus[i].props.has_core_id = true; 4357 machine->possible_cpus->cpus[i].props.core_id = core_id; 4358 } 4359 return machine->possible_cpus; 4360 } 4361 4362 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4363 uint64_t *buid, hwaddr *pio, 4364 hwaddr *mmio32, hwaddr *mmio64, 4365 unsigned n_dma, uint32_t *liobns, Error **errp) 4366 { 4367 /* 4368 * New-style PHB window placement. 4369 * 4370 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4371 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4372 * windows. 4373 * 4374 * Some guest kernels can't work with MMIO windows above 1<<46 4375 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4376 * 4377 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4378 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4379 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4380 * 1TiB 64-bit MMIO windows for each PHB. 4381 */ 4382 const uint64_t base_buid = 0x800000020000000ULL; 4383 int i; 4384 4385 /* Sanity check natural alignments */ 4386 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4387 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4388 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4389 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4390 /* Sanity check bounds */ 4391 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4392 SPAPR_PCI_MEM32_WIN_SIZE); 4393 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4394 SPAPR_PCI_MEM64_WIN_SIZE); 4395 4396 if (index >= SPAPR_MAX_PHBS) { 4397 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4398 SPAPR_MAX_PHBS - 1); 4399 return false; 4400 } 4401 4402 *buid = base_buid + index; 4403 for (i = 0; i < n_dma; ++i) { 4404 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4405 } 4406 4407 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4408 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4409 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4410 return true; 4411 } 4412 4413 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4414 { 4415 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4416 4417 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4418 } 4419 4420 static void spapr_ics_resend(XICSFabric *dev) 4421 { 4422 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4423 4424 ics_resend(spapr->ics); 4425 } 4426 4427 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4428 { 4429 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4430 4431 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4432 } 4433 4434 static void spapr_pic_print_info(InterruptStatsProvider *obj, GString *buf) 4435 { 4436 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4437 4438 spapr_irq_print_info(spapr, buf); 4439 g_string_append_printf(buf, "irqchip: %s\n", 4440 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4441 } 4442 4443 /* 4444 * This is a XIVE only operation 4445 */ 4446 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4447 uint8_t nvt_blk, uint32_t nvt_idx, 4448 bool crowd, bool cam_ignore, uint8_t priority, 4449 uint32_t logic_serv, XiveTCTXMatch *match) 4450 { 4451 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4452 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4453 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4454 int count; 4455 4456 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, cam_ignore, 4457 priority, logic_serv, match); 4458 if (count < 0) { 4459 return count; 4460 } 4461 4462 /* 4463 * When we implement the save and restore of the thread interrupt 4464 * contexts in the enter/exit CPU handlers of the machine and the 4465 * escalations in QEMU, we should be able to handle non dispatched 4466 * vCPUs. 4467 * 4468 * Until this is done, the sPAPR machine should find at least one 4469 * matching context always. 4470 */ 4471 if (count == 0) { 4472 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4473 nvt_blk, nvt_idx); 4474 } 4475 4476 return count; 4477 } 4478 4479 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4480 { 4481 return cpu->vcpu_id; 4482 } 4483 4484 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4485 { 4486 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4487 MachineState *ms = MACHINE(spapr); 4488 int vcpu_id; 4489 4490 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4491 4492 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4493 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4494 error_append_hint(errp, "Adjust the number of cpus to %d " 4495 "or try to raise the number of threads per core\n", 4496 vcpu_id * ms->smp.threads / spapr->vsmt); 4497 return false; 4498 } 4499 4500 cpu->vcpu_id = vcpu_id; 4501 return true; 4502 } 4503 4504 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4505 { 4506 CPUState *cs; 4507 4508 CPU_FOREACH(cs) { 4509 PowerPCCPU *cpu = POWERPC_CPU(cs); 4510 4511 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4512 return cpu; 4513 } 4514 } 4515 4516 return NULL; 4517 } 4518 4519 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4520 { 4521 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4522 4523 return spapr_cpu->in_nested; 4524 } 4525 4526 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4527 { 4528 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4529 4530 /* These are only called by TCG, KVM maintains dispatch state */ 4531 4532 spapr_cpu->prod = false; 4533 if (spapr_cpu->vpa_addr) { 4534 CPUState *cs = CPU(cpu); 4535 uint32_t dispatch; 4536 4537 dispatch = ldl_be_phys(cs->as, 4538 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4539 dispatch++; 4540 if ((dispatch & 1) != 0) { 4541 qemu_log_mask(LOG_GUEST_ERROR, 4542 "VPA: incorrect dispatch counter value for " 4543 "dispatched partition %u, correcting.\n", dispatch); 4544 dispatch++; 4545 } 4546 stl_be_phys(cs->as, 4547 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4548 } 4549 } 4550 4551 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4552 { 4553 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4554 4555 if (spapr_cpu->vpa_addr) { 4556 CPUState *cs = CPU(cpu); 4557 uint32_t dispatch; 4558 4559 dispatch = ldl_be_phys(cs->as, 4560 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4561 dispatch++; 4562 if ((dispatch & 1) != 1) { 4563 qemu_log_mask(LOG_GUEST_ERROR, 4564 "VPA: incorrect dispatch counter value for " 4565 "preempted partition %u, correcting.\n", dispatch); 4566 dispatch++; 4567 } 4568 stl_be_phys(cs->as, 4569 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4570 } 4571 } 4572 4573 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4574 { 4575 MachineClass *mc = MACHINE_CLASS(oc); 4576 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4577 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4578 NMIClass *nc = NMI_CLASS(oc); 4579 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4580 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4581 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4582 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4583 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4584 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4585 4586 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4587 mc->ignore_boot_device_suffixes = true; 4588 4589 /* 4590 * We set up the default / latest behaviour here. The class_init 4591 * functions for the specific versioned machine types can override 4592 * these details for backwards compatibility 4593 */ 4594 mc->init = spapr_machine_init; 4595 mc->reset = spapr_machine_reset; 4596 mc->block_default_type = IF_SCSI; 4597 4598 /* 4599 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4600 * In TCG the limit is restricted by the range of CPU IPIs available. 4601 */ 4602 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4603 4604 mc->no_parallel = 1; 4605 mc->default_boot_order = ""; 4606 mc->default_ram_size = 512 * MiB; 4607 mc->default_ram_id = "ppc_spapr.ram"; 4608 mc->default_display = "std"; 4609 mc->kvm_type = spapr_kvm_type; 4610 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4611 mc->pci_allow_0_address = true; 4612 assert(!mc->get_hotplug_handler); 4613 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4614 hc->pre_plug = spapr_machine_device_pre_plug; 4615 hc->plug = spapr_machine_device_plug; 4616 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4617 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4618 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4619 hc->unplug_request = spapr_machine_device_unplug_request; 4620 hc->unplug = spapr_machine_device_unplug; 4621 4622 smc->update_dt_enabled = true; 4623 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4624 mc->has_hotpluggable_cpus = true; 4625 mc->nvdimm_supported = true; 4626 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4627 fwc->get_dev_path = spapr_get_fw_dev_path; 4628 nc->nmi_monitor_handler = spapr_nmi; 4629 smc->phb_placement = spapr_phb_placement; 4630 vhc->cpu_in_nested = spapr_cpu_in_nested; 4631 vhc->deliver_hv_excp = spapr_exit_nested; 4632 vhc->hypercall = emulate_spapr_hypercall; 4633 vhc->hpt_mask = spapr_hpt_mask; 4634 vhc->map_hptes = spapr_map_hptes; 4635 vhc->unmap_hptes = spapr_unmap_hptes; 4636 vhc->hpte_set_c = spapr_hpte_set_c; 4637 vhc->hpte_set_r = spapr_hpte_set_r; 4638 vhc->get_pate = spapr_get_pate; 4639 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4640 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4641 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4642 xic->ics_get = spapr_ics_get; 4643 xic->ics_resend = spapr_ics_resend; 4644 xic->icp_get = spapr_icp_get; 4645 ispc->print_info = spapr_pic_print_info; 4646 /* Force NUMA node memory size to be a multiple of 4647 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4648 * in which LMBs are represented and hot-added 4649 */ 4650 mc->numa_mem_align_shift = 28; 4651 mc->auto_enable_numa = true; 4652 4653 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4654 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4655 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4656 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4657 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4658 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4659 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4660 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4661 smc->default_caps.caps[SPAPR_CAP_NESTED_PAPR] = SPAPR_CAP_OFF; 4662 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4663 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4664 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4665 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4666 4667 /* 4668 * This cap specifies whether the AIL 3 mode for 4669 * H_SET_RESOURCE is supported. The default is modified 4670 * by default_caps_with_cpu(). 4671 */ 4672 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4673 spapr_caps_add_properties(smc); 4674 smc->irq = &spapr_irq_dual; 4675 smc->dr_phb_enabled = true; 4676 smc->linux_pci_probe = true; 4677 smc->smp_threads_vsmt = true; 4678 smc->nr_xirqs = SPAPR_NR_XIRQS; 4679 xfc->match_nvt = spapr_match_nvt; 4680 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4681 vmc->quiesce = spapr_vof_quiesce; 4682 vmc->setprop = spapr_vof_setprop; 4683 } 4684 4685 static const TypeInfo spapr_machine_info = { 4686 .name = TYPE_SPAPR_MACHINE, 4687 .parent = TYPE_MACHINE, 4688 .abstract = true, 4689 .instance_size = sizeof(SpaprMachineState), 4690 .instance_init = spapr_instance_init, 4691 .instance_finalize = spapr_machine_finalizefn, 4692 .class_size = sizeof(SpaprMachineClass), 4693 .class_init = spapr_machine_class_init, 4694 .interfaces = (InterfaceInfo[]) { 4695 { TYPE_FW_PATH_PROVIDER }, 4696 { TYPE_NMI }, 4697 { TYPE_HOTPLUG_HANDLER }, 4698 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4699 { TYPE_XICS_FABRIC }, 4700 { TYPE_INTERRUPT_STATS_PROVIDER }, 4701 { TYPE_XIVE_FABRIC }, 4702 { TYPE_VOF_MACHINE_IF }, 4703 { } 4704 }, 4705 }; 4706 4707 static void spapr_machine_latest_class_options(MachineClass *mc) 4708 { 4709 mc->alias = "pseries"; 4710 mc->is_default = true; 4711 } 4712 4713 #define DEFINE_SPAPR_MACHINE_IMPL(latest, ...) \ 4714 static void MACHINE_VER_SYM(class_init, spapr, __VA_ARGS__)( \ 4715 ObjectClass *oc, \ 4716 void *data) \ 4717 { \ 4718 MachineClass *mc = MACHINE_CLASS(oc); \ 4719 MACHINE_VER_SYM(class_options, spapr, __VA_ARGS__)(mc); \ 4720 MACHINE_VER_DEPRECATION(__VA_ARGS__); \ 4721 if (latest) { \ 4722 spapr_machine_latest_class_options(mc); \ 4723 } \ 4724 } \ 4725 static const TypeInfo MACHINE_VER_SYM(info, spapr, __VA_ARGS__) = \ 4726 { \ 4727 .name = MACHINE_VER_TYPE_NAME("pseries", __VA_ARGS__), \ 4728 .parent = TYPE_SPAPR_MACHINE, \ 4729 .class_init = MACHINE_VER_SYM(class_init, spapr, __VA_ARGS__), \ 4730 }; \ 4731 static void MACHINE_VER_SYM(register, spapr, __VA_ARGS__)(void) \ 4732 { \ 4733 MACHINE_VER_DELETION(__VA_ARGS__); \ 4734 type_register_static(&MACHINE_VER_SYM(info, spapr, __VA_ARGS__)); \ 4735 } \ 4736 type_init(MACHINE_VER_SYM(register, spapr, __VA_ARGS__)) 4737 4738 #define DEFINE_SPAPR_MACHINE_AS_LATEST(major, minor) \ 4739 DEFINE_SPAPR_MACHINE_IMPL(true, major, minor) 4740 #define DEFINE_SPAPR_MACHINE(major, minor) \ 4741 DEFINE_SPAPR_MACHINE_IMPL(false, major, minor) 4742 4743 /* 4744 * pseries-10.0 4745 */ 4746 static void spapr_machine_10_0_class_options(MachineClass *mc) 4747 { 4748 /* Defaults for the latest behaviour inherited from the base class */ 4749 } 4750 4751 DEFINE_SPAPR_MACHINE_AS_LATEST(10, 0); 4752 4753 /* 4754 * pseries-9.2 4755 */ 4756 static void spapr_machine_9_2_class_options(MachineClass *mc) 4757 { 4758 spapr_machine_10_0_class_options(mc); 4759 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len); 4760 } 4761 4762 DEFINE_SPAPR_MACHINE(9, 2); 4763 4764 /* 4765 * pseries-9.1 4766 */ 4767 static void spapr_machine_9_1_class_options(MachineClass *mc) 4768 { 4769 spapr_machine_9_2_class_options(mc); 4770 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); 4771 } 4772 4773 DEFINE_SPAPR_MACHINE(9, 1); 4774 4775 /* 4776 * pseries-9.0 4777 */ 4778 static void spapr_machine_9_0_class_options(MachineClass *mc) 4779 { 4780 spapr_machine_9_1_class_options(mc); 4781 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 4782 } 4783 4784 DEFINE_SPAPR_MACHINE(9, 0); 4785 4786 /* 4787 * pseries-8.2 4788 */ 4789 static void spapr_machine_8_2_class_options(MachineClass *mc) 4790 { 4791 spapr_machine_9_0_class_options(mc); 4792 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4793 } 4794 4795 DEFINE_SPAPR_MACHINE(8, 2); 4796 4797 /* 4798 * pseries-8.1 4799 */ 4800 static void spapr_machine_8_1_class_options(MachineClass *mc) 4801 { 4802 spapr_machine_8_2_class_options(mc); 4803 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4804 } 4805 4806 DEFINE_SPAPR_MACHINE(8, 1); 4807 4808 /* 4809 * pseries-8.0 4810 */ 4811 static void spapr_machine_8_0_class_options(MachineClass *mc) 4812 { 4813 spapr_machine_8_1_class_options(mc); 4814 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4815 } 4816 4817 DEFINE_SPAPR_MACHINE(8, 0); 4818 4819 /* 4820 * pseries-7.2 4821 */ 4822 static void spapr_machine_7_2_class_options(MachineClass *mc) 4823 { 4824 spapr_machine_8_0_class_options(mc); 4825 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4826 } 4827 4828 DEFINE_SPAPR_MACHINE(7, 2); 4829 4830 /* 4831 * pseries-7.1 4832 */ 4833 static void spapr_machine_7_1_class_options(MachineClass *mc) 4834 { 4835 spapr_machine_7_2_class_options(mc); 4836 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4837 } 4838 4839 DEFINE_SPAPR_MACHINE(7, 1); 4840 4841 /* 4842 * pseries-7.0 4843 */ 4844 static void spapr_machine_7_0_class_options(MachineClass *mc) 4845 { 4846 spapr_machine_7_1_class_options(mc); 4847 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4848 } 4849 4850 DEFINE_SPAPR_MACHINE(7, 0); 4851 4852 /* 4853 * pseries-6.2 4854 */ 4855 static void spapr_machine_6_2_class_options(MachineClass *mc) 4856 { 4857 spapr_machine_7_0_class_options(mc); 4858 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4859 } 4860 4861 DEFINE_SPAPR_MACHINE(6, 2); 4862 4863 /* 4864 * pseries-6.1 4865 */ 4866 static void spapr_machine_6_1_class_options(MachineClass *mc) 4867 { 4868 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4869 4870 spapr_machine_6_2_class_options(mc); 4871 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4872 smc->pre_6_2_numa_affinity = true; 4873 mc->smp_props.prefer_sockets = true; 4874 } 4875 4876 DEFINE_SPAPR_MACHINE(6, 1); 4877 4878 /* 4879 * pseries-6.0 4880 */ 4881 static void spapr_machine_6_0_class_options(MachineClass *mc) 4882 { 4883 spapr_machine_6_1_class_options(mc); 4884 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4885 } 4886 4887 DEFINE_SPAPR_MACHINE(6, 0); 4888 4889 /* 4890 * pseries-5.2 4891 */ 4892 static void spapr_machine_5_2_class_options(MachineClass *mc) 4893 { 4894 spapr_machine_6_0_class_options(mc); 4895 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4896 } 4897 4898 DEFINE_SPAPR_MACHINE(5, 2); 4899 4900 /* 4901 * pseries-5.1 4902 */ 4903 static void spapr_machine_5_1_class_options(MachineClass *mc) 4904 { 4905 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4906 4907 spapr_machine_5_2_class_options(mc); 4908 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4909 smc->pre_5_2_numa_associativity = true; 4910 } 4911 4912 DEFINE_SPAPR_MACHINE(5, 1); 4913 4914 /* 4915 * pseries-5.0 4916 */ 4917 static void spapr_machine_5_0_class_options(MachineClass *mc) 4918 { 4919 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4920 static GlobalProperty compat[] = { 4921 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4922 }; 4923 4924 spapr_machine_5_1_class_options(mc); 4925 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4926 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4927 mc->numa_mem_supported = true; 4928 smc->pre_5_1_assoc_refpoints = true; 4929 } 4930 4931 DEFINE_SPAPR_MACHINE(5, 0); 4932 4933 /* 4934 * pseries-4.2 4935 */ 4936 static void spapr_machine_4_2_class_options(MachineClass *mc) 4937 { 4938 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4939 4940 spapr_machine_5_0_class_options(mc); 4941 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4942 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4943 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4944 smc->rma_limit = 16 * GiB; 4945 mc->nvdimm_supported = false; 4946 } 4947 4948 DEFINE_SPAPR_MACHINE(4, 2); 4949 4950 /* 4951 * pseries-4.1 4952 */ 4953 static void spapr_machine_4_1_class_options(MachineClass *mc) 4954 { 4955 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4956 static GlobalProperty compat[] = { 4957 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4958 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4959 }; 4960 4961 spapr_machine_4_2_class_options(mc); 4962 smc->linux_pci_probe = false; 4963 smc->smp_threads_vsmt = false; 4964 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4965 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4966 } 4967 4968 DEFINE_SPAPR_MACHINE(4, 1); 4969 4970 /* 4971 * pseries-4.0 4972 */ 4973 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4974 uint64_t *buid, hwaddr *pio, 4975 hwaddr *mmio32, hwaddr *mmio64, 4976 unsigned n_dma, uint32_t *liobns, Error **errp) 4977 { 4978 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4979 liobns, errp)) { 4980 return false; 4981 } 4982 return true; 4983 } 4984 static void spapr_machine_4_0_class_options(MachineClass *mc) 4985 { 4986 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4987 4988 spapr_machine_4_1_class_options(mc); 4989 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4990 smc->phb_placement = phb_placement_4_0; 4991 smc->irq = &spapr_irq_xics; 4992 smc->pre_4_1_migration = true; 4993 } 4994 4995 DEFINE_SPAPR_MACHINE(4, 0); 4996 4997 /* 4998 * pseries-3.1 4999 */ 5000 static void spapr_machine_3_1_class_options(MachineClass *mc) 5001 { 5002 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5003 5004 spapr_machine_4_0_class_options(mc); 5005 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 5006 5007 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 5008 smc->update_dt_enabled = false; 5009 smc->dr_phb_enabled = false; 5010 smc->broken_host_serial_model = true; 5011 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5012 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5013 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5014 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5015 } 5016 5017 DEFINE_SPAPR_MACHINE(3, 1); 5018 5019 /* 5020 * pseries-3.0 5021 */ 5022 5023 static void spapr_machine_3_0_class_options(MachineClass *mc) 5024 { 5025 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5026 5027 spapr_machine_3_1_class_options(mc); 5028 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5029 5030 smc->legacy_irq_allocation = true; 5031 smc->nr_xirqs = 0x400; 5032 smc->irq = &spapr_irq_xics_legacy; 5033 } 5034 5035 DEFINE_SPAPR_MACHINE(3, 0); 5036 5037 static void spapr_machine_register_types(void) 5038 { 5039 type_register_static(&spapr_machine_info); 5040 } 5041 5042 type_init(spapr_machine_register_types) 5043