1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 #include "hw/intc/intc.h" 67 68 #include "hw/compat.h" 69 #include "qemu/cutils.h" 70 #include "hw/ppc/spapr_cpu_core.h" 71 #include "qmp-commands.h" 72 73 #include <libfdt.h> 74 75 /* SLOF memory layout: 76 * 77 * SLOF raw image loaded at 0, copies its romfs right below the flat 78 * device-tree, then position SLOF itself 31M below that 79 * 80 * So we set FW_OVERHEAD to 40MB which should account for all of that 81 * and more 82 * 83 * We load our kernel at 4M, leaving space for SLOF initial image 84 */ 85 #define FDT_MAX_SIZE 0x100000 86 #define RTAS_MAX_SIZE 0x10000 87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 88 #define FW_MAX_SIZE 0x400000 89 #define FW_FILE_NAME "slof.bin" 90 #define FW_OVERHEAD 0x2800000 91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 92 93 #define MIN_RMA_SLOF 128UL 94 95 #define PHANDLE_XICP 0x00001111 96 97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 98 99 static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics, 100 const char *type_icp, int nr_servers, 101 int nr_irqs, Error **errp) 102 { 103 XICSFabric *xi = XICS_FABRIC(spapr); 104 Error *err = NULL, *local_err = NULL; 105 ICSState *ics = NULL; 106 int i; 107 108 ics = ICS_SIMPLE(object_new(type_ics)); 109 qdev_set_parent_bus(DEVICE(ics), sysbus_get_default()); 110 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 111 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 112 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL); 113 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 114 error_propagate(&err, local_err); 115 if (err) { 116 goto error; 117 } 118 119 spapr->icps = g_malloc0(nr_servers * sizeof(ICPState)); 120 spapr->nr_servers = nr_servers; 121 122 for (i = 0; i < nr_servers; i++) { 123 ICPState *icp = &spapr->icps[i]; 124 125 object_initialize(icp, sizeof(*icp), type_icp); 126 qdev_set_parent_bus(DEVICE(icp), sysbus_get_default()); 127 object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL); 128 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL); 129 object_property_set_bool(OBJECT(icp), true, "realized", &err); 130 if (err) { 131 goto error; 132 } 133 object_unref(OBJECT(icp)); 134 } 135 136 spapr->ics = ics; 137 return 0; 138 139 error: 140 error_propagate(errp, err); 141 if (ics) { 142 object_unparent(OBJECT(ics)); 143 } 144 return -1; 145 } 146 147 static int xics_system_init(MachineState *machine, 148 int nr_servers, int nr_irqs, Error **errp) 149 { 150 int rc = -1; 151 152 if (kvm_enabled()) { 153 Error *err = NULL; 154 155 if (machine_kernel_irqchip_allowed(machine) && 156 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) { 157 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM, 158 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 159 } 160 if (machine_kernel_irqchip_required(machine) && rc < 0) { 161 error_reportf_err(err, 162 "kernel_irqchip requested but unavailable: "); 163 } else { 164 error_free(err); 165 } 166 } 167 168 if (rc < 0) { 169 xics_spapr_init(SPAPR_MACHINE(machine), errp); 170 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_SIMPLE, 171 TYPE_ICP, nr_servers, nr_irqs, errp); 172 } 173 174 return rc; 175 } 176 177 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 178 int smt_threads) 179 { 180 int i, ret = 0; 181 uint32_t servers_prop[smt_threads]; 182 uint32_t gservers_prop[smt_threads * 2]; 183 int index = ppc_get_vcpu_dt_id(cpu); 184 185 if (cpu->compat_pvr) { 186 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 187 if (ret < 0) { 188 return ret; 189 } 190 } 191 192 /* Build interrupt servers and gservers properties */ 193 for (i = 0; i < smt_threads; i++) { 194 servers_prop[i] = cpu_to_be32(index + i); 195 /* Hack, direct the group queues back to cpu 0 */ 196 gservers_prop[i*2] = cpu_to_be32(index + i); 197 gservers_prop[i*2 + 1] = 0; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 200 servers_prop, sizeof(servers_prop)); 201 if (ret < 0) { 202 return ret; 203 } 204 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 205 gservers_prop, sizeof(gservers_prop)); 206 207 return ret; 208 } 209 210 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 211 { 212 int ret = 0; 213 PowerPCCPU *cpu = POWERPC_CPU(cs); 214 int index = ppc_get_vcpu_dt_id(cpu); 215 uint32_t associativity[] = {cpu_to_be32(0x5), 216 cpu_to_be32(0x0), 217 cpu_to_be32(0x0), 218 cpu_to_be32(0x0), 219 cpu_to_be32(cs->numa_node), 220 cpu_to_be32(index)}; 221 222 /* Advertise NUMA via ibm,associativity */ 223 if (nb_numa_nodes > 1) { 224 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 225 sizeof(associativity)); 226 } 227 228 return ret; 229 } 230 231 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 232 { 233 int ret = 0, offset, cpus_offset; 234 CPUState *cs; 235 char cpu_model[32]; 236 int smt = kvmppc_smt_threads(); 237 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 238 239 CPU_FOREACH(cs) { 240 PowerPCCPU *cpu = POWERPC_CPU(cs); 241 DeviceClass *dc = DEVICE_GET_CLASS(cs); 242 int index = ppc_get_vcpu_dt_id(cpu); 243 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 244 245 if ((index % smt) != 0) { 246 continue; 247 } 248 249 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 250 251 cpus_offset = fdt_path_offset(fdt, "/cpus"); 252 if (cpus_offset < 0) { 253 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 254 "cpus"); 255 if (cpus_offset < 0) { 256 return cpus_offset; 257 } 258 } 259 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 260 if (offset < 0) { 261 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 262 if (offset < 0) { 263 return offset; 264 } 265 } 266 267 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 268 pft_size_prop, sizeof(pft_size_prop)); 269 if (ret < 0) { 270 return ret; 271 } 272 273 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 274 if (ret < 0) { 275 return ret; 276 } 277 278 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 279 if (ret < 0) { 280 return ret; 281 } 282 } 283 return ret; 284 } 285 286 static hwaddr spapr_node0_size(void) 287 { 288 MachineState *machine = MACHINE(qdev_get_machine()); 289 290 if (nb_numa_nodes) { 291 int i; 292 for (i = 0; i < nb_numa_nodes; ++i) { 293 if (numa_info[i].node_mem) { 294 return MIN(pow2floor(numa_info[i].node_mem), 295 machine->ram_size); 296 } 297 } 298 } 299 return machine->ram_size; 300 } 301 302 static void add_str(GString *s, const gchar *s1) 303 { 304 g_string_append_len(s, s1, strlen(s1) + 1); 305 } 306 307 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 308 hwaddr size) 309 { 310 uint32_t associativity[] = { 311 cpu_to_be32(0x4), /* length */ 312 cpu_to_be32(0x0), cpu_to_be32(0x0), 313 cpu_to_be32(0x0), cpu_to_be32(nodeid) 314 }; 315 char mem_name[32]; 316 uint64_t mem_reg_property[2]; 317 int off; 318 319 mem_reg_property[0] = cpu_to_be64(start); 320 mem_reg_property[1] = cpu_to_be64(size); 321 322 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 323 off = fdt_add_subnode(fdt, 0, mem_name); 324 _FDT(off); 325 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 326 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 327 sizeof(mem_reg_property)))); 328 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 329 sizeof(associativity)))); 330 return off; 331 } 332 333 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 334 { 335 MachineState *machine = MACHINE(spapr); 336 hwaddr mem_start, node_size; 337 int i, nb_nodes = nb_numa_nodes; 338 NodeInfo *nodes = numa_info; 339 NodeInfo ramnode; 340 341 /* No NUMA nodes, assume there is just one node with whole RAM */ 342 if (!nb_numa_nodes) { 343 nb_nodes = 1; 344 ramnode.node_mem = machine->ram_size; 345 nodes = &ramnode; 346 } 347 348 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 349 if (!nodes[i].node_mem) { 350 continue; 351 } 352 if (mem_start >= machine->ram_size) { 353 node_size = 0; 354 } else { 355 node_size = nodes[i].node_mem; 356 if (node_size > machine->ram_size - mem_start) { 357 node_size = machine->ram_size - mem_start; 358 } 359 } 360 if (!mem_start) { 361 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 362 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 363 mem_start += spapr->rma_size; 364 node_size -= spapr->rma_size; 365 } 366 for ( ; node_size; ) { 367 hwaddr sizetmp = pow2floor(node_size); 368 369 /* mem_start != 0 here */ 370 if (ctzl(mem_start) < ctzl(sizetmp)) { 371 sizetmp = 1ULL << ctzl(mem_start); 372 } 373 374 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 375 node_size -= sizetmp; 376 mem_start += sizetmp; 377 } 378 } 379 380 return 0; 381 } 382 383 /* Populate the "ibm,pa-features" property */ 384 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 385 { 386 uint8_t pa_features_206[] = { 6, 0, 387 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 388 uint8_t pa_features_207[] = { 24, 0, 389 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 390 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 391 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 392 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 393 uint8_t *pa_features; 394 size_t pa_size; 395 396 switch (env->mmu_model) { 397 case POWERPC_MMU_2_06: 398 case POWERPC_MMU_2_06a: 399 pa_features = pa_features_206; 400 pa_size = sizeof(pa_features_206); 401 break; 402 case POWERPC_MMU_2_07: 403 case POWERPC_MMU_2_07a: 404 pa_features = pa_features_207; 405 pa_size = sizeof(pa_features_207); 406 break; 407 default: 408 return; 409 } 410 411 if (env->ci_large_pages) { 412 /* 413 * Note: we keep CI large pages off by default because a 64K capable 414 * guest provisioned with large pages might otherwise try to map a qemu 415 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 416 * even if that qemu runs on a 4k host. 417 * We dd this bit back here if we are confident this is not an issue 418 */ 419 pa_features[3] |= 0x20; 420 } 421 if (kvmppc_has_cap_htm() && pa_size > 24) { 422 pa_features[24] |= 0x80; /* Transactional memory support */ 423 } 424 425 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 426 } 427 428 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 429 sPAPRMachineState *spapr) 430 { 431 PowerPCCPU *cpu = POWERPC_CPU(cs); 432 CPUPPCState *env = &cpu->env; 433 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 434 int index = ppc_get_vcpu_dt_id(cpu); 435 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 436 0xffffffff, 0xffffffff}; 437 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 438 : SPAPR_TIMEBASE_FREQ; 439 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 440 uint32_t page_sizes_prop[64]; 441 size_t page_sizes_prop_size; 442 uint32_t vcpus_per_socket = smp_threads * smp_cores; 443 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 444 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 445 sPAPRDRConnector *drc; 446 sPAPRDRConnectorClass *drck; 447 int drc_index; 448 449 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 450 if (drc) { 451 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 452 drc_index = drck->get_index(drc); 453 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 454 } 455 456 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 457 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 458 459 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 460 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 461 env->dcache_line_size))); 462 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 463 env->dcache_line_size))); 464 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 465 env->icache_line_size))); 466 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 467 env->icache_line_size))); 468 469 if (pcc->l1_dcache_size) { 470 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 471 pcc->l1_dcache_size))); 472 } else { 473 error_report("Warning: Unknown L1 dcache size for cpu"); 474 } 475 if (pcc->l1_icache_size) { 476 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 477 pcc->l1_icache_size))); 478 } else { 479 error_report("Warning: Unknown L1 icache size for cpu"); 480 } 481 482 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 483 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 484 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 485 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 486 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 487 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 488 489 if (env->spr_cb[SPR_PURR].oea_read) { 490 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 491 } 492 493 if (env->mmu_model & POWERPC_MMU_1TSEG) { 494 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 495 segs, sizeof(segs)))); 496 } 497 498 /* Advertise VMX/VSX (vector extensions) if available 499 * 0 / no property == no vector extensions 500 * 1 == VMX / Altivec available 501 * 2 == VSX available */ 502 if (env->insns_flags & PPC_ALTIVEC) { 503 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 504 505 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 506 } 507 508 /* Advertise DFP (Decimal Floating Point) if available 509 * 0 / no property == no DFP 510 * 1 == DFP available */ 511 if (env->insns_flags2 & PPC2_DFP) { 512 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 513 } 514 515 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 516 sizeof(page_sizes_prop)); 517 if (page_sizes_prop_size) { 518 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 519 page_sizes_prop, page_sizes_prop_size))); 520 } 521 522 spapr_populate_pa_features(env, fdt, offset); 523 524 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 525 cs->cpu_index / vcpus_per_socket))); 526 527 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 528 pft_size_prop, sizeof(pft_size_prop)))); 529 530 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 531 532 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 533 } 534 535 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 536 { 537 CPUState *cs; 538 int cpus_offset; 539 char *nodename; 540 int smt = kvmppc_smt_threads(); 541 542 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 543 _FDT(cpus_offset); 544 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 545 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 546 547 /* 548 * We walk the CPUs in reverse order to ensure that CPU DT nodes 549 * created by fdt_add_subnode() end up in the right order in FDT 550 * for the guest kernel the enumerate the CPUs correctly. 551 */ 552 CPU_FOREACH_REVERSE(cs) { 553 PowerPCCPU *cpu = POWERPC_CPU(cs); 554 int index = ppc_get_vcpu_dt_id(cpu); 555 DeviceClass *dc = DEVICE_GET_CLASS(cs); 556 int offset; 557 558 if ((index % smt) != 0) { 559 continue; 560 } 561 562 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 563 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 564 g_free(nodename); 565 _FDT(offset); 566 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 567 } 568 569 } 570 571 /* 572 * Adds ibm,dynamic-reconfiguration-memory node. 573 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 574 * of this device tree node. 575 */ 576 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 577 { 578 MachineState *machine = MACHINE(spapr); 579 int ret, i, offset; 580 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 581 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 582 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 583 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 584 memory_region_size(&spapr->hotplug_memory.mr)) / 585 lmb_size; 586 uint32_t *int_buf, *cur_index, buf_len; 587 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 588 589 /* 590 * Don't create the node if there is no hotpluggable memory 591 */ 592 if (machine->ram_size == machine->maxram_size) { 593 return 0; 594 } 595 596 /* 597 * Allocate enough buffer size to fit in ibm,dynamic-memory 598 * or ibm,associativity-lookup-arrays 599 */ 600 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 601 * sizeof(uint32_t); 602 cur_index = int_buf = g_malloc0(buf_len); 603 604 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 605 606 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 607 sizeof(prop_lmb_size)); 608 if (ret < 0) { 609 goto out; 610 } 611 612 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 613 if (ret < 0) { 614 goto out; 615 } 616 617 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 618 if (ret < 0) { 619 goto out; 620 } 621 622 /* ibm,dynamic-memory */ 623 int_buf[0] = cpu_to_be32(nr_lmbs); 624 cur_index++; 625 for (i = 0; i < nr_lmbs; i++) { 626 uint64_t addr = i * lmb_size; 627 uint32_t *dynamic_memory = cur_index; 628 629 if (i >= hotplug_lmb_start) { 630 sPAPRDRConnector *drc; 631 sPAPRDRConnectorClass *drck; 632 633 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 634 g_assert(drc); 635 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 636 637 dynamic_memory[0] = cpu_to_be32(addr >> 32); 638 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 639 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 640 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 641 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 642 if (memory_region_present(get_system_memory(), addr)) { 643 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 644 } else { 645 dynamic_memory[5] = cpu_to_be32(0); 646 } 647 } else { 648 /* 649 * LMB information for RMA, boot time RAM and gap b/n RAM and 650 * hotplug memory region -- all these are marked as reserved 651 * and as having no valid DRC. 652 */ 653 dynamic_memory[0] = cpu_to_be32(addr >> 32); 654 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 655 dynamic_memory[2] = cpu_to_be32(0); 656 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 657 dynamic_memory[4] = cpu_to_be32(-1); 658 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 659 SPAPR_LMB_FLAGS_DRC_INVALID); 660 } 661 662 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 663 } 664 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 665 if (ret < 0) { 666 goto out; 667 } 668 669 /* ibm,associativity-lookup-arrays */ 670 cur_index = int_buf; 671 int_buf[0] = cpu_to_be32(nr_nodes); 672 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 673 cur_index += 2; 674 for (i = 0; i < nr_nodes; i++) { 675 uint32_t associativity[] = { 676 cpu_to_be32(0x0), 677 cpu_to_be32(0x0), 678 cpu_to_be32(0x0), 679 cpu_to_be32(i) 680 }; 681 memcpy(cur_index, associativity, sizeof(associativity)); 682 cur_index += 4; 683 } 684 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 685 (cur_index - int_buf) * sizeof(uint32_t)); 686 out: 687 g_free(int_buf); 688 return ret; 689 } 690 691 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 692 sPAPROptionVector *ov5_updates) 693 { 694 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 695 int ret = 0, offset; 696 697 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 698 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 699 g_assert(smc->dr_lmb_enabled); 700 ret = spapr_populate_drconf_memory(spapr, fdt); 701 if (ret) { 702 goto out; 703 } 704 } 705 706 offset = fdt_path_offset(fdt, "/chosen"); 707 if (offset < 0) { 708 offset = fdt_add_subnode(fdt, 0, "chosen"); 709 if (offset < 0) { 710 return offset; 711 } 712 } 713 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 714 "ibm,architecture-vec-5"); 715 716 out: 717 return ret; 718 } 719 720 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 721 target_ulong addr, target_ulong size, 722 sPAPROptionVector *ov5_updates) 723 { 724 void *fdt, *fdt_skel; 725 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 726 727 size -= sizeof(hdr); 728 729 /* Create sceleton */ 730 fdt_skel = g_malloc0(size); 731 _FDT((fdt_create(fdt_skel, size))); 732 _FDT((fdt_begin_node(fdt_skel, ""))); 733 _FDT((fdt_end_node(fdt_skel))); 734 _FDT((fdt_finish(fdt_skel))); 735 fdt = g_malloc0(size); 736 _FDT((fdt_open_into(fdt_skel, fdt, size))); 737 g_free(fdt_skel); 738 739 /* Fixup cpu nodes */ 740 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 741 742 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 743 return -1; 744 } 745 746 /* Pack resulting tree */ 747 _FDT((fdt_pack(fdt))); 748 749 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 750 trace_spapr_cas_failed(size); 751 return -1; 752 } 753 754 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 755 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 756 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 757 g_free(fdt); 758 759 return 0; 760 } 761 762 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 763 { 764 int rtas; 765 GString *hypertas = g_string_sized_new(256); 766 GString *qemu_hypertas = g_string_sized_new(256); 767 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 768 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 769 memory_region_size(&spapr->hotplug_memory.mr); 770 uint32_t lrdr_capacity[] = { 771 cpu_to_be32(max_hotplug_addr >> 32), 772 cpu_to_be32(max_hotplug_addr & 0xffffffff), 773 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 774 cpu_to_be32(max_cpus / smp_threads), 775 }; 776 777 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 778 779 /* hypertas */ 780 add_str(hypertas, "hcall-pft"); 781 add_str(hypertas, "hcall-term"); 782 add_str(hypertas, "hcall-dabr"); 783 add_str(hypertas, "hcall-interrupt"); 784 add_str(hypertas, "hcall-tce"); 785 add_str(hypertas, "hcall-vio"); 786 add_str(hypertas, "hcall-splpar"); 787 add_str(hypertas, "hcall-bulk"); 788 add_str(hypertas, "hcall-set-mode"); 789 add_str(hypertas, "hcall-sprg0"); 790 add_str(hypertas, "hcall-copy"); 791 add_str(hypertas, "hcall-debug"); 792 add_str(qemu_hypertas, "hcall-memop1"); 793 794 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 795 add_str(hypertas, "hcall-multi-tce"); 796 } 797 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 798 hypertas->str, hypertas->len)); 799 g_string_free(hypertas, TRUE); 800 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 801 qemu_hypertas->str, qemu_hypertas->len)); 802 g_string_free(qemu_hypertas, TRUE); 803 804 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 805 refpoints, sizeof(refpoints))); 806 807 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 808 RTAS_ERROR_LOG_MAX)); 809 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 810 RTAS_EVENT_SCAN_RATE)); 811 812 if (msi_nonbroken) { 813 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 814 } 815 816 /* 817 * According to PAPR, rtas ibm,os-term does not guarantee a return 818 * back to the guest cpu. 819 * 820 * While an additional ibm,extended-os-term property indicates 821 * that rtas call return will always occur. Set this property. 822 */ 823 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 824 825 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 826 lrdr_capacity, sizeof(lrdr_capacity))); 827 828 spapr_dt_rtas_tokens(fdt, rtas); 829 } 830 831 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 832 { 833 MachineState *machine = MACHINE(spapr); 834 int chosen; 835 const char *boot_device = machine->boot_order; 836 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 837 size_t cb = 0; 838 char *bootlist = get_boot_devices_list(&cb, true); 839 840 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 841 842 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 843 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 844 spapr->initrd_base)); 845 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 846 spapr->initrd_base + spapr->initrd_size)); 847 848 if (spapr->kernel_size) { 849 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 850 cpu_to_be64(spapr->kernel_size) }; 851 852 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 853 &kprop, sizeof(kprop))); 854 if (spapr->kernel_le) { 855 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 856 } 857 } 858 if (boot_menu) { 859 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 860 } 861 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 862 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 863 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 864 865 if (cb && bootlist) { 866 int i; 867 868 for (i = 0; i < cb; i++) { 869 if (bootlist[i] == '\n') { 870 bootlist[i] = ' '; 871 } 872 } 873 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 874 } 875 876 if (boot_device && strlen(boot_device)) { 877 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 878 } 879 880 if (!spapr->has_graphics && stdout_path) { 881 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 882 } 883 884 g_free(stdout_path); 885 g_free(bootlist); 886 } 887 888 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 889 { 890 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 891 * KVM to work under pHyp with some guest co-operation */ 892 int hypervisor; 893 uint8_t hypercall[16]; 894 895 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 896 /* indicate KVM hypercall interface */ 897 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 898 if (kvmppc_has_cap_fixup_hcalls()) { 899 /* 900 * Older KVM versions with older guest kernels were broken 901 * with the magic page, don't allow the guest to map it. 902 */ 903 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 904 sizeof(hypercall))) { 905 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 906 hypercall, sizeof(hypercall))); 907 } 908 } 909 } 910 911 static void *spapr_build_fdt(sPAPRMachineState *spapr, 912 hwaddr rtas_addr, 913 hwaddr rtas_size) 914 { 915 MachineState *machine = MACHINE(qdev_get_machine()); 916 MachineClass *mc = MACHINE_GET_CLASS(machine); 917 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 918 int ret; 919 void *fdt; 920 sPAPRPHBState *phb; 921 char *buf; 922 923 fdt = g_malloc0(FDT_MAX_SIZE); 924 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 925 926 /* Root node */ 927 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 928 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 929 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 930 931 /* 932 * Add info to guest to indentify which host is it being run on 933 * and what is the uuid of the guest 934 */ 935 if (kvmppc_get_host_model(&buf)) { 936 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 937 g_free(buf); 938 } 939 if (kvmppc_get_host_serial(&buf)) { 940 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 941 g_free(buf); 942 } 943 944 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 945 946 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 947 if (qemu_uuid_set) { 948 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 949 } 950 g_free(buf); 951 952 if (qemu_get_vm_name()) { 953 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 954 qemu_get_vm_name())); 955 } 956 957 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 958 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 959 960 /* /interrupt controller */ 961 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP); 962 963 ret = spapr_populate_memory(spapr, fdt); 964 if (ret < 0) { 965 error_report("couldn't setup memory nodes in fdt"); 966 exit(1); 967 } 968 969 /* /vdevice */ 970 spapr_dt_vdevice(spapr->vio_bus, fdt); 971 972 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 973 ret = spapr_rng_populate_dt(fdt); 974 if (ret < 0) { 975 error_report("could not set up rng device in the fdt"); 976 exit(1); 977 } 978 } 979 980 QLIST_FOREACH(phb, &spapr->phbs, list) { 981 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 982 if (ret < 0) { 983 error_report("couldn't setup PCI devices in fdt"); 984 exit(1); 985 } 986 } 987 988 /* cpus */ 989 spapr_populate_cpus_dt_node(fdt, spapr); 990 991 if (smc->dr_lmb_enabled) { 992 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 993 } 994 995 if (mc->has_hotpluggable_cpus) { 996 int offset = fdt_path_offset(fdt, "/cpus"); 997 ret = spapr_drc_populate_dt(fdt, offset, NULL, 998 SPAPR_DR_CONNECTOR_TYPE_CPU); 999 if (ret < 0) { 1000 error_report("Couldn't set up CPU DR device tree properties"); 1001 exit(1); 1002 } 1003 } 1004 1005 /* /event-sources */ 1006 spapr_dt_events(spapr, fdt); 1007 1008 /* /rtas */ 1009 spapr_dt_rtas(spapr, fdt); 1010 1011 /* /chosen */ 1012 spapr_dt_chosen(spapr, fdt); 1013 1014 /* /hypervisor */ 1015 if (kvm_enabled()) { 1016 spapr_dt_hypervisor(spapr, fdt); 1017 } 1018 1019 /* Build memory reserve map */ 1020 if (spapr->kernel_size) { 1021 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1022 } 1023 if (spapr->initrd_size) { 1024 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1025 } 1026 1027 /* ibm,client-architecture-support updates */ 1028 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1029 if (ret < 0) { 1030 error_report("couldn't setup CAS properties fdt"); 1031 exit(1); 1032 } 1033 1034 return fdt; 1035 } 1036 1037 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1038 { 1039 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1040 } 1041 1042 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1043 PowerPCCPU *cpu) 1044 { 1045 CPUPPCState *env = &cpu->env; 1046 1047 /* The TCG path should also be holding the BQL at this point */ 1048 g_assert(qemu_mutex_iothread_locked()); 1049 1050 if (msr_pr) { 1051 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1052 env->gpr[3] = H_PRIVILEGE; 1053 } else { 1054 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1055 } 1056 } 1057 1058 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1059 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1060 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1061 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1062 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1063 1064 /* 1065 * Get the fd to access the kernel htab, re-opening it if necessary 1066 */ 1067 static int get_htab_fd(sPAPRMachineState *spapr) 1068 { 1069 if (spapr->htab_fd >= 0) { 1070 return spapr->htab_fd; 1071 } 1072 1073 spapr->htab_fd = kvmppc_get_htab_fd(false); 1074 if (spapr->htab_fd < 0) { 1075 error_report("Unable to open fd for reading hash table from KVM: %s", 1076 strerror(errno)); 1077 } 1078 1079 return spapr->htab_fd; 1080 } 1081 1082 static void close_htab_fd(sPAPRMachineState *spapr) 1083 { 1084 if (spapr->htab_fd >= 0) { 1085 close(spapr->htab_fd); 1086 } 1087 spapr->htab_fd = -1; 1088 } 1089 1090 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1091 { 1092 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1093 1094 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1095 } 1096 1097 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1098 hwaddr ptex, int n) 1099 { 1100 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1101 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1102 1103 if (!spapr->htab) { 1104 /* 1105 * HTAB is controlled by KVM. Fetch into temporary buffer 1106 */ 1107 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1108 kvmppc_read_hptes(hptes, ptex, n); 1109 return hptes; 1110 } 1111 1112 /* 1113 * HTAB is controlled by QEMU. Just point to the internally 1114 * accessible PTEG. 1115 */ 1116 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1117 } 1118 1119 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1120 const ppc_hash_pte64_t *hptes, 1121 hwaddr ptex, int n) 1122 { 1123 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1124 1125 if (!spapr->htab) { 1126 g_free((void *)hptes); 1127 } 1128 1129 /* Nothing to do for qemu managed HPT */ 1130 } 1131 1132 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1133 uint64_t pte0, uint64_t pte1) 1134 { 1135 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1136 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1137 1138 if (!spapr->htab) { 1139 kvmppc_write_hpte(ptex, pte0, pte1); 1140 } else { 1141 stq_p(spapr->htab + offset, pte0); 1142 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1143 } 1144 } 1145 1146 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1147 { 1148 int shift; 1149 1150 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1151 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1152 * that's much more than is needed for Linux guests */ 1153 shift = ctz64(pow2ceil(ramsize)) - 7; 1154 shift = MAX(shift, 18); /* Minimum architected size */ 1155 shift = MIN(shift, 46); /* Maximum architected size */ 1156 return shift; 1157 } 1158 1159 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1160 Error **errp) 1161 { 1162 long rc; 1163 1164 /* Clean up any HPT info from a previous boot */ 1165 g_free(spapr->htab); 1166 spapr->htab = NULL; 1167 spapr->htab_shift = 0; 1168 close_htab_fd(spapr); 1169 1170 rc = kvmppc_reset_htab(shift); 1171 if (rc < 0) { 1172 /* kernel-side HPT needed, but couldn't allocate one */ 1173 error_setg_errno(errp, errno, 1174 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1175 shift); 1176 /* This is almost certainly fatal, but if the caller really 1177 * wants to carry on with shift == 0, it's welcome to try */ 1178 } else if (rc > 0) { 1179 /* kernel-side HPT allocated */ 1180 if (rc != shift) { 1181 error_setg(errp, 1182 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1183 shift, rc); 1184 } 1185 1186 spapr->htab_shift = shift; 1187 spapr->htab = NULL; 1188 } else { 1189 /* kernel-side HPT not needed, allocate in userspace instead */ 1190 size_t size = 1ULL << shift; 1191 int i; 1192 1193 spapr->htab = qemu_memalign(size, size); 1194 if (!spapr->htab) { 1195 error_setg_errno(errp, errno, 1196 "Could not allocate HPT of order %d", shift); 1197 return; 1198 } 1199 1200 memset(spapr->htab, 0, size); 1201 spapr->htab_shift = shift; 1202 1203 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1204 DIRTY_HPTE(HPTE(spapr->htab, i)); 1205 } 1206 } 1207 } 1208 1209 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1210 { 1211 bool matched = false; 1212 1213 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1214 matched = true; 1215 } 1216 1217 if (!matched) { 1218 error_report("Device %s is not supported by this machine yet.", 1219 qdev_fw_name(DEVICE(sbdev))); 1220 exit(1); 1221 } 1222 } 1223 1224 static void ppc_spapr_reset(void) 1225 { 1226 MachineState *machine = MACHINE(qdev_get_machine()); 1227 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1228 PowerPCCPU *first_ppc_cpu; 1229 uint32_t rtas_limit; 1230 hwaddr rtas_addr, fdt_addr; 1231 void *fdt; 1232 int rc; 1233 1234 /* Check for unknown sysbus devices */ 1235 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1236 1237 /* Allocate and/or reset the hash page table */ 1238 spapr_reallocate_hpt(spapr, 1239 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1240 &error_fatal); 1241 1242 /* Update the RMA size if necessary */ 1243 if (spapr->vrma_adjust) { 1244 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1245 spapr->htab_shift); 1246 } 1247 1248 qemu_devices_reset(); 1249 1250 /* 1251 * We place the device tree and RTAS just below either the top of the RMA, 1252 * or just below 2GB, whichever is lowere, so that it can be 1253 * processed with 32-bit real mode code if necessary 1254 */ 1255 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1256 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1257 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1258 1259 /* if this reset wasn't generated by CAS, we should reset our 1260 * negotiated options and start from scratch */ 1261 if (!spapr->cas_reboot) { 1262 spapr_ovec_cleanup(spapr->ov5_cas); 1263 spapr->ov5_cas = spapr_ovec_new(); 1264 } 1265 1266 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1267 1268 spapr_load_rtas(spapr, fdt, rtas_addr); 1269 1270 rc = fdt_pack(fdt); 1271 1272 /* Should only fail if we've built a corrupted tree */ 1273 assert(rc == 0); 1274 1275 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1276 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1277 fdt_totalsize(fdt), FDT_MAX_SIZE); 1278 exit(1); 1279 } 1280 1281 /* Load the fdt */ 1282 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1283 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1284 g_free(fdt); 1285 1286 /* Set up the entry state */ 1287 first_ppc_cpu = POWERPC_CPU(first_cpu); 1288 first_ppc_cpu->env.gpr[3] = fdt_addr; 1289 first_ppc_cpu->env.gpr[5] = 0; 1290 first_cpu->halted = 0; 1291 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1292 1293 spapr->cas_reboot = false; 1294 } 1295 1296 static void spapr_create_nvram(sPAPRMachineState *spapr) 1297 { 1298 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1299 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1300 1301 if (dinfo) { 1302 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1303 &error_fatal); 1304 } 1305 1306 qdev_init_nofail(dev); 1307 1308 spapr->nvram = (struct sPAPRNVRAM *)dev; 1309 } 1310 1311 static void spapr_rtc_create(sPAPRMachineState *spapr) 1312 { 1313 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1314 1315 qdev_init_nofail(dev); 1316 spapr->rtc = dev; 1317 1318 object_property_add_alias(qdev_get_machine(), "rtc-time", 1319 OBJECT(spapr->rtc), "date", NULL); 1320 } 1321 1322 /* Returns whether we want to use VGA or not */ 1323 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1324 { 1325 switch (vga_interface_type) { 1326 case VGA_NONE: 1327 return false; 1328 case VGA_DEVICE: 1329 return true; 1330 case VGA_STD: 1331 case VGA_VIRTIO: 1332 return pci_vga_init(pci_bus) != NULL; 1333 default: 1334 error_setg(errp, 1335 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1336 return false; 1337 } 1338 } 1339 1340 static int spapr_post_load(void *opaque, int version_id) 1341 { 1342 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1343 int err = 0; 1344 1345 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1346 int i; 1347 for (i = 0; i < spapr->nr_servers; i++) { 1348 icp_resend(&spapr->icps[i]); 1349 } 1350 } 1351 1352 /* In earlier versions, there was no separate qdev for the PAPR 1353 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1354 * So when migrating from those versions, poke the incoming offset 1355 * value into the RTC device */ 1356 if (version_id < 3) { 1357 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1358 } 1359 1360 return err; 1361 } 1362 1363 static bool version_before_3(void *opaque, int version_id) 1364 { 1365 return version_id < 3; 1366 } 1367 1368 static bool spapr_ov5_cas_needed(void *opaque) 1369 { 1370 sPAPRMachineState *spapr = opaque; 1371 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1372 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1373 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1374 bool cas_needed; 1375 1376 /* Prior to the introduction of sPAPROptionVector, we had two option 1377 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1378 * Both of these options encode machine topology into the device-tree 1379 * in such a way that the now-booted OS should still be able to interact 1380 * appropriately with QEMU regardless of what options were actually 1381 * negotiatied on the source side. 1382 * 1383 * As such, we can avoid migrating the CAS-negotiated options if these 1384 * are the only options available on the current machine/platform. 1385 * Since these are the only options available for pseries-2.7 and 1386 * earlier, this allows us to maintain old->new/new->old migration 1387 * compatibility. 1388 * 1389 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1390 * via default pseries-2.8 machines and explicit command-line parameters. 1391 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1392 * of the actual CAS-negotiated values to continue working properly. For 1393 * example, availability of memory unplug depends on knowing whether 1394 * OV5_HP_EVT was negotiated via CAS. 1395 * 1396 * Thus, for any cases where the set of available CAS-negotiatable 1397 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1398 * include the CAS-negotiated options in the migration stream. 1399 */ 1400 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1401 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1402 1403 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1404 * the mask itself since in the future it's possible "legacy" bits may be 1405 * removed via machine options, which could generate a false positive 1406 * that breaks migration. 1407 */ 1408 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1409 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1410 1411 spapr_ovec_cleanup(ov5_mask); 1412 spapr_ovec_cleanup(ov5_legacy); 1413 spapr_ovec_cleanup(ov5_removed); 1414 1415 return cas_needed; 1416 } 1417 1418 static const VMStateDescription vmstate_spapr_ov5_cas = { 1419 .name = "spapr_option_vector_ov5_cas", 1420 .version_id = 1, 1421 .minimum_version_id = 1, 1422 .needed = spapr_ov5_cas_needed, 1423 .fields = (VMStateField[]) { 1424 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1425 vmstate_spapr_ovec, sPAPROptionVector), 1426 VMSTATE_END_OF_LIST() 1427 }, 1428 }; 1429 1430 static const VMStateDescription vmstate_spapr = { 1431 .name = "spapr", 1432 .version_id = 3, 1433 .minimum_version_id = 1, 1434 .post_load = spapr_post_load, 1435 .fields = (VMStateField[]) { 1436 /* used to be @next_irq */ 1437 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1438 1439 /* RTC offset */ 1440 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1441 1442 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1443 VMSTATE_END_OF_LIST() 1444 }, 1445 .subsections = (const VMStateDescription*[]) { 1446 &vmstate_spapr_ov5_cas, 1447 NULL 1448 } 1449 }; 1450 1451 static int htab_save_setup(QEMUFile *f, void *opaque) 1452 { 1453 sPAPRMachineState *spapr = opaque; 1454 1455 /* "Iteration" header */ 1456 qemu_put_be32(f, spapr->htab_shift); 1457 1458 if (spapr->htab) { 1459 spapr->htab_save_index = 0; 1460 spapr->htab_first_pass = true; 1461 } else { 1462 assert(kvm_enabled()); 1463 } 1464 1465 1466 return 0; 1467 } 1468 1469 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1470 int64_t max_ns) 1471 { 1472 bool has_timeout = max_ns != -1; 1473 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1474 int index = spapr->htab_save_index; 1475 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1476 1477 assert(spapr->htab_first_pass); 1478 1479 do { 1480 int chunkstart; 1481 1482 /* Consume invalid HPTEs */ 1483 while ((index < htabslots) 1484 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1485 index++; 1486 CLEAN_HPTE(HPTE(spapr->htab, index)); 1487 } 1488 1489 /* Consume valid HPTEs */ 1490 chunkstart = index; 1491 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1492 && HPTE_VALID(HPTE(spapr->htab, index))) { 1493 index++; 1494 CLEAN_HPTE(HPTE(spapr->htab, index)); 1495 } 1496 1497 if (index > chunkstart) { 1498 int n_valid = index - chunkstart; 1499 1500 qemu_put_be32(f, chunkstart); 1501 qemu_put_be16(f, n_valid); 1502 qemu_put_be16(f, 0); 1503 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1504 HASH_PTE_SIZE_64 * n_valid); 1505 1506 if (has_timeout && 1507 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1508 break; 1509 } 1510 } 1511 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1512 1513 if (index >= htabslots) { 1514 assert(index == htabslots); 1515 index = 0; 1516 spapr->htab_first_pass = false; 1517 } 1518 spapr->htab_save_index = index; 1519 } 1520 1521 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1522 int64_t max_ns) 1523 { 1524 bool final = max_ns < 0; 1525 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1526 int examined = 0, sent = 0; 1527 int index = spapr->htab_save_index; 1528 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1529 1530 assert(!spapr->htab_first_pass); 1531 1532 do { 1533 int chunkstart, invalidstart; 1534 1535 /* Consume non-dirty HPTEs */ 1536 while ((index < htabslots) 1537 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1538 index++; 1539 examined++; 1540 } 1541 1542 chunkstart = index; 1543 /* Consume valid dirty HPTEs */ 1544 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1545 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1546 && HPTE_VALID(HPTE(spapr->htab, index))) { 1547 CLEAN_HPTE(HPTE(spapr->htab, index)); 1548 index++; 1549 examined++; 1550 } 1551 1552 invalidstart = index; 1553 /* Consume invalid dirty HPTEs */ 1554 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1555 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1556 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1557 CLEAN_HPTE(HPTE(spapr->htab, index)); 1558 index++; 1559 examined++; 1560 } 1561 1562 if (index > chunkstart) { 1563 int n_valid = invalidstart - chunkstart; 1564 int n_invalid = index - invalidstart; 1565 1566 qemu_put_be32(f, chunkstart); 1567 qemu_put_be16(f, n_valid); 1568 qemu_put_be16(f, n_invalid); 1569 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1570 HASH_PTE_SIZE_64 * n_valid); 1571 sent += index - chunkstart; 1572 1573 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1574 break; 1575 } 1576 } 1577 1578 if (examined >= htabslots) { 1579 break; 1580 } 1581 1582 if (index >= htabslots) { 1583 assert(index == htabslots); 1584 index = 0; 1585 } 1586 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1587 1588 if (index >= htabslots) { 1589 assert(index == htabslots); 1590 index = 0; 1591 } 1592 1593 spapr->htab_save_index = index; 1594 1595 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1596 } 1597 1598 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1599 #define MAX_KVM_BUF_SIZE 2048 1600 1601 static int htab_save_iterate(QEMUFile *f, void *opaque) 1602 { 1603 sPAPRMachineState *spapr = opaque; 1604 int fd; 1605 int rc = 0; 1606 1607 /* Iteration header */ 1608 qemu_put_be32(f, 0); 1609 1610 if (!spapr->htab) { 1611 assert(kvm_enabled()); 1612 1613 fd = get_htab_fd(spapr); 1614 if (fd < 0) { 1615 return fd; 1616 } 1617 1618 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1619 if (rc < 0) { 1620 return rc; 1621 } 1622 } else if (spapr->htab_first_pass) { 1623 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1624 } else { 1625 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1626 } 1627 1628 /* End marker */ 1629 qemu_put_be32(f, 0); 1630 qemu_put_be16(f, 0); 1631 qemu_put_be16(f, 0); 1632 1633 return rc; 1634 } 1635 1636 static int htab_save_complete(QEMUFile *f, void *opaque) 1637 { 1638 sPAPRMachineState *spapr = opaque; 1639 int fd; 1640 1641 /* Iteration header */ 1642 qemu_put_be32(f, 0); 1643 1644 if (!spapr->htab) { 1645 int rc; 1646 1647 assert(kvm_enabled()); 1648 1649 fd = get_htab_fd(spapr); 1650 if (fd < 0) { 1651 return fd; 1652 } 1653 1654 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1655 if (rc < 0) { 1656 return rc; 1657 } 1658 } else { 1659 if (spapr->htab_first_pass) { 1660 htab_save_first_pass(f, spapr, -1); 1661 } 1662 htab_save_later_pass(f, spapr, -1); 1663 } 1664 1665 /* End marker */ 1666 qemu_put_be32(f, 0); 1667 qemu_put_be16(f, 0); 1668 qemu_put_be16(f, 0); 1669 1670 return 0; 1671 } 1672 1673 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1674 { 1675 sPAPRMachineState *spapr = opaque; 1676 uint32_t section_hdr; 1677 int fd = -1; 1678 1679 if (version_id < 1 || version_id > 1) { 1680 error_report("htab_load() bad version"); 1681 return -EINVAL; 1682 } 1683 1684 section_hdr = qemu_get_be32(f); 1685 1686 if (section_hdr) { 1687 Error *local_err = NULL; 1688 1689 /* First section gives the htab size */ 1690 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1691 if (local_err) { 1692 error_report_err(local_err); 1693 return -EINVAL; 1694 } 1695 return 0; 1696 } 1697 1698 if (!spapr->htab) { 1699 assert(kvm_enabled()); 1700 1701 fd = kvmppc_get_htab_fd(true); 1702 if (fd < 0) { 1703 error_report("Unable to open fd to restore KVM hash table: %s", 1704 strerror(errno)); 1705 } 1706 } 1707 1708 while (true) { 1709 uint32_t index; 1710 uint16_t n_valid, n_invalid; 1711 1712 index = qemu_get_be32(f); 1713 n_valid = qemu_get_be16(f); 1714 n_invalid = qemu_get_be16(f); 1715 1716 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1717 /* End of Stream */ 1718 break; 1719 } 1720 1721 if ((index + n_valid + n_invalid) > 1722 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1723 /* Bad index in stream */ 1724 error_report( 1725 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1726 index, n_valid, n_invalid, spapr->htab_shift); 1727 return -EINVAL; 1728 } 1729 1730 if (spapr->htab) { 1731 if (n_valid) { 1732 qemu_get_buffer(f, HPTE(spapr->htab, index), 1733 HASH_PTE_SIZE_64 * n_valid); 1734 } 1735 if (n_invalid) { 1736 memset(HPTE(spapr->htab, index + n_valid), 0, 1737 HASH_PTE_SIZE_64 * n_invalid); 1738 } 1739 } else { 1740 int rc; 1741 1742 assert(fd >= 0); 1743 1744 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1745 if (rc < 0) { 1746 return rc; 1747 } 1748 } 1749 } 1750 1751 if (!spapr->htab) { 1752 assert(fd >= 0); 1753 close(fd); 1754 } 1755 1756 return 0; 1757 } 1758 1759 static void htab_cleanup(void *opaque) 1760 { 1761 sPAPRMachineState *spapr = opaque; 1762 1763 close_htab_fd(spapr); 1764 } 1765 1766 static SaveVMHandlers savevm_htab_handlers = { 1767 .save_live_setup = htab_save_setup, 1768 .save_live_iterate = htab_save_iterate, 1769 .save_live_complete_precopy = htab_save_complete, 1770 .cleanup = htab_cleanup, 1771 .load_state = htab_load, 1772 }; 1773 1774 static void spapr_boot_set(void *opaque, const char *boot_device, 1775 Error **errp) 1776 { 1777 MachineState *machine = MACHINE(qdev_get_machine()); 1778 machine->boot_order = g_strdup(boot_device); 1779 } 1780 1781 /* 1782 * Reset routine for LMB DR devices. 1783 * 1784 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1785 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1786 * when it walks all its children devices. LMB devices reset occurs 1787 * as part of spapr_ppc_reset(). 1788 */ 1789 static void spapr_drc_reset(void *opaque) 1790 { 1791 sPAPRDRConnector *drc = opaque; 1792 DeviceState *d = DEVICE(drc); 1793 1794 if (d) { 1795 device_reset(d); 1796 } 1797 } 1798 1799 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1800 { 1801 MachineState *machine = MACHINE(spapr); 1802 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1803 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1804 int i; 1805 1806 for (i = 0; i < nr_lmbs; i++) { 1807 sPAPRDRConnector *drc; 1808 uint64_t addr; 1809 1810 addr = i * lmb_size + spapr->hotplug_memory.base; 1811 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1812 addr/lmb_size); 1813 qemu_register_reset(spapr_drc_reset, drc); 1814 } 1815 } 1816 1817 /* 1818 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1819 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1820 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1821 */ 1822 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1823 { 1824 int i; 1825 1826 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1827 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1828 " is not aligned to %llu MiB", 1829 machine->ram_size, 1830 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1831 return; 1832 } 1833 1834 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1835 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1836 " is not aligned to %llu MiB", 1837 machine->ram_size, 1838 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1839 return; 1840 } 1841 1842 for (i = 0; i < nb_numa_nodes; i++) { 1843 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1844 error_setg(errp, 1845 "Node %d memory size 0x%" PRIx64 1846 " is not aligned to %llu MiB", 1847 i, numa_info[i].node_mem, 1848 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1849 return; 1850 } 1851 } 1852 } 1853 1854 /* find cpu slot in machine->possible_cpus by core_id */ 1855 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1856 { 1857 int index = id / smp_threads; 1858 1859 if (index >= ms->possible_cpus->len) { 1860 return NULL; 1861 } 1862 if (idx) { 1863 *idx = index; 1864 } 1865 return &ms->possible_cpus->cpus[index]; 1866 } 1867 1868 static void spapr_init_cpus(sPAPRMachineState *spapr) 1869 { 1870 MachineState *machine = MACHINE(spapr); 1871 MachineClass *mc = MACHINE_GET_CLASS(machine); 1872 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1873 int smt = kvmppc_smt_threads(); 1874 const CPUArchIdList *possible_cpus; 1875 int boot_cores_nr = smp_cpus / smp_threads; 1876 int i; 1877 1878 if (!type) { 1879 error_report("Unable to find sPAPR CPU Core definition"); 1880 exit(1); 1881 } 1882 1883 possible_cpus = mc->possible_cpu_arch_ids(machine); 1884 if (mc->has_hotpluggable_cpus) { 1885 if (smp_cpus % smp_threads) { 1886 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1887 smp_cpus, smp_threads); 1888 exit(1); 1889 } 1890 if (max_cpus % smp_threads) { 1891 error_report("max_cpus (%u) must be multiple of threads (%u)", 1892 max_cpus, smp_threads); 1893 exit(1); 1894 } 1895 } else { 1896 if (max_cpus != smp_cpus) { 1897 error_report("This machine version does not support CPU hotplug"); 1898 exit(1); 1899 } 1900 boot_cores_nr = possible_cpus->len; 1901 } 1902 1903 for (i = 0; i < possible_cpus->len; i++) { 1904 int core_id = i * smp_threads; 1905 1906 if (mc->has_hotpluggable_cpus) { 1907 sPAPRDRConnector *drc = 1908 spapr_dr_connector_new(OBJECT(spapr), 1909 SPAPR_DR_CONNECTOR_TYPE_CPU, 1910 (core_id / smp_threads) * smt); 1911 1912 qemu_register_reset(spapr_drc_reset, drc); 1913 } 1914 1915 if (i < boot_cores_nr) { 1916 Object *core = object_new(type); 1917 int nr_threads = smp_threads; 1918 1919 /* Handle the partially filled core for older machine types */ 1920 if ((i + 1) * smp_threads >= smp_cpus) { 1921 nr_threads = smp_cpus - i * smp_threads; 1922 } 1923 1924 object_property_set_int(core, nr_threads, "nr-threads", 1925 &error_fatal); 1926 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1927 &error_fatal); 1928 object_property_set_bool(core, true, "realized", &error_fatal); 1929 } 1930 } 1931 g_free(type); 1932 } 1933 1934 /* pSeries LPAR / sPAPR hardware init */ 1935 static void ppc_spapr_init(MachineState *machine) 1936 { 1937 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1938 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1939 const char *kernel_filename = machine->kernel_filename; 1940 const char *initrd_filename = machine->initrd_filename; 1941 PCIHostState *phb; 1942 int i; 1943 MemoryRegion *sysmem = get_system_memory(); 1944 MemoryRegion *ram = g_new(MemoryRegion, 1); 1945 MemoryRegion *rma_region; 1946 void *rma = NULL; 1947 hwaddr rma_alloc_size; 1948 hwaddr node0_size = spapr_node0_size(); 1949 long load_limit, fw_size; 1950 char *filename; 1951 int smt = kvmppc_smt_threads(); 1952 1953 msi_nonbroken = true; 1954 1955 QLIST_INIT(&spapr->phbs); 1956 1957 /* Allocate RMA if necessary */ 1958 rma_alloc_size = kvmppc_alloc_rma(&rma); 1959 1960 if (rma_alloc_size == -1) { 1961 error_report("Unable to create RMA"); 1962 exit(1); 1963 } 1964 1965 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1966 spapr->rma_size = rma_alloc_size; 1967 } else { 1968 spapr->rma_size = node0_size; 1969 1970 /* With KVM, we don't actually know whether KVM supports an 1971 * unbounded RMA (PR KVM) or is limited by the hash table size 1972 * (HV KVM using VRMA), so we always assume the latter 1973 * 1974 * In that case, we also limit the initial allocations for RTAS 1975 * etc... to 256M since we have no way to know what the VRMA size 1976 * is going to be as it depends on the size of the hash table 1977 * isn't determined yet. 1978 */ 1979 if (kvm_enabled()) { 1980 spapr->vrma_adjust = 1; 1981 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1982 } 1983 1984 /* Actually we don't support unbounded RMA anymore since we 1985 * added proper emulation of HV mode. The max we can get is 1986 * 16G which also happens to be what we configure for PAPR 1987 * mode so make sure we don't do anything bigger than that 1988 */ 1989 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1990 } 1991 1992 if (spapr->rma_size > node0_size) { 1993 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1994 spapr->rma_size); 1995 exit(1); 1996 } 1997 1998 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1999 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2000 2001 /* Set up Interrupt Controller before we create the VCPUs */ 2002 xics_system_init(machine, DIV_ROUND_UP(max_cpus * smt, smp_threads), 2003 XICS_IRQS_SPAPR, &error_fatal); 2004 2005 /* Set up containers for ibm,client-set-architecture negotiated options */ 2006 spapr->ov5 = spapr_ovec_new(); 2007 spapr->ov5_cas = spapr_ovec_new(); 2008 2009 if (smc->dr_lmb_enabled) { 2010 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2011 spapr_validate_node_memory(machine, &error_fatal); 2012 } 2013 2014 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2015 2016 /* advertise support for dedicated HP event source to guests */ 2017 if (spapr->use_hotplug_event_source) { 2018 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2019 } 2020 2021 /* init CPUs */ 2022 if (machine->cpu_model == NULL) { 2023 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2024 } 2025 2026 ppc_cpu_parse_features(machine->cpu_model); 2027 2028 spapr_init_cpus(spapr); 2029 2030 if (kvm_enabled()) { 2031 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2032 kvmppc_enable_logical_ci_hcalls(); 2033 kvmppc_enable_set_mode_hcall(); 2034 2035 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2036 kvmppc_enable_clear_ref_mod_hcalls(); 2037 } 2038 2039 /* allocate RAM */ 2040 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2041 machine->ram_size); 2042 memory_region_add_subregion(sysmem, 0, ram); 2043 2044 if (rma_alloc_size && rma) { 2045 rma_region = g_new(MemoryRegion, 1); 2046 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2047 rma_alloc_size, rma); 2048 vmstate_register_ram_global(rma_region); 2049 memory_region_add_subregion(sysmem, 0, rma_region); 2050 } 2051 2052 /* initialize hotplug memory address space */ 2053 if (machine->ram_size < machine->maxram_size) { 2054 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2055 /* 2056 * Limit the number of hotpluggable memory slots to half the number 2057 * slots that KVM supports, leaving the other half for PCI and other 2058 * devices. However ensure that number of slots doesn't drop below 32. 2059 */ 2060 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2061 SPAPR_MAX_RAM_SLOTS; 2062 2063 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2064 max_memslots = SPAPR_MAX_RAM_SLOTS; 2065 } 2066 if (machine->ram_slots > max_memslots) { 2067 error_report("Specified number of memory slots %" 2068 PRIu64" exceeds max supported %d", 2069 machine->ram_slots, max_memslots); 2070 exit(1); 2071 } 2072 2073 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2074 SPAPR_HOTPLUG_MEM_ALIGN); 2075 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2076 "hotplug-memory", hotplug_mem_size); 2077 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2078 &spapr->hotplug_memory.mr); 2079 } 2080 2081 if (smc->dr_lmb_enabled) { 2082 spapr_create_lmb_dr_connectors(spapr); 2083 } 2084 2085 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2086 if (!filename) { 2087 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2088 exit(1); 2089 } 2090 spapr->rtas_size = get_image_size(filename); 2091 if (spapr->rtas_size < 0) { 2092 error_report("Could not get size of LPAR rtas '%s'", filename); 2093 exit(1); 2094 } 2095 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2096 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2097 error_report("Could not load LPAR rtas '%s'", filename); 2098 exit(1); 2099 } 2100 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2101 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2102 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2103 exit(1); 2104 } 2105 g_free(filename); 2106 2107 /* Set up RTAS event infrastructure */ 2108 spapr_events_init(spapr); 2109 2110 /* Set up the RTC RTAS interfaces */ 2111 spapr_rtc_create(spapr); 2112 2113 /* Set up VIO bus */ 2114 spapr->vio_bus = spapr_vio_bus_init(); 2115 2116 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2117 if (serial_hds[i]) { 2118 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2119 } 2120 } 2121 2122 /* We always have at least the nvram device on VIO */ 2123 spapr_create_nvram(spapr); 2124 2125 /* Set up PCI */ 2126 spapr_pci_rtas_init(); 2127 2128 phb = spapr_create_phb(spapr, 0); 2129 2130 for (i = 0; i < nb_nics; i++) { 2131 NICInfo *nd = &nd_table[i]; 2132 2133 if (!nd->model) { 2134 nd->model = g_strdup("ibmveth"); 2135 } 2136 2137 if (strcmp(nd->model, "ibmveth") == 0) { 2138 spapr_vlan_create(spapr->vio_bus, nd); 2139 } else { 2140 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2141 } 2142 } 2143 2144 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2145 spapr_vscsi_create(spapr->vio_bus); 2146 } 2147 2148 /* Graphics */ 2149 if (spapr_vga_init(phb->bus, &error_fatal)) { 2150 spapr->has_graphics = true; 2151 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2152 } 2153 2154 if (machine->usb) { 2155 if (smc->use_ohci_by_default) { 2156 pci_create_simple(phb->bus, -1, "pci-ohci"); 2157 } else { 2158 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2159 } 2160 2161 if (spapr->has_graphics) { 2162 USBBus *usb_bus = usb_bus_find(-1); 2163 2164 usb_create_simple(usb_bus, "usb-kbd"); 2165 usb_create_simple(usb_bus, "usb-mouse"); 2166 } 2167 } 2168 2169 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2170 error_report( 2171 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2172 MIN_RMA_SLOF); 2173 exit(1); 2174 } 2175 2176 if (kernel_filename) { 2177 uint64_t lowaddr = 0; 2178 2179 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2180 NULL, NULL, &lowaddr, NULL, 1, 2181 PPC_ELF_MACHINE, 0, 0); 2182 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2183 spapr->kernel_size = load_elf(kernel_filename, 2184 translate_kernel_address, NULL, NULL, 2185 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2186 0, 0); 2187 spapr->kernel_le = spapr->kernel_size > 0; 2188 } 2189 if (spapr->kernel_size < 0) { 2190 error_report("error loading %s: %s", kernel_filename, 2191 load_elf_strerror(spapr->kernel_size)); 2192 exit(1); 2193 } 2194 2195 /* load initrd */ 2196 if (initrd_filename) { 2197 /* Try to locate the initrd in the gap between the kernel 2198 * and the firmware. Add a bit of space just in case 2199 */ 2200 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2201 + 0x1ffff) & ~0xffff; 2202 spapr->initrd_size = load_image_targphys(initrd_filename, 2203 spapr->initrd_base, 2204 load_limit 2205 - spapr->initrd_base); 2206 if (spapr->initrd_size < 0) { 2207 error_report("could not load initial ram disk '%s'", 2208 initrd_filename); 2209 exit(1); 2210 } 2211 } 2212 } 2213 2214 if (bios_name == NULL) { 2215 bios_name = FW_FILE_NAME; 2216 } 2217 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2218 if (!filename) { 2219 error_report("Could not find LPAR firmware '%s'", bios_name); 2220 exit(1); 2221 } 2222 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2223 if (fw_size <= 0) { 2224 error_report("Could not load LPAR firmware '%s'", filename); 2225 exit(1); 2226 } 2227 g_free(filename); 2228 2229 /* FIXME: Should register things through the MachineState's qdev 2230 * interface, this is a legacy from the sPAPREnvironment structure 2231 * which predated MachineState but had a similar function */ 2232 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2233 register_savevm_live(NULL, "spapr/htab", -1, 1, 2234 &savevm_htab_handlers, spapr); 2235 2236 /* used by RTAS */ 2237 QTAILQ_INIT(&spapr->ccs_list); 2238 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2239 2240 qemu_register_boot_set(spapr_boot_set, spapr); 2241 2242 /* to stop and start vmclock */ 2243 if (kvm_enabled()) { 2244 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2245 &spapr->tb); 2246 } 2247 } 2248 2249 static int spapr_kvm_type(const char *vm_type) 2250 { 2251 if (!vm_type) { 2252 return 0; 2253 } 2254 2255 if (!strcmp(vm_type, "HV")) { 2256 return 1; 2257 } 2258 2259 if (!strcmp(vm_type, "PR")) { 2260 return 2; 2261 } 2262 2263 error_report("Unknown kvm-type specified '%s'", vm_type); 2264 exit(1); 2265 } 2266 2267 /* 2268 * Implementation of an interface to adjust firmware path 2269 * for the bootindex property handling. 2270 */ 2271 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2272 DeviceState *dev) 2273 { 2274 #define CAST(type, obj, name) \ 2275 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2276 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2277 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2278 2279 if (d) { 2280 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2281 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2282 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2283 2284 if (spapr) { 2285 /* 2286 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2287 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2288 * in the top 16 bits of the 64-bit LUN 2289 */ 2290 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2291 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2292 (uint64_t)id << 48); 2293 } else if (virtio) { 2294 /* 2295 * We use SRP luns of the form 01000000 | (target << 8) | lun 2296 * in the top 32 bits of the 64-bit LUN 2297 * Note: the quote above is from SLOF and it is wrong, 2298 * the actual binding is: 2299 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2300 */ 2301 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2302 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2303 (uint64_t)id << 32); 2304 } else if (usb) { 2305 /* 2306 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2307 * in the top 32 bits of the 64-bit LUN 2308 */ 2309 unsigned usb_port = atoi(usb->port->path); 2310 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2311 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2312 (uint64_t)id << 32); 2313 } 2314 } 2315 2316 /* 2317 * SLOF probes the USB devices, and if it recognizes that the device is a 2318 * storage device, it changes its name to "storage" instead of "usb-host", 2319 * and additionally adds a child node for the SCSI LUN, so the correct 2320 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2321 */ 2322 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2323 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2324 if (usb_host_dev_is_scsi_storage(usbdev)) { 2325 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2326 } 2327 } 2328 2329 if (phb) { 2330 /* Replace "pci" with "pci@800000020000000" */ 2331 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2332 } 2333 2334 return NULL; 2335 } 2336 2337 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2338 { 2339 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2340 2341 return g_strdup(spapr->kvm_type); 2342 } 2343 2344 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2345 { 2346 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2347 2348 g_free(spapr->kvm_type); 2349 spapr->kvm_type = g_strdup(value); 2350 } 2351 2352 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2353 { 2354 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2355 2356 return spapr->use_hotplug_event_source; 2357 } 2358 2359 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2360 Error **errp) 2361 { 2362 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2363 2364 spapr->use_hotplug_event_source = value; 2365 } 2366 2367 static void spapr_machine_initfn(Object *obj) 2368 { 2369 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2370 2371 spapr->htab_fd = -1; 2372 spapr->use_hotplug_event_source = true; 2373 object_property_add_str(obj, "kvm-type", 2374 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2375 object_property_set_description(obj, "kvm-type", 2376 "Specifies the KVM virtualization mode (HV, PR)", 2377 NULL); 2378 object_property_add_bool(obj, "modern-hotplug-events", 2379 spapr_get_modern_hotplug_events, 2380 spapr_set_modern_hotplug_events, 2381 NULL); 2382 object_property_set_description(obj, "modern-hotplug-events", 2383 "Use dedicated hotplug event mechanism in" 2384 " place of standard EPOW events when possible" 2385 " (required for memory hot-unplug support)", 2386 NULL); 2387 } 2388 2389 static void spapr_machine_finalizefn(Object *obj) 2390 { 2391 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2392 2393 g_free(spapr->kvm_type); 2394 } 2395 2396 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2397 { 2398 cpu_synchronize_state(cs); 2399 ppc_cpu_do_system_reset(cs); 2400 } 2401 2402 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2403 { 2404 CPUState *cs; 2405 2406 CPU_FOREACH(cs) { 2407 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2408 } 2409 } 2410 2411 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2412 uint32_t node, bool dedicated_hp_event_source, 2413 Error **errp) 2414 { 2415 sPAPRDRConnector *drc; 2416 sPAPRDRConnectorClass *drck; 2417 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2418 int i, fdt_offset, fdt_size; 2419 void *fdt; 2420 uint64_t addr = addr_start; 2421 2422 for (i = 0; i < nr_lmbs; i++) { 2423 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2424 addr/SPAPR_MEMORY_BLOCK_SIZE); 2425 g_assert(drc); 2426 2427 fdt = create_device_tree(&fdt_size); 2428 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2429 SPAPR_MEMORY_BLOCK_SIZE); 2430 2431 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2432 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2433 addr += SPAPR_MEMORY_BLOCK_SIZE; 2434 if (!dev->hotplugged) { 2435 /* guests expect coldplugged LMBs to be pre-allocated */ 2436 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2437 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2438 } 2439 } 2440 /* send hotplug notification to the 2441 * guest only in case of hotplugged memory 2442 */ 2443 if (dev->hotplugged) { 2444 if (dedicated_hp_event_source) { 2445 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2446 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2447 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2448 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2449 nr_lmbs, 2450 drck->get_index(drc)); 2451 } else { 2452 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2453 nr_lmbs); 2454 } 2455 } 2456 } 2457 2458 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2459 uint32_t node, Error **errp) 2460 { 2461 Error *local_err = NULL; 2462 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2463 PCDIMMDevice *dimm = PC_DIMM(dev); 2464 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2465 MemoryRegion *mr = ddc->get_memory_region(dimm); 2466 uint64_t align = memory_region_get_alignment(mr); 2467 uint64_t size = memory_region_size(mr); 2468 uint64_t addr; 2469 char *mem_dev; 2470 2471 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2472 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2473 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2474 goto out; 2475 } 2476 2477 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2478 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2479 error_setg(&local_err, "Memory backend has bad page size. " 2480 "Use 'memory-backend-file' with correct mem-path."); 2481 goto out; 2482 } 2483 2484 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2485 if (local_err) { 2486 goto out; 2487 } 2488 2489 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2490 if (local_err) { 2491 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2492 goto out; 2493 } 2494 2495 spapr_add_lmbs(dev, addr, size, node, 2496 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2497 &error_abort); 2498 2499 out: 2500 error_propagate(errp, local_err); 2501 } 2502 2503 typedef struct sPAPRDIMMState { 2504 uint32_t nr_lmbs; 2505 } sPAPRDIMMState; 2506 2507 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2508 { 2509 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2510 HotplugHandler *hotplug_ctrl; 2511 2512 if (--ds->nr_lmbs) { 2513 return; 2514 } 2515 2516 g_free(ds); 2517 2518 /* 2519 * Now that all the LMBs have been removed by the guest, call the 2520 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2521 */ 2522 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2523 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2524 } 2525 2526 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2527 Error **errp) 2528 { 2529 sPAPRDRConnector *drc; 2530 sPAPRDRConnectorClass *drck; 2531 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2532 int i; 2533 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2534 uint64_t addr = addr_start; 2535 2536 ds->nr_lmbs = nr_lmbs; 2537 for (i = 0; i < nr_lmbs; i++) { 2538 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2539 addr / SPAPR_MEMORY_BLOCK_SIZE); 2540 g_assert(drc); 2541 2542 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2543 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2544 addr += SPAPR_MEMORY_BLOCK_SIZE; 2545 } 2546 2547 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2548 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2549 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2550 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2551 nr_lmbs, 2552 drck->get_index(drc)); 2553 } 2554 2555 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2556 Error **errp) 2557 { 2558 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2559 PCDIMMDevice *dimm = PC_DIMM(dev); 2560 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2561 MemoryRegion *mr = ddc->get_memory_region(dimm); 2562 2563 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2564 object_unparent(OBJECT(dev)); 2565 } 2566 2567 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2568 DeviceState *dev, Error **errp) 2569 { 2570 Error *local_err = NULL; 2571 PCDIMMDevice *dimm = PC_DIMM(dev); 2572 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2573 MemoryRegion *mr = ddc->get_memory_region(dimm); 2574 uint64_t size = memory_region_size(mr); 2575 uint64_t addr; 2576 2577 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2578 if (local_err) { 2579 goto out; 2580 } 2581 2582 spapr_del_lmbs(dev, addr, size, &error_abort); 2583 out: 2584 error_propagate(errp, local_err); 2585 } 2586 2587 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2588 sPAPRMachineState *spapr) 2589 { 2590 PowerPCCPU *cpu = POWERPC_CPU(cs); 2591 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2592 int id = ppc_get_vcpu_dt_id(cpu); 2593 void *fdt; 2594 int offset, fdt_size; 2595 char *nodename; 2596 2597 fdt = create_device_tree(&fdt_size); 2598 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2599 offset = fdt_add_subnode(fdt, 0, nodename); 2600 2601 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2602 g_free(nodename); 2603 2604 *fdt_offset = offset; 2605 return fdt; 2606 } 2607 2608 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2609 Error **errp) 2610 { 2611 MachineState *ms = MACHINE(qdev_get_machine()); 2612 CPUCore *cc = CPU_CORE(dev); 2613 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2614 2615 core_slot->cpu = NULL; 2616 object_unparent(OBJECT(dev)); 2617 } 2618 2619 static void spapr_core_release(DeviceState *dev, void *opaque) 2620 { 2621 HotplugHandler *hotplug_ctrl; 2622 2623 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2624 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2625 } 2626 2627 static 2628 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2629 Error **errp) 2630 { 2631 int index; 2632 sPAPRDRConnector *drc; 2633 sPAPRDRConnectorClass *drck; 2634 Error *local_err = NULL; 2635 CPUCore *cc = CPU_CORE(dev); 2636 int smt = kvmppc_smt_threads(); 2637 2638 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2639 error_setg(errp, "Unable to find CPU core with core-id: %d", 2640 cc->core_id); 2641 return; 2642 } 2643 if (index == 0) { 2644 error_setg(errp, "Boot CPU core may not be unplugged"); 2645 return; 2646 } 2647 2648 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2649 g_assert(drc); 2650 2651 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2652 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2653 if (local_err) { 2654 error_propagate(errp, local_err); 2655 return; 2656 } 2657 2658 spapr_hotplug_req_remove_by_index(drc); 2659 } 2660 2661 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2662 Error **errp) 2663 { 2664 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2665 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2666 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2667 CPUCore *cc = CPU_CORE(dev); 2668 CPUState *cs = CPU(core->threads); 2669 sPAPRDRConnector *drc; 2670 Error *local_err = NULL; 2671 void *fdt = NULL; 2672 int fdt_offset = 0; 2673 int smt = kvmppc_smt_threads(); 2674 CPUArchId *core_slot; 2675 int index; 2676 2677 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2678 if (!core_slot) { 2679 error_setg(errp, "Unable to find CPU core with core-id: %d", 2680 cc->core_id); 2681 return; 2682 } 2683 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2684 2685 g_assert(drc || !mc->has_hotpluggable_cpus); 2686 2687 /* 2688 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2689 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2690 */ 2691 if (dev->hotplugged) { 2692 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2693 } 2694 2695 if (drc) { 2696 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2697 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2698 if (local_err) { 2699 g_free(fdt); 2700 error_propagate(errp, local_err); 2701 return; 2702 } 2703 } 2704 2705 if (dev->hotplugged) { 2706 /* 2707 * Send hotplug notification interrupt to the guest only in case 2708 * of hotplugged CPUs. 2709 */ 2710 spapr_hotplug_req_add_by_index(drc); 2711 } else { 2712 /* 2713 * Set the right DRC states for cold plugged CPU. 2714 */ 2715 if (drc) { 2716 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2717 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2718 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2719 } 2720 } 2721 core_slot->cpu = OBJECT(dev); 2722 } 2723 2724 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2725 Error **errp) 2726 { 2727 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2728 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2729 Error *local_err = NULL; 2730 CPUCore *cc = CPU_CORE(dev); 2731 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2732 const char *type = object_get_typename(OBJECT(dev)); 2733 CPUArchId *core_slot; 2734 int index; 2735 2736 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2737 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2738 goto out; 2739 } 2740 2741 if (strcmp(base_core_type, type)) { 2742 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2743 goto out; 2744 } 2745 2746 if (cc->core_id % smp_threads) { 2747 error_setg(&local_err, "invalid core id %d", cc->core_id); 2748 goto out; 2749 } 2750 2751 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2752 if (!core_slot) { 2753 error_setg(&local_err, "core id %d out of range", cc->core_id); 2754 goto out; 2755 } 2756 2757 if (core_slot->cpu) { 2758 error_setg(&local_err, "core %d already populated", cc->core_id); 2759 goto out; 2760 } 2761 2762 out: 2763 g_free(base_core_type); 2764 error_propagate(errp, local_err); 2765 } 2766 2767 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2768 DeviceState *dev, Error **errp) 2769 { 2770 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2771 2772 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2773 int node; 2774 2775 if (!smc->dr_lmb_enabled) { 2776 error_setg(errp, "Memory hotplug not supported for this machine"); 2777 return; 2778 } 2779 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2780 if (*errp) { 2781 return; 2782 } 2783 if (node < 0 || node >= MAX_NODES) { 2784 error_setg(errp, "Invaild node %d", node); 2785 return; 2786 } 2787 2788 /* 2789 * Currently PowerPC kernel doesn't allow hot-adding memory to 2790 * memory-less node, but instead will silently add the memory 2791 * to the first node that has some memory. This causes two 2792 * unexpected behaviours for the user. 2793 * 2794 * - Memory gets hotplugged to a different node than what the user 2795 * specified. 2796 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2797 * to memory-less node, a reboot will set things accordingly 2798 * and the previously hotplugged memory now ends in the right node. 2799 * This appears as if some memory moved from one node to another. 2800 * 2801 * So until kernel starts supporting memory hotplug to memory-less 2802 * nodes, just prevent such attempts upfront in QEMU. 2803 */ 2804 if (nb_numa_nodes && !numa_info[node].node_mem) { 2805 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2806 node); 2807 return; 2808 } 2809 2810 spapr_memory_plug(hotplug_dev, dev, node, errp); 2811 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2812 spapr_core_plug(hotplug_dev, dev, errp); 2813 } 2814 } 2815 2816 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2817 DeviceState *dev, Error **errp) 2818 { 2819 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2820 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2821 2822 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2823 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2824 spapr_memory_unplug(hotplug_dev, dev, errp); 2825 } else { 2826 error_setg(errp, "Memory hot unplug not supported for this guest"); 2827 } 2828 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2829 if (!mc->has_hotpluggable_cpus) { 2830 error_setg(errp, "CPU hot unplug not supported on this machine"); 2831 return; 2832 } 2833 spapr_core_unplug(hotplug_dev, dev, errp); 2834 } 2835 } 2836 2837 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2838 DeviceState *dev, Error **errp) 2839 { 2840 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2841 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2842 2843 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2844 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2845 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2846 } else { 2847 /* NOTE: this means there is a window after guest reset, prior to 2848 * CAS negotiation, where unplug requests will fail due to the 2849 * capability not being detected yet. This is a bit different than 2850 * the case with PCI unplug, where the events will be queued and 2851 * eventually handled by the guest after boot 2852 */ 2853 error_setg(errp, "Memory hot unplug not supported for this guest"); 2854 } 2855 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2856 if (!mc->has_hotpluggable_cpus) { 2857 error_setg(errp, "CPU hot unplug not supported on this machine"); 2858 return; 2859 } 2860 spapr_core_unplug_request(hotplug_dev, dev, errp); 2861 } 2862 } 2863 2864 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2865 DeviceState *dev, Error **errp) 2866 { 2867 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2868 spapr_core_pre_plug(hotplug_dev, dev, errp); 2869 } 2870 } 2871 2872 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2873 DeviceState *dev) 2874 { 2875 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2876 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2877 return HOTPLUG_HANDLER(machine); 2878 } 2879 return NULL; 2880 } 2881 2882 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2883 { 2884 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2885 * socket means much for the paravirtualized PAPR platform) */ 2886 return cpu_index / smp_threads / smp_cores; 2887 } 2888 2889 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 2890 { 2891 int i; 2892 int spapr_max_cores = max_cpus / smp_threads; 2893 MachineClass *mc = MACHINE_GET_CLASS(machine); 2894 2895 if (!mc->has_hotpluggable_cpus) { 2896 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 2897 } 2898 if (machine->possible_cpus) { 2899 assert(machine->possible_cpus->len == spapr_max_cores); 2900 return machine->possible_cpus; 2901 } 2902 2903 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2904 sizeof(CPUArchId) * spapr_max_cores); 2905 machine->possible_cpus->len = spapr_max_cores; 2906 for (i = 0; i < machine->possible_cpus->len; i++) { 2907 int core_id = i * smp_threads; 2908 2909 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 2910 machine->possible_cpus->cpus[i].arch_id = core_id; 2911 machine->possible_cpus->cpus[i].props.has_core_id = true; 2912 machine->possible_cpus->cpus[i].props.core_id = core_id; 2913 /* TODO: add 'has_node/node' here to describe 2914 to which node core belongs */ 2915 } 2916 return machine->possible_cpus; 2917 } 2918 2919 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2920 uint64_t *buid, hwaddr *pio, 2921 hwaddr *mmio32, hwaddr *mmio64, 2922 unsigned n_dma, uint32_t *liobns, Error **errp) 2923 { 2924 /* 2925 * New-style PHB window placement. 2926 * 2927 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2928 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2929 * windows. 2930 * 2931 * Some guest kernels can't work with MMIO windows above 1<<46 2932 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2933 * 2934 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2935 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2936 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2937 * 1TiB 64-bit MMIO windows for each PHB. 2938 */ 2939 const uint64_t base_buid = 0x800000020000000ULL; 2940 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 2941 SPAPR_PCI_MEM64_WIN_SIZE - 1) 2942 int i; 2943 2944 /* Sanity check natural alignments */ 2945 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2946 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2947 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2948 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2949 /* Sanity check bounds */ 2950 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 2951 SPAPR_PCI_MEM32_WIN_SIZE); 2952 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 2953 SPAPR_PCI_MEM64_WIN_SIZE); 2954 2955 if (index >= SPAPR_MAX_PHBS) { 2956 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 2957 SPAPR_MAX_PHBS - 1); 2958 return; 2959 } 2960 2961 *buid = base_buid + index; 2962 for (i = 0; i < n_dma; ++i) { 2963 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2964 } 2965 2966 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2967 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2968 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2969 } 2970 2971 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 2972 { 2973 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2974 2975 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 2976 } 2977 2978 static void spapr_ics_resend(XICSFabric *dev) 2979 { 2980 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2981 2982 ics_resend(spapr->ics); 2983 } 2984 2985 static ICPState *spapr_icp_get(XICSFabric *xi, int server) 2986 { 2987 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 2988 2989 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL; 2990 } 2991 2992 static void spapr_pic_print_info(InterruptStatsProvider *obj, 2993 Monitor *mon) 2994 { 2995 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2996 int i; 2997 2998 for (i = 0; i < spapr->nr_servers; i++) { 2999 icp_pic_print_info(&spapr->icps[i], mon); 3000 } 3001 3002 ics_pic_print_info(spapr->ics, mon); 3003 } 3004 3005 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3006 { 3007 MachineClass *mc = MACHINE_CLASS(oc); 3008 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3009 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3010 NMIClass *nc = NMI_CLASS(oc); 3011 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3012 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3013 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3014 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3015 3016 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3017 3018 /* 3019 * We set up the default / latest behaviour here. The class_init 3020 * functions for the specific versioned machine types can override 3021 * these details for backwards compatibility 3022 */ 3023 mc->init = ppc_spapr_init; 3024 mc->reset = ppc_spapr_reset; 3025 mc->block_default_type = IF_SCSI; 3026 mc->max_cpus = 1024; 3027 mc->no_parallel = 1; 3028 mc->default_boot_order = ""; 3029 mc->default_ram_size = 512 * M_BYTE; 3030 mc->kvm_type = spapr_kvm_type; 3031 mc->has_dynamic_sysbus = true; 3032 mc->pci_allow_0_address = true; 3033 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3034 hc->pre_plug = spapr_machine_device_pre_plug; 3035 hc->plug = spapr_machine_device_plug; 3036 hc->unplug = spapr_machine_device_unplug; 3037 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3038 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3039 hc->unplug_request = spapr_machine_device_unplug_request; 3040 3041 smc->dr_lmb_enabled = true; 3042 smc->tcg_default_cpu = "POWER8"; 3043 mc->has_hotpluggable_cpus = true; 3044 fwc->get_dev_path = spapr_get_fw_dev_path; 3045 nc->nmi_monitor_handler = spapr_nmi; 3046 smc->phb_placement = spapr_phb_placement; 3047 vhc->hypercall = emulate_spapr_hypercall; 3048 vhc->hpt_mask = spapr_hpt_mask; 3049 vhc->map_hptes = spapr_map_hptes; 3050 vhc->unmap_hptes = spapr_unmap_hptes; 3051 vhc->store_hpte = spapr_store_hpte; 3052 xic->ics_get = spapr_ics_get; 3053 xic->ics_resend = spapr_ics_resend; 3054 xic->icp_get = spapr_icp_get; 3055 ispc->print_info = spapr_pic_print_info; 3056 } 3057 3058 static const TypeInfo spapr_machine_info = { 3059 .name = TYPE_SPAPR_MACHINE, 3060 .parent = TYPE_MACHINE, 3061 .abstract = true, 3062 .instance_size = sizeof(sPAPRMachineState), 3063 .instance_init = spapr_machine_initfn, 3064 .instance_finalize = spapr_machine_finalizefn, 3065 .class_size = sizeof(sPAPRMachineClass), 3066 .class_init = spapr_machine_class_init, 3067 .interfaces = (InterfaceInfo[]) { 3068 { TYPE_FW_PATH_PROVIDER }, 3069 { TYPE_NMI }, 3070 { TYPE_HOTPLUG_HANDLER }, 3071 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3072 { TYPE_XICS_FABRIC }, 3073 { TYPE_INTERRUPT_STATS_PROVIDER }, 3074 { } 3075 }, 3076 }; 3077 3078 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3079 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3080 void *data) \ 3081 { \ 3082 MachineClass *mc = MACHINE_CLASS(oc); \ 3083 spapr_machine_##suffix##_class_options(mc); \ 3084 if (latest) { \ 3085 mc->alias = "pseries"; \ 3086 mc->is_default = 1; \ 3087 } \ 3088 } \ 3089 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3090 { \ 3091 MachineState *machine = MACHINE(obj); \ 3092 spapr_machine_##suffix##_instance_options(machine); \ 3093 } \ 3094 static const TypeInfo spapr_machine_##suffix##_info = { \ 3095 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3096 .parent = TYPE_SPAPR_MACHINE, \ 3097 .class_init = spapr_machine_##suffix##_class_init, \ 3098 .instance_init = spapr_machine_##suffix##_instance_init, \ 3099 }; \ 3100 static void spapr_machine_register_##suffix(void) \ 3101 { \ 3102 type_register(&spapr_machine_##suffix##_info); \ 3103 } \ 3104 type_init(spapr_machine_register_##suffix) 3105 3106 /* 3107 * pseries-2.9 3108 */ 3109 static void spapr_machine_2_9_instance_options(MachineState *machine) 3110 { 3111 } 3112 3113 static void spapr_machine_2_9_class_options(MachineClass *mc) 3114 { 3115 /* Defaults for the latest behaviour inherited from the base class */ 3116 } 3117 3118 DEFINE_SPAPR_MACHINE(2_9, "2.9", true); 3119 3120 /* 3121 * pseries-2.8 3122 */ 3123 #define SPAPR_COMPAT_2_8 \ 3124 HW_COMPAT_2_8 3125 3126 static void spapr_machine_2_8_instance_options(MachineState *machine) 3127 { 3128 spapr_machine_2_9_instance_options(machine); 3129 } 3130 3131 static void spapr_machine_2_8_class_options(MachineClass *mc) 3132 { 3133 spapr_machine_2_9_class_options(mc); 3134 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3135 } 3136 3137 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3138 3139 /* 3140 * pseries-2.7 3141 */ 3142 #define SPAPR_COMPAT_2_7 \ 3143 HW_COMPAT_2_7 \ 3144 { \ 3145 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3146 .property = "mem_win_size", \ 3147 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3148 }, \ 3149 { \ 3150 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3151 .property = "mem64_win_size", \ 3152 .value = "0", \ 3153 }, \ 3154 { \ 3155 .driver = TYPE_POWERPC_CPU, \ 3156 .property = "pre-2.8-migration", \ 3157 .value = "on", \ 3158 }, \ 3159 { \ 3160 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3161 .property = "pre-2.8-migration", \ 3162 .value = "on", \ 3163 }, 3164 3165 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3166 uint64_t *buid, hwaddr *pio, 3167 hwaddr *mmio32, hwaddr *mmio64, 3168 unsigned n_dma, uint32_t *liobns, Error **errp) 3169 { 3170 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3171 const uint64_t base_buid = 0x800000020000000ULL; 3172 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3173 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3174 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3175 const uint32_t max_index = 255; 3176 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3177 3178 uint64_t ram_top = MACHINE(spapr)->ram_size; 3179 hwaddr phb0_base, phb_base; 3180 int i; 3181 3182 /* Do we have hotpluggable memory? */ 3183 if (MACHINE(spapr)->maxram_size > ram_top) { 3184 /* Can't just use maxram_size, because there may be an 3185 * alignment gap between normal and hotpluggable memory 3186 * regions */ 3187 ram_top = spapr->hotplug_memory.base + 3188 memory_region_size(&spapr->hotplug_memory.mr); 3189 } 3190 3191 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3192 3193 if (index > max_index) { 3194 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3195 max_index); 3196 return; 3197 } 3198 3199 *buid = base_buid + index; 3200 for (i = 0; i < n_dma; ++i) { 3201 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3202 } 3203 3204 phb_base = phb0_base + index * phb_spacing; 3205 *pio = phb_base + pio_offset; 3206 *mmio32 = phb_base + mmio_offset; 3207 /* 3208 * We don't set the 64-bit MMIO window, relying on the PHB's 3209 * fallback behaviour of automatically splitting a large "32-bit" 3210 * window into contiguous 32-bit and 64-bit windows 3211 */ 3212 } 3213 3214 static void spapr_machine_2_7_instance_options(MachineState *machine) 3215 { 3216 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3217 3218 spapr_machine_2_8_instance_options(machine); 3219 spapr->use_hotplug_event_source = false; 3220 } 3221 3222 static void spapr_machine_2_7_class_options(MachineClass *mc) 3223 { 3224 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3225 3226 spapr_machine_2_8_class_options(mc); 3227 smc->tcg_default_cpu = "POWER7"; 3228 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3229 smc->phb_placement = phb_placement_2_7; 3230 } 3231 3232 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3233 3234 /* 3235 * pseries-2.6 3236 */ 3237 #define SPAPR_COMPAT_2_6 \ 3238 HW_COMPAT_2_6 \ 3239 { \ 3240 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3241 .property = "ddw",\ 3242 .value = stringify(off),\ 3243 }, 3244 3245 static void spapr_machine_2_6_instance_options(MachineState *machine) 3246 { 3247 spapr_machine_2_7_instance_options(machine); 3248 } 3249 3250 static void spapr_machine_2_6_class_options(MachineClass *mc) 3251 { 3252 spapr_machine_2_7_class_options(mc); 3253 mc->has_hotpluggable_cpus = false; 3254 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3255 } 3256 3257 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3258 3259 /* 3260 * pseries-2.5 3261 */ 3262 #define SPAPR_COMPAT_2_5 \ 3263 HW_COMPAT_2_5 \ 3264 { \ 3265 .driver = "spapr-vlan", \ 3266 .property = "use-rx-buffer-pools", \ 3267 .value = "off", \ 3268 }, 3269 3270 static void spapr_machine_2_5_instance_options(MachineState *machine) 3271 { 3272 spapr_machine_2_6_instance_options(machine); 3273 } 3274 3275 static void spapr_machine_2_5_class_options(MachineClass *mc) 3276 { 3277 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3278 3279 spapr_machine_2_6_class_options(mc); 3280 smc->use_ohci_by_default = true; 3281 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3282 } 3283 3284 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3285 3286 /* 3287 * pseries-2.4 3288 */ 3289 #define SPAPR_COMPAT_2_4 \ 3290 HW_COMPAT_2_4 3291 3292 static void spapr_machine_2_4_instance_options(MachineState *machine) 3293 { 3294 spapr_machine_2_5_instance_options(machine); 3295 } 3296 3297 static void spapr_machine_2_4_class_options(MachineClass *mc) 3298 { 3299 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3300 3301 spapr_machine_2_5_class_options(mc); 3302 smc->dr_lmb_enabled = false; 3303 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3304 } 3305 3306 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3307 3308 /* 3309 * pseries-2.3 3310 */ 3311 #define SPAPR_COMPAT_2_3 \ 3312 HW_COMPAT_2_3 \ 3313 {\ 3314 .driver = "spapr-pci-host-bridge",\ 3315 .property = "dynamic-reconfiguration",\ 3316 .value = "off",\ 3317 }, 3318 3319 static void spapr_machine_2_3_instance_options(MachineState *machine) 3320 { 3321 spapr_machine_2_4_instance_options(machine); 3322 savevm_skip_section_footers(); 3323 global_state_set_optional(); 3324 savevm_skip_configuration(); 3325 } 3326 3327 static void spapr_machine_2_3_class_options(MachineClass *mc) 3328 { 3329 spapr_machine_2_4_class_options(mc); 3330 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3331 } 3332 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3333 3334 /* 3335 * pseries-2.2 3336 */ 3337 3338 #define SPAPR_COMPAT_2_2 \ 3339 HW_COMPAT_2_2 \ 3340 {\ 3341 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3342 .property = "mem_win_size",\ 3343 .value = "0x20000000",\ 3344 }, 3345 3346 static void spapr_machine_2_2_instance_options(MachineState *machine) 3347 { 3348 spapr_machine_2_3_instance_options(machine); 3349 machine->suppress_vmdesc = true; 3350 } 3351 3352 static void spapr_machine_2_2_class_options(MachineClass *mc) 3353 { 3354 spapr_machine_2_3_class_options(mc); 3355 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3356 } 3357 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3358 3359 /* 3360 * pseries-2.1 3361 */ 3362 #define SPAPR_COMPAT_2_1 \ 3363 HW_COMPAT_2_1 3364 3365 static void spapr_machine_2_1_instance_options(MachineState *machine) 3366 { 3367 spapr_machine_2_2_instance_options(machine); 3368 } 3369 3370 static void spapr_machine_2_1_class_options(MachineClass *mc) 3371 { 3372 spapr_machine_2_2_class_options(mc); 3373 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3374 } 3375 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3376 3377 static void spapr_machine_register_types(void) 3378 { 3379 type_register_static(&spapr_machine_info); 3380 } 3381 3382 type_init(spapr_machine_register_types) 3383