1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "hw/mem/memory-device.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_XICP 0x00001111 100 101 /* These two functions implement the VCPU id numbering: one to compute them 102 * all and one to identify thread 0 of a VCORE. Any change to the first one 103 * is likely to have an impact on the second one, so let's keep them close. 104 */ 105 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 106 { 107 assert(spapr->vsmt); 108 return 109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 110 } 111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 112 PowerPCCPU *cpu) 113 { 114 assert(spapr->vsmt); 115 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 116 } 117 118 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 119 { 120 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 121 * and newer QEMUs don't even have them. In both cases, we don't want 122 * to send anything on the wire. 123 */ 124 return false; 125 } 126 127 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 128 .name = "icp/server", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .needed = pre_2_10_vmstate_dummy_icp_needed, 132 .fields = (VMStateField[]) { 133 VMSTATE_UNUSED(4), /* uint32_t xirr */ 134 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 135 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 136 VMSTATE_END_OF_LIST() 137 }, 138 }; 139 140 static void pre_2_10_vmstate_register_dummy_icp(int i) 141 { 142 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 143 (void *)(uintptr_t) i); 144 } 145 146 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 147 { 148 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 149 (void *)(uintptr_t) i); 150 } 151 152 int spapr_max_server_number(sPAPRMachineState *spapr) 153 { 154 assert(spapr->vsmt); 155 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 156 } 157 158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 159 int smt_threads) 160 { 161 int i, ret = 0; 162 uint32_t servers_prop[smt_threads]; 163 uint32_t gservers_prop[smt_threads * 2]; 164 int index = spapr_get_vcpu_id(cpu); 165 166 if (cpu->compat_pvr) { 167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 168 if (ret < 0) { 169 return ret; 170 } 171 } 172 173 /* Build interrupt servers and gservers properties */ 174 for (i = 0; i < smt_threads; i++) { 175 servers_prop[i] = cpu_to_be32(index + i); 176 /* Hack, direct the group queues back to cpu 0 */ 177 gservers_prop[i*2] = cpu_to_be32(index + i); 178 gservers_prop[i*2 + 1] = 0; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 181 servers_prop, sizeof(servers_prop)); 182 if (ret < 0) { 183 return ret; 184 } 185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 186 gservers_prop, sizeof(gservers_prop)); 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 192 { 193 int index = spapr_get_vcpu_id(cpu); 194 uint32_t associativity[] = {cpu_to_be32(0x5), 195 cpu_to_be32(0x0), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(cpu->node_id), 199 cpu_to_be32(index)}; 200 201 /* Advertise NUMA via ibm,associativity */ 202 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 203 sizeof(associativity)); 204 } 205 206 /* Populate the "ibm,pa-features" property */ 207 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset, 210 bool legacy_guest) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (legacy_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 287 { 288 int ret = 0, offset, cpus_offset; 289 CPUState *cs; 290 char cpu_model[32]; 291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 292 293 CPU_FOREACH(cs) { 294 PowerPCCPU *cpu = POWERPC_CPU(cs); 295 DeviceClass *dc = DEVICE_GET_CLASS(cs); 296 int index = spapr_get_vcpu_id(cpu); 297 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 298 299 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 300 continue; 301 } 302 303 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 304 305 cpus_offset = fdt_path_offset(fdt, "/cpus"); 306 if (cpus_offset < 0) { 307 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 308 if (cpus_offset < 0) { 309 return cpus_offset; 310 } 311 } 312 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 313 if (offset < 0) { 314 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 315 if (offset < 0) { 316 return offset; 317 } 318 } 319 320 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 321 pft_size_prop, sizeof(pft_size_prop)); 322 if (ret < 0) { 323 return ret; 324 } 325 326 if (nb_numa_nodes > 1) { 327 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 328 if (ret < 0) { 329 return ret; 330 } 331 } 332 333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 334 if (ret < 0) { 335 return ret; 336 } 337 338 spapr_populate_pa_features(spapr, cpu, fdt, offset, 339 spapr->cas_legacy_guest_workaround); 340 } 341 return ret; 342 } 343 344 static hwaddr spapr_node0_size(MachineState *machine) 345 { 346 if (nb_numa_nodes) { 347 int i; 348 for (i = 0; i < nb_numa_nodes; ++i) { 349 if (numa_info[i].node_mem) { 350 return MIN(pow2floor(numa_info[i].node_mem), 351 machine->ram_size); 352 } 353 } 354 } 355 return machine->ram_size; 356 } 357 358 static void add_str(GString *s, const gchar *s1) 359 { 360 g_string_append_len(s, s1, strlen(s1) + 1); 361 } 362 363 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 364 hwaddr size) 365 { 366 uint32_t associativity[] = { 367 cpu_to_be32(0x4), /* length */ 368 cpu_to_be32(0x0), cpu_to_be32(0x0), 369 cpu_to_be32(0x0), cpu_to_be32(nodeid) 370 }; 371 char mem_name[32]; 372 uint64_t mem_reg_property[2]; 373 int off; 374 375 mem_reg_property[0] = cpu_to_be64(start); 376 mem_reg_property[1] = cpu_to_be64(size); 377 378 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 379 off = fdt_add_subnode(fdt, 0, mem_name); 380 _FDT(off); 381 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 382 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 383 sizeof(mem_reg_property)))); 384 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 385 sizeof(associativity)))); 386 return off; 387 } 388 389 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 390 { 391 MachineState *machine = MACHINE(spapr); 392 hwaddr mem_start, node_size; 393 int i, nb_nodes = nb_numa_nodes; 394 NodeInfo *nodes = numa_info; 395 NodeInfo ramnode; 396 397 /* No NUMA nodes, assume there is just one node with whole RAM */ 398 if (!nb_numa_nodes) { 399 nb_nodes = 1; 400 ramnode.node_mem = machine->ram_size; 401 nodes = &ramnode; 402 } 403 404 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 405 if (!nodes[i].node_mem) { 406 continue; 407 } 408 if (mem_start >= machine->ram_size) { 409 node_size = 0; 410 } else { 411 node_size = nodes[i].node_mem; 412 if (node_size > machine->ram_size - mem_start) { 413 node_size = machine->ram_size - mem_start; 414 } 415 } 416 if (!mem_start) { 417 /* spapr_machine_init() checks for rma_size <= node0_size 418 * already */ 419 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 420 mem_start += spapr->rma_size; 421 node_size -= spapr->rma_size; 422 } 423 for ( ; node_size; ) { 424 hwaddr sizetmp = pow2floor(node_size); 425 426 /* mem_start != 0 here */ 427 if (ctzl(mem_start) < ctzl(sizetmp)) { 428 sizetmp = 1ULL << ctzl(mem_start); 429 } 430 431 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 432 node_size -= sizetmp; 433 mem_start += sizetmp; 434 } 435 } 436 437 return 0; 438 } 439 440 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 441 sPAPRMachineState *spapr) 442 { 443 PowerPCCPU *cpu = POWERPC_CPU(cs); 444 CPUPPCState *env = &cpu->env; 445 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 446 int index = spapr_get_vcpu_id(cpu); 447 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 448 0xffffffff, 0xffffffff}; 449 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 450 : SPAPR_TIMEBASE_FREQ; 451 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 452 uint32_t page_sizes_prop[64]; 453 size_t page_sizes_prop_size; 454 uint32_t vcpus_per_socket = smp_threads * smp_cores; 455 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 456 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 457 sPAPRDRConnector *drc; 458 int drc_index; 459 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 460 int i; 461 462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 463 if (drc) { 464 drc_index = spapr_drc_index(drc); 465 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 466 } 467 468 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 469 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 470 471 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 472 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 473 env->dcache_line_size))); 474 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 475 env->dcache_line_size))); 476 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 477 env->icache_line_size))); 478 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 479 env->icache_line_size))); 480 481 if (pcc->l1_dcache_size) { 482 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 483 pcc->l1_dcache_size))); 484 } else { 485 warn_report("Unknown L1 dcache size for cpu"); 486 } 487 if (pcc->l1_icache_size) { 488 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 489 pcc->l1_icache_size))); 490 } else { 491 warn_report("Unknown L1 icache size for cpu"); 492 } 493 494 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 497 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 499 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 500 501 if (env->spr_cb[SPR_PURR].oea_read) { 502 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 503 } 504 505 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 507 segs, sizeof(segs)))); 508 } 509 510 /* Advertise VSX (vector extensions) if available 511 * 1 == VMX / Altivec available 512 * 2 == VSX available 513 * 514 * Only CPUs for which we create core types in spapr_cpu_core.c 515 * are possible, and all of those have VMX */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 518 } else { 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 520 } 521 522 /* Advertise DFP (Decimal Floating Point) if available 523 * 0 / no property == no DFP 524 * 1 == DFP available */ 525 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 527 } 528 529 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 530 sizeof(page_sizes_prop)); 531 if (page_sizes_prop_size) { 532 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 533 page_sizes_prop, page_sizes_prop_size))); 534 } 535 536 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 537 538 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 539 cs->cpu_index / vcpus_per_socket))); 540 541 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 542 pft_size_prop, sizeof(pft_size_prop)))); 543 544 if (nb_numa_nodes > 1) { 545 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 546 } 547 548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 549 550 if (pcc->radix_page_info) { 551 for (i = 0; i < pcc->radix_page_info->count; i++) { 552 radix_AP_encodings[i] = 553 cpu_to_be32(pcc->radix_page_info->entries[i]); 554 } 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 556 radix_AP_encodings, 557 pcc->radix_page_info->count * 558 sizeof(radix_AP_encodings[0])))); 559 } 560 } 561 562 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 563 { 564 CPUState **rev; 565 CPUState *cs; 566 int n_cpus; 567 int cpus_offset; 568 char *nodename; 569 int i; 570 571 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 572 _FDT(cpus_offset); 573 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 575 576 /* 577 * We walk the CPUs in reverse order to ensure that CPU DT nodes 578 * created by fdt_add_subnode() end up in the right order in FDT 579 * for the guest kernel the enumerate the CPUs correctly. 580 * 581 * The CPU list cannot be traversed in reverse order, so we need 582 * to do extra work. 583 */ 584 n_cpus = 0; 585 rev = NULL; 586 CPU_FOREACH(cs) { 587 rev = g_renew(CPUState *, rev, n_cpus + 1); 588 rev[n_cpus++] = cs; 589 } 590 591 for (i = n_cpus - 1; i >= 0; i--) { 592 CPUState *cs = rev[i]; 593 PowerPCCPU *cpu = POWERPC_CPU(cs); 594 int index = spapr_get_vcpu_id(cpu); 595 DeviceClass *dc = DEVICE_GET_CLASS(cs); 596 int offset; 597 598 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 599 continue; 600 } 601 602 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 603 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 604 g_free(nodename); 605 _FDT(offset); 606 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 607 } 608 609 g_free(rev); 610 } 611 612 static int spapr_rng_populate_dt(void *fdt) 613 { 614 int node; 615 int ret; 616 617 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 618 if (node <= 0) { 619 return -1; 620 } 621 ret = fdt_setprop_string(fdt, node, "device_type", 622 "ibm,platform-facilities"); 623 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 624 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 625 626 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 627 if (node <= 0) { 628 return -1; 629 } 630 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 631 632 return ret ? -1 : 0; 633 } 634 635 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 636 { 637 MemoryDeviceInfoList *info; 638 639 for (info = list; info; info = info->next) { 640 MemoryDeviceInfo *value = info->value; 641 642 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 643 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 644 645 if (addr >= pcdimm_info->addr && 646 addr < (pcdimm_info->addr + pcdimm_info->size)) { 647 return pcdimm_info->node; 648 } 649 } 650 } 651 652 return -1; 653 } 654 655 struct sPAPRDrconfCellV2 { 656 uint32_t seq_lmbs; 657 uint64_t base_addr; 658 uint32_t drc_index; 659 uint32_t aa_index; 660 uint32_t flags; 661 } QEMU_PACKED; 662 663 typedef struct DrconfCellQueue { 664 struct sPAPRDrconfCellV2 cell; 665 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 666 } DrconfCellQueue; 667 668 static DrconfCellQueue * 669 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 670 uint32_t drc_index, uint32_t aa_index, 671 uint32_t flags) 672 { 673 DrconfCellQueue *elem; 674 675 elem = g_malloc0(sizeof(*elem)); 676 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 677 elem->cell.base_addr = cpu_to_be64(base_addr); 678 elem->cell.drc_index = cpu_to_be32(drc_index); 679 elem->cell.aa_index = cpu_to_be32(aa_index); 680 elem->cell.flags = cpu_to_be32(flags); 681 682 return elem; 683 } 684 685 /* ibm,dynamic-memory-v2 */ 686 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 687 int offset, MemoryDeviceInfoList *dimms) 688 { 689 MachineState *machine = MACHINE(spapr); 690 uint8_t *int_buf, *cur_index, buf_len; 691 int ret; 692 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 693 uint64_t addr, cur_addr, size; 694 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 695 uint64_t mem_end = machine->device_memory->base + 696 memory_region_size(&machine->device_memory->mr); 697 uint32_t node, nr_entries = 0; 698 sPAPRDRConnector *drc; 699 DrconfCellQueue *elem, *next; 700 MemoryDeviceInfoList *info; 701 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 702 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 703 704 /* Entry to cover RAM and the gap area */ 705 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 706 SPAPR_LMB_FLAGS_RESERVED | 707 SPAPR_LMB_FLAGS_DRC_INVALID); 708 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 709 nr_entries++; 710 711 cur_addr = machine->device_memory->base; 712 for (info = dimms; info; info = info->next) { 713 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 714 715 addr = di->addr; 716 size = di->size; 717 node = di->node; 718 719 /* Entry for hot-pluggable area */ 720 if (cur_addr < addr) { 721 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 722 g_assert(drc); 723 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 724 cur_addr, spapr_drc_index(drc), -1, 0); 725 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 726 nr_entries++; 727 } 728 729 /* Entry for DIMM */ 730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 731 g_assert(drc); 732 elem = spapr_get_drconf_cell(size / lmb_size, addr, 733 spapr_drc_index(drc), node, 734 SPAPR_LMB_FLAGS_ASSIGNED); 735 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 736 nr_entries++; 737 cur_addr = addr + size; 738 } 739 740 /* Entry for remaining hotpluggable area */ 741 if (cur_addr < mem_end) { 742 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 743 g_assert(drc); 744 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 745 cur_addr, spapr_drc_index(drc), -1, 0); 746 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 747 nr_entries++; 748 } 749 750 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 751 int_buf = cur_index = g_malloc0(buf_len); 752 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 753 cur_index += sizeof(nr_entries); 754 755 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 756 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 757 cur_index += sizeof(elem->cell); 758 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 759 g_free(elem); 760 } 761 762 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 763 g_free(int_buf); 764 if (ret < 0) { 765 return -1; 766 } 767 return 0; 768 } 769 770 /* ibm,dynamic-memory */ 771 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 772 int offset, MemoryDeviceInfoList *dimms) 773 { 774 MachineState *machine = MACHINE(spapr); 775 int i, ret; 776 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 777 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 778 uint32_t nr_lmbs = (machine->device_memory->base + 779 memory_region_size(&machine->device_memory->mr)) / 780 lmb_size; 781 uint32_t *int_buf, *cur_index, buf_len; 782 783 /* 784 * Allocate enough buffer size to fit in ibm,dynamic-memory 785 */ 786 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 787 cur_index = int_buf = g_malloc0(buf_len); 788 int_buf[0] = cpu_to_be32(nr_lmbs); 789 cur_index++; 790 for (i = 0; i < nr_lmbs; i++) { 791 uint64_t addr = i * lmb_size; 792 uint32_t *dynamic_memory = cur_index; 793 794 if (i >= device_lmb_start) { 795 sPAPRDRConnector *drc; 796 797 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 798 g_assert(drc); 799 800 dynamic_memory[0] = cpu_to_be32(addr >> 32); 801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 802 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 804 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 805 if (memory_region_present(get_system_memory(), addr)) { 806 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 807 } else { 808 dynamic_memory[5] = cpu_to_be32(0); 809 } 810 } else { 811 /* 812 * LMB information for RMA, boot time RAM and gap b/n RAM and 813 * device memory region -- all these are marked as reserved 814 * and as having no valid DRC. 815 */ 816 dynamic_memory[0] = cpu_to_be32(addr >> 32); 817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 818 dynamic_memory[2] = cpu_to_be32(0); 819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 820 dynamic_memory[4] = cpu_to_be32(-1); 821 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 822 SPAPR_LMB_FLAGS_DRC_INVALID); 823 } 824 825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 826 } 827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 828 g_free(int_buf); 829 if (ret < 0) { 830 return -1; 831 } 832 return 0; 833 } 834 835 /* 836 * Adds ibm,dynamic-reconfiguration-memory node. 837 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 838 * of this device tree node. 839 */ 840 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 841 { 842 MachineState *machine = MACHINE(spapr); 843 int ret, i, offset; 844 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 845 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 846 uint32_t *int_buf, *cur_index, buf_len; 847 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 848 MemoryDeviceInfoList *dimms = NULL; 849 850 /* 851 * Don't create the node if there is no device memory 852 */ 853 if (machine->ram_size == machine->maxram_size) { 854 return 0; 855 } 856 857 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 858 859 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 860 sizeof(prop_lmb_size)); 861 if (ret < 0) { 862 return ret; 863 } 864 865 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 866 if (ret < 0) { 867 return ret; 868 } 869 870 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 871 if (ret < 0) { 872 return ret; 873 } 874 875 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 876 dimms = qmp_memory_device_list(); 877 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 878 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 879 } else { 880 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 881 } 882 qapi_free_MemoryDeviceInfoList(dimms); 883 884 if (ret < 0) { 885 return ret; 886 } 887 888 /* ibm,associativity-lookup-arrays */ 889 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 890 cur_index = int_buf = g_malloc0(buf_len); 891 int_buf[0] = cpu_to_be32(nr_nodes); 892 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 893 cur_index += 2; 894 for (i = 0; i < nr_nodes; i++) { 895 uint32_t associativity[] = { 896 cpu_to_be32(0x0), 897 cpu_to_be32(0x0), 898 cpu_to_be32(0x0), 899 cpu_to_be32(i) 900 }; 901 memcpy(cur_index, associativity, sizeof(associativity)); 902 cur_index += 4; 903 } 904 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 905 (cur_index - int_buf) * sizeof(uint32_t)); 906 g_free(int_buf); 907 908 return ret; 909 } 910 911 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 912 sPAPROptionVector *ov5_updates) 913 { 914 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 915 int ret = 0, offset; 916 917 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 918 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 919 g_assert(smc->dr_lmb_enabled); 920 ret = spapr_populate_drconf_memory(spapr, fdt); 921 if (ret) { 922 goto out; 923 } 924 } 925 926 offset = fdt_path_offset(fdt, "/chosen"); 927 if (offset < 0) { 928 offset = fdt_add_subnode(fdt, 0, "chosen"); 929 if (offset < 0) { 930 return offset; 931 } 932 } 933 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 934 "ibm,architecture-vec-5"); 935 936 out: 937 return ret; 938 } 939 940 static bool spapr_hotplugged_dev_before_cas(void) 941 { 942 Object *drc_container, *obj; 943 ObjectProperty *prop; 944 ObjectPropertyIterator iter; 945 946 drc_container = container_get(object_get_root(), "/dr-connector"); 947 object_property_iter_init(&iter, drc_container); 948 while ((prop = object_property_iter_next(&iter))) { 949 if (!strstart(prop->type, "link<", NULL)) { 950 continue; 951 } 952 obj = object_property_get_link(drc_container, prop->name, NULL); 953 if (spapr_drc_needed(obj)) { 954 return true; 955 } 956 } 957 return false; 958 } 959 960 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 961 target_ulong addr, target_ulong size, 962 sPAPROptionVector *ov5_updates) 963 { 964 void *fdt, *fdt_skel; 965 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 966 967 if (spapr_hotplugged_dev_before_cas()) { 968 return 1; 969 } 970 971 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 972 error_report("SLOF provided an unexpected CAS buffer size " 973 TARGET_FMT_lu " (min: %zu, max: %u)", 974 size, sizeof(hdr), FW_MAX_SIZE); 975 exit(EXIT_FAILURE); 976 } 977 978 size -= sizeof(hdr); 979 980 /* Create skeleton */ 981 fdt_skel = g_malloc0(size); 982 _FDT((fdt_create(fdt_skel, size))); 983 _FDT((fdt_finish_reservemap(fdt_skel))); 984 _FDT((fdt_begin_node(fdt_skel, ""))); 985 _FDT((fdt_end_node(fdt_skel))); 986 _FDT((fdt_finish(fdt_skel))); 987 fdt = g_malloc0(size); 988 _FDT((fdt_open_into(fdt_skel, fdt, size))); 989 g_free(fdt_skel); 990 991 /* Fixup cpu nodes */ 992 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 993 994 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 995 return -1; 996 } 997 998 /* Pack resulting tree */ 999 _FDT((fdt_pack(fdt))); 1000 1001 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1002 trace_spapr_cas_failed(size); 1003 return -1; 1004 } 1005 1006 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1007 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1008 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1009 g_free(fdt); 1010 1011 return 0; 1012 } 1013 1014 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1015 { 1016 int rtas; 1017 GString *hypertas = g_string_sized_new(256); 1018 GString *qemu_hypertas = g_string_sized_new(256); 1019 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1020 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1021 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1022 uint32_t lrdr_capacity[] = { 1023 cpu_to_be32(max_device_addr >> 32), 1024 cpu_to_be32(max_device_addr & 0xffffffff), 1025 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1026 cpu_to_be32(max_cpus / smp_threads), 1027 }; 1028 uint32_t maxdomains[] = { 1029 cpu_to_be32(4), 1030 cpu_to_be32(0), 1031 cpu_to_be32(0), 1032 cpu_to_be32(0), 1033 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1), 1034 }; 1035 1036 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1037 1038 /* hypertas */ 1039 add_str(hypertas, "hcall-pft"); 1040 add_str(hypertas, "hcall-term"); 1041 add_str(hypertas, "hcall-dabr"); 1042 add_str(hypertas, "hcall-interrupt"); 1043 add_str(hypertas, "hcall-tce"); 1044 add_str(hypertas, "hcall-vio"); 1045 add_str(hypertas, "hcall-splpar"); 1046 add_str(hypertas, "hcall-bulk"); 1047 add_str(hypertas, "hcall-set-mode"); 1048 add_str(hypertas, "hcall-sprg0"); 1049 add_str(hypertas, "hcall-copy"); 1050 add_str(hypertas, "hcall-debug"); 1051 add_str(hypertas, "hcall-vphn"); 1052 add_str(qemu_hypertas, "hcall-memop1"); 1053 1054 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1055 add_str(hypertas, "hcall-multi-tce"); 1056 } 1057 1058 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1059 add_str(hypertas, "hcall-hpt-resize"); 1060 } 1061 1062 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1063 hypertas->str, hypertas->len)); 1064 g_string_free(hypertas, TRUE); 1065 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1066 qemu_hypertas->str, qemu_hypertas->len)); 1067 g_string_free(qemu_hypertas, TRUE); 1068 1069 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1070 refpoints, sizeof(refpoints))); 1071 1072 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1073 maxdomains, sizeof(maxdomains))); 1074 1075 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1076 RTAS_ERROR_LOG_MAX)); 1077 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1078 RTAS_EVENT_SCAN_RATE)); 1079 1080 g_assert(msi_nonbroken); 1081 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1082 1083 /* 1084 * According to PAPR, rtas ibm,os-term does not guarantee a return 1085 * back to the guest cpu. 1086 * 1087 * While an additional ibm,extended-os-term property indicates 1088 * that rtas call return will always occur. Set this property. 1089 */ 1090 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1091 1092 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1093 lrdr_capacity, sizeof(lrdr_capacity))); 1094 1095 spapr_dt_rtas_tokens(fdt, rtas); 1096 } 1097 1098 /* 1099 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1100 * and the XIVE features that the guest may request and thus the valid 1101 * values for bytes 23..26 of option vector 5: 1102 */ 1103 static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt, 1104 int chosen) 1105 { 1106 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1107 1108 char val[2 * 4] = { 1109 23, spapr->irq->ov5, /* Xive mode. */ 1110 24, 0x00, /* Hash/Radix, filled in below. */ 1111 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1112 26, 0x40, /* Radix options: GTSE == yes. */ 1113 }; 1114 1115 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1116 first_ppc_cpu->compat_pvr)) { 1117 /* 1118 * If we're in a pre POWER9 compat mode then the guest should 1119 * do hash and use the legacy interrupt mode 1120 */ 1121 val[1] = 0x00; /* XICS */ 1122 val[3] = 0x00; /* Hash */ 1123 } else if (kvm_enabled()) { 1124 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1125 val[3] = 0x80; /* OV5_MMU_BOTH */ 1126 } else if (kvmppc_has_cap_mmu_radix()) { 1127 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1128 } else { 1129 val[3] = 0x00; /* Hash */ 1130 } 1131 } else { 1132 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1133 val[3] = 0xC0; 1134 } 1135 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1136 val, sizeof(val))); 1137 } 1138 1139 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1140 { 1141 MachineState *machine = MACHINE(spapr); 1142 int chosen; 1143 const char *boot_device = machine->boot_order; 1144 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1145 size_t cb = 0; 1146 char *bootlist = get_boot_devices_list(&cb); 1147 1148 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1149 1150 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1151 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1152 spapr->initrd_base)); 1153 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1154 spapr->initrd_base + spapr->initrd_size)); 1155 1156 if (spapr->kernel_size) { 1157 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1158 cpu_to_be64(spapr->kernel_size) }; 1159 1160 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1161 &kprop, sizeof(kprop))); 1162 if (spapr->kernel_le) { 1163 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1164 } 1165 } 1166 if (boot_menu) { 1167 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1168 } 1169 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1170 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1171 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1172 1173 if (cb && bootlist) { 1174 int i; 1175 1176 for (i = 0; i < cb; i++) { 1177 if (bootlist[i] == '\n') { 1178 bootlist[i] = ' '; 1179 } 1180 } 1181 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1182 } 1183 1184 if (boot_device && strlen(boot_device)) { 1185 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1186 } 1187 1188 if (!spapr->has_graphics && stdout_path) { 1189 /* 1190 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1191 * kernel. New platforms should only use the "stdout-path" property. Set 1192 * the new property and continue using older property to remain 1193 * compatible with the existing firmware. 1194 */ 1195 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1196 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1197 } 1198 1199 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1200 1201 g_free(stdout_path); 1202 g_free(bootlist); 1203 } 1204 1205 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1206 { 1207 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1208 * KVM to work under pHyp with some guest co-operation */ 1209 int hypervisor; 1210 uint8_t hypercall[16]; 1211 1212 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1213 /* indicate KVM hypercall interface */ 1214 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1215 if (kvmppc_has_cap_fixup_hcalls()) { 1216 /* 1217 * Older KVM versions with older guest kernels were broken 1218 * with the magic page, don't allow the guest to map it. 1219 */ 1220 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1221 sizeof(hypercall))) { 1222 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1223 hypercall, sizeof(hypercall))); 1224 } 1225 } 1226 } 1227 1228 static void *spapr_build_fdt(sPAPRMachineState *spapr) 1229 { 1230 MachineState *machine = MACHINE(spapr); 1231 MachineClass *mc = MACHINE_GET_CLASS(machine); 1232 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1233 int ret; 1234 void *fdt; 1235 sPAPRPHBState *phb; 1236 char *buf; 1237 1238 fdt = g_malloc0(FDT_MAX_SIZE); 1239 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1240 1241 /* Root node */ 1242 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1243 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1244 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1245 1246 /* 1247 * Add info to guest to indentify which host is it being run on 1248 * and what is the uuid of the guest 1249 */ 1250 if (kvmppc_get_host_model(&buf)) { 1251 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1252 g_free(buf); 1253 } 1254 if (kvmppc_get_host_serial(&buf)) { 1255 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1256 g_free(buf); 1257 } 1258 1259 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1260 1261 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1262 if (qemu_uuid_set) { 1263 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1264 } 1265 g_free(buf); 1266 1267 if (qemu_get_vm_name()) { 1268 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1269 qemu_get_vm_name())); 1270 } 1271 1272 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1273 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1274 1275 /* /interrupt controller */ 1276 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, 1277 PHANDLE_XICP); 1278 1279 ret = spapr_populate_memory(spapr, fdt); 1280 if (ret < 0) { 1281 error_report("couldn't setup memory nodes in fdt"); 1282 exit(1); 1283 } 1284 1285 /* /vdevice */ 1286 spapr_dt_vdevice(spapr->vio_bus, fdt); 1287 1288 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1289 ret = spapr_rng_populate_dt(fdt); 1290 if (ret < 0) { 1291 error_report("could not set up rng device in the fdt"); 1292 exit(1); 1293 } 1294 } 1295 1296 QLIST_FOREACH(phb, &spapr->phbs, list) { 1297 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, 1298 spapr->irq->nr_msis); 1299 if (ret < 0) { 1300 error_report("couldn't setup PCI devices in fdt"); 1301 exit(1); 1302 } 1303 } 1304 1305 /* cpus */ 1306 spapr_populate_cpus_dt_node(fdt, spapr); 1307 1308 if (smc->dr_lmb_enabled) { 1309 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1310 } 1311 1312 if (mc->has_hotpluggable_cpus) { 1313 int offset = fdt_path_offset(fdt, "/cpus"); 1314 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1315 SPAPR_DR_CONNECTOR_TYPE_CPU); 1316 if (ret < 0) { 1317 error_report("Couldn't set up CPU DR device tree properties"); 1318 exit(1); 1319 } 1320 } 1321 1322 /* /event-sources */ 1323 spapr_dt_events(spapr, fdt); 1324 1325 /* /rtas */ 1326 spapr_dt_rtas(spapr, fdt); 1327 1328 /* /chosen */ 1329 spapr_dt_chosen(spapr, fdt); 1330 1331 /* /hypervisor */ 1332 if (kvm_enabled()) { 1333 spapr_dt_hypervisor(spapr, fdt); 1334 } 1335 1336 /* Build memory reserve map */ 1337 if (spapr->kernel_size) { 1338 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1339 } 1340 if (spapr->initrd_size) { 1341 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1342 } 1343 1344 /* ibm,client-architecture-support updates */ 1345 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1346 if (ret < 0) { 1347 error_report("couldn't setup CAS properties fdt"); 1348 exit(1); 1349 } 1350 1351 return fdt; 1352 } 1353 1354 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1355 { 1356 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1357 } 1358 1359 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1360 PowerPCCPU *cpu) 1361 { 1362 CPUPPCState *env = &cpu->env; 1363 1364 /* The TCG path should also be holding the BQL at this point */ 1365 g_assert(qemu_mutex_iothread_locked()); 1366 1367 if (msr_pr) { 1368 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1369 env->gpr[3] = H_PRIVILEGE; 1370 } else { 1371 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1372 } 1373 } 1374 1375 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1376 { 1377 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1378 1379 return spapr->patb_entry; 1380 } 1381 1382 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1383 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1384 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1385 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1386 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1387 1388 /* 1389 * Get the fd to access the kernel htab, re-opening it if necessary 1390 */ 1391 static int get_htab_fd(sPAPRMachineState *spapr) 1392 { 1393 Error *local_err = NULL; 1394 1395 if (spapr->htab_fd >= 0) { 1396 return spapr->htab_fd; 1397 } 1398 1399 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1400 if (spapr->htab_fd < 0) { 1401 error_report_err(local_err); 1402 } 1403 1404 return spapr->htab_fd; 1405 } 1406 1407 void close_htab_fd(sPAPRMachineState *spapr) 1408 { 1409 if (spapr->htab_fd >= 0) { 1410 close(spapr->htab_fd); 1411 } 1412 spapr->htab_fd = -1; 1413 } 1414 1415 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1416 { 1417 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1418 1419 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1420 } 1421 1422 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1423 { 1424 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1425 1426 assert(kvm_enabled()); 1427 1428 if (!spapr->htab) { 1429 return 0; 1430 } 1431 1432 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1433 } 1434 1435 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1436 hwaddr ptex, int n) 1437 { 1438 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1439 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1440 1441 if (!spapr->htab) { 1442 /* 1443 * HTAB is controlled by KVM. Fetch into temporary buffer 1444 */ 1445 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1446 kvmppc_read_hptes(hptes, ptex, n); 1447 return hptes; 1448 } 1449 1450 /* 1451 * HTAB is controlled by QEMU. Just point to the internally 1452 * accessible PTEG. 1453 */ 1454 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1455 } 1456 1457 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1458 const ppc_hash_pte64_t *hptes, 1459 hwaddr ptex, int n) 1460 { 1461 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1462 1463 if (!spapr->htab) { 1464 g_free((void *)hptes); 1465 } 1466 1467 /* Nothing to do for qemu managed HPT */ 1468 } 1469 1470 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1471 uint64_t pte0, uint64_t pte1) 1472 { 1473 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1474 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1475 1476 if (!spapr->htab) { 1477 kvmppc_write_hpte(ptex, pte0, pte1); 1478 } else { 1479 stq_p(spapr->htab + offset, pte0); 1480 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1481 } 1482 } 1483 1484 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1485 { 1486 int shift; 1487 1488 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1489 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1490 * that's much more than is needed for Linux guests */ 1491 shift = ctz64(pow2ceil(ramsize)) - 7; 1492 shift = MAX(shift, 18); /* Minimum architected size */ 1493 shift = MIN(shift, 46); /* Maximum architected size */ 1494 return shift; 1495 } 1496 1497 void spapr_free_hpt(sPAPRMachineState *spapr) 1498 { 1499 g_free(spapr->htab); 1500 spapr->htab = NULL; 1501 spapr->htab_shift = 0; 1502 close_htab_fd(spapr); 1503 } 1504 1505 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1506 Error **errp) 1507 { 1508 long rc; 1509 1510 /* Clean up any HPT info from a previous boot */ 1511 spapr_free_hpt(spapr); 1512 1513 rc = kvmppc_reset_htab(shift); 1514 if (rc < 0) { 1515 /* kernel-side HPT needed, but couldn't allocate one */ 1516 error_setg_errno(errp, errno, 1517 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1518 shift); 1519 /* This is almost certainly fatal, but if the caller really 1520 * wants to carry on with shift == 0, it's welcome to try */ 1521 } else if (rc > 0) { 1522 /* kernel-side HPT allocated */ 1523 if (rc != shift) { 1524 error_setg(errp, 1525 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1526 shift, rc); 1527 } 1528 1529 spapr->htab_shift = shift; 1530 spapr->htab = NULL; 1531 } else { 1532 /* kernel-side HPT not needed, allocate in userspace instead */ 1533 size_t size = 1ULL << shift; 1534 int i; 1535 1536 spapr->htab = qemu_memalign(size, size); 1537 if (!spapr->htab) { 1538 error_setg_errno(errp, errno, 1539 "Could not allocate HPT of order %d", shift); 1540 return; 1541 } 1542 1543 memset(spapr->htab, 0, size); 1544 spapr->htab_shift = shift; 1545 1546 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1547 DIRTY_HPTE(HPTE(spapr->htab, i)); 1548 } 1549 } 1550 /* We're setting up a hash table, so that means we're not radix */ 1551 spapr->patb_entry = 0; 1552 } 1553 1554 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1555 { 1556 int hpt_shift; 1557 1558 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1559 || (spapr->cas_reboot 1560 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1561 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1562 } else { 1563 uint64_t current_ram_size; 1564 1565 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1566 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1567 } 1568 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1569 1570 if (spapr->vrma_adjust) { 1571 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1572 spapr->htab_shift); 1573 } 1574 } 1575 1576 static int spapr_reset_drcs(Object *child, void *opaque) 1577 { 1578 sPAPRDRConnector *drc = 1579 (sPAPRDRConnector *) object_dynamic_cast(child, 1580 TYPE_SPAPR_DR_CONNECTOR); 1581 1582 if (drc) { 1583 spapr_drc_reset(drc); 1584 } 1585 1586 return 0; 1587 } 1588 1589 static void spapr_machine_reset(void) 1590 { 1591 MachineState *machine = MACHINE(qdev_get_machine()); 1592 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1593 PowerPCCPU *first_ppc_cpu; 1594 uint32_t rtas_limit; 1595 hwaddr rtas_addr, fdt_addr; 1596 void *fdt; 1597 int rc; 1598 1599 spapr_caps_apply(spapr); 1600 1601 first_ppc_cpu = POWERPC_CPU(first_cpu); 1602 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1603 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1604 spapr->max_compat_pvr)) { 1605 /* If using KVM with radix mode available, VCPUs can be started 1606 * without a HPT because KVM will start them in radix mode. 1607 * Set the GR bit in PATB so that we know there is no HPT. */ 1608 spapr->patb_entry = PATBE1_GR; 1609 } else { 1610 spapr_setup_hpt_and_vrma(spapr); 1611 } 1612 1613 /* if this reset wasn't generated by CAS, we should reset our 1614 * negotiated options and start from scratch */ 1615 if (!spapr->cas_reboot) { 1616 spapr_ovec_cleanup(spapr->ov5_cas); 1617 spapr->ov5_cas = spapr_ovec_new(); 1618 1619 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1620 } 1621 1622 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1623 spapr_irq_msi_reset(spapr); 1624 } 1625 1626 qemu_devices_reset(); 1627 1628 /* 1629 * This is fixing some of the default configuration of the XIVE 1630 * devices. To be called after the reset of the machine devices. 1631 */ 1632 spapr_irq_reset(spapr, &error_fatal); 1633 1634 /* DRC reset may cause a device to be unplugged. This will cause troubles 1635 * if this device is used by another device (eg, a running vhost backend 1636 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1637 * situations, we reset DRCs after all devices have been reset. 1638 */ 1639 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1640 1641 spapr_clear_pending_events(spapr); 1642 1643 /* 1644 * We place the device tree and RTAS just below either the top of the RMA, 1645 * or just below 2GB, whichever is lower, so that it can be 1646 * processed with 32-bit real mode code if necessary 1647 */ 1648 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1649 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1650 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1651 1652 fdt = spapr_build_fdt(spapr); 1653 1654 spapr_load_rtas(spapr, fdt, rtas_addr); 1655 1656 rc = fdt_pack(fdt); 1657 1658 /* Should only fail if we've built a corrupted tree */ 1659 assert(rc == 0); 1660 1661 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1662 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1663 fdt_totalsize(fdt), FDT_MAX_SIZE); 1664 exit(1); 1665 } 1666 1667 /* Load the fdt */ 1668 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1669 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1670 g_free(spapr->fdt_blob); 1671 spapr->fdt_size = fdt_totalsize(fdt); 1672 spapr->fdt_initial_size = spapr->fdt_size; 1673 spapr->fdt_blob = fdt; 1674 1675 /* Set up the entry state */ 1676 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1677 first_ppc_cpu->env.gpr[5] = 0; 1678 1679 spapr->cas_reboot = false; 1680 } 1681 1682 static void spapr_create_nvram(sPAPRMachineState *spapr) 1683 { 1684 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1685 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1686 1687 if (dinfo) { 1688 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1689 &error_fatal); 1690 } 1691 1692 qdev_init_nofail(dev); 1693 1694 spapr->nvram = (struct sPAPRNVRAM *)dev; 1695 } 1696 1697 static void spapr_rtc_create(sPAPRMachineState *spapr) 1698 { 1699 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1700 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1701 &error_fatal); 1702 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1703 &error_fatal); 1704 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1705 "date", &error_fatal); 1706 } 1707 1708 /* Returns whether we want to use VGA or not */ 1709 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1710 { 1711 switch (vga_interface_type) { 1712 case VGA_NONE: 1713 return false; 1714 case VGA_DEVICE: 1715 return true; 1716 case VGA_STD: 1717 case VGA_VIRTIO: 1718 case VGA_CIRRUS: 1719 return pci_vga_init(pci_bus) != NULL; 1720 default: 1721 error_setg(errp, 1722 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1723 return false; 1724 } 1725 } 1726 1727 static int spapr_pre_load(void *opaque) 1728 { 1729 int rc; 1730 1731 rc = spapr_caps_pre_load(opaque); 1732 if (rc) { 1733 return rc; 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int spapr_post_load(void *opaque, int version_id) 1740 { 1741 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1742 int err = 0; 1743 1744 err = spapr_caps_post_migration(spapr); 1745 if (err) { 1746 return err; 1747 } 1748 1749 /* 1750 * In earlier versions, there was no separate qdev for the PAPR 1751 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1752 * So when migrating from those versions, poke the incoming offset 1753 * value into the RTC device 1754 */ 1755 if (version_id < 3) { 1756 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1757 if (err) { 1758 return err; 1759 } 1760 } 1761 1762 if (kvm_enabled() && spapr->patb_entry) { 1763 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1764 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1765 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1766 1767 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1768 if (err) { 1769 error_report("Process table config unsupported by the host"); 1770 return -EINVAL; 1771 } 1772 } 1773 1774 err = spapr_irq_post_load(spapr, version_id); 1775 if (err) { 1776 return err; 1777 } 1778 1779 return err; 1780 } 1781 1782 static int spapr_pre_save(void *opaque) 1783 { 1784 int rc; 1785 1786 rc = spapr_caps_pre_save(opaque); 1787 if (rc) { 1788 return rc; 1789 } 1790 1791 return 0; 1792 } 1793 1794 static bool version_before_3(void *opaque, int version_id) 1795 { 1796 return version_id < 3; 1797 } 1798 1799 static bool spapr_pending_events_needed(void *opaque) 1800 { 1801 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1802 return !QTAILQ_EMPTY(&spapr->pending_events); 1803 } 1804 1805 static const VMStateDescription vmstate_spapr_event_entry = { 1806 .name = "spapr_event_log_entry", 1807 .version_id = 1, 1808 .minimum_version_id = 1, 1809 .fields = (VMStateField[]) { 1810 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1811 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1812 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1813 NULL, extended_length), 1814 VMSTATE_END_OF_LIST() 1815 }, 1816 }; 1817 1818 static const VMStateDescription vmstate_spapr_pending_events = { 1819 .name = "spapr_pending_events", 1820 .version_id = 1, 1821 .minimum_version_id = 1, 1822 .needed = spapr_pending_events_needed, 1823 .fields = (VMStateField[]) { 1824 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1825 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1826 VMSTATE_END_OF_LIST() 1827 }, 1828 }; 1829 1830 static bool spapr_ov5_cas_needed(void *opaque) 1831 { 1832 sPAPRMachineState *spapr = opaque; 1833 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1834 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1835 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1836 bool cas_needed; 1837 1838 /* Prior to the introduction of sPAPROptionVector, we had two option 1839 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1840 * Both of these options encode machine topology into the device-tree 1841 * in such a way that the now-booted OS should still be able to interact 1842 * appropriately with QEMU regardless of what options were actually 1843 * negotiatied on the source side. 1844 * 1845 * As such, we can avoid migrating the CAS-negotiated options if these 1846 * are the only options available on the current machine/platform. 1847 * Since these are the only options available for pseries-2.7 and 1848 * earlier, this allows us to maintain old->new/new->old migration 1849 * compatibility. 1850 * 1851 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1852 * via default pseries-2.8 machines and explicit command-line parameters. 1853 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1854 * of the actual CAS-negotiated values to continue working properly. For 1855 * example, availability of memory unplug depends on knowing whether 1856 * OV5_HP_EVT was negotiated via CAS. 1857 * 1858 * Thus, for any cases where the set of available CAS-negotiatable 1859 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1860 * include the CAS-negotiated options in the migration stream, unless 1861 * if they affect boot time behaviour only. 1862 */ 1863 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1864 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1865 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1866 1867 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1868 * the mask itself since in the future it's possible "legacy" bits may be 1869 * removed via machine options, which could generate a false positive 1870 * that breaks migration. 1871 */ 1872 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1873 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1874 1875 spapr_ovec_cleanup(ov5_mask); 1876 spapr_ovec_cleanup(ov5_legacy); 1877 spapr_ovec_cleanup(ov5_removed); 1878 1879 return cas_needed; 1880 } 1881 1882 static const VMStateDescription vmstate_spapr_ov5_cas = { 1883 .name = "spapr_option_vector_ov5_cas", 1884 .version_id = 1, 1885 .minimum_version_id = 1, 1886 .needed = spapr_ov5_cas_needed, 1887 .fields = (VMStateField[]) { 1888 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1889 vmstate_spapr_ovec, sPAPROptionVector), 1890 VMSTATE_END_OF_LIST() 1891 }, 1892 }; 1893 1894 static bool spapr_patb_entry_needed(void *opaque) 1895 { 1896 sPAPRMachineState *spapr = opaque; 1897 1898 return !!spapr->patb_entry; 1899 } 1900 1901 static const VMStateDescription vmstate_spapr_patb_entry = { 1902 .name = "spapr_patb_entry", 1903 .version_id = 1, 1904 .minimum_version_id = 1, 1905 .needed = spapr_patb_entry_needed, 1906 .fields = (VMStateField[]) { 1907 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1908 VMSTATE_END_OF_LIST() 1909 }, 1910 }; 1911 1912 static bool spapr_irq_map_needed(void *opaque) 1913 { 1914 sPAPRMachineState *spapr = opaque; 1915 1916 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1917 } 1918 1919 static const VMStateDescription vmstate_spapr_irq_map = { 1920 .name = "spapr_irq_map", 1921 .version_id = 1, 1922 .minimum_version_id = 1, 1923 .needed = spapr_irq_map_needed, 1924 .fields = (VMStateField[]) { 1925 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 1926 VMSTATE_END_OF_LIST() 1927 }, 1928 }; 1929 1930 static bool spapr_dtb_needed(void *opaque) 1931 { 1932 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1933 1934 return smc->update_dt_enabled; 1935 } 1936 1937 static int spapr_dtb_pre_load(void *opaque) 1938 { 1939 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1940 1941 g_free(spapr->fdt_blob); 1942 spapr->fdt_blob = NULL; 1943 spapr->fdt_size = 0; 1944 1945 return 0; 1946 } 1947 1948 static const VMStateDescription vmstate_spapr_dtb = { 1949 .name = "spapr_dtb", 1950 .version_id = 1, 1951 .minimum_version_id = 1, 1952 .needed = spapr_dtb_needed, 1953 .pre_load = spapr_dtb_pre_load, 1954 .fields = (VMStateField[]) { 1955 VMSTATE_UINT32(fdt_initial_size, sPAPRMachineState), 1956 VMSTATE_UINT32(fdt_size, sPAPRMachineState), 1957 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, sPAPRMachineState, 0, NULL, 1958 fdt_size), 1959 VMSTATE_END_OF_LIST() 1960 }, 1961 }; 1962 1963 static const VMStateDescription vmstate_spapr = { 1964 .name = "spapr", 1965 .version_id = 3, 1966 .minimum_version_id = 1, 1967 .pre_load = spapr_pre_load, 1968 .post_load = spapr_post_load, 1969 .pre_save = spapr_pre_save, 1970 .fields = (VMStateField[]) { 1971 /* used to be @next_irq */ 1972 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1973 1974 /* RTC offset */ 1975 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1976 1977 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1978 VMSTATE_END_OF_LIST() 1979 }, 1980 .subsections = (const VMStateDescription*[]) { 1981 &vmstate_spapr_ov5_cas, 1982 &vmstate_spapr_patb_entry, 1983 &vmstate_spapr_pending_events, 1984 &vmstate_spapr_cap_htm, 1985 &vmstate_spapr_cap_vsx, 1986 &vmstate_spapr_cap_dfp, 1987 &vmstate_spapr_cap_cfpc, 1988 &vmstate_spapr_cap_sbbc, 1989 &vmstate_spapr_cap_ibs, 1990 &vmstate_spapr_irq_map, 1991 &vmstate_spapr_cap_nested_kvm_hv, 1992 &vmstate_spapr_dtb, 1993 NULL 1994 } 1995 }; 1996 1997 static int htab_save_setup(QEMUFile *f, void *opaque) 1998 { 1999 sPAPRMachineState *spapr = opaque; 2000 2001 /* "Iteration" header */ 2002 if (!spapr->htab_shift) { 2003 qemu_put_be32(f, -1); 2004 } else { 2005 qemu_put_be32(f, spapr->htab_shift); 2006 } 2007 2008 if (spapr->htab) { 2009 spapr->htab_save_index = 0; 2010 spapr->htab_first_pass = true; 2011 } else { 2012 if (spapr->htab_shift) { 2013 assert(kvm_enabled()); 2014 } 2015 } 2016 2017 2018 return 0; 2019 } 2020 2021 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 2022 int chunkstart, int n_valid, int n_invalid) 2023 { 2024 qemu_put_be32(f, chunkstart); 2025 qemu_put_be16(f, n_valid); 2026 qemu_put_be16(f, n_invalid); 2027 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2028 HASH_PTE_SIZE_64 * n_valid); 2029 } 2030 2031 static void htab_save_end_marker(QEMUFile *f) 2032 { 2033 qemu_put_be32(f, 0); 2034 qemu_put_be16(f, 0); 2035 qemu_put_be16(f, 0); 2036 } 2037 2038 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 2039 int64_t max_ns) 2040 { 2041 bool has_timeout = max_ns != -1; 2042 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2043 int index = spapr->htab_save_index; 2044 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2045 2046 assert(spapr->htab_first_pass); 2047 2048 do { 2049 int chunkstart; 2050 2051 /* Consume invalid HPTEs */ 2052 while ((index < htabslots) 2053 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2054 CLEAN_HPTE(HPTE(spapr->htab, index)); 2055 index++; 2056 } 2057 2058 /* Consume valid HPTEs */ 2059 chunkstart = index; 2060 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2061 && HPTE_VALID(HPTE(spapr->htab, index))) { 2062 CLEAN_HPTE(HPTE(spapr->htab, index)); 2063 index++; 2064 } 2065 2066 if (index > chunkstart) { 2067 int n_valid = index - chunkstart; 2068 2069 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2070 2071 if (has_timeout && 2072 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2073 break; 2074 } 2075 } 2076 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2077 2078 if (index >= htabslots) { 2079 assert(index == htabslots); 2080 index = 0; 2081 spapr->htab_first_pass = false; 2082 } 2083 spapr->htab_save_index = index; 2084 } 2085 2086 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2087 int64_t max_ns) 2088 { 2089 bool final = max_ns < 0; 2090 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2091 int examined = 0, sent = 0; 2092 int index = spapr->htab_save_index; 2093 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2094 2095 assert(!spapr->htab_first_pass); 2096 2097 do { 2098 int chunkstart, invalidstart; 2099 2100 /* Consume non-dirty HPTEs */ 2101 while ((index < htabslots) 2102 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2103 index++; 2104 examined++; 2105 } 2106 2107 chunkstart = index; 2108 /* Consume valid dirty HPTEs */ 2109 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2110 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2111 && HPTE_VALID(HPTE(spapr->htab, index))) { 2112 CLEAN_HPTE(HPTE(spapr->htab, index)); 2113 index++; 2114 examined++; 2115 } 2116 2117 invalidstart = index; 2118 /* Consume invalid dirty HPTEs */ 2119 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2120 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2121 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2122 CLEAN_HPTE(HPTE(spapr->htab, index)); 2123 index++; 2124 examined++; 2125 } 2126 2127 if (index > chunkstart) { 2128 int n_valid = invalidstart - chunkstart; 2129 int n_invalid = index - invalidstart; 2130 2131 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2132 sent += index - chunkstart; 2133 2134 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2135 break; 2136 } 2137 } 2138 2139 if (examined >= htabslots) { 2140 break; 2141 } 2142 2143 if (index >= htabslots) { 2144 assert(index == htabslots); 2145 index = 0; 2146 } 2147 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2148 2149 if (index >= htabslots) { 2150 assert(index == htabslots); 2151 index = 0; 2152 } 2153 2154 spapr->htab_save_index = index; 2155 2156 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2157 } 2158 2159 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2160 #define MAX_KVM_BUF_SIZE 2048 2161 2162 static int htab_save_iterate(QEMUFile *f, void *opaque) 2163 { 2164 sPAPRMachineState *spapr = opaque; 2165 int fd; 2166 int rc = 0; 2167 2168 /* Iteration header */ 2169 if (!spapr->htab_shift) { 2170 qemu_put_be32(f, -1); 2171 return 1; 2172 } else { 2173 qemu_put_be32(f, 0); 2174 } 2175 2176 if (!spapr->htab) { 2177 assert(kvm_enabled()); 2178 2179 fd = get_htab_fd(spapr); 2180 if (fd < 0) { 2181 return fd; 2182 } 2183 2184 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2185 if (rc < 0) { 2186 return rc; 2187 } 2188 } else if (spapr->htab_first_pass) { 2189 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2190 } else { 2191 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2192 } 2193 2194 htab_save_end_marker(f); 2195 2196 return rc; 2197 } 2198 2199 static int htab_save_complete(QEMUFile *f, void *opaque) 2200 { 2201 sPAPRMachineState *spapr = opaque; 2202 int fd; 2203 2204 /* Iteration header */ 2205 if (!spapr->htab_shift) { 2206 qemu_put_be32(f, -1); 2207 return 0; 2208 } else { 2209 qemu_put_be32(f, 0); 2210 } 2211 2212 if (!spapr->htab) { 2213 int rc; 2214 2215 assert(kvm_enabled()); 2216 2217 fd = get_htab_fd(spapr); 2218 if (fd < 0) { 2219 return fd; 2220 } 2221 2222 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2223 if (rc < 0) { 2224 return rc; 2225 } 2226 } else { 2227 if (spapr->htab_first_pass) { 2228 htab_save_first_pass(f, spapr, -1); 2229 } 2230 htab_save_later_pass(f, spapr, -1); 2231 } 2232 2233 /* End marker */ 2234 htab_save_end_marker(f); 2235 2236 return 0; 2237 } 2238 2239 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2240 { 2241 sPAPRMachineState *spapr = opaque; 2242 uint32_t section_hdr; 2243 int fd = -1; 2244 Error *local_err = NULL; 2245 2246 if (version_id < 1 || version_id > 1) { 2247 error_report("htab_load() bad version"); 2248 return -EINVAL; 2249 } 2250 2251 section_hdr = qemu_get_be32(f); 2252 2253 if (section_hdr == -1) { 2254 spapr_free_hpt(spapr); 2255 return 0; 2256 } 2257 2258 if (section_hdr) { 2259 /* First section gives the htab size */ 2260 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2261 if (local_err) { 2262 error_report_err(local_err); 2263 return -EINVAL; 2264 } 2265 return 0; 2266 } 2267 2268 if (!spapr->htab) { 2269 assert(kvm_enabled()); 2270 2271 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2272 if (fd < 0) { 2273 error_report_err(local_err); 2274 return fd; 2275 } 2276 } 2277 2278 while (true) { 2279 uint32_t index; 2280 uint16_t n_valid, n_invalid; 2281 2282 index = qemu_get_be32(f); 2283 n_valid = qemu_get_be16(f); 2284 n_invalid = qemu_get_be16(f); 2285 2286 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2287 /* End of Stream */ 2288 break; 2289 } 2290 2291 if ((index + n_valid + n_invalid) > 2292 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2293 /* Bad index in stream */ 2294 error_report( 2295 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2296 index, n_valid, n_invalid, spapr->htab_shift); 2297 return -EINVAL; 2298 } 2299 2300 if (spapr->htab) { 2301 if (n_valid) { 2302 qemu_get_buffer(f, HPTE(spapr->htab, index), 2303 HASH_PTE_SIZE_64 * n_valid); 2304 } 2305 if (n_invalid) { 2306 memset(HPTE(spapr->htab, index + n_valid), 0, 2307 HASH_PTE_SIZE_64 * n_invalid); 2308 } 2309 } else { 2310 int rc; 2311 2312 assert(fd >= 0); 2313 2314 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2315 if (rc < 0) { 2316 return rc; 2317 } 2318 } 2319 } 2320 2321 if (!spapr->htab) { 2322 assert(fd >= 0); 2323 close(fd); 2324 } 2325 2326 return 0; 2327 } 2328 2329 static void htab_save_cleanup(void *opaque) 2330 { 2331 sPAPRMachineState *spapr = opaque; 2332 2333 close_htab_fd(spapr); 2334 } 2335 2336 static SaveVMHandlers savevm_htab_handlers = { 2337 .save_setup = htab_save_setup, 2338 .save_live_iterate = htab_save_iterate, 2339 .save_live_complete_precopy = htab_save_complete, 2340 .save_cleanup = htab_save_cleanup, 2341 .load_state = htab_load, 2342 }; 2343 2344 static void spapr_boot_set(void *opaque, const char *boot_device, 2345 Error **errp) 2346 { 2347 MachineState *machine = MACHINE(opaque); 2348 machine->boot_order = g_strdup(boot_device); 2349 } 2350 2351 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2352 { 2353 MachineState *machine = MACHINE(spapr); 2354 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2355 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2356 int i; 2357 2358 for (i = 0; i < nr_lmbs; i++) { 2359 uint64_t addr; 2360 2361 addr = i * lmb_size + machine->device_memory->base; 2362 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2363 addr / lmb_size); 2364 } 2365 } 2366 2367 /* 2368 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2369 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2370 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2371 */ 2372 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2373 { 2374 int i; 2375 2376 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2377 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2378 " is not aligned to %" PRIu64 " MiB", 2379 machine->ram_size, 2380 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2381 return; 2382 } 2383 2384 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2385 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2386 " is not aligned to %" PRIu64 " MiB", 2387 machine->ram_size, 2388 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2389 return; 2390 } 2391 2392 for (i = 0; i < nb_numa_nodes; i++) { 2393 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2394 error_setg(errp, 2395 "Node %d memory size 0x%" PRIx64 2396 " is not aligned to %" PRIu64 " MiB", 2397 i, numa_info[i].node_mem, 2398 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2399 return; 2400 } 2401 } 2402 } 2403 2404 /* find cpu slot in machine->possible_cpus by core_id */ 2405 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2406 { 2407 int index = id / smp_threads; 2408 2409 if (index >= ms->possible_cpus->len) { 2410 return NULL; 2411 } 2412 if (idx) { 2413 *idx = index; 2414 } 2415 return &ms->possible_cpus->cpus[index]; 2416 } 2417 2418 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2419 { 2420 Error *local_err = NULL; 2421 bool vsmt_user = !!spapr->vsmt; 2422 int kvm_smt = kvmppc_smt_threads(); 2423 int ret; 2424 2425 if (!kvm_enabled() && (smp_threads > 1)) { 2426 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2427 "on a pseries machine"); 2428 goto out; 2429 } 2430 if (!is_power_of_2(smp_threads)) { 2431 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2432 "machine because it must be a power of 2", smp_threads); 2433 goto out; 2434 } 2435 2436 /* Detemine the VSMT mode to use: */ 2437 if (vsmt_user) { 2438 if (spapr->vsmt < smp_threads) { 2439 error_setg(&local_err, "Cannot support VSMT mode %d" 2440 " because it must be >= threads/core (%d)", 2441 spapr->vsmt, smp_threads); 2442 goto out; 2443 } 2444 /* In this case, spapr->vsmt has been set by the command line */ 2445 } else { 2446 /* 2447 * Default VSMT value is tricky, because we need it to be as 2448 * consistent as possible (for migration), but this requires 2449 * changing it for at least some existing cases. We pick 8 as 2450 * the value that we'd get with KVM on POWER8, the 2451 * overwhelmingly common case in production systems. 2452 */ 2453 spapr->vsmt = MAX(8, smp_threads); 2454 } 2455 2456 /* KVM: If necessary, set the SMT mode: */ 2457 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2458 ret = kvmppc_set_smt_threads(spapr->vsmt); 2459 if (ret) { 2460 /* Looks like KVM isn't able to change VSMT mode */ 2461 error_setg(&local_err, 2462 "Failed to set KVM's VSMT mode to %d (errno %d)", 2463 spapr->vsmt, ret); 2464 /* We can live with that if the default one is big enough 2465 * for the number of threads, and a submultiple of the one 2466 * we want. In this case we'll waste some vcpu ids, but 2467 * behaviour will be correct */ 2468 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2469 warn_report_err(local_err); 2470 local_err = NULL; 2471 goto out; 2472 } else { 2473 if (!vsmt_user) { 2474 error_append_hint(&local_err, 2475 "On PPC, a VM with %d threads/core" 2476 " on a host with %d threads/core" 2477 " requires the use of VSMT mode %d.\n", 2478 smp_threads, kvm_smt, spapr->vsmt); 2479 } 2480 kvmppc_hint_smt_possible(&local_err); 2481 goto out; 2482 } 2483 } 2484 } 2485 /* else TCG: nothing to do currently */ 2486 out: 2487 error_propagate(errp, local_err); 2488 } 2489 2490 static void spapr_init_cpus(sPAPRMachineState *spapr) 2491 { 2492 MachineState *machine = MACHINE(spapr); 2493 MachineClass *mc = MACHINE_GET_CLASS(machine); 2494 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2495 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2496 const CPUArchIdList *possible_cpus; 2497 int boot_cores_nr = smp_cpus / smp_threads; 2498 int i; 2499 2500 possible_cpus = mc->possible_cpu_arch_ids(machine); 2501 if (mc->has_hotpluggable_cpus) { 2502 if (smp_cpus % smp_threads) { 2503 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2504 smp_cpus, smp_threads); 2505 exit(1); 2506 } 2507 if (max_cpus % smp_threads) { 2508 error_report("max_cpus (%u) must be multiple of threads (%u)", 2509 max_cpus, smp_threads); 2510 exit(1); 2511 } 2512 } else { 2513 if (max_cpus != smp_cpus) { 2514 error_report("This machine version does not support CPU hotplug"); 2515 exit(1); 2516 } 2517 boot_cores_nr = possible_cpus->len; 2518 } 2519 2520 if (smc->pre_2_10_has_unused_icps) { 2521 int i; 2522 2523 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2524 /* Dummy entries get deregistered when real ICPState objects 2525 * are registered during CPU core hotplug. 2526 */ 2527 pre_2_10_vmstate_register_dummy_icp(i); 2528 } 2529 } 2530 2531 for (i = 0; i < possible_cpus->len; i++) { 2532 int core_id = i * smp_threads; 2533 2534 if (mc->has_hotpluggable_cpus) { 2535 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2536 spapr_vcpu_id(spapr, core_id)); 2537 } 2538 2539 if (i < boot_cores_nr) { 2540 Object *core = object_new(type); 2541 int nr_threads = smp_threads; 2542 2543 /* Handle the partially filled core for older machine types */ 2544 if ((i + 1) * smp_threads >= smp_cpus) { 2545 nr_threads = smp_cpus - i * smp_threads; 2546 } 2547 2548 object_property_set_int(core, nr_threads, "nr-threads", 2549 &error_fatal); 2550 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2551 &error_fatal); 2552 object_property_set_bool(core, true, "realized", &error_fatal); 2553 2554 object_unref(core); 2555 } 2556 } 2557 } 2558 2559 static PCIHostState *spapr_create_default_phb(void) 2560 { 2561 DeviceState *dev; 2562 2563 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2564 qdev_prop_set_uint32(dev, "index", 0); 2565 qdev_init_nofail(dev); 2566 2567 return PCI_HOST_BRIDGE(dev); 2568 } 2569 2570 /* pSeries LPAR / sPAPR hardware init */ 2571 static void spapr_machine_init(MachineState *machine) 2572 { 2573 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2574 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2575 const char *kernel_filename = machine->kernel_filename; 2576 const char *initrd_filename = machine->initrd_filename; 2577 PCIHostState *phb; 2578 int i; 2579 MemoryRegion *sysmem = get_system_memory(); 2580 MemoryRegion *ram = g_new(MemoryRegion, 1); 2581 hwaddr node0_size = spapr_node0_size(machine); 2582 long load_limit, fw_size; 2583 char *filename; 2584 Error *resize_hpt_err = NULL; 2585 2586 msi_nonbroken = true; 2587 2588 QLIST_INIT(&spapr->phbs); 2589 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2590 2591 /* Determine capabilities to run with */ 2592 spapr_caps_init(spapr); 2593 2594 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2595 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2596 /* 2597 * If the user explicitly requested a mode we should either 2598 * supply it, or fail completely (which we do below). But if 2599 * it's not set explicitly, we reset our mode to something 2600 * that works 2601 */ 2602 if (resize_hpt_err) { 2603 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2604 error_free(resize_hpt_err); 2605 resize_hpt_err = NULL; 2606 } else { 2607 spapr->resize_hpt = smc->resize_hpt_default; 2608 } 2609 } 2610 2611 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2612 2613 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2614 /* 2615 * User requested HPT resize, but this host can't supply it. Bail out 2616 */ 2617 error_report_err(resize_hpt_err); 2618 exit(1); 2619 } 2620 2621 spapr->rma_size = node0_size; 2622 2623 /* With KVM, we don't actually know whether KVM supports an 2624 * unbounded RMA (PR KVM) or is limited by the hash table size 2625 * (HV KVM using VRMA), so we always assume the latter 2626 * 2627 * In that case, we also limit the initial allocations for RTAS 2628 * etc... to 256M since we have no way to know what the VRMA size 2629 * is going to be as it depends on the size of the hash table 2630 * which isn't determined yet. 2631 */ 2632 if (kvm_enabled()) { 2633 spapr->vrma_adjust = 1; 2634 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2635 } 2636 2637 /* Actually we don't support unbounded RMA anymore since we added 2638 * proper emulation of HV mode. The max we can get is 16G which 2639 * also happens to be what we configure for PAPR mode so make sure 2640 * we don't do anything bigger than that 2641 */ 2642 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2643 2644 if (spapr->rma_size > node0_size) { 2645 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2646 spapr->rma_size); 2647 exit(1); 2648 } 2649 2650 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2651 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2652 2653 /* 2654 * VSMT must be set in order to be able to compute VCPU ids, ie to 2655 * call spapr_max_server_number() or spapr_vcpu_id(). 2656 */ 2657 spapr_set_vsmt_mode(spapr, &error_fatal); 2658 2659 /* Set up Interrupt Controller before we create the VCPUs */ 2660 spapr_irq_init(spapr, &error_fatal); 2661 2662 /* Set up containers for ibm,client-architecture-support negotiated options 2663 */ 2664 spapr->ov5 = spapr_ovec_new(); 2665 spapr->ov5_cas = spapr_ovec_new(); 2666 2667 if (smc->dr_lmb_enabled) { 2668 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2669 spapr_validate_node_memory(machine, &error_fatal); 2670 } 2671 2672 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2673 2674 /* advertise support for dedicated HP event source to guests */ 2675 if (spapr->use_hotplug_event_source) { 2676 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2677 } 2678 2679 /* advertise support for HPT resizing */ 2680 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2681 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2682 } 2683 2684 /* advertise support for ibm,dyamic-memory-v2 */ 2685 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2686 2687 /* advertise XIVE on POWER9 machines */ 2688 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { 2689 if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 2690 0, spapr->max_compat_pvr)) { 2691 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2692 } else if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { 2693 error_report("XIVE-only machines require a POWER9 CPU"); 2694 exit(1); 2695 } 2696 } 2697 2698 /* init CPUs */ 2699 spapr_init_cpus(spapr); 2700 2701 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2702 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2703 spapr->max_compat_pvr)) { 2704 /* KVM and TCG always allow GTSE with radix... */ 2705 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2706 } 2707 /* ... but not with hash (currently). */ 2708 2709 if (kvm_enabled()) { 2710 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2711 kvmppc_enable_logical_ci_hcalls(); 2712 kvmppc_enable_set_mode_hcall(); 2713 2714 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2715 kvmppc_enable_clear_ref_mod_hcalls(); 2716 } 2717 2718 /* allocate RAM */ 2719 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2720 machine->ram_size); 2721 memory_region_add_subregion(sysmem, 0, ram); 2722 2723 /* always allocate the device memory information */ 2724 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2725 2726 /* initialize hotplug memory address space */ 2727 if (machine->ram_size < machine->maxram_size) { 2728 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2729 /* 2730 * Limit the number of hotpluggable memory slots to half the number 2731 * slots that KVM supports, leaving the other half for PCI and other 2732 * devices. However ensure that number of slots doesn't drop below 32. 2733 */ 2734 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2735 SPAPR_MAX_RAM_SLOTS; 2736 2737 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2738 max_memslots = SPAPR_MAX_RAM_SLOTS; 2739 } 2740 if (machine->ram_slots > max_memslots) { 2741 error_report("Specified number of memory slots %" 2742 PRIu64" exceeds max supported %d", 2743 machine->ram_slots, max_memslots); 2744 exit(1); 2745 } 2746 2747 machine->device_memory->base = ROUND_UP(machine->ram_size, 2748 SPAPR_DEVICE_MEM_ALIGN); 2749 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2750 "device-memory", device_mem_size); 2751 memory_region_add_subregion(sysmem, machine->device_memory->base, 2752 &machine->device_memory->mr); 2753 } 2754 2755 if (smc->dr_lmb_enabled) { 2756 spapr_create_lmb_dr_connectors(spapr); 2757 } 2758 2759 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2760 if (!filename) { 2761 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2762 exit(1); 2763 } 2764 spapr->rtas_size = get_image_size(filename); 2765 if (spapr->rtas_size < 0) { 2766 error_report("Could not get size of LPAR rtas '%s'", filename); 2767 exit(1); 2768 } 2769 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2770 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2771 error_report("Could not load LPAR rtas '%s'", filename); 2772 exit(1); 2773 } 2774 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2775 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2776 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2777 exit(1); 2778 } 2779 g_free(filename); 2780 2781 /* Set up RTAS event infrastructure */ 2782 spapr_events_init(spapr); 2783 2784 /* Set up the RTC RTAS interfaces */ 2785 spapr_rtc_create(spapr); 2786 2787 /* Set up VIO bus */ 2788 spapr->vio_bus = spapr_vio_bus_init(); 2789 2790 for (i = 0; i < serial_max_hds(); i++) { 2791 if (serial_hd(i)) { 2792 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2793 } 2794 } 2795 2796 /* We always have at least the nvram device on VIO */ 2797 spapr_create_nvram(spapr); 2798 2799 /* Set up PCI */ 2800 spapr_pci_rtas_init(); 2801 2802 phb = spapr_create_default_phb(); 2803 2804 for (i = 0; i < nb_nics; i++) { 2805 NICInfo *nd = &nd_table[i]; 2806 2807 if (!nd->model) { 2808 nd->model = g_strdup("spapr-vlan"); 2809 } 2810 2811 if (g_str_equal(nd->model, "spapr-vlan") || 2812 g_str_equal(nd->model, "ibmveth")) { 2813 spapr_vlan_create(spapr->vio_bus, nd); 2814 } else { 2815 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2816 } 2817 } 2818 2819 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2820 spapr_vscsi_create(spapr->vio_bus); 2821 } 2822 2823 /* Graphics */ 2824 if (spapr_vga_init(phb->bus, &error_fatal)) { 2825 spapr->has_graphics = true; 2826 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2827 } 2828 2829 if (machine->usb) { 2830 if (smc->use_ohci_by_default) { 2831 pci_create_simple(phb->bus, -1, "pci-ohci"); 2832 } else { 2833 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2834 } 2835 2836 if (spapr->has_graphics) { 2837 USBBus *usb_bus = usb_bus_find(-1); 2838 2839 usb_create_simple(usb_bus, "usb-kbd"); 2840 usb_create_simple(usb_bus, "usb-mouse"); 2841 } 2842 } 2843 2844 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2845 error_report( 2846 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2847 MIN_RMA_SLOF); 2848 exit(1); 2849 } 2850 2851 if (kernel_filename) { 2852 uint64_t lowaddr = 0; 2853 2854 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2855 NULL, NULL, &lowaddr, NULL, 1, 2856 PPC_ELF_MACHINE, 0, 0); 2857 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2858 spapr->kernel_size = load_elf(kernel_filename, 2859 translate_kernel_address, NULL, NULL, 2860 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2861 0, 0); 2862 spapr->kernel_le = spapr->kernel_size > 0; 2863 } 2864 if (spapr->kernel_size < 0) { 2865 error_report("error loading %s: %s", kernel_filename, 2866 load_elf_strerror(spapr->kernel_size)); 2867 exit(1); 2868 } 2869 2870 /* load initrd */ 2871 if (initrd_filename) { 2872 /* Try to locate the initrd in the gap between the kernel 2873 * and the firmware. Add a bit of space just in case 2874 */ 2875 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2876 + 0x1ffff) & ~0xffff; 2877 spapr->initrd_size = load_image_targphys(initrd_filename, 2878 spapr->initrd_base, 2879 load_limit 2880 - spapr->initrd_base); 2881 if (spapr->initrd_size < 0) { 2882 error_report("could not load initial ram disk '%s'", 2883 initrd_filename); 2884 exit(1); 2885 } 2886 } 2887 } 2888 2889 if (bios_name == NULL) { 2890 bios_name = FW_FILE_NAME; 2891 } 2892 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2893 if (!filename) { 2894 error_report("Could not find LPAR firmware '%s'", bios_name); 2895 exit(1); 2896 } 2897 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2898 if (fw_size <= 0) { 2899 error_report("Could not load LPAR firmware '%s'", filename); 2900 exit(1); 2901 } 2902 g_free(filename); 2903 2904 /* FIXME: Should register things through the MachineState's qdev 2905 * interface, this is a legacy from the sPAPREnvironment structure 2906 * which predated MachineState but had a similar function */ 2907 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2908 register_savevm_live(NULL, "spapr/htab", -1, 1, 2909 &savevm_htab_handlers, spapr); 2910 2911 qemu_register_boot_set(spapr_boot_set, spapr); 2912 2913 if (kvm_enabled()) { 2914 /* to stop and start vmclock */ 2915 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2916 &spapr->tb); 2917 2918 kvmppc_spapr_enable_inkernel_multitce(); 2919 } 2920 } 2921 2922 static int spapr_kvm_type(const char *vm_type) 2923 { 2924 if (!vm_type) { 2925 return 0; 2926 } 2927 2928 if (!strcmp(vm_type, "HV")) { 2929 return 1; 2930 } 2931 2932 if (!strcmp(vm_type, "PR")) { 2933 return 2; 2934 } 2935 2936 error_report("Unknown kvm-type specified '%s'", vm_type); 2937 exit(1); 2938 } 2939 2940 /* 2941 * Implementation of an interface to adjust firmware path 2942 * for the bootindex property handling. 2943 */ 2944 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2945 DeviceState *dev) 2946 { 2947 #define CAST(type, obj, name) \ 2948 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2949 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2950 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2951 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2952 2953 if (d) { 2954 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2955 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2956 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2957 2958 if (spapr) { 2959 /* 2960 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2961 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 2962 * 0x8000 | (target << 8) | (bus << 5) | lun 2963 * (see the "Logical unit addressing format" table in SAM5) 2964 */ 2965 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 2966 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2967 (uint64_t)id << 48); 2968 } else if (virtio) { 2969 /* 2970 * We use SRP luns of the form 01000000 | (target << 8) | lun 2971 * in the top 32 bits of the 64-bit LUN 2972 * Note: the quote above is from SLOF and it is wrong, 2973 * the actual binding is: 2974 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2975 */ 2976 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2977 if (d->lun >= 256) { 2978 /* Use the LUN "flat space addressing method" */ 2979 id |= 0x4000; 2980 } 2981 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2982 (uint64_t)id << 32); 2983 } else if (usb) { 2984 /* 2985 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2986 * in the top 32 bits of the 64-bit LUN 2987 */ 2988 unsigned usb_port = atoi(usb->port->path); 2989 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2990 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2991 (uint64_t)id << 32); 2992 } 2993 } 2994 2995 /* 2996 * SLOF probes the USB devices, and if it recognizes that the device is a 2997 * storage device, it changes its name to "storage" instead of "usb-host", 2998 * and additionally adds a child node for the SCSI LUN, so the correct 2999 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3000 */ 3001 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3002 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3003 if (usb_host_dev_is_scsi_storage(usbdev)) { 3004 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3005 } 3006 } 3007 3008 if (phb) { 3009 /* Replace "pci" with "pci@800000020000000" */ 3010 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3011 } 3012 3013 if (vsc) { 3014 /* Same logic as virtio above */ 3015 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3016 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3017 } 3018 3019 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3020 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3021 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3022 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3023 } 3024 3025 return NULL; 3026 } 3027 3028 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3029 { 3030 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3031 3032 return g_strdup(spapr->kvm_type); 3033 } 3034 3035 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3036 { 3037 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3038 3039 g_free(spapr->kvm_type); 3040 spapr->kvm_type = g_strdup(value); 3041 } 3042 3043 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3044 { 3045 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3046 3047 return spapr->use_hotplug_event_source; 3048 } 3049 3050 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3051 Error **errp) 3052 { 3053 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3054 3055 spapr->use_hotplug_event_source = value; 3056 } 3057 3058 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3059 { 3060 return true; 3061 } 3062 3063 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3064 { 3065 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3066 3067 switch (spapr->resize_hpt) { 3068 case SPAPR_RESIZE_HPT_DEFAULT: 3069 return g_strdup("default"); 3070 case SPAPR_RESIZE_HPT_DISABLED: 3071 return g_strdup("disabled"); 3072 case SPAPR_RESIZE_HPT_ENABLED: 3073 return g_strdup("enabled"); 3074 case SPAPR_RESIZE_HPT_REQUIRED: 3075 return g_strdup("required"); 3076 } 3077 g_assert_not_reached(); 3078 } 3079 3080 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3081 { 3082 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3083 3084 if (strcmp(value, "default") == 0) { 3085 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3086 } else if (strcmp(value, "disabled") == 0) { 3087 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3088 } else if (strcmp(value, "enabled") == 0) { 3089 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3090 } else if (strcmp(value, "required") == 0) { 3091 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3092 } else { 3093 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3094 } 3095 } 3096 3097 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3098 void *opaque, Error **errp) 3099 { 3100 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3101 } 3102 3103 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3104 void *opaque, Error **errp) 3105 { 3106 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3107 } 3108 3109 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3110 { 3111 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3112 3113 if (spapr->irq == &spapr_irq_xics_legacy) { 3114 return g_strdup("legacy"); 3115 } else if (spapr->irq == &spapr_irq_xics) { 3116 return g_strdup("xics"); 3117 } else if (spapr->irq == &spapr_irq_xive) { 3118 return g_strdup("xive"); 3119 } else if (spapr->irq == &spapr_irq_dual) { 3120 return g_strdup("dual"); 3121 } 3122 g_assert_not_reached(); 3123 } 3124 3125 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3126 { 3127 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3128 3129 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3130 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3131 return; 3132 } 3133 3134 /* The legacy IRQ backend can not be set */ 3135 if (strcmp(value, "xics") == 0) { 3136 spapr->irq = &spapr_irq_xics; 3137 } else if (strcmp(value, "xive") == 0) { 3138 spapr->irq = &spapr_irq_xive; 3139 } else if (strcmp(value, "dual") == 0) { 3140 spapr->irq = &spapr_irq_dual; 3141 } else { 3142 error_setg(errp, "Bad value for \"ic-mode\" property"); 3143 } 3144 } 3145 3146 static void spapr_instance_init(Object *obj) 3147 { 3148 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3149 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3150 3151 spapr->htab_fd = -1; 3152 spapr->use_hotplug_event_source = true; 3153 object_property_add_str(obj, "kvm-type", 3154 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3155 object_property_set_description(obj, "kvm-type", 3156 "Specifies the KVM virtualization mode (HV, PR)", 3157 NULL); 3158 object_property_add_bool(obj, "modern-hotplug-events", 3159 spapr_get_modern_hotplug_events, 3160 spapr_set_modern_hotplug_events, 3161 NULL); 3162 object_property_set_description(obj, "modern-hotplug-events", 3163 "Use dedicated hotplug event mechanism in" 3164 " place of standard EPOW events when possible" 3165 " (required for memory hot-unplug support)", 3166 NULL); 3167 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3168 "Maximum permitted CPU compatibility mode", 3169 &error_fatal); 3170 3171 object_property_add_str(obj, "resize-hpt", 3172 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3173 object_property_set_description(obj, "resize-hpt", 3174 "Resizing of the Hash Page Table (enabled, disabled, required)", 3175 NULL); 3176 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3177 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3178 object_property_set_description(obj, "vsmt", 3179 "Virtual SMT: KVM behaves as if this were" 3180 " the host's SMT mode", &error_abort); 3181 object_property_add_bool(obj, "vfio-no-msix-emulation", 3182 spapr_get_msix_emulation, NULL, NULL); 3183 3184 /* The machine class defines the default interrupt controller mode */ 3185 spapr->irq = smc->irq; 3186 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3187 spapr_set_ic_mode, NULL); 3188 object_property_set_description(obj, "ic-mode", 3189 "Specifies the interrupt controller mode (xics, xive, dual)", 3190 NULL); 3191 } 3192 3193 static void spapr_machine_finalizefn(Object *obj) 3194 { 3195 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3196 3197 g_free(spapr->kvm_type); 3198 } 3199 3200 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3201 { 3202 cpu_synchronize_state(cs); 3203 ppc_cpu_do_system_reset(cs); 3204 } 3205 3206 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3207 { 3208 CPUState *cs; 3209 3210 CPU_FOREACH(cs) { 3211 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3212 } 3213 } 3214 3215 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3216 uint32_t node, bool dedicated_hp_event_source, 3217 Error **errp) 3218 { 3219 sPAPRDRConnector *drc; 3220 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3221 int i, fdt_offset, fdt_size; 3222 void *fdt; 3223 uint64_t addr = addr_start; 3224 bool hotplugged = spapr_drc_hotplugged(dev); 3225 Error *local_err = NULL; 3226 3227 for (i = 0; i < nr_lmbs; i++) { 3228 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3229 addr / SPAPR_MEMORY_BLOCK_SIZE); 3230 g_assert(drc); 3231 3232 fdt = create_device_tree(&fdt_size); 3233 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3234 SPAPR_MEMORY_BLOCK_SIZE); 3235 3236 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3237 if (local_err) { 3238 while (addr > addr_start) { 3239 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3240 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3241 addr / SPAPR_MEMORY_BLOCK_SIZE); 3242 spapr_drc_detach(drc); 3243 } 3244 g_free(fdt); 3245 error_propagate(errp, local_err); 3246 return; 3247 } 3248 if (!hotplugged) { 3249 spapr_drc_reset(drc); 3250 } 3251 addr += SPAPR_MEMORY_BLOCK_SIZE; 3252 } 3253 /* send hotplug notification to the 3254 * guest only in case of hotplugged memory 3255 */ 3256 if (hotplugged) { 3257 if (dedicated_hp_event_source) { 3258 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3259 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3260 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3261 nr_lmbs, 3262 spapr_drc_index(drc)); 3263 } else { 3264 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3265 nr_lmbs); 3266 } 3267 } 3268 } 3269 3270 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3271 Error **errp) 3272 { 3273 Error *local_err = NULL; 3274 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3275 PCDIMMDevice *dimm = PC_DIMM(dev); 3276 uint64_t size, addr; 3277 uint32_t node; 3278 3279 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3280 3281 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3282 if (local_err) { 3283 goto out; 3284 } 3285 3286 addr = object_property_get_uint(OBJECT(dimm), 3287 PC_DIMM_ADDR_PROP, &local_err); 3288 if (local_err) { 3289 goto out_unplug; 3290 } 3291 3292 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3293 &error_abort); 3294 spapr_add_lmbs(dev, addr, size, node, 3295 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3296 &local_err); 3297 if (local_err) { 3298 goto out_unplug; 3299 } 3300 3301 return; 3302 3303 out_unplug: 3304 pc_dimm_unplug(dimm, MACHINE(ms)); 3305 out: 3306 error_propagate(errp, local_err); 3307 } 3308 3309 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3310 Error **errp) 3311 { 3312 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3313 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3314 PCDIMMDevice *dimm = PC_DIMM(dev); 3315 Error *local_err = NULL; 3316 uint64_t size; 3317 Object *memdev; 3318 hwaddr pagesize; 3319 3320 if (!smc->dr_lmb_enabled) { 3321 error_setg(errp, "Memory hotplug not supported for this machine"); 3322 return; 3323 } 3324 3325 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3326 if (local_err) { 3327 error_propagate(errp, local_err); 3328 return; 3329 } 3330 3331 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3332 error_setg(errp, "Hotplugged memory size must be a multiple of " 3333 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3334 return; 3335 } 3336 3337 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3338 &error_abort); 3339 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3340 spapr_check_pagesize(spapr, pagesize, &local_err); 3341 if (local_err) { 3342 error_propagate(errp, local_err); 3343 return; 3344 } 3345 3346 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3347 } 3348 3349 struct sPAPRDIMMState { 3350 PCDIMMDevice *dimm; 3351 uint32_t nr_lmbs; 3352 QTAILQ_ENTRY(sPAPRDIMMState) next; 3353 }; 3354 3355 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3356 PCDIMMDevice *dimm) 3357 { 3358 sPAPRDIMMState *dimm_state = NULL; 3359 3360 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3361 if (dimm_state->dimm == dimm) { 3362 break; 3363 } 3364 } 3365 return dimm_state; 3366 } 3367 3368 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3369 uint32_t nr_lmbs, 3370 PCDIMMDevice *dimm) 3371 { 3372 sPAPRDIMMState *ds = NULL; 3373 3374 /* 3375 * If this request is for a DIMM whose removal had failed earlier 3376 * (due to guest's refusal to remove the LMBs), we would have this 3377 * dimm already in the pending_dimm_unplugs list. In that 3378 * case don't add again. 3379 */ 3380 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3381 if (!ds) { 3382 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3383 ds->nr_lmbs = nr_lmbs; 3384 ds->dimm = dimm; 3385 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3386 } 3387 return ds; 3388 } 3389 3390 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3391 sPAPRDIMMState *dimm_state) 3392 { 3393 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3394 g_free(dimm_state); 3395 } 3396 3397 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3398 PCDIMMDevice *dimm) 3399 { 3400 sPAPRDRConnector *drc; 3401 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3402 &error_abort); 3403 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3404 uint32_t avail_lmbs = 0; 3405 uint64_t addr_start, addr; 3406 int i; 3407 3408 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3409 &error_abort); 3410 3411 addr = addr_start; 3412 for (i = 0; i < nr_lmbs; i++) { 3413 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3414 addr / SPAPR_MEMORY_BLOCK_SIZE); 3415 g_assert(drc); 3416 if (drc->dev) { 3417 avail_lmbs++; 3418 } 3419 addr += SPAPR_MEMORY_BLOCK_SIZE; 3420 } 3421 3422 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3423 } 3424 3425 /* Callback to be called during DRC release. */ 3426 void spapr_lmb_release(DeviceState *dev) 3427 { 3428 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3429 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3430 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3431 3432 /* This information will get lost if a migration occurs 3433 * during the unplug process. In this case recover it. */ 3434 if (ds == NULL) { 3435 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3436 g_assert(ds); 3437 /* The DRC being examined by the caller at least must be counted */ 3438 g_assert(ds->nr_lmbs); 3439 } 3440 3441 if (--ds->nr_lmbs) { 3442 return; 3443 } 3444 3445 /* 3446 * Now that all the LMBs have been removed by the guest, call the 3447 * unplug handler chain. This can never fail. 3448 */ 3449 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3450 } 3451 3452 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3453 { 3454 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3455 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3456 3457 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3458 object_unparent(OBJECT(dev)); 3459 spapr_pending_dimm_unplugs_remove(spapr, ds); 3460 } 3461 3462 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3463 DeviceState *dev, Error **errp) 3464 { 3465 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3466 Error *local_err = NULL; 3467 PCDIMMDevice *dimm = PC_DIMM(dev); 3468 uint32_t nr_lmbs; 3469 uint64_t size, addr_start, addr; 3470 int i; 3471 sPAPRDRConnector *drc; 3472 3473 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3474 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3475 3476 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3477 &local_err); 3478 if (local_err) { 3479 goto out; 3480 } 3481 3482 /* 3483 * An existing pending dimm state for this DIMM means that there is an 3484 * unplug operation in progress, waiting for the spapr_lmb_release 3485 * callback to complete the job (BQL can't cover that far). In this case, 3486 * bail out to avoid detaching DRCs that were already released. 3487 */ 3488 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3489 error_setg(&local_err, 3490 "Memory unplug already in progress for device %s", 3491 dev->id); 3492 goto out; 3493 } 3494 3495 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3496 3497 addr = addr_start; 3498 for (i = 0; i < nr_lmbs; i++) { 3499 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3500 addr / SPAPR_MEMORY_BLOCK_SIZE); 3501 g_assert(drc); 3502 3503 spapr_drc_detach(drc); 3504 addr += SPAPR_MEMORY_BLOCK_SIZE; 3505 } 3506 3507 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3508 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3509 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3510 nr_lmbs, spapr_drc_index(drc)); 3511 out: 3512 error_propagate(errp, local_err); 3513 } 3514 3515 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3516 sPAPRMachineState *spapr) 3517 { 3518 PowerPCCPU *cpu = POWERPC_CPU(cs); 3519 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3520 int id = spapr_get_vcpu_id(cpu); 3521 void *fdt; 3522 int offset, fdt_size; 3523 char *nodename; 3524 3525 fdt = create_device_tree(&fdt_size); 3526 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3527 offset = fdt_add_subnode(fdt, 0, nodename); 3528 3529 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3530 g_free(nodename); 3531 3532 *fdt_offset = offset; 3533 return fdt; 3534 } 3535 3536 /* Callback to be called during DRC release. */ 3537 void spapr_core_release(DeviceState *dev) 3538 { 3539 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3540 3541 /* Call the unplug handler chain. This can never fail. */ 3542 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3543 } 3544 3545 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3546 { 3547 MachineState *ms = MACHINE(hotplug_dev); 3548 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3549 CPUCore *cc = CPU_CORE(dev); 3550 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3551 3552 if (smc->pre_2_10_has_unused_icps) { 3553 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3554 int i; 3555 3556 for (i = 0; i < cc->nr_threads; i++) { 3557 CPUState *cs = CPU(sc->threads[i]); 3558 3559 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3560 } 3561 } 3562 3563 assert(core_slot); 3564 core_slot->cpu = NULL; 3565 object_unparent(OBJECT(dev)); 3566 } 3567 3568 static 3569 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3570 Error **errp) 3571 { 3572 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3573 int index; 3574 sPAPRDRConnector *drc; 3575 CPUCore *cc = CPU_CORE(dev); 3576 3577 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3578 error_setg(errp, "Unable to find CPU core with core-id: %d", 3579 cc->core_id); 3580 return; 3581 } 3582 if (index == 0) { 3583 error_setg(errp, "Boot CPU core may not be unplugged"); 3584 return; 3585 } 3586 3587 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3588 spapr_vcpu_id(spapr, cc->core_id)); 3589 g_assert(drc); 3590 3591 spapr_drc_detach(drc); 3592 3593 spapr_hotplug_req_remove_by_index(drc); 3594 } 3595 3596 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3597 Error **errp) 3598 { 3599 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3600 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3601 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3602 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3603 CPUCore *cc = CPU_CORE(dev); 3604 CPUState *cs = CPU(core->threads[0]); 3605 sPAPRDRConnector *drc; 3606 Error *local_err = NULL; 3607 CPUArchId *core_slot; 3608 int index; 3609 bool hotplugged = spapr_drc_hotplugged(dev); 3610 3611 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3612 if (!core_slot) { 3613 error_setg(errp, "Unable to find CPU core with core-id: %d", 3614 cc->core_id); 3615 return; 3616 } 3617 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3618 spapr_vcpu_id(spapr, cc->core_id)); 3619 3620 g_assert(drc || !mc->has_hotpluggable_cpus); 3621 3622 if (drc) { 3623 void *fdt; 3624 int fdt_offset; 3625 3626 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3627 3628 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3629 if (local_err) { 3630 g_free(fdt); 3631 error_propagate(errp, local_err); 3632 return; 3633 } 3634 3635 if (hotplugged) { 3636 /* 3637 * Send hotplug notification interrupt to the guest only 3638 * in case of hotplugged CPUs. 3639 */ 3640 spapr_hotplug_req_add_by_index(drc); 3641 } else { 3642 spapr_drc_reset(drc); 3643 } 3644 } 3645 3646 core_slot->cpu = OBJECT(dev); 3647 3648 if (smc->pre_2_10_has_unused_icps) { 3649 int i; 3650 3651 for (i = 0; i < cc->nr_threads; i++) { 3652 cs = CPU(core->threads[i]); 3653 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3654 } 3655 } 3656 } 3657 3658 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3659 Error **errp) 3660 { 3661 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3662 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3663 Error *local_err = NULL; 3664 CPUCore *cc = CPU_CORE(dev); 3665 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3666 const char *type = object_get_typename(OBJECT(dev)); 3667 CPUArchId *core_slot; 3668 int index; 3669 3670 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3671 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3672 goto out; 3673 } 3674 3675 if (strcmp(base_core_type, type)) { 3676 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3677 goto out; 3678 } 3679 3680 if (cc->core_id % smp_threads) { 3681 error_setg(&local_err, "invalid core id %d", cc->core_id); 3682 goto out; 3683 } 3684 3685 /* 3686 * In general we should have homogeneous threads-per-core, but old 3687 * (pre hotplug support) machine types allow the last core to have 3688 * reduced threads as a compatibility hack for when we allowed 3689 * total vcpus not a multiple of threads-per-core. 3690 */ 3691 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3692 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3693 cc->nr_threads, smp_threads); 3694 goto out; 3695 } 3696 3697 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3698 if (!core_slot) { 3699 error_setg(&local_err, "core id %d out of range", cc->core_id); 3700 goto out; 3701 } 3702 3703 if (core_slot->cpu) { 3704 error_setg(&local_err, "core %d already populated", cc->core_id); 3705 goto out; 3706 } 3707 3708 numa_cpu_pre_plug(core_slot, dev, &local_err); 3709 3710 out: 3711 error_propagate(errp, local_err); 3712 } 3713 3714 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3715 DeviceState *dev, Error **errp) 3716 { 3717 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3718 spapr_memory_plug(hotplug_dev, dev, errp); 3719 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3720 spapr_core_plug(hotplug_dev, dev, errp); 3721 } 3722 } 3723 3724 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3725 DeviceState *dev, Error **errp) 3726 { 3727 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3728 spapr_memory_unplug(hotplug_dev, dev); 3729 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3730 spapr_core_unplug(hotplug_dev, dev); 3731 } 3732 } 3733 3734 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3735 DeviceState *dev, Error **errp) 3736 { 3737 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3738 MachineClass *mc = MACHINE_GET_CLASS(sms); 3739 3740 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3741 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3742 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3743 } else { 3744 /* NOTE: this means there is a window after guest reset, prior to 3745 * CAS negotiation, where unplug requests will fail due to the 3746 * capability not being detected yet. This is a bit different than 3747 * the case with PCI unplug, where the events will be queued and 3748 * eventually handled by the guest after boot 3749 */ 3750 error_setg(errp, "Memory hot unplug not supported for this guest"); 3751 } 3752 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3753 if (!mc->has_hotpluggable_cpus) { 3754 error_setg(errp, "CPU hot unplug not supported on this machine"); 3755 return; 3756 } 3757 spapr_core_unplug_request(hotplug_dev, dev, errp); 3758 } 3759 } 3760 3761 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3762 DeviceState *dev, Error **errp) 3763 { 3764 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3765 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3766 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3767 spapr_core_pre_plug(hotplug_dev, dev, errp); 3768 } 3769 } 3770 3771 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3772 DeviceState *dev) 3773 { 3774 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3775 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3776 return HOTPLUG_HANDLER(machine); 3777 } 3778 return NULL; 3779 } 3780 3781 static CpuInstanceProperties 3782 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3783 { 3784 CPUArchId *core_slot; 3785 MachineClass *mc = MACHINE_GET_CLASS(machine); 3786 3787 /* make sure possible_cpu are intialized */ 3788 mc->possible_cpu_arch_ids(machine); 3789 /* get CPU core slot containing thread that matches cpu_index */ 3790 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3791 assert(core_slot); 3792 return core_slot->props; 3793 } 3794 3795 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3796 { 3797 return idx / smp_cores % nb_numa_nodes; 3798 } 3799 3800 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3801 { 3802 int i; 3803 const char *core_type; 3804 int spapr_max_cores = max_cpus / smp_threads; 3805 MachineClass *mc = MACHINE_GET_CLASS(machine); 3806 3807 if (!mc->has_hotpluggable_cpus) { 3808 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3809 } 3810 if (machine->possible_cpus) { 3811 assert(machine->possible_cpus->len == spapr_max_cores); 3812 return machine->possible_cpus; 3813 } 3814 3815 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3816 if (!core_type) { 3817 error_report("Unable to find sPAPR CPU Core definition"); 3818 exit(1); 3819 } 3820 3821 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3822 sizeof(CPUArchId) * spapr_max_cores); 3823 machine->possible_cpus->len = spapr_max_cores; 3824 for (i = 0; i < machine->possible_cpus->len; i++) { 3825 int core_id = i * smp_threads; 3826 3827 machine->possible_cpus->cpus[i].type = core_type; 3828 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3829 machine->possible_cpus->cpus[i].arch_id = core_id; 3830 machine->possible_cpus->cpus[i].props.has_core_id = true; 3831 machine->possible_cpus->cpus[i].props.core_id = core_id; 3832 } 3833 return machine->possible_cpus; 3834 } 3835 3836 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3837 uint64_t *buid, hwaddr *pio, 3838 hwaddr *mmio32, hwaddr *mmio64, 3839 unsigned n_dma, uint32_t *liobns, Error **errp) 3840 { 3841 /* 3842 * New-style PHB window placement. 3843 * 3844 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3845 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3846 * windows. 3847 * 3848 * Some guest kernels can't work with MMIO windows above 1<<46 3849 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3850 * 3851 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3852 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3853 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3854 * 1TiB 64-bit MMIO windows for each PHB. 3855 */ 3856 const uint64_t base_buid = 0x800000020000000ULL; 3857 int i; 3858 3859 /* Sanity check natural alignments */ 3860 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3861 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3862 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3863 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3864 /* Sanity check bounds */ 3865 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3866 SPAPR_PCI_MEM32_WIN_SIZE); 3867 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3868 SPAPR_PCI_MEM64_WIN_SIZE); 3869 3870 if (index >= SPAPR_MAX_PHBS) { 3871 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3872 SPAPR_MAX_PHBS - 1); 3873 return; 3874 } 3875 3876 *buid = base_buid + index; 3877 for (i = 0; i < n_dma; ++i) { 3878 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3879 } 3880 3881 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3882 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3883 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3884 } 3885 3886 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3887 { 3888 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3889 3890 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3891 } 3892 3893 static void spapr_ics_resend(XICSFabric *dev) 3894 { 3895 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3896 3897 ics_resend(spapr->ics); 3898 } 3899 3900 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3901 { 3902 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3903 3904 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 3905 } 3906 3907 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3908 Monitor *mon) 3909 { 3910 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3911 3912 spapr->irq->print_info(spapr, mon); 3913 } 3914 3915 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3916 { 3917 return cpu->vcpu_id; 3918 } 3919 3920 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3921 { 3922 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3923 int vcpu_id; 3924 3925 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3926 3927 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3928 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3929 error_append_hint(errp, "Adjust the number of cpus to %d " 3930 "or try to raise the number of threads per core\n", 3931 vcpu_id * smp_threads / spapr->vsmt); 3932 return; 3933 } 3934 3935 cpu->vcpu_id = vcpu_id; 3936 } 3937 3938 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3939 { 3940 CPUState *cs; 3941 3942 CPU_FOREACH(cs) { 3943 PowerPCCPU *cpu = POWERPC_CPU(cs); 3944 3945 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3946 return cpu; 3947 } 3948 } 3949 3950 return NULL; 3951 } 3952 3953 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3954 { 3955 MachineClass *mc = MACHINE_CLASS(oc); 3956 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3957 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3958 NMIClass *nc = NMI_CLASS(oc); 3959 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3960 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3961 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3962 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3963 3964 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3965 mc->ignore_boot_device_suffixes = true; 3966 3967 /* 3968 * We set up the default / latest behaviour here. The class_init 3969 * functions for the specific versioned machine types can override 3970 * these details for backwards compatibility 3971 */ 3972 mc->init = spapr_machine_init; 3973 mc->reset = spapr_machine_reset; 3974 mc->block_default_type = IF_SCSI; 3975 mc->max_cpus = 1024; 3976 mc->no_parallel = 1; 3977 mc->default_boot_order = ""; 3978 mc->default_ram_size = 512 * MiB; 3979 mc->default_display = "std"; 3980 mc->kvm_type = spapr_kvm_type; 3981 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3982 mc->pci_allow_0_address = true; 3983 assert(!mc->get_hotplug_handler); 3984 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3985 hc->pre_plug = spapr_machine_device_pre_plug; 3986 hc->plug = spapr_machine_device_plug; 3987 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3988 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3989 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3990 hc->unplug_request = spapr_machine_device_unplug_request; 3991 hc->unplug = spapr_machine_device_unplug; 3992 3993 smc->dr_lmb_enabled = true; 3994 smc->update_dt_enabled = true; 3995 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 3996 mc->has_hotpluggable_cpus = true; 3997 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3998 fwc->get_dev_path = spapr_get_fw_dev_path; 3999 nc->nmi_monitor_handler = spapr_nmi; 4000 smc->phb_placement = spapr_phb_placement; 4001 vhc->hypercall = emulate_spapr_hypercall; 4002 vhc->hpt_mask = spapr_hpt_mask; 4003 vhc->map_hptes = spapr_map_hptes; 4004 vhc->unmap_hptes = spapr_unmap_hptes; 4005 vhc->store_hpte = spapr_store_hpte; 4006 vhc->get_patbe = spapr_get_patbe; 4007 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4008 xic->ics_get = spapr_ics_get; 4009 xic->ics_resend = spapr_ics_resend; 4010 xic->icp_get = spapr_icp_get; 4011 ispc->print_info = spapr_pic_print_info; 4012 /* Force NUMA node memory size to be a multiple of 4013 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4014 * in which LMBs are represented and hot-added 4015 */ 4016 mc->numa_mem_align_shift = 28; 4017 4018 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4019 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4020 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4021 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4022 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4023 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4024 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4025 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4026 spapr_caps_add_properties(smc, &error_abort); 4027 smc->irq = &spapr_irq_xics; 4028 } 4029 4030 static const TypeInfo spapr_machine_info = { 4031 .name = TYPE_SPAPR_MACHINE, 4032 .parent = TYPE_MACHINE, 4033 .abstract = true, 4034 .instance_size = sizeof(sPAPRMachineState), 4035 .instance_init = spapr_instance_init, 4036 .instance_finalize = spapr_machine_finalizefn, 4037 .class_size = sizeof(sPAPRMachineClass), 4038 .class_init = spapr_machine_class_init, 4039 .interfaces = (InterfaceInfo[]) { 4040 { TYPE_FW_PATH_PROVIDER }, 4041 { TYPE_NMI }, 4042 { TYPE_HOTPLUG_HANDLER }, 4043 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4044 { TYPE_XICS_FABRIC }, 4045 { TYPE_INTERRUPT_STATS_PROVIDER }, 4046 { } 4047 }, 4048 }; 4049 4050 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4051 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4052 void *data) \ 4053 { \ 4054 MachineClass *mc = MACHINE_CLASS(oc); \ 4055 spapr_machine_##suffix##_class_options(mc); \ 4056 if (latest) { \ 4057 mc->alias = "pseries"; \ 4058 mc->is_default = 1; \ 4059 } \ 4060 } \ 4061 static const TypeInfo spapr_machine_##suffix##_info = { \ 4062 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4063 .parent = TYPE_SPAPR_MACHINE, \ 4064 .class_init = spapr_machine_##suffix##_class_init, \ 4065 }; \ 4066 static void spapr_machine_register_##suffix(void) \ 4067 { \ 4068 type_register(&spapr_machine_##suffix##_info); \ 4069 } \ 4070 type_init(spapr_machine_register_##suffix) 4071 4072 /* 4073 * pseries-4.0 4074 */ 4075 static void spapr_machine_4_0_class_options(MachineClass *mc) 4076 { 4077 /* Defaults for the latest behaviour inherited from the base class */ 4078 } 4079 4080 DEFINE_SPAPR_MACHINE(4_0, "4.0", true); 4081 4082 /* 4083 * pseries-3.1 4084 */ 4085 static void spapr_machine_3_1_class_options(MachineClass *mc) 4086 { 4087 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4088 4089 spapr_machine_4_0_class_options(mc); 4090 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4091 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4092 smc->update_dt_enabled = false; 4093 } 4094 4095 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4096 4097 /* 4098 * pseries-3.0 4099 */ 4100 4101 static void spapr_machine_3_0_class_options(MachineClass *mc) 4102 { 4103 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4104 4105 spapr_machine_3_1_class_options(mc); 4106 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4107 4108 smc->legacy_irq_allocation = true; 4109 smc->irq = &spapr_irq_xics_legacy; 4110 } 4111 4112 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4113 4114 /* 4115 * pseries-2.12 4116 */ 4117 static void spapr_machine_2_12_class_options(MachineClass *mc) 4118 { 4119 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4120 static GlobalProperty compat[] = { 4121 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4122 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4123 }; 4124 4125 spapr_machine_3_0_class_options(mc); 4126 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4127 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4128 4129 /* We depend on kvm_enabled() to choose a default value for the 4130 * hpt-max-page-size capability. Of course we can't do it here 4131 * because this is too early and the HW accelerator isn't initialzed 4132 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4133 */ 4134 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4135 } 4136 4137 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4138 4139 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4140 { 4141 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4142 4143 spapr_machine_2_12_class_options(mc); 4144 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4145 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4146 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4147 } 4148 4149 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4150 4151 /* 4152 * pseries-2.11 4153 */ 4154 4155 static void spapr_machine_2_11_class_options(MachineClass *mc) 4156 { 4157 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4158 4159 spapr_machine_2_12_class_options(mc); 4160 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4161 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4162 } 4163 4164 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4165 4166 /* 4167 * pseries-2.10 4168 */ 4169 4170 static void spapr_machine_2_10_class_options(MachineClass *mc) 4171 { 4172 spapr_machine_2_11_class_options(mc); 4173 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4174 } 4175 4176 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4177 4178 /* 4179 * pseries-2.9 4180 */ 4181 4182 static void spapr_machine_2_9_class_options(MachineClass *mc) 4183 { 4184 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4185 static GlobalProperty compat[] = { 4186 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4187 }; 4188 4189 spapr_machine_2_10_class_options(mc); 4190 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4191 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4192 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4193 smc->pre_2_10_has_unused_icps = true; 4194 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4195 } 4196 4197 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4198 4199 /* 4200 * pseries-2.8 4201 */ 4202 4203 static void spapr_machine_2_8_class_options(MachineClass *mc) 4204 { 4205 static GlobalProperty compat[] = { 4206 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4207 }; 4208 4209 spapr_machine_2_9_class_options(mc); 4210 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4211 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4212 mc->numa_mem_align_shift = 23; 4213 } 4214 4215 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4216 4217 /* 4218 * pseries-2.7 4219 */ 4220 4221 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4222 uint64_t *buid, hwaddr *pio, 4223 hwaddr *mmio32, hwaddr *mmio64, 4224 unsigned n_dma, uint32_t *liobns, Error **errp) 4225 { 4226 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4227 const uint64_t base_buid = 0x800000020000000ULL; 4228 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4229 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4230 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4231 const uint32_t max_index = 255; 4232 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4233 4234 uint64_t ram_top = MACHINE(spapr)->ram_size; 4235 hwaddr phb0_base, phb_base; 4236 int i; 4237 4238 /* Do we have device memory? */ 4239 if (MACHINE(spapr)->maxram_size > ram_top) { 4240 /* Can't just use maxram_size, because there may be an 4241 * alignment gap between normal and device memory regions 4242 */ 4243 ram_top = MACHINE(spapr)->device_memory->base + 4244 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4245 } 4246 4247 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4248 4249 if (index > max_index) { 4250 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4251 max_index); 4252 return; 4253 } 4254 4255 *buid = base_buid + index; 4256 for (i = 0; i < n_dma; ++i) { 4257 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4258 } 4259 4260 phb_base = phb0_base + index * phb_spacing; 4261 *pio = phb_base + pio_offset; 4262 *mmio32 = phb_base + mmio_offset; 4263 /* 4264 * We don't set the 64-bit MMIO window, relying on the PHB's 4265 * fallback behaviour of automatically splitting a large "32-bit" 4266 * window into contiguous 32-bit and 64-bit windows 4267 */ 4268 } 4269 4270 static void spapr_machine_2_7_class_options(MachineClass *mc) 4271 { 4272 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4273 static GlobalProperty compat[] = { 4274 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4275 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4276 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4277 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4278 }; 4279 4280 spapr_machine_2_8_class_options(mc); 4281 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4282 mc->default_machine_opts = "modern-hotplug-events=off"; 4283 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4284 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4285 smc->phb_placement = phb_placement_2_7; 4286 } 4287 4288 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4289 4290 /* 4291 * pseries-2.6 4292 */ 4293 4294 static void spapr_machine_2_6_class_options(MachineClass *mc) 4295 { 4296 static GlobalProperty compat[] = { 4297 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4298 }; 4299 4300 spapr_machine_2_7_class_options(mc); 4301 mc->has_hotpluggable_cpus = false; 4302 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4303 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4304 } 4305 4306 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4307 4308 /* 4309 * pseries-2.5 4310 */ 4311 4312 static void spapr_machine_2_5_class_options(MachineClass *mc) 4313 { 4314 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4315 static GlobalProperty compat[] = { 4316 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4317 }; 4318 4319 spapr_machine_2_6_class_options(mc); 4320 smc->use_ohci_by_default = true; 4321 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4322 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4323 } 4324 4325 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4326 4327 /* 4328 * pseries-2.4 4329 */ 4330 4331 static void spapr_machine_2_4_class_options(MachineClass *mc) 4332 { 4333 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4334 4335 spapr_machine_2_5_class_options(mc); 4336 smc->dr_lmb_enabled = false; 4337 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4338 } 4339 4340 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4341 4342 /* 4343 * pseries-2.3 4344 */ 4345 4346 static void spapr_machine_2_3_class_options(MachineClass *mc) 4347 { 4348 static GlobalProperty compat[] = { 4349 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4350 }; 4351 spapr_machine_2_4_class_options(mc); 4352 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4353 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4354 } 4355 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4356 4357 /* 4358 * pseries-2.2 4359 */ 4360 4361 static void spapr_machine_2_2_class_options(MachineClass *mc) 4362 { 4363 static GlobalProperty compat[] = { 4364 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4365 }; 4366 4367 spapr_machine_2_3_class_options(mc); 4368 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4369 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4370 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4371 } 4372 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4373 4374 /* 4375 * pseries-2.1 4376 */ 4377 4378 static void spapr_machine_2_1_class_options(MachineClass *mc) 4379 { 4380 spapr_machine_2_2_class_options(mc); 4381 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4382 } 4383 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4384 4385 static void spapr_machine_register_types(void) 4386 { 4387 type_register_static(&spapr_machine_info); 4388 } 4389 4390 type_init(spapr_machine_register_types) 4391