1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "mmu-hash64.h" 50 #include "mmu-book3s-v3.h" 51 #include "cpu-models.h" 52 #include "hw/core/cpu.h" 53 54 #include "hw/boards.h" 55 #include "hw/ppc/ppc.h" 56 #include "hw/loader.h" 57 58 #include "hw/ppc/fdt.h" 59 #include "hw/ppc/spapr.h" 60 #include "hw/ppc/spapr_vio.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/pci-host/spapr.h" 63 #include "hw/pci/msi.h" 64 65 #include "hw/pci/pci.h" 66 #include "hw/scsi/scsi.h" 67 #include "hw/virtio/virtio-scsi.h" 68 #include "hw/virtio/vhost-scsi-common.h" 69 70 #include "exec/address-spaces.h" 71 #include "exec/ram_addr.h" 72 #include "hw/usb.h" 73 #include "qemu/config-file.h" 74 #include "qemu/error-report.h" 75 #include "trace.h" 76 #include "hw/nmi.h" 77 #include "hw/intc/intc.h" 78 79 #include "qemu/cutils.h" 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 84 #include "monitor/monitor.h" 85 86 #include <libfdt.h> 87 88 /* SLOF memory layout: 89 * 90 * SLOF raw image loaded at 0, copies its romfs right below the flat 91 * device-tree, then position SLOF itself 31M below that 92 * 93 * So we set FW_OVERHEAD to 40MB which should account for all of that 94 * and more 95 * 96 * We load our kernel at 4M, leaving space for SLOF initial image 97 */ 98 #define FDT_MAX_SIZE 0x100000 99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 100 #define FW_MAX_SIZE 0x400000 101 #define FW_FILE_NAME "slof.bin" 102 #define FW_OVERHEAD 0x2800000 103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 104 105 #define MIN_RMA_SLOF 128UL 106 107 #define PHANDLE_INTC 0x00001111 108 109 /* These two functions implement the VCPU id numbering: one to compute them 110 * all and one to identify thread 0 of a VCORE. Any change to the first one 111 * is likely to have an impact on the second one, so let's keep them close. 112 */ 113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 114 { 115 MachineState *ms = MACHINE(spapr); 116 unsigned int smp_threads = ms->smp.threads; 117 118 assert(spapr->vsmt); 119 return 120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 121 } 122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 123 PowerPCCPU *cpu) 124 { 125 assert(spapr->vsmt); 126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 int spapr_max_server_number(SpaprMachineState *spapr) 164 { 165 MachineState *ms = MACHINE(spapr); 166 167 assert(spapr->vsmt); 168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 169 } 170 171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 172 int smt_threads) 173 { 174 int i, ret = 0; 175 uint32_t servers_prop[smt_threads]; 176 uint32_t gservers_prop[smt_threads * 2]; 177 int index = spapr_get_vcpu_id(cpu); 178 179 if (cpu->compat_pvr) { 180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 181 if (ret < 0) { 182 return ret; 183 } 184 } 185 186 /* Build interrupt servers and gservers properties */ 187 for (i = 0; i < smt_threads; i++) { 188 servers_prop[i] = cpu_to_be32(index + i); 189 /* Hack, direct the group queues back to cpu 0 */ 190 gservers_prop[i*2] = cpu_to_be32(index + i); 191 gservers_prop[i*2 + 1] = 0; 192 } 193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 194 servers_prop, sizeof(servers_prop)); 195 if (ret < 0) { 196 return ret; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 199 gservers_prop, sizeof(gservers_prop)); 200 201 return ret; 202 } 203 204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 205 { 206 int index = spapr_get_vcpu_id(cpu); 207 uint32_t associativity[] = {cpu_to_be32(0x5), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(cpu->node_id), 212 cpu_to_be32(index)}; 213 214 /* Advertise NUMA via ibm,associativity */ 215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 216 sizeof(associativity)); 217 } 218 219 /* Populate the "ibm,pa-features" property */ 220 static void spapr_populate_pa_features(SpaprMachineState *spapr, 221 PowerPCCPU *cpu, 222 void *fdt, int offset) 223 { 224 uint8_t pa_features_206[] = { 6, 0, 225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 226 uint8_t pa_features_207[] = { 24, 0, 227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 231 uint8_t pa_features_300[] = { 66, 0, 232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 235 /* 6: DS207 */ 236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 237 /* 16: Vector */ 238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 247 /* 42: PM, 44: PC RA, 46: SC vec'd */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 249 /* 48: SIMD, 50: QP BFP, 52: String */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 251 /* 54: DecFP, 56: DecI, 58: SHA */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 253 /* 60: NM atomic, 62: RNG */ 254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (!pa_features) { 272 return; 273 } 274 275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 276 /* 277 * Note: we keep CI large pages off by default because a 64K capable 278 * guest provisioned with large pages might otherwise try to map a qemu 279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 280 * even if that qemu runs on a 4k host. 281 * We dd this bit back here if we are confident this is not an issue 282 */ 283 pa_features[3] |= 0x20; 284 } 285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 286 pa_features[24] |= 0x80; /* Transactional memory support */ 287 } 288 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 289 /* Workaround for broken kernels that attempt (guest) radix 290 * mode when they can't handle it, if they see the radix bit set 291 * in pa-features. So hide it from them. */ 292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 293 } 294 295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 296 } 297 298 static hwaddr spapr_node0_size(MachineState *machine) 299 { 300 if (machine->numa_state->num_nodes) { 301 int i; 302 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 303 if (machine->numa_state->nodes[i].node_mem) { 304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 305 machine->ram_size); 306 } 307 } 308 } 309 return machine->ram_size; 310 } 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 318 hwaddr size) 319 { 320 uint32_t associativity[] = { 321 cpu_to_be32(0x4), /* length */ 322 cpu_to_be32(0x0), cpu_to_be32(0x0), 323 cpu_to_be32(0x0), cpu_to_be32(nodeid) 324 }; 325 char mem_name[32]; 326 uint64_t mem_reg_property[2]; 327 int off; 328 329 mem_reg_property[0] = cpu_to_be64(start); 330 mem_reg_property[1] = cpu_to_be64(size); 331 332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 333 off = fdt_add_subnode(fdt, 0, mem_name); 334 _FDT(off); 335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 337 sizeof(mem_reg_property)))); 338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 339 sizeof(associativity)))); 340 return off; 341 } 342 343 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 344 { 345 MachineState *machine = MACHINE(spapr); 346 hwaddr mem_start, node_size; 347 int i, nb_nodes = machine->numa_state->num_nodes; 348 NodeInfo *nodes = machine->numa_state->nodes; 349 350 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 351 if (!nodes[i].node_mem) { 352 continue; 353 } 354 if (mem_start >= machine->ram_size) { 355 node_size = 0; 356 } else { 357 node_size = nodes[i].node_mem; 358 if (node_size > machine->ram_size - mem_start) { 359 node_size = machine->ram_size - mem_start; 360 } 361 } 362 if (!mem_start) { 363 /* spapr_machine_init() checks for rma_size <= node0_size 364 * already */ 365 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 366 mem_start += spapr->rma_size; 367 node_size -= spapr->rma_size; 368 } 369 for ( ; node_size; ) { 370 hwaddr sizetmp = pow2floor(node_size); 371 372 /* mem_start != 0 here */ 373 if (ctzl(mem_start) < ctzl(sizetmp)) { 374 sizetmp = 1ULL << ctzl(mem_start); 375 } 376 377 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 378 node_size -= sizetmp; 379 mem_start += sizetmp; 380 } 381 } 382 383 return 0; 384 } 385 386 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 387 SpaprMachineState *spapr) 388 { 389 MachineState *ms = MACHINE(spapr); 390 PowerPCCPU *cpu = POWERPC_CPU(cs); 391 CPUPPCState *env = &cpu->env; 392 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 393 int index = spapr_get_vcpu_id(cpu); 394 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 395 0xffffffff, 0xffffffff}; 396 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 397 : SPAPR_TIMEBASE_FREQ; 398 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 399 uint32_t page_sizes_prop[64]; 400 size_t page_sizes_prop_size; 401 unsigned int smp_threads = ms->smp.threads; 402 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 403 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 404 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 405 SpaprDrc *drc; 406 int drc_index; 407 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 408 int i; 409 410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 411 if (drc) { 412 drc_index = spapr_drc_index(drc); 413 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 414 } 415 416 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 417 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 418 419 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 420 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 421 env->dcache_line_size))); 422 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 423 env->dcache_line_size))); 424 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 425 env->icache_line_size))); 426 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 427 env->icache_line_size))); 428 429 if (pcc->l1_dcache_size) { 430 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 431 pcc->l1_dcache_size))); 432 } else { 433 warn_report("Unknown L1 dcache size for cpu"); 434 } 435 if (pcc->l1_icache_size) { 436 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 437 pcc->l1_icache_size))); 438 } else { 439 warn_report("Unknown L1 icache size for cpu"); 440 } 441 442 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 443 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 445 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 447 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 448 449 if (env->spr_cb[SPR_PURR].oea_read) { 450 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 451 } 452 if (env->spr_cb[SPR_SPURR].oea_read) { 453 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 454 } 455 456 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 457 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 458 segs, sizeof(segs)))); 459 } 460 461 /* Advertise VSX (vector extensions) if available 462 * 1 == VMX / Altivec available 463 * 2 == VSX available 464 * 465 * Only CPUs for which we create core types in spapr_cpu_core.c 466 * are possible, and all of those have VMX */ 467 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 468 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 469 } else { 470 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 471 } 472 473 /* Advertise DFP (Decimal Floating Point) if available 474 * 0 / no property == no DFP 475 * 1 == DFP available */ 476 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 477 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 478 } 479 480 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 481 sizeof(page_sizes_prop)); 482 if (page_sizes_prop_size) { 483 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 484 page_sizes_prop, page_sizes_prop_size))); 485 } 486 487 spapr_populate_pa_features(spapr, cpu, fdt, offset); 488 489 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 490 cs->cpu_index / vcpus_per_socket))); 491 492 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 493 pft_size_prop, sizeof(pft_size_prop)))); 494 495 if (ms->numa_state->num_nodes > 1) { 496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 497 } 498 499 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 500 501 if (pcc->radix_page_info) { 502 for (i = 0; i < pcc->radix_page_info->count; i++) { 503 radix_AP_encodings[i] = 504 cpu_to_be32(pcc->radix_page_info->entries[i]); 505 } 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 507 radix_AP_encodings, 508 pcc->radix_page_info->count * 509 sizeof(radix_AP_encodings[0])))); 510 } 511 512 /* 513 * We set this property to let the guest know that it can use the large 514 * decrementer and its width in bits. 515 */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 517 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 518 pcc->lrg_decr_bits))); 519 } 520 521 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 522 { 523 CPUState **rev; 524 CPUState *cs; 525 int n_cpus; 526 int cpus_offset; 527 char *nodename; 528 int i; 529 530 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 531 _FDT(cpus_offset); 532 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 534 535 /* 536 * We walk the CPUs in reverse order to ensure that CPU DT nodes 537 * created by fdt_add_subnode() end up in the right order in FDT 538 * for the guest kernel the enumerate the CPUs correctly. 539 * 540 * The CPU list cannot be traversed in reverse order, so we need 541 * to do extra work. 542 */ 543 n_cpus = 0; 544 rev = NULL; 545 CPU_FOREACH(cs) { 546 rev = g_renew(CPUState *, rev, n_cpus + 1); 547 rev[n_cpus++] = cs; 548 } 549 550 for (i = n_cpus - 1; i >= 0; i--) { 551 CPUState *cs = rev[i]; 552 PowerPCCPU *cpu = POWERPC_CPU(cs); 553 int index = spapr_get_vcpu_id(cpu); 554 DeviceClass *dc = DEVICE_GET_CLASS(cs); 555 int offset; 556 557 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 558 continue; 559 } 560 561 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 562 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 563 g_free(nodename); 564 _FDT(offset); 565 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 566 } 567 568 g_free(rev); 569 } 570 571 static int spapr_rng_populate_dt(void *fdt) 572 { 573 int node; 574 int ret; 575 576 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 577 if (node <= 0) { 578 return -1; 579 } 580 ret = fdt_setprop_string(fdt, node, "device_type", 581 "ibm,platform-facilities"); 582 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 583 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 584 585 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 586 if (node <= 0) { 587 return -1; 588 } 589 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 590 591 return ret ? -1 : 0; 592 } 593 594 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 595 { 596 MemoryDeviceInfoList *info; 597 598 for (info = list; info; info = info->next) { 599 MemoryDeviceInfo *value = info->value; 600 601 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 602 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 603 604 if (addr >= pcdimm_info->addr && 605 addr < (pcdimm_info->addr + pcdimm_info->size)) { 606 return pcdimm_info->node; 607 } 608 } 609 } 610 611 return -1; 612 } 613 614 struct sPAPRDrconfCellV2 { 615 uint32_t seq_lmbs; 616 uint64_t base_addr; 617 uint32_t drc_index; 618 uint32_t aa_index; 619 uint32_t flags; 620 } QEMU_PACKED; 621 622 typedef struct DrconfCellQueue { 623 struct sPAPRDrconfCellV2 cell; 624 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 625 } DrconfCellQueue; 626 627 static DrconfCellQueue * 628 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 629 uint32_t drc_index, uint32_t aa_index, 630 uint32_t flags) 631 { 632 DrconfCellQueue *elem; 633 634 elem = g_malloc0(sizeof(*elem)); 635 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 636 elem->cell.base_addr = cpu_to_be64(base_addr); 637 elem->cell.drc_index = cpu_to_be32(drc_index); 638 elem->cell.aa_index = cpu_to_be32(aa_index); 639 elem->cell.flags = cpu_to_be32(flags); 640 641 return elem; 642 } 643 644 /* ibm,dynamic-memory-v2 */ 645 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 646 int offset, MemoryDeviceInfoList *dimms) 647 { 648 MachineState *machine = MACHINE(spapr); 649 uint8_t *int_buf, *cur_index; 650 int ret; 651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 652 uint64_t addr, cur_addr, size; 653 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 654 uint64_t mem_end = machine->device_memory->base + 655 memory_region_size(&machine->device_memory->mr); 656 uint32_t node, buf_len, nr_entries = 0; 657 SpaprDrc *drc; 658 DrconfCellQueue *elem, *next; 659 MemoryDeviceInfoList *info; 660 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 661 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 662 663 /* Entry to cover RAM and the gap area */ 664 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 665 SPAPR_LMB_FLAGS_RESERVED | 666 SPAPR_LMB_FLAGS_DRC_INVALID); 667 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 668 nr_entries++; 669 670 cur_addr = machine->device_memory->base; 671 for (info = dimms; info; info = info->next) { 672 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 673 674 addr = di->addr; 675 size = di->size; 676 node = di->node; 677 678 /* Entry for hot-pluggable area */ 679 if (cur_addr < addr) { 680 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 681 g_assert(drc); 682 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 683 cur_addr, spapr_drc_index(drc), -1, 0); 684 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 685 nr_entries++; 686 } 687 688 /* Entry for DIMM */ 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell(size / lmb_size, addr, 692 spapr_drc_index(drc), node, 693 SPAPR_LMB_FLAGS_ASSIGNED); 694 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 695 nr_entries++; 696 cur_addr = addr + size; 697 } 698 699 /* Entry for remaining hotpluggable area */ 700 if (cur_addr < mem_end) { 701 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 702 g_assert(drc); 703 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 704 cur_addr, spapr_drc_index(drc), -1, 0); 705 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 706 nr_entries++; 707 } 708 709 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 710 int_buf = cur_index = g_malloc0(buf_len); 711 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 712 cur_index += sizeof(nr_entries); 713 714 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 715 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 716 cur_index += sizeof(elem->cell); 717 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 718 g_free(elem); 719 } 720 721 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 722 g_free(int_buf); 723 if (ret < 0) { 724 return -1; 725 } 726 return 0; 727 } 728 729 /* ibm,dynamic-memory */ 730 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 731 int offset, MemoryDeviceInfoList *dimms) 732 { 733 MachineState *machine = MACHINE(spapr); 734 int i, ret; 735 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 736 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 737 uint32_t nr_lmbs = (machine->device_memory->base + 738 memory_region_size(&machine->device_memory->mr)) / 739 lmb_size; 740 uint32_t *int_buf, *cur_index, buf_len; 741 742 /* 743 * Allocate enough buffer size to fit in ibm,dynamic-memory 744 */ 745 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 746 cur_index = int_buf = g_malloc0(buf_len); 747 int_buf[0] = cpu_to_be32(nr_lmbs); 748 cur_index++; 749 for (i = 0; i < nr_lmbs; i++) { 750 uint64_t addr = i * lmb_size; 751 uint32_t *dynamic_memory = cur_index; 752 753 if (i >= device_lmb_start) { 754 SpaprDrc *drc; 755 756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 757 g_assert(drc); 758 759 dynamic_memory[0] = cpu_to_be32(addr >> 32); 760 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 761 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 762 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 763 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 764 if (memory_region_present(get_system_memory(), addr)) { 765 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 766 } else { 767 dynamic_memory[5] = cpu_to_be32(0); 768 } 769 } else { 770 /* 771 * LMB information for RMA, boot time RAM and gap b/n RAM and 772 * device memory region -- all these are marked as reserved 773 * and as having no valid DRC. 774 */ 775 dynamic_memory[0] = cpu_to_be32(addr >> 32); 776 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 777 dynamic_memory[2] = cpu_to_be32(0); 778 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 779 dynamic_memory[4] = cpu_to_be32(-1); 780 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 781 SPAPR_LMB_FLAGS_DRC_INVALID); 782 } 783 784 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 785 } 786 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 787 g_free(int_buf); 788 if (ret < 0) { 789 return -1; 790 } 791 return 0; 792 } 793 794 /* 795 * Adds ibm,dynamic-reconfiguration-memory node. 796 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 797 * of this device tree node. 798 */ 799 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 800 { 801 MachineState *machine = MACHINE(spapr); 802 int nb_numa_nodes = machine->numa_state->num_nodes; 803 int ret, i, offset; 804 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 805 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 806 uint32_t *int_buf, *cur_index, buf_len; 807 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 808 MemoryDeviceInfoList *dimms = NULL; 809 810 /* 811 * Don't create the node if there is no device memory 812 */ 813 if (machine->ram_size == machine->maxram_size) { 814 return 0; 815 } 816 817 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 818 819 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 820 sizeof(prop_lmb_size)); 821 if (ret < 0) { 822 return ret; 823 } 824 825 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 826 if (ret < 0) { 827 return ret; 828 } 829 830 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 831 if (ret < 0) { 832 return ret; 833 } 834 835 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 836 dimms = qmp_memory_device_list(); 837 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 838 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 839 } else { 840 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 841 } 842 qapi_free_MemoryDeviceInfoList(dimms); 843 844 if (ret < 0) { 845 return ret; 846 } 847 848 /* ibm,associativity-lookup-arrays */ 849 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 850 cur_index = int_buf = g_malloc0(buf_len); 851 int_buf[0] = cpu_to_be32(nr_nodes); 852 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 853 cur_index += 2; 854 for (i = 0; i < nr_nodes; i++) { 855 uint32_t associativity[] = { 856 cpu_to_be32(0x0), 857 cpu_to_be32(0x0), 858 cpu_to_be32(0x0), 859 cpu_to_be32(i) 860 }; 861 memcpy(cur_index, associativity, sizeof(associativity)); 862 cur_index += 4; 863 } 864 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 865 (cur_index - int_buf) * sizeof(uint32_t)); 866 g_free(int_buf); 867 868 return ret; 869 } 870 871 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 872 SpaprOptionVector *ov5_updates) 873 { 874 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 875 int ret = 0, offset; 876 877 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 878 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 879 g_assert(smc->dr_lmb_enabled); 880 ret = spapr_populate_drconf_memory(spapr, fdt); 881 if (ret) { 882 goto out; 883 } 884 } 885 886 offset = fdt_path_offset(fdt, "/chosen"); 887 if (offset < 0) { 888 offset = fdt_add_subnode(fdt, 0, "chosen"); 889 if (offset < 0) { 890 return offset; 891 } 892 } 893 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 894 "ibm,architecture-vec-5"); 895 896 out: 897 return ret; 898 } 899 900 static bool spapr_hotplugged_dev_before_cas(void) 901 { 902 Object *drc_container, *obj; 903 ObjectProperty *prop; 904 ObjectPropertyIterator iter; 905 906 drc_container = container_get(object_get_root(), "/dr-connector"); 907 object_property_iter_init(&iter, drc_container); 908 while ((prop = object_property_iter_next(&iter))) { 909 if (!strstart(prop->type, "link<", NULL)) { 910 continue; 911 } 912 obj = object_property_get_link(drc_container, prop->name, NULL); 913 if (spapr_drc_needed(obj)) { 914 return true; 915 } 916 } 917 return false; 918 } 919 920 static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, 921 size_t space); 922 923 int spapr_h_cas_compose_response(SpaprMachineState *spapr, 924 target_ulong addr, target_ulong size, 925 SpaprOptionVector *ov5_updates) 926 { 927 void *fdt; 928 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 929 930 if (spapr_hotplugged_dev_before_cas()) { 931 return 1; 932 } 933 934 if (size < sizeof(hdr)) { 935 error_report("SLOF provided insufficient CAS buffer " 936 TARGET_FMT_lu " (min: %zu)", size, sizeof(hdr)); 937 exit(EXIT_FAILURE); 938 } 939 940 size -= sizeof(hdr); 941 942 fdt = spapr_build_fdt(spapr, false, size); 943 _FDT((fdt_pack(fdt))); 944 945 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 946 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 947 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 948 949 g_free(spapr->fdt_blob); 950 spapr->fdt_size = fdt_totalsize(fdt); 951 spapr->fdt_initial_size = spapr->fdt_size; 952 spapr->fdt_blob = fdt; 953 954 return 0; 955 } 956 957 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 958 { 959 MachineState *ms = MACHINE(spapr); 960 int rtas; 961 GString *hypertas = g_string_sized_new(256); 962 GString *qemu_hypertas = g_string_sized_new(256); 963 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 964 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 965 memory_region_size(&MACHINE(spapr)->device_memory->mr); 966 uint32_t lrdr_capacity[] = { 967 cpu_to_be32(max_device_addr >> 32), 968 cpu_to_be32(max_device_addr & 0xffffffff), 969 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 970 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 971 }; 972 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 973 uint32_t maxdomains[] = { 974 cpu_to_be32(4), 975 maxdomain, 976 maxdomain, 977 maxdomain, 978 cpu_to_be32(spapr->gpu_numa_id), 979 }; 980 981 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 982 983 /* hypertas */ 984 add_str(hypertas, "hcall-pft"); 985 add_str(hypertas, "hcall-term"); 986 add_str(hypertas, "hcall-dabr"); 987 add_str(hypertas, "hcall-interrupt"); 988 add_str(hypertas, "hcall-tce"); 989 add_str(hypertas, "hcall-vio"); 990 add_str(hypertas, "hcall-splpar"); 991 add_str(hypertas, "hcall-join"); 992 add_str(hypertas, "hcall-bulk"); 993 add_str(hypertas, "hcall-set-mode"); 994 add_str(hypertas, "hcall-sprg0"); 995 add_str(hypertas, "hcall-copy"); 996 add_str(hypertas, "hcall-debug"); 997 add_str(hypertas, "hcall-vphn"); 998 add_str(qemu_hypertas, "hcall-memop1"); 999 1000 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1001 add_str(hypertas, "hcall-multi-tce"); 1002 } 1003 1004 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1005 add_str(hypertas, "hcall-hpt-resize"); 1006 } 1007 1008 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1009 hypertas->str, hypertas->len)); 1010 g_string_free(hypertas, TRUE); 1011 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1012 qemu_hypertas->str, qemu_hypertas->len)); 1013 g_string_free(qemu_hypertas, TRUE); 1014 1015 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1016 refpoints, sizeof(refpoints))); 1017 1018 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1019 maxdomains, sizeof(maxdomains))); 1020 1021 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1022 RTAS_ERROR_LOG_MAX)); 1023 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1024 RTAS_EVENT_SCAN_RATE)); 1025 1026 g_assert(msi_nonbroken); 1027 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1028 1029 /* 1030 * According to PAPR, rtas ibm,os-term does not guarantee a return 1031 * back to the guest cpu. 1032 * 1033 * While an additional ibm,extended-os-term property indicates 1034 * that rtas call return will always occur. Set this property. 1035 */ 1036 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1037 1038 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1039 lrdr_capacity, sizeof(lrdr_capacity))); 1040 1041 spapr_dt_rtas_tokens(fdt, rtas); 1042 } 1043 1044 /* 1045 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1046 * and the XIVE features that the guest may request and thus the valid 1047 * values for bytes 23..26 of option vector 5: 1048 */ 1049 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1050 int chosen) 1051 { 1052 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1053 1054 char val[2 * 4] = { 1055 23, 0x00, /* XICS / XIVE mode */ 1056 24, 0x00, /* Hash/Radix, filled in below. */ 1057 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1058 26, 0x40, /* Radix options: GTSE == yes. */ 1059 }; 1060 1061 if (spapr->irq->xics && spapr->irq->xive) { 1062 val[1] = SPAPR_OV5_XIVE_BOTH; 1063 } else if (spapr->irq->xive) { 1064 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1065 } else { 1066 assert(spapr->irq->xics); 1067 val[1] = SPAPR_OV5_XIVE_LEGACY; 1068 } 1069 1070 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1071 first_ppc_cpu->compat_pvr)) { 1072 /* 1073 * If we're in a pre POWER9 compat mode then the guest should 1074 * do hash and use the legacy interrupt mode 1075 */ 1076 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1077 val[3] = 0x00; /* Hash */ 1078 } else if (kvm_enabled()) { 1079 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1080 val[3] = 0x80; /* OV5_MMU_BOTH */ 1081 } else if (kvmppc_has_cap_mmu_radix()) { 1082 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1083 } else { 1084 val[3] = 0x00; /* Hash */ 1085 } 1086 } else { 1087 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1088 val[3] = 0xC0; 1089 } 1090 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1091 val, sizeof(val))); 1092 } 1093 1094 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1095 { 1096 MachineState *machine = MACHINE(spapr); 1097 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1098 int chosen; 1099 const char *boot_device = machine->boot_order; 1100 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1101 size_t cb = 0; 1102 char *bootlist = get_boot_devices_list(&cb); 1103 1104 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1105 1106 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1107 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1108 machine->kernel_cmdline)); 1109 } 1110 if (spapr->initrd_size) { 1111 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1112 spapr->initrd_base)); 1113 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1114 spapr->initrd_base + spapr->initrd_size)); 1115 } 1116 1117 if (spapr->kernel_size) { 1118 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1119 cpu_to_be64(spapr->kernel_size) }; 1120 1121 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1122 &kprop, sizeof(kprop))); 1123 if (spapr->kernel_le) { 1124 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1125 } 1126 } 1127 if (boot_menu) { 1128 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1129 } 1130 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1131 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1132 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1133 1134 if (cb && bootlist) { 1135 int i; 1136 1137 for (i = 0; i < cb; i++) { 1138 if (bootlist[i] == '\n') { 1139 bootlist[i] = ' '; 1140 } 1141 } 1142 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1143 } 1144 1145 if (boot_device && strlen(boot_device)) { 1146 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1147 } 1148 1149 if (!spapr->has_graphics && stdout_path) { 1150 /* 1151 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1152 * kernel. New platforms should only use the "stdout-path" property. Set 1153 * the new property and continue using older property to remain 1154 * compatible with the existing firmware. 1155 */ 1156 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1157 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1158 } 1159 1160 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1161 if (smc->linux_pci_probe) { 1162 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1163 } 1164 1165 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1166 1167 g_free(stdout_path); 1168 g_free(bootlist); 1169 } 1170 1171 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1172 { 1173 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1174 * KVM to work under pHyp with some guest co-operation */ 1175 int hypervisor; 1176 uint8_t hypercall[16]; 1177 1178 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1179 /* indicate KVM hypercall interface */ 1180 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1181 if (kvmppc_has_cap_fixup_hcalls()) { 1182 /* 1183 * Older KVM versions with older guest kernels were broken 1184 * with the magic page, don't allow the guest to map it. 1185 */ 1186 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1187 sizeof(hypercall))) { 1188 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1189 hypercall, sizeof(hypercall))); 1190 } 1191 } 1192 } 1193 1194 static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, 1195 size_t space) 1196 { 1197 MachineState *machine = MACHINE(spapr); 1198 MachineClass *mc = MACHINE_GET_CLASS(machine); 1199 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1200 int ret; 1201 void *fdt; 1202 SpaprPhbState *phb; 1203 char *buf; 1204 1205 fdt = g_malloc0(space); 1206 _FDT((fdt_create_empty_tree(fdt, space))); 1207 1208 /* Root node */ 1209 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1210 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1211 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1212 1213 /* Guest UUID & Name*/ 1214 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1215 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1216 if (qemu_uuid_set) { 1217 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1218 } 1219 g_free(buf); 1220 1221 if (qemu_get_vm_name()) { 1222 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1223 qemu_get_vm_name())); 1224 } 1225 1226 /* Host Model & Serial Number */ 1227 if (spapr->host_model) { 1228 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1229 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1230 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1231 g_free(buf); 1232 } 1233 1234 if (spapr->host_serial) { 1235 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1236 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1237 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1238 g_free(buf); 1239 } 1240 1241 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1242 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1243 1244 /* /interrupt controller */ 1245 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1246 1247 ret = spapr_populate_memory(spapr, fdt); 1248 if (ret < 0) { 1249 error_report("couldn't setup memory nodes in fdt"); 1250 exit(1); 1251 } 1252 1253 /* /vdevice */ 1254 spapr_dt_vdevice(spapr->vio_bus, fdt); 1255 1256 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1257 ret = spapr_rng_populate_dt(fdt); 1258 if (ret < 0) { 1259 error_report("could not set up rng device in the fdt"); 1260 exit(1); 1261 } 1262 } 1263 1264 QLIST_FOREACH(phb, &spapr->phbs, list) { 1265 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1266 if (ret < 0) { 1267 error_report("couldn't setup PCI devices in fdt"); 1268 exit(1); 1269 } 1270 } 1271 1272 /* cpus */ 1273 spapr_populate_cpus_dt_node(fdt, spapr); 1274 1275 if (smc->dr_lmb_enabled) { 1276 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1277 } 1278 1279 if (mc->has_hotpluggable_cpus) { 1280 int offset = fdt_path_offset(fdt, "/cpus"); 1281 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1282 if (ret < 0) { 1283 error_report("Couldn't set up CPU DR device tree properties"); 1284 exit(1); 1285 } 1286 } 1287 1288 /* /event-sources */ 1289 spapr_dt_events(spapr, fdt); 1290 1291 /* /rtas */ 1292 spapr_dt_rtas(spapr, fdt); 1293 1294 /* /chosen */ 1295 if (reset) { 1296 spapr_dt_chosen(spapr, fdt); 1297 } 1298 1299 /* /hypervisor */ 1300 if (kvm_enabled()) { 1301 spapr_dt_hypervisor(spapr, fdt); 1302 } 1303 1304 /* Build memory reserve map */ 1305 if (reset) { 1306 if (spapr->kernel_size) { 1307 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1308 } 1309 if (spapr->initrd_size) { 1310 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1311 spapr->initrd_size))); 1312 } 1313 } 1314 1315 /* ibm,client-architecture-support updates */ 1316 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1317 if (ret < 0) { 1318 error_report("couldn't setup CAS properties fdt"); 1319 exit(1); 1320 } 1321 1322 if (smc->dr_phb_enabled) { 1323 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1324 if (ret < 0) { 1325 error_report("Couldn't set up PHB DR device tree properties"); 1326 exit(1); 1327 } 1328 } 1329 1330 return fdt; 1331 } 1332 1333 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1334 { 1335 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1336 } 1337 1338 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1339 PowerPCCPU *cpu) 1340 { 1341 CPUPPCState *env = &cpu->env; 1342 1343 /* The TCG path should also be holding the BQL at this point */ 1344 g_assert(qemu_mutex_iothread_locked()); 1345 1346 if (msr_pr) { 1347 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1348 env->gpr[3] = H_PRIVILEGE; 1349 } else { 1350 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1351 } 1352 } 1353 1354 struct LPCRSyncState { 1355 target_ulong value; 1356 target_ulong mask; 1357 }; 1358 1359 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1360 { 1361 struct LPCRSyncState *s = arg.host_ptr; 1362 PowerPCCPU *cpu = POWERPC_CPU(cs); 1363 CPUPPCState *env = &cpu->env; 1364 target_ulong lpcr; 1365 1366 cpu_synchronize_state(cs); 1367 lpcr = env->spr[SPR_LPCR]; 1368 lpcr &= ~s->mask; 1369 lpcr |= s->value; 1370 ppc_store_lpcr(cpu, lpcr); 1371 } 1372 1373 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1374 { 1375 CPUState *cs; 1376 struct LPCRSyncState s = { 1377 .value = value, 1378 .mask = mask 1379 }; 1380 CPU_FOREACH(cs) { 1381 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1382 } 1383 } 1384 1385 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1386 { 1387 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1388 1389 /* Copy PATE1:GR into PATE0:HR */ 1390 entry->dw0 = spapr->patb_entry & PATE0_HR; 1391 entry->dw1 = spapr->patb_entry; 1392 } 1393 1394 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1395 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1396 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1397 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1398 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1399 1400 /* 1401 * Get the fd to access the kernel htab, re-opening it if necessary 1402 */ 1403 static int get_htab_fd(SpaprMachineState *spapr) 1404 { 1405 Error *local_err = NULL; 1406 1407 if (spapr->htab_fd >= 0) { 1408 return spapr->htab_fd; 1409 } 1410 1411 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1412 if (spapr->htab_fd < 0) { 1413 error_report_err(local_err); 1414 } 1415 1416 return spapr->htab_fd; 1417 } 1418 1419 void close_htab_fd(SpaprMachineState *spapr) 1420 { 1421 if (spapr->htab_fd >= 0) { 1422 close(spapr->htab_fd); 1423 } 1424 spapr->htab_fd = -1; 1425 } 1426 1427 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1428 { 1429 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1430 1431 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1432 } 1433 1434 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1435 { 1436 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1437 1438 assert(kvm_enabled()); 1439 1440 if (!spapr->htab) { 1441 return 0; 1442 } 1443 1444 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1445 } 1446 1447 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1448 hwaddr ptex, int n) 1449 { 1450 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1451 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1452 1453 if (!spapr->htab) { 1454 /* 1455 * HTAB is controlled by KVM. Fetch into temporary buffer 1456 */ 1457 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1458 kvmppc_read_hptes(hptes, ptex, n); 1459 return hptes; 1460 } 1461 1462 /* 1463 * HTAB is controlled by QEMU. Just point to the internally 1464 * accessible PTEG. 1465 */ 1466 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1467 } 1468 1469 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1470 const ppc_hash_pte64_t *hptes, 1471 hwaddr ptex, int n) 1472 { 1473 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1474 1475 if (!spapr->htab) { 1476 g_free((void *)hptes); 1477 } 1478 1479 /* Nothing to do for qemu managed HPT */ 1480 } 1481 1482 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1483 uint64_t pte0, uint64_t pte1) 1484 { 1485 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1486 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1487 1488 if (!spapr->htab) { 1489 kvmppc_write_hpte(ptex, pte0, pte1); 1490 } else { 1491 if (pte0 & HPTE64_V_VALID) { 1492 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1493 /* 1494 * When setting valid, we write PTE1 first. This ensures 1495 * proper synchronization with the reading code in 1496 * ppc_hash64_pteg_search() 1497 */ 1498 smp_wmb(); 1499 stq_p(spapr->htab + offset, pte0); 1500 } else { 1501 stq_p(spapr->htab + offset, pte0); 1502 /* 1503 * When clearing it we set PTE0 first. This ensures proper 1504 * synchronization with the reading code in 1505 * ppc_hash64_pteg_search() 1506 */ 1507 smp_wmb(); 1508 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1509 } 1510 } 1511 } 1512 1513 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1514 uint64_t pte1) 1515 { 1516 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1517 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1518 1519 if (!spapr->htab) { 1520 /* There should always be a hash table when this is called */ 1521 error_report("spapr_hpte_set_c called with no hash table !"); 1522 return; 1523 } 1524 1525 /* The HW performs a non-atomic byte update */ 1526 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1527 } 1528 1529 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1530 uint64_t pte1) 1531 { 1532 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1533 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1534 1535 if (!spapr->htab) { 1536 /* There should always be a hash table when this is called */ 1537 error_report("spapr_hpte_set_r called with no hash table !"); 1538 return; 1539 } 1540 1541 /* The HW performs a non-atomic byte update */ 1542 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1543 } 1544 1545 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1546 { 1547 int shift; 1548 1549 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1550 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1551 * that's much more than is needed for Linux guests */ 1552 shift = ctz64(pow2ceil(ramsize)) - 7; 1553 shift = MAX(shift, 18); /* Minimum architected size */ 1554 shift = MIN(shift, 46); /* Maximum architected size */ 1555 return shift; 1556 } 1557 1558 void spapr_free_hpt(SpaprMachineState *spapr) 1559 { 1560 g_free(spapr->htab); 1561 spapr->htab = NULL; 1562 spapr->htab_shift = 0; 1563 close_htab_fd(spapr); 1564 } 1565 1566 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1567 Error **errp) 1568 { 1569 long rc; 1570 1571 /* Clean up any HPT info from a previous boot */ 1572 spapr_free_hpt(spapr); 1573 1574 rc = kvmppc_reset_htab(shift); 1575 if (rc < 0) { 1576 /* kernel-side HPT needed, but couldn't allocate one */ 1577 error_setg_errno(errp, errno, 1578 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1579 shift); 1580 /* This is almost certainly fatal, but if the caller really 1581 * wants to carry on with shift == 0, it's welcome to try */ 1582 } else if (rc > 0) { 1583 /* kernel-side HPT allocated */ 1584 if (rc != shift) { 1585 error_setg(errp, 1586 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1587 shift, rc); 1588 } 1589 1590 spapr->htab_shift = shift; 1591 spapr->htab = NULL; 1592 } else { 1593 /* kernel-side HPT not needed, allocate in userspace instead */ 1594 size_t size = 1ULL << shift; 1595 int i; 1596 1597 spapr->htab = qemu_memalign(size, size); 1598 if (!spapr->htab) { 1599 error_setg_errno(errp, errno, 1600 "Could not allocate HPT of order %d", shift); 1601 return; 1602 } 1603 1604 memset(spapr->htab, 0, size); 1605 spapr->htab_shift = shift; 1606 1607 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1608 DIRTY_HPTE(HPTE(spapr->htab, i)); 1609 } 1610 } 1611 /* We're setting up a hash table, so that means we're not radix */ 1612 spapr->patb_entry = 0; 1613 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1614 } 1615 1616 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1617 { 1618 int hpt_shift; 1619 1620 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1621 || (spapr->cas_reboot 1622 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1623 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1624 } else { 1625 uint64_t current_ram_size; 1626 1627 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1628 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1629 } 1630 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1631 1632 if (spapr->vrma_adjust) { 1633 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1634 spapr->htab_shift); 1635 } 1636 } 1637 1638 static int spapr_reset_drcs(Object *child, void *opaque) 1639 { 1640 SpaprDrc *drc = 1641 (SpaprDrc *) object_dynamic_cast(child, 1642 TYPE_SPAPR_DR_CONNECTOR); 1643 1644 if (drc) { 1645 spapr_drc_reset(drc); 1646 } 1647 1648 return 0; 1649 } 1650 1651 static void spapr_machine_reset(MachineState *machine) 1652 { 1653 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1654 PowerPCCPU *first_ppc_cpu; 1655 hwaddr fdt_addr; 1656 void *fdt; 1657 int rc; 1658 1659 spapr_caps_apply(spapr); 1660 1661 first_ppc_cpu = POWERPC_CPU(first_cpu); 1662 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1663 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1664 spapr->max_compat_pvr)) { 1665 /* 1666 * If using KVM with radix mode available, VCPUs can be started 1667 * without a HPT because KVM will start them in radix mode. 1668 * Set the GR bit in PATE so that we know there is no HPT. 1669 */ 1670 spapr->patb_entry = PATE1_GR; 1671 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1672 } else { 1673 spapr_setup_hpt_and_vrma(spapr); 1674 } 1675 1676 qemu_devices_reset(); 1677 1678 /* 1679 * If this reset wasn't generated by CAS, we should reset our 1680 * negotiated options and start from scratch 1681 */ 1682 if (!spapr->cas_reboot) { 1683 spapr_ovec_cleanup(spapr->ov5_cas); 1684 spapr->ov5_cas = spapr_ovec_new(); 1685 1686 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1687 } 1688 1689 /* 1690 * This is fixing some of the default configuration of the XIVE 1691 * devices. To be called after the reset of the machine devices. 1692 */ 1693 spapr_irq_reset(spapr, &error_fatal); 1694 1695 /* 1696 * There is no CAS under qtest. Simulate one to please the code that 1697 * depends on spapr->ov5_cas. This is especially needed to test device 1698 * unplug, so we do that before resetting the DRCs. 1699 */ 1700 if (qtest_enabled()) { 1701 spapr_ovec_cleanup(spapr->ov5_cas); 1702 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1703 } 1704 1705 /* DRC reset may cause a device to be unplugged. This will cause troubles 1706 * if this device is used by another device (eg, a running vhost backend 1707 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1708 * situations, we reset DRCs after all devices have been reset. 1709 */ 1710 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1711 1712 spapr_clear_pending_events(spapr); 1713 1714 /* 1715 * We place the device tree and RTAS just below either the top of the RMA, 1716 * or just below 2GB, whichever is lower, so that it can be 1717 * processed with 32-bit real mode code if necessary 1718 */ 1719 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1720 1721 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1722 1723 rc = fdt_pack(fdt); 1724 1725 /* Should only fail if we've built a corrupted tree */ 1726 assert(rc == 0); 1727 1728 /* Load the fdt */ 1729 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1730 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1731 g_free(spapr->fdt_blob); 1732 spapr->fdt_size = fdt_totalsize(fdt); 1733 spapr->fdt_initial_size = spapr->fdt_size; 1734 spapr->fdt_blob = fdt; 1735 1736 /* Set up the entry state */ 1737 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1738 first_ppc_cpu->env.gpr[5] = 0; 1739 1740 spapr->cas_reboot = false; 1741 } 1742 1743 static void spapr_create_nvram(SpaprMachineState *spapr) 1744 { 1745 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1746 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1747 1748 if (dinfo) { 1749 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1750 &error_fatal); 1751 } 1752 1753 qdev_init_nofail(dev); 1754 1755 spapr->nvram = (struct SpaprNvram *)dev; 1756 } 1757 1758 static void spapr_rtc_create(SpaprMachineState *spapr) 1759 { 1760 object_initialize_child(OBJECT(spapr), "rtc", 1761 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1762 &error_fatal, NULL); 1763 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1764 &error_fatal); 1765 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1766 "date", &error_fatal); 1767 } 1768 1769 /* Returns whether we want to use VGA or not */ 1770 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1771 { 1772 switch (vga_interface_type) { 1773 case VGA_NONE: 1774 return false; 1775 case VGA_DEVICE: 1776 return true; 1777 case VGA_STD: 1778 case VGA_VIRTIO: 1779 case VGA_CIRRUS: 1780 return pci_vga_init(pci_bus) != NULL; 1781 default: 1782 error_setg(errp, 1783 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1784 return false; 1785 } 1786 } 1787 1788 static int spapr_pre_load(void *opaque) 1789 { 1790 int rc; 1791 1792 rc = spapr_caps_pre_load(opaque); 1793 if (rc) { 1794 return rc; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static int spapr_post_load(void *opaque, int version_id) 1801 { 1802 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1803 int err = 0; 1804 1805 err = spapr_caps_post_migration(spapr); 1806 if (err) { 1807 return err; 1808 } 1809 1810 /* 1811 * In earlier versions, there was no separate qdev for the PAPR 1812 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1813 * So when migrating from those versions, poke the incoming offset 1814 * value into the RTC device 1815 */ 1816 if (version_id < 3) { 1817 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1818 if (err) { 1819 return err; 1820 } 1821 } 1822 1823 if (kvm_enabled() && spapr->patb_entry) { 1824 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1825 bool radix = !!(spapr->patb_entry & PATE1_GR); 1826 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1827 1828 /* 1829 * Update LPCR:HR and UPRT as they may not be set properly in 1830 * the stream 1831 */ 1832 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1833 LPCR_HR | LPCR_UPRT); 1834 1835 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1836 if (err) { 1837 error_report("Process table config unsupported by the host"); 1838 return -EINVAL; 1839 } 1840 } 1841 1842 err = spapr_irq_post_load(spapr, version_id); 1843 if (err) { 1844 return err; 1845 } 1846 1847 return err; 1848 } 1849 1850 static int spapr_pre_save(void *opaque) 1851 { 1852 int rc; 1853 1854 rc = spapr_caps_pre_save(opaque); 1855 if (rc) { 1856 return rc; 1857 } 1858 1859 return 0; 1860 } 1861 1862 static bool version_before_3(void *opaque, int version_id) 1863 { 1864 return version_id < 3; 1865 } 1866 1867 static bool spapr_pending_events_needed(void *opaque) 1868 { 1869 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1870 return !QTAILQ_EMPTY(&spapr->pending_events); 1871 } 1872 1873 static const VMStateDescription vmstate_spapr_event_entry = { 1874 .name = "spapr_event_log_entry", 1875 .version_id = 1, 1876 .minimum_version_id = 1, 1877 .fields = (VMStateField[]) { 1878 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1879 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1880 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1881 NULL, extended_length), 1882 VMSTATE_END_OF_LIST() 1883 }, 1884 }; 1885 1886 static const VMStateDescription vmstate_spapr_pending_events = { 1887 .name = "spapr_pending_events", 1888 .version_id = 1, 1889 .minimum_version_id = 1, 1890 .needed = spapr_pending_events_needed, 1891 .fields = (VMStateField[]) { 1892 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1893 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1894 VMSTATE_END_OF_LIST() 1895 }, 1896 }; 1897 1898 static bool spapr_ov5_cas_needed(void *opaque) 1899 { 1900 SpaprMachineState *spapr = opaque; 1901 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1902 SpaprOptionVector *ov5_legacy = spapr_ovec_new(); 1903 SpaprOptionVector *ov5_removed = spapr_ovec_new(); 1904 bool cas_needed; 1905 1906 /* Prior to the introduction of SpaprOptionVector, we had two option 1907 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1908 * Both of these options encode machine topology into the device-tree 1909 * in such a way that the now-booted OS should still be able to interact 1910 * appropriately with QEMU regardless of what options were actually 1911 * negotiatied on the source side. 1912 * 1913 * As such, we can avoid migrating the CAS-negotiated options if these 1914 * are the only options available on the current machine/platform. 1915 * Since these are the only options available for pseries-2.7 and 1916 * earlier, this allows us to maintain old->new/new->old migration 1917 * compatibility. 1918 * 1919 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1920 * via default pseries-2.8 machines and explicit command-line parameters. 1921 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1922 * of the actual CAS-negotiated values to continue working properly. For 1923 * example, availability of memory unplug depends on knowing whether 1924 * OV5_HP_EVT was negotiated via CAS. 1925 * 1926 * Thus, for any cases where the set of available CAS-negotiatable 1927 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1928 * include the CAS-negotiated options in the migration stream, unless 1929 * if they affect boot time behaviour only. 1930 */ 1931 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1932 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1933 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1934 1935 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1936 * the mask itself since in the future it's possible "legacy" bits may be 1937 * removed via machine options, which could generate a false positive 1938 * that breaks migration. 1939 */ 1940 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1941 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1942 1943 spapr_ovec_cleanup(ov5_mask); 1944 spapr_ovec_cleanup(ov5_legacy); 1945 spapr_ovec_cleanup(ov5_removed); 1946 1947 return cas_needed; 1948 } 1949 1950 static const VMStateDescription vmstate_spapr_ov5_cas = { 1951 .name = "spapr_option_vector_ov5_cas", 1952 .version_id = 1, 1953 .minimum_version_id = 1, 1954 .needed = spapr_ov5_cas_needed, 1955 .fields = (VMStateField[]) { 1956 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1957 vmstate_spapr_ovec, SpaprOptionVector), 1958 VMSTATE_END_OF_LIST() 1959 }, 1960 }; 1961 1962 static bool spapr_patb_entry_needed(void *opaque) 1963 { 1964 SpaprMachineState *spapr = opaque; 1965 1966 return !!spapr->patb_entry; 1967 } 1968 1969 static const VMStateDescription vmstate_spapr_patb_entry = { 1970 .name = "spapr_patb_entry", 1971 .version_id = 1, 1972 .minimum_version_id = 1, 1973 .needed = spapr_patb_entry_needed, 1974 .fields = (VMStateField[]) { 1975 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1976 VMSTATE_END_OF_LIST() 1977 }, 1978 }; 1979 1980 static bool spapr_irq_map_needed(void *opaque) 1981 { 1982 SpaprMachineState *spapr = opaque; 1983 1984 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1985 } 1986 1987 static const VMStateDescription vmstate_spapr_irq_map = { 1988 .name = "spapr_irq_map", 1989 .version_id = 1, 1990 .minimum_version_id = 1, 1991 .needed = spapr_irq_map_needed, 1992 .fields = (VMStateField[]) { 1993 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1994 VMSTATE_END_OF_LIST() 1995 }, 1996 }; 1997 1998 static bool spapr_dtb_needed(void *opaque) 1999 { 2000 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2001 2002 return smc->update_dt_enabled; 2003 } 2004 2005 static int spapr_dtb_pre_load(void *opaque) 2006 { 2007 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2008 2009 g_free(spapr->fdt_blob); 2010 spapr->fdt_blob = NULL; 2011 spapr->fdt_size = 0; 2012 2013 return 0; 2014 } 2015 2016 static const VMStateDescription vmstate_spapr_dtb = { 2017 .name = "spapr_dtb", 2018 .version_id = 1, 2019 .minimum_version_id = 1, 2020 .needed = spapr_dtb_needed, 2021 .pre_load = spapr_dtb_pre_load, 2022 .fields = (VMStateField[]) { 2023 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2024 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2025 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2026 fdt_size), 2027 VMSTATE_END_OF_LIST() 2028 }, 2029 }; 2030 2031 static const VMStateDescription vmstate_spapr = { 2032 .name = "spapr", 2033 .version_id = 3, 2034 .minimum_version_id = 1, 2035 .pre_load = spapr_pre_load, 2036 .post_load = spapr_post_load, 2037 .pre_save = spapr_pre_save, 2038 .fields = (VMStateField[]) { 2039 /* used to be @next_irq */ 2040 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2041 2042 /* RTC offset */ 2043 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2044 2045 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2046 VMSTATE_END_OF_LIST() 2047 }, 2048 .subsections = (const VMStateDescription*[]) { 2049 &vmstate_spapr_ov5_cas, 2050 &vmstate_spapr_patb_entry, 2051 &vmstate_spapr_pending_events, 2052 &vmstate_spapr_cap_htm, 2053 &vmstate_spapr_cap_vsx, 2054 &vmstate_spapr_cap_dfp, 2055 &vmstate_spapr_cap_cfpc, 2056 &vmstate_spapr_cap_sbbc, 2057 &vmstate_spapr_cap_ibs, 2058 &vmstate_spapr_cap_hpt_maxpagesize, 2059 &vmstate_spapr_irq_map, 2060 &vmstate_spapr_cap_nested_kvm_hv, 2061 &vmstate_spapr_dtb, 2062 &vmstate_spapr_cap_large_decr, 2063 &vmstate_spapr_cap_ccf_assist, 2064 NULL 2065 } 2066 }; 2067 2068 static int htab_save_setup(QEMUFile *f, void *opaque) 2069 { 2070 SpaprMachineState *spapr = opaque; 2071 2072 /* "Iteration" header */ 2073 if (!spapr->htab_shift) { 2074 qemu_put_be32(f, -1); 2075 } else { 2076 qemu_put_be32(f, spapr->htab_shift); 2077 } 2078 2079 if (spapr->htab) { 2080 spapr->htab_save_index = 0; 2081 spapr->htab_first_pass = true; 2082 } else { 2083 if (spapr->htab_shift) { 2084 assert(kvm_enabled()); 2085 } 2086 } 2087 2088 2089 return 0; 2090 } 2091 2092 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2093 int chunkstart, int n_valid, int n_invalid) 2094 { 2095 qemu_put_be32(f, chunkstart); 2096 qemu_put_be16(f, n_valid); 2097 qemu_put_be16(f, n_invalid); 2098 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2099 HASH_PTE_SIZE_64 * n_valid); 2100 } 2101 2102 static void htab_save_end_marker(QEMUFile *f) 2103 { 2104 qemu_put_be32(f, 0); 2105 qemu_put_be16(f, 0); 2106 qemu_put_be16(f, 0); 2107 } 2108 2109 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2110 int64_t max_ns) 2111 { 2112 bool has_timeout = max_ns != -1; 2113 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2114 int index = spapr->htab_save_index; 2115 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2116 2117 assert(spapr->htab_first_pass); 2118 2119 do { 2120 int chunkstart; 2121 2122 /* Consume invalid HPTEs */ 2123 while ((index < htabslots) 2124 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2125 CLEAN_HPTE(HPTE(spapr->htab, index)); 2126 index++; 2127 } 2128 2129 /* Consume valid HPTEs */ 2130 chunkstart = index; 2131 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2132 && HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 } 2136 2137 if (index > chunkstart) { 2138 int n_valid = index - chunkstart; 2139 2140 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2141 2142 if (has_timeout && 2143 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2144 break; 2145 } 2146 } 2147 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2148 2149 if (index >= htabslots) { 2150 assert(index == htabslots); 2151 index = 0; 2152 spapr->htab_first_pass = false; 2153 } 2154 spapr->htab_save_index = index; 2155 } 2156 2157 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2158 int64_t max_ns) 2159 { 2160 bool final = max_ns < 0; 2161 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2162 int examined = 0, sent = 0; 2163 int index = spapr->htab_save_index; 2164 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2165 2166 assert(!spapr->htab_first_pass); 2167 2168 do { 2169 int chunkstart, invalidstart; 2170 2171 /* Consume non-dirty HPTEs */ 2172 while ((index < htabslots) 2173 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2174 index++; 2175 examined++; 2176 } 2177 2178 chunkstart = index; 2179 /* Consume valid dirty HPTEs */ 2180 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2181 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2182 && HPTE_VALID(HPTE(spapr->htab, index))) { 2183 CLEAN_HPTE(HPTE(spapr->htab, index)); 2184 index++; 2185 examined++; 2186 } 2187 2188 invalidstart = index; 2189 /* Consume invalid dirty HPTEs */ 2190 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2191 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2192 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2193 CLEAN_HPTE(HPTE(spapr->htab, index)); 2194 index++; 2195 examined++; 2196 } 2197 2198 if (index > chunkstart) { 2199 int n_valid = invalidstart - chunkstart; 2200 int n_invalid = index - invalidstart; 2201 2202 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2203 sent += index - chunkstart; 2204 2205 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2206 break; 2207 } 2208 } 2209 2210 if (examined >= htabslots) { 2211 break; 2212 } 2213 2214 if (index >= htabslots) { 2215 assert(index == htabslots); 2216 index = 0; 2217 } 2218 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2219 2220 if (index >= htabslots) { 2221 assert(index == htabslots); 2222 index = 0; 2223 } 2224 2225 spapr->htab_save_index = index; 2226 2227 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2228 } 2229 2230 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2231 #define MAX_KVM_BUF_SIZE 2048 2232 2233 static int htab_save_iterate(QEMUFile *f, void *opaque) 2234 { 2235 SpaprMachineState *spapr = opaque; 2236 int fd; 2237 int rc = 0; 2238 2239 /* Iteration header */ 2240 if (!spapr->htab_shift) { 2241 qemu_put_be32(f, -1); 2242 return 1; 2243 } else { 2244 qemu_put_be32(f, 0); 2245 } 2246 2247 if (!spapr->htab) { 2248 assert(kvm_enabled()); 2249 2250 fd = get_htab_fd(spapr); 2251 if (fd < 0) { 2252 return fd; 2253 } 2254 2255 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2256 if (rc < 0) { 2257 return rc; 2258 } 2259 } else if (spapr->htab_first_pass) { 2260 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2261 } else { 2262 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2263 } 2264 2265 htab_save_end_marker(f); 2266 2267 return rc; 2268 } 2269 2270 static int htab_save_complete(QEMUFile *f, void *opaque) 2271 { 2272 SpaprMachineState *spapr = opaque; 2273 int fd; 2274 2275 /* Iteration header */ 2276 if (!spapr->htab_shift) { 2277 qemu_put_be32(f, -1); 2278 return 0; 2279 } else { 2280 qemu_put_be32(f, 0); 2281 } 2282 2283 if (!spapr->htab) { 2284 int rc; 2285 2286 assert(kvm_enabled()); 2287 2288 fd = get_htab_fd(spapr); 2289 if (fd < 0) { 2290 return fd; 2291 } 2292 2293 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2294 if (rc < 0) { 2295 return rc; 2296 } 2297 } else { 2298 if (spapr->htab_first_pass) { 2299 htab_save_first_pass(f, spapr, -1); 2300 } 2301 htab_save_later_pass(f, spapr, -1); 2302 } 2303 2304 /* End marker */ 2305 htab_save_end_marker(f); 2306 2307 return 0; 2308 } 2309 2310 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2311 { 2312 SpaprMachineState *spapr = opaque; 2313 uint32_t section_hdr; 2314 int fd = -1; 2315 Error *local_err = NULL; 2316 2317 if (version_id < 1 || version_id > 1) { 2318 error_report("htab_load() bad version"); 2319 return -EINVAL; 2320 } 2321 2322 section_hdr = qemu_get_be32(f); 2323 2324 if (section_hdr == -1) { 2325 spapr_free_hpt(spapr); 2326 return 0; 2327 } 2328 2329 if (section_hdr) { 2330 /* First section gives the htab size */ 2331 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2332 if (local_err) { 2333 error_report_err(local_err); 2334 return -EINVAL; 2335 } 2336 return 0; 2337 } 2338 2339 if (!spapr->htab) { 2340 assert(kvm_enabled()); 2341 2342 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2343 if (fd < 0) { 2344 error_report_err(local_err); 2345 return fd; 2346 } 2347 } 2348 2349 while (true) { 2350 uint32_t index; 2351 uint16_t n_valid, n_invalid; 2352 2353 index = qemu_get_be32(f); 2354 n_valid = qemu_get_be16(f); 2355 n_invalid = qemu_get_be16(f); 2356 2357 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2358 /* End of Stream */ 2359 break; 2360 } 2361 2362 if ((index + n_valid + n_invalid) > 2363 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2364 /* Bad index in stream */ 2365 error_report( 2366 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2367 index, n_valid, n_invalid, spapr->htab_shift); 2368 return -EINVAL; 2369 } 2370 2371 if (spapr->htab) { 2372 if (n_valid) { 2373 qemu_get_buffer(f, HPTE(spapr->htab, index), 2374 HASH_PTE_SIZE_64 * n_valid); 2375 } 2376 if (n_invalid) { 2377 memset(HPTE(spapr->htab, index + n_valid), 0, 2378 HASH_PTE_SIZE_64 * n_invalid); 2379 } 2380 } else { 2381 int rc; 2382 2383 assert(fd >= 0); 2384 2385 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2386 if (rc < 0) { 2387 return rc; 2388 } 2389 } 2390 } 2391 2392 if (!spapr->htab) { 2393 assert(fd >= 0); 2394 close(fd); 2395 } 2396 2397 return 0; 2398 } 2399 2400 static void htab_save_cleanup(void *opaque) 2401 { 2402 SpaprMachineState *spapr = opaque; 2403 2404 close_htab_fd(spapr); 2405 } 2406 2407 static SaveVMHandlers savevm_htab_handlers = { 2408 .save_setup = htab_save_setup, 2409 .save_live_iterate = htab_save_iterate, 2410 .save_live_complete_precopy = htab_save_complete, 2411 .save_cleanup = htab_save_cleanup, 2412 .load_state = htab_load, 2413 }; 2414 2415 static void spapr_boot_set(void *opaque, const char *boot_device, 2416 Error **errp) 2417 { 2418 MachineState *machine = MACHINE(opaque); 2419 machine->boot_order = g_strdup(boot_device); 2420 } 2421 2422 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2423 { 2424 MachineState *machine = MACHINE(spapr); 2425 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2426 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2427 int i; 2428 2429 for (i = 0; i < nr_lmbs; i++) { 2430 uint64_t addr; 2431 2432 addr = i * lmb_size + machine->device_memory->base; 2433 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2434 addr / lmb_size); 2435 } 2436 } 2437 2438 /* 2439 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2440 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2441 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2442 */ 2443 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2444 { 2445 int i; 2446 2447 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2448 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2449 " is not aligned to %" PRIu64 " MiB", 2450 machine->ram_size, 2451 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2452 return; 2453 } 2454 2455 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2456 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2457 " is not aligned to %" PRIu64 " MiB", 2458 machine->ram_size, 2459 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2460 return; 2461 } 2462 2463 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2464 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2465 error_setg(errp, 2466 "Node %d memory size 0x%" PRIx64 2467 " is not aligned to %" PRIu64 " MiB", 2468 i, machine->numa_state->nodes[i].node_mem, 2469 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2470 return; 2471 } 2472 } 2473 } 2474 2475 /* find cpu slot in machine->possible_cpus by core_id */ 2476 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2477 { 2478 int index = id / ms->smp.threads; 2479 2480 if (index >= ms->possible_cpus->len) { 2481 return NULL; 2482 } 2483 if (idx) { 2484 *idx = index; 2485 } 2486 return &ms->possible_cpus->cpus[index]; 2487 } 2488 2489 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2490 { 2491 MachineState *ms = MACHINE(spapr); 2492 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2493 Error *local_err = NULL; 2494 bool vsmt_user = !!spapr->vsmt; 2495 int kvm_smt = kvmppc_smt_threads(); 2496 int ret; 2497 unsigned int smp_threads = ms->smp.threads; 2498 2499 if (!kvm_enabled() && (smp_threads > 1)) { 2500 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2501 "on a pseries machine"); 2502 goto out; 2503 } 2504 if (!is_power_of_2(smp_threads)) { 2505 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2506 "machine because it must be a power of 2", smp_threads); 2507 goto out; 2508 } 2509 2510 /* Detemine the VSMT mode to use: */ 2511 if (vsmt_user) { 2512 if (spapr->vsmt < smp_threads) { 2513 error_setg(&local_err, "Cannot support VSMT mode %d" 2514 " because it must be >= threads/core (%d)", 2515 spapr->vsmt, smp_threads); 2516 goto out; 2517 } 2518 /* In this case, spapr->vsmt has been set by the command line */ 2519 } else if (!smc->smp_threads_vsmt) { 2520 /* 2521 * Default VSMT value is tricky, because we need it to be as 2522 * consistent as possible (for migration), but this requires 2523 * changing it for at least some existing cases. We pick 8 as 2524 * the value that we'd get with KVM on POWER8, the 2525 * overwhelmingly common case in production systems. 2526 */ 2527 spapr->vsmt = MAX(8, smp_threads); 2528 } else { 2529 spapr->vsmt = smp_threads; 2530 } 2531 2532 /* KVM: If necessary, set the SMT mode: */ 2533 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2534 ret = kvmppc_set_smt_threads(spapr->vsmt); 2535 if (ret) { 2536 /* Looks like KVM isn't able to change VSMT mode */ 2537 error_setg(&local_err, 2538 "Failed to set KVM's VSMT mode to %d (errno %d)", 2539 spapr->vsmt, ret); 2540 /* We can live with that if the default one is big enough 2541 * for the number of threads, and a submultiple of the one 2542 * we want. In this case we'll waste some vcpu ids, but 2543 * behaviour will be correct */ 2544 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2545 warn_report_err(local_err); 2546 local_err = NULL; 2547 goto out; 2548 } else { 2549 if (!vsmt_user) { 2550 error_append_hint(&local_err, 2551 "On PPC, a VM with %d threads/core" 2552 " on a host with %d threads/core" 2553 " requires the use of VSMT mode %d.\n", 2554 smp_threads, kvm_smt, spapr->vsmt); 2555 } 2556 kvmppc_error_append_smt_possible_hint(&local_err); 2557 goto out; 2558 } 2559 } 2560 } 2561 /* else TCG: nothing to do currently */ 2562 out: 2563 error_propagate(errp, local_err); 2564 } 2565 2566 static void spapr_init_cpus(SpaprMachineState *spapr) 2567 { 2568 MachineState *machine = MACHINE(spapr); 2569 MachineClass *mc = MACHINE_GET_CLASS(machine); 2570 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2571 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2572 const CPUArchIdList *possible_cpus; 2573 unsigned int smp_cpus = machine->smp.cpus; 2574 unsigned int smp_threads = machine->smp.threads; 2575 unsigned int max_cpus = machine->smp.max_cpus; 2576 int boot_cores_nr = smp_cpus / smp_threads; 2577 int i; 2578 2579 possible_cpus = mc->possible_cpu_arch_ids(machine); 2580 if (mc->has_hotpluggable_cpus) { 2581 if (smp_cpus % smp_threads) { 2582 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2583 smp_cpus, smp_threads); 2584 exit(1); 2585 } 2586 if (max_cpus % smp_threads) { 2587 error_report("max_cpus (%u) must be multiple of threads (%u)", 2588 max_cpus, smp_threads); 2589 exit(1); 2590 } 2591 } else { 2592 if (max_cpus != smp_cpus) { 2593 error_report("This machine version does not support CPU hotplug"); 2594 exit(1); 2595 } 2596 boot_cores_nr = possible_cpus->len; 2597 } 2598 2599 if (smc->pre_2_10_has_unused_icps) { 2600 int i; 2601 2602 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2603 /* Dummy entries get deregistered when real ICPState objects 2604 * are registered during CPU core hotplug. 2605 */ 2606 pre_2_10_vmstate_register_dummy_icp(i); 2607 } 2608 } 2609 2610 for (i = 0; i < possible_cpus->len; i++) { 2611 int core_id = i * smp_threads; 2612 2613 if (mc->has_hotpluggable_cpus) { 2614 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2615 spapr_vcpu_id(spapr, core_id)); 2616 } 2617 2618 if (i < boot_cores_nr) { 2619 Object *core = object_new(type); 2620 int nr_threads = smp_threads; 2621 2622 /* Handle the partially filled core for older machine types */ 2623 if ((i + 1) * smp_threads >= smp_cpus) { 2624 nr_threads = smp_cpus - i * smp_threads; 2625 } 2626 2627 object_property_set_int(core, nr_threads, "nr-threads", 2628 &error_fatal); 2629 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2630 &error_fatal); 2631 object_property_set_bool(core, true, "realized", &error_fatal); 2632 2633 object_unref(core); 2634 } 2635 } 2636 } 2637 2638 static PCIHostState *spapr_create_default_phb(void) 2639 { 2640 DeviceState *dev; 2641 2642 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2643 qdev_prop_set_uint32(dev, "index", 0); 2644 qdev_init_nofail(dev); 2645 2646 return PCI_HOST_BRIDGE(dev); 2647 } 2648 2649 /* pSeries LPAR / sPAPR hardware init */ 2650 static void spapr_machine_init(MachineState *machine) 2651 { 2652 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2653 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2654 const char *kernel_filename = machine->kernel_filename; 2655 const char *initrd_filename = machine->initrd_filename; 2656 PCIHostState *phb; 2657 int i; 2658 MemoryRegion *sysmem = get_system_memory(); 2659 MemoryRegion *ram = g_new(MemoryRegion, 1); 2660 hwaddr node0_size = spapr_node0_size(machine); 2661 long load_limit, fw_size; 2662 char *filename; 2663 Error *resize_hpt_err = NULL; 2664 2665 msi_nonbroken = true; 2666 2667 QLIST_INIT(&spapr->phbs); 2668 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2669 2670 /* Determine capabilities to run with */ 2671 spapr_caps_init(spapr); 2672 2673 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2674 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2675 /* 2676 * If the user explicitly requested a mode we should either 2677 * supply it, or fail completely (which we do below). But if 2678 * it's not set explicitly, we reset our mode to something 2679 * that works 2680 */ 2681 if (resize_hpt_err) { 2682 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2683 error_free(resize_hpt_err); 2684 resize_hpt_err = NULL; 2685 } else { 2686 spapr->resize_hpt = smc->resize_hpt_default; 2687 } 2688 } 2689 2690 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2691 2692 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2693 /* 2694 * User requested HPT resize, but this host can't supply it. Bail out 2695 */ 2696 error_report_err(resize_hpt_err); 2697 exit(1); 2698 } 2699 2700 spapr->rma_size = node0_size; 2701 2702 /* With KVM, we don't actually know whether KVM supports an 2703 * unbounded RMA (PR KVM) or is limited by the hash table size 2704 * (HV KVM using VRMA), so we always assume the latter 2705 * 2706 * In that case, we also limit the initial allocations for RTAS 2707 * etc... to 256M since we have no way to know what the VRMA size 2708 * is going to be as it depends on the size of the hash table 2709 * which isn't determined yet. 2710 */ 2711 if (kvm_enabled()) { 2712 spapr->vrma_adjust = 1; 2713 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2714 } 2715 2716 /* Actually we don't support unbounded RMA anymore since we added 2717 * proper emulation of HV mode. The max we can get is 16G which 2718 * also happens to be what we configure for PAPR mode so make sure 2719 * we don't do anything bigger than that 2720 */ 2721 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2722 2723 if (spapr->rma_size > node0_size) { 2724 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2725 spapr->rma_size); 2726 exit(1); 2727 } 2728 2729 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2730 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2731 2732 /* 2733 * VSMT must be set in order to be able to compute VCPU ids, ie to 2734 * call spapr_max_server_number() or spapr_vcpu_id(). 2735 */ 2736 spapr_set_vsmt_mode(spapr, &error_fatal); 2737 2738 /* Set up Interrupt Controller before we create the VCPUs */ 2739 spapr_irq_init(spapr, &error_fatal); 2740 2741 /* Set up containers for ibm,client-architecture-support negotiated options 2742 */ 2743 spapr->ov5 = spapr_ovec_new(); 2744 spapr->ov5_cas = spapr_ovec_new(); 2745 2746 if (smc->dr_lmb_enabled) { 2747 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2748 spapr_validate_node_memory(machine, &error_fatal); 2749 } 2750 2751 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2752 2753 /* advertise support for dedicated HP event source to guests */ 2754 if (spapr->use_hotplug_event_source) { 2755 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2756 } 2757 2758 /* advertise support for HPT resizing */ 2759 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2760 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2761 } 2762 2763 /* advertise support for ibm,dyamic-memory-v2 */ 2764 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2765 2766 /* advertise XIVE on POWER9 machines */ 2767 if (spapr->irq->xive) { 2768 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2769 } 2770 2771 /* init CPUs */ 2772 spapr_init_cpus(spapr); 2773 2774 /* 2775 * check we don't have a memory-less/cpu-less NUMA node 2776 * Firmware relies on the existing memory/cpu topology to provide the 2777 * NUMA topology to the kernel. 2778 * And the linux kernel needs to know the NUMA topology at start 2779 * to be able to hotplug CPUs later. 2780 */ 2781 if (machine->numa_state->num_nodes) { 2782 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2783 /* check for memory-less node */ 2784 if (machine->numa_state->nodes[i].node_mem == 0) { 2785 CPUState *cs; 2786 int found = 0; 2787 /* check for cpu-less node */ 2788 CPU_FOREACH(cs) { 2789 PowerPCCPU *cpu = POWERPC_CPU(cs); 2790 if (cpu->node_id == i) { 2791 found = 1; 2792 break; 2793 } 2794 } 2795 /* memory-less and cpu-less node */ 2796 if (!found) { 2797 error_report( 2798 "Memory-less/cpu-less nodes are not supported (node %d)", 2799 i); 2800 exit(1); 2801 } 2802 } 2803 } 2804 2805 } 2806 2807 /* 2808 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2809 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2810 * called from vPHB reset handler so we initialize the counter here. 2811 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2812 * must be equally distant from any other node. 2813 * The final value of spapr->gpu_numa_id is going to be written to 2814 * max-associativity-domains in spapr_build_fdt(). 2815 */ 2816 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2817 2818 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2819 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2820 spapr->max_compat_pvr)) { 2821 /* KVM and TCG always allow GTSE with radix... */ 2822 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2823 } 2824 /* ... but not with hash (currently). */ 2825 2826 if (kvm_enabled()) { 2827 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2828 kvmppc_enable_logical_ci_hcalls(); 2829 kvmppc_enable_set_mode_hcall(); 2830 2831 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2832 kvmppc_enable_clear_ref_mod_hcalls(); 2833 2834 /* Enable H_PAGE_INIT */ 2835 kvmppc_enable_h_page_init(); 2836 } 2837 2838 /* allocate RAM */ 2839 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2840 machine->ram_size); 2841 memory_region_add_subregion(sysmem, 0, ram); 2842 2843 /* always allocate the device memory information */ 2844 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2845 2846 /* initialize hotplug memory address space */ 2847 if (machine->ram_size < machine->maxram_size) { 2848 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2849 /* 2850 * Limit the number of hotpluggable memory slots to half the number 2851 * slots that KVM supports, leaving the other half for PCI and other 2852 * devices. However ensure that number of slots doesn't drop below 32. 2853 */ 2854 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2855 SPAPR_MAX_RAM_SLOTS; 2856 2857 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2858 max_memslots = SPAPR_MAX_RAM_SLOTS; 2859 } 2860 if (machine->ram_slots > max_memslots) { 2861 error_report("Specified number of memory slots %" 2862 PRIu64" exceeds max supported %d", 2863 machine->ram_slots, max_memslots); 2864 exit(1); 2865 } 2866 2867 machine->device_memory->base = ROUND_UP(machine->ram_size, 2868 SPAPR_DEVICE_MEM_ALIGN); 2869 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2870 "device-memory", device_mem_size); 2871 memory_region_add_subregion(sysmem, machine->device_memory->base, 2872 &machine->device_memory->mr); 2873 } 2874 2875 if (smc->dr_lmb_enabled) { 2876 spapr_create_lmb_dr_connectors(spapr); 2877 } 2878 2879 /* Set up RTAS event infrastructure */ 2880 spapr_events_init(spapr); 2881 2882 /* Set up the RTC RTAS interfaces */ 2883 spapr_rtc_create(spapr); 2884 2885 /* Set up VIO bus */ 2886 spapr->vio_bus = spapr_vio_bus_init(); 2887 2888 for (i = 0; i < serial_max_hds(); i++) { 2889 if (serial_hd(i)) { 2890 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2891 } 2892 } 2893 2894 /* We always have at least the nvram device on VIO */ 2895 spapr_create_nvram(spapr); 2896 2897 /* 2898 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2899 * connectors (described in root DT node's "ibm,drc-types" property) 2900 * are pre-initialized here. additional child connectors (such as 2901 * connectors for a PHBs PCI slots) are added as needed during their 2902 * parent's realization. 2903 */ 2904 if (smc->dr_phb_enabled) { 2905 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2906 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2907 } 2908 } 2909 2910 /* Set up PCI */ 2911 spapr_pci_rtas_init(); 2912 2913 phb = spapr_create_default_phb(); 2914 2915 for (i = 0; i < nb_nics; i++) { 2916 NICInfo *nd = &nd_table[i]; 2917 2918 if (!nd->model) { 2919 nd->model = g_strdup("spapr-vlan"); 2920 } 2921 2922 if (g_str_equal(nd->model, "spapr-vlan") || 2923 g_str_equal(nd->model, "ibmveth")) { 2924 spapr_vlan_create(spapr->vio_bus, nd); 2925 } else { 2926 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2927 } 2928 } 2929 2930 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2931 spapr_vscsi_create(spapr->vio_bus); 2932 } 2933 2934 /* Graphics */ 2935 if (spapr_vga_init(phb->bus, &error_fatal)) { 2936 spapr->has_graphics = true; 2937 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2938 } 2939 2940 if (machine->usb) { 2941 if (smc->use_ohci_by_default) { 2942 pci_create_simple(phb->bus, -1, "pci-ohci"); 2943 } else { 2944 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2945 } 2946 2947 if (spapr->has_graphics) { 2948 USBBus *usb_bus = usb_bus_find(-1); 2949 2950 usb_create_simple(usb_bus, "usb-kbd"); 2951 usb_create_simple(usb_bus, "usb-mouse"); 2952 } 2953 } 2954 2955 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2956 error_report( 2957 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2958 MIN_RMA_SLOF); 2959 exit(1); 2960 } 2961 2962 if (kernel_filename) { 2963 uint64_t lowaddr = 0; 2964 2965 spapr->kernel_size = load_elf(kernel_filename, NULL, 2966 translate_kernel_address, NULL, 2967 NULL, &lowaddr, NULL, 1, 2968 PPC_ELF_MACHINE, 0, 0); 2969 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2970 spapr->kernel_size = load_elf(kernel_filename, NULL, 2971 translate_kernel_address, NULL, NULL, 2972 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2973 0, 0); 2974 spapr->kernel_le = spapr->kernel_size > 0; 2975 } 2976 if (spapr->kernel_size < 0) { 2977 error_report("error loading %s: %s", kernel_filename, 2978 load_elf_strerror(spapr->kernel_size)); 2979 exit(1); 2980 } 2981 2982 /* load initrd */ 2983 if (initrd_filename) { 2984 /* Try to locate the initrd in the gap between the kernel 2985 * and the firmware. Add a bit of space just in case 2986 */ 2987 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2988 + 0x1ffff) & ~0xffff; 2989 spapr->initrd_size = load_image_targphys(initrd_filename, 2990 spapr->initrd_base, 2991 load_limit 2992 - spapr->initrd_base); 2993 if (spapr->initrd_size < 0) { 2994 error_report("could not load initial ram disk '%s'", 2995 initrd_filename); 2996 exit(1); 2997 } 2998 } 2999 } 3000 3001 if (bios_name == NULL) { 3002 bios_name = FW_FILE_NAME; 3003 } 3004 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3005 if (!filename) { 3006 error_report("Could not find LPAR firmware '%s'", bios_name); 3007 exit(1); 3008 } 3009 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3010 if (fw_size <= 0) { 3011 error_report("Could not load LPAR firmware '%s'", filename); 3012 exit(1); 3013 } 3014 g_free(filename); 3015 3016 /* FIXME: Should register things through the MachineState's qdev 3017 * interface, this is a legacy from the sPAPREnvironment structure 3018 * which predated MachineState but had a similar function */ 3019 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3020 register_savevm_live("spapr/htab", -1, 1, 3021 &savevm_htab_handlers, spapr); 3022 3023 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3024 &error_fatal); 3025 3026 qemu_register_boot_set(spapr_boot_set, spapr); 3027 3028 /* 3029 * Nothing needs to be done to resume a suspended guest because 3030 * suspending does not change the machine state, so no need for 3031 * a ->wakeup method. 3032 */ 3033 qemu_register_wakeup_support(); 3034 3035 if (kvm_enabled()) { 3036 /* to stop and start vmclock */ 3037 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3038 &spapr->tb); 3039 3040 kvmppc_spapr_enable_inkernel_multitce(); 3041 } 3042 } 3043 3044 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3045 { 3046 if (!vm_type) { 3047 return 0; 3048 } 3049 3050 if (!strcmp(vm_type, "HV")) { 3051 return 1; 3052 } 3053 3054 if (!strcmp(vm_type, "PR")) { 3055 return 2; 3056 } 3057 3058 error_report("Unknown kvm-type specified '%s'", vm_type); 3059 exit(1); 3060 } 3061 3062 /* 3063 * Implementation of an interface to adjust firmware path 3064 * for the bootindex property handling. 3065 */ 3066 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3067 DeviceState *dev) 3068 { 3069 #define CAST(type, obj, name) \ 3070 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3071 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3072 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3073 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3074 3075 if (d) { 3076 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3077 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3078 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3079 3080 if (spapr) { 3081 /* 3082 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3083 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3084 * 0x8000 | (target << 8) | (bus << 5) | lun 3085 * (see the "Logical unit addressing format" table in SAM5) 3086 */ 3087 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3088 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3089 (uint64_t)id << 48); 3090 } else if (virtio) { 3091 /* 3092 * We use SRP luns of the form 01000000 | (target << 8) | lun 3093 * in the top 32 bits of the 64-bit LUN 3094 * Note: the quote above is from SLOF and it is wrong, 3095 * the actual binding is: 3096 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3097 */ 3098 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3099 if (d->lun >= 256) { 3100 /* Use the LUN "flat space addressing method" */ 3101 id |= 0x4000; 3102 } 3103 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3104 (uint64_t)id << 32); 3105 } else if (usb) { 3106 /* 3107 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3108 * in the top 32 bits of the 64-bit LUN 3109 */ 3110 unsigned usb_port = atoi(usb->port->path); 3111 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3112 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3113 (uint64_t)id << 32); 3114 } 3115 } 3116 3117 /* 3118 * SLOF probes the USB devices, and if it recognizes that the device is a 3119 * storage device, it changes its name to "storage" instead of "usb-host", 3120 * and additionally adds a child node for the SCSI LUN, so the correct 3121 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3122 */ 3123 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3124 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3125 if (usb_host_dev_is_scsi_storage(usbdev)) { 3126 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3127 } 3128 } 3129 3130 if (phb) { 3131 /* Replace "pci" with "pci@800000020000000" */ 3132 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3133 } 3134 3135 if (vsc) { 3136 /* Same logic as virtio above */ 3137 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3138 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3139 } 3140 3141 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3142 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3143 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3144 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3145 } 3146 3147 return NULL; 3148 } 3149 3150 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3151 { 3152 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3153 3154 return g_strdup(spapr->kvm_type); 3155 } 3156 3157 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3158 { 3159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3160 3161 g_free(spapr->kvm_type); 3162 spapr->kvm_type = g_strdup(value); 3163 } 3164 3165 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3166 { 3167 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3168 3169 return spapr->use_hotplug_event_source; 3170 } 3171 3172 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3173 Error **errp) 3174 { 3175 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 spapr->use_hotplug_event_source = value; 3178 } 3179 3180 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3181 { 3182 return true; 3183 } 3184 3185 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3186 { 3187 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3188 3189 switch (spapr->resize_hpt) { 3190 case SPAPR_RESIZE_HPT_DEFAULT: 3191 return g_strdup("default"); 3192 case SPAPR_RESIZE_HPT_DISABLED: 3193 return g_strdup("disabled"); 3194 case SPAPR_RESIZE_HPT_ENABLED: 3195 return g_strdup("enabled"); 3196 case SPAPR_RESIZE_HPT_REQUIRED: 3197 return g_strdup("required"); 3198 } 3199 g_assert_not_reached(); 3200 } 3201 3202 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3203 { 3204 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3205 3206 if (strcmp(value, "default") == 0) { 3207 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3208 } else if (strcmp(value, "disabled") == 0) { 3209 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3210 } else if (strcmp(value, "enabled") == 0) { 3211 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3212 } else if (strcmp(value, "required") == 0) { 3213 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3214 } else { 3215 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3216 } 3217 } 3218 3219 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3220 void *opaque, Error **errp) 3221 { 3222 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3223 } 3224 3225 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3226 void *opaque, Error **errp) 3227 { 3228 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3229 } 3230 3231 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3232 { 3233 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3234 3235 if (spapr->irq == &spapr_irq_xics_legacy) { 3236 return g_strdup("legacy"); 3237 } else if (spapr->irq == &spapr_irq_xics) { 3238 return g_strdup("xics"); 3239 } else if (spapr->irq == &spapr_irq_xive) { 3240 return g_strdup("xive"); 3241 } else if (spapr->irq == &spapr_irq_dual) { 3242 return g_strdup("dual"); 3243 } 3244 g_assert_not_reached(); 3245 } 3246 3247 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3248 { 3249 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3250 3251 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3252 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3253 return; 3254 } 3255 3256 /* The legacy IRQ backend can not be set */ 3257 if (strcmp(value, "xics") == 0) { 3258 spapr->irq = &spapr_irq_xics; 3259 } else if (strcmp(value, "xive") == 0) { 3260 spapr->irq = &spapr_irq_xive; 3261 } else if (strcmp(value, "dual") == 0) { 3262 spapr->irq = &spapr_irq_dual; 3263 } else { 3264 error_setg(errp, "Bad value for \"ic-mode\" property"); 3265 } 3266 } 3267 3268 static char *spapr_get_host_model(Object *obj, Error **errp) 3269 { 3270 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3271 3272 return g_strdup(spapr->host_model); 3273 } 3274 3275 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3276 { 3277 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3278 3279 g_free(spapr->host_model); 3280 spapr->host_model = g_strdup(value); 3281 } 3282 3283 static char *spapr_get_host_serial(Object *obj, Error **errp) 3284 { 3285 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3286 3287 return g_strdup(spapr->host_serial); 3288 } 3289 3290 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3291 { 3292 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3293 3294 g_free(spapr->host_serial); 3295 spapr->host_serial = g_strdup(value); 3296 } 3297 3298 static void spapr_instance_init(Object *obj) 3299 { 3300 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3301 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3302 3303 spapr->htab_fd = -1; 3304 spapr->use_hotplug_event_source = true; 3305 object_property_add_str(obj, "kvm-type", 3306 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3307 object_property_set_description(obj, "kvm-type", 3308 "Specifies the KVM virtualization mode (HV, PR)", 3309 NULL); 3310 object_property_add_bool(obj, "modern-hotplug-events", 3311 spapr_get_modern_hotplug_events, 3312 spapr_set_modern_hotplug_events, 3313 NULL); 3314 object_property_set_description(obj, "modern-hotplug-events", 3315 "Use dedicated hotplug event mechanism in" 3316 " place of standard EPOW events when possible" 3317 " (required for memory hot-unplug support)", 3318 NULL); 3319 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3320 "Maximum permitted CPU compatibility mode", 3321 &error_fatal); 3322 3323 object_property_add_str(obj, "resize-hpt", 3324 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3325 object_property_set_description(obj, "resize-hpt", 3326 "Resizing of the Hash Page Table (enabled, disabled, required)", 3327 NULL); 3328 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3329 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3330 object_property_set_description(obj, "vsmt", 3331 "Virtual SMT: KVM behaves as if this were" 3332 " the host's SMT mode", &error_abort); 3333 object_property_add_bool(obj, "vfio-no-msix-emulation", 3334 spapr_get_msix_emulation, NULL, NULL); 3335 3336 /* The machine class defines the default interrupt controller mode */ 3337 spapr->irq = smc->irq; 3338 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3339 spapr_set_ic_mode, NULL); 3340 object_property_set_description(obj, "ic-mode", 3341 "Specifies the interrupt controller mode (xics, xive, dual)", 3342 NULL); 3343 3344 object_property_add_str(obj, "host-model", 3345 spapr_get_host_model, spapr_set_host_model, 3346 &error_abort); 3347 object_property_set_description(obj, "host-model", 3348 "Host model to advertise in guest device tree", &error_abort); 3349 object_property_add_str(obj, "host-serial", 3350 spapr_get_host_serial, spapr_set_host_serial, 3351 &error_abort); 3352 object_property_set_description(obj, "host-serial", 3353 "Host serial number to advertise in guest device tree", &error_abort); 3354 } 3355 3356 static void spapr_machine_finalizefn(Object *obj) 3357 { 3358 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3359 3360 g_free(spapr->kvm_type); 3361 } 3362 3363 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3364 { 3365 cpu_synchronize_state(cs); 3366 ppc_cpu_do_system_reset(cs); 3367 } 3368 3369 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3370 { 3371 CPUState *cs; 3372 3373 CPU_FOREACH(cs) { 3374 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3375 } 3376 } 3377 3378 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3379 void *fdt, int *fdt_start_offset, Error **errp) 3380 { 3381 uint64_t addr; 3382 uint32_t node; 3383 3384 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3385 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3386 &error_abort); 3387 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3388 SPAPR_MEMORY_BLOCK_SIZE); 3389 return 0; 3390 } 3391 3392 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3393 bool dedicated_hp_event_source, Error **errp) 3394 { 3395 SpaprDrc *drc; 3396 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3397 int i; 3398 uint64_t addr = addr_start; 3399 bool hotplugged = spapr_drc_hotplugged(dev); 3400 Error *local_err = NULL; 3401 3402 for (i = 0; i < nr_lmbs; i++) { 3403 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3404 addr / SPAPR_MEMORY_BLOCK_SIZE); 3405 g_assert(drc); 3406 3407 spapr_drc_attach(drc, dev, &local_err); 3408 if (local_err) { 3409 while (addr > addr_start) { 3410 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3411 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3412 addr / SPAPR_MEMORY_BLOCK_SIZE); 3413 spapr_drc_detach(drc); 3414 } 3415 error_propagate(errp, local_err); 3416 return; 3417 } 3418 if (!hotplugged) { 3419 spapr_drc_reset(drc); 3420 } 3421 addr += SPAPR_MEMORY_BLOCK_SIZE; 3422 } 3423 /* send hotplug notification to the 3424 * guest only in case of hotplugged memory 3425 */ 3426 if (hotplugged) { 3427 if (dedicated_hp_event_source) { 3428 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3429 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3430 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3431 nr_lmbs, 3432 spapr_drc_index(drc)); 3433 } else { 3434 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3435 nr_lmbs); 3436 } 3437 } 3438 } 3439 3440 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3441 Error **errp) 3442 { 3443 Error *local_err = NULL; 3444 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3445 PCDIMMDevice *dimm = PC_DIMM(dev); 3446 uint64_t size, addr; 3447 3448 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3449 3450 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3451 if (local_err) { 3452 goto out; 3453 } 3454 3455 addr = object_property_get_uint(OBJECT(dimm), 3456 PC_DIMM_ADDR_PROP, &local_err); 3457 if (local_err) { 3458 goto out_unplug; 3459 } 3460 3461 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3462 &local_err); 3463 if (local_err) { 3464 goto out_unplug; 3465 } 3466 3467 return; 3468 3469 out_unplug: 3470 pc_dimm_unplug(dimm, MACHINE(ms)); 3471 out: 3472 error_propagate(errp, local_err); 3473 } 3474 3475 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3476 Error **errp) 3477 { 3478 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3479 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3480 PCDIMMDevice *dimm = PC_DIMM(dev); 3481 Error *local_err = NULL; 3482 uint64_t size; 3483 Object *memdev; 3484 hwaddr pagesize; 3485 3486 if (!smc->dr_lmb_enabled) { 3487 error_setg(errp, "Memory hotplug not supported for this machine"); 3488 return; 3489 } 3490 3491 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3492 if (local_err) { 3493 error_propagate(errp, local_err); 3494 return; 3495 } 3496 3497 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3498 error_setg(errp, "Hotplugged memory size must be a multiple of " 3499 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3500 return; 3501 } 3502 3503 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3504 &error_abort); 3505 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3506 spapr_check_pagesize(spapr, pagesize, &local_err); 3507 if (local_err) { 3508 error_propagate(errp, local_err); 3509 return; 3510 } 3511 3512 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3513 } 3514 3515 struct SpaprDimmState { 3516 PCDIMMDevice *dimm; 3517 uint32_t nr_lmbs; 3518 QTAILQ_ENTRY(SpaprDimmState) next; 3519 }; 3520 3521 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3522 PCDIMMDevice *dimm) 3523 { 3524 SpaprDimmState *dimm_state = NULL; 3525 3526 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3527 if (dimm_state->dimm == dimm) { 3528 break; 3529 } 3530 } 3531 return dimm_state; 3532 } 3533 3534 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3535 uint32_t nr_lmbs, 3536 PCDIMMDevice *dimm) 3537 { 3538 SpaprDimmState *ds = NULL; 3539 3540 /* 3541 * If this request is for a DIMM whose removal had failed earlier 3542 * (due to guest's refusal to remove the LMBs), we would have this 3543 * dimm already in the pending_dimm_unplugs list. In that 3544 * case don't add again. 3545 */ 3546 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3547 if (!ds) { 3548 ds = g_malloc0(sizeof(SpaprDimmState)); 3549 ds->nr_lmbs = nr_lmbs; 3550 ds->dimm = dimm; 3551 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3552 } 3553 return ds; 3554 } 3555 3556 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3557 SpaprDimmState *dimm_state) 3558 { 3559 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3560 g_free(dimm_state); 3561 } 3562 3563 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3564 PCDIMMDevice *dimm) 3565 { 3566 SpaprDrc *drc; 3567 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3568 &error_abort); 3569 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3570 uint32_t avail_lmbs = 0; 3571 uint64_t addr_start, addr; 3572 int i; 3573 3574 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3575 &error_abort); 3576 3577 addr = addr_start; 3578 for (i = 0; i < nr_lmbs; i++) { 3579 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3580 addr / SPAPR_MEMORY_BLOCK_SIZE); 3581 g_assert(drc); 3582 if (drc->dev) { 3583 avail_lmbs++; 3584 } 3585 addr += SPAPR_MEMORY_BLOCK_SIZE; 3586 } 3587 3588 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3589 } 3590 3591 /* Callback to be called during DRC release. */ 3592 void spapr_lmb_release(DeviceState *dev) 3593 { 3594 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3595 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3596 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3597 3598 /* This information will get lost if a migration occurs 3599 * during the unplug process. In this case recover it. */ 3600 if (ds == NULL) { 3601 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3602 g_assert(ds); 3603 /* The DRC being examined by the caller at least must be counted */ 3604 g_assert(ds->nr_lmbs); 3605 } 3606 3607 if (--ds->nr_lmbs) { 3608 return; 3609 } 3610 3611 /* 3612 * Now that all the LMBs have been removed by the guest, call the 3613 * unplug handler chain. This can never fail. 3614 */ 3615 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3616 object_unparent(OBJECT(dev)); 3617 } 3618 3619 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3620 { 3621 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3622 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3623 3624 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3625 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3626 spapr_pending_dimm_unplugs_remove(spapr, ds); 3627 } 3628 3629 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3630 DeviceState *dev, Error **errp) 3631 { 3632 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3633 Error *local_err = NULL; 3634 PCDIMMDevice *dimm = PC_DIMM(dev); 3635 uint32_t nr_lmbs; 3636 uint64_t size, addr_start, addr; 3637 int i; 3638 SpaprDrc *drc; 3639 3640 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3641 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3642 3643 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3644 &local_err); 3645 if (local_err) { 3646 goto out; 3647 } 3648 3649 /* 3650 * An existing pending dimm state for this DIMM means that there is an 3651 * unplug operation in progress, waiting for the spapr_lmb_release 3652 * callback to complete the job (BQL can't cover that far). In this case, 3653 * bail out to avoid detaching DRCs that were already released. 3654 */ 3655 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3656 error_setg(&local_err, 3657 "Memory unplug already in progress for device %s", 3658 dev->id); 3659 goto out; 3660 } 3661 3662 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3663 3664 addr = addr_start; 3665 for (i = 0; i < nr_lmbs; i++) { 3666 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3667 addr / SPAPR_MEMORY_BLOCK_SIZE); 3668 g_assert(drc); 3669 3670 spapr_drc_detach(drc); 3671 addr += SPAPR_MEMORY_BLOCK_SIZE; 3672 } 3673 3674 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3675 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3676 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3677 nr_lmbs, spapr_drc_index(drc)); 3678 out: 3679 error_propagate(errp, local_err); 3680 } 3681 3682 /* Callback to be called during DRC release. */ 3683 void spapr_core_release(DeviceState *dev) 3684 { 3685 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3686 3687 /* Call the unplug handler chain. This can never fail. */ 3688 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3689 object_unparent(OBJECT(dev)); 3690 } 3691 3692 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3693 { 3694 MachineState *ms = MACHINE(hotplug_dev); 3695 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3696 CPUCore *cc = CPU_CORE(dev); 3697 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3698 3699 if (smc->pre_2_10_has_unused_icps) { 3700 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3701 int i; 3702 3703 for (i = 0; i < cc->nr_threads; i++) { 3704 CPUState *cs = CPU(sc->threads[i]); 3705 3706 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3707 } 3708 } 3709 3710 assert(core_slot); 3711 core_slot->cpu = NULL; 3712 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3713 } 3714 3715 static 3716 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3717 Error **errp) 3718 { 3719 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3720 int index; 3721 SpaprDrc *drc; 3722 CPUCore *cc = CPU_CORE(dev); 3723 3724 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3725 error_setg(errp, "Unable to find CPU core with core-id: %d", 3726 cc->core_id); 3727 return; 3728 } 3729 if (index == 0) { 3730 error_setg(errp, "Boot CPU core may not be unplugged"); 3731 return; 3732 } 3733 3734 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3735 spapr_vcpu_id(spapr, cc->core_id)); 3736 g_assert(drc); 3737 3738 if (!spapr_drc_unplug_requested(drc)) { 3739 spapr_drc_detach(drc); 3740 spapr_hotplug_req_remove_by_index(drc); 3741 } 3742 } 3743 3744 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3745 void *fdt, int *fdt_start_offset, Error **errp) 3746 { 3747 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3748 CPUState *cs = CPU(core->threads[0]); 3749 PowerPCCPU *cpu = POWERPC_CPU(cs); 3750 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3751 int id = spapr_get_vcpu_id(cpu); 3752 char *nodename; 3753 int offset; 3754 3755 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3756 offset = fdt_add_subnode(fdt, 0, nodename); 3757 g_free(nodename); 3758 3759 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3760 3761 *fdt_start_offset = offset; 3762 return 0; 3763 } 3764 3765 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3766 Error **errp) 3767 { 3768 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3769 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3770 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3771 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3772 CPUCore *cc = CPU_CORE(dev); 3773 CPUState *cs; 3774 SpaprDrc *drc; 3775 Error *local_err = NULL; 3776 CPUArchId *core_slot; 3777 int index; 3778 bool hotplugged = spapr_drc_hotplugged(dev); 3779 int i; 3780 3781 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3782 if (!core_slot) { 3783 error_setg(errp, "Unable to find CPU core with core-id: %d", 3784 cc->core_id); 3785 return; 3786 } 3787 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3788 spapr_vcpu_id(spapr, cc->core_id)); 3789 3790 g_assert(drc || !mc->has_hotpluggable_cpus); 3791 3792 if (drc) { 3793 spapr_drc_attach(drc, dev, &local_err); 3794 if (local_err) { 3795 error_propagate(errp, local_err); 3796 return; 3797 } 3798 3799 if (hotplugged) { 3800 /* 3801 * Send hotplug notification interrupt to the guest only 3802 * in case of hotplugged CPUs. 3803 */ 3804 spapr_hotplug_req_add_by_index(drc); 3805 } else { 3806 spapr_drc_reset(drc); 3807 } 3808 } 3809 3810 core_slot->cpu = OBJECT(dev); 3811 3812 if (smc->pre_2_10_has_unused_icps) { 3813 for (i = 0; i < cc->nr_threads; i++) { 3814 cs = CPU(core->threads[i]); 3815 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3816 } 3817 } 3818 3819 /* 3820 * Set compatibility mode to match the boot CPU, which was either set 3821 * by the machine reset code or by CAS. 3822 */ 3823 if (hotplugged) { 3824 for (i = 0; i < cc->nr_threads; i++) { 3825 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3826 &local_err); 3827 if (local_err) { 3828 error_propagate(errp, local_err); 3829 return; 3830 } 3831 } 3832 } 3833 } 3834 3835 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3836 Error **errp) 3837 { 3838 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3839 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3840 Error *local_err = NULL; 3841 CPUCore *cc = CPU_CORE(dev); 3842 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3843 const char *type = object_get_typename(OBJECT(dev)); 3844 CPUArchId *core_slot; 3845 int index; 3846 unsigned int smp_threads = machine->smp.threads; 3847 3848 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3849 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3850 goto out; 3851 } 3852 3853 if (strcmp(base_core_type, type)) { 3854 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3855 goto out; 3856 } 3857 3858 if (cc->core_id % smp_threads) { 3859 error_setg(&local_err, "invalid core id %d", cc->core_id); 3860 goto out; 3861 } 3862 3863 /* 3864 * In general we should have homogeneous threads-per-core, but old 3865 * (pre hotplug support) machine types allow the last core to have 3866 * reduced threads as a compatibility hack for when we allowed 3867 * total vcpus not a multiple of threads-per-core. 3868 */ 3869 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3870 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3871 cc->nr_threads, smp_threads); 3872 goto out; 3873 } 3874 3875 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3876 if (!core_slot) { 3877 error_setg(&local_err, "core id %d out of range", cc->core_id); 3878 goto out; 3879 } 3880 3881 if (core_slot->cpu) { 3882 error_setg(&local_err, "core %d already populated", cc->core_id); 3883 goto out; 3884 } 3885 3886 numa_cpu_pre_plug(core_slot, dev, &local_err); 3887 3888 out: 3889 error_propagate(errp, local_err); 3890 } 3891 3892 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3893 void *fdt, int *fdt_start_offset, Error **errp) 3894 { 3895 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3896 int intc_phandle; 3897 3898 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3899 if (intc_phandle <= 0) { 3900 return -1; 3901 } 3902 3903 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3904 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3905 return -1; 3906 } 3907 3908 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3909 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3910 3911 return 0; 3912 } 3913 3914 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3915 Error **errp) 3916 { 3917 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3918 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3919 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3920 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3921 3922 if (dev->hotplugged && !smc->dr_phb_enabled) { 3923 error_setg(errp, "PHB hotplug not supported for this machine"); 3924 return; 3925 } 3926 3927 if (sphb->index == (uint32_t)-1) { 3928 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3929 return; 3930 } 3931 3932 /* 3933 * This will check that sphb->index doesn't exceed the maximum number of 3934 * PHBs for the current machine type. 3935 */ 3936 smc->phb_placement(spapr, sphb->index, 3937 &sphb->buid, &sphb->io_win_addr, 3938 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3939 windows_supported, sphb->dma_liobn, 3940 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3941 errp); 3942 } 3943 3944 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3945 Error **errp) 3946 { 3947 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3948 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3949 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3950 SpaprDrc *drc; 3951 bool hotplugged = spapr_drc_hotplugged(dev); 3952 Error *local_err = NULL; 3953 3954 if (!smc->dr_phb_enabled) { 3955 return; 3956 } 3957 3958 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3959 /* hotplug hooks should check it's enabled before getting this far */ 3960 assert(drc); 3961 3962 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3963 if (local_err) { 3964 error_propagate(errp, local_err); 3965 return; 3966 } 3967 3968 if (hotplugged) { 3969 spapr_hotplug_req_add_by_index(drc); 3970 } else { 3971 spapr_drc_reset(drc); 3972 } 3973 } 3974 3975 void spapr_phb_release(DeviceState *dev) 3976 { 3977 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3978 3979 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3980 object_unparent(OBJECT(dev)); 3981 } 3982 3983 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3984 { 3985 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3986 } 3987 3988 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3989 DeviceState *dev, Error **errp) 3990 { 3991 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3992 SpaprDrc *drc; 3993 3994 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3995 assert(drc); 3996 3997 if (!spapr_drc_unplug_requested(drc)) { 3998 spapr_drc_detach(drc); 3999 spapr_hotplug_req_remove_by_index(drc); 4000 } 4001 } 4002 4003 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4004 Error **errp) 4005 { 4006 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4007 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4008 4009 if (spapr->tpm_proxy != NULL) { 4010 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4011 return; 4012 } 4013 4014 spapr->tpm_proxy = tpm_proxy; 4015 } 4016 4017 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4018 { 4019 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4020 4021 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4022 object_unparent(OBJECT(dev)); 4023 spapr->tpm_proxy = NULL; 4024 } 4025 4026 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4027 DeviceState *dev, Error **errp) 4028 { 4029 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4030 spapr_memory_plug(hotplug_dev, dev, errp); 4031 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4032 spapr_core_plug(hotplug_dev, dev, errp); 4033 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4034 spapr_phb_plug(hotplug_dev, dev, errp); 4035 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4036 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4037 } 4038 } 4039 4040 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4041 DeviceState *dev, Error **errp) 4042 { 4043 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4044 spapr_memory_unplug(hotplug_dev, dev); 4045 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4046 spapr_core_unplug(hotplug_dev, dev); 4047 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4048 spapr_phb_unplug(hotplug_dev, dev); 4049 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4050 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4051 } 4052 } 4053 4054 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4055 DeviceState *dev, Error **errp) 4056 { 4057 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4058 MachineClass *mc = MACHINE_GET_CLASS(sms); 4059 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4060 4061 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4062 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4063 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4064 } else { 4065 /* NOTE: this means there is a window after guest reset, prior to 4066 * CAS negotiation, where unplug requests will fail due to the 4067 * capability not being detected yet. This is a bit different than 4068 * the case with PCI unplug, where the events will be queued and 4069 * eventually handled by the guest after boot 4070 */ 4071 error_setg(errp, "Memory hot unplug not supported for this guest"); 4072 } 4073 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4074 if (!mc->has_hotpluggable_cpus) { 4075 error_setg(errp, "CPU hot unplug not supported on this machine"); 4076 return; 4077 } 4078 spapr_core_unplug_request(hotplug_dev, dev, errp); 4079 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4080 if (!smc->dr_phb_enabled) { 4081 error_setg(errp, "PHB hot unplug not supported on this machine"); 4082 return; 4083 } 4084 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4086 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4087 } 4088 } 4089 4090 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4091 DeviceState *dev, Error **errp) 4092 { 4093 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4094 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4095 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4096 spapr_core_pre_plug(hotplug_dev, dev, errp); 4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4098 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4099 } 4100 } 4101 4102 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4103 DeviceState *dev) 4104 { 4105 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4106 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4107 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4108 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4109 return HOTPLUG_HANDLER(machine); 4110 } 4111 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4112 PCIDevice *pcidev = PCI_DEVICE(dev); 4113 PCIBus *root = pci_device_root_bus(pcidev); 4114 SpaprPhbState *phb = 4115 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4116 TYPE_SPAPR_PCI_HOST_BRIDGE); 4117 4118 if (phb) { 4119 return HOTPLUG_HANDLER(phb); 4120 } 4121 } 4122 return NULL; 4123 } 4124 4125 static CpuInstanceProperties 4126 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4127 { 4128 CPUArchId *core_slot; 4129 MachineClass *mc = MACHINE_GET_CLASS(machine); 4130 4131 /* make sure possible_cpu are intialized */ 4132 mc->possible_cpu_arch_ids(machine); 4133 /* get CPU core slot containing thread that matches cpu_index */ 4134 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4135 assert(core_slot); 4136 return core_slot->props; 4137 } 4138 4139 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4140 { 4141 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4142 } 4143 4144 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4145 { 4146 int i; 4147 unsigned int smp_threads = machine->smp.threads; 4148 unsigned int smp_cpus = machine->smp.cpus; 4149 const char *core_type; 4150 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4151 MachineClass *mc = MACHINE_GET_CLASS(machine); 4152 4153 if (!mc->has_hotpluggable_cpus) { 4154 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4155 } 4156 if (machine->possible_cpus) { 4157 assert(machine->possible_cpus->len == spapr_max_cores); 4158 return machine->possible_cpus; 4159 } 4160 4161 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4162 if (!core_type) { 4163 error_report("Unable to find sPAPR CPU Core definition"); 4164 exit(1); 4165 } 4166 4167 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4168 sizeof(CPUArchId) * spapr_max_cores); 4169 machine->possible_cpus->len = spapr_max_cores; 4170 for (i = 0; i < machine->possible_cpus->len; i++) { 4171 int core_id = i * smp_threads; 4172 4173 machine->possible_cpus->cpus[i].type = core_type; 4174 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4175 machine->possible_cpus->cpus[i].arch_id = core_id; 4176 machine->possible_cpus->cpus[i].props.has_core_id = true; 4177 machine->possible_cpus->cpus[i].props.core_id = core_id; 4178 } 4179 return machine->possible_cpus; 4180 } 4181 4182 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4183 uint64_t *buid, hwaddr *pio, 4184 hwaddr *mmio32, hwaddr *mmio64, 4185 unsigned n_dma, uint32_t *liobns, 4186 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4187 { 4188 /* 4189 * New-style PHB window placement. 4190 * 4191 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4192 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4193 * windows. 4194 * 4195 * Some guest kernels can't work with MMIO windows above 1<<46 4196 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4197 * 4198 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4199 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4200 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4201 * 1TiB 64-bit MMIO windows for each PHB. 4202 */ 4203 const uint64_t base_buid = 0x800000020000000ULL; 4204 int i; 4205 4206 /* Sanity check natural alignments */ 4207 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4208 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4209 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4210 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4211 /* Sanity check bounds */ 4212 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4213 SPAPR_PCI_MEM32_WIN_SIZE); 4214 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4215 SPAPR_PCI_MEM64_WIN_SIZE); 4216 4217 if (index >= SPAPR_MAX_PHBS) { 4218 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4219 SPAPR_MAX_PHBS - 1); 4220 return; 4221 } 4222 4223 *buid = base_buid + index; 4224 for (i = 0; i < n_dma; ++i) { 4225 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4226 } 4227 4228 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4229 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4230 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4231 4232 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4233 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4234 } 4235 4236 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4237 { 4238 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4239 4240 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4241 } 4242 4243 static void spapr_ics_resend(XICSFabric *dev) 4244 { 4245 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4246 4247 ics_resend(spapr->ics); 4248 } 4249 4250 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4251 { 4252 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4253 4254 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4255 } 4256 4257 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4258 Monitor *mon) 4259 { 4260 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4261 4262 spapr_irq_print_info(spapr, mon); 4263 monitor_printf(mon, "irqchip: %s\n", 4264 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4265 } 4266 4267 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4268 uint8_t nvt_blk, uint32_t nvt_idx, 4269 bool cam_ignore, uint8_t priority, 4270 uint32_t logic_serv, XiveTCTXMatch *match) 4271 { 4272 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4273 XivePresenter *xptr = XIVE_PRESENTER(spapr->xive); 4274 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4275 int count; 4276 4277 /* This is a XIVE only operation */ 4278 assert(spapr->active_intc == SPAPR_INTC(spapr->xive)); 4279 4280 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4281 priority, logic_serv, match); 4282 if (count < 0) { 4283 return count; 4284 } 4285 4286 /* 4287 * When we implement the save and restore of the thread interrupt 4288 * contexts in the enter/exit CPU handlers of the machine and the 4289 * escalations in QEMU, we should be able to handle non dispatched 4290 * vCPUs. 4291 * 4292 * Until this is done, the sPAPR machine should find at least one 4293 * matching context always. 4294 */ 4295 if (count == 0) { 4296 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4297 nvt_blk, nvt_idx); 4298 } 4299 4300 return count; 4301 } 4302 4303 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4304 { 4305 return cpu->vcpu_id; 4306 } 4307 4308 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4309 { 4310 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4311 MachineState *ms = MACHINE(spapr); 4312 int vcpu_id; 4313 4314 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4315 4316 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4317 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4318 error_append_hint(errp, "Adjust the number of cpus to %d " 4319 "or try to raise the number of threads per core\n", 4320 vcpu_id * ms->smp.threads / spapr->vsmt); 4321 return; 4322 } 4323 4324 cpu->vcpu_id = vcpu_id; 4325 } 4326 4327 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4328 { 4329 CPUState *cs; 4330 4331 CPU_FOREACH(cs) { 4332 PowerPCCPU *cpu = POWERPC_CPU(cs); 4333 4334 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4335 return cpu; 4336 } 4337 } 4338 4339 return NULL; 4340 } 4341 4342 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4343 { 4344 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4345 4346 /* These are only called by TCG, KVM maintains dispatch state */ 4347 4348 spapr_cpu->prod = false; 4349 if (spapr_cpu->vpa_addr) { 4350 CPUState *cs = CPU(cpu); 4351 uint32_t dispatch; 4352 4353 dispatch = ldl_be_phys(cs->as, 4354 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4355 dispatch++; 4356 if ((dispatch & 1) != 0) { 4357 qemu_log_mask(LOG_GUEST_ERROR, 4358 "VPA: incorrect dispatch counter value for " 4359 "dispatched partition %u, correcting.\n", dispatch); 4360 dispatch++; 4361 } 4362 stl_be_phys(cs->as, 4363 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4364 } 4365 } 4366 4367 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4368 { 4369 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4370 4371 if (spapr_cpu->vpa_addr) { 4372 CPUState *cs = CPU(cpu); 4373 uint32_t dispatch; 4374 4375 dispatch = ldl_be_phys(cs->as, 4376 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4377 dispatch++; 4378 if ((dispatch & 1) != 1) { 4379 qemu_log_mask(LOG_GUEST_ERROR, 4380 "VPA: incorrect dispatch counter value for " 4381 "preempted partition %u, correcting.\n", dispatch); 4382 dispatch++; 4383 } 4384 stl_be_phys(cs->as, 4385 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4386 } 4387 } 4388 4389 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4390 { 4391 MachineClass *mc = MACHINE_CLASS(oc); 4392 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4393 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4394 NMIClass *nc = NMI_CLASS(oc); 4395 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4396 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4397 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4398 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4399 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4400 4401 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4402 mc->ignore_boot_device_suffixes = true; 4403 4404 /* 4405 * We set up the default / latest behaviour here. The class_init 4406 * functions for the specific versioned machine types can override 4407 * these details for backwards compatibility 4408 */ 4409 mc->init = spapr_machine_init; 4410 mc->reset = spapr_machine_reset; 4411 mc->block_default_type = IF_SCSI; 4412 mc->max_cpus = 1024; 4413 mc->no_parallel = 1; 4414 mc->default_boot_order = ""; 4415 mc->default_ram_size = 512 * MiB; 4416 mc->default_display = "std"; 4417 mc->kvm_type = spapr_kvm_type; 4418 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4419 mc->pci_allow_0_address = true; 4420 assert(!mc->get_hotplug_handler); 4421 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4422 hc->pre_plug = spapr_machine_device_pre_plug; 4423 hc->plug = spapr_machine_device_plug; 4424 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4425 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4426 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4427 hc->unplug_request = spapr_machine_device_unplug_request; 4428 hc->unplug = spapr_machine_device_unplug; 4429 4430 smc->dr_lmb_enabled = true; 4431 smc->update_dt_enabled = true; 4432 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4433 mc->has_hotpluggable_cpus = true; 4434 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4435 fwc->get_dev_path = spapr_get_fw_dev_path; 4436 nc->nmi_monitor_handler = spapr_nmi; 4437 smc->phb_placement = spapr_phb_placement; 4438 vhc->hypercall = emulate_spapr_hypercall; 4439 vhc->hpt_mask = spapr_hpt_mask; 4440 vhc->map_hptes = spapr_map_hptes; 4441 vhc->unmap_hptes = spapr_unmap_hptes; 4442 vhc->hpte_set_c = spapr_hpte_set_c; 4443 vhc->hpte_set_r = spapr_hpte_set_r; 4444 vhc->get_pate = spapr_get_pate; 4445 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4446 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4447 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4448 xic->ics_get = spapr_ics_get; 4449 xic->ics_resend = spapr_ics_resend; 4450 xic->icp_get = spapr_icp_get; 4451 ispc->print_info = spapr_pic_print_info; 4452 /* Force NUMA node memory size to be a multiple of 4453 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4454 * in which LMBs are represented and hot-added 4455 */ 4456 mc->numa_mem_align_shift = 28; 4457 mc->numa_mem_supported = true; 4458 mc->auto_enable_numa = true; 4459 4460 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4461 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4462 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4463 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4464 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4465 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4466 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4467 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4468 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4469 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4470 spapr_caps_add_properties(smc, &error_abort); 4471 smc->irq = &spapr_irq_dual; 4472 smc->dr_phb_enabled = true; 4473 smc->linux_pci_probe = true; 4474 smc->smp_threads_vsmt = true; 4475 smc->nr_xirqs = SPAPR_NR_XIRQS; 4476 xfc->match_nvt = spapr_match_nvt; 4477 } 4478 4479 static const TypeInfo spapr_machine_info = { 4480 .name = TYPE_SPAPR_MACHINE, 4481 .parent = TYPE_MACHINE, 4482 .abstract = true, 4483 .instance_size = sizeof(SpaprMachineState), 4484 .instance_init = spapr_instance_init, 4485 .instance_finalize = spapr_machine_finalizefn, 4486 .class_size = sizeof(SpaprMachineClass), 4487 .class_init = spapr_machine_class_init, 4488 .interfaces = (InterfaceInfo[]) { 4489 { TYPE_FW_PATH_PROVIDER }, 4490 { TYPE_NMI }, 4491 { TYPE_HOTPLUG_HANDLER }, 4492 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4493 { TYPE_XICS_FABRIC }, 4494 { TYPE_INTERRUPT_STATS_PROVIDER }, 4495 { TYPE_XIVE_FABRIC }, 4496 { } 4497 }, 4498 }; 4499 4500 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4501 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4502 void *data) \ 4503 { \ 4504 MachineClass *mc = MACHINE_CLASS(oc); \ 4505 spapr_machine_##suffix##_class_options(mc); \ 4506 if (latest) { \ 4507 mc->alias = "pseries"; \ 4508 mc->is_default = 1; \ 4509 } \ 4510 } \ 4511 static const TypeInfo spapr_machine_##suffix##_info = { \ 4512 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4513 .parent = TYPE_SPAPR_MACHINE, \ 4514 .class_init = spapr_machine_##suffix##_class_init, \ 4515 }; \ 4516 static void spapr_machine_register_##suffix(void) \ 4517 { \ 4518 type_register(&spapr_machine_##suffix##_info); \ 4519 } \ 4520 type_init(spapr_machine_register_##suffix) 4521 4522 /* 4523 * pseries-5.0 4524 */ 4525 static void spapr_machine_5_0_class_options(MachineClass *mc) 4526 { 4527 /* Defaults for the latest behaviour inherited from the base class */ 4528 } 4529 4530 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4531 4532 /* 4533 * pseries-4.2 4534 */ 4535 static void spapr_machine_4_2_class_options(MachineClass *mc) 4536 { 4537 spapr_machine_5_0_class_options(mc); 4538 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4539 } 4540 4541 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4542 4543 /* 4544 * pseries-4.1 4545 */ 4546 static void spapr_machine_4_1_class_options(MachineClass *mc) 4547 { 4548 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4549 static GlobalProperty compat[] = { 4550 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4551 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4552 }; 4553 4554 spapr_machine_4_2_class_options(mc); 4555 smc->linux_pci_probe = false; 4556 smc->smp_threads_vsmt = false; 4557 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4558 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4559 } 4560 4561 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4562 4563 /* 4564 * pseries-4.0 4565 */ 4566 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4567 uint64_t *buid, hwaddr *pio, 4568 hwaddr *mmio32, hwaddr *mmio64, 4569 unsigned n_dma, uint32_t *liobns, 4570 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4571 { 4572 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4573 nv2gpa, nv2atsd, errp); 4574 *nv2gpa = 0; 4575 *nv2atsd = 0; 4576 } 4577 4578 static void spapr_machine_4_0_class_options(MachineClass *mc) 4579 { 4580 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4581 4582 spapr_machine_4_1_class_options(mc); 4583 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4584 smc->phb_placement = phb_placement_4_0; 4585 smc->irq = &spapr_irq_xics; 4586 smc->pre_4_1_migration = true; 4587 } 4588 4589 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4590 4591 /* 4592 * pseries-3.1 4593 */ 4594 static void spapr_machine_3_1_class_options(MachineClass *mc) 4595 { 4596 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4597 4598 spapr_machine_4_0_class_options(mc); 4599 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4600 4601 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4602 smc->update_dt_enabled = false; 4603 smc->dr_phb_enabled = false; 4604 smc->broken_host_serial_model = true; 4605 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4606 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4607 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4608 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4609 } 4610 4611 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4612 4613 /* 4614 * pseries-3.0 4615 */ 4616 4617 static void spapr_machine_3_0_class_options(MachineClass *mc) 4618 { 4619 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4620 4621 spapr_machine_3_1_class_options(mc); 4622 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4623 4624 smc->legacy_irq_allocation = true; 4625 smc->nr_xirqs = 0x400; 4626 smc->irq = &spapr_irq_xics_legacy; 4627 } 4628 4629 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4630 4631 /* 4632 * pseries-2.12 4633 */ 4634 static void spapr_machine_2_12_class_options(MachineClass *mc) 4635 { 4636 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4637 static GlobalProperty compat[] = { 4638 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4639 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4640 }; 4641 4642 spapr_machine_3_0_class_options(mc); 4643 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4644 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4645 4646 /* We depend on kvm_enabled() to choose a default value for the 4647 * hpt-max-page-size capability. Of course we can't do it here 4648 * because this is too early and the HW accelerator isn't initialzed 4649 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4650 */ 4651 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4652 } 4653 4654 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4655 4656 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4657 { 4658 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4659 4660 spapr_machine_2_12_class_options(mc); 4661 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4662 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4663 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4664 } 4665 4666 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4667 4668 /* 4669 * pseries-2.11 4670 */ 4671 4672 static void spapr_machine_2_11_class_options(MachineClass *mc) 4673 { 4674 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4675 4676 spapr_machine_2_12_class_options(mc); 4677 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4678 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4679 } 4680 4681 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4682 4683 /* 4684 * pseries-2.10 4685 */ 4686 4687 static void spapr_machine_2_10_class_options(MachineClass *mc) 4688 { 4689 spapr_machine_2_11_class_options(mc); 4690 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4691 } 4692 4693 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4694 4695 /* 4696 * pseries-2.9 4697 */ 4698 4699 static void spapr_machine_2_9_class_options(MachineClass *mc) 4700 { 4701 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4702 static GlobalProperty compat[] = { 4703 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4704 }; 4705 4706 spapr_machine_2_10_class_options(mc); 4707 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4708 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4709 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4710 smc->pre_2_10_has_unused_icps = true; 4711 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4712 } 4713 4714 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4715 4716 /* 4717 * pseries-2.8 4718 */ 4719 4720 static void spapr_machine_2_8_class_options(MachineClass *mc) 4721 { 4722 static GlobalProperty compat[] = { 4723 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4724 }; 4725 4726 spapr_machine_2_9_class_options(mc); 4727 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4728 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4729 mc->numa_mem_align_shift = 23; 4730 } 4731 4732 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4733 4734 /* 4735 * pseries-2.7 4736 */ 4737 4738 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4739 uint64_t *buid, hwaddr *pio, 4740 hwaddr *mmio32, hwaddr *mmio64, 4741 unsigned n_dma, uint32_t *liobns, 4742 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4743 { 4744 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4745 const uint64_t base_buid = 0x800000020000000ULL; 4746 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4747 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4748 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4749 const uint32_t max_index = 255; 4750 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4751 4752 uint64_t ram_top = MACHINE(spapr)->ram_size; 4753 hwaddr phb0_base, phb_base; 4754 int i; 4755 4756 /* Do we have device memory? */ 4757 if (MACHINE(spapr)->maxram_size > ram_top) { 4758 /* Can't just use maxram_size, because there may be an 4759 * alignment gap between normal and device memory regions 4760 */ 4761 ram_top = MACHINE(spapr)->device_memory->base + 4762 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4763 } 4764 4765 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4766 4767 if (index > max_index) { 4768 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4769 max_index); 4770 return; 4771 } 4772 4773 *buid = base_buid + index; 4774 for (i = 0; i < n_dma; ++i) { 4775 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4776 } 4777 4778 phb_base = phb0_base + index * phb_spacing; 4779 *pio = phb_base + pio_offset; 4780 *mmio32 = phb_base + mmio_offset; 4781 /* 4782 * We don't set the 64-bit MMIO window, relying on the PHB's 4783 * fallback behaviour of automatically splitting a large "32-bit" 4784 * window into contiguous 32-bit and 64-bit windows 4785 */ 4786 4787 *nv2gpa = 0; 4788 *nv2atsd = 0; 4789 } 4790 4791 static void spapr_machine_2_7_class_options(MachineClass *mc) 4792 { 4793 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4794 static GlobalProperty compat[] = { 4795 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4796 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4797 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4798 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4799 }; 4800 4801 spapr_machine_2_8_class_options(mc); 4802 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4803 mc->default_machine_opts = "modern-hotplug-events=off"; 4804 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4805 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4806 smc->phb_placement = phb_placement_2_7; 4807 } 4808 4809 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4810 4811 /* 4812 * pseries-2.6 4813 */ 4814 4815 static void spapr_machine_2_6_class_options(MachineClass *mc) 4816 { 4817 static GlobalProperty compat[] = { 4818 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4819 }; 4820 4821 spapr_machine_2_7_class_options(mc); 4822 mc->has_hotpluggable_cpus = false; 4823 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4824 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4825 } 4826 4827 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4828 4829 /* 4830 * pseries-2.5 4831 */ 4832 4833 static void spapr_machine_2_5_class_options(MachineClass *mc) 4834 { 4835 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4836 static GlobalProperty compat[] = { 4837 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4838 }; 4839 4840 spapr_machine_2_6_class_options(mc); 4841 smc->use_ohci_by_default = true; 4842 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4843 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4844 } 4845 4846 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4847 4848 /* 4849 * pseries-2.4 4850 */ 4851 4852 static void spapr_machine_2_4_class_options(MachineClass *mc) 4853 { 4854 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4855 4856 spapr_machine_2_5_class_options(mc); 4857 smc->dr_lmb_enabled = false; 4858 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4859 } 4860 4861 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4862 4863 /* 4864 * pseries-2.3 4865 */ 4866 4867 static void spapr_machine_2_3_class_options(MachineClass *mc) 4868 { 4869 static GlobalProperty compat[] = { 4870 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4871 }; 4872 spapr_machine_2_4_class_options(mc); 4873 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4874 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4875 } 4876 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4877 4878 /* 4879 * pseries-2.2 4880 */ 4881 4882 static void spapr_machine_2_2_class_options(MachineClass *mc) 4883 { 4884 static GlobalProperty compat[] = { 4885 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4886 }; 4887 4888 spapr_machine_2_3_class_options(mc); 4889 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4890 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4891 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4892 } 4893 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4894 4895 /* 4896 * pseries-2.1 4897 */ 4898 4899 static void spapr_machine_2_1_class_options(MachineClass *mc) 4900 { 4901 spapr_machine_2_2_class_options(mc); 4902 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4903 } 4904 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4905 4906 static void spapr_machine_register_types(void) 4907 { 4908 type_register_static(&spapr_machine_info); 4909 } 4910 4911 type_init(spapr_machine_register_types) 4912