1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "hw/mem/memory-device.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_INTC 0x00001111 100 101 /* These two functions implement the VCPU id numbering: one to compute them 102 * all and one to identify thread 0 of a VCORE. Any change to the first one 103 * is likely to have an impact on the second one, so let's keep them close. 104 */ 105 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 106 { 107 assert(spapr->vsmt); 108 return 109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 110 } 111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 112 PowerPCCPU *cpu) 113 { 114 assert(spapr->vsmt); 115 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 116 } 117 118 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 119 { 120 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 121 * and newer QEMUs don't even have them. In both cases, we don't want 122 * to send anything on the wire. 123 */ 124 return false; 125 } 126 127 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 128 .name = "icp/server", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .needed = pre_2_10_vmstate_dummy_icp_needed, 132 .fields = (VMStateField[]) { 133 VMSTATE_UNUSED(4), /* uint32_t xirr */ 134 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 135 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 136 VMSTATE_END_OF_LIST() 137 }, 138 }; 139 140 static void pre_2_10_vmstate_register_dummy_icp(int i) 141 { 142 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 143 (void *)(uintptr_t) i); 144 } 145 146 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 147 { 148 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 149 (void *)(uintptr_t) i); 150 } 151 152 int spapr_max_server_number(sPAPRMachineState *spapr) 153 { 154 assert(spapr->vsmt); 155 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 156 } 157 158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 159 int smt_threads) 160 { 161 int i, ret = 0; 162 uint32_t servers_prop[smt_threads]; 163 uint32_t gservers_prop[smt_threads * 2]; 164 int index = spapr_get_vcpu_id(cpu); 165 166 if (cpu->compat_pvr) { 167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 168 if (ret < 0) { 169 return ret; 170 } 171 } 172 173 /* Build interrupt servers and gservers properties */ 174 for (i = 0; i < smt_threads; i++) { 175 servers_prop[i] = cpu_to_be32(index + i); 176 /* Hack, direct the group queues back to cpu 0 */ 177 gservers_prop[i*2] = cpu_to_be32(index + i); 178 gservers_prop[i*2 + 1] = 0; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 181 servers_prop, sizeof(servers_prop)); 182 if (ret < 0) { 183 return ret; 184 } 185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 186 gservers_prop, sizeof(gservers_prop)); 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 192 { 193 int index = spapr_get_vcpu_id(cpu); 194 uint32_t associativity[] = {cpu_to_be32(0x5), 195 cpu_to_be32(0x0), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(cpu->node_id), 199 cpu_to_be32(index)}; 200 201 /* Advertise NUMA via ibm,associativity */ 202 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 203 sizeof(associativity)); 204 } 205 206 /* Populate the "ibm,pa-features" property */ 207 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset, 210 bool legacy_guest) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (legacy_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 287 { 288 int ret = 0, offset, cpus_offset; 289 CPUState *cs; 290 char cpu_model[32]; 291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 292 293 CPU_FOREACH(cs) { 294 PowerPCCPU *cpu = POWERPC_CPU(cs); 295 DeviceClass *dc = DEVICE_GET_CLASS(cs); 296 int index = spapr_get_vcpu_id(cpu); 297 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 298 299 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 300 continue; 301 } 302 303 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 304 305 cpus_offset = fdt_path_offset(fdt, "/cpus"); 306 if (cpus_offset < 0) { 307 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 308 if (cpus_offset < 0) { 309 return cpus_offset; 310 } 311 } 312 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 313 if (offset < 0) { 314 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 315 if (offset < 0) { 316 return offset; 317 } 318 } 319 320 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 321 pft_size_prop, sizeof(pft_size_prop)); 322 if (ret < 0) { 323 return ret; 324 } 325 326 if (nb_numa_nodes > 1) { 327 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 328 if (ret < 0) { 329 return ret; 330 } 331 } 332 333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 334 if (ret < 0) { 335 return ret; 336 } 337 338 spapr_populate_pa_features(spapr, cpu, fdt, offset, 339 spapr->cas_legacy_guest_workaround); 340 } 341 return ret; 342 } 343 344 static hwaddr spapr_node0_size(MachineState *machine) 345 { 346 if (nb_numa_nodes) { 347 int i; 348 for (i = 0; i < nb_numa_nodes; ++i) { 349 if (numa_info[i].node_mem) { 350 return MIN(pow2floor(numa_info[i].node_mem), 351 machine->ram_size); 352 } 353 } 354 } 355 return machine->ram_size; 356 } 357 358 static void add_str(GString *s, const gchar *s1) 359 { 360 g_string_append_len(s, s1, strlen(s1) + 1); 361 } 362 363 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 364 hwaddr size) 365 { 366 uint32_t associativity[] = { 367 cpu_to_be32(0x4), /* length */ 368 cpu_to_be32(0x0), cpu_to_be32(0x0), 369 cpu_to_be32(0x0), cpu_to_be32(nodeid) 370 }; 371 char mem_name[32]; 372 uint64_t mem_reg_property[2]; 373 int off; 374 375 mem_reg_property[0] = cpu_to_be64(start); 376 mem_reg_property[1] = cpu_to_be64(size); 377 378 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 379 off = fdt_add_subnode(fdt, 0, mem_name); 380 _FDT(off); 381 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 382 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 383 sizeof(mem_reg_property)))); 384 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 385 sizeof(associativity)))); 386 return off; 387 } 388 389 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 390 { 391 MachineState *machine = MACHINE(spapr); 392 hwaddr mem_start, node_size; 393 int i, nb_nodes = nb_numa_nodes; 394 NodeInfo *nodes = numa_info; 395 NodeInfo ramnode; 396 397 /* No NUMA nodes, assume there is just one node with whole RAM */ 398 if (!nb_numa_nodes) { 399 nb_nodes = 1; 400 ramnode.node_mem = machine->ram_size; 401 nodes = &ramnode; 402 } 403 404 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 405 if (!nodes[i].node_mem) { 406 continue; 407 } 408 if (mem_start >= machine->ram_size) { 409 node_size = 0; 410 } else { 411 node_size = nodes[i].node_mem; 412 if (node_size > machine->ram_size - mem_start) { 413 node_size = machine->ram_size - mem_start; 414 } 415 } 416 if (!mem_start) { 417 /* spapr_machine_init() checks for rma_size <= node0_size 418 * already */ 419 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 420 mem_start += spapr->rma_size; 421 node_size -= spapr->rma_size; 422 } 423 for ( ; node_size; ) { 424 hwaddr sizetmp = pow2floor(node_size); 425 426 /* mem_start != 0 here */ 427 if (ctzl(mem_start) < ctzl(sizetmp)) { 428 sizetmp = 1ULL << ctzl(mem_start); 429 } 430 431 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 432 node_size -= sizetmp; 433 mem_start += sizetmp; 434 } 435 } 436 437 return 0; 438 } 439 440 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 441 sPAPRMachineState *spapr) 442 { 443 PowerPCCPU *cpu = POWERPC_CPU(cs); 444 CPUPPCState *env = &cpu->env; 445 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 446 int index = spapr_get_vcpu_id(cpu); 447 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 448 0xffffffff, 0xffffffff}; 449 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 450 : SPAPR_TIMEBASE_FREQ; 451 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 452 uint32_t page_sizes_prop[64]; 453 size_t page_sizes_prop_size; 454 uint32_t vcpus_per_socket = smp_threads * smp_cores; 455 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 456 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 457 sPAPRDRConnector *drc; 458 int drc_index; 459 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 460 int i; 461 462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 463 if (drc) { 464 drc_index = spapr_drc_index(drc); 465 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 466 } 467 468 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 469 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 470 471 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 472 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 473 env->dcache_line_size))); 474 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 475 env->dcache_line_size))); 476 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 477 env->icache_line_size))); 478 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 479 env->icache_line_size))); 480 481 if (pcc->l1_dcache_size) { 482 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 483 pcc->l1_dcache_size))); 484 } else { 485 warn_report("Unknown L1 dcache size for cpu"); 486 } 487 if (pcc->l1_icache_size) { 488 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 489 pcc->l1_icache_size))); 490 } else { 491 warn_report("Unknown L1 icache size for cpu"); 492 } 493 494 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 497 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 499 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 500 501 if (env->spr_cb[SPR_PURR].oea_read) { 502 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 503 } 504 505 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 507 segs, sizeof(segs)))); 508 } 509 510 /* Advertise VSX (vector extensions) if available 511 * 1 == VMX / Altivec available 512 * 2 == VSX available 513 * 514 * Only CPUs for which we create core types in spapr_cpu_core.c 515 * are possible, and all of those have VMX */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 518 } else { 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 520 } 521 522 /* Advertise DFP (Decimal Floating Point) if available 523 * 0 / no property == no DFP 524 * 1 == DFP available */ 525 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 527 } 528 529 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 530 sizeof(page_sizes_prop)); 531 if (page_sizes_prop_size) { 532 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 533 page_sizes_prop, page_sizes_prop_size))); 534 } 535 536 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 537 538 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 539 cs->cpu_index / vcpus_per_socket))); 540 541 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 542 pft_size_prop, sizeof(pft_size_prop)))); 543 544 if (nb_numa_nodes > 1) { 545 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 546 } 547 548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 549 550 if (pcc->radix_page_info) { 551 for (i = 0; i < pcc->radix_page_info->count; i++) { 552 radix_AP_encodings[i] = 553 cpu_to_be32(pcc->radix_page_info->entries[i]); 554 } 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 556 radix_AP_encodings, 557 pcc->radix_page_info->count * 558 sizeof(radix_AP_encodings[0])))); 559 } 560 } 561 562 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 563 { 564 CPUState **rev; 565 CPUState *cs; 566 int n_cpus; 567 int cpus_offset; 568 char *nodename; 569 int i; 570 571 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 572 _FDT(cpus_offset); 573 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 575 576 /* 577 * We walk the CPUs in reverse order to ensure that CPU DT nodes 578 * created by fdt_add_subnode() end up in the right order in FDT 579 * for the guest kernel the enumerate the CPUs correctly. 580 * 581 * The CPU list cannot be traversed in reverse order, so we need 582 * to do extra work. 583 */ 584 n_cpus = 0; 585 rev = NULL; 586 CPU_FOREACH(cs) { 587 rev = g_renew(CPUState *, rev, n_cpus + 1); 588 rev[n_cpus++] = cs; 589 } 590 591 for (i = n_cpus - 1; i >= 0; i--) { 592 CPUState *cs = rev[i]; 593 PowerPCCPU *cpu = POWERPC_CPU(cs); 594 int index = spapr_get_vcpu_id(cpu); 595 DeviceClass *dc = DEVICE_GET_CLASS(cs); 596 int offset; 597 598 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 599 continue; 600 } 601 602 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 603 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 604 g_free(nodename); 605 _FDT(offset); 606 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 607 } 608 609 g_free(rev); 610 } 611 612 static int spapr_rng_populate_dt(void *fdt) 613 { 614 int node; 615 int ret; 616 617 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 618 if (node <= 0) { 619 return -1; 620 } 621 ret = fdt_setprop_string(fdt, node, "device_type", 622 "ibm,platform-facilities"); 623 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 624 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 625 626 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 627 if (node <= 0) { 628 return -1; 629 } 630 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 631 632 return ret ? -1 : 0; 633 } 634 635 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 636 { 637 MemoryDeviceInfoList *info; 638 639 for (info = list; info; info = info->next) { 640 MemoryDeviceInfo *value = info->value; 641 642 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 643 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 644 645 if (addr >= pcdimm_info->addr && 646 addr < (pcdimm_info->addr + pcdimm_info->size)) { 647 return pcdimm_info->node; 648 } 649 } 650 } 651 652 return -1; 653 } 654 655 struct sPAPRDrconfCellV2 { 656 uint32_t seq_lmbs; 657 uint64_t base_addr; 658 uint32_t drc_index; 659 uint32_t aa_index; 660 uint32_t flags; 661 } QEMU_PACKED; 662 663 typedef struct DrconfCellQueue { 664 struct sPAPRDrconfCellV2 cell; 665 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 666 } DrconfCellQueue; 667 668 static DrconfCellQueue * 669 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 670 uint32_t drc_index, uint32_t aa_index, 671 uint32_t flags) 672 { 673 DrconfCellQueue *elem; 674 675 elem = g_malloc0(sizeof(*elem)); 676 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 677 elem->cell.base_addr = cpu_to_be64(base_addr); 678 elem->cell.drc_index = cpu_to_be32(drc_index); 679 elem->cell.aa_index = cpu_to_be32(aa_index); 680 elem->cell.flags = cpu_to_be32(flags); 681 682 return elem; 683 } 684 685 /* ibm,dynamic-memory-v2 */ 686 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 687 int offset, MemoryDeviceInfoList *dimms) 688 { 689 MachineState *machine = MACHINE(spapr); 690 uint8_t *int_buf, *cur_index; 691 int ret; 692 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 693 uint64_t addr, cur_addr, size; 694 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 695 uint64_t mem_end = machine->device_memory->base + 696 memory_region_size(&machine->device_memory->mr); 697 uint32_t node, buf_len, nr_entries = 0; 698 sPAPRDRConnector *drc; 699 DrconfCellQueue *elem, *next; 700 MemoryDeviceInfoList *info; 701 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 702 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 703 704 /* Entry to cover RAM and the gap area */ 705 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 706 SPAPR_LMB_FLAGS_RESERVED | 707 SPAPR_LMB_FLAGS_DRC_INVALID); 708 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 709 nr_entries++; 710 711 cur_addr = machine->device_memory->base; 712 for (info = dimms; info; info = info->next) { 713 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 714 715 addr = di->addr; 716 size = di->size; 717 node = di->node; 718 719 /* Entry for hot-pluggable area */ 720 if (cur_addr < addr) { 721 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 722 g_assert(drc); 723 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 724 cur_addr, spapr_drc_index(drc), -1, 0); 725 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 726 nr_entries++; 727 } 728 729 /* Entry for DIMM */ 730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 731 g_assert(drc); 732 elem = spapr_get_drconf_cell(size / lmb_size, addr, 733 spapr_drc_index(drc), node, 734 SPAPR_LMB_FLAGS_ASSIGNED); 735 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 736 nr_entries++; 737 cur_addr = addr + size; 738 } 739 740 /* Entry for remaining hotpluggable area */ 741 if (cur_addr < mem_end) { 742 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 743 g_assert(drc); 744 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 745 cur_addr, spapr_drc_index(drc), -1, 0); 746 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 747 nr_entries++; 748 } 749 750 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 751 int_buf = cur_index = g_malloc0(buf_len); 752 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 753 cur_index += sizeof(nr_entries); 754 755 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 756 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 757 cur_index += sizeof(elem->cell); 758 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 759 g_free(elem); 760 } 761 762 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 763 g_free(int_buf); 764 if (ret < 0) { 765 return -1; 766 } 767 return 0; 768 } 769 770 /* ibm,dynamic-memory */ 771 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 772 int offset, MemoryDeviceInfoList *dimms) 773 { 774 MachineState *machine = MACHINE(spapr); 775 int i, ret; 776 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 777 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 778 uint32_t nr_lmbs = (machine->device_memory->base + 779 memory_region_size(&machine->device_memory->mr)) / 780 lmb_size; 781 uint32_t *int_buf, *cur_index, buf_len; 782 783 /* 784 * Allocate enough buffer size to fit in ibm,dynamic-memory 785 */ 786 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 787 cur_index = int_buf = g_malloc0(buf_len); 788 int_buf[0] = cpu_to_be32(nr_lmbs); 789 cur_index++; 790 for (i = 0; i < nr_lmbs; i++) { 791 uint64_t addr = i * lmb_size; 792 uint32_t *dynamic_memory = cur_index; 793 794 if (i >= device_lmb_start) { 795 sPAPRDRConnector *drc; 796 797 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 798 g_assert(drc); 799 800 dynamic_memory[0] = cpu_to_be32(addr >> 32); 801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 802 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 804 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 805 if (memory_region_present(get_system_memory(), addr)) { 806 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 807 } else { 808 dynamic_memory[5] = cpu_to_be32(0); 809 } 810 } else { 811 /* 812 * LMB information for RMA, boot time RAM and gap b/n RAM and 813 * device memory region -- all these are marked as reserved 814 * and as having no valid DRC. 815 */ 816 dynamic_memory[0] = cpu_to_be32(addr >> 32); 817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 818 dynamic_memory[2] = cpu_to_be32(0); 819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 820 dynamic_memory[4] = cpu_to_be32(-1); 821 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 822 SPAPR_LMB_FLAGS_DRC_INVALID); 823 } 824 825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 826 } 827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 828 g_free(int_buf); 829 if (ret < 0) { 830 return -1; 831 } 832 return 0; 833 } 834 835 /* 836 * Adds ibm,dynamic-reconfiguration-memory node. 837 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 838 * of this device tree node. 839 */ 840 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 841 { 842 MachineState *machine = MACHINE(spapr); 843 int ret, i, offset; 844 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 845 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 846 uint32_t *int_buf, *cur_index, buf_len; 847 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 848 MemoryDeviceInfoList *dimms = NULL; 849 850 /* 851 * Don't create the node if there is no device memory 852 */ 853 if (machine->ram_size == machine->maxram_size) { 854 return 0; 855 } 856 857 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 858 859 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 860 sizeof(prop_lmb_size)); 861 if (ret < 0) { 862 return ret; 863 } 864 865 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 866 if (ret < 0) { 867 return ret; 868 } 869 870 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 871 if (ret < 0) { 872 return ret; 873 } 874 875 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 876 dimms = qmp_memory_device_list(); 877 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 878 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 879 } else { 880 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 881 } 882 qapi_free_MemoryDeviceInfoList(dimms); 883 884 if (ret < 0) { 885 return ret; 886 } 887 888 /* ibm,associativity-lookup-arrays */ 889 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 890 cur_index = int_buf = g_malloc0(buf_len); 891 int_buf[0] = cpu_to_be32(nr_nodes); 892 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 893 cur_index += 2; 894 for (i = 0; i < nr_nodes; i++) { 895 uint32_t associativity[] = { 896 cpu_to_be32(0x0), 897 cpu_to_be32(0x0), 898 cpu_to_be32(0x0), 899 cpu_to_be32(i) 900 }; 901 memcpy(cur_index, associativity, sizeof(associativity)); 902 cur_index += 4; 903 } 904 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 905 (cur_index - int_buf) * sizeof(uint32_t)); 906 g_free(int_buf); 907 908 return ret; 909 } 910 911 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 912 sPAPROptionVector *ov5_updates) 913 { 914 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 915 int ret = 0, offset; 916 917 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 918 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 919 g_assert(smc->dr_lmb_enabled); 920 ret = spapr_populate_drconf_memory(spapr, fdt); 921 if (ret) { 922 goto out; 923 } 924 } 925 926 offset = fdt_path_offset(fdt, "/chosen"); 927 if (offset < 0) { 928 offset = fdt_add_subnode(fdt, 0, "chosen"); 929 if (offset < 0) { 930 return offset; 931 } 932 } 933 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 934 "ibm,architecture-vec-5"); 935 936 out: 937 return ret; 938 } 939 940 static bool spapr_hotplugged_dev_before_cas(void) 941 { 942 Object *drc_container, *obj; 943 ObjectProperty *prop; 944 ObjectPropertyIterator iter; 945 946 drc_container = container_get(object_get_root(), "/dr-connector"); 947 object_property_iter_init(&iter, drc_container); 948 while ((prop = object_property_iter_next(&iter))) { 949 if (!strstart(prop->type, "link<", NULL)) { 950 continue; 951 } 952 obj = object_property_get_link(drc_container, prop->name, NULL); 953 if (spapr_drc_needed(obj)) { 954 return true; 955 } 956 } 957 return false; 958 } 959 960 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 961 target_ulong addr, target_ulong size, 962 sPAPROptionVector *ov5_updates) 963 { 964 void *fdt, *fdt_skel; 965 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 966 967 if (spapr_hotplugged_dev_before_cas()) { 968 return 1; 969 } 970 971 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 972 error_report("SLOF provided an unexpected CAS buffer size " 973 TARGET_FMT_lu " (min: %zu, max: %u)", 974 size, sizeof(hdr), FW_MAX_SIZE); 975 exit(EXIT_FAILURE); 976 } 977 978 size -= sizeof(hdr); 979 980 /* Create skeleton */ 981 fdt_skel = g_malloc0(size); 982 _FDT((fdt_create(fdt_skel, size))); 983 _FDT((fdt_finish_reservemap(fdt_skel))); 984 _FDT((fdt_begin_node(fdt_skel, ""))); 985 _FDT((fdt_end_node(fdt_skel))); 986 _FDT((fdt_finish(fdt_skel))); 987 fdt = g_malloc0(size); 988 _FDT((fdt_open_into(fdt_skel, fdt, size))); 989 g_free(fdt_skel); 990 991 /* Fixup cpu nodes */ 992 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 993 994 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 995 return -1; 996 } 997 998 /* Pack resulting tree */ 999 _FDT((fdt_pack(fdt))); 1000 1001 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1002 trace_spapr_cas_failed(size); 1003 return -1; 1004 } 1005 1006 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1007 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1008 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1009 g_free(fdt); 1010 1011 return 0; 1012 } 1013 1014 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1015 { 1016 int rtas; 1017 GString *hypertas = g_string_sized_new(256); 1018 GString *qemu_hypertas = g_string_sized_new(256); 1019 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1020 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1021 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1022 uint32_t lrdr_capacity[] = { 1023 cpu_to_be32(max_device_addr >> 32), 1024 cpu_to_be32(max_device_addr & 0xffffffff), 1025 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1026 cpu_to_be32(max_cpus / smp_threads), 1027 }; 1028 uint32_t maxdomains[] = { 1029 cpu_to_be32(4), 1030 cpu_to_be32(0), 1031 cpu_to_be32(0), 1032 cpu_to_be32(0), 1033 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1), 1034 }; 1035 1036 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1037 1038 /* hypertas */ 1039 add_str(hypertas, "hcall-pft"); 1040 add_str(hypertas, "hcall-term"); 1041 add_str(hypertas, "hcall-dabr"); 1042 add_str(hypertas, "hcall-interrupt"); 1043 add_str(hypertas, "hcall-tce"); 1044 add_str(hypertas, "hcall-vio"); 1045 add_str(hypertas, "hcall-splpar"); 1046 add_str(hypertas, "hcall-bulk"); 1047 add_str(hypertas, "hcall-set-mode"); 1048 add_str(hypertas, "hcall-sprg0"); 1049 add_str(hypertas, "hcall-copy"); 1050 add_str(hypertas, "hcall-debug"); 1051 add_str(hypertas, "hcall-vphn"); 1052 add_str(qemu_hypertas, "hcall-memop1"); 1053 1054 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1055 add_str(hypertas, "hcall-multi-tce"); 1056 } 1057 1058 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1059 add_str(hypertas, "hcall-hpt-resize"); 1060 } 1061 1062 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1063 hypertas->str, hypertas->len)); 1064 g_string_free(hypertas, TRUE); 1065 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1066 qemu_hypertas->str, qemu_hypertas->len)); 1067 g_string_free(qemu_hypertas, TRUE); 1068 1069 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1070 refpoints, sizeof(refpoints))); 1071 1072 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1073 maxdomains, sizeof(maxdomains))); 1074 1075 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1076 RTAS_ERROR_LOG_MAX)); 1077 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1078 RTAS_EVENT_SCAN_RATE)); 1079 1080 g_assert(msi_nonbroken); 1081 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1082 1083 /* 1084 * According to PAPR, rtas ibm,os-term does not guarantee a return 1085 * back to the guest cpu. 1086 * 1087 * While an additional ibm,extended-os-term property indicates 1088 * that rtas call return will always occur. Set this property. 1089 */ 1090 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1091 1092 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1093 lrdr_capacity, sizeof(lrdr_capacity))); 1094 1095 spapr_dt_rtas_tokens(fdt, rtas); 1096 } 1097 1098 /* 1099 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1100 * and the XIVE features that the guest may request and thus the valid 1101 * values for bytes 23..26 of option vector 5: 1102 */ 1103 static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt, 1104 int chosen) 1105 { 1106 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1107 1108 char val[2 * 4] = { 1109 23, spapr->irq->ov5, /* Xive mode. */ 1110 24, 0x00, /* Hash/Radix, filled in below. */ 1111 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1112 26, 0x40, /* Radix options: GTSE == yes. */ 1113 }; 1114 1115 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1116 first_ppc_cpu->compat_pvr)) { 1117 /* 1118 * If we're in a pre POWER9 compat mode then the guest should 1119 * do hash and use the legacy interrupt mode 1120 */ 1121 val[1] = 0x00; /* XICS */ 1122 val[3] = 0x00; /* Hash */ 1123 } else if (kvm_enabled()) { 1124 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1125 val[3] = 0x80; /* OV5_MMU_BOTH */ 1126 } else if (kvmppc_has_cap_mmu_radix()) { 1127 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1128 } else { 1129 val[3] = 0x00; /* Hash */ 1130 } 1131 } else { 1132 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1133 val[3] = 0xC0; 1134 } 1135 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1136 val, sizeof(val))); 1137 } 1138 1139 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1140 { 1141 MachineState *machine = MACHINE(spapr); 1142 int chosen; 1143 const char *boot_device = machine->boot_order; 1144 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1145 size_t cb = 0; 1146 char *bootlist = get_boot_devices_list(&cb); 1147 1148 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1149 1150 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1151 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1152 spapr->initrd_base)); 1153 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1154 spapr->initrd_base + spapr->initrd_size)); 1155 1156 if (spapr->kernel_size) { 1157 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1158 cpu_to_be64(spapr->kernel_size) }; 1159 1160 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1161 &kprop, sizeof(kprop))); 1162 if (spapr->kernel_le) { 1163 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1164 } 1165 } 1166 if (boot_menu) { 1167 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1168 } 1169 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1170 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1171 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1172 1173 if (cb && bootlist) { 1174 int i; 1175 1176 for (i = 0; i < cb; i++) { 1177 if (bootlist[i] == '\n') { 1178 bootlist[i] = ' '; 1179 } 1180 } 1181 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1182 } 1183 1184 if (boot_device && strlen(boot_device)) { 1185 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1186 } 1187 1188 if (!spapr->has_graphics && stdout_path) { 1189 /* 1190 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1191 * kernel. New platforms should only use the "stdout-path" property. Set 1192 * the new property and continue using older property to remain 1193 * compatible with the existing firmware. 1194 */ 1195 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1196 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1197 } 1198 1199 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1200 1201 g_free(stdout_path); 1202 g_free(bootlist); 1203 } 1204 1205 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1206 { 1207 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1208 * KVM to work under pHyp with some guest co-operation */ 1209 int hypervisor; 1210 uint8_t hypercall[16]; 1211 1212 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1213 /* indicate KVM hypercall interface */ 1214 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1215 if (kvmppc_has_cap_fixup_hcalls()) { 1216 /* 1217 * Older KVM versions with older guest kernels were broken 1218 * with the magic page, don't allow the guest to map it. 1219 */ 1220 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1221 sizeof(hypercall))) { 1222 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1223 hypercall, sizeof(hypercall))); 1224 } 1225 } 1226 } 1227 1228 static void *spapr_build_fdt(sPAPRMachineState *spapr) 1229 { 1230 MachineState *machine = MACHINE(spapr); 1231 MachineClass *mc = MACHINE_GET_CLASS(machine); 1232 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1233 int ret; 1234 void *fdt; 1235 sPAPRPHBState *phb; 1236 char *buf; 1237 1238 fdt = g_malloc0(FDT_MAX_SIZE); 1239 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1240 1241 /* Root node */ 1242 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1243 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1244 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1245 1246 /* 1247 * Add info to guest to indentify which host is it being run on 1248 * and what is the uuid of the guest 1249 */ 1250 if (spapr->host_model && !g_str_equal(spapr->host_model, "none")) { 1251 if (g_str_equal(spapr->host_model, "passthrough")) { 1252 /* -M host-model=passthrough */ 1253 if (kvmppc_get_host_model(&buf)) { 1254 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1255 g_free(buf); 1256 } 1257 } else { 1258 /* -M host-model=<user-string> */ 1259 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1260 } 1261 } 1262 1263 if (spapr->host_serial && !g_str_equal(spapr->host_serial, "none")) { 1264 if (g_str_equal(spapr->host_serial, "passthrough")) { 1265 /* -M host-serial=passthrough */ 1266 if (kvmppc_get_host_serial(&buf)) { 1267 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1268 g_free(buf); 1269 } 1270 } else { 1271 /* -M host-serial=<user-string> */ 1272 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1273 } 1274 } 1275 1276 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1277 1278 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1279 if (qemu_uuid_set) { 1280 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1281 } 1282 g_free(buf); 1283 1284 if (qemu_get_vm_name()) { 1285 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1286 qemu_get_vm_name())); 1287 } 1288 1289 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1290 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1291 1292 /* /interrupt controller */ 1293 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, 1294 PHANDLE_INTC); 1295 1296 ret = spapr_populate_memory(spapr, fdt); 1297 if (ret < 0) { 1298 error_report("couldn't setup memory nodes in fdt"); 1299 exit(1); 1300 } 1301 1302 /* /vdevice */ 1303 spapr_dt_vdevice(spapr->vio_bus, fdt); 1304 1305 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1306 ret = spapr_rng_populate_dt(fdt); 1307 if (ret < 0) { 1308 error_report("could not set up rng device in the fdt"); 1309 exit(1); 1310 } 1311 } 1312 1313 QLIST_FOREACH(phb, &spapr->phbs, list) { 1314 ret = spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt, 1315 spapr->irq->nr_msis); 1316 if (ret < 0) { 1317 error_report("couldn't setup PCI devices in fdt"); 1318 exit(1); 1319 } 1320 } 1321 1322 /* cpus */ 1323 spapr_populate_cpus_dt_node(fdt, spapr); 1324 1325 if (smc->dr_lmb_enabled) { 1326 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1327 } 1328 1329 if (mc->has_hotpluggable_cpus) { 1330 int offset = fdt_path_offset(fdt, "/cpus"); 1331 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1332 SPAPR_DR_CONNECTOR_TYPE_CPU); 1333 if (ret < 0) { 1334 error_report("Couldn't set up CPU DR device tree properties"); 1335 exit(1); 1336 } 1337 } 1338 1339 /* /event-sources */ 1340 spapr_dt_events(spapr, fdt); 1341 1342 /* /rtas */ 1343 spapr_dt_rtas(spapr, fdt); 1344 1345 /* /chosen */ 1346 spapr_dt_chosen(spapr, fdt); 1347 1348 /* /hypervisor */ 1349 if (kvm_enabled()) { 1350 spapr_dt_hypervisor(spapr, fdt); 1351 } 1352 1353 /* Build memory reserve map */ 1354 if (spapr->kernel_size) { 1355 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1356 } 1357 if (spapr->initrd_size) { 1358 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1359 } 1360 1361 /* ibm,client-architecture-support updates */ 1362 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1363 if (ret < 0) { 1364 error_report("couldn't setup CAS properties fdt"); 1365 exit(1); 1366 } 1367 1368 return fdt; 1369 } 1370 1371 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1372 { 1373 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1374 } 1375 1376 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1377 PowerPCCPU *cpu) 1378 { 1379 CPUPPCState *env = &cpu->env; 1380 1381 /* The TCG path should also be holding the BQL at this point */ 1382 g_assert(qemu_mutex_iothread_locked()); 1383 1384 if (msr_pr) { 1385 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1386 env->gpr[3] = H_PRIVILEGE; 1387 } else { 1388 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1389 } 1390 } 1391 1392 struct LPCRSyncState { 1393 target_ulong value; 1394 target_ulong mask; 1395 }; 1396 1397 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1398 { 1399 struct LPCRSyncState *s = arg.host_ptr; 1400 PowerPCCPU *cpu = POWERPC_CPU(cs); 1401 CPUPPCState *env = &cpu->env; 1402 target_ulong lpcr; 1403 1404 cpu_synchronize_state(cs); 1405 lpcr = env->spr[SPR_LPCR]; 1406 lpcr &= ~s->mask; 1407 lpcr |= s->value; 1408 ppc_store_lpcr(cpu, lpcr); 1409 } 1410 1411 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1412 { 1413 CPUState *cs; 1414 struct LPCRSyncState s = { 1415 .value = value, 1416 .mask = mask 1417 }; 1418 CPU_FOREACH(cs) { 1419 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1420 } 1421 } 1422 1423 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1424 { 1425 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1426 1427 /* Copy PATE1:GR into PATE0:HR */ 1428 entry->dw0 = spapr->patb_entry & PATE0_HR; 1429 entry->dw1 = spapr->patb_entry; 1430 } 1431 1432 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1433 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1434 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1435 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1436 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1437 1438 /* 1439 * Get the fd to access the kernel htab, re-opening it if necessary 1440 */ 1441 static int get_htab_fd(sPAPRMachineState *spapr) 1442 { 1443 Error *local_err = NULL; 1444 1445 if (spapr->htab_fd >= 0) { 1446 return spapr->htab_fd; 1447 } 1448 1449 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1450 if (spapr->htab_fd < 0) { 1451 error_report_err(local_err); 1452 } 1453 1454 return spapr->htab_fd; 1455 } 1456 1457 void close_htab_fd(sPAPRMachineState *spapr) 1458 { 1459 if (spapr->htab_fd >= 0) { 1460 close(spapr->htab_fd); 1461 } 1462 spapr->htab_fd = -1; 1463 } 1464 1465 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1466 { 1467 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1468 1469 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1470 } 1471 1472 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1473 { 1474 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1475 1476 assert(kvm_enabled()); 1477 1478 if (!spapr->htab) { 1479 return 0; 1480 } 1481 1482 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1483 } 1484 1485 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1486 hwaddr ptex, int n) 1487 { 1488 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1489 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1490 1491 if (!spapr->htab) { 1492 /* 1493 * HTAB is controlled by KVM. Fetch into temporary buffer 1494 */ 1495 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1496 kvmppc_read_hptes(hptes, ptex, n); 1497 return hptes; 1498 } 1499 1500 /* 1501 * HTAB is controlled by QEMU. Just point to the internally 1502 * accessible PTEG. 1503 */ 1504 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1505 } 1506 1507 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1508 const ppc_hash_pte64_t *hptes, 1509 hwaddr ptex, int n) 1510 { 1511 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1512 1513 if (!spapr->htab) { 1514 g_free((void *)hptes); 1515 } 1516 1517 /* Nothing to do for qemu managed HPT */ 1518 } 1519 1520 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1521 uint64_t pte0, uint64_t pte1) 1522 { 1523 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1524 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1525 1526 if (!spapr->htab) { 1527 kvmppc_write_hpte(ptex, pte0, pte1); 1528 } else { 1529 if (pte0 & HPTE64_V_VALID) { 1530 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1531 /* 1532 * When setting valid, we write PTE1 first. This ensures 1533 * proper synchronization with the reading code in 1534 * ppc_hash64_pteg_search() 1535 */ 1536 smp_wmb(); 1537 stq_p(spapr->htab + offset, pte0); 1538 } else { 1539 stq_p(spapr->htab + offset, pte0); 1540 /* 1541 * When clearing it we set PTE0 first. This ensures proper 1542 * synchronization with the reading code in 1543 * ppc_hash64_pteg_search() 1544 */ 1545 smp_wmb(); 1546 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1547 } 1548 } 1549 } 1550 1551 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1552 { 1553 int shift; 1554 1555 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1556 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1557 * that's much more than is needed for Linux guests */ 1558 shift = ctz64(pow2ceil(ramsize)) - 7; 1559 shift = MAX(shift, 18); /* Minimum architected size */ 1560 shift = MIN(shift, 46); /* Maximum architected size */ 1561 return shift; 1562 } 1563 1564 void spapr_free_hpt(sPAPRMachineState *spapr) 1565 { 1566 g_free(spapr->htab); 1567 spapr->htab = NULL; 1568 spapr->htab_shift = 0; 1569 close_htab_fd(spapr); 1570 } 1571 1572 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1573 Error **errp) 1574 { 1575 long rc; 1576 1577 /* Clean up any HPT info from a previous boot */ 1578 spapr_free_hpt(spapr); 1579 1580 rc = kvmppc_reset_htab(shift); 1581 if (rc < 0) { 1582 /* kernel-side HPT needed, but couldn't allocate one */ 1583 error_setg_errno(errp, errno, 1584 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1585 shift); 1586 /* This is almost certainly fatal, but if the caller really 1587 * wants to carry on with shift == 0, it's welcome to try */ 1588 } else if (rc > 0) { 1589 /* kernel-side HPT allocated */ 1590 if (rc != shift) { 1591 error_setg(errp, 1592 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1593 shift, rc); 1594 } 1595 1596 spapr->htab_shift = shift; 1597 spapr->htab = NULL; 1598 } else { 1599 /* kernel-side HPT not needed, allocate in userspace instead */ 1600 size_t size = 1ULL << shift; 1601 int i; 1602 1603 spapr->htab = qemu_memalign(size, size); 1604 if (!spapr->htab) { 1605 error_setg_errno(errp, errno, 1606 "Could not allocate HPT of order %d", shift); 1607 return; 1608 } 1609 1610 memset(spapr->htab, 0, size); 1611 spapr->htab_shift = shift; 1612 1613 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1614 DIRTY_HPTE(HPTE(spapr->htab, i)); 1615 } 1616 } 1617 /* We're setting up a hash table, so that means we're not radix */ 1618 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1619 } 1620 1621 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1622 { 1623 int hpt_shift; 1624 1625 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1626 || (spapr->cas_reboot 1627 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1628 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1629 } else { 1630 uint64_t current_ram_size; 1631 1632 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1633 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1634 } 1635 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1636 1637 if (spapr->vrma_adjust) { 1638 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1639 spapr->htab_shift); 1640 } 1641 } 1642 1643 static int spapr_reset_drcs(Object *child, void *opaque) 1644 { 1645 sPAPRDRConnector *drc = 1646 (sPAPRDRConnector *) object_dynamic_cast(child, 1647 TYPE_SPAPR_DR_CONNECTOR); 1648 1649 if (drc) { 1650 spapr_drc_reset(drc); 1651 } 1652 1653 return 0; 1654 } 1655 1656 static void spapr_machine_reset(void) 1657 { 1658 MachineState *machine = MACHINE(qdev_get_machine()); 1659 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1660 PowerPCCPU *first_ppc_cpu; 1661 uint32_t rtas_limit; 1662 hwaddr rtas_addr, fdt_addr; 1663 void *fdt; 1664 int rc; 1665 1666 spapr_caps_apply(spapr); 1667 1668 first_ppc_cpu = POWERPC_CPU(first_cpu); 1669 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1670 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1671 spapr->max_compat_pvr)) { 1672 /* 1673 * If using KVM with radix mode available, VCPUs can be started 1674 * without a HPT because KVM will start them in radix mode. 1675 * Set the GR bit in PATE so that we know there is no HPT. 1676 */ 1677 spapr->patb_entry = PATE1_GR; 1678 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1679 } else { 1680 spapr_setup_hpt_and_vrma(spapr); 1681 } 1682 1683 /* 1684 * If this reset wasn't generated by CAS, we should reset our 1685 * negotiated options and start from scratch 1686 */ 1687 if (!spapr->cas_reboot) { 1688 spapr_ovec_cleanup(spapr->ov5_cas); 1689 spapr->ov5_cas = spapr_ovec_new(); 1690 1691 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1692 } 1693 1694 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1695 spapr_irq_msi_reset(spapr); 1696 } 1697 1698 qemu_devices_reset(); 1699 1700 /* 1701 * This is fixing some of the default configuration of the XIVE 1702 * devices. To be called after the reset of the machine devices. 1703 */ 1704 spapr_irq_reset(spapr, &error_fatal); 1705 1706 /* DRC reset may cause a device to be unplugged. This will cause troubles 1707 * if this device is used by another device (eg, a running vhost backend 1708 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1709 * situations, we reset DRCs after all devices have been reset. 1710 */ 1711 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1712 1713 spapr_clear_pending_events(spapr); 1714 1715 /* 1716 * We place the device tree and RTAS just below either the top of the RMA, 1717 * or just below 2GB, whichever is lower, so that it can be 1718 * processed with 32-bit real mode code if necessary 1719 */ 1720 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1721 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1722 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1723 1724 fdt = spapr_build_fdt(spapr); 1725 1726 spapr_load_rtas(spapr, fdt, rtas_addr); 1727 1728 rc = fdt_pack(fdt); 1729 1730 /* Should only fail if we've built a corrupted tree */ 1731 assert(rc == 0); 1732 1733 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1734 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1735 fdt_totalsize(fdt), FDT_MAX_SIZE); 1736 exit(1); 1737 } 1738 1739 /* Load the fdt */ 1740 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1741 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1742 g_free(spapr->fdt_blob); 1743 spapr->fdt_size = fdt_totalsize(fdt); 1744 spapr->fdt_initial_size = spapr->fdt_size; 1745 spapr->fdt_blob = fdt; 1746 1747 /* Set up the entry state */ 1748 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1749 first_ppc_cpu->env.gpr[5] = 0; 1750 1751 spapr->cas_reboot = false; 1752 } 1753 1754 static void spapr_create_nvram(sPAPRMachineState *spapr) 1755 { 1756 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1757 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1758 1759 if (dinfo) { 1760 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1761 &error_fatal); 1762 } 1763 1764 qdev_init_nofail(dev); 1765 1766 spapr->nvram = (struct sPAPRNVRAM *)dev; 1767 } 1768 1769 static void spapr_rtc_create(sPAPRMachineState *spapr) 1770 { 1771 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1772 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1773 &error_fatal); 1774 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1775 &error_fatal); 1776 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1777 "date", &error_fatal); 1778 } 1779 1780 /* Returns whether we want to use VGA or not */ 1781 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1782 { 1783 switch (vga_interface_type) { 1784 case VGA_NONE: 1785 return false; 1786 case VGA_DEVICE: 1787 return true; 1788 case VGA_STD: 1789 case VGA_VIRTIO: 1790 case VGA_CIRRUS: 1791 return pci_vga_init(pci_bus) != NULL; 1792 default: 1793 error_setg(errp, 1794 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1795 return false; 1796 } 1797 } 1798 1799 static int spapr_pre_load(void *opaque) 1800 { 1801 int rc; 1802 1803 rc = spapr_caps_pre_load(opaque); 1804 if (rc) { 1805 return rc; 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int spapr_post_load(void *opaque, int version_id) 1812 { 1813 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1814 int err = 0; 1815 1816 err = spapr_caps_post_migration(spapr); 1817 if (err) { 1818 return err; 1819 } 1820 1821 /* 1822 * In earlier versions, there was no separate qdev for the PAPR 1823 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1824 * So when migrating from those versions, poke the incoming offset 1825 * value into the RTC device 1826 */ 1827 if (version_id < 3) { 1828 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1829 if (err) { 1830 return err; 1831 } 1832 } 1833 1834 if (kvm_enabled() && spapr->patb_entry) { 1835 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1836 bool radix = !!(spapr->patb_entry & PATE1_GR); 1837 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1838 1839 /* 1840 * Update LPCR:HR and UPRT as they may not be set properly in 1841 * the stream 1842 */ 1843 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1844 LPCR_HR | LPCR_UPRT); 1845 1846 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1847 if (err) { 1848 error_report("Process table config unsupported by the host"); 1849 return -EINVAL; 1850 } 1851 } 1852 1853 err = spapr_irq_post_load(spapr, version_id); 1854 if (err) { 1855 return err; 1856 } 1857 1858 return err; 1859 } 1860 1861 static int spapr_pre_save(void *opaque) 1862 { 1863 int rc; 1864 1865 rc = spapr_caps_pre_save(opaque); 1866 if (rc) { 1867 return rc; 1868 } 1869 1870 return 0; 1871 } 1872 1873 static bool version_before_3(void *opaque, int version_id) 1874 { 1875 return version_id < 3; 1876 } 1877 1878 static bool spapr_pending_events_needed(void *opaque) 1879 { 1880 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1881 return !QTAILQ_EMPTY(&spapr->pending_events); 1882 } 1883 1884 static const VMStateDescription vmstate_spapr_event_entry = { 1885 .name = "spapr_event_log_entry", 1886 .version_id = 1, 1887 .minimum_version_id = 1, 1888 .fields = (VMStateField[]) { 1889 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1890 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1891 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1892 NULL, extended_length), 1893 VMSTATE_END_OF_LIST() 1894 }, 1895 }; 1896 1897 static const VMStateDescription vmstate_spapr_pending_events = { 1898 .name = "spapr_pending_events", 1899 .version_id = 1, 1900 .minimum_version_id = 1, 1901 .needed = spapr_pending_events_needed, 1902 .fields = (VMStateField[]) { 1903 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1904 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1905 VMSTATE_END_OF_LIST() 1906 }, 1907 }; 1908 1909 static bool spapr_ov5_cas_needed(void *opaque) 1910 { 1911 sPAPRMachineState *spapr = opaque; 1912 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1913 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1914 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1915 bool cas_needed; 1916 1917 /* Prior to the introduction of sPAPROptionVector, we had two option 1918 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1919 * Both of these options encode machine topology into the device-tree 1920 * in such a way that the now-booted OS should still be able to interact 1921 * appropriately with QEMU regardless of what options were actually 1922 * negotiatied on the source side. 1923 * 1924 * As such, we can avoid migrating the CAS-negotiated options if these 1925 * are the only options available on the current machine/platform. 1926 * Since these are the only options available for pseries-2.7 and 1927 * earlier, this allows us to maintain old->new/new->old migration 1928 * compatibility. 1929 * 1930 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1931 * via default pseries-2.8 machines and explicit command-line parameters. 1932 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1933 * of the actual CAS-negotiated values to continue working properly. For 1934 * example, availability of memory unplug depends on knowing whether 1935 * OV5_HP_EVT was negotiated via CAS. 1936 * 1937 * Thus, for any cases where the set of available CAS-negotiatable 1938 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1939 * include the CAS-negotiated options in the migration stream, unless 1940 * if they affect boot time behaviour only. 1941 */ 1942 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1943 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1944 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1945 1946 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1947 * the mask itself since in the future it's possible "legacy" bits may be 1948 * removed via machine options, which could generate a false positive 1949 * that breaks migration. 1950 */ 1951 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1952 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1953 1954 spapr_ovec_cleanup(ov5_mask); 1955 spapr_ovec_cleanup(ov5_legacy); 1956 spapr_ovec_cleanup(ov5_removed); 1957 1958 return cas_needed; 1959 } 1960 1961 static const VMStateDescription vmstate_spapr_ov5_cas = { 1962 .name = "spapr_option_vector_ov5_cas", 1963 .version_id = 1, 1964 .minimum_version_id = 1, 1965 .needed = spapr_ov5_cas_needed, 1966 .fields = (VMStateField[]) { 1967 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1968 vmstate_spapr_ovec, sPAPROptionVector), 1969 VMSTATE_END_OF_LIST() 1970 }, 1971 }; 1972 1973 static bool spapr_patb_entry_needed(void *opaque) 1974 { 1975 sPAPRMachineState *spapr = opaque; 1976 1977 return !!spapr->patb_entry; 1978 } 1979 1980 static const VMStateDescription vmstate_spapr_patb_entry = { 1981 .name = "spapr_patb_entry", 1982 .version_id = 1, 1983 .minimum_version_id = 1, 1984 .needed = spapr_patb_entry_needed, 1985 .fields = (VMStateField[]) { 1986 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1987 VMSTATE_END_OF_LIST() 1988 }, 1989 }; 1990 1991 static bool spapr_irq_map_needed(void *opaque) 1992 { 1993 sPAPRMachineState *spapr = opaque; 1994 1995 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1996 } 1997 1998 static const VMStateDescription vmstate_spapr_irq_map = { 1999 .name = "spapr_irq_map", 2000 .version_id = 1, 2001 .minimum_version_id = 1, 2002 .needed = spapr_irq_map_needed, 2003 .fields = (VMStateField[]) { 2004 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 2005 VMSTATE_END_OF_LIST() 2006 }, 2007 }; 2008 2009 static bool spapr_dtb_needed(void *opaque) 2010 { 2011 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2012 2013 return smc->update_dt_enabled; 2014 } 2015 2016 static int spapr_dtb_pre_load(void *opaque) 2017 { 2018 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 2019 2020 g_free(spapr->fdt_blob); 2021 spapr->fdt_blob = NULL; 2022 spapr->fdt_size = 0; 2023 2024 return 0; 2025 } 2026 2027 static const VMStateDescription vmstate_spapr_dtb = { 2028 .name = "spapr_dtb", 2029 .version_id = 1, 2030 .minimum_version_id = 1, 2031 .needed = spapr_dtb_needed, 2032 .pre_load = spapr_dtb_pre_load, 2033 .fields = (VMStateField[]) { 2034 VMSTATE_UINT32(fdt_initial_size, sPAPRMachineState), 2035 VMSTATE_UINT32(fdt_size, sPAPRMachineState), 2036 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, sPAPRMachineState, 0, NULL, 2037 fdt_size), 2038 VMSTATE_END_OF_LIST() 2039 }, 2040 }; 2041 2042 static const VMStateDescription vmstate_spapr = { 2043 .name = "spapr", 2044 .version_id = 3, 2045 .minimum_version_id = 1, 2046 .pre_load = spapr_pre_load, 2047 .post_load = spapr_post_load, 2048 .pre_save = spapr_pre_save, 2049 .fields = (VMStateField[]) { 2050 /* used to be @next_irq */ 2051 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2052 2053 /* RTC offset */ 2054 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 2055 2056 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 2057 VMSTATE_END_OF_LIST() 2058 }, 2059 .subsections = (const VMStateDescription*[]) { 2060 &vmstate_spapr_ov5_cas, 2061 &vmstate_spapr_patb_entry, 2062 &vmstate_spapr_pending_events, 2063 &vmstate_spapr_cap_htm, 2064 &vmstate_spapr_cap_vsx, 2065 &vmstate_spapr_cap_dfp, 2066 &vmstate_spapr_cap_cfpc, 2067 &vmstate_spapr_cap_sbbc, 2068 &vmstate_spapr_cap_ibs, 2069 &vmstate_spapr_irq_map, 2070 &vmstate_spapr_cap_nested_kvm_hv, 2071 &vmstate_spapr_dtb, 2072 NULL 2073 } 2074 }; 2075 2076 static int htab_save_setup(QEMUFile *f, void *opaque) 2077 { 2078 sPAPRMachineState *spapr = opaque; 2079 2080 /* "Iteration" header */ 2081 if (!spapr->htab_shift) { 2082 qemu_put_be32(f, -1); 2083 } else { 2084 qemu_put_be32(f, spapr->htab_shift); 2085 } 2086 2087 if (spapr->htab) { 2088 spapr->htab_save_index = 0; 2089 spapr->htab_first_pass = true; 2090 } else { 2091 if (spapr->htab_shift) { 2092 assert(kvm_enabled()); 2093 } 2094 } 2095 2096 2097 return 0; 2098 } 2099 2100 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 2101 int chunkstart, int n_valid, int n_invalid) 2102 { 2103 qemu_put_be32(f, chunkstart); 2104 qemu_put_be16(f, n_valid); 2105 qemu_put_be16(f, n_invalid); 2106 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2107 HASH_PTE_SIZE_64 * n_valid); 2108 } 2109 2110 static void htab_save_end_marker(QEMUFile *f) 2111 { 2112 qemu_put_be32(f, 0); 2113 qemu_put_be16(f, 0); 2114 qemu_put_be16(f, 0); 2115 } 2116 2117 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 2118 int64_t max_ns) 2119 { 2120 bool has_timeout = max_ns != -1; 2121 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2122 int index = spapr->htab_save_index; 2123 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2124 2125 assert(spapr->htab_first_pass); 2126 2127 do { 2128 int chunkstart; 2129 2130 /* Consume invalid HPTEs */ 2131 while ((index < htabslots) 2132 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 } 2136 2137 /* Consume valid HPTEs */ 2138 chunkstart = index; 2139 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2140 && HPTE_VALID(HPTE(spapr->htab, index))) { 2141 CLEAN_HPTE(HPTE(spapr->htab, index)); 2142 index++; 2143 } 2144 2145 if (index > chunkstart) { 2146 int n_valid = index - chunkstart; 2147 2148 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2149 2150 if (has_timeout && 2151 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2152 break; 2153 } 2154 } 2155 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2156 2157 if (index >= htabslots) { 2158 assert(index == htabslots); 2159 index = 0; 2160 spapr->htab_first_pass = false; 2161 } 2162 spapr->htab_save_index = index; 2163 } 2164 2165 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2166 int64_t max_ns) 2167 { 2168 bool final = max_ns < 0; 2169 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2170 int examined = 0, sent = 0; 2171 int index = spapr->htab_save_index; 2172 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2173 2174 assert(!spapr->htab_first_pass); 2175 2176 do { 2177 int chunkstart, invalidstart; 2178 2179 /* Consume non-dirty HPTEs */ 2180 while ((index < htabslots) 2181 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2182 index++; 2183 examined++; 2184 } 2185 2186 chunkstart = index; 2187 /* Consume valid dirty HPTEs */ 2188 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2189 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2190 && HPTE_VALID(HPTE(spapr->htab, index))) { 2191 CLEAN_HPTE(HPTE(spapr->htab, index)); 2192 index++; 2193 examined++; 2194 } 2195 2196 invalidstart = index; 2197 /* Consume invalid dirty HPTEs */ 2198 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2199 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2200 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2201 CLEAN_HPTE(HPTE(spapr->htab, index)); 2202 index++; 2203 examined++; 2204 } 2205 2206 if (index > chunkstart) { 2207 int n_valid = invalidstart - chunkstart; 2208 int n_invalid = index - invalidstart; 2209 2210 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2211 sent += index - chunkstart; 2212 2213 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2214 break; 2215 } 2216 } 2217 2218 if (examined >= htabslots) { 2219 break; 2220 } 2221 2222 if (index >= htabslots) { 2223 assert(index == htabslots); 2224 index = 0; 2225 } 2226 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2227 2228 if (index >= htabslots) { 2229 assert(index == htabslots); 2230 index = 0; 2231 } 2232 2233 spapr->htab_save_index = index; 2234 2235 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2236 } 2237 2238 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2239 #define MAX_KVM_BUF_SIZE 2048 2240 2241 static int htab_save_iterate(QEMUFile *f, void *opaque) 2242 { 2243 sPAPRMachineState *spapr = opaque; 2244 int fd; 2245 int rc = 0; 2246 2247 /* Iteration header */ 2248 if (!spapr->htab_shift) { 2249 qemu_put_be32(f, -1); 2250 return 1; 2251 } else { 2252 qemu_put_be32(f, 0); 2253 } 2254 2255 if (!spapr->htab) { 2256 assert(kvm_enabled()); 2257 2258 fd = get_htab_fd(spapr); 2259 if (fd < 0) { 2260 return fd; 2261 } 2262 2263 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2264 if (rc < 0) { 2265 return rc; 2266 } 2267 } else if (spapr->htab_first_pass) { 2268 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2269 } else { 2270 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2271 } 2272 2273 htab_save_end_marker(f); 2274 2275 return rc; 2276 } 2277 2278 static int htab_save_complete(QEMUFile *f, void *opaque) 2279 { 2280 sPAPRMachineState *spapr = opaque; 2281 int fd; 2282 2283 /* Iteration header */ 2284 if (!spapr->htab_shift) { 2285 qemu_put_be32(f, -1); 2286 return 0; 2287 } else { 2288 qemu_put_be32(f, 0); 2289 } 2290 2291 if (!spapr->htab) { 2292 int rc; 2293 2294 assert(kvm_enabled()); 2295 2296 fd = get_htab_fd(spapr); 2297 if (fd < 0) { 2298 return fd; 2299 } 2300 2301 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2302 if (rc < 0) { 2303 return rc; 2304 } 2305 } else { 2306 if (spapr->htab_first_pass) { 2307 htab_save_first_pass(f, spapr, -1); 2308 } 2309 htab_save_later_pass(f, spapr, -1); 2310 } 2311 2312 /* End marker */ 2313 htab_save_end_marker(f); 2314 2315 return 0; 2316 } 2317 2318 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2319 { 2320 sPAPRMachineState *spapr = opaque; 2321 uint32_t section_hdr; 2322 int fd = -1; 2323 Error *local_err = NULL; 2324 2325 if (version_id < 1 || version_id > 1) { 2326 error_report("htab_load() bad version"); 2327 return -EINVAL; 2328 } 2329 2330 section_hdr = qemu_get_be32(f); 2331 2332 if (section_hdr == -1) { 2333 spapr_free_hpt(spapr); 2334 return 0; 2335 } 2336 2337 if (section_hdr) { 2338 /* First section gives the htab size */ 2339 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2340 if (local_err) { 2341 error_report_err(local_err); 2342 return -EINVAL; 2343 } 2344 return 0; 2345 } 2346 2347 if (!spapr->htab) { 2348 assert(kvm_enabled()); 2349 2350 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2351 if (fd < 0) { 2352 error_report_err(local_err); 2353 return fd; 2354 } 2355 } 2356 2357 while (true) { 2358 uint32_t index; 2359 uint16_t n_valid, n_invalid; 2360 2361 index = qemu_get_be32(f); 2362 n_valid = qemu_get_be16(f); 2363 n_invalid = qemu_get_be16(f); 2364 2365 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2366 /* End of Stream */ 2367 break; 2368 } 2369 2370 if ((index + n_valid + n_invalid) > 2371 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2372 /* Bad index in stream */ 2373 error_report( 2374 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2375 index, n_valid, n_invalid, spapr->htab_shift); 2376 return -EINVAL; 2377 } 2378 2379 if (spapr->htab) { 2380 if (n_valid) { 2381 qemu_get_buffer(f, HPTE(spapr->htab, index), 2382 HASH_PTE_SIZE_64 * n_valid); 2383 } 2384 if (n_invalid) { 2385 memset(HPTE(spapr->htab, index + n_valid), 0, 2386 HASH_PTE_SIZE_64 * n_invalid); 2387 } 2388 } else { 2389 int rc; 2390 2391 assert(fd >= 0); 2392 2393 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2394 if (rc < 0) { 2395 return rc; 2396 } 2397 } 2398 } 2399 2400 if (!spapr->htab) { 2401 assert(fd >= 0); 2402 close(fd); 2403 } 2404 2405 return 0; 2406 } 2407 2408 static void htab_save_cleanup(void *opaque) 2409 { 2410 sPAPRMachineState *spapr = opaque; 2411 2412 close_htab_fd(spapr); 2413 } 2414 2415 static SaveVMHandlers savevm_htab_handlers = { 2416 .save_setup = htab_save_setup, 2417 .save_live_iterate = htab_save_iterate, 2418 .save_live_complete_precopy = htab_save_complete, 2419 .save_cleanup = htab_save_cleanup, 2420 .load_state = htab_load, 2421 }; 2422 2423 static void spapr_boot_set(void *opaque, const char *boot_device, 2424 Error **errp) 2425 { 2426 MachineState *machine = MACHINE(opaque); 2427 machine->boot_order = g_strdup(boot_device); 2428 } 2429 2430 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2431 { 2432 MachineState *machine = MACHINE(spapr); 2433 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2434 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2435 int i; 2436 2437 for (i = 0; i < nr_lmbs; i++) { 2438 uint64_t addr; 2439 2440 addr = i * lmb_size + machine->device_memory->base; 2441 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2442 addr / lmb_size); 2443 } 2444 } 2445 2446 /* 2447 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2448 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2449 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2450 */ 2451 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2452 { 2453 int i; 2454 2455 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2456 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2457 " is not aligned to %" PRIu64 " MiB", 2458 machine->ram_size, 2459 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2460 return; 2461 } 2462 2463 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2464 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2465 " is not aligned to %" PRIu64 " MiB", 2466 machine->ram_size, 2467 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2468 return; 2469 } 2470 2471 for (i = 0; i < nb_numa_nodes; i++) { 2472 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2473 error_setg(errp, 2474 "Node %d memory size 0x%" PRIx64 2475 " is not aligned to %" PRIu64 " MiB", 2476 i, numa_info[i].node_mem, 2477 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2478 return; 2479 } 2480 } 2481 } 2482 2483 /* find cpu slot in machine->possible_cpus by core_id */ 2484 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2485 { 2486 int index = id / smp_threads; 2487 2488 if (index >= ms->possible_cpus->len) { 2489 return NULL; 2490 } 2491 if (idx) { 2492 *idx = index; 2493 } 2494 return &ms->possible_cpus->cpus[index]; 2495 } 2496 2497 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2498 { 2499 Error *local_err = NULL; 2500 bool vsmt_user = !!spapr->vsmt; 2501 int kvm_smt = kvmppc_smt_threads(); 2502 int ret; 2503 2504 if (!kvm_enabled() && (smp_threads > 1)) { 2505 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2506 "on a pseries machine"); 2507 goto out; 2508 } 2509 if (!is_power_of_2(smp_threads)) { 2510 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2511 "machine because it must be a power of 2", smp_threads); 2512 goto out; 2513 } 2514 2515 /* Detemine the VSMT mode to use: */ 2516 if (vsmt_user) { 2517 if (spapr->vsmt < smp_threads) { 2518 error_setg(&local_err, "Cannot support VSMT mode %d" 2519 " because it must be >= threads/core (%d)", 2520 spapr->vsmt, smp_threads); 2521 goto out; 2522 } 2523 /* In this case, spapr->vsmt has been set by the command line */ 2524 } else { 2525 /* 2526 * Default VSMT value is tricky, because we need it to be as 2527 * consistent as possible (for migration), but this requires 2528 * changing it for at least some existing cases. We pick 8 as 2529 * the value that we'd get with KVM on POWER8, the 2530 * overwhelmingly common case in production systems. 2531 */ 2532 spapr->vsmt = MAX(8, smp_threads); 2533 } 2534 2535 /* KVM: If necessary, set the SMT mode: */ 2536 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2537 ret = kvmppc_set_smt_threads(spapr->vsmt); 2538 if (ret) { 2539 /* Looks like KVM isn't able to change VSMT mode */ 2540 error_setg(&local_err, 2541 "Failed to set KVM's VSMT mode to %d (errno %d)", 2542 spapr->vsmt, ret); 2543 /* We can live with that if the default one is big enough 2544 * for the number of threads, and a submultiple of the one 2545 * we want. In this case we'll waste some vcpu ids, but 2546 * behaviour will be correct */ 2547 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2548 warn_report_err(local_err); 2549 local_err = NULL; 2550 goto out; 2551 } else { 2552 if (!vsmt_user) { 2553 error_append_hint(&local_err, 2554 "On PPC, a VM with %d threads/core" 2555 " on a host with %d threads/core" 2556 " requires the use of VSMT mode %d.\n", 2557 smp_threads, kvm_smt, spapr->vsmt); 2558 } 2559 kvmppc_hint_smt_possible(&local_err); 2560 goto out; 2561 } 2562 } 2563 } 2564 /* else TCG: nothing to do currently */ 2565 out: 2566 error_propagate(errp, local_err); 2567 } 2568 2569 static void spapr_init_cpus(sPAPRMachineState *spapr) 2570 { 2571 MachineState *machine = MACHINE(spapr); 2572 MachineClass *mc = MACHINE_GET_CLASS(machine); 2573 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2574 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2575 const CPUArchIdList *possible_cpus; 2576 int boot_cores_nr = smp_cpus / smp_threads; 2577 int i; 2578 2579 possible_cpus = mc->possible_cpu_arch_ids(machine); 2580 if (mc->has_hotpluggable_cpus) { 2581 if (smp_cpus % smp_threads) { 2582 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2583 smp_cpus, smp_threads); 2584 exit(1); 2585 } 2586 if (max_cpus % smp_threads) { 2587 error_report("max_cpus (%u) must be multiple of threads (%u)", 2588 max_cpus, smp_threads); 2589 exit(1); 2590 } 2591 } else { 2592 if (max_cpus != smp_cpus) { 2593 error_report("This machine version does not support CPU hotplug"); 2594 exit(1); 2595 } 2596 boot_cores_nr = possible_cpus->len; 2597 } 2598 2599 if (smc->pre_2_10_has_unused_icps) { 2600 int i; 2601 2602 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2603 /* Dummy entries get deregistered when real ICPState objects 2604 * are registered during CPU core hotplug. 2605 */ 2606 pre_2_10_vmstate_register_dummy_icp(i); 2607 } 2608 } 2609 2610 for (i = 0; i < possible_cpus->len; i++) { 2611 int core_id = i * smp_threads; 2612 2613 if (mc->has_hotpluggable_cpus) { 2614 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2615 spapr_vcpu_id(spapr, core_id)); 2616 } 2617 2618 if (i < boot_cores_nr) { 2619 Object *core = object_new(type); 2620 int nr_threads = smp_threads; 2621 2622 /* Handle the partially filled core for older machine types */ 2623 if ((i + 1) * smp_threads >= smp_cpus) { 2624 nr_threads = smp_cpus - i * smp_threads; 2625 } 2626 2627 object_property_set_int(core, nr_threads, "nr-threads", 2628 &error_fatal); 2629 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2630 &error_fatal); 2631 object_property_set_bool(core, true, "realized", &error_fatal); 2632 2633 object_unref(core); 2634 } 2635 } 2636 } 2637 2638 static PCIHostState *spapr_create_default_phb(void) 2639 { 2640 DeviceState *dev; 2641 2642 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2643 qdev_prop_set_uint32(dev, "index", 0); 2644 qdev_init_nofail(dev); 2645 2646 return PCI_HOST_BRIDGE(dev); 2647 } 2648 2649 /* pSeries LPAR / sPAPR hardware init */ 2650 static void spapr_machine_init(MachineState *machine) 2651 { 2652 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2653 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2654 const char *kernel_filename = machine->kernel_filename; 2655 const char *initrd_filename = machine->initrd_filename; 2656 PCIHostState *phb; 2657 int i; 2658 MemoryRegion *sysmem = get_system_memory(); 2659 MemoryRegion *ram = g_new(MemoryRegion, 1); 2660 hwaddr node0_size = spapr_node0_size(machine); 2661 long load_limit, fw_size; 2662 char *filename; 2663 Error *resize_hpt_err = NULL; 2664 2665 msi_nonbroken = true; 2666 2667 QLIST_INIT(&spapr->phbs); 2668 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2669 2670 /* Determine capabilities to run with */ 2671 spapr_caps_init(spapr); 2672 2673 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2674 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2675 /* 2676 * If the user explicitly requested a mode we should either 2677 * supply it, or fail completely (which we do below). But if 2678 * it's not set explicitly, we reset our mode to something 2679 * that works 2680 */ 2681 if (resize_hpt_err) { 2682 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2683 error_free(resize_hpt_err); 2684 resize_hpt_err = NULL; 2685 } else { 2686 spapr->resize_hpt = smc->resize_hpt_default; 2687 } 2688 } 2689 2690 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2691 2692 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2693 /* 2694 * User requested HPT resize, but this host can't supply it. Bail out 2695 */ 2696 error_report_err(resize_hpt_err); 2697 exit(1); 2698 } 2699 2700 spapr->rma_size = node0_size; 2701 2702 /* With KVM, we don't actually know whether KVM supports an 2703 * unbounded RMA (PR KVM) or is limited by the hash table size 2704 * (HV KVM using VRMA), so we always assume the latter 2705 * 2706 * In that case, we also limit the initial allocations for RTAS 2707 * etc... to 256M since we have no way to know what the VRMA size 2708 * is going to be as it depends on the size of the hash table 2709 * which isn't determined yet. 2710 */ 2711 if (kvm_enabled()) { 2712 spapr->vrma_adjust = 1; 2713 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2714 } 2715 2716 /* Actually we don't support unbounded RMA anymore since we added 2717 * proper emulation of HV mode. The max we can get is 16G which 2718 * also happens to be what we configure for PAPR mode so make sure 2719 * we don't do anything bigger than that 2720 */ 2721 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2722 2723 if (spapr->rma_size > node0_size) { 2724 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2725 spapr->rma_size); 2726 exit(1); 2727 } 2728 2729 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2730 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2731 2732 /* 2733 * VSMT must be set in order to be able to compute VCPU ids, ie to 2734 * call spapr_max_server_number() or spapr_vcpu_id(). 2735 */ 2736 spapr_set_vsmt_mode(spapr, &error_fatal); 2737 2738 /* Set up Interrupt Controller before we create the VCPUs */ 2739 spapr_irq_init(spapr, &error_fatal); 2740 2741 /* Set up containers for ibm,client-architecture-support negotiated options 2742 */ 2743 spapr->ov5 = spapr_ovec_new(); 2744 spapr->ov5_cas = spapr_ovec_new(); 2745 2746 if (smc->dr_lmb_enabled) { 2747 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2748 spapr_validate_node_memory(machine, &error_fatal); 2749 } 2750 2751 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2752 2753 /* advertise support for dedicated HP event source to guests */ 2754 if (spapr->use_hotplug_event_source) { 2755 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2756 } 2757 2758 /* advertise support for HPT resizing */ 2759 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2760 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2761 } 2762 2763 /* advertise support for ibm,dyamic-memory-v2 */ 2764 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2765 2766 /* advertise XIVE on POWER9 machines */ 2767 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { 2768 if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 2769 0, spapr->max_compat_pvr)) { 2770 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2771 } else if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { 2772 error_report("XIVE-only machines require a POWER9 CPU"); 2773 exit(1); 2774 } 2775 } 2776 2777 /* init CPUs */ 2778 spapr_init_cpus(spapr); 2779 2780 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2781 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2782 spapr->max_compat_pvr)) { 2783 /* KVM and TCG always allow GTSE with radix... */ 2784 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2785 } 2786 /* ... but not with hash (currently). */ 2787 2788 if (kvm_enabled()) { 2789 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2790 kvmppc_enable_logical_ci_hcalls(); 2791 kvmppc_enable_set_mode_hcall(); 2792 2793 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2794 kvmppc_enable_clear_ref_mod_hcalls(); 2795 } 2796 2797 /* allocate RAM */ 2798 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2799 machine->ram_size); 2800 memory_region_add_subregion(sysmem, 0, ram); 2801 2802 /* always allocate the device memory information */ 2803 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2804 2805 /* initialize hotplug memory address space */ 2806 if (machine->ram_size < machine->maxram_size) { 2807 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2808 /* 2809 * Limit the number of hotpluggable memory slots to half the number 2810 * slots that KVM supports, leaving the other half for PCI and other 2811 * devices. However ensure that number of slots doesn't drop below 32. 2812 */ 2813 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2814 SPAPR_MAX_RAM_SLOTS; 2815 2816 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2817 max_memslots = SPAPR_MAX_RAM_SLOTS; 2818 } 2819 if (machine->ram_slots > max_memslots) { 2820 error_report("Specified number of memory slots %" 2821 PRIu64" exceeds max supported %d", 2822 machine->ram_slots, max_memslots); 2823 exit(1); 2824 } 2825 2826 machine->device_memory->base = ROUND_UP(machine->ram_size, 2827 SPAPR_DEVICE_MEM_ALIGN); 2828 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2829 "device-memory", device_mem_size); 2830 memory_region_add_subregion(sysmem, machine->device_memory->base, 2831 &machine->device_memory->mr); 2832 } 2833 2834 if (smc->dr_lmb_enabled) { 2835 spapr_create_lmb_dr_connectors(spapr); 2836 } 2837 2838 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2839 if (!filename) { 2840 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2841 exit(1); 2842 } 2843 spapr->rtas_size = get_image_size(filename); 2844 if (spapr->rtas_size < 0) { 2845 error_report("Could not get size of LPAR rtas '%s'", filename); 2846 exit(1); 2847 } 2848 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2849 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2850 error_report("Could not load LPAR rtas '%s'", filename); 2851 exit(1); 2852 } 2853 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2854 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2855 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2856 exit(1); 2857 } 2858 g_free(filename); 2859 2860 /* Set up RTAS event infrastructure */ 2861 spapr_events_init(spapr); 2862 2863 /* Set up the RTC RTAS interfaces */ 2864 spapr_rtc_create(spapr); 2865 2866 /* Set up VIO bus */ 2867 spapr->vio_bus = spapr_vio_bus_init(); 2868 2869 for (i = 0; i < serial_max_hds(); i++) { 2870 if (serial_hd(i)) { 2871 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2872 } 2873 } 2874 2875 /* We always have at least the nvram device on VIO */ 2876 spapr_create_nvram(spapr); 2877 2878 /* 2879 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2880 * connectors (described in root DT node's "ibm,drc-types" property) 2881 * are pre-initialized here. additional child connectors (such as 2882 * connectors for a PHBs PCI slots) are added as needed during their 2883 * parent's realization. 2884 */ 2885 if (smc->dr_phb_enabled) { 2886 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2887 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2888 } 2889 } 2890 2891 /* Set up PCI */ 2892 spapr_pci_rtas_init(); 2893 2894 phb = spapr_create_default_phb(); 2895 2896 for (i = 0; i < nb_nics; i++) { 2897 NICInfo *nd = &nd_table[i]; 2898 2899 if (!nd->model) { 2900 nd->model = g_strdup("spapr-vlan"); 2901 } 2902 2903 if (g_str_equal(nd->model, "spapr-vlan") || 2904 g_str_equal(nd->model, "ibmveth")) { 2905 spapr_vlan_create(spapr->vio_bus, nd); 2906 } else { 2907 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2908 } 2909 } 2910 2911 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2912 spapr_vscsi_create(spapr->vio_bus); 2913 } 2914 2915 /* Graphics */ 2916 if (spapr_vga_init(phb->bus, &error_fatal)) { 2917 spapr->has_graphics = true; 2918 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2919 } 2920 2921 if (machine->usb) { 2922 if (smc->use_ohci_by_default) { 2923 pci_create_simple(phb->bus, -1, "pci-ohci"); 2924 } else { 2925 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2926 } 2927 2928 if (spapr->has_graphics) { 2929 USBBus *usb_bus = usb_bus_find(-1); 2930 2931 usb_create_simple(usb_bus, "usb-kbd"); 2932 usb_create_simple(usb_bus, "usb-mouse"); 2933 } 2934 } 2935 2936 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2937 error_report( 2938 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2939 MIN_RMA_SLOF); 2940 exit(1); 2941 } 2942 2943 if (kernel_filename) { 2944 uint64_t lowaddr = 0; 2945 2946 spapr->kernel_size = load_elf(kernel_filename, NULL, 2947 translate_kernel_address, NULL, 2948 NULL, &lowaddr, NULL, 1, 2949 PPC_ELF_MACHINE, 0, 0); 2950 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2951 spapr->kernel_size = load_elf(kernel_filename, NULL, 2952 translate_kernel_address, NULL, NULL, 2953 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2954 0, 0); 2955 spapr->kernel_le = spapr->kernel_size > 0; 2956 } 2957 if (spapr->kernel_size < 0) { 2958 error_report("error loading %s: %s", kernel_filename, 2959 load_elf_strerror(spapr->kernel_size)); 2960 exit(1); 2961 } 2962 2963 /* load initrd */ 2964 if (initrd_filename) { 2965 /* Try to locate the initrd in the gap between the kernel 2966 * and the firmware. Add a bit of space just in case 2967 */ 2968 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2969 + 0x1ffff) & ~0xffff; 2970 spapr->initrd_size = load_image_targphys(initrd_filename, 2971 spapr->initrd_base, 2972 load_limit 2973 - spapr->initrd_base); 2974 if (spapr->initrd_size < 0) { 2975 error_report("could not load initial ram disk '%s'", 2976 initrd_filename); 2977 exit(1); 2978 } 2979 } 2980 } 2981 2982 if (bios_name == NULL) { 2983 bios_name = FW_FILE_NAME; 2984 } 2985 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2986 if (!filename) { 2987 error_report("Could not find LPAR firmware '%s'", bios_name); 2988 exit(1); 2989 } 2990 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2991 if (fw_size <= 0) { 2992 error_report("Could not load LPAR firmware '%s'", filename); 2993 exit(1); 2994 } 2995 g_free(filename); 2996 2997 /* FIXME: Should register things through the MachineState's qdev 2998 * interface, this is a legacy from the sPAPREnvironment structure 2999 * which predated MachineState but had a similar function */ 3000 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3001 register_savevm_live(NULL, "spapr/htab", -1, 1, 3002 &savevm_htab_handlers, spapr); 3003 3004 qemu_register_boot_set(spapr_boot_set, spapr); 3005 3006 if (kvm_enabled()) { 3007 /* to stop and start vmclock */ 3008 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3009 &spapr->tb); 3010 3011 kvmppc_spapr_enable_inkernel_multitce(); 3012 } 3013 } 3014 3015 static int spapr_kvm_type(const char *vm_type) 3016 { 3017 if (!vm_type) { 3018 return 0; 3019 } 3020 3021 if (!strcmp(vm_type, "HV")) { 3022 return 1; 3023 } 3024 3025 if (!strcmp(vm_type, "PR")) { 3026 return 2; 3027 } 3028 3029 error_report("Unknown kvm-type specified '%s'", vm_type); 3030 exit(1); 3031 } 3032 3033 /* 3034 * Implementation of an interface to adjust firmware path 3035 * for the bootindex property handling. 3036 */ 3037 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3038 DeviceState *dev) 3039 { 3040 #define CAST(type, obj, name) \ 3041 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3042 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3043 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3044 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3045 3046 if (d) { 3047 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3048 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3049 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3050 3051 if (spapr) { 3052 /* 3053 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3054 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3055 * 0x8000 | (target << 8) | (bus << 5) | lun 3056 * (see the "Logical unit addressing format" table in SAM5) 3057 */ 3058 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3059 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3060 (uint64_t)id << 48); 3061 } else if (virtio) { 3062 /* 3063 * We use SRP luns of the form 01000000 | (target << 8) | lun 3064 * in the top 32 bits of the 64-bit LUN 3065 * Note: the quote above is from SLOF and it is wrong, 3066 * the actual binding is: 3067 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3068 */ 3069 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3070 if (d->lun >= 256) { 3071 /* Use the LUN "flat space addressing method" */ 3072 id |= 0x4000; 3073 } 3074 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3075 (uint64_t)id << 32); 3076 } else if (usb) { 3077 /* 3078 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3079 * in the top 32 bits of the 64-bit LUN 3080 */ 3081 unsigned usb_port = atoi(usb->port->path); 3082 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3083 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3084 (uint64_t)id << 32); 3085 } 3086 } 3087 3088 /* 3089 * SLOF probes the USB devices, and if it recognizes that the device is a 3090 * storage device, it changes its name to "storage" instead of "usb-host", 3091 * and additionally adds a child node for the SCSI LUN, so the correct 3092 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3093 */ 3094 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3095 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3096 if (usb_host_dev_is_scsi_storage(usbdev)) { 3097 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3098 } 3099 } 3100 3101 if (phb) { 3102 /* Replace "pci" with "pci@800000020000000" */ 3103 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3104 } 3105 3106 if (vsc) { 3107 /* Same logic as virtio above */ 3108 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3109 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3110 } 3111 3112 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3113 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3114 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3115 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3116 } 3117 3118 return NULL; 3119 } 3120 3121 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3122 { 3123 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3124 3125 return g_strdup(spapr->kvm_type); 3126 } 3127 3128 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3129 { 3130 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3131 3132 g_free(spapr->kvm_type); 3133 spapr->kvm_type = g_strdup(value); 3134 } 3135 3136 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3137 { 3138 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3139 3140 return spapr->use_hotplug_event_source; 3141 } 3142 3143 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3144 Error **errp) 3145 { 3146 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3147 3148 spapr->use_hotplug_event_source = value; 3149 } 3150 3151 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3152 { 3153 return true; 3154 } 3155 3156 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3157 { 3158 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3159 3160 switch (spapr->resize_hpt) { 3161 case SPAPR_RESIZE_HPT_DEFAULT: 3162 return g_strdup("default"); 3163 case SPAPR_RESIZE_HPT_DISABLED: 3164 return g_strdup("disabled"); 3165 case SPAPR_RESIZE_HPT_ENABLED: 3166 return g_strdup("enabled"); 3167 case SPAPR_RESIZE_HPT_REQUIRED: 3168 return g_strdup("required"); 3169 } 3170 g_assert_not_reached(); 3171 } 3172 3173 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3174 { 3175 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 if (strcmp(value, "default") == 0) { 3178 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3179 } else if (strcmp(value, "disabled") == 0) { 3180 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3181 } else if (strcmp(value, "enabled") == 0) { 3182 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3183 } else if (strcmp(value, "required") == 0) { 3184 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3185 } else { 3186 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3187 } 3188 } 3189 3190 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3191 void *opaque, Error **errp) 3192 { 3193 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3194 } 3195 3196 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3197 void *opaque, Error **errp) 3198 { 3199 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3200 } 3201 3202 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3203 { 3204 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3205 3206 if (spapr->irq == &spapr_irq_xics_legacy) { 3207 return g_strdup("legacy"); 3208 } else if (spapr->irq == &spapr_irq_xics) { 3209 return g_strdup("xics"); 3210 } else if (spapr->irq == &spapr_irq_xive) { 3211 return g_strdup("xive"); 3212 } else if (spapr->irq == &spapr_irq_dual) { 3213 return g_strdup("dual"); 3214 } 3215 g_assert_not_reached(); 3216 } 3217 3218 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3219 { 3220 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3221 3222 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3223 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3224 return; 3225 } 3226 3227 /* The legacy IRQ backend can not be set */ 3228 if (strcmp(value, "xics") == 0) { 3229 spapr->irq = &spapr_irq_xics; 3230 } else if (strcmp(value, "xive") == 0) { 3231 spapr->irq = &spapr_irq_xive; 3232 } else if (strcmp(value, "dual") == 0) { 3233 spapr->irq = &spapr_irq_dual; 3234 } else { 3235 error_setg(errp, "Bad value for \"ic-mode\" property"); 3236 } 3237 } 3238 3239 static char *spapr_get_host_model(Object *obj, Error **errp) 3240 { 3241 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3242 3243 return g_strdup(spapr->host_model); 3244 } 3245 3246 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3247 { 3248 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3249 3250 g_free(spapr->host_model); 3251 spapr->host_model = g_strdup(value); 3252 } 3253 3254 static char *spapr_get_host_serial(Object *obj, Error **errp) 3255 { 3256 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3257 3258 return g_strdup(spapr->host_serial); 3259 } 3260 3261 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3262 { 3263 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3264 3265 g_free(spapr->host_serial); 3266 spapr->host_serial = g_strdup(value); 3267 } 3268 3269 static void spapr_instance_init(Object *obj) 3270 { 3271 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3272 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3273 3274 spapr->htab_fd = -1; 3275 spapr->use_hotplug_event_source = true; 3276 object_property_add_str(obj, "kvm-type", 3277 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3278 object_property_set_description(obj, "kvm-type", 3279 "Specifies the KVM virtualization mode (HV, PR)", 3280 NULL); 3281 object_property_add_bool(obj, "modern-hotplug-events", 3282 spapr_get_modern_hotplug_events, 3283 spapr_set_modern_hotplug_events, 3284 NULL); 3285 object_property_set_description(obj, "modern-hotplug-events", 3286 "Use dedicated hotplug event mechanism in" 3287 " place of standard EPOW events when possible" 3288 " (required for memory hot-unplug support)", 3289 NULL); 3290 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3291 "Maximum permitted CPU compatibility mode", 3292 &error_fatal); 3293 3294 object_property_add_str(obj, "resize-hpt", 3295 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3296 object_property_set_description(obj, "resize-hpt", 3297 "Resizing of the Hash Page Table (enabled, disabled, required)", 3298 NULL); 3299 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3300 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3301 object_property_set_description(obj, "vsmt", 3302 "Virtual SMT: KVM behaves as if this were" 3303 " the host's SMT mode", &error_abort); 3304 object_property_add_bool(obj, "vfio-no-msix-emulation", 3305 spapr_get_msix_emulation, NULL, NULL); 3306 3307 /* The machine class defines the default interrupt controller mode */ 3308 spapr->irq = smc->irq; 3309 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3310 spapr_set_ic_mode, NULL); 3311 object_property_set_description(obj, "ic-mode", 3312 "Specifies the interrupt controller mode (xics, xive, dual)", 3313 NULL); 3314 3315 object_property_add_str(obj, "host-model", 3316 spapr_get_host_model, spapr_set_host_model, 3317 &error_abort); 3318 object_property_set_description(obj, "host-model", 3319 "Set host's model-id to use - none|passthrough|string", &error_abort); 3320 object_property_add_str(obj, "host-serial", 3321 spapr_get_host_serial, spapr_set_host_serial, 3322 &error_abort); 3323 object_property_set_description(obj, "host-serial", 3324 "Set host's system-id to use - none|passthrough|string", &error_abort); 3325 } 3326 3327 static void spapr_machine_finalizefn(Object *obj) 3328 { 3329 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3330 3331 g_free(spapr->kvm_type); 3332 } 3333 3334 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3335 { 3336 cpu_synchronize_state(cs); 3337 ppc_cpu_do_system_reset(cs); 3338 } 3339 3340 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3341 { 3342 CPUState *cs; 3343 3344 CPU_FOREACH(cs) { 3345 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3346 } 3347 } 3348 3349 int spapr_lmb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 3350 void *fdt, int *fdt_start_offset, Error **errp) 3351 { 3352 uint64_t addr; 3353 uint32_t node; 3354 3355 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3356 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3357 &error_abort); 3358 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3359 SPAPR_MEMORY_BLOCK_SIZE); 3360 return 0; 3361 } 3362 3363 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3364 bool dedicated_hp_event_source, Error **errp) 3365 { 3366 sPAPRDRConnector *drc; 3367 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3368 int i; 3369 uint64_t addr = addr_start; 3370 bool hotplugged = spapr_drc_hotplugged(dev); 3371 Error *local_err = NULL; 3372 3373 for (i = 0; i < nr_lmbs; i++) { 3374 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3375 addr / SPAPR_MEMORY_BLOCK_SIZE); 3376 g_assert(drc); 3377 3378 spapr_drc_attach(drc, dev, &local_err); 3379 if (local_err) { 3380 while (addr > addr_start) { 3381 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3382 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3383 addr / SPAPR_MEMORY_BLOCK_SIZE); 3384 spapr_drc_detach(drc); 3385 } 3386 error_propagate(errp, local_err); 3387 return; 3388 } 3389 if (!hotplugged) { 3390 spapr_drc_reset(drc); 3391 } 3392 addr += SPAPR_MEMORY_BLOCK_SIZE; 3393 } 3394 /* send hotplug notification to the 3395 * guest only in case of hotplugged memory 3396 */ 3397 if (hotplugged) { 3398 if (dedicated_hp_event_source) { 3399 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3400 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3401 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3402 nr_lmbs, 3403 spapr_drc_index(drc)); 3404 } else { 3405 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3406 nr_lmbs); 3407 } 3408 } 3409 } 3410 3411 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3412 Error **errp) 3413 { 3414 Error *local_err = NULL; 3415 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3416 PCDIMMDevice *dimm = PC_DIMM(dev); 3417 uint64_t size, addr; 3418 3419 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3420 3421 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3422 if (local_err) { 3423 goto out; 3424 } 3425 3426 addr = object_property_get_uint(OBJECT(dimm), 3427 PC_DIMM_ADDR_PROP, &local_err); 3428 if (local_err) { 3429 goto out_unplug; 3430 } 3431 3432 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3433 &local_err); 3434 if (local_err) { 3435 goto out_unplug; 3436 } 3437 3438 return; 3439 3440 out_unplug: 3441 pc_dimm_unplug(dimm, MACHINE(ms)); 3442 out: 3443 error_propagate(errp, local_err); 3444 } 3445 3446 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3447 Error **errp) 3448 { 3449 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3450 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3451 PCDIMMDevice *dimm = PC_DIMM(dev); 3452 Error *local_err = NULL; 3453 uint64_t size; 3454 Object *memdev; 3455 hwaddr pagesize; 3456 3457 if (!smc->dr_lmb_enabled) { 3458 error_setg(errp, "Memory hotplug not supported for this machine"); 3459 return; 3460 } 3461 3462 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3463 if (local_err) { 3464 error_propagate(errp, local_err); 3465 return; 3466 } 3467 3468 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3469 error_setg(errp, "Hotplugged memory size must be a multiple of " 3470 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3471 return; 3472 } 3473 3474 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3475 &error_abort); 3476 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3477 spapr_check_pagesize(spapr, pagesize, &local_err); 3478 if (local_err) { 3479 error_propagate(errp, local_err); 3480 return; 3481 } 3482 3483 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3484 } 3485 3486 struct sPAPRDIMMState { 3487 PCDIMMDevice *dimm; 3488 uint32_t nr_lmbs; 3489 QTAILQ_ENTRY(sPAPRDIMMState) next; 3490 }; 3491 3492 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3493 PCDIMMDevice *dimm) 3494 { 3495 sPAPRDIMMState *dimm_state = NULL; 3496 3497 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3498 if (dimm_state->dimm == dimm) { 3499 break; 3500 } 3501 } 3502 return dimm_state; 3503 } 3504 3505 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3506 uint32_t nr_lmbs, 3507 PCDIMMDevice *dimm) 3508 { 3509 sPAPRDIMMState *ds = NULL; 3510 3511 /* 3512 * If this request is for a DIMM whose removal had failed earlier 3513 * (due to guest's refusal to remove the LMBs), we would have this 3514 * dimm already in the pending_dimm_unplugs list. In that 3515 * case don't add again. 3516 */ 3517 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3518 if (!ds) { 3519 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3520 ds->nr_lmbs = nr_lmbs; 3521 ds->dimm = dimm; 3522 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3523 } 3524 return ds; 3525 } 3526 3527 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3528 sPAPRDIMMState *dimm_state) 3529 { 3530 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3531 g_free(dimm_state); 3532 } 3533 3534 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3535 PCDIMMDevice *dimm) 3536 { 3537 sPAPRDRConnector *drc; 3538 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3539 &error_abort); 3540 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3541 uint32_t avail_lmbs = 0; 3542 uint64_t addr_start, addr; 3543 int i; 3544 3545 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3546 &error_abort); 3547 3548 addr = addr_start; 3549 for (i = 0; i < nr_lmbs; i++) { 3550 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3551 addr / SPAPR_MEMORY_BLOCK_SIZE); 3552 g_assert(drc); 3553 if (drc->dev) { 3554 avail_lmbs++; 3555 } 3556 addr += SPAPR_MEMORY_BLOCK_SIZE; 3557 } 3558 3559 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3560 } 3561 3562 /* Callback to be called during DRC release. */ 3563 void spapr_lmb_release(DeviceState *dev) 3564 { 3565 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3566 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3567 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3568 3569 /* This information will get lost if a migration occurs 3570 * during the unplug process. In this case recover it. */ 3571 if (ds == NULL) { 3572 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3573 g_assert(ds); 3574 /* The DRC being examined by the caller at least must be counted */ 3575 g_assert(ds->nr_lmbs); 3576 } 3577 3578 if (--ds->nr_lmbs) { 3579 return; 3580 } 3581 3582 /* 3583 * Now that all the LMBs have been removed by the guest, call the 3584 * unplug handler chain. This can never fail. 3585 */ 3586 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3587 } 3588 3589 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3590 { 3591 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3592 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3593 3594 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3595 object_unparent(OBJECT(dev)); 3596 spapr_pending_dimm_unplugs_remove(spapr, ds); 3597 } 3598 3599 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3600 DeviceState *dev, Error **errp) 3601 { 3602 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3603 Error *local_err = NULL; 3604 PCDIMMDevice *dimm = PC_DIMM(dev); 3605 uint32_t nr_lmbs; 3606 uint64_t size, addr_start, addr; 3607 int i; 3608 sPAPRDRConnector *drc; 3609 3610 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3611 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3612 3613 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3614 &local_err); 3615 if (local_err) { 3616 goto out; 3617 } 3618 3619 /* 3620 * An existing pending dimm state for this DIMM means that there is an 3621 * unplug operation in progress, waiting for the spapr_lmb_release 3622 * callback to complete the job (BQL can't cover that far). In this case, 3623 * bail out to avoid detaching DRCs that were already released. 3624 */ 3625 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3626 error_setg(&local_err, 3627 "Memory unplug already in progress for device %s", 3628 dev->id); 3629 goto out; 3630 } 3631 3632 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3633 3634 addr = addr_start; 3635 for (i = 0; i < nr_lmbs; i++) { 3636 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3637 addr / SPAPR_MEMORY_BLOCK_SIZE); 3638 g_assert(drc); 3639 3640 spapr_drc_detach(drc); 3641 addr += SPAPR_MEMORY_BLOCK_SIZE; 3642 } 3643 3644 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3645 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3646 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3647 nr_lmbs, spapr_drc_index(drc)); 3648 out: 3649 error_propagate(errp, local_err); 3650 } 3651 3652 /* Callback to be called during DRC release. */ 3653 void spapr_core_release(DeviceState *dev) 3654 { 3655 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3656 3657 /* Call the unplug handler chain. This can never fail. */ 3658 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3659 } 3660 3661 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3662 { 3663 MachineState *ms = MACHINE(hotplug_dev); 3664 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3665 CPUCore *cc = CPU_CORE(dev); 3666 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3667 3668 if (smc->pre_2_10_has_unused_icps) { 3669 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3670 int i; 3671 3672 for (i = 0; i < cc->nr_threads; i++) { 3673 CPUState *cs = CPU(sc->threads[i]); 3674 3675 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3676 } 3677 } 3678 3679 assert(core_slot); 3680 core_slot->cpu = NULL; 3681 object_unparent(OBJECT(dev)); 3682 } 3683 3684 static 3685 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3686 Error **errp) 3687 { 3688 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3689 int index; 3690 sPAPRDRConnector *drc; 3691 CPUCore *cc = CPU_CORE(dev); 3692 3693 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3694 error_setg(errp, "Unable to find CPU core with core-id: %d", 3695 cc->core_id); 3696 return; 3697 } 3698 if (index == 0) { 3699 error_setg(errp, "Boot CPU core may not be unplugged"); 3700 return; 3701 } 3702 3703 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3704 spapr_vcpu_id(spapr, cc->core_id)); 3705 g_assert(drc); 3706 3707 spapr_drc_detach(drc); 3708 3709 spapr_hotplug_req_remove_by_index(drc); 3710 } 3711 3712 int spapr_core_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 3713 void *fdt, int *fdt_start_offset, Error **errp) 3714 { 3715 sPAPRCPUCore *core = SPAPR_CPU_CORE(drc->dev); 3716 CPUState *cs = CPU(core->threads[0]); 3717 PowerPCCPU *cpu = POWERPC_CPU(cs); 3718 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3719 int id = spapr_get_vcpu_id(cpu); 3720 char *nodename; 3721 int offset; 3722 3723 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3724 offset = fdt_add_subnode(fdt, 0, nodename); 3725 g_free(nodename); 3726 3727 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3728 3729 *fdt_start_offset = offset; 3730 return 0; 3731 } 3732 3733 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3734 Error **errp) 3735 { 3736 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3737 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3738 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3739 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3740 CPUCore *cc = CPU_CORE(dev); 3741 CPUState *cs; 3742 sPAPRDRConnector *drc; 3743 Error *local_err = NULL; 3744 CPUArchId *core_slot; 3745 int index; 3746 bool hotplugged = spapr_drc_hotplugged(dev); 3747 3748 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3749 if (!core_slot) { 3750 error_setg(errp, "Unable to find CPU core with core-id: %d", 3751 cc->core_id); 3752 return; 3753 } 3754 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3755 spapr_vcpu_id(spapr, cc->core_id)); 3756 3757 g_assert(drc || !mc->has_hotpluggable_cpus); 3758 3759 if (drc) { 3760 spapr_drc_attach(drc, dev, &local_err); 3761 if (local_err) { 3762 error_propagate(errp, local_err); 3763 return; 3764 } 3765 3766 if (hotplugged) { 3767 /* 3768 * Send hotplug notification interrupt to the guest only 3769 * in case of hotplugged CPUs. 3770 */ 3771 spapr_hotplug_req_add_by_index(drc); 3772 } else { 3773 spapr_drc_reset(drc); 3774 } 3775 } 3776 3777 core_slot->cpu = OBJECT(dev); 3778 3779 if (smc->pre_2_10_has_unused_icps) { 3780 int i; 3781 3782 for (i = 0; i < cc->nr_threads; i++) { 3783 cs = CPU(core->threads[i]); 3784 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3785 } 3786 } 3787 } 3788 3789 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3790 Error **errp) 3791 { 3792 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3793 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3794 Error *local_err = NULL; 3795 CPUCore *cc = CPU_CORE(dev); 3796 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3797 const char *type = object_get_typename(OBJECT(dev)); 3798 CPUArchId *core_slot; 3799 int index; 3800 3801 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3802 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3803 goto out; 3804 } 3805 3806 if (strcmp(base_core_type, type)) { 3807 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3808 goto out; 3809 } 3810 3811 if (cc->core_id % smp_threads) { 3812 error_setg(&local_err, "invalid core id %d", cc->core_id); 3813 goto out; 3814 } 3815 3816 /* 3817 * In general we should have homogeneous threads-per-core, but old 3818 * (pre hotplug support) machine types allow the last core to have 3819 * reduced threads as a compatibility hack for when we allowed 3820 * total vcpus not a multiple of threads-per-core. 3821 */ 3822 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3823 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3824 cc->nr_threads, smp_threads); 3825 goto out; 3826 } 3827 3828 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3829 if (!core_slot) { 3830 error_setg(&local_err, "core id %d out of range", cc->core_id); 3831 goto out; 3832 } 3833 3834 if (core_slot->cpu) { 3835 error_setg(&local_err, "core %d already populated", cc->core_id); 3836 goto out; 3837 } 3838 3839 numa_cpu_pre_plug(core_slot, dev, &local_err); 3840 3841 out: 3842 error_propagate(errp, local_err); 3843 } 3844 3845 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3846 DeviceState *dev, Error **errp) 3847 { 3848 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3849 spapr_memory_plug(hotplug_dev, dev, errp); 3850 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3851 spapr_core_plug(hotplug_dev, dev, errp); 3852 } 3853 } 3854 3855 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3856 DeviceState *dev, Error **errp) 3857 { 3858 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3859 spapr_memory_unplug(hotplug_dev, dev); 3860 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3861 spapr_core_unplug(hotplug_dev, dev); 3862 } 3863 } 3864 3865 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3866 DeviceState *dev, Error **errp) 3867 { 3868 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3869 MachineClass *mc = MACHINE_GET_CLASS(sms); 3870 3871 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3872 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3873 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3874 } else { 3875 /* NOTE: this means there is a window after guest reset, prior to 3876 * CAS negotiation, where unplug requests will fail due to the 3877 * capability not being detected yet. This is a bit different than 3878 * the case with PCI unplug, where the events will be queued and 3879 * eventually handled by the guest after boot 3880 */ 3881 error_setg(errp, "Memory hot unplug not supported for this guest"); 3882 } 3883 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3884 if (!mc->has_hotpluggable_cpus) { 3885 error_setg(errp, "CPU hot unplug not supported on this machine"); 3886 return; 3887 } 3888 spapr_core_unplug_request(hotplug_dev, dev, errp); 3889 } 3890 } 3891 3892 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3893 DeviceState *dev, Error **errp) 3894 { 3895 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3896 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3897 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3898 spapr_core_pre_plug(hotplug_dev, dev, errp); 3899 } 3900 } 3901 3902 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3903 DeviceState *dev) 3904 { 3905 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3906 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3907 return HOTPLUG_HANDLER(machine); 3908 } 3909 return NULL; 3910 } 3911 3912 static CpuInstanceProperties 3913 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3914 { 3915 CPUArchId *core_slot; 3916 MachineClass *mc = MACHINE_GET_CLASS(machine); 3917 3918 /* make sure possible_cpu are intialized */ 3919 mc->possible_cpu_arch_ids(machine); 3920 /* get CPU core slot containing thread that matches cpu_index */ 3921 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3922 assert(core_slot); 3923 return core_slot->props; 3924 } 3925 3926 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3927 { 3928 return idx / smp_cores % nb_numa_nodes; 3929 } 3930 3931 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3932 { 3933 int i; 3934 const char *core_type; 3935 int spapr_max_cores = max_cpus / smp_threads; 3936 MachineClass *mc = MACHINE_GET_CLASS(machine); 3937 3938 if (!mc->has_hotpluggable_cpus) { 3939 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3940 } 3941 if (machine->possible_cpus) { 3942 assert(machine->possible_cpus->len == spapr_max_cores); 3943 return machine->possible_cpus; 3944 } 3945 3946 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3947 if (!core_type) { 3948 error_report("Unable to find sPAPR CPU Core definition"); 3949 exit(1); 3950 } 3951 3952 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3953 sizeof(CPUArchId) * spapr_max_cores); 3954 machine->possible_cpus->len = spapr_max_cores; 3955 for (i = 0; i < machine->possible_cpus->len; i++) { 3956 int core_id = i * smp_threads; 3957 3958 machine->possible_cpus->cpus[i].type = core_type; 3959 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3960 machine->possible_cpus->cpus[i].arch_id = core_id; 3961 machine->possible_cpus->cpus[i].props.has_core_id = true; 3962 machine->possible_cpus->cpus[i].props.core_id = core_id; 3963 } 3964 return machine->possible_cpus; 3965 } 3966 3967 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3968 uint64_t *buid, hwaddr *pio, 3969 hwaddr *mmio32, hwaddr *mmio64, 3970 unsigned n_dma, uint32_t *liobns, Error **errp) 3971 { 3972 /* 3973 * New-style PHB window placement. 3974 * 3975 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3976 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3977 * windows. 3978 * 3979 * Some guest kernels can't work with MMIO windows above 1<<46 3980 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3981 * 3982 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3983 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3984 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3985 * 1TiB 64-bit MMIO windows for each PHB. 3986 */ 3987 const uint64_t base_buid = 0x800000020000000ULL; 3988 int i; 3989 3990 /* Sanity check natural alignments */ 3991 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3992 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3993 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3994 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3995 /* Sanity check bounds */ 3996 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3997 SPAPR_PCI_MEM32_WIN_SIZE); 3998 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3999 SPAPR_PCI_MEM64_WIN_SIZE); 4000 4001 if (index >= SPAPR_MAX_PHBS) { 4002 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4003 SPAPR_MAX_PHBS - 1); 4004 return; 4005 } 4006 4007 *buid = base_buid + index; 4008 for (i = 0; i < n_dma; ++i) { 4009 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4010 } 4011 4012 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4013 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4014 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4015 } 4016 4017 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4018 { 4019 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 4020 4021 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4022 } 4023 4024 static void spapr_ics_resend(XICSFabric *dev) 4025 { 4026 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 4027 4028 ics_resend(spapr->ics); 4029 } 4030 4031 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4032 { 4033 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4034 4035 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4036 } 4037 4038 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4039 Monitor *mon) 4040 { 4041 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 4042 4043 spapr->irq->print_info(spapr, mon); 4044 } 4045 4046 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4047 { 4048 return cpu->vcpu_id; 4049 } 4050 4051 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4052 { 4053 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4054 int vcpu_id; 4055 4056 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4057 4058 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4059 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4060 error_append_hint(errp, "Adjust the number of cpus to %d " 4061 "or try to raise the number of threads per core\n", 4062 vcpu_id * smp_threads / spapr->vsmt); 4063 return; 4064 } 4065 4066 cpu->vcpu_id = vcpu_id; 4067 } 4068 4069 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4070 { 4071 CPUState *cs; 4072 4073 CPU_FOREACH(cs) { 4074 PowerPCCPU *cpu = POWERPC_CPU(cs); 4075 4076 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4077 return cpu; 4078 } 4079 } 4080 4081 return NULL; 4082 } 4083 4084 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4085 { 4086 MachineClass *mc = MACHINE_CLASS(oc); 4087 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4088 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4089 NMIClass *nc = NMI_CLASS(oc); 4090 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4091 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4092 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4093 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4094 4095 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4096 mc->ignore_boot_device_suffixes = true; 4097 4098 /* 4099 * We set up the default / latest behaviour here. The class_init 4100 * functions for the specific versioned machine types can override 4101 * these details for backwards compatibility 4102 */ 4103 mc->init = spapr_machine_init; 4104 mc->reset = spapr_machine_reset; 4105 mc->block_default_type = IF_SCSI; 4106 mc->max_cpus = 1024; 4107 mc->no_parallel = 1; 4108 mc->default_boot_order = ""; 4109 mc->default_ram_size = 512 * MiB; 4110 mc->default_display = "std"; 4111 mc->kvm_type = spapr_kvm_type; 4112 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4113 mc->pci_allow_0_address = true; 4114 assert(!mc->get_hotplug_handler); 4115 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4116 hc->pre_plug = spapr_machine_device_pre_plug; 4117 hc->plug = spapr_machine_device_plug; 4118 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4119 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4120 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4121 hc->unplug_request = spapr_machine_device_unplug_request; 4122 hc->unplug = spapr_machine_device_unplug; 4123 4124 smc->dr_lmb_enabled = true; 4125 smc->update_dt_enabled = true; 4126 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4127 mc->has_hotpluggable_cpus = true; 4128 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4129 fwc->get_dev_path = spapr_get_fw_dev_path; 4130 nc->nmi_monitor_handler = spapr_nmi; 4131 smc->phb_placement = spapr_phb_placement; 4132 vhc->hypercall = emulate_spapr_hypercall; 4133 vhc->hpt_mask = spapr_hpt_mask; 4134 vhc->map_hptes = spapr_map_hptes; 4135 vhc->unmap_hptes = spapr_unmap_hptes; 4136 vhc->store_hpte = spapr_store_hpte; 4137 vhc->get_pate = spapr_get_pate; 4138 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4139 xic->ics_get = spapr_ics_get; 4140 xic->ics_resend = spapr_ics_resend; 4141 xic->icp_get = spapr_icp_get; 4142 ispc->print_info = spapr_pic_print_info; 4143 /* Force NUMA node memory size to be a multiple of 4144 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4145 * in which LMBs are represented and hot-added 4146 */ 4147 mc->numa_mem_align_shift = 28; 4148 4149 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4150 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4151 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4152 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4153 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4154 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4155 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4156 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4157 spapr_caps_add_properties(smc, &error_abort); 4158 smc->irq = &spapr_irq_xics; 4159 } 4160 4161 static const TypeInfo spapr_machine_info = { 4162 .name = TYPE_SPAPR_MACHINE, 4163 .parent = TYPE_MACHINE, 4164 .abstract = true, 4165 .instance_size = sizeof(sPAPRMachineState), 4166 .instance_init = spapr_instance_init, 4167 .instance_finalize = spapr_machine_finalizefn, 4168 .class_size = sizeof(sPAPRMachineClass), 4169 .class_init = spapr_machine_class_init, 4170 .interfaces = (InterfaceInfo[]) { 4171 { TYPE_FW_PATH_PROVIDER }, 4172 { TYPE_NMI }, 4173 { TYPE_HOTPLUG_HANDLER }, 4174 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4175 { TYPE_XICS_FABRIC }, 4176 { TYPE_INTERRUPT_STATS_PROVIDER }, 4177 { } 4178 }, 4179 }; 4180 4181 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4182 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4183 void *data) \ 4184 { \ 4185 MachineClass *mc = MACHINE_CLASS(oc); \ 4186 spapr_machine_##suffix##_class_options(mc); \ 4187 if (latest) { \ 4188 mc->alias = "pseries"; \ 4189 mc->is_default = 1; \ 4190 } \ 4191 } \ 4192 static const TypeInfo spapr_machine_##suffix##_info = { \ 4193 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4194 .parent = TYPE_SPAPR_MACHINE, \ 4195 .class_init = spapr_machine_##suffix##_class_init, \ 4196 }; \ 4197 static void spapr_machine_register_##suffix(void) \ 4198 { \ 4199 type_register(&spapr_machine_##suffix##_info); \ 4200 } \ 4201 type_init(spapr_machine_register_##suffix) 4202 4203 /* 4204 * pseries-4.0 4205 */ 4206 static void spapr_machine_4_0_class_options(MachineClass *mc) 4207 { 4208 /* Defaults for the latest behaviour inherited from the base class */ 4209 } 4210 4211 DEFINE_SPAPR_MACHINE(4_0, "4.0", true); 4212 4213 /* 4214 * pseries-3.1 4215 */ 4216 static void spapr_machine_3_1_class_options(MachineClass *mc) 4217 { 4218 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4219 static GlobalProperty compat[] = { 4220 { TYPE_SPAPR_MACHINE, "host-model", "passthrough" }, 4221 { TYPE_SPAPR_MACHINE, "host-serial", "passthrough" }, 4222 }; 4223 4224 spapr_machine_4_0_class_options(mc); 4225 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4226 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4227 4228 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4229 smc->update_dt_enabled = false; 4230 } 4231 4232 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4233 4234 /* 4235 * pseries-3.0 4236 */ 4237 4238 static void spapr_machine_3_0_class_options(MachineClass *mc) 4239 { 4240 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4241 4242 spapr_machine_3_1_class_options(mc); 4243 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4244 4245 smc->legacy_irq_allocation = true; 4246 smc->irq = &spapr_irq_xics_legacy; 4247 } 4248 4249 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4250 4251 /* 4252 * pseries-2.12 4253 */ 4254 static void spapr_machine_2_12_class_options(MachineClass *mc) 4255 { 4256 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4257 static GlobalProperty compat[] = { 4258 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4259 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4260 }; 4261 4262 spapr_machine_3_0_class_options(mc); 4263 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4264 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4265 4266 /* We depend on kvm_enabled() to choose a default value for the 4267 * hpt-max-page-size capability. Of course we can't do it here 4268 * because this is too early and the HW accelerator isn't initialzed 4269 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4270 */ 4271 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4272 } 4273 4274 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4275 4276 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4277 { 4278 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4279 4280 spapr_machine_2_12_class_options(mc); 4281 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4282 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4283 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4284 } 4285 4286 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4287 4288 /* 4289 * pseries-2.11 4290 */ 4291 4292 static void spapr_machine_2_11_class_options(MachineClass *mc) 4293 { 4294 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4295 4296 spapr_machine_2_12_class_options(mc); 4297 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4298 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4299 } 4300 4301 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4302 4303 /* 4304 * pseries-2.10 4305 */ 4306 4307 static void spapr_machine_2_10_class_options(MachineClass *mc) 4308 { 4309 spapr_machine_2_11_class_options(mc); 4310 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4311 } 4312 4313 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4314 4315 /* 4316 * pseries-2.9 4317 */ 4318 4319 static void spapr_machine_2_9_class_options(MachineClass *mc) 4320 { 4321 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4322 static GlobalProperty compat[] = { 4323 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4324 }; 4325 4326 spapr_machine_2_10_class_options(mc); 4327 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4328 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4329 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4330 smc->pre_2_10_has_unused_icps = true; 4331 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4332 } 4333 4334 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4335 4336 /* 4337 * pseries-2.8 4338 */ 4339 4340 static void spapr_machine_2_8_class_options(MachineClass *mc) 4341 { 4342 static GlobalProperty compat[] = { 4343 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4344 }; 4345 4346 spapr_machine_2_9_class_options(mc); 4347 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4348 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4349 mc->numa_mem_align_shift = 23; 4350 } 4351 4352 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4353 4354 /* 4355 * pseries-2.7 4356 */ 4357 4358 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4359 uint64_t *buid, hwaddr *pio, 4360 hwaddr *mmio32, hwaddr *mmio64, 4361 unsigned n_dma, uint32_t *liobns, Error **errp) 4362 { 4363 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4364 const uint64_t base_buid = 0x800000020000000ULL; 4365 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4366 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4367 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4368 const uint32_t max_index = 255; 4369 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4370 4371 uint64_t ram_top = MACHINE(spapr)->ram_size; 4372 hwaddr phb0_base, phb_base; 4373 int i; 4374 4375 /* Do we have device memory? */ 4376 if (MACHINE(spapr)->maxram_size > ram_top) { 4377 /* Can't just use maxram_size, because there may be an 4378 * alignment gap between normal and device memory regions 4379 */ 4380 ram_top = MACHINE(spapr)->device_memory->base + 4381 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4382 } 4383 4384 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4385 4386 if (index > max_index) { 4387 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4388 max_index); 4389 return; 4390 } 4391 4392 *buid = base_buid + index; 4393 for (i = 0; i < n_dma; ++i) { 4394 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4395 } 4396 4397 phb_base = phb0_base + index * phb_spacing; 4398 *pio = phb_base + pio_offset; 4399 *mmio32 = phb_base + mmio_offset; 4400 /* 4401 * We don't set the 64-bit MMIO window, relying on the PHB's 4402 * fallback behaviour of automatically splitting a large "32-bit" 4403 * window into contiguous 32-bit and 64-bit windows 4404 */ 4405 } 4406 4407 static void spapr_machine_2_7_class_options(MachineClass *mc) 4408 { 4409 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4410 static GlobalProperty compat[] = { 4411 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4412 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4413 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4414 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4415 }; 4416 4417 spapr_machine_2_8_class_options(mc); 4418 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4419 mc->default_machine_opts = "modern-hotplug-events=off"; 4420 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4421 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4422 smc->phb_placement = phb_placement_2_7; 4423 } 4424 4425 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4426 4427 /* 4428 * pseries-2.6 4429 */ 4430 4431 static void spapr_machine_2_6_class_options(MachineClass *mc) 4432 { 4433 static GlobalProperty compat[] = { 4434 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4435 }; 4436 4437 spapr_machine_2_7_class_options(mc); 4438 mc->has_hotpluggable_cpus = false; 4439 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4440 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4441 } 4442 4443 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4444 4445 /* 4446 * pseries-2.5 4447 */ 4448 4449 static void spapr_machine_2_5_class_options(MachineClass *mc) 4450 { 4451 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4452 static GlobalProperty compat[] = { 4453 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4454 }; 4455 4456 spapr_machine_2_6_class_options(mc); 4457 smc->use_ohci_by_default = true; 4458 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4459 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4460 } 4461 4462 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4463 4464 /* 4465 * pseries-2.4 4466 */ 4467 4468 static void spapr_machine_2_4_class_options(MachineClass *mc) 4469 { 4470 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4471 4472 spapr_machine_2_5_class_options(mc); 4473 smc->dr_lmb_enabled = false; 4474 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4475 } 4476 4477 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4478 4479 /* 4480 * pseries-2.3 4481 */ 4482 4483 static void spapr_machine_2_3_class_options(MachineClass *mc) 4484 { 4485 static GlobalProperty compat[] = { 4486 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4487 }; 4488 spapr_machine_2_4_class_options(mc); 4489 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4490 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4491 } 4492 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4493 4494 /* 4495 * pseries-2.2 4496 */ 4497 4498 static void spapr_machine_2_2_class_options(MachineClass *mc) 4499 { 4500 static GlobalProperty compat[] = { 4501 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4502 }; 4503 4504 spapr_machine_2_3_class_options(mc); 4505 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4506 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4507 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4508 } 4509 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4510 4511 /* 4512 * pseries-2.1 4513 */ 4514 4515 static void spapr_machine_2_1_class_options(MachineClass *mc) 4516 { 4517 spapr_machine_2_2_class_options(mc); 4518 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4519 } 4520 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4521 4522 static void spapr_machine_register_types(void) 4523 { 4524 type_register_static(&spapr_machine_info); 4525 } 4526 4527 type_init(spapr_machine_register_types) 4528