1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define FDT_MAX_SIZE 0x100000 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 static void spapr_dt_pa_features(SpaprMachineState *spapr, 221 PowerPCCPU *cpu, 222 void *fdt, int offset) 223 { 224 uint8_t pa_features_206[] = { 6, 0, 225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 226 uint8_t pa_features_207[] = { 24, 0, 227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 231 uint8_t pa_features_300[] = { 66, 0, 232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 235 /* 6: DS207 */ 236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 237 /* 16: Vector */ 238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 247 /* 42: PM, 44: PC RA, 46: SC vec'd */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 249 /* 48: SIMD, 50: QP BFP, 52: String */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 251 /* 54: DecFP, 56: DecI, 58: SHA */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 253 /* 60: NM atomic, 62: RNG */ 254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (!pa_features) { 272 return; 273 } 274 275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 276 /* 277 * Note: we keep CI large pages off by default because a 64K capable 278 * guest provisioned with large pages might otherwise try to map a qemu 279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 280 * even if that qemu runs on a 4k host. 281 * We dd this bit back here if we are confident this is not an issue 282 */ 283 pa_features[3] |= 0x20; 284 } 285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 286 pa_features[24] |= 0x80; /* Transactional memory support */ 287 } 288 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 289 /* Workaround for broken kernels that attempt (guest) radix 290 * mode when they can't handle it, if they see the radix bit set 291 * in pa-features. So hide it from them. */ 292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 293 } 294 295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 296 } 297 298 static hwaddr spapr_node0_size(MachineState *machine) 299 { 300 if (machine->numa_state->num_nodes) { 301 int i; 302 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 303 if (machine->numa_state->nodes[i].node_mem) { 304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 305 machine->ram_size); 306 } 307 } 308 } 309 return machine->ram_size; 310 } 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start, 318 hwaddr size) 319 { 320 uint32_t associativity[] = { 321 cpu_to_be32(0x4), /* length */ 322 cpu_to_be32(0x0), cpu_to_be32(0x0), 323 cpu_to_be32(0x0), cpu_to_be32(nodeid) 324 }; 325 char mem_name[32]; 326 uint64_t mem_reg_property[2]; 327 int off; 328 329 mem_reg_property[0] = cpu_to_be64(start); 330 mem_reg_property[1] = cpu_to_be64(size); 331 332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 333 off = fdt_add_subnode(fdt, 0, mem_name); 334 _FDT(off); 335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 337 sizeof(mem_reg_property)))); 338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 339 sizeof(associativity)))); 340 return off; 341 } 342 343 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 344 { 345 MemoryDeviceInfoList *info; 346 347 for (info = list; info; info = info->next) { 348 MemoryDeviceInfo *value = info->value; 349 350 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 351 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 352 353 if (addr >= pcdimm_info->addr && 354 addr < (pcdimm_info->addr + pcdimm_info->size)) { 355 return pcdimm_info->node; 356 } 357 } 358 } 359 360 return -1; 361 } 362 363 struct sPAPRDrconfCellV2 { 364 uint32_t seq_lmbs; 365 uint64_t base_addr; 366 uint32_t drc_index; 367 uint32_t aa_index; 368 uint32_t flags; 369 } QEMU_PACKED; 370 371 typedef struct DrconfCellQueue { 372 struct sPAPRDrconfCellV2 cell; 373 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 374 } DrconfCellQueue; 375 376 static DrconfCellQueue * 377 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 378 uint32_t drc_index, uint32_t aa_index, 379 uint32_t flags) 380 { 381 DrconfCellQueue *elem; 382 383 elem = g_malloc0(sizeof(*elem)); 384 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 385 elem->cell.base_addr = cpu_to_be64(base_addr); 386 elem->cell.drc_index = cpu_to_be32(drc_index); 387 elem->cell.aa_index = cpu_to_be32(aa_index); 388 elem->cell.flags = cpu_to_be32(flags); 389 390 return elem; 391 } 392 393 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 394 int offset, MemoryDeviceInfoList *dimms) 395 { 396 MachineState *machine = MACHINE(spapr); 397 uint8_t *int_buf, *cur_index; 398 int ret; 399 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 400 uint64_t addr, cur_addr, size; 401 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 402 uint64_t mem_end = machine->device_memory->base + 403 memory_region_size(&machine->device_memory->mr); 404 uint32_t node, buf_len, nr_entries = 0; 405 SpaprDrc *drc; 406 DrconfCellQueue *elem, *next; 407 MemoryDeviceInfoList *info; 408 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 409 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 410 411 /* Entry to cover RAM and the gap area */ 412 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 413 SPAPR_LMB_FLAGS_RESERVED | 414 SPAPR_LMB_FLAGS_DRC_INVALID); 415 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 416 nr_entries++; 417 418 cur_addr = machine->device_memory->base; 419 for (info = dimms; info; info = info->next) { 420 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 421 422 addr = di->addr; 423 size = di->size; 424 node = di->node; 425 426 /* 427 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 428 * area is marked hotpluggable in the next iteration for the bigger 429 * chunk including the NVDIMM occupied area. 430 */ 431 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 432 continue; 433 434 /* Entry for hot-pluggable area */ 435 if (cur_addr < addr) { 436 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 437 g_assert(drc); 438 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 439 cur_addr, spapr_drc_index(drc), -1, 0); 440 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 441 nr_entries++; 442 } 443 444 /* Entry for DIMM */ 445 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 446 g_assert(drc); 447 elem = spapr_get_drconf_cell(size / lmb_size, addr, 448 spapr_drc_index(drc), node, 449 SPAPR_LMB_FLAGS_ASSIGNED); 450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 451 nr_entries++; 452 cur_addr = addr + size; 453 } 454 455 /* Entry for remaining hotpluggable area */ 456 if (cur_addr < mem_end) { 457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 458 g_assert(drc); 459 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 460 cur_addr, spapr_drc_index(drc), -1, 0); 461 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 462 nr_entries++; 463 } 464 465 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 466 int_buf = cur_index = g_malloc0(buf_len); 467 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 468 cur_index += sizeof(nr_entries); 469 470 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 471 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 472 cur_index += sizeof(elem->cell); 473 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 474 g_free(elem); 475 } 476 477 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 478 g_free(int_buf); 479 if (ret < 0) { 480 return -1; 481 } 482 return 0; 483 } 484 485 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 486 int offset, MemoryDeviceInfoList *dimms) 487 { 488 MachineState *machine = MACHINE(spapr); 489 int i, ret; 490 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 491 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 492 uint32_t nr_lmbs = (machine->device_memory->base + 493 memory_region_size(&machine->device_memory->mr)) / 494 lmb_size; 495 uint32_t *int_buf, *cur_index, buf_len; 496 497 /* 498 * Allocate enough buffer size to fit in ibm,dynamic-memory 499 */ 500 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 501 cur_index = int_buf = g_malloc0(buf_len); 502 int_buf[0] = cpu_to_be32(nr_lmbs); 503 cur_index++; 504 for (i = 0; i < nr_lmbs; i++) { 505 uint64_t addr = i * lmb_size; 506 uint32_t *dynamic_memory = cur_index; 507 508 if (i >= device_lmb_start) { 509 SpaprDrc *drc; 510 511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 512 g_assert(drc); 513 514 dynamic_memory[0] = cpu_to_be32(addr >> 32); 515 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 516 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 517 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 518 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 519 if (memory_region_present(get_system_memory(), addr)) { 520 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 521 } else { 522 dynamic_memory[5] = cpu_to_be32(0); 523 } 524 } else { 525 /* 526 * LMB information for RMA, boot time RAM and gap b/n RAM and 527 * device memory region -- all these are marked as reserved 528 * and as having no valid DRC. 529 */ 530 dynamic_memory[0] = cpu_to_be32(addr >> 32); 531 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 532 dynamic_memory[2] = cpu_to_be32(0); 533 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 534 dynamic_memory[4] = cpu_to_be32(-1); 535 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 536 SPAPR_LMB_FLAGS_DRC_INVALID); 537 } 538 539 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 540 } 541 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 542 g_free(int_buf); 543 if (ret < 0) { 544 return -1; 545 } 546 return 0; 547 } 548 549 /* 550 * Adds ibm,dynamic-reconfiguration-memory node. 551 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 552 * of this device tree node. 553 */ 554 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 555 void *fdt) 556 { 557 MachineState *machine = MACHINE(spapr); 558 int nb_numa_nodes = machine->numa_state->num_nodes; 559 int ret, i, offset; 560 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 561 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 562 uint32_t *int_buf, *cur_index, buf_len; 563 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 564 MemoryDeviceInfoList *dimms = NULL; 565 566 /* 567 * Don't create the node if there is no device memory 568 */ 569 if (machine->ram_size == machine->maxram_size) { 570 return 0; 571 } 572 573 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 574 575 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 576 sizeof(prop_lmb_size)); 577 if (ret < 0) { 578 return ret; 579 } 580 581 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 582 if (ret < 0) { 583 return ret; 584 } 585 586 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 587 if (ret < 0) { 588 return ret; 589 } 590 591 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 592 dimms = qmp_memory_device_list(); 593 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 594 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 595 } else { 596 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 597 } 598 qapi_free_MemoryDeviceInfoList(dimms); 599 600 if (ret < 0) { 601 return ret; 602 } 603 604 /* ibm,associativity-lookup-arrays */ 605 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 606 cur_index = int_buf = g_malloc0(buf_len); 607 int_buf[0] = cpu_to_be32(nr_nodes); 608 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 609 cur_index += 2; 610 for (i = 0; i < nr_nodes; i++) { 611 uint32_t associativity[] = { 612 cpu_to_be32(0x0), 613 cpu_to_be32(0x0), 614 cpu_to_be32(0x0), 615 cpu_to_be32(i) 616 }; 617 memcpy(cur_index, associativity, sizeof(associativity)); 618 cur_index += 4; 619 } 620 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 621 (cur_index - int_buf) * sizeof(uint32_t)); 622 g_free(int_buf); 623 624 return ret; 625 } 626 627 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 628 { 629 MachineState *machine = MACHINE(spapr); 630 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 631 hwaddr mem_start, node_size; 632 int i, nb_nodes = machine->numa_state->num_nodes; 633 NodeInfo *nodes = machine->numa_state->nodes; 634 635 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 636 if (!nodes[i].node_mem) { 637 continue; 638 } 639 if (mem_start >= machine->ram_size) { 640 node_size = 0; 641 } else { 642 node_size = nodes[i].node_mem; 643 if (node_size > machine->ram_size - mem_start) { 644 node_size = machine->ram_size - mem_start; 645 } 646 } 647 if (!mem_start) { 648 /* spapr_machine_init() checks for rma_size <= node0_size 649 * already */ 650 spapr_dt_memory_node(fdt, i, 0, spapr->rma_size); 651 mem_start += spapr->rma_size; 652 node_size -= spapr->rma_size; 653 } 654 for ( ; node_size; ) { 655 hwaddr sizetmp = pow2floor(node_size); 656 657 /* mem_start != 0 here */ 658 if (ctzl(mem_start) < ctzl(sizetmp)) { 659 sizetmp = 1ULL << ctzl(mem_start); 660 } 661 662 spapr_dt_memory_node(fdt, i, mem_start, sizetmp); 663 node_size -= sizetmp; 664 mem_start += sizetmp; 665 } 666 } 667 668 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 669 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 670 int ret; 671 672 g_assert(smc->dr_lmb_enabled); 673 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 674 if (ret) { 675 return ret; 676 } 677 } 678 679 return 0; 680 } 681 682 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 683 SpaprMachineState *spapr) 684 { 685 MachineState *ms = MACHINE(spapr); 686 PowerPCCPU *cpu = POWERPC_CPU(cs); 687 CPUPPCState *env = &cpu->env; 688 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 689 int index = spapr_get_vcpu_id(cpu); 690 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 691 0xffffffff, 0xffffffff}; 692 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 693 : SPAPR_TIMEBASE_FREQ; 694 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 695 uint32_t page_sizes_prop[64]; 696 size_t page_sizes_prop_size; 697 unsigned int smp_threads = ms->smp.threads; 698 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 699 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 700 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 701 SpaprDrc *drc; 702 int drc_index; 703 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 704 int i; 705 706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 707 if (drc) { 708 drc_index = spapr_drc_index(drc); 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 710 } 711 712 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 713 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 714 715 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 716 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 717 env->dcache_line_size))); 718 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 719 env->dcache_line_size))); 720 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 721 env->icache_line_size))); 722 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 723 env->icache_line_size))); 724 725 if (pcc->l1_dcache_size) { 726 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 727 pcc->l1_dcache_size))); 728 } else { 729 warn_report("Unknown L1 dcache size for cpu"); 730 } 731 if (pcc->l1_icache_size) { 732 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 733 pcc->l1_icache_size))); 734 } else { 735 warn_report("Unknown L1 icache size for cpu"); 736 } 737 738 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 739 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 740 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 741 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 742 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 743 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 744 745 if (env->spr_cb[SPR_PURR].oea_read) { 746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 747 } 748 if (env->spr_cb[SPR_SPURR].oea_read) { 749 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 750 } 751 752 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 753 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 754 segs, sizeof(segs)))); 755 } 756 757 /* Advertise VSX (vector extensions) if available 758 * 1 == VMX / Altivec available 759 * 2 == VSX available 760 * 761 * Only CPUs for which we create core types in spapr_cpu_core.c 762 * are possible, and all of those have VMX */ 763 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 764 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 765 } else { 766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 767 } 768 769 /* Advertise DFP (Decimal Floating Point) if available 770 * 0 / no property == no DFP 771 * 1 == DFP available */ 772 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 773 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 774 } 775 776 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 777 sizeof(page_sizes_prop)); 778 if (page_sizes_prop_size) { 779 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 780 page_sizes_prop, page_sizes_prop_size))); 781 } 782 783 spapr_dt_pa_features(spapr, cpu, fdt, offset); 784 785 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 786 cs->cpu_index / vcpus_per_socket))); 787 788 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 789 pft_size_prop, sizeof(pft_size_prop)))); 790 791 if (ms->numa_state->num_nodes > 1) { 792 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 793 } 794 795 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 796 797 if (pcc->radix_page_info) { 798 for (i = 0; i < pcc->radix_page_info->count; i++) { 799 radix_AP_encodings[i] = 800 cpu_to_be32(pcc->radix_page_info->entries[i]); 801 } 802 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 803 radix_AP_encodings, 804 pcc->radix_page_info->count * 805 sizeof(radix_AP_encodings[0])))); 806 } 807 808 /* 809 * We set this property to let the guest know that it can use the large 810 * decrementer and its width in bits. 811 */ 812 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 813 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 814 pcc->lrg_decr_bits))); 815 } 816 817 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 818 { 819 CPUState **rev; 820 CPUState *cs; 821 int n_cpus; 822 int cpus_offset; 823 char *nodename; 824 int i; 825 826 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 827 _FDT(cpus_offset); 828 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 829 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 830 831 /* 832 * We walk the CPUs in reverse order to ensure that CPU DT nodes 833 * created by fdt_add_subnode() end up in the right order in FDT 834 * for the guest kernel the enumerate the CPUs correctly. 835 * 836 * The CPU list cannot be traversed in reverse order, so we need 837 * to do extra work. 838 */ 839 n_cpus = 0; 840 rev = NULL; 841 CPU_FOREACH(cs) { 842 rev = g_renew(CPUState *, rev, n_cpus + 1); 843 rev[n_cpus++] = cs; 844 } 845 846 for (i = n_cpus - 1; i >= 0; i--) { 847 CPUState *cs = rev[i]; 848 PowerPCCPU *cpu = POWERPC_CPU(cs); 849 int index = spapr_get_vcpu_id(cpu); 850 DeviceClass *dc = DEVICE_GET_CLASS(cs); 851 int offset; 852 853 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 854 continue; 855 } 856 857 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 858 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 859 g_free(nodename); 860 _FDT(offset); 861 spapr_dt_cpu(cs, fdt, offset, spapr); 862 } 863 864 g_free(rev); 865 } 866 867 static int spapr_dt_rng(void *fdt) 868 { 869 int node; 870 int ret; 871 872 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 873 if (node <= 0) { 874 return -1; 875 } 876 ret = fdt_setprop_string(fdt, node, "device_type", 877 "ibm,platform-facilities"); 878 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 879 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 880 881 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 882 if (node <= 0) { 883 return -1; 884 } 885 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 886 887 return ret ? -1 : 0; 888 } 889 890 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 891 { 892 MachineState *ms = MACHINE(spapr); 893 int rtas; 894 GString *hypertas = g_string_sized_new(256); 895 GString *qemu_hypertas = g_string_sized_new(256); 896 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 897 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 898 memory_region_size(&MACHINE(spapr)->device_memory->mr); 899 uint32_t lrdr_capacity[] = { 900 cpu_to_be32(max_device_addr >> 32), 901 cpu_to_be32(max_device_addr & 0xffffffff), 902 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 903 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 904 }; 905 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 906 uint32_t maxdomains[] = { 907 cpu_to_be32(4), 908 maxdomain, 909 maxdomain, 910 maxdomain, 911 cpu_to_be32(spapr->gpu_numa_id), 912 }; 913 914 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 915 916 /* hypertas */ 917 add_str(hypertas, "hcall-pft"); 918 add_str(hypertas, "hcall-term"); 919 add_str(hypertas, "hcall-dabr"); 920 add_str(hypertas, "hcall-interrupt"); 921 add_str(hypertas, "hcall-tce"); 922 add_str(hypertas, "hcall-vio"); 923 add_str(hypertas, "hcall-splpar"); 924 add_str(hypertas, "hcall-join"); 925 add_str(hypertas, "hcall-bulk"); 926 add_str(hypertas, "hcall-set-mode"); 927 add_str(hypertas, "hcall-sprg0"); 928 add_str(hypertas, "hcall-copy"); 929 add_str(hypertas, "hcall-debug"); 930 add_str(hypertas, "hcall-vphn"); 931 add_str(qemu_hypertas, "hcall-memop1"); 932 933 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 934 add_str(hypertas, "hcall-multi-tce"); 935 } 936 937 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 938 add_str(hypertas, "hcall-hpt-resize"); 939 } 940 941 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 942 hypertas->str, hypertas->len)); 943 g_string_free(hypertas, TRUE); 944 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 945 qemu_hypertas->str, qemu_hypertas->len)); 946 g_string_free(qemu_hypertas, TRUE); 947 948 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 949 refpoints, sizeof(refpoints))); 950 951 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 952 maxdomains, sizeof(maxdomains))); 953 954 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_SIZE)); 955 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 956 RTAS_ERROR_LOG_MAX)); 957 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 958 RTAS_EVENT_SCAN_RATE)); 959 960 g_assert(msi_nonbroken); 961 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 962 963 /* 964 * According to PAPR, rtas ibm,os-term does not guarantee a return 965 * back to the guest cpu. 966 * 967 * While an additional ibm,extended-os-term property indicates 968 * that rtas call return will always occur. Set this property. 969 */ 970 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 971 972 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 973 lrdr_capacity, sizeof(lrdr_capacity))); 974 975 spapr_dt_rtas_tokens(fdt, rtas); 976 } 977 978 /* 979 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 980 * and the XIVE features that the guest may request and thus the valid 981 * values for bytes 23..26 of option vector 5: 982 */ 983 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 984 int chosen) 985 { 986 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 987 988 char val[2 * 4] = { 989 23, 0x00, /* XICS / XIVE mode */ 990 24, 0x00, /* Hash/Radix, filled in below. */ 991 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 992 26, 0x40, /* Radix options: GTSE == yes. */ 993 }; 994 995 if (spapr->irq->xics && spapr->irq->xive) { 996 val[1] = SPAPR_OV5_XIVE_BOTH; 997 } else if (spapr->irq->xive) { 998 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 999 } else { 1000 assert(spapr->irq->xics); 1001 val[1] = SPAPR_OV5_XIVE_LEGACY; 1002 } 1003 1004 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1005 first_ppc_cpu->compat_pvr)) { 1006 /* 1007 * If we're in a pre POWER9 compat mode then the guest should 1008 * do hash and use the legacy interrupt mode 1009 */ 1010 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1011 val[3] = 0x00; /* Hash */ 1012 } else if (kvm_enabled()) { 1013 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1014 val[3] = 0x80; /* OV5_MMU_BOTH */ 1015 } else if (kvmppc_has_cap_mmu_radix()) { 1016 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1017 } else { 1018 val[3] = 0x00; /* Hash */ 1019 } 1020 } else { 1021 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1022 val[3] = 0xC0; 1023 } 1024 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1025 val, sizeof(val))); 1026 } 1027 1028 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1029 { 1030 MachineState *machine = MACHINE(spapr); 1031 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1032 int chosen; 1033 1034 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1035 1036 if (reset) { 1037 const char *boot_device = machine->boot_order; 1038 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1039 size_t cb = 0; 1040 char *bootlist = get_boot_devices_list(&cb); 1041 1042 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1043 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1044 machine->kernel_cmdline)); 1045 } 1046 1047 if (spapr->initrd_size) { 1048 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1049 spapr->initrd_base)); 1050 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1051 spapr->initrd_base + spapr->initrd_size)); 1052 } 1053 1054 if (spapr->kernel_size) { 1055 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1056 cpu_to_be64(spapr->kernel_size) }; 1057 1058 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1059 &kprop, sizeof(kprop))); 1060 if (spapr->kernel_le) { 1061 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1062 } 1063 } 1064 if (boot_menu) { 1065 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1066 } 1067 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1068 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1069 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1070 1071 if (cb && bootlist) { 1072 int i; 1073 1074 for (i = 0; i < cb; i++) { 1075 if (bootlist[i] == '\n') { 1076 bootlist[i] = ' '; 1077 } 1078 } 1079 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1080 } 1081 1082 if (boot_device && strlen(boot_device)) { 1083 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1084 } 1085 1086 if (!spapr->has_graphics && stdout_path) { 1087 /* 1088 * "linux,stdout-path" and "stdout" properties are 1089 * deprecated by linux kernel. New platforms should only 1090 * use the "stdout-path" property. Set the new property 1091 * and continue using older property to remain compatible 1092 * with the existing firmware. 1093 */ 1094 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1095 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1096 } 1097 1098 /* 1099 * We can deal with BAR reallocation just fine, advertise it 1100 * to the guest 1101 */ 1102 if (smc->linux_pci_probe) { 1103 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1104 } 1105 1106 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1107 1108 g_free(stdout_path); 1109 g_free(bootlist); 1110 } 1111 1112 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1113 } 1114 1115 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1116 { 1117 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1118 * KVM to work under pHyp with some guest co-operation */ 1119 int hypervisor; 1120 uint8_t hypercall[16]; 1121 1122 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1123 /* indicate KVM hypercall interface */ 1124 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1125 if (kvmppc_has_cap_fixup_hcalls()) { 1126 /* 1127 * Older KVM versions with older guest kernels were broken 1128 * with the magic page, don't allow the guest to map it. 1129 */ 1130 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1131 sizeof(hypercall))) { 1132 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1133 hypercall, sizeof(hypercall))); 1134 } 1135 } 1136 } 1137 1138 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1139 { 1140 MachineState *machine = MACHINE(spapr); 1141 MachineClass *mc = MACHINE_GET_CLASS(machine); 1142 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1143 int ret; 1144 void *fdt; 1145 SpaprPhbState *phb; 1146 char *buf; 1147 1148 fdt = g_malloc0(space); 1149 _FDT((fdt_create_empty_tree(fdt, space))); 1150 1151 /* Root node */ 1152 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1153 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1154 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1155 1156 /* Guest UUID & Name*/ 1157 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1158 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1159 if (qemu_uuid_set) { 1160 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1161 } 1162 g_free(buf); 1163 1164 if (qemu_get_vm_name()) { 1165 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1166 qemu_get_vm_name())); 1167 } 1168 1169 /* Host Model & Serial Number */ 1170 if (spapr->host_model) { 1171 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1172 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1173 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1174 g_free(buf); 1175 } 1176 1177 if (spapr->host_serial) { 1178 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1179 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1180 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1181 g_free(buf); 1182 } 1183 1184 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1185 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1186 1187 /* /interrupt controller */ 1188 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1189 1190 ret = spapr_dt_memory(spapr, fdt); 1191 if (ret < 0) { 1192 error_report("couldn't setup memory nodes in fdt"); 1193 exit(1); 1194 } 1195 1196 /* /vdevice */ 1197 spapr_dt_vdevice(spapr->vio_bus, fdt); 1198 1199 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1200 ret = spapr_dt_rng(fdt); 1201 if (ret < 0) { 1202 error_report("could not set up rng device in the fdt"); 1203 exit(1); 1204 } 1205 } 1206 1207 QLIST_FOREACH(phb, &spapr->phbs, list) { 1208 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1209 if (ret < 0) { 1210 error_report("couldn't setup PCI devices in fdt"); 1211 exit(1); 1212 } 1213 } 1214 1215 spapr_dt_cpus(fdt, spapr); 1216 1217 if (smc->dr_lmb_enabled) { 1218 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1219 } 1220 1221 if (mc->has_hotpluggable_cpus) { 1222 int offset = fdt_path_offset(fdt, "/cpus"); 1223 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1224 if (ret < 0) { 1225 error_report("Couldn't set up CPU DR device tree properties"); 1226 exit(1); 1227 } 1228 } 1229 1230 /* /event-sources */ 1231 spapr_dt_events(spapr, fdt); 1232 1233 /* /rtas */ 1234 spapr_dt_rtas(spapr, fdt); 1235 1236 /* /chosen */ 1237 spapr_dt_chosen(spapr, fdt, reset); 1238 1239 /* /hypervisor */ 1240 if (kvm_enabled()) { 1241 spapr_dt_hypervisor(spapr, fdt); 1242 } 1243 1244 /* Build memory reserve map */ 1245 if (reset) { 1246 if (spapr->kernel_size) { 1247 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1248 spapr->kernel_size))); 1249 } 1250 if (spapr->initrd_size) { 1251 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1252 spapr->initrd_size))); 1253 } 1254 } 1255 1256 if (smc->dr_phb_enabled) { 1257 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1258 if (ret < 0) { 1259 error_report("Couldn't set up PHB DR device tree properties"); 1260 exit(1); 1261 } 1262 } 1263 1264 /* NVDIMM devices */ 1265 if (mc->nvdimm_supported) { 1266 spapr_dt_persistent_memory(fdt); 1267 } 1268 1269 return fdt; 1270 } 1271 1272 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1273 { 1274 SpaprMachineState *spapr = opaque; 1275 1276 return (addr & 0x0fffffff) + spapr->kernel_addr; 1277 } 1278 1279 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1280 PowerPCCPU *cpu) 1281 { 1282 CPUPPCState *env = &cpu->env; 1283 1284 /* The TCG path should also be holding the BQL at this point */ 1285 g_assert(qemu_mutex_iothread_locked()); 1286 1287 if (msr_pr) { 1288 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1289 env->gpr[3] = H_PRIVILEGE; 1290 } else { 1291 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1292 } 1293 } 1294 1295 struct LPCRSyncState { 1296 target_ulong value; 1297 target_ulong mask; 1298 }; 1299 1300 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1301 { 1302 struct LPCRSyncState *s = arg.host_ptr; 1303 PowerPCCPU *cpu = POWERPC_CPU(cs); 1304 CPUPPCState *env = &cpu->env; 1305 target_ulong lpcr; 1306 1307 cpu_synchronize_state(cs); 1308 lpcr = env->spr[SPR_LPCR]; 1309 lpcr &= ~s->mask; 1310 lpcr |= s->value; 1311 ppc_store_lpcr(cpu, lpcr); 1312 } 1313 1314 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1315 { 1316 CPUState *cs; 1317 struct LPCRSyncState s = { 1318 .value = value, 1319 .mask = mask 1320 }; 1321 CPU_FOREACH(cs) { 1322 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1323 } 1324 } 1325 1326 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1327 { 1328 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1329 1330 /* Copy PATE1:GR into PATE0:HR */ 1331 entry->dw0 = spapr->patb_entry & PATE0_HR; 1332 entry->dw1 = spapr->patb_entry; 1333 } 1334 1335 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1336 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1337 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1338 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1339 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1340 1341 /* 1342 * Get the fd to access the kernel htab, re-opening it if necessary 1343 */ 1344 static int get_htab_fd(SpaprMachineState *spapr) 1345 { 1346 Error *local_err = NULL; 1347 1348 if (spapr->htab_fd >= 0) { 1349 return spapr->htab_fd; 1350 } 1351 1352 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1353 if (spapr->htab_fd < 0) { 1354 error_report_err(local_err); 1355 } 1356 1357 return spapr->htab_fd; 1358 } 1359 1360 void close_htab_fd(SpaprMachineState *spapr) 1361 { 1362 if (spapr->htab_fd >= 0) { 1363 close(spapr->htab_fd); 1364 } 1365 spapr->htab_fd = -1; 1366 } 1367 1368 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1369 { 1370 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1371 1372 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1373 } 1374 1375 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1376 { 1377 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1378 1379 assert(kvm_enabled()); 1380 1381 if (!spapr->htab) { 1382 return 0; 1383 } 1384 1385 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1386 } 1387 1388 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1389 hwaddr ptex, int n) 1390 { 1391 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1392 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1393 1394 if (!spapr->htab) { 1395 /* 1396 * HTAB is controlled by KVM. Fetch into temporary buffer 1397 */ 1398 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1399 kvmppc_read_hptes(hptes, ptex, n); 1400 return hptes; 1401 } 1402 1403 /* 1404 * HTAB is controlled by QEMU. Just point to the internally 1405 * accessible PTEG. 1406 */ 1407 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1408 } 1409 1410 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1411 const ppc_hash_pte64_t *hptes, 1412 hwaddr ptex, int n) 1413 { 1414 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1415 1416 if (!spapr->htab) { 1417 g_free((void *)hptes); 1418 } 1419 1420 /* Nothing to do for qemu managed HPT */ 1421 } 1422 1423 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1424 uint64_t pte0, uint64_t pte1) 1425 { 1426 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1427 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1428 1429 if (!spapr->htab) { 1430 kvmppc_write_hpte(ptex, pte0, pte1); 1431 } else { 1432 if (pte0 & HPTE64_V_VALID) { 1433 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1434 /* 1435 * When setting valid, we write PTE1 first. This ensures 1436 * proper synchronization with the reading code in 1437 * ppc_hash64_pteg_search() 1438 */ 1439 smp_wmb(); 1440 stq_p(spapr->htab + offset, pte0); 1441 } else { 1442 stq_p(spapr->htab + offset, pte0); 1443 /* 1444 * When clearing it we set PTE0 first. This ensures proper 1445 * synchronization with the reading code in 1446 * ppc_hash64_pteg_search() 1447 */ 1448 smp_wmb(); 1449 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1450 } 1451 } 1452 } 1453 1454 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1455 uint64_t pte1) 1456 { 1457 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1458 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1459 1460 if (!spapr->htab) { 1461 /* There should always be a hash table when this is called */ 1462 error_report("spapr_hpte_set_c called with no hash table !"); 1463 return; 1464 } 1465 1466 /* The HW performs a non-atomic byte update */ 1467 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1468 } 1469 1470 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1471 uint64_t pte1) 1472 { 1473 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1474 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1475 1476 if (!spapr->htab) { 1477 /* There should always be a hash table when this is called */ 1478 error_report("spapr_hpte_set_r called with no hash table !"); 1479 return; 1480 } 1481 1482 /* The HW performs a non-atomic byte update */ 1483 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1484 } 1485 1486 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1487 { 1488 int shift; 1489 1490 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1491 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1492 * that's much more than is needed for Linux guests */ 1493 shift = ctz64(pow2ceil(ramsize)) - 7; 1494 shift = MAX(shift, 18); /* Minimum architected size */ 1495 shift = MIN(shift, 46); /* Maximum architected size */ 1496 return shift; 1497 } 1498 1499 void spapr_free_hpt(SpaprMachineState *spapr) 1500 { 1501 g_free(spapr->htab); 1502 spapr->htab = NULL; 1503 spapr->htab_shift = 0; 1504 close_htab_fd(spapr); 1505 } 1506 1507 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1508 Error **errp) 1509 { 1510 long rc; 1511 1512 /* Clean up any HPT info from a previous boot */ 1513 spapr_free_hpt(spapr); 1514 1515 rc = kvmppc_reset_htab(shift); 1516 if (rc < 0) { 1517 /* kernel-side HPT needed, but couldn't allocate one */ 1518 error_setg_errno(errp, errno, 1519 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1520 shift); 1521 /* This is almost certainly fatal, but if the caller really 1522 * wants to carry on with shift == 0, it's welcome to try */ 1523 } else if (rc > 0) { 1524 /* kernel-side HPT allocated */ 1525 if (rc != shift) { 1526 error_setg(errp, 1527 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1528 shift, rc); 1529 } 1530 1531 spapr->htab_shift = shift; 1532 spapr->htab = NULL; 1533 } else { 1534 /* kernel-side HPT not needed, allocate in userspace instead */ 1535 size_t size = 1ULL << shift; 1536 int i; 1537 1538 spapr->htab = qemu_memalign(size, size); 1539 if (!spapr->htab) { 1540 error_setg_errno(errp, errno, 1541 "Could not allocate HPT of order %d", shift); 1542 return; 1543 } 1544 1545 memset(spapr->htab, 0, size); 1546 spapr->htab_shift = shift; 1547 1548 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1549 DIRTY_HPTE(HPTE(spapr->htab, i)); 1550 } 1551 } 1552 /* We're setting up a hash table, so that means we're not radix */ 1553 spapr->patb_entry = 0; 1554 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1555 } 1556 1557 void spapr_setup_hpt(SpaprMachineState *spapr) 1558 { 1559 int hpt_shift; 1560 1561 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1562 || (spapr->cas_reboot 1563 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1564 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1565 } else { 1566 uint64_t current_ram_size; 1567 1568 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1569 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1570 } 1571 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1572 1573 if (kvm_enabled()) { 1574 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1575 1576 /* Check our RMA fits in the possible VRMA */ 1577 if (vrma_limit < spapr->rma_size) { 1578 error_report("Unable to create %" HWADDR_PRIu 1579 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1580 spapr->rma_size / MiB, vrma_limit / MiB); 1581 exit(EXIT_FAILURE); 1582 } 1583 } 1584 } 1585 1586 static int spapr_reset_drcs(Object *child, void *opaque) 1587 { 1588 SpaprDrc *drc = 1589 (SpaprDrc *) object_dynamic_cast(child, 1590 TYPE_SPAPR_DR_CONNECTOR); 1591 1592 if (drc) { 1593 spapr_drc_reset(drc); 1594 } 1595 1596 return 0; 1597 } 1598 1599 static void spapr_machine_reset(MachineState *machine) 1600 { 1601 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1602 PowerPCCPU *first_ppc_cpu; 1603 hwaddr fdt_addr; 1604 void *fdt; 1605 int rc; 1606 1607 kvmppc_svm_off(&error_fatal); 1608 spapr_caps_apply(spapr); 1609 1610 first_ppc_cpu = POWERPC_CPU(first_cpu); 1611 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1612 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1613 spapr->max_compat_pvr)) { 1614 /* 1615 * If using KVM with radix mode available, VCPUs can be started 1616 * without a HPT because KVM will start them in radix mode. 1617 * Set the GR bit in PATE so that we know there is no HPT. 1618 */ 1619 spapr->patb_entry = PATE1_GR; 1620 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1621 } else { 1622 spapr_setup_hpt(spapr); 1623 } 1624 1625 qemu_devices_reset(); 1626 1627 /* 1628 * If this reset wasn't generated by CAS, we should reset our 1629 * negotiated options and start from scratch 1630 */ 1631 if (!spapr->cas_reboot) { 1632 spapr_ovec_cleanup(spapr->ov5_cas); 1633 spapr->ov5_cas = spapr_ovec_new(); 1634 1635 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1636 } 1637 1638 /* 1639 * This is fixing some of the default configuration of the XIVE 1640 * devices. To be called after the reset of the machine devices. 1641 */ 1642 spapr_irq_reset(spapr, &error_fatal); 1643 1644 /* 1645 * There is no CAS under qtest. Simulate one to please the code that 1646 * depends on spapr->ov5_cas. This is especially needed to test device 1647 * unplug, so we do that before resetting the DRCs. 1648 */ 1649 if (qtest_enabled()) { 1650 spapr_ovec_cleanup(spapr->ov5_cas); 1651 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1652 } 1653 1654 /* DRC reset may cause a device to be unplugged. This will cause troubles 1655 * if this device is used by another device (eg, a running vhost backend 1656 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1657 * situations, we reset DRCs after all devices have been reset. 1658 */ 1659 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1660 1661 spapr_clear_pending_events(spapr); 1662 1663 /* 1664 * We place the device tree and RTAS just below either the top of the RMA, 1665 * or just below 2GB, whichever is lower, so that it can be 1666 * processed with 32-bit real mode code if necessary 1667 */ 1668 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1669 1670 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1671 1672 rc = fdt_pack(fdt); 1673 1674 /* Should only fail if we've built a corrupted tree */ 1675 assert(rc == 0); 1676 1677 /* Load the fdt */ 1678 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1679 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1680 g_free(spapr->fdt_blob); 1681 spapr->fdt_size = fdt_totalsize(fdt); 1682 spapr->fdt_initial_size = spapr->fdt_size; 1683 spapr->fdt_blob = fdt; 1684 1685 /* Set up the entry state */ 1686 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1687 first_ppc_cpu->env.gpr[5] = 0; 1688 1689 spapr->cas_reboot = false; 1690 1691 spapr->fwnmi_machine_check_addr = -1; 1692 spapr->fwnmi_machine_check_interlock = -1; 1693 1694 /* Signal all vCPUs waiting on this condition */ 1695 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1696 1697 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1698 } 1699 1700 static void spapr_create_nvram(SpaprMachineState *spapr) 1701 { 1702 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1703 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1704 1705 if (dinfo) { 1706 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1707 &error_fatal); 1708 } 1709 1710 qdev_init_nofail(dev); 1711 1712 spapr->nvram = (struct SpaprNvram *)dev; 1713 } 1714 1715 static void spapr_rtc_create(SpaprMachineState *spapr) 1716 { 1717 object_initialize_child(OBJECT(spapr), "rtc", 1718 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1719 &error_fatal, NULL); 1720 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1721 &error_fatal); 1722 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1723 "date", &error_fatal); 1724 } 1725 1726 /* Returns whether we want to use VGA or not */ 1727 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1728 { 1729 switch (vga_interface_type) { 1730 case VGA_NONE: 1731 return false; 1732 case VGA_DEVICE: 1733 return true; 1734 case VGA_STD: 1735 case VGA_VIRTIO: 1736 case VGA_CIRRUS: 1737 return pci_vga_init(pci_bus) != NULL; 1738 default: 1739 error_setg(errp, 1740 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1741 return false; 1742 } 1743 } 1744 1745 static int spapr_pre_load(void *opaque) 1746 { 1747 int rc; 1748 1749 rc = spapr_caps_pre_load(opaque); 1750 if (rc) { 1751 return rc; 1752 } 1753 1754 return 0; 1755 } 1756 1757 static int spapr_post_load(void *opaque, int version_id) 1758 { 1759 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1760 int err = 0; 1761 1762 err = spapr_caps_post_migration(spapr); 1763 if (err) { 1764 return err; 1765 } 1766 1767 /* 1768 * In earlier versions, there was no separate qdev for the PAPR 1769 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1770 * So when migrating from those versions, poke the incoming offset 1771 * value into the RTC device 1772 */ 1773 if (version_id < 3) { 1774 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1775 if (err) { 1776 return err; 1777 } 1778 } 1779 1780 if (kvm_enabled() && spapr->patb_entry) { 1781 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1782 bool radix = !!(spapr->patb_entry & PATE1_GR); 1783 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1784 1785 /* 1786 * Update LPCR:HR and UPRT as they may not be set properly in 1787 * the stream 1788 */ 1789 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1790 LPCR_HR | LPCR_UPRT); 1791 1792 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1793 if (err) { 1794 error_report("Process table config unsupported by the host"); 1795 return -EINVAL; 1796 } 1797 } 1798 1799 err = spapr_irq_post_load(spapr, version_id); 1800 if (err) { 1801 return err; 1802 } 1803 1804 return err; 1805 } 1806 1807 static int spapr_pre_save(void *opaque) 1808 { 1809 int rc; 1810 1811 rc = spapr_caps_pre_save(opaque); 1812 if (rc) { 1813 return rc; 1814 } 1815 1816 return 0; 1817 } 1818 1819 static bool version_before_3(void *opaque, int version_id) 1820 { 1821 return version_id < 3; 1822 } 1823 1824 static bool spapr_pending_events_needed(void *opaque) 1825 { 1826 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1827 return !QTAILQ_EMPTY(&spapr->pending_events); 1828 } 1829 1830 static const VMStateDescription vmstate_spapr_event_entry = { 1831 .name = "spapr_event_log_entry", 1832 .version_id = 1, 1833 .minimum_version_id = 1, 1834 .fields = (VMStateField[]) { 1835 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1836 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1837 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1838 NULL, extended_length), 1839 VMSTATE_END_OF_LIST() 1840 }, 1841 }; 1842 1843 static const VMStateDescription vmstate_spapr_pending_events = { 1844 .name = "spapr_pending_events", 1845 .version_id = 1, 1846 .minimum_version_id = 1, 1847 .needed = spapr_pending_events_needed, 1848 .fields = (VMStateField[]) { 1849 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1850 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1851 VMSTATE_END_OF_LIST() 1852 }, 1853 }; 1854 1855 static bool spapr_ov5_cas_needed(void *opaque) 1856 { 1857 SpaprMachineState *spapr = opaque; 1858 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1859 bool cas_needed; 1860 1861 /* Prior to the introduction of SpaprOptionVector, we had two option 1862 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1863 * Both of these options encode machine topology into the device-tree 1864 * in such a way that the now-booted OS should still be able to interact 1865 * appropriately with QEMU regardless of what options were actually 1866 * negotiatied on the source side. 1867 * 1868 * As such, we can avoid migrating the CAS-negotiated options if these 1869 * are the only options available on the current machine/platform. 1870 * Since these are the only options available for pseries-2.7 and 1871 * earlier, this allows us to maintain old->new/new->old migration 1872 * compatibility. 1873 * 1874 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1875 * via default pseries-2.8 machines and explicit command-line parameters. 1876 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1877 * of the actual CAS-negotiated values to continue working properly. For 1878 * example, availability of memory unplug depends on knowing whether 1879 * OV5_HP_EVT was negotiated via CAS. 1880 * 1881 * Thus, for any cases where the set of available CAS-negotiatable 1882 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1883 * include the CAS-negotiated options in the migration stream, unless 1884 * if they affect boot time behaviour only. 1885 */ 1886 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1887 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1888 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1889 1890 /* We need extra information if we have any bits outside the mask 1891 * defined above */ 1892 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1893 1894 spapr_ovec_cleanup(ov5_mask); 1895 1896 return cas_needed; 1897 } 1898 1899 static const VMStateDescription vmstate_spapr_ov5_cas = { 1900 .name = "spapr_option_vector_ov5_cas", 1901 .version_id = 1, 1902 .minimum_version_id = 1, 1903 .needed = spapr_ov5_cas_needed, 1904 .fields = (VMStateField[]) { 1905 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1906 vmstate_spapr_ovec, SpaprOptionVector), 1907 VMSTATE_END_OF_LIST() 1908 }, 1909 }; 1910 1911 static bool spapr_patb_entry_needed(void *opaque) 1912 { 1913 SpaprMachineState *spapr = opaque; 1914 1915 return !!spapr->patb_entry; 1916 } 1917 1918 static const VMStateDescription vmstate_spapr_patb_entry = { 1919 .name = "spapr_patb_entry", 1920 .version_id = 1, 1921 .minimum_version_id = 1, 1922 .needed = spapr_patb_entry_needed, 1923 .fields = (VMStateField[]) { 1924 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1925 VMSTATE_END_OF_LIST() 1926 }, 1927 }; 1928 1929 static bool spapr_irq_map_needed(void *opaque) 1930 { 1931 SpaprMachineState *spapr = opaque; 1932 1933 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1934 } 1935 1936 static const VMStateDescription vmstate_spapr_irq_map = { 1937 .name = "spapr_irq_map", 1938 .version_id = 1, 1939 .minimum_version_id = 1, 1940 .needed = spapr_irq_map_needed, 1941 .fields = (VMStateField[]) { 1942 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1943 VMSTATE_END_OF_LIST() 1944 }, 1945 }; 1946 1947 static bool spapr_dtb_needed(void *opaque) 1948 { 1949 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1950 1951 return smc->update_dt_enabled; 1952 } 1953 1954 static int spapr_dtb_pre_load(void *opaque) 1955 { 1956 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1957 1958 g_free(spapr->fdt_blob); 1959 spapr->fdt_blob = NULL; 1960 spapr->fdt_size = 0; 1961 1962 return 0; 1963 } 1964 1965 static const VMStateDescription vmstate_spapr_dtb = { 1966 .name = "spapr_dtb", 1967 .version_id = 1, 1968 .minimum_version_id = 1, 1969 .needed = spapr_dtb_needed, 1970 .pre_load = spapr_dtb_pre_load, 1971 .fields = (VMStateField[]) { 1972 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1973 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1974 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1975 fdt_size), 1976 VMSTATE_END_OF_LIST() 1977 }, 1978 }; 1979 1980 static bool spapr_fwnmi_needed(void *opaque) 1981 { 1982 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1983 1984 return spapr->fwnmi_machine_check_addr != -1; 1985 } 1986 1987 static int spapr_fwnmi_pre_save(void *opaque) 1988 { 1989 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1990 1991 /* 1992 * Check if machine check handling is in progress and print a 1993 * warning message. 1994 */ 1995 if (spapr->fwnmi_machine_check_interlock != -1) { 1996 warn_report("A machine check is being handled during migration. The" 1997 "handler may run and log hardware error on the destination"); 1998 } 1999 2000 return 0; 2001 } 2002 2003 static const VMStateDescription vmstate_spapr_fwnmi = { 2004 .name = "spapr_fwnmi", 2005 .version_id = 1, 2006 .minimum_version_id = 1, 2007 .needed = spapr_fwnmi_needed, 2008 .pre_save = spapr_fwnmi_pre_save, 2009 .fields = (VMStateField[]) { 2010 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2011 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2012 VMSTATE_END_OF_LIST() 2013 }, 2014 }; 2015 2016 static const VMStateDescription vmstate_spapr = { 2017 .name = "spapr", 2018 .version_id = 3, 2019 .minimum_version_id = 1, 2020 .pre_load = spapr_pre_load, 2021 .post_load = spapr_post_load, 2022 .pre_save = spapr_pre_save, 2023 .fields = (VMStateField[]) { 2024 /* used to be @next_irq */ 2025 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2026 2027 /* RTC offset */ 2028 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2029 2030 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2031 VMSTATE_END_OF_LIST() 2032 }, 2033 .subsections = (const VMStateDescription*[]) { 2034 &vmstate_spapr_ov5_cas, 2035 &vmstate_spapr_patb_entry, 2036 &vmstate_spapr_pending_events, 2037 &vmstate_spapr_cap_htm, 2038 &vmstate_spapr_cap_vsx, 2039 &vmstate_spapr_cap_dfp, 2040 &vmstate_spapr_cap_cfpc, 2041 &vmstate_spapr_cap_sbbc, 2042 &vmstate_spapr_cap_ibs, 2043 &vmstate_spapr_cap_hpt_maxpagesize, 2044 &vmstate_spapr_irq_map, 2045 &vmstate_spapr_cap_nested_kvm_hv, 2046 &vmstate_spapr_dtb, 2047 &vmstate_spapr_cap_large_decr, 2048 &vmstate_spapr_cap_ccf_assist, 2049 &vmstate_spapr_cap_fwnmi, 2050 &vmstate_spapr_fwnmi, 2051 NULL 2052 } 2053 }; 2054 2055 static int htab_save_setup(QEMUFile *f, void *opaque) 2056 { 2057 SpaprMachineState *spapr = opaque; 2058 2059 /* "Iteration" header */ 2060 if (!spapr->htab_shift) { 2061 qemu_put_be32(f, -1); 2062 } else { 2063 qemu_put_be32(f, spapr->htab_shift); 2064 } 2065 2066 if (spapr->htab) { 2067 spapr->htab_save_index = 0; 2068 spapr->htab_first_pass = true; 2069 } else { 2070 if (spapr->htab_shift) { 2071 assert(kvm_enabled()); 2072 } 2073 } 2074 2075 2076 return 0; 2077 } 2078 2079 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2080 int chunkstart, int n_valid, int n_invalid) 2081 { 2082 qemu_put_be32(f, chunkstart); 2083 qemu_put_be16(f, n_valid); 2084 qemu_put_be16(f, n_invalid); 2085 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2086 HASH_PTE_SIZE_64 * n_valid); 2087 } 2088 2089 static void htab_save_end_marker(QEMUFile *f) 2090 { 2091 qemu_put_be32(f, 0); 2092 qemu_put_be16(f, 0); 2093 qemu_put_be16(f, 0); 2094 } 2095 2096 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2097 int64_t max_ns) 2098 { 2099 bool has_timeout = max_ns != -1; 2100 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2101 int index = spapr->htab_save_index; 2102 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2103 2104 assert(spapr->htab_first_pass); 2105 2106 do { 2107 int chunkstart; 2108 2109 /* Consume invalid HPTEs */ 2110 while ((index < htabslots) 2111 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2112 CLEAN_HPTE(HPTE(spapr->htab, index)); 2113 index++; 2114 } 2115 2116 /* Consume valid HPTEs */ 2117 chunkstart = index; 2118 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2119 && HPTE_VALID(HPTE(spapr->htab, index))) { 2120 CLEAN_HPTE(HPTE(spapr->htab, index)); 2121 index++; 2122 } 2123 2124 if (index > chunkstart) { 2125 int n_valid = index - chunkstart; 2126 2127 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2128 2129 if (has_timeout && 2130 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2131 break; 2132 } 2133 } 2134 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2135 2136 if (index >= htabslots) { 2137 assert(index == htabslots); 2138 index = 0; 2139 spapr->htab_first_pass = false; 2140 } 2141 spapr->htab_save_index = index; 2142 } 2143 2144 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2145 int64_t max_ns) 2146 { 2147 bool final = max_ns < 0; 2148 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2149 int examined = 0, sent = 0; 2150 int index = spapr->htab_save_index; 2151 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2152 2153 assert(!spapr->htab_first_pass); 2154 2155 do { 2156 int chunkstart, invalidstart; 2157 2158 /* Consume non-dirty HPTEs */ 2159 while ((index < htabslots) 2160 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2161 index++; 2162 examined++; 2163 } 2164 2165 chunkstart = index; 2166 /* Consume valid dirty HPTEs */ 2167 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2168 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2169 && HPTE_VALID(HPTE(spapr->htab, index))) { 2170 CLEAN_HPTE(HPTE(spapr->htab, index)); 2171 index++; 2172 examined++; 2173 } 2174 2175 invalidstart = index; 2176 /* Consume invalid dirty HPTEs */ 2177 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2178 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2179 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2180 CLEAN_HPTE(HPTE(spapr->htab, index)); 2181 index++; 2182 examined++; 2183 } 2184 2185 if (index > chunkstart) { 2186 int n_valid = invalidstart - chunkstart; 2187 int n_invalid = index - invalidstart; 2188 2189 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2190 sent += index - chunkstart; 2191 2192 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2193 break; 2194 } 2195 } 2196 2197 if (examined >= htabslots) { 2198 break; 2199 } 2200 2201 if (index >= htabslots) { 2202 assert(index == htabslots); 2203 index = 0; 2204 } 2205 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2206 2207 if (index >= htabslots) { 2208 assert(index == htabslots); 2209 index = 0; 2210 } 2211 2212 spapr->htab_save_index = index; 2213 2214 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2215 } 2216 2217 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2218 #define MAX_KVM_BUF_SIZE 2048 2219 2220 static int htab_save_iterate(QEMUFile *f, void *opaque) 2221 { 2222 SpaprMachineState *spapr = opaque; 2223 int fd; 2224 int rc = 0; 2225 2226 /* Iteration header */ 2227 if (!spapr->htab_shift) { 2228 qemu_put_be32(f, -1); 2229 return 1; 2230 } else { 2231 qemu_put_be32(f, 0); 2232 } 2233 2234 if (!spapr->htab) { 2235 assert(kvm_enabled()); 2236 2237 fd = get_htab_fd(spapr); 2238 if (fd < 0) { 2239 return fd; 2240 } 2241 2242 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2243 if (rc < 0) { 2244 return rc; 2245 } 2246 } else if (spapr->htab_first_pass) { 2247 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2248 } else { 2249 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2250 } 2251 2252 htab_save_end_marker(f); 2253 2254 return rc; 2255 } 2256 2257 static int htab_save_complete(QEMUFile *f, void *opaque) 2258 { 2259 SpaprMachineState *spapr = opaque; 2260 int fd; 2261 2262 /* Iteration header */ 2263 if (!spapr->htab_shift) { 2264 qemu_put_be32(f, -1); 2265 return 0; 2266 } else { 2267 qemu_put_be32(f, 0); 2268 } 2269 2270 if (!spapr->htab) { 2271 int rc; 2272 2273 assert(kvm_enabled()); 2274 2275 fd = get_htab_fd(spapr); 2276 if (fd < 0) { 2277 return fd; 2278 } 2279 2280 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2281 if (rc < 0) { 2282 return rc; 2283 } 2284 } else { 2285 if (spapr->htab_first_pass) { 2286 htab_save_first_pass(f, spapr, -1); 2287 } 2288 htab_save_later_pass(f, spapr, -1); 2289 } 2290 2291 /* End marker */ 2292 htab_save_end_marker(f); 2293 2294 return 0; 2295 } 2296 2297 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2298 { 2299 SpaprMachineState *spapr = opaque; 2300 uint32_t section_hdr; 2301 int fd = -1; 2302 Error *local_err = NULL; 2303 2304 if (version_id < 1 || version_id > 1) { 2305 error_report("htab_load() bad version"); 2306 return -EINVAL; 2307 } 2308 2309 section_hdr = qemu_get_be32(f); 2310 2311 if (section_hdr == -1) { 2312 spapr_free_hpt(spapr); 2313 return 0; 2314 } 2315 2316 if (section_hdr) { 2317 /* First section gives the htab size */ 2318 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2319 if (local_err) { 2320 error_report_err(local_err); 2321 return -EINVAL; 2322 } 2323 return 0; 2324 } 2325 2326 if (!spapr->htab) { 2327 assert(kvm_enabled()); 2328 2329 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2330 if (fd < 0) { 2331 error_report_err(local_err); 2332 return fd; 2333 } 2334 } 2335 2336 while (true) { 2337 uint32_t index; 2338 uint16_t n_valid, n_invalid; 2339 2340 index = qemu_get_be32(f); 2341 n_valid = qemu_get_be16(f); 2342 n_invalid = qemu_get_be16(f); 2343 2344 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2345 /* End of Stream */ 2346 break; 2347 } 2348 2349 if ((index + n_valid + n_invalid) > 2350 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2351 /* Bad index in stream */ 2352 error_report( 2353 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2354 index, n_valid, n_invalid, spapr->htab_shift); 2355 return -EINVAL; 2356 } 2357 2358 if (spapr->htab) { 2359 if (n_valid) { 2360 qemu_get_buffer(f, HPTE(spapr->htab, index), 2361 HASH_PTE_SIZE_64 * n_valid); 2362 } 2363 if (n_invalid) { 2364 memset(HPTE(spapr->htab, index + n_valid), 0, 2365 HASH_PTE_SIZE_64 * n_invalid); 2366 } 2367 } else { 2368 int rc; 2369 2370 assert(fd >= 0); 2371 2372 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2373 if (rc < 0) { 2374 return rc; 2375 } 2376 } 2377 } 2378 2379 if (!spapr->htab) { 2380 assert(fd >= 0); 2381 close(fd); 2382 } 2383 2384 return 0; 2385 } 2386 2387 static void htab_save_cleanup(void *opaque) 2388 { 2389 SpaprMachineState *spapr = opaque; 2390 2391 close_htab_fd(spapr); 2392 } 2393 2394 static SaveVMHandlers savevm_htab_handlers = { 2395 .save_setup = htab_save_setup, 2396 .save_live_iterate = htab_save_iterate, 2397 .save_live_complete_precopy = htab_save_complete, 2398 .save_cleanup = htab_save_cleanup, 2399 .load_state = htab_load, 2400 }; 2401 2402 static void spapr_boot_set(void *opaque, const char *boot_device, 2403 Error **errp) 2404 { 2405 MachineState *machine = MACHINE(opaque); 2406 machine->boot_order = g_strdup(boot_device); 2407 } 2408 2409 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2410 { 2411 MachineState *machine = MACHINE(spapr); 2412 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2413 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2414 int i; 2415 2416 for (i = 0; i < nr_lmbs; i++) { 2417 uint64_t addr; 2418 2419 addr = i * lmb_size + machine->device_memory->base; 2420 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2421 addr / lmb_size); 2422 } 2423 } 2424 2425 /* 2426 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2427 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2428 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2429 */ 2430 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2431 { 2432 int i; 2433 2434 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2435 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2436 " is not aligned to %" PRIu64 " MiB", 2437 machine->ram_size, 2438 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2439 return; 2440 } 2441 2442 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2443 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2444 " is not aligned to %" PRIu64 " MiB", 2445 machine->ram_size, 2446 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2447 return; 2448 } 2449 2450 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2451 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2452 error_setg(errp, 2453 "Node %d memory size 0x%" PRIx64 2454 " is not aligned to %" PRIu64 " MiB", 2455 i, machine->numa_state->nodes[i].node_mem, 2456 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2457 return; 2458 } 2459 } 2460 } 2461 2462 /* find cpu slot in machine->possible_cpus by core_id */ 2463 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2464 { 2465 int index = id / ms->smp.threads; 2466 2467 if (index >= ms->possible_cpus->len) { 2468 return NULL; 2469 } 2470 if (idx) { 2471 *idx = index; 2472 } 2473 return &ms->possible_cpus->cpus[index]; 2474 } 2475 2476 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2477 { 2478 MachineState *ms = MACHINE(spapr); 2479 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2480 Error *local_err = NULL; 2481 bool vsmt_user = !!spapr->vsmt; 2482 int kvm_smt = kvmppc_smt_threads(); 2483 int ret; 2484 unsigned int smp_threads = ms->smp.threads; 2485 2486 if (!kvm_enabled() && (smp_threads > 1)) { 2487 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2488 "on a pseries machine"); 2489 goto out; 2490 } 2491 if (!is_power_of_2(smp_threads)) { 2492 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2493 "machine because it must be a power of 2", smp_threads); 2494 goto out; 2495 } 2496 2497 /* Detemine the VSMT mode to use: */ 2498 if (vsmt_user) { 2499 if (spapr->vsmt < smp_threads) { 2500 error_setg(&local_err, "Cannot support VSMT mode %d" 2501 " because it must be >= threads/core (%d)", 2502 spapr->vsmt, smp_threads); 2503 goto out; 2504 } 2505 /* In this case, spapr->vsmt has been set by the command line */ 2506 } else if (!smc->smp_threads_vsmt) { 2507 /* 2508 * Default VSMT value is tricky, because we need it to be as 2509 * consistent as possible (for migration), but this requires 2510 * changing it for at least some existing cases. We pick 8 as 2511 * the value that we'd get with KVM on POWER8, the 2512 * overwhelmingly common case in production systems. 2513 */ 2514 spapr->vsmt = MAX(8, smp_threads); 2515 } else { 2516 spapr->vsmt = smp_threads; 2517 } 2518 2519 /* KVM: If necessary, set the SMT mode: */ 2520 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2521 ret = kvmppc_set_smt_threads(spapr->vsmt); 2522 if (ret) { 2523 /* Looks like KVM isn't able to change VSMT mode */ 2524 error_setg(&local_err, 2525 "Failed to set KVM's VSMT mode to %d (errno %d)", 2526 spapr->vsmt, ret); 2527 /* We can live with that if the default one is big enough 2528 * for the number of threads, and a submultiple of the one 2529 * we want. In this case we'll waste some vcpu ids, but 2530 * behaviour will be correct */ 2531 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2532 warn_report_err(local_err); 2533 local_err = NULL; 2534 goto out; 2535 } else { 2536 if (!vsmt_user) { 2537 error_append_hint(&local_err, 2538 "On PPC, a VM with %d threads/core" 2539 " on a host with %d threads/core" 2540 " requires the use of VSMT mode %d.\n", 2541 smp_threads, kvm_smt, spapr->vsmt); 2542 } 2543 kvmppc_error_append_smt_possible_hint(&local_err); 2544 goto out; 2545 } 2546 } 2547 } 2548 /* else TCG: nothing to do currently */ 2549 out: 2550 error_propagate(errp, local_err); 2551 } 2552 2553 static void spapr_init_cpus(SpaprMachineState *spapr) 2554 { 2555 MachineState *machine = MACHINE(spapr); 2556 MachineClass *mc = MACHINE_GET_CLASS(machine); 2557 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2558 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2559 const CPUArchIdList *possible_cpus; 2560 unsigned int smp_cpus = machine->smp.cpus; 2561 unsigned int smp_threads = machine->smp.threads; 2562 unsigned int max_cpus = machine->smp.max_cpus; 2563 int boot_cores_nr = smp_cpus / smp_threads; 2564 int i; 2565 2566 possible_cpus = mc->possible_cpu_arch_ids(machine); 2567 if (mc->has_hotpluggable_cpus) { 2568 if (smp_cpus % smp_threads) { 2569 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2570 smp_cpus, smp_threads); 2571 exit(1); 2572 } 2573 if (max_cpus % smp_threads) { 2574 error_report("max_cpus (%u) must be multiple of threads (%u)", 2575 max_cpus, smp_threads); 2576 exit(1); 2577 } 2578 } else { 2579 if (max_cpus != smp_cpus) { 2580 error_report("This machine version does not support CPU hotplug"); 2581 exit(1); 2582 } 2583 boot_cores_nr = possible_cpus->len; 2584 } 2585 2586 if (smc->pre_2_10_has_unused_icps) { 2587 int i; 2588 2589 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2590 /* Dummy entries get deregistered when real ICPState objects 2591 * are registered during CPU core hotplug. 2592 */ 2593 pre_2_10_vmstate_register_dummy_icp(i); 2594 } 2595 } 2596 2597 for (i = 0; i < possible_cpus->len; i++) { 2598 int core_id = i * smp_threads; 2599 2600 if (mc->has_hotpluggable_cpus) { 2601 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2602 spapr_vcpu_id(spapr, core_id)); 2603 } 2604 2605 if (i < boot_cores_nr) { 2606 Object *core = object_new(type); 2607 int nr_threads = smp_threads; 2608 2609 /* Handle the partially filled core for older machine types */ 2610 if ((i + 1) * smp_threads >= smp_cpus) { 2611 nr_threads = smp_cpus - i * smp_threads; 2612 } 2613 2614 object_property_set_int(core, nr_threads, "nr-threads", 2615 &error_fatal); 2616 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2617 &error_fatal); 2618 object_property_set_bool(core, true, "realized", &error_fatal); 2619 2620 object_unref(core); 2621 } 2622 } 2623 } 2624 2625 static PCIHostState *spapr_create_default_phb(void) 2626 { 2627 DeviceState *dev; 2628 2629 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2630 qdev_prop_set_uint32(dev, "index", 0); 2631 qdev_init_nofail(dev); 2632 2633 return PCI_HOST_BRIDGE(dev); 2634 } 2635 2636 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2637 { 2638 MachineState *machine = MACHINE(spapr); 2639 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2640 hwaddr rma_size = machine->ram_size; 2641 hwaddr node0_size = spapr_node0_size(machine); 2642 2643 /* RMA has to fit in the first NUMA node */ 2644 rma_size = MIN(rma_size, node0_size); 2645 2646 /* 2647 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2648 * never exceed that 2649 */ 2650 rma_size = MIN(rma_size, 1 * TiB); 2651 2652 /* 2653 * Clamp the RMA size based on machine type. This is for 2654 * migration compatibility with older qemu versions, which limited 2655 * the RMA size for complicated and mostly bad reasons. 2656 */ 2657 if (smc->rma_limit) { 2658 rma_size = MIN(rma_size, smc->rma_limit); 2659 } 2660 2661 if (rma_size < MIN_RMA_SLOF) { 2662 error_setg(errp, 2663 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2664 "ldMiB guest RMA (Real Mode Area memory)", 2665 MIN_RMA_SLOF / MiB); 2666 return 0; 2667 } 2668 2669 return rma_size; 2670 } 2671 2672 /* pSeries LPAR / sPAPR hardware init */ 2673 static void spapr_machine_init(MachineState *machine) 2674 { 2675 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2676 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2677 MachineClass *mc = MACHINE_GET_CLASS(machine); 2678 const char *kernel_filename = machine->kernel_filename; 2679 const char *initrd_filename = machine->initrd_filename; 2680 PCIHostState *phb; 2681 int i; 2682 MemoryRegion *sysmem = get_system_memory(); 2683 long load_limit, fw_size; 2684 char *filename; 2685 Error *resize_hpt_err = NULL; 2686 2687 msi_nonbroken = true; 2688 2689 QLIST_INIT(&spapr->phbs); 2690 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2691 2692 /* Determine capabilities to run with */ 2693 spapr_caps_init(spapr); 2694 2695 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2696 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2697 /* 2698 * If the user explicitly requested a mode we should either 2699 * supply it, or fail completely (which we do below). But if 2700 * it's not set explicitly, we reset our mode to something 2701 * that works 2702 */ 2703 if (resize_hpt_err) { 2704 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2705 error_free(resize_hpt_err); 2706 resize_hpt_err = NULL; 2707 } else { 2708 spapr->resize_hpt = smc->resize_hpt_default; 2709 } 2710 } 2711 2712 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2713 2714 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2715 /* 2716 * User requested HPT resize, but this host can't supply it. Bail out 2717 */ 2718 error_report_err(resize_hpt_err); 2719 exit(1); 2720 } 2721 2722 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2723 2724 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2725 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2726 2727 /* 2728 * VSMT must be set in order to be able to compute VCPU ids, ie to 2729 * call spapr_max_server_number() or spapr_vcpu_id(). 2730 */ 2731 spapr_set_vsmt_mode(spapr, &error_fatal); 2732 2733 /* Set up Interrupt Controller before we create the VCPUs */ 2734 spapr_irq_init(spapr, &error_fatal); 2735 2736 /* Set up containers for ibm,client-architecture-support negotiated options 2737 */ 2738 spapr->ov5 = spapr_ovec_new(); 2739 spapr->ov5_cas = spapr_ovec_new(); 2740 2741 if (smc->dr_lmb_enabled) { 2742 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2743 spapr_validate_node_memory(machine, &error_fatal); 2744 } 2745 2746 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2747 2748 /* advertise support for dedicated HP event source to guests */ 2749 if (spapr->use_hotplug_event_source) { 2750 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2751 } 2752 2753 /* advertise support for HPT resizing */ 2754 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2755 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2756 } 2757 2758 /* advertise support for ibm,dyamic-memory-v2 */ 2759 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2760 2761 /* advertise XIVE on POWER9 machines */ 2762 if (spapr->irq->xive) { 2763 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2764 } 2765 2766 /* init CPUs */ 2767 spapr_init_cpus(spapr); 2768 2769 /* 2770 * check we don't have a memory-less/cpu-less NUMA node 2771 * Firmware relies on the existing memory/cpu topology to provide the 2772 * NUMA topology to the kernel. 2773 * And the linux kernel needs to know the NUMA topology at start 2774 * to be able to hotplug CPUs later. 2775 */ 2776 if (machine->numa_state->num_nodes) { 2777 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2778 /* check for memory-less node */ 2779 if (machine->numa_state->nodes[i].node_mem == 0) { 2780 CPUState *cs; 2781 int found = 0; 2782 /* check for cpu-less node */ 2783 CPU_FOREACH(cs) { 2784 PowerPCCPU *cpu = POWERPC_CPU(cs); 2785 if (cpu->node_id == i) { 2786 found = 1; 2787 break; 2788 } 2789 } 2790 /* memory-less and cpu-less node */ 2791 if (!found) { 2792 error_report( 2793 "Memory-less/cpu-less nodes are not supported (node %d)", 2794 i); 2795 exit(1); 2796 } 2797 } 2798 } 2799 2800 } 2801 2802 /* 2803 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2804 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2805 * called from vPHB reset handler so we initialize the counter here. 2806 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2807 * must be equally distant from any other node. 2808 * The final value of spapr->gpu_numa_id is going to be written to 2809 * max-associativity-domains in spapr_build_fdt(). 2810 */ 2811 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2812 2813 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2814 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2815 spapr->max_compat_pvr)) { 2816 /* KVM and TCG always allow GTSE with radix... */ 2817 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2818 } 2819 /* ... but not with hash (currently). */ 2820 2821 if (kvm_enabled()) { 2822 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2823 kvmppc_enable_logical_ci_hcalls(); 2824 kvmppc_enable_set_mode_hcall(); 2825 2826 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2827 kvmppc_enable_clear_ref_mod_hcalls(); 2828 2829 /* Enable H_PAGE_INIT */ 2830 kvmppc_enable_h_page_init(); 2831 } 2832 2833 /* map RAM */ 2834 memory_region_add_subregion(sysmem, 0, machine->ram); 2835 2836 /* always allocate the device memory information */ 2837 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2838 2839 /* initialize hotplug memory address space */ 2840 if (machine->ram_size < machine->maxram_size) { 2841 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2842 /* 2843 * Limit the number of hotpluggable memory slots to half the number 2844 * slots that KVM supports, leaving the other half for PCI and other 2845 * devices. However ensure that number of slots doesn't drop below 32. 2846 */ 2847 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2848 SPAPR_MAX_RAM_SLOTS; 2849 2850 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2851 max_memslots = SPAPR_MAX_RAM_SLOTS; 2852 } 2853 if (machine->ram_slots > max_memslots) { 2854 error_report("Specified number of memory slots %" 2855 PRIu64" exceeds max supported %d", 2856 machine->ram_slots, max_memslots); 2857 exit(1); 2858 } 2859 2860 machine->device_memory->base = ROUND_UP(machine->ram_size, 2861 SPAPR_DEVICE_MEM_ALIGN); 2862 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2863 "device-memory", device_mem_size); 2864 memory_region_add_subregion(sysmem, machine->device_memory->base, 2865 &machine->device_memory->mr); 2866 } 2867 2868 if (smc->dr_lmb_enabled) { 2869 spapr_create_lmb_dr_connectors(spapr); 2870 } 2871 2872 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2873 /* Create the error string for live migration blocker */ 2874 error_setg(&spapr->fwnmi_migration_blocker, 2875 "A machine check is being handled during migration. The handler" 2876 "may run and log hardware error on the destination"); 2877 } 2878 2879 if (mc->nvdimm_supported) { 2880 spapr_create_nvdimm_dr_connectors(spapr); 2881 } 2882 2883 /* Set up RTAS event infrastructure */ 2884 spapr_events_init(spapr); 2885 2886 /* Set up the RTC RTAS interfaces */ 2887 spapr_rtc_create(spapr); 2888 2889 /* Set up VIO bus */ 2890 spapr->vio_bus = spapr_vio_bus_init(); 2891 2892 for (i = 0; i < serial_max_hds(); i++) { 2893 if (serial_hd(i)) { 2894 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2895 } 2896 } 2897 2898 /* We always have at least the nvram device on VIO */ 2899 spapr_create_nvram(spapr); 2900 2901 /* 2902 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2903 * connectors (described in root DT node's "ibm,drc-types" property) 2904 * are pre-initialized here. additional child connectors (such as 2905 * connectors for a PHBs PCI slots) are added as needed during their 2906 * parent's realization. 2907 */ 2908 if (smc->dr_phb_enabled) { 2909 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2910 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2911 } 2912 } 2913 2914 /* Set up PCI */ 2915 spapr_pci_rtas_init(); 2916 2917 phb = spapr_create_default_phb(); 2918 2919 for (i = 0; i < nb_nics; i++) { 2920 NICInfo *nd = &nd_table[i]; 2921 2922 if (!nd->model) { 2923 nd->model = g_strdup("spapr-vlan"); 2924 } 2925 2926 if (g_str_equal(nd->model, "spapr-vlan") || 2927 g_str_equal(nd->model, "ibmveth")) { 2928 spapr_vlan_create(spapr->vio_bus, nd); 2929 } else { 2930 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2931 } 2932 } 2933 2934 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2935 spapr_vscsi_create(spapr->vio_bus); 2936 } 2937 2938 /* Graphics */ 2939 if (spapr_vga_init(phb->bus, &error_fatal)) { 2940 spapr->has_graphics = true; 2941 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2942 } 2943 2944 if (machine->usb) { 2945 if (smc->use_ohci_by_default) { 2946 pci_create_simple(phb->bus, -1, "pci-ohci"); 2947 } else { 2948 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2949 } 2950 2951 if (spapr->has_graphics) { 2952 USBBus *usb_bus = usb_bus_find(-1); 2953 2954 usb_create_simple(usb_bus, "usb-kbd"); 2955 usb_create_simple(usb_bus, "usb-mouse"); 2956 } 2957 } 2958 2959 if (kernel_filename) { 2960 uint64_t lowaddr = 0; 2961 2962 spapr->kernel_size = load_elf(kernel_filename, NULL, 2963 translate_kernel_address, spapr, 2964 NULL, &lowaddr, NULL, NULL, 1, 2965 PPC_ELF_MACHINE, 0, 0); 2966 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2967 spapr->kernel_size = load_elf(kernel_filename, NULL, 2968 translate_kernel_address, spapr, NULL, 2969 &lowaddr, NULL, NULL, 0, 2970 PPC_ELF_MACHINE, 2971 0, 0); 2972 spapr->kernel_le = spapr->kernel_size > 0; 2973 } 2974 if (spapr->kernel_size < 0) { 2975 error_report("error loading %s: %s", kernel_filename, 2976 load_elf_strerror(spapr->kernel_size)); 2977 exit(1); 2978 } 2979 2980 /* load initrd */ 2981 if (initrd_filename) { 2982 /* Try to locate the initrd in the gap between the kernel 2983 * and the firmware. Add a bit of space just in case 2984 */ 2985 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2986 + 0x1ffff) & ~0xffff; 2987 spapr->initrd_size = load_image_targphys(initrd_filename, 2988 spapr->initrd_base, 2989 load_limit 2990 - spapr->initrd_base); 2991 if (spapr->initrd_size < 0) { 2992 error_report("could not load initial ram disk '%s'", 2993 initrd_filename); 2994 exit(1); 2995 } 2996 } 2997 } 2998 2999 if (bios_name == NULL) { 3000 bios_name = FW_FILE_NAME; 3001 } 3002 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3003 if (!filename) { 3004 error_report("Could not find LPAR firmware '%s'", bios_name); 3005 exit(1); 3006 } 3007 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3008 if (fw_size <= 0) { 3009 error_report("Could not load LPAR firmware '%s'", filename); 3010 exit(1); 3011 } 3012 g_free(filename); 3013 3014 /* FIXME: Should register things through the MachineState's qdev 3015 * interface, this is a legacy from the sPAPREnvironment structure 3016 * which predated MachineState but had a similar function */ 3017 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3018 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3019 &savevm_htab_handlers, spapr); 3020 3021 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3022 &error_fatal); 3023 3024 qemu_register_boot_set(spapr_boot_set, spapr); 3025 3026 /* 3027 * Nothing needs to be done to resume a suspended guest because 3028 * suspending does not change the machine state, so no need for 3029 * a ->wakeup method. 3030 */ 3031 qemu_register_wakeup_support(); 3032 3033 if (kvm_enabled()) { 3034 /* to stop and start vmclock */ 3035 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3036 &spapr->tb); 3037 3038 kvmppc_spapr_enable_inkernel_multitce(); 3039 } 3040 3041 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3042 } 3043 3044 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3045 { 3046 if (!vm_type) { 3047 return 0; 3048 } 3049 3050 if (!strcmp(vm_type, "HV")) { 3051 return 1; 3052 } 3053 3054 if (!strcmp(vm_type, "PR")) { 3055 return 2; 3056 } 3057 3058 error_report("Unknown kvm-type specified '%s'", vm_type); 3059 exit(1); 3060 } 3061 3062 /* 3063 * Implementation of an interface to adjust firmware path 3064 * for the bootindex property handling. 3065 */ 3066 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3067 DeviceState *dev) 3068 { 3069 #define CAST(type, obj, name) \ 3070 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3071 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3072 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3073 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3074 3075 if (d) { 3076 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3077 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3078 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3079 3080 if (spapr) { 3081 /* 3082 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3083 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3084 * 0x8000 | (target << 8) | (bus << 5) | lun 3085 * (see the "Logical unit addressing format" table in SAM5) 3086 */ 3087 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3088 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3089 (uint64_t)id << 48); 3090 } else if (virtio) { 3091 /* 3092 * We use SRP luns of the form 01000000 | (target << 8) | lun 3093 * in the top 32 bits of the 64-bit LUN 3094 * Note: the quote above is from SLOF and it is wrong, 3095 * the actual binding is: 3096 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3097 */ 3098 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3099 if (d->lun >= 256) { 3100 /* Use the LUN "flat space addressing method" */ 3101 id |= 0x4000; 3102 } 3103 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3104 (uint64_t)id << 32); 3105 } else if (usb) { 3106 /* 3107 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3108 * in the top 32 bits of the 64-bit LUN 3109 */ 3110 unsigned usb_port = atoi(usb->port->path); 3111 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3112 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3113 (uint64_t)id << 32); 3114 } 3115 } 3116 3117 /* 3118 * SLOF probes the USB devices, and if it recognizes that the device is a 3119 * storage device, it changes its name to "storage" instead of "usb-host", 3120 * and additionally adds a child node for the SCSI LUN, so the correct 3121 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3122 */ 3123 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3124 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3125 if (usb_host_dev_is_scsi_storage(usbdev)) { 3126 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3127 } 3128 } 3129 3130 if (phb) { 3131 /* Replace "pci" with "pci@800000020000000" */ 3132 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3133 } 3134 3135 if (vsc) { 3136 /* Same logic as virtio above */ 3137 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3138 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3139 } 3140 3141 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3142 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3143 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3144 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3145 } 3146 3147 return NULL; 3148 } 3149 3150 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3151 { 3152 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3153 3154 return g_strdup(spapr->kvm_type); 3155 } 3156 3157 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3158 { 3159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3160 3161 g_free(spapr->kvm_type); 3162 spapr->kvm_type = g_strdup(value); 3163 } 3164 3165 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3166 { 3167 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3168 3169 return spapr->use_hotplug_event_source; 3170 } 3171 3172 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3173 Error **errp) 3174 { 3175 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 spapr->use_hotplug_event_source = value; 3178 } 3179 3180 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3181 { 3182 return true; 3183 } 3184 3185 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3186 { 3187 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3188 3189 switch (spapr->resize_hpt) { 3190 case SPAPR_RESIZE_HPT_DEFAULT: 3191 return g_strdup("default"); 3192 case SPAPR_RESIZE_HPT_DISABLED: 3193 return g_strdup("disabled"); 3194 case SPAPR_RESIZE_HPT_ENABLED: 3195 return g_strdup("enabled"); 3196 case SPAPR_RESIZE_HPT_REQUIRED: 3197 return g_strdup("required"); 3198 } 3199 g_assert_not_reached(); 3200 } 3201 3202 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3203 { 3204 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3205 3206 if (strcmp(value, "default") == 0) { 3207 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3208 } else if (strcmp(value, "disabled") == 0) { 3209 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3210 } else if (strcmp(value, "enabled") == 0) { 3211 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3212 } else if (strcmp(value, "required") == 0) { 3213 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3214 } else { 3215 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3216 } 3217 } 3218 3219 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3220 void *opaque, Error **errp) 3221 { 3222 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3223 } 3224 3225 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3226 void *opaque, Error **errp) 3227 { 3228 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3229 } 3230 3231 static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name, 3232 void *opaque, Error **errp) 3233 { 3234 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3235 } 3236 3237 static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name, 3238 void *opaque, Error **errp) 3239 { 3240 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3241 } 3242 3243 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3244 { 3245 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3246 3247 if (spapr->irq == &spapr_irq_xics_legacy) { 3248 return g_strdup("legacy"); 3249 } else if (spapr->irq == &spapr_irq_xics) { 3250 return g_strdup("xics"); 3251 } else if (spapr->irq == &spapr_irq_xive) { 3252 return g_strdup("xive"); 3253 } else if (spapr->irq == &spapr_irq_dual) { 3254 return g_strdup("dual"); 3255 } 3256 g_assert_not_reached(); 3257 } 3258 3259 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3260 { 3261 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3262 3263 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3264 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3265 return; 3266 } 3267 3268 /* The legacy IRQ backend can not be set */ 3269 if (strcmp(value, "xics") == 0) { 3270 spapr->irq = &spapr_irq_xics; 3271 } else if (strcmp(value, "xive") == 0) { 3272 spapr->irq = &spapr_irq_xive; 3273 } else if (strcmp(value, "dual") == 0) { 3274 spapr->irq = &spapr_irq_dual; 3275 } else { 3276 error_setg(errp, "Bad value for \"ic-mode\" property"); 3277 } 3278 } 3279 3280 static char *spapr_get_host_model(Object *obj, Error **errp) 3281 { 3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3283 3284 return g_strdup(spapr->host_model); 3285 } 3286 3287 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3288 { 3289 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3290 3291 g_free(spapr->host_model); 3292 spapr->host_model = g_strdup(value); 3293 } 3294 3295 static char *spapr_get_host_serial(Object *obj, Error **errp) 3296 { 3297 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3298 3299 return g_strdup(spapr->host_serial); 3300 } 3301 3302 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3303 { 3304 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3305 3306 g_free(spapr->host_serial); 3307 spapr->host_serial = g_strdup(value); 3308 } 3309 3310 static void spapr_instance_init(Object *obj) 3311 { 3312 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3313 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3314 3315 spapr->htab_fd = -1; 3316 spapr->use_hotplug_event_source = true; 3317 object_property_add_str(obj, "kvm-type", 3318 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3319 object_property_set_description(obj, "kvm-type", 3320 "Specifies the KVM virtualization mode (HV, PR)", 3321 NULL); 3322 object_property_add_bool(obj, "modern-hotplug-events", 3323 spapr_get_modern_hotplug_events, 3324 spapr_set_modern_hotplug_events, 3325 NULL); 3326 object_property_set_description(obj, "modern-hotplug-events", 3327 "Use dedicated hotplug event mechanism in" 3328 " place of standard EPOW events when possible" 3329 " (required for memory hot-unplug support)", 3330 NULL); 3331 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3332 "Maximum permitted CPU compatibility mode", 3333 &error_fatal); 3334 3335 object_property_add_str(obj, "resize-hpt", 3336 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3337 object_property_set_description(obj, "resize-hpt", 3338 "Resizing of the Hash Page Table (enabled, disabled, required)", 3339 NULL); 3340 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3341 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3342 object_property_set_description(obj, "vsmt", 3343 "Virtual SMT: KVM behaves as if this were" 3344 " the host's SMT mode", &error_abort); 3345 object_property_add_bool(obj, "vfio-no-msix-emulation", 3346 spapr_get_msix_emulation, NULL, NULL); 3347 3348 object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr, 3349 spapr_set_kernel_addr, NULL, &spapr->kernel_addr, 3350 &error_abort); 3351 object_property_set_description(obj, "kernel-addr", 3352 stringify(KERNEL_LOAD_ADDR) 3353 " for -kernel is the default", 3354 NULL); 3355 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3356 /* The machine class defines the default interrupt controller mode */ 3357 spapr->irq = smc->irq; 3358 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3359 spapr_set_ic_mode, NULL); 3360 object_property_set_description(obj, "ic-mode", 3361 "Specifies the interrupt controller mode (xics, xive, dual)", 3362 NULL); 3363 3364 object_property_add_str(obj, "host-model", 3365 spapr_get_host_model, spapr_set_host_model, 3366 &error_abort); 3367 object_property_set_description(obj, "host-model", 3368 "Host model to advertise in guest device tree", &error_abort); 3369 object_property_add_str(obj, "host-serial", 3370 spapr_get_host_serial, spapr_set_host_serial, 3371 &error_abort); 3372 object_property_set_description(obj, "host-serial", 3373 "Host serial number to advertise in guest device tree", &error_abort); 3374 } 3375 3376 static void spapr_machine_finalizefn(Object *obj) 3377 { 3378 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3379 3380 g_free(spapr->kvm_type); 3381 } 3382 3383 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3384 { 3385 cpu_synchronize_state(cs); 3386 ppc_cpu_do_system_reset(cs); 3387 } 3388 3389 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3390 { 3391 CPUState *cs; 3392 3393 CPU_FOREACH(cs) { 3394 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3395 } 3396 } 3397 3398 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3399 void *fdt, int *fdt_start_offset, Error **errp) 3400 { 3401 uint64_t addr; 3402 uint32_t node; 3403 3404 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3405 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3406 &error_abort); 3407 *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr, 3408 SPAPR_MEMORY_BLOCK_SIZE); 3409 return 0; 3410 } 3411 3412 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3413 bool dedicated_hp_event_source, Error **errp) 3414 { 3415 SpaprDrc *drc; 3416 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3417 int i; 3418 uint64_t addr = addr_start; 3419 bool hotplugged = spapr_drc_hotplugged(dev); 3420 Error *local_err = NULL; 3421 3422 for (i = 0; i < nr_lmbs; i++) { 3423 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3424 addr / SPAPR_MEMORY_BLOCK_SIZE); 3425 g_assert(drc); 3426 3427 spapr_drc_attach(drc, dev, &local_err); 3428 if (local_err) { 3429 while (addr > addr_start) { 3430 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3431 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3432 addr / SPAPR_MEMORY_BLOCK_SIZE); 3433 spapr_drc_detach(drc); 3434 } 3435 error_propagate(errp, local_err); 3436 return; 3437 } 3438 if (!hotplugged) { 3439 spapr_drc_reset(drc); 3440 } 3441 addr += SPAPR_MEMORY_BLOCK_SIZE; 3442 } 3443 /* send hotplug notification to the 3444 * guest only in case of hotplugged memory 3445 */ 3446 if (hotplugged) { 3447 if (dedicated_hp_event_source) { 3448 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3449 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3450 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3451 nr_lmbs, 3452 spapr_drc_index(drc)); 3453 } else { 3454 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3455 nr_lmbs); 3456 } 3457 } 3458 } 3459 3460 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3461 Error **errp) 3462 { 3463 Error *local_err = NULL; 3464 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3465 PCDIMMDevice *dimm = PC_DIMM(dev); 3466 uint64_t size, addr, slot; 3467 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3468 3469 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3470 3471 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3472 if (local_err) { 3473 goto out; 3474 } 3475 3476 if (!is_nvdimm) { 3477 addr = object_property_get_uint(OBJECT(dimm), 3478 PC_DIMM_ADDR_PROP, &local_err); 3479 if (local_err) { 3480 goto out_unplug; 3481 } 3482 spapr_add_lmbs(dev, addr, size, 3483 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3484 &local_err); 3485 } else { 3486 slot = object_property_get_uint(OBJECT(dimm), 3487 PC_DIMM_SLOT_PROP, &local_err); 3488 if (local_err) { 3489 goto out_unplug; 3490 } 3491 spapr_add_nvdimm(dev, slot, &local_err); 3492 } 3493 3494 if (local_err) { 3495 goto out_unplug; 3496 } 3497 3498 return; 3499 3500 out_unplug: 3501 pc_dimm_unplug(dimm, MACHINE(ms)); 3502 out: 3503 error_propagate(errp, local_err); 3504 } 3505 3506 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3507 Error **errp) 3508 { 3509 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3510 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3511 const MachineClass *mc = MACHINE_CLASS(smc); 3512 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3513 PCDIMMDevice *dimm = PC_DIMM(dev); 3514 Error *local_err = NULL; 3515 uint64_t size; 3516 Object *memdev; 3517 hwaddr pagesize; 3518 3519 if (!smc->dr_lmb_enabled) { 3520 error_setg(errp, "Memory hotplug not supported for this machine"); 3521 return; 3522 } 3523 3524 if (is_nvdimm && !mc->nvdimm_supported) { 3525 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3526 return; 3527 } 3528 3529 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3530 if (local_err) { 3531 error_propagate(errp, local_err); 3532 return; 3533 } 3534 3535 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3536 error_setg(errp, "Hotplugged memory size must be a multiple of " 3537 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3538 return; 3539 } else if (is_nvdimm) { 3540 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3541 if (local_err) { 3542 error_propagate(errp, local_err); 3543 return; 3544 } 3545 } 3546 3547 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3548 &error_abort); 3549 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3550 spapr_check_pagesize(spapr, pagesize, &local_err); 3551 if (local_err) { 3552 error_propagate(errp, local_err); 3553 return; 3554 } 3555 3556 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3557 } 3558 3559 struct SpaprDimmState { 3560 PCDIMMDevice *dimm; 3561 uint32_t nr_lmbs; 3562 QTAILQ_ENTRY(SpaprDimmState) next; 3563 }; 3564 3565 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3566 PCDIMMDevice *dimm) 3567 { 3568 SpaprDimmState *dimm_state = NULL; 3569 3570 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3571 if (dimm_state->dimm == dimm) { 3572 break; 3573 } 3574 } 3575 return dimm_state; 3576 } 3577 3578 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3579 uint32_t nr_lmbs, 3580 PCDIMMDevice *dimm) 3581 { 3582 SpaprDimmState *ds = NULL; 3583 3584 /* 3585 * If this request is for a DIMM whose removal had failed earlier 3586 * (due to guest's refusal to remove the LMBs), we would have this 3587 * dimm already in the pending_dimm_unplugs list. In that 3588 * case don't add again. 3589 */ 3590 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3591 if (!ds) { 3592 ds = g_malloc0(sizeof(SpaprDimmState)); 3593 ds->nr_lmbs = nr_lmbs; 3594 ds->dimm = dimm; 3595 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3596 } 3597 return ds; 3598 } 3599 3600 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3601 SpaprDimmState *dimm_state) 3602 { 3603 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3604 g_free(dimm_state); 3605 } 3606 3607 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3608 PCDIMMDevice *dimm) 3609 { 3610 SpaprDrc *drc; 3611 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3612 &error_abort); 3613 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3614 uint32_t avail_lmbs = 0; 3615 uint64_t addr_start, addr; 3616 int i; 3617 3618 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3619 &error_abort); 3620 3621 addr = addr_start; 3622 for (i = 0; i < nr_lmbs; i++) { 3623 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3624 addr / SPAPR_MEMORY_BLOCK_SIZE); 3625 g_assert(drc); 3626 if (drc->dev) { 3627 avail_lmbs++; 3628 } 3629 addr += SPAPR_MEMORY_BLOCK_SIZE; 3630 } 3631 3632 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3633 } 3634 3635 /* Callback to be called during DRC release. */ 3636 void spapr_lmb_release(DeviceState *dev) 3637 { 3638 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3639 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3640 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3641 3642 /* This information will get lost if a migration occurs 3643 * during the unplug process. In this case recover it. */ 3644 if (ds == NULL) { 3645 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3646 g_assert(ds); 3647 /* The DRC being examined by the caller at least must be counted */ 3648 g_assert(ds->nr_lmbs); 3649 } 3650 3651 if (--ds->nr_lmbs) { 3652 return; 3653 } 3654 3655 /* 3656 * Now that all the LMBs have been removed by the guest, call the 3657 * unplug handler chain. This can never fail. 3658 */ 3659 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3660 object_unparent(OBJECT(dev)); 3661 } 3662 3663 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3664 { 3665 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3666 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3667 3668 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3669 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3670 spapr_pending_dimm_unplugs_remove(spapr, ds); 3671 } 3672 3673 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3674 DeviceState *dev, Error **errp) 3675 { 3676 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3677 Error *local_err = NULL; 3678 PCDIMMDevice *dimm = PC_DIMM(dev); 3679 uint32_t nr_lmbs; 3680 uint64_t size, addr_start, addr; 3681 int i; 3682 SpaprDrc *drc; 3683 3684 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3685 error_setg(&local_err, 3686 "nvdimm device hot unplug is not supported yet."); 3687 goto out; 3688 } 3689 3690 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3691 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3692 3693 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3694 &local_err); 3695 if (local_err) { 3696 goto out; 3697 } 3698 3699 /* 3700 * An existing pending dimm state for this DIMM means that there is an 3701 * unplug operation in progress, waiting for the spapr_lmb_release 3702 * callback to complete the job (BQL can't cover that far). In this case, 3703 * bail out to avoid detaching DRCs that were already released. 3704 */ 3705 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3706 error_setg(&local_err, 3707 "Memory unplug already in progress for device %s", 3708 dev->id); 3709 goto out; 3710 } 3711 3712 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3713 3714 addr = addr_start; 3715 for (i = 0; i < nr_lmbs; i++) { 3716 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3717 addr / SPAPR_MEMORY_BLOCK_SIZE); 3718 g_assert(drc); 3719 3720 spapr_drc_detach(drc); 3721 addr += SPAPR_MEMORY_BLOCK_SIZE; 3722 } 3723 3724 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3725 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3726 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3727 nr_lmbs, spapr_drc_index(drc)); 3728 out: 3729 error_propagate(errp, local_err); 3730 } 3731 3732 /* Callback to be called during DRC release. */ 3733 void spapr_core_release(DeviceState *dev) 3734 { 3735 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3736 3737 /* Call the unplug handler chain. This can never fail. */ 3738 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3739 object_unparent(OBJECT(dev)); 3740 } 3741 3742 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3743 { 3744 MachineState *ms = MACHINE(hotplug_dev); 3745 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3746 CPUCore *cc = CPU_CORE(dev); 3747 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3748 3749 if (smc->pre_2_10_has_unused_icps) { 3750 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3751 int i; 3752 3753 for (i = 0; i < cc->nr_threads; i++) { 3754 CPUState *cs = CPU(sc->threads[i]); 3755 3756 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3757 } 3758 } 3759 3760 assert(core_slot); 3761 core_slot->cpu = NULL; 3762 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3763 } 3764 3765 static 3766 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3767 Error **errp) 3768 { 3769 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3770 int index; 3771 SpaprDrc *drc; 3772 CPUCore *cc = CPU_CORE(dev); 3773 3774 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3775 error_setg(errp, "Unable to find CPU core with core-id: %d", 3776 cc->core_id); 3777 return; 3778 } 3779 if (index == 0) { 3780 error_setg(errp, "Boot CPU core may not be unplugged"); 3781 return; 3782 } 3783 3784 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3785 spapr_vcpu_id(spapr, cc->core_id)); 3786 g_assert(drc); 3787 3788 if (!spapr_drc_unplug_requested(drc)) { 3789 spapr_drc_detach(drc); 3790 spapr_hotplug_req_remove_by_index(drc); 3791 } 3792 } 3793 3794 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3795 void *fdt, int *fdt_start_offset, Error **errp) 3796 { 3797 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3798 CPUState *cs = CPU(core->threads[0]); 3799 PowerPCCPU *cpu = POWERPC_CPU(cs); 3800 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3801 int id = spapr_get_vcpu_id(cpu); 3802 char *nodename; 3803 int offset; 3804 3805 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3806 offset = fdt_add_subnode(fdt, 0, nodename); 3807 g_free(nodename); 3808 3809 spapr_dt_cpu(cs, fdt, offset, spapr); 3810 3811 *fdt_start_offset = offset; 3812 return 0; 3813 } 3814 3815 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3816 Error **errp) 3817 { 3818 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3819 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3820 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3821 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3822 CPUCore *cc = CPU_CORE(dev); 3823 CPUState *cs; 3824 SpaprDrc *drc; 3825 Error *local_err = NULL; 3826 CPUArchId *core_slot; 3827 int index; 3828 bool hotplugged = spapr_drc_hotplugged(dev); 3829 int i; 3830 3831 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3832 if (!core_slot) { 3833 error_setg(errp, "Unable to find CPU core with core-id: %d", 3834 cc->core_id); 3835 return; 3836 } 3837 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3838 spapr_vcpu_id(spapr, cc->core_id)); 3839 3840 g_assert(drc || !mc->has_hotpluggable_cpus); 3841 3842 if (drc) { 3843 spapr_drc_attach(drc, dev, &local_err); 3844 if (local_err) { 3845 error_propagate(errp, local_err); 3846 return; 3847 } 3848 3849 if (hotplugged) { 3850 /* 3851 * Send hotplug notification interrupt to the guest only 3852 * in case of hotplugged CPUs. 3853 */ 3854 spapr_hotplug_req_add_by_index(drc); 3855 } else { 3856 spapr_drc_reset(drc); 3857 } 3858 } 3859 3860 core_slot->cpu = OBJECT(dev); 3861 3862 if (smc->pre_2_10_has_unused_icps) { 3863 for (i = 0; i < cc->nr_threads; i++) { 3864 cs = CPU(core->threads[i]); 3865 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3866 } 3867 } 3868 3869 /* 3870 * Set compatibility mode to match the boot CPU, which was either set 3871 * by the machine reset code or by CAS. 3872 */ 3873 if (hotplugged) { 3874 for (i = 0; i < cc->nr_threads; i++) { 3875 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3876 &local_err); 3877 if (local_err) { 3878 error_propagate(errp, local_err); 3879 return; 3880 } 3881 } 3882 } 3883 } 3884 3885 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3886 Error **errp) 3887 { 3888 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3889 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3890 Error *local_err = NULL; 3891 CPUCore *cc = CPU_CORE(dev); 3892 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3893 const char *type = object_get_typename(OBJECT(dev)); 3894 CPUArchId *core_slot; 3895 int index; 3896 unsigned int smp_threads = machine->smp.threads; 3897 3898 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3899 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3900 goto out; 3901 } 3902 3903 if (strcmp(base_core_type, type)) { 3904 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3905 goto out; 3906 } 3907 3908 if (cc->core_id % smp_threads) { 3909 error_setg(&local_err, "invalid core id %d", cc->core_id); 3910 goto out; 3911 } 3912 3913 /* 3914 * In general we should have homogeneous threads-per-core, but old 3915 * (pre hotplug support) machine types allow the last core to have 3916 * reduced threads as a compatibility hack for when we allowed 3917 * total vcpus not a multiple of threads-per-core. 3918 */ 3919 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3920 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3921 cc->nr_threads, smp_threads); 3922 goto out; 3923 } 3924 3925 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3926 if (!core_slot) { 3927 error_setg(&local_err, "core id %d out of range", cc->core_id); 3928 goto out; 3929 } 3930 3931 if (core_slot->cpu) { 3932 error_setg(&local_err, "core %d already populated", cc->core_id); 3933 goto out; 3934 } 3935 3936 numa_cpu_pre_plug(core_slot, dev, &local_err); 3937 3938 out: 3939 error_propagate(errp, local_err); 3940 } 3941 3942 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3943 void *fdt, int *fdt_start_offset, Error **errp) 3944 { 3945 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3946 int intc_phandle; 3947 3948 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3949 if (intc_phandle <= 0) { 3950 return -1; 3951 } 3952 3953 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3954 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3955 return -1; 3956 } 3957 3958 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3959 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3960 3961 return 0; 3962 } 3963 3964 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3965 Error **errp) 3966 { 3967 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3968 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3969 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3970 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3971 3972 if (dev->hotplugged && !smc->dr_phb_enabled) { 3973 error_setg(errp, "PHB hotplug not supported for this machine"); 3974 return; 3975 } 3976 3977 if (sphb->index == (uint32_t)-1) { 3978 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3979 return; 3980 } 3981 3982 /* 3983 * This will check that sphb->index doesn't exceed the maximum number of 3984 * PHBs for the current machine type. 3985 */ 3986 smc->phb_placement(spapr, sphb->index, 3987 &sphb->buid, &sphb->io_win_addr, 3988 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3989 windows_supported, sphb->dma_liobn, 3990 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3991 errp); 3992 } 3993 3994 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3995 Error **errp) 3996 { 3997 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3998 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3999 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4000 SpaprDrc *drc; 4001 bool hotplugged = spapr_drc_hotplugged(dev); 4002 Error *local_err = NULL; 4003 4004 if (!smc->dr_phb_enabled) { 4005 return; 4006 } 4007 4008 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4009 /* hotplug hooks should check it's enabled before getting this far */ 4010 assert(drc); 4011 4012 spapr_drc_attach(drc, DEVICE(dev), &local_err); 4013 if (local_err) { 4014 error_propagate(errp, local_err); 4015 return; 4016 } 4017 4018 if (hotplugged) { 4019 spapr_hotplug_req_add_by_index(drc); 4020 } else { 4021 spapr_drc_reset(drc); 4022 } 4023 } 4024 4025 void spapr_phb_release(DeviceState *dev) 4026 { 4027 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4028 4029 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4030 object_unparent(OBJECT(dev)); 4031 } 4032 4033 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4034 { 4035 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4036 } 4037 4038 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4039 DeviceState *dev, Error **errp) 4040 { 4041 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4042 SpaprDrc *drc; 4043 4044 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4045 assert(drc); 4046 4047 if (!spapr_drc_unplug_requested(drc)) { 4048 spapr_drc_detach(drc); 4049 spapr_hotplug_req_remove_by_index(drc); 4050 } 4051 } 4052 4053 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4054 Error **errp) 4055 { 4056 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4057 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4058 4059 if (spapr->tpm_proxy != NULL) { 4060 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4061 return; 4062 } 4063 4064 spapr->tpm_proxy = tpm_proxy; 4065 } 4066 4067 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4068 { 4069 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4070 4071 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4072 object_unparent(OBJECT(dev)); 4073 spapr->tpm_proxy = NULL; 4074 } 4075 4076 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4077 DeviceState *dev, Error **errp) 4078 { 4079 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4080 spapr_memory_plug(hotplug_dev, dev, errp); 4081 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4082 spapr_core_plug(hotplug_dev, dev, errp); 4083 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4084 spapr_phb_plug(hotplug_dev, dev, errp); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4086 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4087 } 4088 } 4089 4090 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4091 DeviceState *dev, Error **errp) 4092 { 4093 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4094 spapr_memory_unplug(hotplug_dev, dev); 4095 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4096 spapr_core_unplug(hotplug_dev, dev); 4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4098 spapr_phb_unplug(hotplug_dev, dev); 4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4100 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4101 } 4102 } 4103 4104 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4105 DeviceState *dev, Error **errp) 4106 { 4107 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4108 MachineClass *mc = MACHINE_GET_CLASS(sms); 4109 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4110 4111 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4112 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4113 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4114 } else { 4115 /* NOTE: this means there is a window after guest reset, prior to 4116 * CAS negotiation, where unplug requests will fail due to the 4117 * capability not being detected yet. This is a bit different than 4118 * the case with PCI unplug, where the events will be queued and 4119 * eventually handled by the guest after boot 4120 */ 4121 error_setg(errp, "Memory hot unplug not supported for this guest"); 4122 } 4123 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4124 if (!mc->has_hotpluggable_cpus) { 4125 error_setg(errp, "CPU hot unplug not supported on this machine"); 4126 return; 4127 } 4128 spapr_core_unplug_request(hotplug_dev, dev, errp); 4129 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4130 if (!smc->dr_phb_enabled) { 4131 error_setg(errp, "PHB hot unplug not supported on this machine"); 4132 return; 4133 } 4134 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4135 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4136 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4137 } 4138 } 4139 4140 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4141 DeviceState *dev, Error **errp) 4142 { 4143 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4144 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4145 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4146 spapr_core_pre_plug(hotplug_dev, dev, errp); 4147 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4148 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4149 } 4150 } 4151 4152 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4153 DeviceState *dev) 4154 { 4155 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4156 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4157 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4158 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4159 return HOTPLUG_HANDLER(machine); 4160 } 4161 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4162 PCIDevice *pcidev = PCI_DEVICE(dev); 4163 PCIBus *root = pci_device_root_bus(pcidev); 4164 SpaprPhbState *phb = 4165 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4166 TYPE_SPAPR_PCI_HOST_BRIDGE); 4167 4168 if (phb) { 4169 return HOTPLUG_HANDLER(phb); 4170 } 4171 } 4172 return NULL; 4173 } 4174 4175 static CpuInstanceProperties 4176 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4177 { 4178 CPUArchId *core_slot; 4179 MachineClass *mc = MACHINE_GET_CLASS(machine); 4180 4181 /* make sure possible_cpu are intialized */ 4182 mc->possible_cpu_arch_ids(machine); 4183 /* get CPU core slot containing thread that matches cpu_index */ 4184 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4185 assert(core_slot); 4186 return core_slot->props; 4187 } 4188 4189 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4190 { 4191 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4192 } 4193 4194 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4195 { 4196 int i; 4197 unsigned int smp_threads = machine->smp.threads; 4198 unsigned int smp_cpus = machine->smp.cpus; 4199 const char *core_type; 4200 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4201 MachineClass *mc = MACHINE_GET_CLASS(machine); 4202 4203 if (!mc->has_hotpluggable_cpus) { 4204 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4205 } 4206 if (machine->possible_cpus) { 4207 assert(machine->possible_cpus->len == spapr_max_cores); 4208 return machine->possible_cpus; 4209 } 4210 4211 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4212 if (!core_type) { 4213 error_report("Unable to find sPAPR CPU Core definition"); 4214 exit(1); 4215 } 4216 4217 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4218 sizeof(CPUArchId) * spapr_max_cores); 4219 machine->possible_cpus->len = spapr_max_cores; 4220 for (i = 0; i < machine->possible_cpus->len; i++) { 4221 int core_id = i * smp_threads; 4222 4223 machine->possible_cpus->cpus[i].type = core_type; 4224 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4225 machine->possible_cpus->cpus[i].arch_id = core_id; 4226 machine->possible_cpus->cpus[i].props.has_core_id = true; 4227 machine->possible_cpus->cpus[i].props.core_id = core_id; 4228 } 4229 return machine->possible_cpus; 4230 } 4231 4232 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4233 uint64_t *buid, hwaddr *pio, 4234 hwaddr *mmio32, hwaddr *mmio64, 4235 unsigned n_dma, uint32_t *liobns, 4236 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4237 { 4238 /* 4239 * New-style PHB window placement. 4240 * 4241 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4242 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4243 * windows. 4244 * 4245 * Some guest kernels can't work with MMIO windows above 1<<46 4246 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4247 * 4248 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4249 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4250 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4251 * 1TiB 64-bit MMIO windows for each PHB. 4252 */ 4253 const uint64_t base_buid = 0x800000020000000ULL; 4254 int i; 4255 4256 /* Sanity check natural alignments */ 4257 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4258 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4259 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4260 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4261 /* Sanity check bounds */ 4262 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4263 SPAPR_PCI_MEM32_WIN_SIZE); 4264 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4265 SPAPR_PCI_MEM64_WIN_SIZE); 4266 4267 if (index >= SPAPR_MAX_PHBS) { 4268 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4269 SPAPR_MAX_PHBS - 1); 4270 return; 4271 } 4272 4273 *buid = base_buid + index; 4274 for (i = 0; i < n_dma; ++i) { 4275 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4276 } 4277 4278 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4279 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4280 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4281 4282 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4283 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4284 } 4285 4286 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4287 { 4288 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4289 4290 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4291 } 4292 4293 static void spapr_ics_resend(XICSFabric *dev) 4294 { 4295 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4296 4297 ics_resend(spapr->ics); 4298 } 4299 4300 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4301 { 4302 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4303 4304 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4305 } 4306 4307 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4308 Monitor *mon) 4309 { 4310 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4311 4312 spapr_irq_print_info(spapr, mon); 4313 monitor_printf(mon, "irqchip: %s\n", 4314 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4315 } 4316 4317 /* 4318 * This is a XIVE only operation 4319 */ 4320 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4321 uint8_t nvt_blk, uint32_t nvt_idx, 4322 bool cam_ignore, uint8_t priority, 4323 uint32_t logic_serv, XiveTCTXMatch *match) 4324 { 4325 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4326 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4327 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4328 int count; 4329 4330 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4331 priority, logic_serv, match); 4332 if (count < 0) { 4333 return count; 4334 } 4335 4336 /* 4337 * When we implement the save and restore of the thread interrupt 4338 * contexts in the enter/exit CPU handlers of the machine and the 4339 * escalations in QEMU, we should be able to handle non dispatched 4340 * vCPUs. 4341 * 4342 * Until this is done, the sPAPR machine should find at least one 4343 * matching context always. 4344 */ 4345 if (count == 0) { 4346 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4347 nvt_blk, nvt_idx); 4348 } 4349 4350 return count; 4351 } 4352 4353 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4354 { 4355 return cpu->vcpu_id; 4356 } 4357 4358 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4359 { 4360 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4361 MachineState *ms = MACHINE(spapr); 4362 int vcpu_id; 4363 4364 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4365 4366 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4367 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4368 error_append_hint(errp, "Adjust the number of cpus to %d " 4369 "or try to raise the number of threads per core\n", 4370 vcpu_id * ms->smp.threads / spapr->vsmt); 4371 return; 4372 } 4373 4374 cpu->vcpu_id = vcpu_id; 4375 } 4376 4377 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4378 { 4379 CPUState *cs; 4380 4381 CPU_FOREACH(cs) { 4382 PowerPCCPU *cpu = POWERPC_CPU(cs); 4383 4384 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4385 return cpu; 4386 } 4387 } 4388 4389 return NULL; 4390 } 4391 4392 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4393 { 4394 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4395 4396 /* These are only called by TCG, KVM maintains dispatch state */ 4397 4398 spapr_cpu->prod = false; 4399 if (spapr_cpu->vpa_addr) { 4400 CPUState *cs = CPU(cpu); 4401 uint32_t dispatch; 4402 4403 dispatch = ldl_be_phys(cs->as, 4404 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4405 dispatch++; 4406 if ((dispatch & 1) != 0) { 4407 qemu_log_mask(LOG_GUEST_ERROR, 4408 "VPA: incorrect dispatch counter value for " 4409 "dispatched partition %u, correcting.\n", dispatch); 4410 dispatch++; 4411 } 4412 stl_be_phys(cs->as, 4413 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4414 } 4415 } 4416 4417 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4418 { 4419 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4420 4421 if (spapr_cpu->vpa_addr) { 4422 CPUState *cs = CPU(cpu); 4423 uint32_t dispatch; 4424 4425 dispatch = ldl_be_phys(cs->as, 4426 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4427 dispatch++; 4428 if ((dispatch & 1) != 1) { 4429 qemu_log_mask(LOG_GUEST_ERROR, 4430 "VPA: incorrect dispatch counter value for " 4431 "preempted partition %u, correcting.\n", dispatch); 4432 dispatch++; 4433 } 4434 stl_be_phys(cs->as, 4435 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4436 } 4437 } 4438 4439 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4440 { 4441 MachineClass *mc = MACHINE_CLASS(oc); 4442 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4443 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4444 NMIClass *nc = NMI_CLASS(oc); 4445 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4446 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4447 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4448 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4449 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4450 4451 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4452 mc->ignore_boot_device_suffixes = true; 4453 4454 /* 4455 * We set up the default / latest behaviour here. The class_init 4456 * functions for the specific versioned machine types can override 4457 * these details for backwards compatibility 4458 */ 4459 mc->init = spapr_machine_init; 4460 mc->reset = spapr_machine_reset; 4461 mc->block_default_type = IF_SCSI; 4462 mc->max_cpus = 1024; 4463 mc->no_parallel = 1; 4464 mc->default_boot_order = ""; 4465 mc->default_ram_size = 512 * MiB; 4466 mc->default_ram_id = "ppc_spapr.ram"; 4467 mc->default_display = "std"; 4468 mc->kvm_type = spapr_kvm_type; 4469 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4470 mc->pci_allow_0_address = true; 4471 assert(!mc->get_hotplug_handler); 4472 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4473 hc->pre_plug = spapr_machine_device_pre_plug; 4474 hc->plug = spapr_machine_device_plug; 4475 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4476 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4477 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4478 hc->unplug_request = spapr_machine_device_unplug_request; 4479 hc->unplug = spapr_machine_device_unplug; 4480 4481 smc->dr_lmb_enabled = true; 4482 smc->update_dt_enabled = true; 4483 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4484 mc->has_hotpluggable_cpus = true; 4485 mc->nvdimm_supported = true; 4486 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4487 fwc->get_dev_path = spapr_get_fw_dev_path; 4488 nc->nmi_monitor_handler = spapr_nmi; 4489 smc->phb_placement = spapr_phb_placement; 4490 vhc->hypercall = emulate_spapr_hypercall; 4491 vhc->hpt_mask = spapr_hpt_mask; 4492 vhc->map_hptes = spapr_map_hptes; 4493 vhc->unmap_hptes = spapr_unmap_hptes; 4494 vhc->hpte_set_c = spapr_hpte_set_c; 4495 vhc->hpte_set_r = spapr_hpte_set_r; 4496 vhc->get_pate = spapr_get_pate; 4497 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4498 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4499 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4500 xic->ics_get = spapr_ics_get; 4501 xic->ics_resend = spapr_ics_resend; 4502 xic->icp_get = spapr_icp_get; 4503 ispc->print_info = spapr_pic_print_info; 4504 /* Force NUMA node memory size to be a multiple of 4505 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4506 * in which LMBs are represented and hot-added 4507 */ 4508 mc->numa_mem_align_shift = 28; 4509 mc->numa_mem_supported = true; 4510 mc->auto_enable_numa = true; 4511 4512 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4513 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4514 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4515 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4516 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4517 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4518 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4519 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4520 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4521 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4522 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4523 spapr_caps_add_properties(smc, &error_abort); 4524 smc->irq = &spapr_irq_dual; 4525 smc->dr_phb_enabled = true; 4526 smc->linux_pci_probe = true; 4527 smc->smp_threads_vsmt = true; 4528 smc->nr_xirqs = SPAPR_NR_XIRQS; 4529 xfc->match_nvt = spapr_match_nvt; 4530 } 4531 4532 static const TypeInfo spapr_machine_info = { 4533 .name = TYPE_SPAPR_MACHINE, 4534 .parent = TYPE_MACHINE, 4535 .abstract = true, 4536 .instance_size = sizeof(SpaprMachineState), 4537 .instance_init = spapr_instance_init, 4538 .instance_finalize = spapr_machine_finalizefn, 4539 .class_size = sizeof(SpaprMachineClass), 4540 .class_init = spapr_machine_class_init, 4541 .interfaces = (InterfaceInfo[]) { 4542 { TYPE_FW_PATH_PROVIDER }, 4543 { TYPE_NMI }, 4544 { TYPE_HOTPLUG_HANDLER }, 4545 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4546 { TYPE_XICS_FABRIC }, 4547 { TYPE_INTERRUPT_STATS_PROVIDER }, 4548 { TYPE_XIVE_FABRIC }, 4549 { } 4550 }, 4551 }; 4552 4553 static void spapr_machine_latest_class_options(MachineClass *mc) 4554 { 4555 mc->alias = "pseries"; 4556 mc->is_default = true; 4557 } 4558 4559 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4560 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4561 void *data) \ 4562 { \ 4563 MachineClass *mc = MACHINE_CLASS(oc); \ 4564 spapr_machine_##suffix##_class_options(mc); \ 4565 if (latest) { \ 4566 spapr_machine_latest_class_options(mc); \ 4567 } \ 4568 } \ 4569 static const TypeInfo spapr_machine_##suffix##_info = { \ 4570 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4571 .parent = TYPE_SPAPR_MACHINE, \ 4572 .class_init = spapr_machine_##suffix##_class_init, \ 4573 }; \ 4574 static void spapr_machine_register_##suffix(void) \ 4575 { \ 4576 type_register(&spapr_machine_##suffix##_info); \ 4577 } \ 4578 type_init(spapr_machine_register_##suffix) 4579 4580 /* 4581 * pseries-5.0 4582 */ 4583 static void spapr_machine_5_0_class_options(MachineClass *mc) 4584 { 4585 /* Defaults for the latest behaviour inherited from the base class */ 4586 } 4587 4588 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4589 4590 /* 4591 * pseries-4.2 4592 */ 4593 static void spapr_machine_4_2_class_options(MachineClass *mc) 4594 { 4595 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4596 4597 spapr_machine_5_0_class_options(mc); 4598 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4599 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4600 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4601 smc->rma_limit = 16 * GiB; 4602 mc->nvdimm_supported = false; 4603 } 4604 4605 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4606 4607 /* 4608 * pseries-4.1 4609 */ 4610 static void spapr_machine_4_1_class_options(MachineClass *mc) 4611 { 4612 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4613 static GlobalProperty compat[] = { 4614 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4615 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4616 }; 4617 4618 spapr_machine_4_2_class_options(mc); 4619 smc->linux_pci_probe = false; 4620 smc->smp_threads_vsmt = false; 4621 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4622 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4623 } 4624 4625 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4626 4627 /* 4628 * pseries-4.0 4629 */ 4630 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4631 uint64_t *buid, hwaddr *pio, 4632 hwaddr *mmio32, hwaddr *mmio64, 4633 unsigned n_dma, uint32_t *liobns, 4634 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4635 { 4636 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4637 nv2gpa, nv2atsd, errp); 4638 *nv2gpa = 0; 4639 *nv2atsd = 0; 4640 } 4641 4642 static void spapr_machine_4_0_class_options(MachineClass *mc) 4643 { 4644 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4645 4646 spapr_machine_4_1_class_options(mc); 4647 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4648 smc->phb_placement = phb_placement_4_0; 4649 smc->irq = &spapr_irq_xics; 4650 smc->pre_4_1_migration = true; 4651 } 4652 4653 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4654 4655 /* 4656 * pseries-3.1 4657 */ 4658 static void spapr_machine_3_1_class_options(MachineClass *mc) 4659 { 4660 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4661 4662 spapr_machine_4_0_class_options(mc); 4663 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4664 4665 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4666 smc->update_dt_enabled = false; 4667 smc->dr_phb_enabled = false; 4668 smc->broken_host_serial_model = true; 4669 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4670 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4671 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4672 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4673 } 4674 4675 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4676 4677 /* 4678 * pseries-3.0 4679 */ 4680 4681 static void spapr_machine_3_0_class_options(MachineClass *mc) 4682 { 4683 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4684 4685 spapr_machine_3_1_class_options(mc); 4686 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4687 4688 smc->legacy_irq_allocation = true; 4689 smc->nr_xirqs = 0x400; 4690 smc->irq = &spapr_irq_xics_legacy; 4691 } 4692 4693 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4694 4695 /* 4696 * pseries-2.12 4697 */ 4698 static void spapr_machine_2_12_class_options(MachineClass *mc) 4699 { 4700 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4701 static GlobalProperty compat[] = { 4702 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4703 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4704 }; 4705 4706 spapr_machine_3_0_class_options(mc); 4707 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4708 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4709 4710 /* We depend on kvm_enabled() to choose a default value for the 4711 * hpt-max-page-size capability. Of course we can't do it here 4712 * because this is too early and the HW accelerator isn't initialzed 4713 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4714 */ 4715 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4716 } 4717 4718 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4719 4720 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4721 { 4722 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4723 4724 spapr_machine_2_12_class_options(mc); 4725 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4726 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4727 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4728 } 4729 4730 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4731 4732 /* 4733 * pseries-2.11 4734 */ 4735 4736 static void spapr_machine_2_11_class_options(MachineClass *mc) 4737 { 4738 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4739 4740 spapr_machine_2_12_class_options(mc); 4741 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4742 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4743 } 4744 4745 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4746 4747 /* 4748 * pseries-2.10 4749 */ 4750 4751 static void spapr_machine_2_10_class_options(MachineClass *mc) 4752 { 4753 spapr_machine_2_11_class_options(mc); 4754 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4755 } 4756 4757 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4758 4759 /* 4760 * pseries-2.9 4761 */ 4762 4763 static void spapr_machine_2_9_class_options(MachineClass *mc) 4764 { 4765 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4766 static GlobalProperty compat[] = { 4767 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4768 }; 4769 4770 spapr_machine_2_10_class_options(mc); 4771 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4772 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4773 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4774 smc->pre_2_10_has_unused_icps = true; 4775 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4776 } 4777 4778 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4779 4780 /* 4781 * pseries-2.8 4782 */ 4783 4784 static void spapr_machine_2_8_class_options(MachineClass *mc) 4785 { 4786 static GlobalProperty compat[] = { 4787 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4788 }; 4789 4790 spapr_machine_2_9_class_options(mc); 4791 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4792 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4793 mc->numa_mem_align_shift = 23; 4794 } 4795 4796 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4797 4798 /* 4799 * pseries-2.7 4800 */ 4801 4802 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4803 uint64_t *buid, hwaddr *pio, 4804 hwaddr *mmio32, hwaddr *mmio64, 4805 unsigned n_dma, uint32_t *liobns, 4806 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4807 { 4808 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4809 const uint64_t base_buid = 0x800000020000000ULL; 4810 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4811 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4812 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4813 const uint32_t max_index = 255; 4814 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4815 4816 uint64_t ram_top = MACHINE(spapr)->ram_size; 4817 hwaddr phb0_base, phb_base; 4818 int i; 4819 4820 /* Do we have device memory? */ 4821 if (MACHINE(spapr)->maxram_size > ram_top) { 4822 /* Can't just use maxram_size, because there may be an 4823 * alignment gap between normal and device memory regions 4824 */ 4825 ram_top = MACHINE(spapr)->device_memory->base + 4826 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4827 } 4828 4829 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4830 4831 if (index > max_index) { 4832 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4833 max_index); 4834 return; 4835 } 4836 4837 *buid = base_buid + index; 4838 for (i = 0; i < n_dma; ++i) { 4839 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4840 } 4841 4842 phb_base = phb0_base + index * phb_spacing; 4843 *pio = phb_base + pio_offset; 4844 *mmio32 = phb_base + mmio_offset; 4845 /* 4846 * We don't set the 64-bit MMIO window, relying on the PHB's 4847 * fallback behaviour of automatically splitting a large "32-bit" 4848 * window into contiguous 32-bit and 64-bit windows 4849 */ 4850 4851 *nv2gpa = 0; 4852 *nv2atsd = 0; 4853 } 4854 4855 static void spapr_machine_2_7_class_options(MachineClass *mc) 4856 { 4857 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4858 static GlobalProperty compat[] = { 4859 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4860 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4861 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4862 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4863 }; 4864 4865 spapr_machine_2_8_class_options(mc); 4866 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4867 mc->default_machine_opts = "modern-hotplug-events=off"; 4868 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4869 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4870 smc->phb_placement = phb_placement_2_7; 4871 } 4872 4873 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4874 4875 /* 4876 * pseries-2.6 4877 */ 4878 4879 static void spapr_machine_2_6_class_options(MachineClass *mc) 4880 { 4881 static GlobalProperty compat[] = { 4882 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4883 }; 4884 4885 spapr_machine_2_7_class_options(mc); 4886 mc->has_hotpluggable_cpus = false; 4887 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4888 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4889 } 4890 4891 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4892 4893 /* 4894 * pseries-2.5 4895 */ 4896 4897 static void spapr_machine_2_5_class_options(MachineClass *mc) 4898 { 4899 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4900 static GlobalProperty compat[] = { 4901 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4902 }; 4903 4904 spapr_machine_2_6_class_options(mc); 4905 smc->use_ohci_by_default = true; 4906 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4907 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4908 } 4909 4910 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4911 4912 /* 4913 * pseries-2.4 4914 */ 4915 4916 static void spapr_machine_2_4_class_options(MachineClass *mc) 4917 { 4918 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4919 4920 spapr_machine_2_5_class_options(mc); 4921 smc->dr_lmb_enabled = false; 4922 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4923 } 4924 4925 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4926 4927 /* 4928 * pseries-2.3 4929 */ 4930 4931 static void spapr_machine_2_3_class_options(MachineClass *mc) 4932 { 4933 static GlobalProperty compat[] = { 4934 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4935 }; 4936 spapr_machine_2_4_class_options(mc); 4937 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4938 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4939 } 4940 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4941 4942 /* 4943 * pseries-2.2 4944 */ 4945 4946 static void spapr_machine_2_2_class_options(MachineClass *mc) 4947 { 4948 static GlobalProperty compat[] = { 4949 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4950 }; 4951 4952 spapr_machine_2_3_class_options(mc); 4953 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4954 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4955 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4956 } 4957 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4958 4959 /* 4960 * pseries-2.1 4961 */ 4962 4963 static void spapr_machine_2_1_class_options(MachineClass *mc) 4964 { 4965 spapr_machine_2_2_class_options(mc); 4966 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4967 } 4968 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4969 4970 static void spapr_machine_register_types(void) 4971 { 4972 type_register_static(&spapr_machine_info); 4973 } 4974 4975 type_init(spapr_machine_register_types) 4976