1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/hostmem.h" 34 #include "sysemu/numa.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/runstate.h" 38 #include "qemu/log.h" 39 #include "hw/fw-path-provider.h" 40 #include "elf.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/cpus.h" 44 #include "sysemu/hw_accel.h" 45 #include "kvm_ppc.h" 46 #include "migration/misc.h" 47 #include "migration/qemu-file-types.h" 48 #include "migration/global_state.h" 49 #include "migration/register.h" 50 #include "migration/blocker.h" 51 #include "mmu-hash64.h" 52 #include "mmu-book3s-v3.h" 53 #include "cpu-models.h" 54 #include "hw/core/cpu.h" 55 56 #include "hw/boards.h" 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/address-spaces.h" 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_OVERHEAD 0x2800000 106 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 107 108 #define MIN_RMA_SLOF (128 * MiB) 109 110 #define PHANDLE_INTC 0x00001111 111 112 /* These two functions implement the VCPU id numbering: one to compute them 113 * all and one to identify thread 0 of a VCORE. Any change to the first one 114 * is likely to have an impact on the second one, so let's keep them close. 115 */ 116 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 117 { 118 MachineState *ms = MACHINE(spapr); 119 unsigned int smp_threads = ms->smp.threads; 120 121 assert(spapr->vsmt); 122 return 123 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 124 } 125 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 126 PowerPCCPU *cpu) 127 { 128 assert(spapr->vsmt); 129 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 130 } 131 132 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 133 { 134 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 135 * and newer QEMUs don't even have them. In both cases, we don't want 136 * to send anything on the wire. 137 */ 138 return false; 139 } 140 141 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 142 .name = "icp/server", 143 .version_id = 1, 144 .minimum_version_id = 1, 145 .needed = pre_2_10_vmstate_dummy_icp_needed, 146 .fields = (VMStateField[]) { 147 VMSTATE_UNUSED(4), /* uint32_t xirr */ 148 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 149 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 150 VMSTATE_END_OF_LIST() 151 }, 152 }; 153 154 static void pre_2_10_vmstate_register_dummy_icp(int i) 155 { 156 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 157 (void *)(uintptr_t) i); 158 } 159 160 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 161 { 162 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 163 (void *)(uintptr_t) i); 164 } 165 166 int spapr_max_server_number(SpaprMachineState *spapr) 167 { 168 MachineState *ms = MACHINE(spapr); 169 170 assert(spapr->vsmt); 171 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 172 } 173 174 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 175 int smt_threads) 176 { 177 int i, ret = 0; 178 uint32_t servers_prop[smt_threads]; 179 uint32_t gservers_prop[smt_threads * 2]; 180 int index = spapr_get_vcpu_id(cpu); 181 182 if (cpu->compat_pvr) { 183 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 184 if (ret < 0) { 185 return ret; 186 } 187 } 188 189 /* Build interrupt servers and gservers properties */ 190 for (i = 0; i < smt_threads; i++) { 191 servers_prop[i] = cpu_to_be32(index + i); 192 /* Hack, direct the group queues back to cpu 0 */ 193 gservers_prop[i*2] = cpu_to_be32(index + i); 194 gservers_prop[i*2 + 1] = 0; 195 } 196 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 197 servers_prop, sizeof(servers_prop)); 198 if (ret < 0) { 199 return ret; 200 } 201 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 202 gservers_prop, sizeof(gservers_prop)); 203 204 return ret; 205 } 206 207 static void spapr_dt_pa_features(SpaprMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset) 210 { 211 uint8_t pa_features_206[] = { 6, 0, 212 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 213 uint8_t pa_features_207[] = { 24, 0, 214 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 215 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 216 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 217 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 218 uint8_t pa_features_300[] = { 66, 0, 219 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 220 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 221 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 222 /* 6: DS207 */ 223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 224 /* 16: Vector */ 225 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 226 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 227 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 228 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 229 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 230 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 231 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 232 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 234 /* 42: PM, 44: PC RA, 46: SC vec'd */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 236 /* 48: SIMD, 50: QP BFP, 52: String */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 238 /* 54: DecFP, 56: DecI, 58: SHA */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 240 /* 60: NM atomic, 62: RNG */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 242 }; 243 uint8_t *pa_features = NULL; 244 size_t pa_size; 245 246 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 247 pa_features = pa_features_206; 248 pa_size = sizeof(pa_features_206); 249 } 250 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 251 pa_features = pa_features_207; 252 pa_size = sizeof(pa_features_207); 253 } 254 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 255 pa_features = pa_features_300; 256 pa_size = sizeof(pa_features_300); 257 } 258 if (!pa_features) { 259 return; 260 } 261 262 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 263 /* 264 * Note: we keep CI large pages off by default because a 64K capable 265 * guest provisioned with large pages might otherwise try to map a qemu 266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 267 * even if that qemu runs on a 4k host. 268 * We dd this bit back here if we are confident this is not an issue 269 */ 270 pa_features[3] |= 0x20; 271 } 272 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 273 pa_features[24] |= 0x80; /* Transactional memory support */ 274 } 275 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 276 /* Workaround for broken kernels that attempt (guest) radix 277 * mode when they can't handle it, if they see the radix bit set 278 * in pa-features. So hide it from them. */ 279 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 280 } 281 282 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 283 } 284 285 static hwaddr spapr_node0_size(MachineState *machine) 286 { 287 if (machine->numa_state->num_nodes) { 288 int i; 289 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 290 if (machine->numa_state->nodes[i].node_mem) { 291 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 292 machine->ram_size); 293 } 294 } 295 } 296 return machine->ram_size; 297 } 298 299 bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr) 300 { 301 MachineState *machine = MACHINE(spapr); 302 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 303 304 return smc->pre_5_2_numa_associativity || 305 machine->numa_state->num_nodes <= 1; 306 } 307 308 static void add_str(GString *s, const gchar *s1) 309 { 310 g_string_append_len(s, s1, strlen(s1) + 1); 311 } 312 313 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 314 hwaddr start, hwaddr size) 315 { 316 char mem_name[32]; 317 uint64_t mem_reg_property[2]; 318 int off; 319 320 mem_reg_property[0] = cpu_to_be64(start); 321 mem_reg_property[1] = cpu_to_be64(size); 322 323 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 324 off = fdt_add_subnode(fdt, 0, mem_name); 325 _FDT(off); 326 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 327 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 328 sizeof(mem_reg_property)))); 329 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 330 return off; 331 } 332 333 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 334 { 335 MemoryDeviceInfoList *info; 336 337 for (info = list; info; info = info->next) { 338 MemoryDeviceInfo *value = info->value; 339 340 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 341 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 342 343 if (addr >= pcdimm_info->addr && 344 addr < (pcdimm_info->addr + pcdimm_info->size)) { 345 return pcdimm_info->node; 346 } 347 } 348 } 349 350 return -1; 351 } 352 353 struct sPAPRDrconfCellV2 { 354 uint32_t seq_lmbs; 355 uint64_t base_addr; 356 uint32_t drc_index; 357 uint32_t aa_index; 358 uint32_t flags; 359 } QEMU_PACKED; 360 361 typedef struct DrconfCellQueue { 362 struct sPAPRDrconfCellV2 cell; 363 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 364 } DrconfCellQueue; 365 366 static DrconfCellQueue * 367 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 368 uint32_t drc_index, uint32_t aa_index, 369 uint32_t flags) 370 { 371 DrconfCellQueue *elem; 372 373 elem = g_malloc0(sizeof(*elem)); 374 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 375 elem->cell.base_addr = cpu_to_be64(base_addr); 376 elem->cell.drc_index = cpu_to_be32(drc_index); 377 elem->cell.aa_index = cpu_to_be32(aa_index); 378 elem->cell.flags = cpu_to_be32(flags); 379 380 return elem; 381 } 382 383 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 384 int offset, MemoryDeviceInfoList *dimms) 385 { 386 MachineState *machine = MACHINE(spapr); 387 uint8_t *int_buf, *cur_index; 388 int ret; 389 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 390 uint64_t addr, cur_addr, size; 391 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 392 uint64_t mem_end = machine->device_memory->base + 393 memory_region_size(&machine->device_memory->mr); 394 uint32_t node, buf_len, nr_entries = 0; 395 SpaprDrc *drc; 396 DrconfCellQueue *elem, *next; 397 MemoryDeviceInfoList *info; 398 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 399 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 400 401 /* Entry to cover RAM and the gap area */ 402 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 403 SPAPR_LMB_FLAGS_RESERVED | 404 SPAPR_LMB_FLAGS_DRC_INVALID); 405 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 406 nr_entries++; 407 408 cur_addr = machine->device_memory->base; 409 for (info = dimms; info; info = info->next) { 410 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 411 412 addr = di->addr; 413 size = di->size; 414 node = di->node; 415 416 /* 417 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 418 * area is marked hotpluggable in the next iteration for the bigger 419 * chunk including the NVDIMM occupied area. 420 */ 421 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 422 continue; 423 424 /* Entry for hot-pluggable area */ 425 if (cur_addr < addr) { 426 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 427 g_assert(drc); 428 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 429 cur_addr, spapr_drc_index(drc), -1, 0); 430 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 431 nr_entries++; 432 } 433 434 /* Entry for DIMM */ 435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 436 g_assert(drc); 437 elem = spapr_get_drconf_cell(size / lmb_size, addr, 438 spapr_drc_index(drc), node, 439 (SPAPR_LMB_FLAGS_ASSIGNED | 440 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 441 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 442 nr_entries++; 443 cur_addr = addr + size; 444 } 445 446 /* Entry for remaining hotpluggable area */ 447 if (cur_addr < mem_end) { 448 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 449 g_assert(drc); 450 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 451 cur_addr, spapr_drc_index(drc), -1, 0); 452 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 453 nr_entries++; 454 } 455 456 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 457 int_buf = cur_index = g_malloc0(buf_len); 458 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 459 cur_index += sizeof(nr_entries); 460 461 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 462 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 463 cur_index += sizeof(elem->cell); 464 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 465 g_free(elem); 466 } 467 468 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 469 g_free(int_buf); 470 if (ret < 0) { 471 return -1; 472 } 473 return 0; 474 } 475 476 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 477 int offset, MemoryDeviceInfoList *dimms) 478 { 479 MachineState *machine = MACHINE(spapr); 480 int i, ret; 481 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 482 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 483 uint32_t nr_lmbs = (machine->device_memory->base + 484 memory_region_size(&machine->device_memory->mr)) / 485 lmb_size; 486 uint32_t *int_buf, *cur_index, buf_len; 487 488 /* 489 * Allocate enough buffer size to fit in ibm,dynamic-memory 490 */ 491 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 492 cur_index = int_buf = g_malloc0(buf_len); 493 int_buf[0] = cpu_to_be32(nr_lmbs); 494 cur_index++; 495 for (i = 0; i < nr_lmbs; i++) { 496 uint64_t addr = i * lmb_size; 497 uint32_t *dynamic_memory = cur_index; 498 499 if (i >= device_lmb_start) { 500 SpaprDrc *drc; 501 502 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 503 g_assert(drc); 504 505 dynamic_memory[0] = cpu_to_be32(addr >> 32); 506 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 507 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 508 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 509 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 510 if (memory_region_present(get_system_memory(), addr)) { 511 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 512 } else { 513 dynamic_memory[5] = cpu_to_be32(0); 514 } 515 } else { 516 /* 517 * LMB information for RMA, boot time RAM and gap b/n RAM and 518 * device memory region -- all these are marked as reserved 519 * and as having no valid DRC. 520 */ 521 dynamic_memory[0] = cpu_to_be32(addr >> 32); 522 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 523 dynamic_memory[2] = cpu_to_be32(0); 524 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 525 dynamic_memory[4] = cpu_to_be32(-1); 526 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 527 SPAPR_LMB_FLAGS_DRC_INVALID); 528 } 529 530 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 531 } 532 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 533 g_free(int_buf); 534 if (ret < 0) { 535 return -1; 536 } 537 return 0; 538 } 539 540 /* 541 * Adds ibm,dynamic-reconfiguration-memory node. 542 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 543 * of this device tree node. 544 */ 545 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 546 void *fdt) 547 { 548 MachineState *machine = MACHINE(spapr); 549 int ret, offset; 550 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 551 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 552 cpu_to_be32(lmb_size & 0xffffffff)}; 553 MemoryDeviceInfoList *dimms = NULL; 554 555 /* 556 * Don't create the node if there is no device memory 557 */ 558 if (machine->ram_size == machine->maxram_size) { 559 return 0; 560 } 561 562 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 563 564 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 565 sizeof(prop_lmb_size)); 566 if (ret < 0) { 567 return ret; 568 } 569 570 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 571 if (ret < 0) { 572 return ret; 573 } 574 575 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 576 if (ret < 0) { 577 return ret; 578 } 579 580 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 581 dimms = qmp_memory_device_list(); 582 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 583 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 584 } else { 585 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 586 } 587 qapi_free_MemoryDeviceInfoList(dimms); 588 589 if (ret < 0) { 590 return ret; 591 } 592 593 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 594 595 return ret; 596 } 597 598 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 599 { 600 MachineState *machine = MACHINE(spapr); 601 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 602 hwaddr mem_start, node_size; 603 int i, nb_nodes = machine->numa_state->num_nodes; 604 NodeInfo *nodes = machine->numa_state->nodes; 605 606 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 607 if (!nodes[i].node_mem) { 608 continue; 609 } 610 if (mem_start >= machine->ram_size) { 611 node_size = 0; 612 } else { 613 node_size = nodes[i].node_mem; 614 if (node_size > machine->ram_size - mem_start) { 615 node_size = machine->ram_size - mem_start; 616 } 617 } 618 if (!mem_start) { 619 /* spapr_machine_init() checks for rma_size <= node0_size 620 * already */ 621 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 622 mem_start += spapr->rma_size; 623 node_size -= spapr->rma_size; 624 } 625 for ( ; node_size; ) { 626 hwaddr sizetmp = pow2floor(node_size); 627 628 /* mem_start != 0 here */ 629 if (ctzl(mem_start) < ctzl(sizetmp)) { 630 sizetmp = 1ULL << ctzl(mem_start); 631 } 632 633 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 634 node_size -= sizetmp; 635 mem_start += sizetmp; 636 } 637 } 638 639 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 640 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 641 int ret; 642 643 g_assert(smc->dr_lmb_enabled); 644 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 645 if (ret) { 646 return ret; 647 } 648 } 649 650 return 0; 651 } 652 653 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 654 SpaprMachineState *spapr) 655 { 656 MachineState *ms = MACHINE(spapr); 657 PowerPCCPU *cpu = POWERPC_CPU(cs); 658 CPUPPCState *env = &cpu->env; 659 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 660 int index = spapr_get_vcpu_id(cpu); 661 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 662 0xffffffff, 0xffffffff}; 663 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 664 : SPAPR_TIMEBASE_FREQ; 665 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 666 uint32_t page_sizes_prop[64]; 667 size_t page_sizes_prop_size; 668 unsigned int smp_threads = ms->smp.threads; 669 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 670 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 671 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 672 SpaprDrc *drc; 673 int drc_index; 674 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 675 int i; 676 677 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 678 if (drc) { 679 drc_index = spapr_drc_index(drc); 680 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 681 } 682 683 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 684 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 685 686 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 688 env->dcache_line_size))); 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 690 env->dcache_line_size))); 691 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 692 env->icache_line_size))); 693 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 694 env->icache_line_size))); 695 696 if (pcc->l1_dcache_size) { 697 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 698 pcc->l1_dcache_size))); 699 } else { 700 warn_report("Unknown L1 dcache size for cpu"); 701 } 702 if (pcc->l1_icache_size) { 703 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 704 pcc->l1_icache_size))); 705 } else { 706 warn_report("Unknown L1 icache size for cpu"); 707 } 708 709 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 710 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 711 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 713 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 714 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 715 716 if (env->spr_cb[SPR_PURR].oea_read) { 717 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 718 } 719 if (env->spr_cb[SPR_SPURR].oea_read) { 720 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 721 } 722 723 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 724 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 725 segs, sizeof(segs)))); 726 } 727 728 /* Advertise VSX (vector extensions) if available 729 * 1 == VMX / Altivec available 730 * 2 == VSX available 731 * 732 * Only CPUs for which we create core types in spapr_cpu_core.c 733 * are possible, and all of those have VMX */ 734 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 735 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 736 } else { 737 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 738 } 739 740 /* Advertise DFP (Decimal Floating Point) if available 741 * 0 / no property == no DFP 742 * 1 == DFP available */ 743 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 744 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 745 } 746 747 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 748 sizeof(page_sizes_prop)); 749 if (page_sizes_prop_size) { 750 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 751 page_sizes_prop, page_sizes_prop_size))); 752 } 753 754 spapr_dt_pa_features(spapr, cpu, fdt, offset); 755 756 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 757 cs->cpu_index / vcpus_per_socket))); 758 759 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 760 pft_size_prop, sizeof(pft_size_prop)))); 761 762 if (ms->numa_state->num_nodes > 1) { 763 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 764 } 765 766 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 767 768 if (pcc->radix_page_info) { 769 for (i = 0; i < pcc->radix_page_info->count; i++) { 770 radix_AP_encodings[i] = 771 cpu_to_be32(pcc->radix_page_info->entries[i]); 772 } 773 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 774 radix_AP_encodings, 775 pcc->radix_page_info->count * 776 sizeof(radix_AP_encodings[0])))); 777 } 778 779 /* 780 * We set this property to let the guest know that it can use the large 781 * decrementer and its width in bits. 782 */ 783 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 784 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 785 pcc->lrg_decr_bits))); 786 } 787 788 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 789 { 790 CPUState **rev; 791 CPUState *cs; 792 int n_cpus; 793 int cpus_offset; 794 int i; 795 796 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 797 _FDT(cpus_offset); 798 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 799 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 800 801 /* 802 * We walk the CPUs in reverse order to ensure that CPU DT nodes 803 * created by fdt_add_subnode() end up in the right order in FDT 804 * for the guest kernel the enumerate the CPUs correctly. 805 * 806 * The CPU list cannot be traversed in reverse order, so we need 807 * to do extra work. 808 */ 809 n_cpus = 0; 810 rev = NULL; 811 CPU_FOREACH(cs) { 812 rev = g_renew(CPUState *, rev, n_cpus + 1); 813 rev[n_cpus++] = cs; 814 } 815 816 for (i = n_cpus - 1; i >= 0; i--) { 817 CPUState *cs = rev[i]; 818 PowerPCCPU *cpu = POWERPC_CPU(cs); 819 int index = spapr_get_vcpu_id(cpu); 820 DeviceClass *dc = DEVICE_GET_CLASS(cs); 821 g_autofree char *nodename = NULL; 822 int offset; 823 824 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 825 continue; 826 } 827 828 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 829 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 830 _FDT(offset); 831 spapr_dt_cpu(cs, fdt, offset, spapr); 832 } 833 834 g_free(rev); 835 } 836 837 static int spapr_dt_rng(void *fdt) 838 { 839 int node; 840 int ret; 841 842 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 843 if (node <= 0) { 844 return -1; 845 } 846 ret = fdt_setprop_string(fdt, node, "device_type", 847 "ibm,platform-facilities"); 848 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 849 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 850 851 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 852 if (node <= 0) { 853 return -1; 854 } 855 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 856 857 return ret ? -1 : 0; 858 } 859 860 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 861 { 862 MachineState *ms = MACHINE(spapr); 863 int rtas; 864 GString *hypertas = g_string_sized_new(256); 865 GString *qemu_hypertas = g_string_sized_new(256); 866 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 867 memory_region_size(&MACHINE(spapr)->device_memory->mr); 868 uint32_t lrdr_capacity[] = { 869 cpu_to_be32(max_device_addr >> 32), 870 cpu_to_be32(max_device_addr & 0xffffffff), 871 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 872 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 873 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 874 }; 875 876 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 877 878 /* hypertas */ 879 add_str(hypertas, "hcall-pft"); 880 add_str(hypertas, "hcall-term"); 881 add_str(hypertas, "hcall-dabr"); 882 add_str(hypertas, "hcall-interrupt"); 883 add_str(hypertas, "hcall-tce"); 884 add_str(hypertas, "hcall-vio"); 885 add_str(hypertas, "hcall-splpar"); 886 add_str(hypertas, "hcall-join"); 887 add_str(hypertas, "hcall-bulk"); 888 add_str(hypertas, "hcall-set-mode"); 889 add_str(hypertas, "hcall-sprg0"); 890 add_str(hypertas, "hcall-copy"); 891 add_str(hypertas, "hcall-debug"); 892 add_str(hypertas, "hcall-vphn"); 893 add_str(qemu_hypertas, "hcall-memop1"); 894 895 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 896 add_str(hypertas, "hcall-multi-tce"); 897 } 898 899 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 900 add_str(hypertas, "hcall-hpt-resize"); 901 } 902 903 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 904 hypertas->str, hypertas->len)); 905 g_string_free(hypertas, TRUE); 906 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 907 qemu_hypertas->str, qemu_hypertas->len)); 908 g_string_free(qemu_hypertas, TRUE); 909 910 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 911 912 /* 913 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 914 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 915 * 916 * The system reset requirements are driven by existing Linux and PowerVM 917 * implementation which (contrary to PAPR) saves r3 in the error log 918 * structure like machine check, so Linux expects to find the saved r3 919 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 920 * does not look at the error value). 921 * 922 * System reset interrupts are not subject to interlock like machine 923 * check, so this memory area could be corrupted if the sreset is 924 * interrupted by a machine check (or vice versa) if it was shared. To 925 * prevent this, system reset uses per-CPU areas for the sreset save 926 * area. A system reset that interrupts a system reset handler could 927 * still overwrite this area, but Linux doesn't try to recover in that 928 * case anyway. 929 * 930 * The extra 8 bytes is required because Linux's FWNMI error log check 931 * is off-by-one. 932 */ 933 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 934 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 935 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 936 RTAS_ERROR_LOG_MAX)); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 938 RTAS_EVENT_SCAN_RATE)); 939 940 g_assert(msi_nonbroken); 941 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 942 943 /* 944 * According to PAPR, rtas ibm,os-term does not guarantee a return 945 * back to the guest cpu. 946 * 947 * While an additional ibm,extended-os-term property indicates 948 * that rtas call return will always occur. Set this property. 949 */ 950 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 951 952 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 953 lrdr_capacity, sizeof(lrdr_capacity))); 954 955 spapr_dt_rtas_tokens(fdt, rtas); 956 } 957 958 /* 959 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 960 * and the XIVE features that the guest may request and thus the valid 961 * values for bytes 23..26 of option vector 5: 962 */ 963 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 964 int chosen) 965 { 966 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 967 968 char val[2 * 4] = { 969 23, 0x00, /* XICS / XIVE mode */ 970 24, 0x00, /* Hash/Radix, filled in below. */ 971 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 972 26, 0x40, /* Radix options: GTSE == yes. */ 973 }; 974 975 if (spapr->irq->xics && spapr->irq->xive) { 976 val[1] = SPAPR_OV5_XIVE_BOTH; 977 } else if (spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 979 } else { 980 assert(spapr->irq->xics); 981 val[1] = SPAPR_OV5_XIVE_LEGACY; 982 } 983 984 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 985 first_ppc_cpu->compat_pvr)) { 986 /* 987 * If we're in a pre POWER9 compat mode then the guest should 988 * do hash and use the legacy interrupt mode 989 */ 990 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 991 val[3] = 0x00; /* Hash */ 992 } else if (kvm_enabled()) { 993 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 994 val[3] = 0x80; /* OV5_MMU_BOTH */ 995 } else if (kvmppc_has_cap_mmu_radix()) { 996 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 997 } else { 998 val[3] = 0x00; /* Hash */ 999 } 1000 } else { 1001 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1002 val[3] = 0xC0; 1003 } 1004 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1005 val, sizeof(val))); 1006 } 1007 1008 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1009 { 1010 MachineState *machine = MACHINE(spapr); 1011 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1012 int chosen; 1013 1014 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1015 1016 if (reset) { 1017 const char *boot_device = machine->boot_order; 1018 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1019 size_t cb = 0; 1020 char *bootlist = get_boot_devices_list(&cb); 1021 1022 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1023 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1024 machine->kernel_cmdline)); 1025 } 1026 1027 if (spapr->initrd_size) { 1028 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1029 spapr->initrd_base)); 1030 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1031 spapr->initrd_base + spapr->initrd_size)); 1032 } 1033 1034 if (spapr->kernel_size) { 1035 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1036 cpu_to_be64(spapr->kernel_size) }; 1037 1038 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1039 &kprop, sizeof(kprop))); 1040 if (spapr->kernel_le) { 1041 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1042 } 1043 } 1044 if (boot_menu) { 1045 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1046 } 1047 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1049 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1050 1051 if (cb && bootlist) { 1052 int i; 1053 1054 for (i = 0; i < cb; i++) { 1055 if (bootlist[i] == '\n') { 1056 bootlist[i] = ' '; 1057 } 1058 } 1059 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1060 } 1061 1062 if (boot_device && strlen(boot_device)) { 1063 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1064 } 1065 1066 if (!spapr->has_graphics && stdout_path) { 1067 /* 1068 * "linux,stdout-path" and "stdout" properties are 1069 * deprecated by linux kernel. New platforms should only 1070 * use the "stdout-path" property. Set the new property 1071 * and continue using older property to remain compatible 1072 * with the existing firmware. 1073 */ 1074 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1075 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1076 } 1077 1078 /* 1079 * We can deal with BAR reallocation just fine, advertise it 1080 * to the guest 1081 */ 1082 if (smc->linux_pci_probe) { 1083 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1084 } 1085 1086 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1087 1088 g_free(stdout_path); 1089 g_free(bootlist); 1090 } 1091 1092 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1093 } 1094 1095 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1096 { 1097 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1098 * KVM to work under pHyp with some guest co-operation */ 1099 int hypervisor; 1100 uint8_t hypercall[16]; 1101 1102 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1103 /* indicate KVM hypercall interface */ 1104 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1105 if (kvmppc_has_cap_fixup_hcalls()) { 1106 /* 1107 * Older KVM versions with older guest kernels were broken 1108 * with the magic page, don't allow the guest to map it. 1109 */ 1110 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1111 sizeof(hypercall))) { 1112 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1113 hypercall, sizeof(hypercall))); 1114 } 1115 } 1116 } 1117 1118 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1119 { 1120 MachineState *machine = MACHINE(spapr); 1121 MachineClass *mc = MACHINE_GET_CLASS(machine); 1122 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1123 uint32_t root_drc_type_mask = 0; 1124 int ret; 1125 void *fdt; 1126 SpaprPhbState *phb; 1127 char *buf; 1128 1129 fdt = g_malloc0(space); 1130 _FDT((fdt_create_empty_tree(fdt, space))); 1131 1132 /* Root node */ 1133 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1134 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1135 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1136 1137 /* Guest UUID & Name*/ 1138 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1139 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1140 if (qemu_uuid_set) { 1141 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1142 } 1143 g_free(buf); 1144 1145 if (qemu_get_vm_name()) { 1146 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1147 qemu_get_vm_name())); 1148 } 1149 1150 /* Host Model & Serial Number */ 1151 if (spapr->host_model) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1153 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1154 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1155 g_free(buf); 1156 } 1157 1158 if (spapr->host_serial) { 1159 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1160 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1161 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1162 g_free(buf); 1163 } 1164 1165 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1166 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1167 1168 /* /interrupt controller */ 1169 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1170 1171 ret = spapr_dt_memory(spapr, fdt); 1172 if (ret < 0) { 1173 error_report("couldn't setup memory nodes in fdt"); 1174 exit(1); 1175 } 1176 1177 /* /vdevice */ 1178 spapr_dt_vdevice(spapr->vio_bus, fdt); 1179 1180 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1181 ret = spapr_dt_rng(fdt); 1182 if (ret < 0) { 1183 error_report("could not set up rng device in the fdt"); 1184 exit(1); 1185 } 1186 } 1187 1188 QLIST_FOREACH(phb, &spapr->phbs, list) { 1189 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1190 if (ret < 0) { 1191 error_report("couldn't setup PCI devices in fdt"); 1192 exit(1); 1193 } 1194 } 1195 1196 spapr_dt_cpus(fdt, spapr); 1197 1198 /* ibm,drc-indexes and friends */ 1199 if (smc->dr_lmb_enabled) { 1200 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1201 } 1202 if (smc->dr_phb_enabled) { 1203 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1204 } 1205 if (mc->nvdimm_supported) { 1206 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1207 } 1208 if (root_drc_type_mask) { 1209 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1210 } 1211 1212 if (mc->has_hotpluggable_cpus) { 1213 int offset = fdt_path_offset(fdt, "/cpus"); 1214 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1215 if (ret < 0) { 1216 error_report("Couldn't set up CPU DR device tree properties"); 1217 exit(1); 1218 } 1219 } 1220 1221 /* /event-sources */ 1222 spapr_dt_events(spapr, fdt); 1223 1224 /* /rtas */ 1225 spapr_dt_rtas(spapr, fdt); 1226 1227 /* /chosen */ 1228 spapr_dt_chosen(spapr, fdt, reset); 1229 1230 /* /hypervisor */ 1231 if (kvm_enabled()) { 1232 spapr_dt_hypervisor(spapr, fdt); 1233 } 1234 1235 /* Build memory reserve map */ 1236 if (reset) { 1237 if (spapr->kernel_size) { 1238 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1239 spapr->kernel_size))); 1240 } 1241 if (spapr->initrd_size) { 1242 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1243 spapr->initrd_size))); 1244 } 1245 } 1246 1247 /* NVDIMM devices */ 1248 if (mc->nvdimm_supported) { 1249 spapr_dt_persistent_memory(spapr, fdt); 1250 } 1251 1252 return fdt; 1253 } 1254 1255 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1256 { 1257 SpaprMachineState *spapr = opaque; 1258 1259 return (addr & 0x0fffffff) + spapr->kernel_addr; 1260 } 1261 1262 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1263 PowerPCCPU *cpu) 1264 { 1265 CPUPPCState *env = &cpu->env; 1266 1267 /* The TCG path should also be holding the BQL at this point */ 1268 g_assert(qemu_mutex_iothread_locked()); 1269 1270 if (msr_pr) { 1271 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1272 env->gpr[3] = H_PRIVILEGE; 1273 } else { 1274 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1275 } 1276 } 1277 1278 struct LPCRSyncState { 1279 target_ulong value; 1280 target_ulong mask; 1281 }; 1282 1283 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1284 { 1285 struct LPCRSyncState *s = arg.host_ptr; 1286 PowerPCCPU *cpu = POWERPC_CPU(cs); 1287 CPUPPCState *env = &cpu->env; 1288 target_ulong lpcr; 1289 1290 cpu_synchronize_state(cs); 1291 lpcr = env->spr[SPR_LPCR]; 1292 lpcr &= ~s->mask; 1293 lpcr |= s->value; 1294 ppc_store_lpcr(cpu, lpcr); 1295 } 1296 1297 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1298 { 1299 CPUState *cs; 1300 struct LPCRSyncState s = { 1301 .value = value, 1302 .mask = mask 1303 }; 1304 CPU_FOREACH(cs) { 1305 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1306 } 1307 } 1308 1309 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1310 { 1311 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1312 1313 /* Copy PATE1:GR into PATE0:HR */ 1314 entry->dw0 = spapr->patb_entry & PATE0_HR; 1315 entry->dw1 = spapr->patb_entry; 1316 } 1317 1318 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1319 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1320 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1321 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1322 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1323 1324 /* 1325 * Get the fd to access the kernel htab, re-opening it if necessary 1326 */ 1327 static int get_htab_fd(SpaprMachineState *spapr) 1328 { 1329 Error *local_err = NULL; 1330 1331 if (spapr->htab_fd >= 0) { 1332 return spapr->htab_fd; 1333 } 1334 1335 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1336 if (spapr->htab_fd < 0) { 1337 error_report_err(local_err); 1338 } 1339 1340 return spapr->htab_fd; 1341 } 1342 1343 void close_htab_fd(SpaprMachineState *spapr) 1344 { 1345 if (spapr->htab_fd >= 0) { 1346 close(spapr->htab_fd); 1347 } 1348 spapr->htab_fd = -1; 1349 } 1350 1351 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1352 { 1353 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1354 1355 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1356 } 1357 1358 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1359 { 1360 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1361 1362 assert(kvm_enabled()); 1363 1364 if (!spapr->htab) { 1365 return 0; 1366 } 1367 1368 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1369 } 1370 1371 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1372 hwaddr ptex, int n) 1373 { 1374 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1375 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1376 1377 if (!spapr->htab) { 1378 /* 1379 * HTAB is controlled by KVM. Fetch into temporary buffer 1380 */ 1381 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1382 kvmppc_read_hptes(hptes, ptex, n); 1383 return hptes; 1384 } 1385 1386 /* 1387 * HTAB is controlled by QEMU. Just point to the internally 1388 * accessible PTEG. 1389 */ 1390 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1391 } 1392 1393 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1394 const ppc_hash_pte64_t *hptes, 1395 hwaddr ptex, int n) 1396 { 1397 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1398 1399 if (!spapr->htab) { 1400 g_free((void *)hptes); 1401 } 1402 1403 /* Nothing to do for qemu managed HPT */ 1404 } 1405 1406 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1407 uint64_t pte0, uint64_t pte1) 1408 { 1409 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1410 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1411 1412 if (!spapr->htab) { 1413 kvmppc_write_hpte(ptex, pte0, pte1); 1414 } else { 1415 if (pte0 & HPTE64_V_VALID) { 1416 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1417 /* 1418 * When setting valid, we write PTE1 first. This ensures 1419 * proper synchronization with the reading code in 1420 * ppc_hash64_pteg_search() 1421 */ 1422 smp_wmb(); 1423 stq_p(spapr->htab + offset, pte0); 1424 } else { 1425 stq_p(spapr->htab + offset, pte0); 1426 /* 1427 * When clearing it we set PTE0 first. This ensures proper 1428 * synchronization with the reading code in 1429 * ppc_hash64_pteg_search() 1430 */ 1431 smp_wmb(); 1432 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1433 } 1434 } 1435 } 1436 1437 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1438 uint64_t pte1) 1439 { 1440 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1441 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1442 1443 if (!spapr->htab) { 1444 /* There should always be a hash table when this is called */ 1445 error_report("spapr_hpte_set_c called with no hash table !"); 1446 return; 1447 } 1448 1449 /* The HW performs a non-atomic byte update */ 1450 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1451 } 1452 1453 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1454 uint64_t pte1) 1455 { 1456 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1457 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1458 1459 if (!spapr->htab) { 1460 /* There should always be a hash table when this is called */ 1461 error_report("spapr_hpte_set_r called with no hash table !"); 1462 return; 1463 } 1464 1465 /* The HW performs a non-atomic byte update */ 1466 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1467 } 1468 1469 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1470 { 1471 int shift; 1472 1473 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1474 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1475 * that's much more than is needed for Linux guests */ 1476 shift = ctz64(pow2ceil(ramsize)) - 7; 1477 shift = MAX(shift, 18); /* Minimum architected size */ 1478 shift = MIN(shift, 46); /* Maximum architected size */ 1479 return shift; 1480 } 1481 1482 void spapr_free_hpt(SpaprMachineState *spapr) 1483 { 1484 g_free(spapr->htab); 1485 spapr->htab = NULL; 1486 spapr->htab_shift = 0; 1487 close_htab_fd(spapr); 1488 } 1489 1490 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1491 { 1492 ERRP_GUARD(); 1493 long rc; 1494 1495 /* Clean up any HPT info from a previous boot */ 1496 spapr_free_hpt(spapr); 1497 1498 rc = kvmppc_reset_htab(shift); 1499 1500 if (rc == -EOPNOTSUPP) { 1501 error_setg(errp, "HPT not supported in nested guests"); 1502 return -EOPNOTSUPP; 1503 } 1504 1505 if (rc < 0) { 1506 /* kernel-side HPT needed, but couldn't allocate one */ 1507 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1508 shift); 1509 error_append_hint(errp, "Try smaller maxmem?\n"); 1510 return -errno; 1511 } else if (rc > 0) { 1512 /* kernel-side HPT allocated */ 1513 if (rc != shift) { 1514 error_setg(errp, 1515 "Requested order %d HPT, but kernel allocated order %ld", 1516 shift, rc); 1517 error_append_hint(errp, "Try smaller maxmem?\n"); 1518 return -ENOSPC; 1519 } 1520 1521 spapr->htab_shift = shift; 1522 spapr->htab = NULL; 1523 } else { 1524 /* kernel-side HPT not needed, allocate in userspace instead */ 1525 size_t size = 1ULL << shift; 1526 int i; 1527 1528 spapr->htab = qemu_memalign(size, size); 1529 memset(spapr->htab, 0, size); 1530 spapr->htab_shift = shift; 1531 1532 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1533 DIRTY_HPTE(HPTE(spapr->htab, i)); 1534 } 1535 } 1536 /* We're setting up a hash table, so that means we're not radix */ 1537 spapr->patb_entry = 0; 1538 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1539 return 0; 1540 } 1541 1542 void spapr_setup_hpt(SpaprMachineState *spapr) 1543 { 1544 int hpt_shift; 1545 1546 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1547 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1548 } else { 1549 uint64_t current_ram_size; 1550 1551 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1552 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1553 } 1554 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1555 1556 if (kvm_enabled()) { 1557 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1558 1559 /* Check our RMA fits in the possible VRMA */ 1560 if (vrma_limit < spapr->rma_size) { 1561 error_report("Unable to create %" HWADDR_PRIu 1562 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1563 spapr->rma_size / MiB, vrma_limit / MiB); 1564 exit(EXIT_FAILURE); 1565 } 1566 } 1567 } 1568 1569 static void spapr_machine_reset(MachineState *machine) 1570 { 1571 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1572 PowerPCCPU *first_ppc_cpu; 1573 hwaddr fdt_addr; 1574 void *fdt; 1575 int rc; 1576 1577 pef_kvm_reset(machine->cgs, &error_fatal); 1578 spapr_caps_apply(spapr); 1579 1580 first_ppc_cpu = POWERPC_CPU(first_cpu); 1581 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1582 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1583 spapr->max_compat_pvr)) { 1584 /* 1585 * If using KVM with radix mode available, VCPUs can be started 1586 * without a HPT because KVM will start them in radix mode. 1587 * Set the GR bit in PATE so that we know there is no HPT. 1588 */ 1589 spapr->patb_entry = PATE1_GR; 1590 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1591 } else { 1592 spapr_setup_hpt(spapr); 1593 } 1594 1595 qemu_devices_reset(); 1596 1597 spapr_ovec_cleanup(spapr->ov5_cas); 1598 spapr->ov5_cas = spapr_ovec_new(); 1599 1600 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1601 1602 /* 1603 * This is fixing some of the default configuration of the XIVE 1604 * devices. To be called after the reset of the machine devices. 1605 */ 1606 spapr_irq_reset(spapr, &error_fatal); 1607 1608 /* 1609 * There is no CAS under qtest. Simulate one to please the code that 1610 * depends on spapr->ov5_cas. This is especially needed to test device 1611 * unplug, so we do that before resetting the DRCs. 1612 */ 1613 if (qtest_enabled()) { 1614 spapr_ovec_cleanup(spapr->ov5_cas); 1615 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1616 } 1617 1618 /* DRC reset may cause a device to be unplugged. This will cause troubles 1619 * if this device is used by another device (eg, a running vhost backend 1620 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1621 * situations, we reset DRCs after all devices have been reset. 1622 */ 1623 spapr_drc_reset_all(spapr); 1624 1625 spapr_clear_pending_events(spapr); 1626 1627 /* 1628 * We place the device tree and RTAS just below either the top of the RMA, 1629 * or just below 2GB, whichever is lower, so that it can be 1630 * processed with 32-bit real mode code if necessary 1631 */ 1632 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1633 1634 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1635 1636 rc = fdt_pack(fdt); 1637 1638 /* Should only fail if we've built a corrupted tree */ 1639 assert(rc == 0); 1640 1641 /* Load the fdt */ 1642 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1643 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1644 g_free(spapr->fdt_blob); 1645 spapr->fdt_size = fdt_totalsize(fdt); 1646 spapr->fdt_initial_size = spapr->fdt_size; 1647 spapr->fdt_blob = fdt; 1648 1649 /* Set up the entry state */ 1650 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1651 first_ppc_cpu->env.gpr[5] = 0; 1652 1653 spapr->fwnmi_system_reset_addr = -1; 1654 spapr->fwnmi_machine_check_addr = -1; 1655 spapr->fwnmi_machine_check_interlock = -1; 1656 1657 /* Signal all vCPUs waiting on this condition */ 1658 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1659 1660 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1661 } 1662 1663 static void spapr_create_nvram(SpaprMachineState *spapr) 1664 { 1665 DeviceState *dev = qdev_new("spapr-nvram"); 1666 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1667 1668 if (dinfo) { 1669 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1670 &error_fatal); 1671 } 1672 1673 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1674 1675 spapr->nvram = (struct SpaprNvram *)dev; 1676 } 1677 1678 static void spapr_rtc_create(SpaprMachineState *spapr) 1679 { 1680 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1681 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1682 &error_fatal, NULL); 1683 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1684 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1685 "date"); 1686 } 1687 1688 /* Returns whether we want to use VGA or not */ 1689 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1690 { 1691 switch (vga_interface_type) { 1692 case VGA_NONE: 1693 return false; 1694 case VGA_DEVICE: 1695 return true; 1696 case VGA_STD: 1697 case VGA_VIRTIO: 1698 case VGA_CIRRUS: 1699 return pci_vga_init(pci_bus) != NULL; 1700 default: 1701 error_setg(errp, 1702 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1703 return false; 1704 } 1705 } 1706 1707 static int spapr_pre_load(void *opaque) 1708 { 1709 int rc; 1710 1711 rc = spapr_caps_pre_load(opaque); 1712 if (rc) { 1713 return rc; 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int spapr_post_load(void *opaque, int version_id) 1720 { 1721 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1722 int err = 0; 1723 1724 err = spapr_caps_post_migration(spapr); 1725 if (err) { 1726 return err; 1727 } 1728 1729 /* 1730 * In earlier versions, there was no separate qdev for the PAPR 1731 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1732 * So when migrating from those versions, poke the incoming offset 1733 * value into the RTC device 1734 */ 1735 if (version_id < 3) { 1736 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1737 if (err) { 1738 return err; 1739 } 1740 } 1741 1742 if (kvm_enabled() && spapr->patb_entry) { 1743 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1744 bool radix = !!(spapr->patb_entry & PATE1_GR); 1745 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1746 1747 /* 1748 * Update LPCR:HR and UPRT as they may not be set properly in 1749 * the stream 1750 */ 1751 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1752 LPCR_HR | LPCR_UPRT); 1753 1754 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1755 if (err) { 1756 error_report("Process table config unsupported by the host"); 1757 return -EINVAL; 1758 } 1759 } 1760 1761 err = spapr_irq_post_load(spapr, version_id); 1762 if (err) { 1763 return err; 1764 } 1765 1766 return err; 1767 } 1768 1769 static int spapr_pre_save(void *opaque) 1770 { 1771 int rc; 1772 1773 rc = spapr_caps_pre_save(opaque); 1774 if (rc) { 1775 return rc; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static bool version_before_3(void *opaque, int version_id) 1782 { 1783 return version_id < 3; 1784 } 1785 1786 static bool spapr_pending_events_needed(void *opaque) 1787 { 1788 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1789 return !QTAILQ_EMPTY(&spapr->pending_events); 1790 } 1791 1792 static const VMStateDescription vmstate_spapr_event_entry = { 1793 .name = "spapr_event_log_entry", 1794 .version_id = 1, 1795 .minimum_version_id = 1, 1796 .fields = (VMStateField[]) { 1797 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1798 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1799 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1800 NULL, extended_length), 1801 VMSTATE_END_OF_LIST() 1802 }, 1803 }; 1804 1805 static const VMStateDescription vmstate_spapr_pending_events = { 1806 .name = "spapr_pending_events", 1807 .version_id = 1, 1808 .minimum_version_id = 1, 1809 .needed = spapr_pending_events_needed, 1810 .fields = (VMStateField[]) { 1811 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1812 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1813 VMSTATE_END_OF_LIST() 1814 }, 1815 }; 1816 1817 static bool spapr_ov5_cas_needed(void *opaque) 1818 { 1819 SpaprMachineState *spapr = opaque; 1820 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1821 bool cas_needed; 1822 1823 /* Prior to the introduction of SpaprOptionVector, we had two option 1824 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1825 * Both of these options encode machine topology into the device-tree 1826 * in such a way that the now-booted OS should still be able to interact 1827 * appropriately with QEMU regardless of what options were actually 1828 * negotiatied on the source side. 1829 * 1830 * As such, we can avoid migrating the CAS-negotiated options if these 1831 * are the only options available on the current machine/platform. 1832 * Since these are the only options available for pseries-2.7 and 1833 * earlier, this allows us to maintain old->new/new->old migration 1834 * compatibility. 1835 * 1836 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1837 * via default pseries-2.8 machines and explicit command-line parameters. 1838 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1839 * of the actual CAS-negotiated values to continue working properly. For 1840 * example, availability of memory unplug depends on knowing whether 1841 * OV5_HP_EVT was negotiated via CAS. 1842 * 1843 * Thus, for any cases where the set of available CAS-negotiatable 1844 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1845 * include the CAS-negotiated options in the migration stream, unless 1846 * if they affect boot time behaviour only. 1847 */ 1848 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1849 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1850 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1851 1852 /* We need extra information if we have any bits outside the mask 1853 * defined above */ 1854 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1855 1856 spapr_ovec_cleanup(ov5_mask); 1857 1858 return cas_needed; 1859 } 1860 1861 static const VMStateDescription vmstate_spapr_ov5_cas = { 1862 .name = "spapr_option_vector_ov5_cas", 1863 .version_id = 1, 1864 .minimum_version_id = 1, 1865 .needed = spapr_ov5_cas_needed, 1866 .fields = (VMStateField[]) { 1867 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1868 vmstate_spapr_ovec, SpaprOptionVector), 1869 VMSTATE_END_OF_LIST() 1870 }, 1871 }; 1872 1873 static bool spapr_patb_entry_needed(void *opaque) 1874 { 1875 SpaprMachineState *spapr = opaque; 1876 1877 return !!spapr->patb_entry; 1878 } 1879 1880 static const VMStateDescription vmstate_spapr_patb_entry = { 1881 .name = "spapr_patb_entry", 1882 .version_id = 1, 1883 .minimum_version_id = 1, 1884 .needed = spapr_patb_entry_needed, 1885 .fields = (VMStateField[]) { 1886 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1887 VMSTATE_END_OF_LIST() 1888 }, 1889 }; 1890 1891 static bool spapr_irq_map_needed(void *opaque) 1892 { 1893 SpaprMachineState *spapr = opaque; 1894 1895 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1896 } 1897 1898 static const VMStateDescription vmstate_spapr_irq_map = { 1899 .name = "spapr_irq_map", 1900 .version_id = 1, 1901 .minimum_version_id = 1, 1902 .needed = spapr_irq_map_needed, 1903 .fields = (VMStateField[]) { 1904 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1905 VMSTATE_END_OF_LIST() 1906 }, 1907 }; 1908 1909 static bool spapr_dtb_needed(void *opaque) 1910 { 1911 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1912 1913 return smc->update_dt_enabled; 1914 } 1915 1916 static int spapr_dtb_pre_load(void *opaque) 1917 { 1918 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1919 1920 g_free(spapr->fdt_blob); 1921 spapr->fdt_blob = NULL; 1922 spapr->fdt_size = 0; 1923 1924 return 0; 1925 } 1926 1927 static const VMStateDescription vmstate_spapr_dtb = { 1928 .name = "spapr_dtb", 1929 .version_id = 1, 1930 .minimum_version_id = 1, 1931 .needed = spapr_dtb_needed, 1932 .pre_load = spapr_dtb_pre_load, 1933 .fields = (VMStateField[]) { 1934 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1935 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1936 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1937 fdt_size), 1938 VMSTATE_END_OF_LIST() 1939 }, 1940 }; 1941 1942 static bool spapr_fwnmi_needed(void *opaque) 1943 { 1944 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1945 1946 return spapr->fwnmi_machine_check_addr != -1; 1947 } 1948 1949 static int spapr_fwnmi_pre_save(void *opaque) 1950 { 1951 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1952 1953 /* 1954 * Check if machine check handling is in progress and print a 1955 * warning message. 1956 */ 1957 if (spapr->fwnmi_machine_check_interlock != -1) { 1958 warn_report("A machine check is being handled during migration. The" 1959 "handler may run and log hardware error on the destination"); 1960 } 1961 1962 return 0; 1963 } 1964 1965 static const VMStateDescription vmstate_spapr_fwnmi = { 1966 .name = "spapr_fwnmi", 1967 .version_id = 1, 1968 .minimum_version_id = 1, 1969 .needed = spapr_fwnmi_needed, 1970 .pre_save = spapr_fwnmi_pre_save, 1971 .fields = (VMStateField[]) { 1972 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1973 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1974 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1975 VMSTATE_END_OF_LIST() 1976 }, 1977 }; 1978 1979 static const VMStateDescription vmstate_spapr = { 1980 .name = "spapr", 1981 .version_id = 3, 1982 .minimum_version_id = 1, 1983 .pre_load = spapr_pre_load, 1984 .post_load = spapr_post_load, 1985 .pre_save = spapr_pre_save, 1986 .fields = (VMStateField[]) { 1987 /* used to be @next_irq */ 1988 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1989 1990 /* RTC offset */ 1991 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1992 1993 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 1994 VMSTATE_END_OF_LIST() 1995 }, 1996 .subsections = (const VMStateDescription*[]) { 1997 &vmstate_spapr_ov5_cas, 1998 &vmstate_spapr_patb_entry, 1999 &vmstate_spapr_pending_events, 2000 &vmstate_spapr_cap_htm, 2001 &vmstate_spapr_cap_vsx, 2002 &vmstate_spapr_cap_dfp, 2003 &vmstate_spapr_cap_cfpc, 2004 &vmstate_spapr_cap_sbbc, 2005 &vmstate_spapr_cap_ibs, 2006 &vmstate_spapr_cap_hpt_maxpagesize, 2007 &vmstate_spapr_irq_map, 2008 &vmstate_spapr_cap_nested_kvm_hv, 2009 &vmstate_spapr_dtb, 2010 &vmstate_spapr_cap_large_decr, 2011 &vmstate_spapr_cap_ccf_assist, 2012 &vmstate_spapr_cap_fwnmi, 2013 &vmstate_spapr_fwnmi, 2014 NULL 2015 } 2016 }; 2017 2018 static int htab_save_setup(QEMUFile *f, void *opaque) 2019 { 2020 SpaprMachineState *spapr = opaque; 2021 2022 /* "Iteration" header */ 2023 if (!spapr->htab_shift) { 2024 qemu_put_be32(f, -1); 2025 } else { 2026 qemu_put_be32(f, spapr->htab_shift); 2027 } 2028 2029 if (spapr->htab) { 2030 spapr->htab_save_index = 0; 2031 spapr->htab_first_pass = true; 2032 } else { 2033 if (spapr->htab_shift) { 2034 assert(kvm_enabled()); 2035 } 2036 } 2037 2038 2039 return 0; 2040 } 2041 2042 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2043 int chunkstart, int n_valid, int n_invalid) 2044 { 2045 qemu_put_be32(f, chunkstart); 2046 qemu_put_be16(f, n_valid); 2047 qemu_put_be16(f, n_invalid); 2048 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2049 HASH_PTE_SIZE_64 * n_valid); 2050 } 2051 2052 static void htab_save_end_marker(QEMUFile *f) 2053 { 2054 qemu_put_be32(f, 0); 2055 qemu_put_be16(f, 0); 2056 qemu_put_be16(f, 0); 2057 } 2058 2059 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2060 int64_t max_ns) 2061 { 2062 bool has_timeout = max_ns != -1; 2063 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2064 int index = spapr->htab_save_index; 2065 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2066 2067 assert(spapr->htab_first_pass); 2068 2069 do { 2070 int chunkstart; 2071 2072 /* Consume invalid HPTEs */ 2073 while ((index < htabslots) 2074 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2075 CLEAN_HPTE(HPTE(spapr->htab, index)); 2076 index++; 2077 } 2078 2079 /* Consume valid HPTEs */ 2080 chunkstart = index; 2081 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2082 && HPTE_VALID(HPTE(spapr->htab, index))) { 2083 CLEAN_HPTE(HPTE(spapr->htab, index)); 2084 index++; 2085 } 2086 2087 if (index > chunkstart) { 2088 int n_valid = index - chunkstart; 2089 2090 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2091 2092 if (has_timeout && 2093 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2094 break; 2095 } 2096 } 2097 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2098 2099 if (index >= htabslots) { 2100 assert(index == htabslots); 2101 index = 0; 2102 spapr->htab_first_pass = false; 2103 } 2104 spapr->htab_save_index = index; 2105 } 2106 2107 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2108 int64_t max_ns) 2109 { 2110 bool final = max_ns < 0; 2111 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2112 int examined = 0, sent = 0; 2113 int index = spapr->htab_save_index; 2114 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2115 2116 assert(!spapr->htab_first_pass); 2117 2118 do { 2119 int chunkstart, invalidstart; 2120 2121 /* Consume non-dirty HPTEs */ 2122 while ((index < htabslots) 2123 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2124 index++; 2125 examined++; 2126 } 2127 2128 chunkstart = index; 2129 /* Consume valid dirty HPTEs */ 2130 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2131 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2132 && HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 examined++; 2136 } 2137 2138 invalidstart = index; 2139 /* Consume invalid dirty HPTEs */ 2140 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2141 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2142 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2143 CLEAN_HPTE(HPTE(spapr->htab, index)); 2144 index++; 2145 examined++; 2146 } 2147 2148 if (index > chunkstart) { 2149 int n_valid = invalidstart - chunkstart; 2150 int n_invalid = index - invalidstart; 2151 2152 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2153 sent += index - chunkstart; 2154 2155 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2156 break; 2157 } 2158 } 2159 2160 if (examined >= htabslots) { 2161 break; 2162 } 2163 2164 if (index >= htabslots) { 2165 assert(index == htabslots); 2166 index = 0; 2167 } 2168 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2169 2170 if (index >= htabslots) { 2171 assert(index == htabslots); 2172 index = 0; 2173 } 2174 2175 spapr->htab_save_index = index; 2176 2177 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2178 } 2179 2180 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2181 #define MAX_KVM_BUF_SIZE 2048 2182 2183 static int htab_save_iterate(QEMUFile *f, void *opaque) 2184 { 2185 SpaprMachineState *spapr = opaque; 2186 int fd; 2187 int rc = 0; 2188 2189 /* Iteration header */ 2190 if (!spapr->htab_shift) { 2191 qemu_put_be32(f, -1); 2192 return 1; 2193 } else { 2194 qemu_put_be32(f, 0); 2195 } 2196 2197 if (!spapr->htab) { 2198 assert(kvm_enabled()); 2199 2200 fd = get_htab_fd(spapr); 2201 if (fd < 0) { 2202 return fd; 2203 } 2204 2205 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2206 if (rc < 0) { 2207 return rc; 2208 } 2209 } else if (spapr->htab_first_pass) { 2210 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2211 } else { 2212 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2213 } 2214 2215 htab_save_end_marker(f); 2216 2217 return rc; 2218 } 2219 2220 static int htab_save_complete(QEMUFile *f, void *opaque) 2221 { 2222 SpaprMachineState *spapr = opaque; 2223 int fd; 2224 2225 /* Iteration header */ 2226 if (!spapr->htab_shift) { 2227 qemu_put_be32(f, -1); 2228 return 0; 2229 } else { 2230 qemu_put_be32(f, 0); 2231 } 2232 2233 if (!spapr->htab) { 2234 int rc; 2235 2236 assert(kvm_enabled()); 2237 2238 fd = get_htab_fd(spapr); 2239 if (fd < 0) { 2240 return fd; 2241 } 2242 2243 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2244 if (rc < 0) { 2245 return rc; 2246 } 2247 } else { 2248 if (spapr->htab_first_pass) { 2249 htab_save_first_pass(f, spapr, -1); 2250 } 2251 htab_save_later_pass(f, spapr, -1); 2252 } 2253 2254 /* End marker */ 2255 htab_save_end_marker(f); 2256 2257 return 0; 2258 } 2259 2260 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2261 { 2262 SpaprMachineState *spapr = opaque; 2263 uint32_t section_hdr; 2264 int fd = -1; 2265 Error *local_err = NULL; 2266 2267 if (version_id < 1 || version_id > 1) { 2268 error_report("htab_load() bad version"); 2269 return -EINVAL; 2270 } 2271 2272 section_hdr = qemu_get_be32(f); 2273 2274 if (section_hdr == -1) { 2275 spapr_free_hpt(spapr); 2276 return 0; 2277 } 2278 2279 if (section_hdr) { 2280 int ret; 2281 2282 /* First section gives the htab size */ 2283 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2284 if (ret < 0) { 2285 error_report_err(local_err); 2286 return ret; 2287 } 2288 return 0; 2289 } 2290 2291 if (!spapr->htab) { 2292 assert(kvm_enabled()); 2293 2294 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2295 if (fd < 0) { 2296 error_report_err(local_err); 2297 return fd; 2298 } 2299 } 2300 2301 while (true) { 2302 uint32_t index; 2303 uint16_t n_valid, n_invalid; 2304 2305 index = qemu_get_be32(f); 2306 n_valid = qemu_get_be16(f); 2307 n_invalid = qemu_get_be16(f); 2308 2309 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2310 /* End of Stream */ 2311 break; 2312 } 2313 2314 if ((index + n_valid + n_invalid) > 2315 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2316 /* Bad index in stream */ 2317 error_report( 2318 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2319 index, n_valid, n_invalid, spapr->htab_shift); 2320 return -EINVAL; 2321 } 2322 2323 if (spapr->htab) { 2324 if (n_valid) { 2325 qemu_get_buffer(f, HPTE(spapr->htab, index), 2326 HASH_PTE_SIZE_64 * n_valid); 2327 } 2328 if (n_invalid) { 2329 memset(HPTE(spapr->htab, index + n_valid), 0, 2330 HASH_PTE_SIZE_64 * n_invalid); 2331 } 2332 } else { 2333 int rc; 2334 2335 assert(fd >= 0); 2336 2337 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2338 &local_err); 2339 if (rc < 0) { 2340 error_report_err(local_err); 2341 return rc; 2342 } 2343 } 2344 } 2345 2346 if (!spapr->htab) { 2347 assert(fd >= 0); 2348 close(fd); 2349 } 2350 2351 return 0; 2352 } 2353 2354 static void htab_save_cleanup(void *opaque) 2355 { 2356 SpaprMachineState *spapr = opaque; 2357 2358 close_htab_fd(spapr); 2359 } 2360 2361 static SaveVMHandlers savevm_htab_handlers = { 2362 .save_setup = htab_save_setup, 2363 .save_live_iterate = htab_save_iterate, 2364 .save_live_complete_precopy = htab_save_complete, 2365 .save_cleanup = htab_save_cleanup, 2366 .load_state = htab_load, 2367 }; 2368 2369 static void spapr_boot_set(void *opaque, const char *boot_device, 2370 Error **errp) 2371 { 2372 MachineState *machine = MACHINE(opaque); 2373 machine->boot_order = g_strdup(boot_device); 2374 } 2375 2376 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2377 { 2378 MachineState *machine = MACHINE(spapr); 2379 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2380 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2381 int i; 2382 2383 for (i = 0; i < nr_lmbs; i++) { 2384 uint64_t addr; 2385 2386 addr = i * lmb_size + machine->device_memory->base; 2387 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2388 addr / lmb_size); 2389 } 2390 } 2391 2392 /* 2393 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2394 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2395 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2396 */ 2397 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2398 { 2399 int i; 2400 2401 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2402 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2403 " is not aligned to %" PRIu64 " MiB", 2404 machine->ram_size, 2405 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2406 return; 2407 } 2408 2409 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2410 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2411 " is not aligned to %" PRIu64 " MiB", 2412 machine->ram_size, 2413 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2414 return; 2415 } 2416 2417 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2418 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2419 error_setg(errp, 2420 "Node %d memory size 0x%" PRIx64 2421 " is not aligned to %" PRIu64 " MiB", 2422 i, machine->numa_state->nodes[i].node_mem, 2423 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2424 return; 2425 } 2426 } 2427 } 2428 2429 /* find cpu slot in machine->possible_cpus by core_id */ 2430 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2431 { 2432 int index = id / ms->smp.threads; 2433 2434 if (index >= ms->possible_cpus->len) { 2435 return NULL; 2436 } 2437 if (idx) { 2438 *idx = index; 2439 } 2440 return &ms->possible_cpus->cpus[index]; 2441 } 2442 2443 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2444 { 2445 MachineState *ms = MACHINE(spapr); 2446 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2447 Error *local_err = NULL; 2448 bool vsmt_user = !!spapr->vsmt; 2449 int kvm_smt = kvmppc_smt_threads(); 2450 int ret; 2451 unsigned int smp_threads = ms->smp.threads; 2452 2453 if (!kvm_enabled() && (smp_threads > 1)) { 2454 error_setg(errp, "TCG cannot support more than 1 thread/core " 2455 "on a pseries machine"); 2456 return; 2457 } 2458 if (!is_power_of_2(smp_threads)) { 2459 error_setg(errp, "Cannot support %d threads/core on a pseries " 2460 "machine because it must be a power of 2", smp_threads); 2461 return; 2462 } 2463 2464 /* Detemine the VSMT mode to use: */ 2465 if (vsmt_user) { 2466 if (spapr->vsmt < smp_threads) { 2467 error_setg(errp, "Cannot support VSMT mode %d" 2468 " because it must be >= threads/core (%d)", 2469 spapr->vsmt, smp_threads); 2470 return; 2471 } 2472 /* In this case, spapr->vsmt has been set by the command line */ 2473 } else if (!smc->smp_threads_vsmt) { 2474 /* 2475 * Default VSMT value is tricky, because we need it to be as 2476 * consistent as possible (for migration), but this requires 2477 * changing it for at least some existing cases. We pick 8 as 2478 * the value that we'd get with KVM on POWER8, the 2479 * overwhelmingly common case in production systems. 2480 */ 2481 spapr->vsmt = MAX(8, smp_threads); 2482 } else { 2483 spapr->vsmt = smp_threads; 2484 } 2485 2486 /* KVM: If necessary, set the SMT mode: */ 2487 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2488 ret = kvmppc_set_smt_threads(spapr->vsmt); 2489 if (ret) { 2490 /* Looks like KVM isn't able to change VSMT mode */ 2491 error_setg(&local_err, 2492 "Failed to set KVM's VSMT mode to %d (errno %d)", 2493 spapr->vsmt, ret); 2494 /* We can live with that if the default one is big enough 2495 * for the number of threads, and a submultiple of the one 2496 * we want. In this case we'll waste some vcpu ids, but 2497 * behaviour will be correct */ 2498 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2499 warn_report_err(local_err); 2500 } else { 2501 if (!vsmt_user) { 2502 error_append_hint(&local_err, 2503 "On PPC, a VM with %d threads/core" 2504 " on a host with %d threads/core" 2505 " requires the use of VSMT mode %d.\n", 2506 smp_threads, kvm_smt, spapr->vsmt); 2507 } 2508 kvmppc_error_append_smt_possible_hint(&local_err); 2509 error_propagate(errp, local_err); 2510 } 2511 } 2512 } 2513 /* else TCG: nothing to do currently */ 2514 } 2515 2516 static void spapr_init_cpus(SpaprMachineState *spapr) 2517 { 2518 MachineState *machine = MACHINE(spapr); 2519 MachineClass *mc = MACHINE_GET_CLASS(machine); 2520 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2521 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2522 const CPUArchIdList *possible_cpus; 2523 unsigned int smp_cpus = machine->smp.cpus; 2524 unsigned int smp_threads = machine->smp.threads; 2525 unsigned int max_cpus = machine->smp.max_cpus; 2526 int boot_cores_nr = smp_cpus / smp_threads; 2527 int i; 2528 2529 possible_cpus = mc->possible_cpu_arch_ids(machine); 2530 if (mc->has_hotpluggable_cpus) { 2531 if (smp_cpus % smp_threads) { 2532 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2533 smp_cpus, smp_threads); 2534 exit(1); 2535 } 2536 if (max_cpus % smp_threads) { 2537 error_report("max_cpus (%u) must be multiple of threads (%u)", 2538 max_cpus, smp_threads); 2539 exit(1); 2540 } 2541 } else { 2542 if (max_cpus != smp_cpus) { 2543 error_report("This machine version does not support CPU hotplug"); 2544 exit(1); 2545 } 2546 boot_cores_nr = possible_cpus->len; 2547 } 2548 2549 if (smc->pre_2_10_has_unused_icps) { 2550 int i; 2551 2552 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2553 /* Dummy entries get deregistered when real ICPState objects 2554 * are registered during CPU core hotplug. 2555 */ 2556 pre_2_10_vmstate_register_dummy_icp(i); 2557 } 2558 } 2559 2560 for (i = 0; i < possible_cpus->len; i++) { 2561 int core_id = i * smp_threads; 2562 2563 if (mc->has_hotpluggable_cpus) { 2564 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2565 spapr_vcpu_id(spapr, core_id)); 2566 } 2567 2568 if (i < boot_cores_nr) { 2569 Object *core = object_new(type); 2570 int nr_threads = smp_threads; 2571 2572 /* Handle the partially filled core for older machine types */ 2573 if ((i + 1) * smp_threads >= smp_cpus) { 2574 nr_threads = smp_cpus - i * smp_threads; 2575 } 2576 2577 object_property_set_int(core, "nr-threads", nr_threads, 2578 &error_fatal); 2579 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2580 &error_fatal); 2581 qdev_realize(DEVICE(core), NULL, &error_fatal); 2582 2583 object_unref(core); 2584 } 2585 } 2586 } 2587 2588 static PCIHostState *spapr_create_default_phb(void) 2589 { 2590 DeviceState *dev; 2591 2592 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2593 qdev_prop_set_uint32(dev, "index", 0); 2594 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2595 2596 return PCI_HOST_BRIDGE(dev); 2597 } 2598 2599 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2600 { 2601 MachineState *machine = MACHINE(spapr); 2602 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2603 hwaddr rma_size = machine->ram_size; 2604 hwaddr node0_size = spapr_node0_size(machine); 2605 2606 /* RMA has to fit in the first NUMA node */ 2607 rma_size = MIN(rma_size, node0_size); 2608 2609 /* 2610 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2611 * never exceed that 2612 */ 2613 rma_size = MIN(rma_size, 1 * TiB); 2614 2615 /* 2616 * Clamp the RMA size based on machine type. This is for 2617 * migration compatibility with older qemu versions, which limited 2618 * the RMA size for complicated and mostly bad reasons. 2619 */ 2620 if (smc->rma_limit) { 2621 rma_size = MIN(rma_size, smc->rma_limit); 2622 } 2623 2624 if (rma_size < MIN_RMA_SLOF) { 2625 error_setg(errp, 2626 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2627 "ldMiB guest RMA (Real Mode Area memory)", 2628 MIN_RMA_SLOF / MiB); 2629 return 0; 2630 } 2631 2632 return rma_size; 2633 } 2634 2635 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2636 { 2637 MachineState *machine = MACHINE(spapr); 2638 int i; 2639 2640 for (i = 0; i < machine->ram_slots; i++) { 2641 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2642 } 2643 } 2644 2645 /* pSeries LPAR / sPAPR hardware init */ 2646 static void spapr_machine_init(MachineState *machine) 2647 { 2648 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2649 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2650 MachineClass *mc = MACHINE_GET_CLASS(machine); 2651 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2652 const char *kernel_filename = machine->kernel_filename; 2653 const char *initrd_filename = machine->initrd_filename; 2654 PCIHostState *phb; 2655 int i; 2656 MemoryRegion *sysmem = get_system_memory(); 2657 long load_limit, fw_size; 2658 char *filename; 2659 Error *resize_hpt_err = NULL; 2660 2661 /* 2662 * if Secure VM (PEF) support is configured, then initialize it 2663 */ 2664 pef_kvm_init(machine->cgs, &error_fatal); 2665 2666 msi_nonbroken = true; 2667 2668 QLIST_INIT(&spapr->phbs); 2669 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2670 2671 /* Determine capabilities to run with */ 2672 spapr_caps_init(spapr); 2673 2674 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2675 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2676 /* 2677 * If the user explicitly requested a mode we should either 2678 * supply it, or fail completely (which we do below). But if 2679 * it's not set explicitly, we reset our mode to something 2680 * that works 2681 */ 2682 if (resize_hpt_err) { 2683 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2684 error_free(resize_hpt_err); 2685 resize_hpt_err = NULL; 2686 } else { 2687 spapr->resize_hpt = smc->resize_hpt_default; 2688 } 2689 } 2690 2691 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2692 2693 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2694 /* 2695 * User requested HPT resize, but this host can't supply it. Bail out 2696 */ 2697 error_report_err(resize_hpt_err); 2698 exit(1); 2699 } 2700 error_free(resize_hpt_err); 2701 2702 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2703 2704 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2705 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2706 2707 /* 2708 * VSMT must be set in order to be able to compute VCPU ids, ie to 2709 * call spapr_max_server_number() or spapr_vcpu_id(). 2710 */ 2711 spapr_set_vsmt_mode(spapr, &error_fatal); 2712 2713 /* Set up Interrupt Controller before we create the VCPUs */ 2714 spapr_irq_init(spapr, &error_fatal); 2715 2716 /* Set up containers for ibm,client-architecture-support negotiated options 2717 */ 2718 spapr->ov5 = spapr_ovec_new(); 2719 spapr->ov5_cas = spapr_ovec_new(); 2720 2721 if (smc->dr_lmb_enabled) { 2722 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2723 spapr_validate_node_memory(machine, &error_fatal); 2724 } 2725 2726 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2727 2728 /* advertise support for dedicated HP event source to guests */ 2729 if (spapr->use_hotplug_event_source) { 2730 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2731 } 2732 2733 /* advertise support for HPT resizing */ 2734 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2735 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2736 } 2737 2738 /* advertise support for ibm,dyamic-memory-v2 */ 2739 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2740 2741 /* advertise XIVE on POWER9 machines */ 2742 if (spapr->irq->xive) { 2743 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2744 } 2745 2746 /* init CPUs */ 2747 spapr_init_cpus(spapr); 2748 2749 /* 2750 * check we don't have a memory-less/cpu-less NUMA node 2751 * Firmware relies on the existing memory/cpu topology to provide the 2752 * NUMA topology to the kernel. 2753 * And the linux kernel needs to know the NUMA topology at start 2754 * to be able to hotplug CPUs later. 2755 */ 2756 if (machine->numa_state->num_nodes) { 2757 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2758 /* check for memory-less node */ 2759 if (machine->numa_state->nodes[i].node_mem == 0) { 2760 CPUState *cs; 2761 int found = 0; 2762 /* check for cpu-less node */ 2763 CPU_FOREACH(cs) { 2764 PowerPCCPU *cpu = POWERPC_CPU(cs); 2765 if (cpu->node_id == i) { 2766 found = 1; 2767 break; 2768 } 2769 } 2770 /* memory-less and cpu-less node */ 2771 if (!found) { 2772 error_report( 2773 "Memory-less/cpu-less nodes are not supported (node %d)", 2774 i); 2775 exit(1); 2776 } 2777 } 2778 } 2779 2780 } 2781 2782 /* 2783 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2784 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2785 * called from vPHB reset handler so we initialize the counter here. 2786 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2787 * must be equally distant from any other node. 2788 * The final value of spapr->gpu_numa_id is going to be written to 2789 * max-associativity-domains in spapr_build_fdt(). 2790 */ 2791 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2792 2793 /* Init numa_assoc_array */ 2794 spapr_numa_associativity_init(spapr, machine); 2795 2796 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2797 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2798 spapr->max_compat_pvr)) { 2799 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2800 /* KVM and TCG always allow GTSE with radix... */ 2801 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2802 } 2803 /* ... but not with hash (currently). */ 2804 2805 if (kvm_enabled()) { 2806 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2807 kvmppc_enable_logical_ci_hcalls(); 2808 kvmppc_enable_set_mode_hcall(); 2809 2810 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2811 kvmppc_enable_clear_ref_mod_hcalls(); 2812 2813 /* Enable H_PAGE_INIT */ 2814 kvmppc_enable_h_page_init(); 2815 } 2816 2817 /* map RAM */ 2818 memory_region_add_subregion(sysmem, 0, machine->ram); 2819 2820 /* always allocate the device memory information */ 2821 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2822 2823 /* initialize hotplug memory address space */ 2824 if (machine->ram_size < machine->maxram_size) { 2825 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2826 /* 2827 * Limit the number of hotpluggable memory slots to half the number 2828 * slots that KVM supports, leaving the other half for PCI and other 2829 * devices. However ensure that number of slots doesn't drop below 32. 2830 */ 2831 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2832 SPAPR_MAX_RAM_SLOTS; 2833 2834 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2835 max_memslots = SPAPR_MAX_RAM_SLOTS; 2836 } 2837 if (machine->ram_slots > max_memslots) { 2838 error_report("Specified number of memory slots %" 2839 PRIu64" exceeds max supported %d", 2840 machine->ram_slots, max_memslots); 2841 exit(1); 2842 } 2843 2844 machine->device_memory->base = ROUND_UP(machine->ram_size, 2845 SPAPR_DEVICE_MEM_ALIGN); 2846 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2847 "device-memory", device_mem_size); 2848 memory_region_add_subregion(sysmem, machine->device_memory->base, 2849 &machine->device_memory->mr); 2850 } 2851 2852 if (smc->dr_lmb_enabled) { 2853 spapr_create_lmb_dr_connectors(spapr); 2854 } 2855 2856 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2857 /* Create the error string for live migration blocker */ 2858 error_setg(&spapr->fwnmi_migration_blocker, 2859 "A machine check is being handled during migration. The handler" 2860 "may run and log hardware error on the destination"); 2861 } 2862 2863 if (mc->nvdimm_supported) { 2864 spapr_create_nvdimm_dr_connectors(spapr); 2865 } 2866 2867 /* Set up RTAS event infrastructure */ 2868 spapr_events_init(spapr); 2869 2870 /* Set up the RTC RTAS interfaces */ 2871 spapr_rtc_create(spapr); 2872 2873 /* Set up VIO bus */ 2874 spapr->vio_bus = spapr_vio_bus_init(); 2875 2876 for (i = 0; serial_hd(i); i++) { 2877 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2878 } 2879 2880 /* We always have at least the nvram device on VIO */ 2881 spapr_create_nvram(spapr); 2882 2883 /* 2884 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2885 * connectors (described in root DT node's "ibm,drc-types" property) 2886 * are pre-initialized here. additional child connectors (such as 2887 * connectors for a PHBs PCI slots) are added as needed during their 2888 * parent's realization. 2889 */ 2890 if (smc->dr_phb_enabled) { 2891 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2892 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2893 } 2894 } 2895 2896 /* Set up PCI */ 2897 spapr_pci_rtas_init(); 2898 2899 phb = spapr_create_default_phb(); 2900 2901 for (i = 0; i < nb_nics; i++) { 2902 NICInfo *nd = &nd_table[i]; 2903 2904 if (!nd->model) { 2905 nd->model = g_strdup("spapr-vlan"); 2906 } 2907 2908 if (g_str_equal(nd->model, "spapr-vlan") || 2909 g_str_equal(nd->model, "ibmveth")) { 2910 spapr_vlan_create(spapr->vio_bus, nd); 2911 } else { 2912 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2913 } 2914 } 2915 2916 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2917 spapr_vscsi_create(spapr->vio_bus); 2918 } 2919 2920 /* Graphics */ 2921 if (spapr_vga_init(phb->bus, &error_fatal)) { 2922 spapr->has_graphics = true; 2923 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2924 } 2925 2926 if (machine->usb) { 2927 if (smc->use_ohci_by_default) { 2928 pci_create_simple(phb->bus, -1, "pci-ohci"); 2929 } else { 2930 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2931 } 2932 2933 if (spapr->has_graphics) { 2934 USBBus *usb_bus = usb_bus_find(-1); 2935 2936 usb_create_simple(usb_bus, "usb-kbd"); 2937 usb_create_simple(usb_bus, "usb-mouse"); 2938 } 2939 } 2940 2941 if (kernel_filename) { 2942 spapr->kernel_size = load_elf(kernel_filename, NULL, 2943 translate_kernel_address, spapr, 2944 NULL, NULL, NULL, NULL, 1, 2945 PPC_ELF_MACHINE, 0, 0); 2946 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2947 spapr->kernel_size = load_elf(kernel_filename, NULL, 2948 translate_kernel_address, spapr, 2949 NULL, NULL, NULL, NULL, 0, 2950 PPC_ELF_MACHINE, 0, 0); 2951 spapr->kernel_le = spapr->kernel_size > 0; 2952 } 2953 if (spapr->kernel_size < 0) { 2954 error_report("error loading %s: %s", kernel_filename, 2955 load_elf_strerror(spapr->kernel_size)); 2956 exit(1); 2957 } 2958 2959 /* load initrd */ 2960 if (initrd_filename) { 2961 /* Try to locate the initrd in the gap between the kernel 2962 * and the firmware. Add a bit of space just in case 2963 */ 2964 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2965 + 0x1ffff) & ~0xffff; 2966 spapr->initrd_size = load_image_targphys(initrd_filename, 2967 spapr->initrd_base, 2968 load_limit 2969 - spapr->initrd_base); 2970 if (spapr->initrd_size < 0) { 2971 error_report("could not load initial ram disk '%s'", 2972 initrd_filename); 2973 exit(1); 2974 } 2975 } 2976 } 2977 2978 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2979 if (!filename) { 2980 error_report("Could not find LPAR firmware '%s'", bios_name); 2981 exit(1); 2982 } 2983 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2984 if (fw_size <= 0) { 2985 error_report("Could not load LPAR firmware '%s'", filename); 2986 exit(1); 2987 } 2988 g_free(filename); 2989 2990 /* FIXME: Should register things through the MachineState's qdev 2991 * interface, this is a legacy from the sPAPREnvironment structure 2992 * which predated MachineState but had a similar function */ 2993 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2994 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2995 &savevm_htab_handlers, spapr); 2996 2997 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2998 2999 qemu_register_boot_set(spapr_boot_set, spapr); 3000 3001 /* 3002 * Nothing needs to be done to resume a suspended guest because 3003 * suspending does not change the machine state, so no need for 3004 * a ->wakeup method. 3005 */ 3006 qemu_register_wakeup_support(); 3007 3008 if (kvm_enabled()) { 3009 /* to stop and start vmclock */ 3010 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3011 &spapr->tb); 3012 3013 kvmppc_spapr_enable_inkernel_multitce(); 3014 } 3015 3016 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3017 } 3018 3019 #define DEFAULT_KVM_TYPE "auto" 3020 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3021 { 3022 /* 3023 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3024 * accomodate the 'HV' and 'PV' formats that exists in the 3025 * wild. The 'auto' mode is being introduced already as 3026 * lower-case, thus we don't need to bother checking for 3027 * "AUTO". 3028 */ 3029 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3030 return 0; 3031 } 3032 3033 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3034 return 1; 3035 } 3036 3037 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3038 return 2; 3039 } 3040 3041 error_report("Unknown kvm-type specified '%s'", vm_type); 3042 exit(1); 3043 } 3044 3045 /* 3046 * Implementation of an interface to adjust firmware path 3047 * for the bootindex property handling. 3048 */ 3049 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3050 DeviceState *dev) 3051 { 3052 #define CAST(type, obj, name) \ 3053 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3054 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3055 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3056 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3057 3058 if (d) { 3059 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3060 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3061 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3062 3063 if (spapr) { 3064 /* 3065 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3066 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3067 * 0x8000 | (target << 8) | (bus << 5) | lun 3068 * (see the "Logical unit addressing format" table in SAM5) 3069 */ 3070 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3071 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3072 (uint64_t)id << 48); 3073 } else if (virtio) { 3074 /* 3075 * We use SRP luns of the form 01000000 | (target << 8) | lun 3076 * in the top 32 bits of the 64-bit LUN 3077 * Note: the quote above is from SLOF and it is wrong, 3078 * the actual binding is: 3079 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3080 */ 3081 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3082 if (d->lun >= 256) { 3083 /* Use the LUN "flat space addressing method" */ 3084 id |= 0x4000; 3085 } 3086 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3087 (uint64_t)id << 32); 3088 } else if (usb) { 3089 /* 3090 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3091 * in the top 32 bits of the 64-bit LUN 3092 */ 3093 unsigned usb_port = atoi(usb->port->path); 3094 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3095 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3096 (uint64_t)id << 32); 3097 } 3098 } 3099 3100 /* 3101 * SLOF probes the USB devices, and if it recognizes that the device is a 3102 * storage device, it changes its name to "storage" instead of "usb-host", 3103 * and additionally adds a child node for the SCSI LUN, so the correct 3104 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3105 */ 3106 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3107 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3108 if (usb_host_dev_is_scsi_storage(usbdev)) { 3109 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3110 } 3111 } 3112 3113 if (phb) { 3114 /* Replace "pci" with "pci@800000020000000" */ 3115 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3116 } 3117 3118 if (vsc) { 3119 /* Same logic as virtio above */ 3120 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3121 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3122 } 3123 3124 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3125 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3126 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3127 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3128 } 3129 3130 return NULL; 3131 } 3132 3133 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3134 { 3135 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3136 3137 return g_strdup(spapr->kvm_type); 3138 } 3139 3140 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3141 { 3142 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3143 3144 g_free(spapr->kvm_type); 3145 spapr->kvm_type = g_strdup(value); 3146 } 3147 3148 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3149 { 3150 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3151 3152 return spapr->use_hotplug_event_source; 3153 } 3154 3155 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3156 Error **errp) 3157 { 3158 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3159 3160 spapr->use_hotplug_event_source = value; 3161 } 3162 3163 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3164 { 3165 return true; 3166 } 3167 3168 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3169 { 3170 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3171 3172 switch (spapr->resize_hpt) { 3173 case SPAPR_RESIZE_HPT_DEFAULT: 3174 return g_strdup("default"); 3175 case SPAPR_RESIZE_HPT_DISABLED: 3176 return g_strdup("disabled"); 3177 case SPAPR_RESIZE_HPT_ENABLED: 3178 return g_strdup("enabled"); 3179 case SPAPR_RESIZE_HPT_REQUIRED: 3180 return g_strdup("required"); 3181 } 3182 g_assert_not_reached(); 3183 } 3184 3185 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3186 { 3187 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3188 3189 if (strcmp(value, "default") == 0) { 3190 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3191 } else if (strcmp(value, "disabled") == 0) { 3192 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3193 } else if (strcmp(value, "enabled") == 0) { 3194 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3195 } else if (strcmp(value, "required") == 0) { 3196 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3197 } else { 3198 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3199 } 3200 } 3201 3202 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3203 { 3204 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3205 3206 if (spapr->irq == &spapr_irq_xics_legacy) { 3207 return g_strdup("legacy"); 3208 } else if (spapr->irq == &spapr_irq_xics) { 3209 return g_strdup("xics"); 3210 } else if (spapr->irq == &spapr_irq_xive) { 3211 return g_strdup("xive"); 3212 } else if (spapr->irq == &spapr_irq_dual) { 3213 return g_strdup("dual"); 3214 } 3215 g_assert_not_reached(); 3216 } 3217 3218 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3219 { 3220 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3221 3222 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3223 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3224 return; 3225 } 3226 3227 /* The legacy IRQ backend can not be set */ 3228 if (strcmp(value, "xics") == 0) { 3229 spapr->irq = &spapr_irq_xics; 3230 } else if (strcmp(value, "xive") == 0) { 3231 spapr->irq = &spapr_irq_xive; 3232 } else if (strcmp(value, "dual") == 0) { 3233 spapr->irq = &spapr_irq_dual; 3234 } else { 3235 error_setg(errp, "Bad value for \"ic-mode\" property"); 3236 } 3237 } 3238 3239 static char *spapr_get_host_model(Object *obj, Error **errp) 3240 { 3241 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3242 3243 return g_strdup(spapr->host_model); 3244 } 3245 3246 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3247 { 3248 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3249 3250 g_free(spapr->host_model); 3251 spapr->host_model = g_strdup(value); 3252 } 3253 3254 static char *spapr_get_host_serial(Object *obj, Error **errp) 3255 { 3256 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3257 3258 return g_strdup(spapr->host_serial); 3259 } 3260 3261 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3262 { 3263 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3264 3265 g_free(spapr->host_serial); 3266 spapr->host_serial = g_strdup(value); 3267 } 3268 3269 static void spapr_instance_init(Object *obj) 3270 { 3271 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3272 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3273 MachineState *ms = MACHINE(spapr); 3274 MachineClass *mc = MACHINE_GET_CLASS(ms); 3275 3276 /* 3277 * NVDIMM support went live in 5.1 without considering that, in 3278 * other archs, the user needs to enable NVDIMM support with the 3279 * 'nvdimm' machine option and the default behavior is NVDIMM 3280 * support disabled. It is too late to roll back to the standard 3281 * behavior without breaking 5.1 guests. 3282 */ 3283 if (mc->nvdimm_supported) { 3284 ms->nvdimms_state->is_enabled = true; 3285 } 3286 3287 spapr->htab_fd = -1; 3288 spapr->use_hotplug_event_source = true; 3289 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3290 object_property_add_str(obj, "kvm-type", 3291 spapr_get_kvm_type, spapr_set_kvm_type); 3292 object_property_set_description(obj, "kvm-type", 3293 "Specifies the KVM virtualization mode (auto," 3294 " hv, pr). Defaults to 'auto'. This mode will use" 3295 " any available KVM module loaded in the host," 3296 " where kvm_hv takes precedence if both kvm_hv and" 3297 " kvm_pr are loaded."); 3298 object_property_add_bool(obj, "modern-hotplug-events", 3299 spapr_get_modern_hotplug_events, 3300 spapr_set_modern_hotplug_events); 3301 object_property_set_description(obj, "modern-hotplug-events", 3302 "Use dedicated hotplug event mechanism in" 3303 " place of standard EPOW events when possible" 3304 " (required for memory hot-unplug support)"); 3305 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3306 "Maximum permitted CPU compatibility mode"); 3307 3308 object_property_add_str(obj, "resize-hpt", 3309 spapr_get_resize_hpt, spapr_set_resize_hpt); 3310 object_property_set_description(obj, "resize-hpt", 3311 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3312 object_property_add_uint32_ptr(obj, "vsmt", 3313 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3314 object_property_set_description(obj, "vsmt", 3315 "Virtual SMT: KVM behaves as if this were" 3316 " the host's SMT mode"); 3317 3318 object_property_add_bool(obj, "vfio-no-msix-emulation", 3319 spapr_get_msix_emulation, NULL); 3320 3321 object_property_add_uint64_ptr(obj, "kernel-addr", 3322 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3323 object_property_set_description(obj, "kernel-addr", 3324 stringify(KERNEL_LOAD_ADDR) 3325 " for -kernel is the default"); 3326 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3327 /* The machine class defines the default interrupt controller mode */ 3328 spapr->irq = smc->irq; 3329 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3330 spapr_set_ic_mode); 3331 object_property_set_description(obj, "ic-mode", 3332 "Specifies the interrupt controller mode (xics, xive, dual)"); 3333 3334 object_property_add_str(obj, "host-model", 3335 spapr_get_host_model, spapr_set_host_model); 3336 object_property_set_description(obj, "host-model", 3337 "Host model to advertise in guest device tree"); 3338 object_property_add_str(obj, "host-serial", 3339 spapr_get_host_serial, spapr_set_host_serial); 3340 object_property_set_description(obj, "host-serial", 3341 "Host serial number to advertise in guest device tree"); 3342 } 3343 3344 static void spapr_machine_finalizefn(Object *obj) 3345 { 3346 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3347 3348 g_free(spapr->kvm_type); 3349 } 3350 3351 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3352 { 3353 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3354 PowerPCCPU *cpu = POWERPC_CPU(cs); 3355 CPUPPCState *env = &cpu->env; 3356 3357 cpu_synchronize_state(cs); 3358 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3359 if (spapr->fwnmi_system_reset_addr != -1) { 3360 uint64_t rtas_addr, addr; 3361 3362 /* get rtas addr from fdt */ 3363 rtas_addr = spapr_get_rtas_addr(); 3364 if (!rtas_addr) { 3365 qemu_system_guest_panicked(NULL); 3366 return; 3367 } 3368 3369 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3370 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3371 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3372 env->gpr[3] = addr; 3373 } 3374 ppc_cpu_do_system_reset(cs); 3375 if (spapr->fwnmi_system_reset_addr != -1) { 3376 env->nip = spapr->fwnmi_system_reset_addr; 3377 } 3378 } 3379 3380 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3381 { 3382 CPUState *cs; 3383 3384 CPU_FOREACH(cs) { 3385 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3386 } 3387 } 3388 3389 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3390 void *fdt, int *fdt_start_offset, Error **errp) 3391 { 3392 uint64_t addr; 3393 uint32_t node; 3394 3395 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3396 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3397 &error_abort); 3398 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3399 SPAPR_MEMORY_BLOCK_SIZE); 3400 return 0; 3401 } 3402 3403 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3404 bool dedicated_hp_event_source) 3405 { 3406 SpaprDrc *drc; 3407 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3408 int i; 3409 uint64_t addr = addr_start; 3410 bool hotplugged = spapr_drc_hotplugged(dev); 3411 3412 for (i = 0; i < nr_lmbs; i++) { 3413 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3414 addr / SPAPR_MEMORY_BLOCK_SIZE); 3415 g_assert(drc); 3416 3417 /* 3418 * memory_device_get_free_addr() provided a range of free addresses 3419 * that doesn't overlap with any existing mapping at pre-plug. The 3420 * corresponding LMB DRCs are thus assumed to be all attachable. 3421 */ 3422 spapr_drc_attach(drc, dev); 3423 if (!hotplugged) { 3424 spapr_drc_reset(drc); 3425 } 3426 addr += SPAPR_MEMORY_BLOCK_SIZE; 3427 } 3428 /* send hotplug notification to the 3429 * guest only in case of hotplugged memory 3430 */ 3431 if (hotplugged) { 3432 if (dedicated_hp_event_source) { 3433 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3434 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3435 g_assert(drc); 3436 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3437 nr_lmbs, 3438 spapr_drc_index(drc)); 3439 } else { 3440 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3441 nr_lmbs); 3442 } 3443 } 3444 } 3445 3446 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3447 { 3448 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3449 PCDIMMDevice *dimm = PC_DIMM(dev); 3450 uint64_t size, addr; 3451 int64_t slot; 3452 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3453 3454 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3455 3456 pc_dimm_plug(dimm, MACHINE(ms)); 3457 3458 if (!is_nvdimm) { 3459 addr = object_property_get_uint(OBJECT(dimm), 3460 PC_DIMM_ADDR_PROP, &error_abort); 3461 spapr_add_lmbs(dev, addr, size, 3462 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3463 } else { 3464 slot = object_property_get_int(OBJECT(dimm), 3465 PC_DIMM_SLOT_PROP, &error_abort); 3466 /* We should have valid slot number at this point */ 3467 g_assert(slot >= 0); 3468 spapr_add_nvdimm(dev, slot); 3469 } 3470 } 3471 3472 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3473 Error **errp) 3474 { 3475 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3476 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3477 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3478 PCDIMMDevice *dimm = PC_DIMM(dev); 3479 Error *local_err = NULL; 3480 uint64_t size; 3481 Object *memdev; 3482 hwaddr pagesize; 3483 3484 if (!smc->dr_lmb_enabled) { 3485 error_setg(errp, "Memory hotplug not supported for this machine"); 3486 return; 3487 } 3488 3489 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3490 if (local_err) { 3491 error_propagate(errp, local_err); 3492 return; 3493 } 3494 3495 if (is_nvdimm) { 3496 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3497 return; 3498 } 3499 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3500 error_setg(errp, "Hotplugged memory size must be a multiple of " 3501 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3502 return; 3503 } 3504 3505 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3506 &error_abort); 3507 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3508 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3509 return; 3510 } 3511 3512 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3513 } 3514 3515 struct SpaprDimmState { 3516 PCDIMMDevice *dimm; 3517 uint32_t nr_lmbs; 3518 QTAILQ_ENTRY(SpaprDimmState) next; 3519 }; 3520 3521 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3522 PCDIMMDevice *dimm) 3523 { 3524 SpaprDimmState *dimm_state = NULL; 3525 3526 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3527 if (dimm_state->dimm == dimm) { 3528 break; 3529 } 3530 } 3531 return dimm_state; 3532 } 3533 3534 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3535 uint32_t nr_lmbs, 3536 PCDIMMDevice *dimm) 3537 { 3538 SpaprDimmState *ds = NULL; 3539 3540 /* 3541 * If this request is for a DIMM whose removal had failed earlier 3542 * (due to guest's refusal to remove the LMBs), we would have this 3543 * dimm already in the pending_dimm_unplugs list. In that 3544 * case don't add again. 3545 */ 3546 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3547 if (!ds) { 3548 ds = g_malloc0(sizeof(SpaprDimmState)); 3549 ds->nr_lmbs = nr_lmbs; 3550 ds->dimm = dimm; 3551 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3552 } 3553 return ds; 3554 } 3555 3556 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3557 SpaprDimmState *dimm_state) 3558 { 3559 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3560 g_free(dimm_state); 3561 } 3562 3563 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3564 PCDIMMDevice *dimm) 3565 { 3566 SpaprDrc *drc; 3567 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3568 &error_abort); 3569 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3570 uint32_t avail_lmbs = 0; 3571 uint64_t addr_start, addr; 3572 int i; 3573 3574 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3575 &error_abort); 3576 3577 addr = addr_start; 3578 for (i = 0; i < nr_lmbs; i++) { 3579 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3580 addr / SPAPR_MEMORY_BLOCK_SIZE); 3581 g_assert(drc); 3582 if (drc->dev) { 3583 avail_lmbs++; 3584 } 3585 addr += SPAPR_MEMORY_BLOCK_SIZE; 3586 } 3587 3588 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3589 } 3590 3591 /* Callback to be called during DRC release. */ 3592 void spapr_lmb_release(DeviceState *dev) 3593 { 3594 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3595 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3596 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3597 3598 /* This information will get lost if a migration occurs 3599 * during the unplug process. In this case recover it. */ 3600 if (ds == NULL) { 3601 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3602 g_assert(ds); 3603 /* The DRC being examined by the caller at least must be counted */ 3604 g_assert(ds->nr_lmbs); 3605 } 3606 3607 if (--ds->nr_lmbs) { 3608 return; 3609 } 3610 3611 /* 3612 * Now that all the LMBs have been removed by the guest, call the 3613 * unplug handler chain. This can never fail. 3614 */ 3615 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3616 object_unparent(OBJECT(dev)); 3617 } 3618 3619 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3620 { 3621 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3622 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3623 3624 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3625 qdev_unrealize(dev); 3626 spapr_pending_dimm_unplugs_remove(spapr, ds); 3627 } 3628 3629 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3630 DeviceState *dev, Error **errp) 3631 { 3632 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3633 PCDIMMDevice *dimm = PC_DIMM(dev); 3634 uint32_t nr_lmbs; 3635 uint64_t size, addr_start, addr; 3636 int i; 3637 SpaprDrc *drc; 3638 3639 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3640 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3641 return; 3642 } 3643 3644 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3645 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3646 3647 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3648 &error_abort); 3649 3650 /* 3651 * An existing pending dimm state for this DIMM means that there is an 3652 * unplug operation in progress, waiting for the spapr_lmb_release 3653 * callback to complete the job (BQL can't cover that far). In this case, 3654 * bail out to avoid detaching DRCs that were already released. 3655 */ 3656 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3657 error_setg(errp, "Memory unplug already in progress for device %s", 3658 dev->id); 3659 return; 3660 } 3661 3662 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3663 3664 addr = addr_start; 3665 for (i = 0; i < nr_lmbs; i++) { 3666 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3667 addr / SPAPR_MEMORY_BLOCK_SIZE); 3668 g_assert(drc); 3669 3670 spapr_drc_detach(drc); 3671 addr += SPAPR_MEMORY_BLOCK_SIZE; 3672 } 3673 3674 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3675 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3676 g_assert(drc); 3677 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3678 nr_lmbs, spapr_drc_index(drc)); 3679 } 3680 3681 /* Callback to be called during DRC release. */ 3682 void spapr_core_release(DeviceState *dev) 3683 { 3684 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3685 3686 /* Call the unplug handler chain. This can never fail. */ 3687 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3688 object_unparent(OBJECT(dev)); 3689 } 3690 3691 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3692 { 3693 MachineState *ms = MACHINE(hotplug_dev); 3694 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3695 CPUCore *cc = CPU_CORE(dev); 3696 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3697 3698 if (smc->pre_2_10_has_unused_icps) { 3699 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3700 int i; 3701 3702 for (i = 0; i < cc->nr_threads; i++) { 3703 CPUState *cs = CPU(sc->threads[i]); 3704 3705 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3706 } 3707 } 3708 3709 assert(core_slot); 3710 core_slot->cpu = NULL; 3711 qdev_unrealize(dev); 3712 } 3713 3714 static 3715 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3716 Error **errp) 3717 { 3718 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3719 int index; 3720 SpaprDrc *drc; 3721 CPUCore *cc = CPU_CORE(dev); 3722 3723 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3724 error_setg(errp, "Unable to find CPU core with core-id: %d", 3725 cc->core_id); 3726 return; 3727 } 3728 if (index == 0) { 3729 error_setg(errp, "Boot CPU core may not be unplugged"); 3730 return; 3731 } 3732 3733 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3734 spapr_vcpu_id(spapr, cc->core_id)); 3735 g_assert(drc); 3736 3737 if (!spapr_drc_unplug_requested(drc)) { 3738 spapr_drc_detach(drc); 3739 spapr_hotplug_req_remove_by_index(drc); 3740 } 3741 } 3742 3743 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3744 void *fdt, int *fdt_start_offset, Error **errp) 3745 { 3746 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3747 CPUState *cs = CPU(core->threads[0]); 3748 PowerPCCPU *cpu = POWERPC_CPU(cs); 3749 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3750 int id = spapr_get_vcpu_id(cpu); 3751 g_autofree char *nodename = NULL; 3752 int offset; 3753 3754 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3755 offset = fdt_add_subnode(fdt, 0, nodename); 3756 3757 spapr_dt_cpu(cs, fdt, offset, spapr); 3758 3759 *fdt_start_offset = offset; 3760 return 0; 3761 } 3762 3763 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3764 { 3765 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3766 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3767 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3768 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3769 CPUCore *cc = CPU_CORE(dev); 3770 CPUState *cs; 3771 SpaprDrc *drc; 3772 CPUArchId *core_slot; 3773 int index; 3774 bool hotplugged = spapr_drc_hotplugged(dev); 3775 int i; 3776 3777 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3778 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3779 3780 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3781 spapr_vcpu_id(spapr, cc->core_id)); 3782 3783 g_assert(drc || !mc->has_hotpluggable_cpus); 3784 3785 if (drc) { 3786 /* 3787 * spapr_core_pre_plug() already buys us this is a brand new 3788 * core being plugged into a free slot. Nothing should already 3789 * be attached to the corresponding DRC. 3790 */ 3791 spapr_drc_attach(drc, dev); 3792 3793 if (hotplugged) { 3794 /* 3795 * Send hotplug notification interrupt to the guest only 3796 * in case of hotplugged CPUs. 3797 */ 3798 spapr_hotplug_req_add_by_index(drc); 3799 } else { 3800 spapr_drc_reset(drc); 3801 } 3802 } 3803 3804 core_slot->cpu = OBJECT(dev); 3805 3806 /* 3807 * Set compatibility mode to match the boot CPU, which was either set 3808 * by the machine reset code or by CAS. This really shouldn't fail at 3809 * this point. 3810 */ 3811 if (hotplugged) { 3812 for (i = 0; i < cc->nr_threads; i++) { 3813 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3814 &error_abort); 3815 } 3816 } 3817 3818 if (smc->pre_2_10_has_unused_icps) { 3819 for (i = 0; i < cc->nr_threads; i++) { 3820 cs = CPU(core->threads[i]); 3821 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3822 } 3823 } 3824 } 3825 3826 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3827 Error **errp) 3828 { 3829 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3830 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3831 CPUCore *cc = CPU_CORE(dev); 3832 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3833 const char *type = object_get_typename(OBJECT(dev)); 3834 CPUArchId *core_slot; 3835 int index; 3836 unsigned int smp_threads = machine->smp.threads; 3837 3838 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3839 error_setg(errp, "CPU hotplug not supported for this machine"); 3840 return; 3841 } 3842 3843 if (strcmp(base_core_type, type)) { 3844 error_setg(errp, "CPU core type should be %s", base_core_type); 3845 return; 3846 } 3847 3848 if (cc->core_id % smp_threads) { 3849 error_setg(errp, "invalid core id %d", cc->core_id); 3850 return; 3851 } 3852 3853 /* 3854 * In general we should have homogeneous threads-per-core, but old 3855 * (pre hotplug support) machine types allow the last core to have 3856 * reduced threads as a compatibility hack for when we allowed 3857 * total vcpus not a multiple of threads-per-core. 3858 */ 3859 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3860 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3861 smp_threads); 3862 return; 3863 } 3864 3865 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3866 if (!core_slot) { 3867 error_setg(errp, "core id %d out of range", cc->core_id); 3868 return; 3869 } 3870 3871 if (core_slot->cpu) { 3872 error_setg(errp, "core %d already populated", cc->core_id); 3873 return; 3874 } 3875 3876 numa_cpu_pre_plug(core_slot, dev, errp); 3877 } 3878 3879 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3880 void *fdt, int *fdt_start_offset, Error **errp) 3881 { 3882 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3883 int intc_phandle; 3884 3885 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3886 if (intc_phandle <= 0) { 3887 return -1; 3888 } 3889 3890 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3891 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3892 return -1; 3893 } 3894 3895 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3896 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3897 3898 return 0; 3899 } 3900 3901 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3902 Error **errp) 3903 { 3904 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3905 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3906 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3907 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3908 SpaprDrc *drc; 3909 3910 if (dev->hotplugged && !smc->dr_phb_enabled) { 3911 error_setg(errp, "PHB hotplug not supported for this machine"); 3912 return false; 3913 } 3914 3915 if (sphb->index == (uint32_t)-1) { 3916 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3917 return false; 3918 } 3919 3920 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3921 if (drc && drc->dev) { 3922 error_setg(errp, "PHB %d already attached", sphb->index); 3923 return false; 3924 } 3925 3926 /* 3927 * This will check that sphb->index doesn't exceed the maximum number of 3928 * PHBs for the current machine type. 3929 */ 3930 return 3931 smc->phb_placement(spapr, sphb->index, 3932 &sphb->buid, &sphb->io_win_addr, 3933 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3934 windows_supported, sphb->dma_liobn, 3935 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3936 errp); 3937 } 3938 3939 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3940 { 3941 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3942 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3943 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3944 SpaprDrc *drc; 3945 bool hotplugged = spapr_drc_hotplugged(dev); 3946 3947 if (!smc->dr_phb_enabled) { 3948 return; 3949 } 3950 3951 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3952 /* hotplug hooks should check it's enabled before getting this far */ 3953 assert(drc); 3954 3955 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 3956 spapr_drc_attach(drc, dev); 3957 3958 if (hotplugged) { 3959 spapr_hotplug_req_add_by_index(drc); 3960 } else { 3961 spapr_drc_reset(drc); 3962 } 3963 } 3964 3965 void spapr_phb_release(DeviceState *dev) 3966 { 3967 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3968 3969 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3970 object_unparent(OBJECT(dev)); 3971 } 3972 3973 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3974 { 3975 qdev_unrealize(dev); 3976 } 3977 3978 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3979 DeviceState *dev, Error **errp) 3980 { 3981 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3982 SpaprDrc *drc; 3983 3984 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3985 assert(drc); 3986 3987 if (!spapr_drc_unplug_requested(drc)) { 3988 spapr_drc_detach(drc); 3989 spapr_hotplug_req_remove_by_index(drc); 3990 } 3991 } 3992 3993 static 3994 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3995 Error **errp) 3996 { 3997 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3998 3999 if (spapr->tpm_proxy != NULL) { 4000 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4001 return false; 4002 } 4003 4004 return true; 4005 } 4006 4007 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4008 { 4009 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4010 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4011 4012 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4013 g_assert(spapr->tpm_proxy == NULL); 4014 4015 spapr->tpm_proxy = tpm_proxy; 4016 } 4017 4018 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4019 { 4020 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4021 4022 qdev_unrealize(dev); 4023 object_unparent(OBJECT(dev)); 4024 spapr->tpm_proxy = NULL; 4025 } 4026 4027 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4028 DeviceState *dev, Error **errp) 4029 { 4030 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4031 spapr_memory_plug(hotplug_dev, dev); 4032 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4033 spapr_core_plug(hotplug_dev, dev); 4034 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4035 spapr_phb_plug(hotplug_dev, dev); 4036 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4037 spapr_tpm_proxy_plug(hotplug_dev, dev); 4038 } 4039 } 4040 4041 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4042 DeviceState *dev, Error **errp) 4043 { 4044 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4045 spapr_memory_unplug(hotplug_dev, dev); 4046 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4047 spapr_core_unplug(hotplug_dev, dev); 4048 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4049 spapr_phb_unplug(hotplug_dev, dev); 4050 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4051 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4052 } 4053 } 4054 4055 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4056 { 4057 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4058 /* 4059 * CAS will process all pending unplug requests. 4060 * 4061 * HACK: a guest could theoretically have cleared all bits in OV5, 4062 * but none of the guests we care for do. 4063 */ 4064 spapr_ovec_empty(spapr->ov5_cas); 4065 } 4066 4067 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4068 DeviceState *dev, Error **errp) 4069 { 4070 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4071 MachineClass *mc = MACHINE_GET_CLASS(sms); 4072 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4073 4074 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4075 if (spapr_memory_hot_unplug_supported(sms)) { 4076 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4077 } else { 4078 error_setg(errp, "Memory hot unplug not supported for this guest"); 4079 } 4080 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4081 if (!mc->has_hotpluggable_cpus) { 4082 error_setg(errp, "CPU hot unplug not supported on this machine"); 4083 return; 4084 } 4085 spapr_core_unplug_request(hotplug_dev, dev, errp); 4086 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4087 if (!smc->dr_phb_enabled) { 4088 error_setg(errp, "PHB hot unplug not supported on this machine"); 4089 return; 4090 } 4091 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4092 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4093 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4094 } 4095 } 4096 4097 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4098 DeviceState *dev, Error **errp) 4099 { 4100 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4101 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4102 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4103 spapr_core_pre_plug(hotplug_dev, dev, errp); 4104 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4105 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4106 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4107 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4108 } 4109 } 4110 4111 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4112 DeviceState *dev) 4113 { 4114 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4115 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4116 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4117 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4118 return HOTPLUG_HANDLER(machine); 4119 } 4120 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4121 PCIDevice *pcidev = PCI_DEVICE(dev); 4122 PCIBus *root = pci_device_root_bus(pcidev); 4123 SpaprPhbState *phb = 4124 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4125 TYPE_SPAPR_PCI_HOST_BRIDGE); 4126 4127 if (phb) { 4128 return HOTPLUG_HANDLER(phb); 4129 } 4130 } 4131 return NULL; 4132 } 4133 4134 static CpuInstanceProperties 4135 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4136 { 4137 CPUArchId *core_slot; 4138 MachineClass *mc = MACHINE_GET_CLASS(machine); 4139 4140 /* make sure possible_cpu are intialized */ 4141 mc->possible_cpu_arch_ids(machine); 4142 /* get CPU core slot containing thread that matches cpu_index */ 4143 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4144 assert(core_slot); 4145 return core_slot->props; 4146 } 4147 4148 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4149 { 4150 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4151 } 4152 4153 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4154 { 4155 int i; 4156 unsigned int smp_threads = machine->smp.threads; 4157 unsigned int smp_cpus = machine->smp.cpus; 4158 const char *core_type; 4159 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4160 MachineClass *mc = MACHINE_GET_CLASS(machine); 4161 4162 if (!mc->has_hotpluggable_cpus) { 4163 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4164 } 4165 if (machine->possible_cpus) { 4166 assert(machine->possible_cpus->len == spapr_max_cores); 4167 return machine->possible_cpus; 4168 } 4169 4170 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4171 if (!core_type) { 4172 error_report("Unable to find sPAPR CPU Core definition"); 4173 exit(1); 4174 } 4175 4176 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4177 sizeof(CPUArchId) * spapr_max_cores); 4178 machine->possible_cpus->len = spapr_max_cores; 4179 for (i = 0; i < machine->possible_cpus->len; i++) { 4180 int core_id = i * smp_threads; 4181 4182 machine->possible_cpus->cpus[i].type = core_type; 4183 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4184 machine->possible_cpus->cpus[i].arch_id = core_id; 4185 machine->possible_cpus->cpus[i].props.has_core_id = true; 4186 machine->possible_cpus->cpus[i].props.core_id = core_id; 4187 } 4188 return machine->possible_cpus; 4189 } 4190 4191 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4192 uint64_t *buid, hwaddr *pio, 4193 hwaddr *mmio32, hwaddr *mmio64, 4194 unsigned n_dma, uint32_t *liobns, 4195 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4196 { 4197 /* 4198 * New-style PHB window placement. 4199 * 4200 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4201 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4202 * windows. 4203 * 4204 * Some guest kernels can't work with MMIO windows above 1<<46 4205 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4206 * 4207 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4208 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4209 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4210 * 1TiB 64-bit MMIO windows for each PHB. 4211 */ 4212 const uint64_t base_buid = 0x800000020000000ULL; 4213 int i; 4214 4215 /* Sanity check natural alignments */ 4216 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4217 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4218 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4219 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4220 /* Sanity check bounds */ 4221 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4222 SPAPR_PCI_MEM32_WIN_SIZE); 4223 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4224 SPAPR_PCI_MEM64_WIN_SIZE); 4225 4226 if (index >= SPAPR_MAX_PHBS) { 4227 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4228 SPAPR_MAX_PHBS - 1); 4229 return false; 4230 } 4231 4232 *buid = base_buid + index; 4233 for (i = 0; i < n_dma; ++i) { 4234 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4235 } 4236 4237 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4238 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4239 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4240 4241 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4242 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4243 return true; 4244 } 4245 4246 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4247 { 4248 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4249 4250 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4251 } 4252 4253 static void spapr_ics_resend(XICSFabric *dev) 4254 { 4255 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4256 4257 ics_resend(spapr->ics); 4258 } 4259 4260 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4261 { 4262 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4263 4264 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4265 } 4266 4267 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4268 Monitor *mon) 4269 { 4270 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4271 4272 spapr_irq_print_info(spapr, mon); 4273 monitor_printf(mon, "irqchip: %s\n", 4274 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4275 } 4276 4277 /* 4278 * This is a XIVE only operation 4279 */ 4280 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4281 uint8_t nvt_blk, uint32_t nvt_idx, 4282 bool cam_ignore, uint8_t priority, 4283 uint32_t logic_serv, XiveTCTXMatch *match) 4284 { 4285 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4286 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4287 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4288 int count; 4289 4290 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4291 priority, logic_serv, match); 4292 if (count < 0) { 4293 return count; 4294 } 4295 4296 /* 4297 * When we implement the save and restore of the thread interrupt 4298 * contexts in the enter/exit CPU handlers of the machine and the 4299 * escalations in QEMU, we should be able to handle non dispatched 4300 * vCPUs. 4301 * 4302 * Until this is done, the sPAPR machine should find at least one 4303 * matching context always. 4304 */ 4305 if (count == 0) { 4306 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4307 nvt_blk, nvt_idx); 4308 } 4309 4310 return count; 4311 } 4312 4313 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4314 { 4315 return cpu->vcpu_id; 4316 } 4317 4318 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4319 { 4320 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4321 MachineState *ms = MACHINE(spapr); 4322 int vcpu_id; 4323 4324 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4325 4326 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4327 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4328 error_append_hint(errp, "Adjust the number of cpus to %d " 4329 "or try to raise the number of threads per core\n", 4330 vcpu_id * ms->smp.threads / spapr->vsmt); 4331 return false; 4332 } 4333 4334 cpu->vcpu_id = vcpu_id; 4335 return true; 4336 } 4337 4338 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4339 { 4340 CPUState *cs; 4341 4342 CPU_FOREACH(cs) { 4343 PowerPCCPU *cpu = POWERPC_CPU(cs); 4344 4345 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4346 return cpu; 4347 } 4348 } 4349 4350 return NULL; 4351 } 4352 4353 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4354 { 4355 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4356 4357 /* These are only called by TCG, KVM maintains dispatch state */ 4358 4359 spapr_cpu->prod = false; 4360 if (spapr_cpu->vpa_addr) { 4361 CPUState *cs = CPU(cpu); 4362 uint32_t dispatch; 4363 4364 dispatch = ldl_be_phys(cs->as, 4365 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4366 dispatch++; 4367 if ((dispatch & 1) != 0) { 4368 qemu_log_mask(LOG_GUEST_ERROR, 4369 "VPA: incorrect dispatch counter value for " 4370 "dispatched partition %u, correcting.\n", dispatch); 4371 dispatch++; 4372 } 4373 stl_be_phys(cs->as, 4374 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4375 } 4376 } 4377 4378 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4379 { 4380 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4381 4382 if (spapr_cpu->vpa_addr) { 4383 CPUState *cs = CPU(cpu); 4384 uint32_t dispatch; 4385 4386 dispatch = ldl_be_phys(cs->as, 4387 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4388 dispatch++; 4389 if ((dispatch & 1) != 1) { 4390 qemu_log_mask(LOG_GUEST_ERROR, 4391 "VPA: incorrect dispatch counter value for " 4392 "preempted partition %u, correcting.\n", dispatch); 4393 dispatch++; 4394 } 4395 stl_be_phys(cs->as, 4396 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4397 } 4398 } 4399 4400 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4401 { 4402 MachineClass *mc = MACHINE_CLASS(oc); 4403 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4404 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4405 NMIClass *nc = NMI_CLASS(oc); 4406 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4407 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4408 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4409 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4410 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4411 4412 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4413 mc->ignore_boot_device_suffixes = true; 4414 4415 /* 4416 * We set up the default / latest behaviour here. The class_init 4417 * functions for the specific versioned machine types can override 4418 * these details for backwards compatibility 4419 */ 4420 mc->init = spapr_machine_init; 4421 mc->reset = spapr_machine_reset; 4422 mc->block_default_type = IF_SCSI; 4423 mc->max_cpus = 1024; 4424 mc->no_parallel = 1; 4425 mc->default_boot_order = ""; 4426 mc->default_ram_size = 512 * MiB; 4427 mc->default_ram_id = "ppc_spapr.ram"; 4428 mc->default_display = "std"; 4429 mc->kvm_type = spapr_kvm_type; 4430 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4431 mc->pci_allow_0_address = true; 4432 assert(!mc->get_hotplug_handler); 4433 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4434 hc->pre_plug = spapr_machine_device_pre_plug; 4435 hc->plug = spapr_machine_device_plug; 4436 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4437 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4438 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4439 hc->unplug_request = spapr_machine_device_unplug_request; 4440 hc->unplug = spapr_machine_device_unplug; 4441 4442 smc->dr_lmb_enabled = true; 4443 smc->update_dt_enabled = true; 4444 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4445 mc->has_hotpluggable_cpus = true; 4446 mc->nvdimm_supported = true; 4447 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4448 fwc->get_dev_path = spapr_get_fw_dev_path; 4449 nc->nmi_monitor_handler = spapr_nmi; 4450 smc->phb_placement = spapr_phb_placement; 4451 vhc->hypercall = emulate_spapr_hypercall; 4452 vhc->hpt_mask = spapr_hpt_mask; 4453 vhc->map_hptes = spapr_map_hptes; 4454 vhc->unmap_hptes = spapr_unmap_hptes; 4455 vhc->hpte_set_c = spapr_hpte_set_c; 4456 vhc->hpte_set_r = spapr_hpte_set_r; 4457 vhc->get_pate = spapr_get_pate; 4458 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4459 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4460 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4461 xic->ics_get = spapr_ics_get; 4462 xic->ics_resend = spapr_ics_resend; 4463 xic->icp_get = spapr_icp_get; 4464 ispc->print_info = spapr_pic_print_info; 4465 /* Force NUMA node memory size to be a multiple of 4466 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4467 * in which LMBs are represented and hot-added 4468 */ 4469 mc->numa_mem_align_shift = 28; 4470 mc->auto_enable_numa = true; 4471 4472 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4473 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4474 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4475 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4476 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4477 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4478 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4479 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4480 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4481 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4482 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4483 spapr_caps_add_properties(smc); 4484 smc->irq = &spapr_irq_dual; 4485 smc->dr_phb_enabled = true; 4486 smc->linux_pci_probe = true; 4487 smc->smp_threads_vsmt = true; 4488 smc->nr_xirqs = SPAPR_NR_XIRQS; 4489 xfc->match_nvt = spapr_match_nvt; 4490 } 4491 4492 static const TypeInfo spapr_machine_info = { 4493 .name = TYPE_SPAPR_MACHINE, 4494 .parent = TYPE_MACHINE, 4495 .abstract = true, 4496 .instance_size = sizeof(SpaprMachineState), 4497 .instance_init = spapr_instance_init, 4498 .instance_finalize = spapr_machine_finalizefn, 4499 .class_size = sizeof(SpaprMachineClass), 4500 .class_init = spapr_machine_class_init, 4501 .interfaces = (InterfaceInfo[]) { 4502 { TYPE_FW_PATH_PROVIDER }, 4503 { TYPE_NMI }, 4504 { TYPE_HOTPLUG_HANDLER }, 4505 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4506 { TYPE_XICS_FABRIC }, 4507 { TYPE_INTERRUPT_STATS_PROVIDER }, 4508 { TYPE_XIVE_FABRIC }, 4509 { } 4510 }, 4511 }; 4512 4513 static void spapr_machine_latest_class_options(MachineClass *mc) 4514 { 4515 mc->alias = "pseries"; 4516 mc->is_default = true; 4517 } 4518 4519 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4520 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4521 void *data) \ 4522 { \ 4523 MachineClass *mc = MACHINE_CLASS(oc); \ 4524 spapr_machine_##suffix##_class_options(mc); \ 4525 if (latest) { \ 4526 spapr_machine_latest_class_options(mc); \ 4527 } \ 4528 } \ 4529 static const TypeInfo spapr_machine_##suffix##_info = { \ 4530 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4531 .parent = TYPE_SPAPR_MACHINE, \ 4532 .class_init = spapr_machine_##suffix##_class_init, \ 4533 }; \ 4534 static void spapr_machine_register_##suffix(void) \ 4535 { \ 4536 type_register(&spapr_machine_##suffix##_info); \ 4537 } \ 4538 type_init(spapr_machine_register_##suffix) 4539 4540 /* 4541 * pseries-6.0 4542 */ 4543 static void spapr_machine_6_0_class_options(MachineClass *mc) 4544 { 4545 /* Defaults for the latest behaviour inherited from the base class */ 4546 } 4547 4548 DEFINE_SPAPR_MACHINE(6_0, "6.0", true); 4549 4550 /* 4551 * pseries-5.2 4552 */ 4553 static void spapr_machine_5_2_class_options(MachineClass *mc) 4554 { 4555 spapr_machine_6_0_class_options(mc); 4556 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4557 } 4558 4559 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4560 4561 /* 4562 * pseries-5.1 4563 */ 4564 static void spapr_machine_5_1_class_options(MachineClass *mc) 4565 { 4566 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4567 4568 spapr_machine_5_2_class_options(mc); 4569 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4570 smc->pre_5_2_numa_associativity = true; 4571 } 4572 4573 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4574 4575 /* 4576 * pseries-5.0 4577 */ 4578 static void spapr_machine_5_0_class_options(MachineClass *mc) 4579 { 4580 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4581 static GlobalProperty compat[] = { 4582 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4583 }; 4584 4585 spapr_machine_5_1_class_options(mc); 4586 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4587 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4588 mc->numa_mem_supported = true; 4589 smc->pre_5_1_assoc_refpoints = true; 4590 } 4591 4592 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4593 4594 /* 4595 * pseries-4.2 4596 */ 4597 static void spapr_machine_4_2_class_options(MachineClass *mc) 4598 { 4599 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4600 4601 spapr_machine_5_0_class_options(mc); 4602 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4603 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4604 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4605 smc->rma_limit = 16 * GiB; 4606 mc->nvdimm_supported = false; 4607 } 4608 4609 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4610 4611 /* 4612 * pseries-4.1 4613 */ 4614 static void spapr_machine_4_1_class_options(MachineClass *mc) 4615 { 4616 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4617 static GlobalProperty compat[] = { 4618 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4619 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4620 }; 4621 4622 spapr_machine_4_2_class_options(mc); 4623 smc->linux_pci_probe = false; 4624 smc->smp_threads_vsmt = false; 4625 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4626 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4627 } 4628 4629 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4630 4631 /* 4632 * pseries-4.0 4633 */ 4634 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4635 uint64_t *buid, hwaddr *pio, 4636 hwaddr *mmio32, hwaddr *mmio64, 4637 unsigned n_dma, uint32_t *liobns, 4638 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4639 { 4640 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4641 liobns, nv2gpa, nv2atsd, errp)) { 4642 return false; 4643 } 4644 4645 *nv2gpa = 0; 4646 *nv2atsd = 0; 4647 return true; 4648 } 4649 static void spapr_machine_4_0_class_options(MachineClass *mc) 4650 { 4651 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4652 4653 spapr_machine_4_1_class_options(mc); 4654 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4655 smc->phb_placement = phb_placement_4_0; 4656 smc->irq = &spapr_irq_xics; 4657 smc->pre_4_1_migration = true; 4658 } 4659 4660 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4661 4662 /* 4663 * pseries-3.1 4664 */ 4665 static void spapr_machine_3_1_class_options(MachineClass *mc) 4666 { 4667 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4668 4669 spapr_machine_4_0_class_options(mc); 4670 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4671 4672 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4673 smc->update_dt_enabled = false; 4674 smc->dr_phb_enabled = false; 4675 smc->broken_host_serial_model = true; 4676 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4677 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4678 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4679 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4680 } 4681 4682 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4683 4684 /* 4685 * pseries-3.0 4686 */ 4687 4688 static void spapr_machine_3_0_class_options(MachineClass *mc) 4689 { 4690 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4691 4692 spapr_machine_3_1_class_options(mc); 4693 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4694 4695 smc->legacy_irq_allocation = true; 4696 smc->nr_xirqs = 0x400; 4697 smc->irq = &spapr_irq_xics_legacy; 4698 } 4699 4700 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4701 4702 /* 4703 * pseries-2.12 4704 */ 4705 static void spapr_machine_2_12_class_options(MachineClass *mc) 4706 { 4707 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4708 static GlobalProperty compat[] = { 4709 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4710 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4711 }; 4712 4713 spapr_machine_3_0_class_options(mc); 4714 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4715 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4716 4717 /* We depend on kvm_enabled() to choose a default value for the 4718 * hpt-max-page-size capability. Of course we can't do it here 4719 * because this is too early and the HW accelerator isn't initialzed 4720 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4721 */ 4722 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4723 } 4724 4725 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4726 4727 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4728 { 4729 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4730 4731 spapr_machine_2_12_class_options(mc); 4732 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4733 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4734 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4735 } 4736 4737 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4738 4739 /* 4740 * pseries-2.11 4741 */ 4742 4743 static void spapr_machine_2_11_class_options(MachineClass *mc) 4744 { 4745 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4746 4747 spapr_machine_2_12_class_options(mc); 4748 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4749 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4750 } 4751 4752 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4753 4754 /* 4755 * pseries-2.10 4756 */ 4757 4758 static void spapr_machine_2_10_class_options(MachineClass *mc) 4759 { 4760 spapr_machine_2_11_class_options(mc); 4761 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4762 } 4763 4764 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4765 4766 /* 4767 * pseries-2.9 4768 */ 4769 4770 static void spapr_machine_2_9_class_options(MachineClass *mc) 4771 { 4772 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4773 static GlobalProperty compat[] = { 4774 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4775 }; 4776 4777 spapr_machine_2_10_class_options(mc); 4778 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4779 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4780 smc->pre_2_10_has_unused_icps = true; 4781 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4782 } 4783 4784 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4785 4786 /* 4787 * pseries-2.8 4788 */ 4789 4790 static void spapr_machine_2_8_class_options(MachineClass *mc) 4791 { 4792 static GlobalProperty compat[] = { 4793 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4794 }; 4795 4796 spapr_machine_2_9_class_options(mc); 4797 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4798 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4799 mc->numa_mem_align_shift = 23; 4800 } 4801 4802 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4803 4804 /* 4805 * pseries-2.7 4806 */ 4807 4808 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4809 uint64_t *buid, hwaddr *pio, 4810 hwaddr *mmio32, hwaddr *mmio64, 4811 unsigned n_dma, uint32_t *liobns, 4812 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4813 { 4814 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4815 const uint64_t base_buid = 0x800000020000000ULL; 4816 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4817 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4818 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4819 const uint32_t max_index = 255; 4820 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4821 4822 uint64_t ram_top = MACHINE(spapr)->ram_size; 4823 hwaddr phb0_base, phb_base; 4824 int i; 4825 4826 /* Do we have device memory? */ 4827 if (MACHINE(spapr)->maxram_size > ram_top) { 4828 /* Can't just use maxram_size, because there may be an 4829 * alignment gap between normal and device memory regions 4830 */ 4831 ram_top = MACHINE(spapr)->device_memory->base + 4832 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4833 } 4834 4835 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4836 4837 if (index > max_index) { 4838 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4839 max_index); 4840 return false; 4841 } 4842 4843 *buid = base_buid + index; 4844 for (i = 0; i < n_dma; ++i) { 4845 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4846 } 4847 4848 phb_base = phb0_base + index * phb_spacing; 4849 *pio = phb_base + pio_offset; 4850 *mmio32 = phb_base + mmio_offset; 4851 /* 4852 * We don't set the 64-bit MMIO window, relying on the PHB's 4853 * fallback behaviour of automatically splitting a large "32-bit" 4854 * window into contiguous 32-bit and 64-bit windows 4855 */ 4856 4857 *nv2gpa = 0; 4858 *nv2atsd = 0; 4859 return true; 4860 } 4861 4862 static void spapr_machine_2_7_class_options(MachineClass *mc) 4863 { 4864 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4865 static GlobalProperty compat[] = { 4866 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4867 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4868 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4869 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4870 }; 4871 4872 spapr_machine_2_8_class_options(mc); 4873 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4874 mc->default_machine_opts = "modern-hotplug-events=off"; 4875 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4876 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4877 smc->phb_placement = phb_placement_2_7; 4878 } 4879 4880 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4881 4882 /* 4883 * pseries-2.6 4884 */ 4885 4886 static void spapr_machine_2_6_class_options(MachineClass *mc) 4887 { 4888 static GlobalProperty compat[] = { 4889 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4890 }; 4891 4892 spapr_machine_2_7_class_options(mc); 4893 mc->has_hotpluggable_cpus = false; 4894 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4895 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4896 } 4897 4898 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4899 4900 /* 4901 * pseries-2.5 4902 */ 4903 4904 static void spapr_machine_2_5_class_options(MachineClass *mc) 4905 { 4906 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4907 static GlobalProperty compat[] = { 4908 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4909 }; 4910 4911 spapr_machine_2_6_class_options(mc); 4912 smc->use_ohci_by_default = true; 4913 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4914 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4915 } 4916 4917 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4918 4919 /* 4920 * pseries-2.4 4921 */ 4922 4923 static void spapr_machine_2_4_class_options(MachineClass *mc) 4924 { 4925 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4926 4927 spapr_machine_2_5_class_options(mc); 4928 smc->dr_lmb_enabled = false; 4929 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4930 } 4931 4932 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4933 4934 /* 4935 * pseries-2.3 4936 */ 4937 4938 static void spapr_machine_2_3_class_options(MachineClass *mc) 4939 { 4940 static GlobalProperty compat[] = { 4941 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4942 }; 4943 spapr_machine_2_4_class_options(mc); 4944 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4945 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4946 } 4947 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4948 4949 /* 4950 * pseries-2.2 4951 */ 4952 4953 static void spapr_machine_2_2_class_options(MachineClass *mc) 4954 { 4955 static GlobalProperty compat[] = { 4956 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4957 }; 4958 4959 spapr_machine_2_3_class_options(mc); 4960 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4961 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4962 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4963 } 4964 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4965 4966 /* 4967 * pseries-2.1 4968 */ 4969 4970 static void spapr_machine_2_1_class_options(MachineClass *mc) 4971 { 4972 spapr_machine_2_2_class_options(mc); 4973 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4974 } 4975 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4976 4977 static void spapr_machine_register_types(void) 4978 { 4979 type_register_static(&spapr_machine_info); 4980 } 4981 4982 type_init(spapr_machine_register_types) 4983