1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "system/system.h" 36 #include "system/hostmem.h" 37 #include "system/numa.h" 38 #include "system/tcg.h" 39 #include "system/qtest.h" 40 #include "system/reset.h" 41 #include "system/runstate.h" 42 #include "qemu/log.h" 43 #include "hw/fw-path-provider.h" 44 #include "elf.h" 45 #include "net/net.h" 46 #include "system/device_tree.h" 47 #include "system/cpus.h" 48 #include "system/hw_accel.h" 49 #include "kvm_ppc.h" 50 #include "migration/misc.h" 51 #include "migration/qemu-file-types.h" 52 #include "migration/global_state.h" 53 #include "migration/register.h" 54 #include "migration/blocker.h" 55 #include "mmu-hash64.h" 56 #include "mmu-book3s-v3.h" 57 #include "cpu-models.h" 58 #include "hw/core/cpu.h" 59 60 #include "hw/ppc/ppc.h" 61 #include "hw/loader.h" 62 63 #include "hw/ppc/fdt.h" 64 #include "hw/ppc/spapr.h" 65 #include "hw/ppc/spapr_nested.h" 66 #include "hw/ppc/spapr_vio.h" 67 #include "hw/ppc/vof.h" 68 #include "hw/qdev-properties.h" 69 #include "hw/pci-host/spapr.h" 70 #include "hw/pci/msi.h" 71 72 #include "hw/pci/pci.h" 73 #include "hw/scsi/scsi.h" 74 #include "hw/virtio/virtio-scsi.h" 75 #include "hw/virtio/vhost-scsi-common.h" 76 77 #include "exec/ram_addr.h" 78 #include "system/confidential-guest-support.h" 79 #include "hw/usb.h" 80 #include "qemu/config-file.h" 81 #include "qemu/error-report.h" 82 #include "trace.h" 83 #include "hw/nmi.h" 84 #include "hw/intc/intc.h" 85 86 #include "hw/ppc/spapr_cpu_core.h" 87 #include "hw/mem/memory-device.h" 88 #include "hw/ppc/spapr_tpm_proxy.h" 89 #include "hw/ppc/spapr_nvdimm.h" 90 #include "hw/ppc/spapr_numa.h" 91 92 #include <libfdt.h> 93 94 /* SLOF memory layout: 95 * 96 * SLOF raw image loaded at 0, copies its romfs right below the flat 97 * device-tree, then position SLOF itself 31M below that 98 * 99 * So we set FW_OVERHEAD to 40MB which should account for all of that 100 * and more 101 * 102 * We load our kernel at 4M, leaving space for SLOF initial image 103 */ 104 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 105 #define FW_MAX_SIZE 0x400000 106 #define FW_FILE_NAME "slof.bin" 107 #define FW_FILE_NAME_VOF "vof.bin" 108 #define FW_OVERHEAD 0x2800000 109 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 110 111 #define MIN_RMA_SLOF (128 * MiB) 112 113 #define PHANDLE_INTC 0x00001111 114 115 /* These two functions implement the VCPU id numbering: one to compute them 116 * all and one to identify thread 0 of a VCORE. Any change to the first one 117 * is likely to have an impact on the second one, so let's keep them close. 118 */ 119 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 120 { 121 MachineState *ms = MACHINE(spapr); 122 unsigned int smp_threads = ms->smp.threads; 123 124 assert(spapr->vsmt); 125 return 126 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 127 } 128 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 129 PowerPCCPU *cpu) 130 { 131 assert(spapr->vsmt); 132 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 133 } 134 135 int spapr_max_server_number(SpaprMachineState *spapr) 136 { 137 MachineState *ms = MACHINE(spapr); 138 139 assert(spapr->vsmt); 140 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 141 } 142 143 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 144 int smt_threads) 145 { 146 int i, ret = 0; 147 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 148 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 149 int index = spapr_get_vcpu_id(cpu); 150 151 if (cpu->compat_pvr) { 152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 153 if (ret < 0) { 154 return ret; 155 } 156 } 157 158 /* Build interrupt servers and gservers properties */ 159 for (i = 0; i < smt_threads; i++) { 160 servers_prop[i] = cpu_to_be32(index + i); 161 /* Hack, direct the group queues back to cpu 0 */ 162 gservers_prop[i*2] = cpu_to_be32(index + i); 163 gservers_prop[i*2 + 1] = 0; 164 } 165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 166 servers_prop, sizeof(*servers_prop) * smt_threads); 167 if (ret < 0) { 168 return ret; 169 } 170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 171 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 172 173 return ret; 174 } 175 176 static void spapr_dt_pa_features(SpaprMachineState *spapr, 177 PowerPCCPU *cpu, 178 void *fdt, int offset) 179 { 180 /* 181 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 182 * but not MTTCG, so disable it. To advertise it, a cap would have 183 * to be added, or support implemented for MTTCG. 184 * 185 * Copy/paste is not supported by TCG, so it is not advertised. KVM 186 * can execute them but it has no accelerator drivers which are usable, 187 * so there isn't much need for it anyway. 188 */ 189 190 /* These should be kept in sync with pnv */ 191 uint8_t pa_features_206[] = { 6, 0, 192 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 193 uint8_t pa_features_207[] = { 24, 0, 194 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 195 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 196 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 197 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 198 uint8_t pa_features_300[] = { 66, 0, 199 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 200 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 201 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 202 /* 6: DS207 */ 203 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 204 /* 16: Vector */ 205 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 206 /* 18: Vec. Scalar, 20: Vec. XOR */ 207 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 208 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 209 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 210 /* 32: LE atomic, 34: EBB + ext EBB */ 211 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 212 /* 40: Radix MMU */ 213 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 214 /* 42: PM, 44: PC RA, 46: SC vec'd */ 215 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 216 /* 48: SIMD, 50: QP BFP, 52: String */ 217 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 218 /* 54: DecFP, 56: DecI, 58: SHA */ 219 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 220 /* 60: NM atomic, 62: RNG */ 221 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 222 }; 223 /* 3.1 removes SAO, HTM support */ 224 uint8_t pa_features_31[] = { 74, 0, 225 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 226 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 227 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 228 /* 6: DS207 */ 229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 230 /* 16: Vector */ 231 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 232 /* 18: Vec. Scalar, 20: Vec. XOR */ 233 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 234 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 236 /* 32: LE atomic, 34: EBB + ext EBB */ 237 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 238 /* 40: Radix MMU */ 239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 240 /* 42: PM, 44: PC RA, 46: SC vec'd */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 242 /* 48: SIMD, 50: QP BFP, 52: String */ 243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 244 /* 54: DecFP, 56: DecI, 58: SHA */ 245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 246 /* 60: NM atomic, 62: RNG */ 247 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 248 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 249 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 250 /* 72: [P]HASHST/[P]HASHCHK */ 251 0x80, 0x00, /* 72 - 73 */ 252 }; 253 uint8_t *pa_features = NULL; 254 size_t pa_size; 255 256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 257 pa_features = pa_features_206; 258 pa_size = sizeof(pa_features_206); 259 } 260 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 261 pa_features = pa_features_207; 262 pa_size = sizeof(pa_features_207); 263 } 264 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 265 pa_features = pa_features_300; 266 pa_size = sizeof(pa_features_300); 267 } 268 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) { 269 pa_features = pa_features_31; 270 pa_size = sizeof(pa_features_31); 271 } 272 if (!pa_features) { 273 return; 274 } 275 276 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 277 /* 278 * Note: we keep CI large pages off by default because a 64K capable 279 * guest provisioned with large pages might otherwise try to map a qemu 280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 281 * even if that qemu runs on a 4k host. 282 * We dd this bit back here if we are confident this is not an issue 283 */ 284 pa_features[3] |= 0x20; 285 } 286 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 287 pa_features[24] |= 0x80; /* Transactional memory support */ 288 } 289 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 290 /* Workaround for broken kernels that attempt (guest) radix 291 * mode when they can't handle it, if they see the radix bit set 292 * in pa-features. So hide it from them. */ 293 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 294 } 295 296 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 297 } 298 299 static void spapr_dt_pi_features(SpaprMachineState *spapr, 300 PowerPCCPU *cpu, 301 void *fdt, int offset) 302 { 303 uint8_t pi_features[] = { 1, 0, 304 0x00 }; 305 306 if (kvm_enabled() && ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 307 0, cpu->compat_pvr)) { 308 /* 309 * POWER9 and later CPUs with KVM run in LPAR-per-thread mode where 310 * all threads are essentially independent CPUs, and msgsndp does not 311 * work (because it is physically-addressed) and therefore is 312 * emulated by KVM, so disable it here to ensure XIVE will be used. 313 * This is both KVM and CPU implementation-specific behaviour so a KVM 314 * cap would be cleanest, but for now this works. If KVM ever permits 315 * native msgsndp execution by guests, a cap could be added at that 316 * time. 317 */ 318 pi_features[2] |= 0x08; /* 4: No msgsndp */ 319 } 320 321 _FDT((fdt_setprop(fdt, offset, "ibm,pi-features", pi_features, 322 sizeof(pi_features)))); 323 } 324 325 static hwaddr spapr_node0_size(MachineState *machine) 326 { 327 if (machine->numa_state->num_nodes) { 328 int i; 329 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 330 if (machine->numa_state->nodes[i].node_mem) { 331 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 332 machine->ram_size); 333 } 334 } 335 } 336 return machine->ram_size; 337 } 338 339 static void add_str(GString *s, const gchar *s1) 340 { 341 g_string_append_len(s, s1, strlen(s1) + 1); 342 } 343 344 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 345 hwaddr start, hwaddr size) 346 { 347 char mem_name[32]; 348 uint64_t mem_reg_property[2]; 349 int off; 350 351 mem_reg_property[0] = cpu_to_be64(start); 352 mem_reg_property[1] = cpu_to_be64(size); 353 354 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 355 off = fdt_add_subnode(fdt, 0, mem_name); 356 _FDT(off); 357 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 358 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 359 sizeof(mem_reg_property)))); 360 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 361 return off; 362 } 363 364 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 365 { 366 MemoryDeviceInfoList *info; 367 368 for (info = list; info; info = info->next) { 369 MemoryDeviceInfo *value = info->value; 370 371 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 372 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 373 374 if (addr >= pcdimm_info->addr && 375 addr < (pcdimm_info->addr + pcdimm_info->size)) { 376 return pcdimm_info->node; 377 } 378 } 379 } 380 381 return -1; 382 } 383 384 struct sPAPRDrconfCellV2 { 385 uint32_t seq_lmbs; 386 uint64_t base_addr; 387 uint32_t drc_index; 388 uint32_t aa_index; 389 uint32_t flags; 390 } QEMU_PACKED; 391 392 typedef struct DrconfCellQueue { 393 struct sPAPRDrconfCellV2 cell; 394 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 395 } DrconfCellQueue; 396 397 static DrconfCellQueue * 398 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 399 uint32_t drc_index, uint32_t aa_index, 400 uint32_t flags) 401 { 402 DrconfCellQueue *elem; 403 404 elem = g_malloc0(sizeof(*elem)); 405 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 406 elem->cell.base_addr = cpu_to_be64(base_addr); 407 elem->cell.drc_index = cpu_to_be32(drc_index); 408 elem->cell.aa_index = cpu_to_be32(aa_index); 409 elem->cell.flags = cpu_to_be32(flags); 410 411 return elem; 412 } 413 414 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 415 int offset, MemoryDeviceInfoList *dimms) 416 { 417 MachineState *machine = MACHINE(spapr); 418 uint8_t *int_buf, *cur_index; 419 int ret; 420 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 421 uint64_t addr, cur_addr, size; 422 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 423 uint64_t mem_end = machine->device_memory->base + 424 memory_region_size(&machine->device_memory->mr); 425 uint32_t node, buf_len, nr_entries = 0; 426 SpaprDrc *drc; 427 DrconfCellQueue *elem, *next; 428 MemoryDeviceInfoList *info; 429 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 430 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 431 432 /* Entry to cover RAM and the gap area */ 433 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 434 SPAPR_LMB_FLAGS_RESERVED | 435 SPAPR_LMB_FLAGS_DRC_INVALID); 436 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 437 nr_entries++; 438 439 cur_addr = machine->device_memory->base; 440 for (info = dimms; info; info = info->next) { 441 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 442 443 addr = di->addr; 444 size = di->size; 445 node = di->node; 446 447 /* 448 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 449 * area is marked hotpluggable in the next iteration for the bigger 450 * chunk including the NVDIMM occupied area. 451 */ 452 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 453 continue; 454 455 /* Entry for hot-pluggable area */ 456 if (cur_addr < addr) { 457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 458 g_assert(drc); 459 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 460 cur_addr, spapr_drc_index(drc), -1, 0); 461 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 462 nr_entries++; 463 } 464 465 /* Entry for DIMM */ 466 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 467 g_assert(drc); 468 elem = spapr_get_drconf_cell(size / lmb_size, addr, 469 spapr_drc_index(drc), node, 470 (SPAPR_LMB_FLAGS_ASSIGNED | 471 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 472 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 473 nr_entries++; 474 cur_addr = addr + size; 475 } 476 477 /* Entry for remaining hotpluggable area */ 478 if (cur_addr < mem_end) { 479 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 480 g_assert(drc); 481 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 482 cur_addr, spapr_drc_index(drc), -1, 0); 483 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 484 nr_entries++; 485 } 486 487 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 488 int_buf = cur_index = g_malloc0(buf_len); 489 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 490 cur_index += sizeof(nr_entries); 491 492 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 493 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 494 cur_index += sizeof(elem->cell); 495 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 496 g_free(elem); 497 } 498 499 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 500 g_free(int_buf); 501 if (ret < 0) { 502 return -1; 503 } 504 return 0; 505 } 506 507 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 508 int offset, MemoryDeviceInfoList *dimms) 509 { 510 MachineState *machine = MACHINE(spapr); 511 int i, ret; 512 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 513 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 514 uint32_t nr_lmbs = (machine->device_memory->base + 515 memory_region_size(&machine->device_memory->mr)) / 516 lmb_size; 517 uint32_t *int_buf, *cur_index, buf_len; 518 519 /* 520 * Allocate enough buffer size to fit in ibm,dynamic-memory 521 */ 522 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 523 cur_index = int_buf = g_malloc0(buf_len); 524 int_buf[0] = cpu_to_be32(nr_lmbs); 525 cur_index++; 526 for (i = 0; i < nr_lmbs; i++) { 527 uint64_t addr = i * lmb_size; 528 uint32_t *dynamic_memory = cur_index; 529 530 if (i >= device_lmb_start) { 531 SpaprDrc *drc; 532 533 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 534 g_assert(drc); 535 536 dynamic_memory[0] = cpu_to_be32(addr >> 32); 537 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 538 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 539 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 540 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 541 if (memory_region_present(get_system_memory(), addr)) { 542 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 543 } else { 544 dynamic_memory[5] = cpu_to_be32(0); 545 } 546 } else { 547 /* 548 * LMB information for RMA, boot time RAM and gap b/n RAM and 549 * device memory region -- all these are marked as reserved 550 * and as having no valid DRC. 551 */ 552 dynamic_memory[0] = cpu_to_be32(addr >> 32); 553 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 554 dynamic_memory[2] = cpu_to_be32(0); 555 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 556 dynamic_memory[4] = cpu_to_be32(-1); 557 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 558 SPAPR_LMB_FLAGS_DRC_INVALID); 559 } 560 561 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 562 } 563 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 564 g_free(int_buf); 565 if (ret < 0) { 566 return -1; 567 } 568 return 0; 569 } 570 571 /* 572 * Adds ibm,dynamic-reconfiguration-memory node. 573 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 574 * of this device tree node. 575 */ 576 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 577 void *fdt) 578 { 579 MachineState *machine = MACHINE(spapr); 580 int ret, offset; 581 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 582 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 583 cpu_to_be32(lmb_size & 0xffffffff)}; 584 MemoryDeviceInfoList *dimms = NULL; 585 586 /* Don't create the node if there is no device memory. */ 587 if (!machine->device_memory) { 588 return 0; 589 } 590 591 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 592 593 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 594 sizeof(prop_lmb_size)); 595 if (ret < 0) { 596 return ret; 597 } 598 599 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 600 if (ret < 0) { 601 return ret; 602 } 603 604 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 605 if (ret < 0) { 606 return ret; 607 } 608 609 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 610 dimms = qmp_memory_device_list(); 611 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 612 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 613 } else { 614 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 615 } 616 qapi_free_MemoryDeviceInfoList(dimms); 617 618 if (ret < 0) { 619 return ret; 620 } 621 622 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 623 624 return ret; 625 } 626 627 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 628 { 629 MachineState *machine = MACHINE(spapr); 630 hwaddr mem_start, node_size; 631 int i, nb_nodes = machine->numa_state->num_nodes; 632 NodeInfo *nodes = machine->numa_state->nodes; 633 634 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 635 if (!nodes[i].node_mem) { 636 continue; 637 } 638 if (mem_start >= machine->ram_size) { 639 node_size = 0; 640 } else { 641 node_size = nodes[i].node_mem; 642 if (node_size > machine->ram_size - mem_start) { 643 node_size = machine->ram_size - mem_start; 644 } 645 } 646 if (!mem_start) { 647 /* spapr_machine_init() checks for rma_size <= node0_size 648 * already */ 649 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 650 mem_start += spapr->rma_size; 651 node_size -= spapr->rma_size; 652 } 653 for ( ; node_size; ) { 654 hwaddr sizetmp = pow2floor(node_size); 655 656 /* mem_start != 0 here */ 657 if (ctzl(mem_start) < ctzl(sizetmp)) { 658 sizetmp = 1ULL << ctzl(mem_start); 659 } 660 661 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 662 node_size -= sizetmp; 663 mem_start += sizetmp; 664 } 665 } 666 667 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 668 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 669 int ret; 670 671 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 672 if (ret) { 673 return ret; 674 } 675 } 676 677 return 0; 678 } 679 680 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 681 SpaprMachineState *spapr) 682 { 683 MachineState *ms = MACHINE(spapr); 684 PowerPCCPU *cpu = POWERPC_CPU(cs); 685 CPUPPCState *env = &cpu->env; 686 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 687 int index = spapr_get_vcpu_id(cpu); 688 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 689 0xffffffff, 0xffffffff}; 690 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 691 : SPAPR_TIMEBASE_FREQ; 692 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 693 uint32_t page_sizes_prop[64]; 694 size_t page_sizes_prop_size; 695 unsigned int smp_threads = ms->smp.threads; 696 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 697 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 698 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 699 SpaprDrc *drc; 700 int drc_index; 701 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 702 int i; 703 704 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, env->core_index); 705 if (drc) { 706 drc_index = spapr_drc_index(drc); 707 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 708 } 709 710 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 711 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 712 713 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 714 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 715 env->dcache_line_size))); 716 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 717 env->dcache_line_size))); 718 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 719 env->icache_line_size))); 720 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 721 env->icache_line_size))); 722 723 if (pcc->l1_dcache_size) { 724 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 725 pcc->l1_dcache_size))); 726 } else { 727 warn_report("Unknown L1 dcache size for cpu"); 728 } 729 if (pcc->l1_icache_size) { 730 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 731 pcc->l1_icache_size))); 732 } else { 733 warn_report("Unknown L1 icache size for cpu"); 734 } 735 736 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 737 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 738 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 739 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 740 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 741 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 742 743 if (ppc_has_spr(cpu, SPR_PURR)) { 744 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 745 } 746 if (ppc_has_spr(cpu, SPR_PURR)) { 747 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 748 } 749 750 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 751 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 752 segs, sizeof(segs)))); 753 } 754 755 /* Advertise VSX (vector extensions) if available 756 * 1 == VMX / Altivec available 757 * 2 == VSX available 758 * 759 * Only CPUs for which we create core types in spapr_cpu_core.c 760 * are possible, and all of those have VMX */ 761 if (env->insns_flags & PPC_ALTIVEC) { 762 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 763 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 764 } else { 765 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 766 } 767 } 768 769 /* Advertise DFP (Decimal Floating Point) if available 770 * 0 / no property == no DFP 771 * 1 == DFP available */ 772 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 773 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 774 } 775 776 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 777 sizeof(page_sizes_prop)); 778 if (page_sizes_prop_size) { 779 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 780 page_sizes_prop, page_sizes_prop_size))); 781 } 782 783 spapr_dt_pa_features(spapr, cpu, fdt, offset); 784 785 spapr_dt_pi_features(spapr, cpu, fdt, offset); 786 787 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 788 cs->cpu_index / vcpus_per_socket))); 789 790 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 791 pft_size_prop, sizeof(pft_size_prop)))); 792 793 if (ms->numa_state->num_nodes > 1) { 794 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 795 } 796 797 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 798 799 if (pcc->radix_page_info) { 800 for (i = 0; i < pcc->radix_page_info->count; i++) { 801 radix_AP_encodings[i] = 802 cpu_to_be32(pcc->radix_page_info->entries[i]); 803 } 804 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 805 radix_AP_encodings, 806 pcc->radix_page_info->count * 807 sizeof(radix_AP_encodings[0])))); 808 } 809 810 /* 811 * We set this property to let the guest know that it can use the large 812 * decrementer and its width in bits. 813 */ 814 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 815 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 816 pcc->lrg_decr_bits))); 817 } 818 819 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 820 int cpus_offset) 821 { 822 PowerPCCPU *cpu = POWERPC_CPU(cs); 823 int index = spapr_get_vcpu_id(cpu); 824 DeviceClass *dc = DEVICE_GET_CLASS(cs); 825 g_autofree char *nodename = NULL; 826 int offset; 827 828 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 829 return; 830 } 831 832 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 833 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 834 _FDT(offset); 835 spapr_dt_cpu(cs, fdt, offset, spapr); 836 } 837 838 839 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 840 { 841 CPUState **rev; 842 CPUState *cs; 843 int n_cpus; 844 int cpus_offset; 845 int i; 846 847 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 848 _FDT(cpus_offset); 849 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 850 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 851 852 /* 853 * We walk the CPUs in reverse order to ensure that CPU DT nodes 854 * created by fdt_add_subnode() end up in the right order in FDT 855 * for the guest kernel the enumerate the CPUs correctly. 856 * 857 * The CPU list cannot be traversed in reverse order, so we need 858 * to do extra work. 859 */ 860 n_cpus = 0; 861 rev = NULL; 862 CPU_FOREACH(cs) { 863 rev = g_renew(CPUState *, rev, n_cpus + 1); 864 rev[n_cpus++] = cs; 865 } 866 867 for (i = n_cpus - 1; i >= 0; i--) { 868 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 869 } 870 871 g_free(rev); 872 } 873 874 static int spapr_dt_rng(void *fdt) 875 { 876 int node; 877 int ret; 878 879 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 880 if (node <= 0) { 881 return -1; 882 } 883 ret = fdt_setprop_string(fdt, node, "device_type", 884 "ibm,platform-facilities"); 885 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 886 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 887 888 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 889 if (node <= 0) { 890 return -1; 891 } 892 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 893 894 return ret ? -1 : 0; 895 } 896 897 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 898 { 899 MachineState *ms = MACHINE(spapr); 900 int rtas; 901 GString *hypertas = g_string_sized_new(256); 902 GString *qemu_hypertas = g_string_sized_new(256); 903 uint32_t lrdr_capacity[] = { 904 0, 905 0, 906 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 907 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 908 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 909 }; 910 911 /* Do we have device memory? */ 912 if (MACHINE(spapr)->device_memory) { 913 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 914 memory_region_size(&MACHINE(spapr)->device_memory->mr); 915 916 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 917 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 918 } 919 920 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 921 922 /* hypertas */ 923 add_str(hypertas, "hcall-pft"); 924 add_str(hypertas, "hcall-term"); 925 add_str(hypertas, "hcall-dabr"); 926 add_str(hypertas, "hcall-interrupt"); 927 add_str(hypertas, "hcall-tce"); 928 add_str(hypertas, "hcall-vio"); 929 add_str(hypertas, "hcall-splpar"); 930 add_str(hypertas, "hcall-join"); 931 add_str(hypertas, "hcall-bulk"); 932 add_str(hypertas, "hcall-set-mode"); 933 add_str(hypertas, "hcall-sprg0"); 934 add_str(hypertas, "hcall-copy"); 935 add_str(hypertas, "hcall-debug"); 936 add_str(hypertas, "hcall-vphn"); 937 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 938 add_str(hypertas, "hcall-rpt-invalidate"); 939 } 940 941 add_str(qemu_hypertas, "hcall-memop1"); 942 943 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 944 add_str(hypertas, "hcall-multi-tce"); 945 } 946 947 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 948 add_str(hypertas, "hcall-hpt-resize"); 949 } 950 951 add_str(hypertas, "hcall-watchdog"); 952 953 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 954 hypertas->str, hypertas->len)); 955 g_string_free(hypertas, TRUE); 956 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 957 qemu_hypertas->str, qemu_hypertas->len)); 958 g_string_free(qemu_hypertas, TRUE); 959 960 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 961 962 /* 963 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 964 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 965 * 966 * The system reset requirements are driven by existing Linux and PowerVM 967 * implementation which (contrary to PAPR) saves r3 in the error log 968 * structure like machine check, so Linux expects to find the saved r3 969 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 970 * does not look at the error value). 971 * 972 * System reset interrupts are not subject to interlock like machine 973 * check, so this memory area could be corrupted if the sreset is 974 * interrupted by a machine check (or vice versa) if it was shared. To 975 * prevent this, system reset uses per-CPU areas for the sreset save 976 * area. A system reset that interrupts a system reset handler could 977 * still overwrite this area, but Linux doesn't try to recover in that 978 * case anyway. 979 * 980 * The extra 8 bytes is required because Linux's FWNMI error log check 981 * is off-by-one. 982 * 983 * RTAS_MIN_SIZE is required for the RTAS blob itself. 984 */ 985 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 986 RTAS_ERROR_LOG_MAX + 987 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 988 sizeof(uint64_t))); 989 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 990 RTAS_ERROR_LOG_MAX)); 991 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 992 RTAS_EVENT_SCAN_RATE)); 993 994 g_assert(msi_nonbroken); 995 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 996 997 /* 998 * According to PAPR, rtas ibm,os-term does not guarantee a return 999 * back to the guest cpu. 1000 * 1001 * While an additional ibm,extended-os-term property indicates 1002 * that rtas call return will always occur. Set this property. 1003 */ 1004 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1005 1006 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1007 lrdr_capacity, sizeof(lrdr_capacity))); 1008 1009 spapr_dt_rtas_tokens(fdt, rtas); 1010 } 1011 1012 /* 1013 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1014 * and the XIVE features that the guest may request and thus the valid 1015 * values for bytes 23..26 of option vector 5: 1016 */ 1017 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1018 int chosen) 1019 { 1020 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1021 1022 char val[2 * 4] = { 1023 23, 0x00, /* XICS / XIVE mode */ 1024 24, 0x00, /* Hash/Radix, filled in below. */ 1025 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1026 26, 0x40, /* Radix options: GTSE == yes. */ 1027 }; 1028 1029 if (spapr->irq->xics && spapr->irq->xive) { 1030 val[1] = SPAPR_OV5_XIVE_BOTH; 1031 } else if (spapr->irq->xive) { 1032 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1033 } else { 1034 assert(spapr->irq->xics); 1035 val[1] = SPAPR_OV5_XIVE_LEGACY; 1036 } 1037 1038 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1039 first_ppc_cpu->compat_pvr)) { 1040 /* 1041 * If we're in a pre POWER9 compat mode then the guest should 1042 * do hash and use the legacy interrupt mode 1043 */ 1044 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1045 val[3] = 0x00; /* Hash */ 1046 spapr_check_mmu_mode(false); 1047 } else if (kvm_enabled()) { 1048 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1049 val[3] = 0x80; /* OV5_MMU_BOTH */ 1050 } else if (kvmppc_has_cap_mmu_radix()) { 1051 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1052 } else { 1053 val[3] = 0x00; /* Hash */ 1054 } 1055 } else { 1056 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1057 val[3] = 0xC0; 1058 } 1059 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1060 val, sizeof(val))); 1061 } 1062 1063 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1064 { 1065 MachineState *machine = MACHINE(spapr); 1066 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1067 int chosen; 1068 1069 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1070 1071 if (reset) { 1072 const char *boot_device = spapr->boot_device; 1073 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1074 size_t cb = 0; 1075 g_autofree char *bootlist = get_boot_devices_list(&cb); 1076 1077 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1078 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1079 machine->kernel_cmdline)); 1080 } 1081 1082 if (spapr->initrd_size) { 1083 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1084 spapr->initrd_base)); 1085 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1086 spapr->initrd_base + spapr->initrd_size)); 1087 } 1088 1089 if (spapr->kernel_size) { 1090 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1091 cpu_to_be64(spapr->kernel_size) }; 1092 1093 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1094 &kprop, sizeof(kprop))); 1095 if (spapr->kernel_le) { 1096 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1097 } 1098 } 1099 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1100 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1101 } 1102 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1103 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1104 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1105 1106 if (cb && bootlist) { 1107 int i; 1108 1109 for (i = 0; i < cb; i++) { 1110 if (bootlist[i] == '\n') { 1111 bootlist[i] = ' '; 1112 } 1113 } 1114 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1115 } 1116 1117 if (boot_device && strlen(boot_device)) { 1118 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1119 } 1120 1121 if (spapr->want_stdout_path && stdout_path) { 1122 /* 1123 * "linux,stdout-path" and "stdout" properties are 1124 * deprecated by linux kernel. New platforms should only 1125 * use the "stdout-path" property. Set the new property 1126 * and continue using older property to remain compatible 1127 * with the existing firmware. 1128 */ 1129 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1130 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1131 } 1132 1133 /* 1134 * We can deal with BAR reallocation just fine, advertise it 1135 * to the guest 1136 */ 1137 if (smc->linux_pci_probe) { 1138 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1139 } 1140 1141 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1142 } 1143 1144 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1145 1146 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1147 } 1148 1149 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1150 { 1151 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1152 * KVM to work under pHyp with some guest co-operation */ 1153 int hypervisor; 1154 uint8_t hypercall[16]; 1155 1156 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1157 /* indicate KVM hypercall interface */ 1158 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1159 if (kvmppc_has_cap_fixup_hcalls()) { 1160 /* 1161 * Older KVM versions with older guest kernels were broken 1162 * with the magic page, don't allow the guest to map it. 1163 */ 1164 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1165 sizeof(hypercall))) { 1166 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1167 hypercall, sizeof(hypercall))); 1168 } 1169 } 1170 } 1171 1172 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1173 { 1174 MachineState *machine = MACHINE(spapr); 1175 MachineClass *mc = MACHINE_GET_CLASS(machine); 1176 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1177 uint32_t root_drc_type_mask = 0; 1178 int ret; 1179 void *fdt; 1180 SpaprPhbState *phb; 1181 char *buf; 1182 1183 fdt = g_malloc0(space); 1184 _FDT((fdt_create_empty_tree(fdt, space))); 1185 1186 /* Root node */ 1187 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1188 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1189 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1190 1191 /* Guest UUID & Name*/ 1192 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1193 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1194 if (qemu_uuid_set) { 1195 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1196 } 1197 g_free(buf); 1198 1199 if (qemu_get_vm_name()) { 1200 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1201 qemu_get_vm_name())); 1202 } 1203 1204 /* Host Model & Serial Number */ 1205 if (spapr->host_model) { 1206 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1207 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1208 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1209 g_free(buf); 1210 } 1211 1212 if (spapr->host_serial) { 1213 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1214 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1215 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1216 g_free(buf); 1217 } 1218 1219 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1220 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1221 1222 /* /interrupt controller */ 1223 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1224 1225 ret = spapr_dt_memory(spapr, fdt); 1226 if (ret < 0) { 1227 error_report("couldn't setup memory nodes in fdt"); 1228 exit(1); 1229 } 1230 1231 /* /vdevice */ 1232 spapr_dt_vdevice(spapr->vio_bus, fdt); 1233 1234 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1235 ret = spapr_dt_rng(fdt); 1236 if (ret < 0) { 1237 error_report("could not set up rng device in the fdt"); 1238 exit(1); 1239 } 1240 } 1241 1242 QLIST_FOREACH(phb, &spapr->phbs, list) { 1243 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1244 if (ret < 0) { 1245 error_report("couldn't setup PCI devices in fdt"); 1246 exit(1); 1247 } 1248 } 1249 1250 spapr_dt_cpus(fdt, spapr); 1251 1252 /* ibm,drc-indexes and friends */ 1253 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1254 if (smc->dr_phb_enabled) { 1255 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1256 } 1257 if (mc->nvdimm_supported) { 1258 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1259 } 1260 if (root_drc_type_mask) { 1261 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1262 } 1263 1264 if (mc->has_hotpluggable_cpus) { 1265 int offset = fdt_path_offset(fdt, "/cpus"); 1266 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1267 if (ret < 0) { 1268 error_report("Couldn't set up CPU DR device tree properties"); 1269 exit(1); 1270 } 1271 } 1272 1273 /* /event-sources */ 1274 spapr_dt_events(spapr, fdt); 1275 1276 /* /rtas */ 1277 spapr_dt_rtas(spapr, fdt); 1278 1279 /* /chosen */ 1280 spapr_dt_chosen(spapr, fdt, reset); 1281 1282 /* /hypervisor */ 1283 if (kvm_enabled()) { 1284 spapr_dt_hypervisor(spapr, fdt); 1285 } 1286 1287 /* Build memory reserve map */ 1288 if (reset) { 1289 if (spapr->kernel_size) { 1290 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1291 spapr->kernel_size))); 1292 } 1293 if (spapr->initrd_size) { 1294 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1295 spapr->initrd_size))); 1296 } 1297 } 1298 1299 /* NVDIMM devices */ 1300 if (mc->nvdimm_supported) { 1301 spapr_dt_persistent_memory(spapr, fdt); 1302 } 1303 1304 return fdt; 1305 } 1306 1307 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1308 { 1309 SpaprMachineState *spapr = opaque; 1310 1311 return (addr & 0x0fffffff) + spapr->kernel_addr; 1312 } 1313 1314 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1315 PowerPCCPU *cpu) 1316 { 1317 CPUPPCState *env = &cpu->env; 1318 1319 /* The TCG path should also be holding the BQL at this point */ 1320 g_assert(bql_locked()); 1321 1322 g_assert(!vhyp_cpu_in_nested(cpu)); 1323 1324 if (FIELD_EX64(env->msr, MSR, PR)) { 1325 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1326 env->gpr[3] = H_PRIVILEGE; 1327 } else { 1328 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1329 } 1330 } 1331 1332 struct LPCRSyncState { 1333 target_ulong value; 1334 target_ulong mask; 1335 }; 1336 1337 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1338 { 1339 struct LPCRSyncState *s = arg.host_ptr; 1340 PowerPCCPU *cpu = POWERPC_CPU(cs); 1341 CPUPPCState *env = &cpu->env; 1342 target_ulong lpcr; 1343 1344 cpu_synchronize_state(cs); 1345 lpcr = env->spr[SPR_LPCR]; 1346 lpcr &= ~s->mask; 1347 lpcr |= s->value; 1348 ppc_store_lpcr(cpu, lpcr); 1349 } 1350 1351 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1352 { 1353 CPUState *cs; 1354 struct LPCRSyncState s = { 1355 .value = value, 1356 .mask = mask 1357 }; 1358 CPU_FOREACH(cs) { 1359 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1360 } 1361 } 1362 1363 /* May be used when the machine is not running */ 1364 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1365 { 1366 CPUState *cs; 1367 CPU_FOREACH(cs) { 1368 PowerPCCPU *cpu = POWERPC_CPU(cs); 1369 CPUPPCState *env = &cpu->env; 1370 target_ulong lpcr; 1371 1372 lpcr = env->spr[SPR_LPCR]; 1373 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1374 ppc_store_lpcr(cpu, lpcr); 1375 } 1376 } 1377 1378 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1379 target_ulong lpid, ppc_v3_pate_t *entry) 1380 { 1381 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1382 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1383 1384 if (!spapr_cpu->in_nested) { 1385 assert(lpid == 0); 1386 1387 /* Copy PATE1:GR into PATE0:HR */ 1388 entry->dw0 = spapr->patb_entry & PATE0_HR; 1389 entry->dw1 = spapr->patb_entry; 1390 return true; 1391 } else { 1392 if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) { 1393 return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); 1394 } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) { 1395 return spapr_get_pate_nested_papr(spapr, cpu, lpid, entry); 1396 } else { 1397 g_assert_not_reached(); 1398 } 1399 } 1400 } 1401 1402 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1403 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1404 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1405 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1406 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1407 1408 /* 1409 * Get the fd to access the kernel htab, re-opening it if necessary 1410 */ 1411 static int get_htab_fd(SpaprMachineState *spapr) 1412 { 1413 Error *local_err = NULL; 1414 1415 if (spapr->htab_fd >= 0) { 1416 return spapr->htab_fd; 1417 } 1418 1419 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1420 if (spapr->htab_fd < 0) { 1421 error_report_err(local_err); 1422 } 1423 1424 return spapr->htab_fd; 1425 } 1426 1427 void close_htab_fd(SpaprMachineState *spapr) 1428 { 1429 if (spapr->htab_fd >= 0) { 1430 close(spapr->htab_fd); 1431 } 1432 spapr->htab_fd = -1; 1433 } 1434 1435 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1436 { 1437 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1438 1439 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1440 } 1441 1442 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1443 { 1444 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1445 1446 assert(kvm_enabled()); 1447 1448 if (!spapr->htab) { 1449 return 0; 1450 } 1451 1452 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1453 } 1454 1455 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1456 hwaddr ptex, int n) 1457 { 1458 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1459 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1460 1461 if (!spapr->htab) { 1462 /* 1463 * HTAB is controlled by KVM. Fetch into temporary buffer 1464 */ 1465 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1466 kvmppc_read_hptes(hptes, ptex, n); 1467 return hptes; 1468 } 1469 1470 /* 1471 * HTAB is controlled by QEMU. Just point to the internally 1472 * accessible PTEG. 1473 */ 1474 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1475 } 1476 1477 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1478 const ppc_hash_pte64_t *hptes, 1479 hwaddr ptex, int n) 1480 { 1481 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1482 1483 if (!spapr->htab) { 1484 g_free((void *)hptes); 1485 } 1486 1487 /* Nothing to do for qemu managed HPT */ 1488 } 1489 1490 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1491 uint64_t pte0, uint64_t pte1) 1492 { 1493 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1494 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1495 1496 if (!spapr->htab) { 1497 kvmppc_write_hpte(ptex, pte0, pte1); 1498 } else { 1499 if (pte0 & HPTE64_V_VALID) { 1500 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1501 /* 1502 * When setting valid, we write PTE1 first. This ensures 1503 * proper synchronization with the reading code in 1504 * ppc_hash64_pteg_search() 1505 */ 1506 smp_wmb(); 1507 stq_p(spapr->htab + offset, pte0); 1508 } else { 1509 stq_p(spapr->htab + offset, pte0); 1510 /* 1511 * When clearing it we set PTE0 first. This ensures proper 1512 * synchronization with the reading code in 1513 * ppc_hash64_pteg_search() 1514 */ 1515 smp_wmb(); 1516 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1517 } 1518 } 1519 } 1520 1521 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1522 uint64_t pte1) 1523 { 1524 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1525 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1526 1527 if (!spapr->htab) { 1528 /* There should always be a hash table when this is called */ 1529 error_report("spapr_hpte_set_c called with no hash table !"); 1530 return; 1531 } 1532 1533 /* The HW performs a non-atomic byte update */ 1534 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1535 } 1536 1537 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1538 uint64_t pte1) 1539 { 1540 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1541 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1542 1543 if (!spapr->htab) { 1544 /* There should always be a hash table when this is called */ 1545 error_report("spapr_hpte_set_r called with no hash table !"); 1546 return; 1547 } 1548 1549 /* The HW performs a non-atomic byte update */ 1550 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1551 } 1552 1553 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1554 { 1555 int shift; 1556 1557 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1558 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1559 * that's much more than is needed for Linux guests */ 1560 shift = ctz64(pow2ceil(ramsize)) - 7; 1561 shift = MAX(shift, 18); /* Minimum architected size */ 1562 shift = MIN(shift, 46); /* Maximum architected size */ 1563 return shift; 1564 } 1565 1566 void spapr_free_hpt(SpaprMachineState *spapr) 1567 { 1568 qemu_vfree(spapr->htab); 1569 spapr->htab = NULL; 1570 spapr->htab_shift = 0; 1571 close_htab_fd(spapr); 1572 } 1573 1574 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1575 { 1576 ERRP_GUARD(); 1577 long rc; 1578 1579 /* Clean up any HPT info from a previous boot */ 1580 spapr_free_hpt(spapr); 1581 1582 rc = kvmppc_reset_htab(shift); 1583 1584 if (rc == -EOPNOTSUPP) { 1585 error_setg(errp, "HPT not supported in nested guests"); 1586 return -EOPNOTSUPP; 1587 } 1588 1589 if (rc < 0) { 1590 /* kernel-side HPT needed, but couldn't allocate one */ 1591 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1592 shift); 1593 error_append_hint(errp, "Try smaller maxmem?\n"); 1594 return -errno; 1595 } else if (rc > 0) { 1596 /* kernel-side HPT allocated */ 1597 if (rc != shift) { 1598 error_setg(errp, 1599 "Requested order %d HPT, but kernel allocated order %ld", 1600 shift, rc); 1601 error_append_hint(errp, "Try smaller maxmem?\n"); 1602 return -ENOSPC; 1603 } 1604 1605 spapr->htab_shift = shift; 1606 spapr->htab = NULL; 1607 } else { 1608 /* kernel-side HPT not needed, allocate in userspace instead */ 1609 size_t size = 1ULL << shift; 1610 int i; 1611 1612 spapr->htab = qemu_memalign(size, size); 1613 memset(spapr->htab, 0, size); 1614 spapr->htab_shift = shift; 1615 1616 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1617 DIRTY_HPTE(HPTE(spapr->htab, i)); 1618 } 1619 } 1620 /* We're setting up a hash table, so that means we're not radix */ 1621 spapr->patb_entry = 0; 1622 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1623 return 0; 1624 } 1625 1626 void spapr_setup_hpt(SpaprMachineState *spapr) 1627 { 1628 int hpt_shift; 1629 1630 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1631 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1632 } else { 1633 uint64_t current_ram_size; 1634 1635 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1636 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1637 } 1638 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1639 1640 if (kvm_enabled()) { 1641 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1642 1643 /* Check our RMA fits in the possible VRMA */ 1644 if (vrma_limit < spapr->rma_size) { 1645 error_report("Unable to create %" HWADDR_PRIu 1646 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1647 spapr->rma_size / MiB, vrma_limit / MiB); 1648 exit(EXIT_FAILURE); 1649 } 1650 } 1651 } 1652 1653 void spapr_check_mmu_mode(bool guest_radix) 1654 { 1655 if (guest_radix) { 1656 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1657 error_report("Guest requested unavailable MMU mode (radix)."); 1658 exit(EXIT_FAILURE); 1659 } 1660 } else { 1661 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1662 && !kvmppc_has_cap_mmu_hash_v3()) { 1663 error_report("Guest requested unavailable MMU mode (hash)."); 1664 exit(EXIT_FAILURE); 1665 } 1666 } 1667 } 1668 1669 static void spapr_machine_reset(MachineState *machine, ResetType type) 1670 { 1671 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1672 PowerPCCPU *first_ppc_cpu; 1673 hwaddr fdt_addr; 1674 void *fdt; 1675 int rc; 1676 1677 if (type != RESET_TYPE_SNAPSHOT_LOAD) { 1678 /* 1679 * Record-replay snapshot load must not consume random, this was 1680 * already replayed from initial machine reset. 1681 */ 1682 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1683 } 1684 1685 if (machine->cgs) { 1686 confidential_guest_kvm_reset(machine->cgs, &error_fatal); 1687 } 1688 spapr_caps_apply(spapr); 1689 spapr_nested_reset(spapr); 1690 1691 first_ppc_cpu = POWERPC_CPU(first_cpu); 1692 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1693 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1694 spapr->max_compat_pvr)) { 1695 /* 1696 * If using KVM with radix mode available, VCPUs can be started 1697 * without a HPT because KVM will start them in radix mode. 1698 * Set the GR bit in PATE so that we know there is no HPT. 1699 */ 1700 spapr->patb_entry = PATE1_GR; 1701 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1702 } else { 1703 spapr_setup_hpt(spapr); 1704 } 1705 1706 qemu_devices_reset(type); 1707 1708 spapr_ovec_cleanup(spapr->ov5_cas); 1709 spapr->ov5_cas = spapr_ovec_new(); 1710 1711 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1712 1713 /* 1714 * This is fixing some of the default configuration of the XIVE 1715 * devices. To be called after the reset of the machine devices. 1716 */ 1717 spapr_irq_reset(spapr, &error_fatal); 1718 1719 /* 1720 * There is no CAS under qtest. Simulate one to please the code that 1721 * depends on spapr->ov5_cas. This is especially needed to test device 1722 * unplug, so we do that before resetting the DRCs. 1723 */ 1724 if (qtest_enabled()) { 1725 spapr_ovec_cleanup(spapr->ov5_cas); 1726 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1727 } 1728 1729 spapr_nvdimm_finish_flushes(); 1730 1731 /* DRC reset may cause a device to be unplugged. This will cause troubles 1732 * if this device is used by another device (eg, a running vhost backend 1733 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1734 * situations, we reset DRCs after all devices have been reset. 1735 */ 1736 spapr_drc_reset_all(spapr); 1737 1738 spapr_clear_pending_events(spapr); 1739 1740 /* 1741 * We place the device tree just below either the top of the RMA, 1742 * or just below 2GB, whichever is lower, so that it can be 1743 * processed with 32-bit real mode code if necessary 1744 */ 1745 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1746 1747 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1748 if (spapr->vof) { 1749 spapr_vof_reset(spapr, fdt, &error_fatal); 1750 /* 1751 * Do not pack the FDT as the client may change properties. 1752 * VOF client does not expect the FDT so we do not load it to the VM. 1753 */ 1754 } else { 1755 rc = fdt_pack(fdt); 1756 /* Should only fail if we've built a corrupted tree */ 1757 assert(rc == 0); 1758 1759 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1760 0, fdt_addr, 0); 1761 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1762 } 1763 1764 g_free(spapr->fdt_blob); 1765 spapr->fdt_size = fdt_totalsize(fdt); 1766 spapr->fdt_initial_size = spapr->fdt_size; 1767 spapr->fdt_blob = fdt; 1768 1769 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1770 machine->fdt = fdt; 1771 1772 /* Set up the entry state */ 1773 first_ppc_cpu->env.gpr[5] = 0; 1774 1775 spapr->fwnmi_system_reset_addr = -1; 1776 spapr->fwnmi_machine_check_addr = -1; 1777 spapr->fwnmi_machine_check_interlock = -1; 1778 1779 /* Signal all vCPUs waiting on this condition */ 1780 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1781 1782 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1783 } 1784 1785 static void spapr_create_nvram(SpaprMachineState *spapr) 1786 { 1787 DeviceState *dev = qdev_new("spapr-nvram"); 1788 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1789 1790 if (dinfo) { 1791 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1792 &error_fatal); 1793 } 1794 1795 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1796 1797 spapr->nvram = (struct SpaprNvram *)dev; 1798 } 1799 1800 static void spapr_rtc_create(SpaprMachineState *spapr) 1801 { 1802 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1803 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1804 &error_fatal, NULL); 1805 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1806 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1807 "date"); 1808 } 1809 1810 /* Returns whether we want to use VGA or not */ 1811 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1812 { 1813 vga_interface_created = true; 1814 switch (vga_interface_type) { 1815 case VGA_NONE: 1816 return false; 1817 case VGA_DEVICE: 1818 return true; 1819 case VGA_STD: 1820 case VGA_VIRTIO: 1821 case VGA_CIRRUS: 1822 return pci_vga_init(pci_bus) != NULL; 1823 default: 1824 error_setg(errp, 1825 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1826 return false; 1827 } 1828 } 1829 1830 static int spapr_pre_load(void *opaque) 1831 { 1832 int rc; 1833 1834 rc = spapr_caps_pre_load(opaque); 1835 if (rc) { 1836 return rc; 1837 } 1838 1839 return 0; 1840 } 1841 1842 static int spapr_post_load(void *opaque, int version_id) 1843 { 1844 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1845 int err = 0; 1846 1847 err = spapr_caps_post_migration(spapr); 1848 if (err) { 1849 return err; 1850 } 1851 1852 /* 1853 * In earlier versions, there was no separate qdev for the PAPR 1854 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1855 * So when migrating from those versions, poke the incoming offset 1856 * value into the RTC device 1857 */ 1858 if (version_id < 3) { 1859 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1860 if (err) { 1861 return err; 1862 } 1863 } 1864 1865 if (kvm_enabled() && spapr->patb_entry) { 1866 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1867 bool radix = !!(spapr->patb_entry & PATE1_GR); 1868 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1869 1870 /* 1871 * Update LPCR:HR and UPRT as they may not be set properly in 1872 * the stream 1873 */ 1874 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1875 LPCR_HR | LPCR_UPRT); 1876 1877 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1878 if (err) { 1879 error_report("Process table config unsupported by the host"); 1880 return -EINVAL; 1881 } 1882 } 1883 1884 err = spapr_irq_post_load(spapr, version_id); 1885 if (err) { 1886 return err; 1887 } 1888 1889 return err; 1890 } 1891 1892 static int spapr_pre_save(void *opaque) 1893 { 1894 int rc; 1895 1896 rc = spapr_caps_pre_save(opaque); 1897 if (rc) { 1898 return rc; 1899 } 1900 1901 return 0; 1902 } 1903 1904 static bool version_before_3(void *opaque, int version_id) 1905 { 1906 return version_id < 3; 1907 } 1908 1909 static bool spapr_pending_events_needed(void *opaque) 1910 { 1911 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1912 return !QTAILQ_EMPTY(&spapr->pending_events); 1913 } 1914 1915 static const VMStateDescription vmstate_spapr_event_entry = { 1916 .name = "spapr_event_log_entry", 1917 .version_id = 1, 1918 .minimum_version_id = 1, 1919 .fields = (const VMStateField[]) { 1920 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1921 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1922 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1923 NULL, extended_length), 1924 VMSTATE_END_OF_LIST() 1925 }, 1926 }; 1927 1928 static const VMStateDescription vmstate_spapr_pending_events = { 1929 .name = "spapr_pending_events", 1930 .version_id = 1, 1931 .minimum_version_id = 1, 1932 .needed = spapr_pending_events_needed, 1933 .fields = (const VMStateField[]) { 1934 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1935 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1936 VMSTATE_END_OF_LIST() 1937 }, 1938 }; 1939 1940 static bool spapr_ov5_cas_needed(void *opaque) 1941 { 1942 SpaprMachineState *spapr = opaque; 1943 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1944 bool cas_needed; 1945 1946 /* Prior to the introduction of SpaprOptionVector, we had two option 1947 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1948 * Both of these options encode machine topology into the device-tree 1949 * in such a way that the now-booted OS should still be able to interact 1950 * appropriately with QEMU regardless of what options were actually 1951 * negotiatied on the source side. 1952 * 1953 * As such, we can avoid migrating the CAS-negotiated options if these 1954 * are the only options available on the current machine/platform. 1955 * Since these are the only options available for pseries-2.7 and 1956 * earlier, this allows us to maintain old->new/new->old migration 1957 * compatibility. 1958 * 1959 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1960 * via default pseries-2.8 machines and explicit command-line parameters. 1961 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1962 * of the actual CAS-negotiated values to continue working properly. For 1963 * example, availability of memory unplug depends on knowing whether 1964 * OV5_HP_EVT was negotiated via CAS. 1965 * 1966 * Thus, for any cases where the set of available CAS-negotiatable 1967 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1968 * include the CAS-negotiated options in the migration stream, unless 1969 * if they affect boot time behaviour only. 1970 */ 1971 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1972 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1973 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1974 1975 /* We need extra information if we have any bits outside the mask 1976 * defined above */ 1977 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1978 1979 spapr_ovec_cleanup(ov5_mask); 1980 1981 return cas_needed; 1982 } 1983 1984 static const VMStateDescription vmstate_spapr_ov5_cas = { 1985 .name = "spapr_option_vector_ov5_cas", 1986 .version_id = 1, 1987 .minimum_version_id = 1, 1988 .needed = spapr_ov5_cas_needed, 1989 .fields = (const VMStateField[]) { 1990 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1991 vmstate_spapr_ovec, SpaprOptionVector), 1992 VMSTATE_END_OF_LIST() 1993 }, 1994 }; 1995 1996 static bool spapr_patb_entry_needed(void *opaque) 1997 { 1998 SpaprMachineState *spapr = opaque; 1999 2000 return !!spapr->patb_entry; 2001 } 2002 2003 static const VMStateDescription vmstate_spapr_patb_entry = { 2004 .name = "spapr_patb_entry", 2005 .version_id = 1, 2006 .minimum_version_id = 1, 2007 .needed = spapr_patb_entry_needed, 2008 .fields = (const VMStateField[]) { 2009 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2010 VMSTATE_END_OF_LIST() 2011 }, 2012 }; 2013 2014 static bool spapr_irq_map_needed(void *opaque) 2015 { 2016 SpaprMachineState *spapr = opaque; 2017 2018 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2019 } 2020 2021 static const VMStateDescription vmstate_spapr_irq_map = { 2022 .name = "spapr_irq_map", 2023 .version_id = 1, 2024 .minimum_version_id = 1, 2025 .needed = spapr_irq_map_needed, 2026 .fields = (const VMStateField[]) { 2027 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2028 VMSTATE_END_OF_LIST() 2029 }, 2030 }; 2031 2032 static bool spapr_dtb_needed(void *opaque) 2033 { 2034 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2035 2036 return smc->update_dt_enabled; 2037 } 2038 2039 static int spapr_dtb_pre_load(void *opaque) 2040 { 2041 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2042 2043 g_free(spapr->fdt_blob); 2044 spapr->fdt_blob = NULL; 2045 spapr->fdt_size = 0; 2046 2047 return 0; 2048 } 2049 2050 static const VMStateDescription vmstate_spapr_dtb = { 2051 .name = "spapr_dtb", 2052 .version_id = 1, 2053 .minimum_version_id = 1, 2054 .needed = spapr_dtb_needed, 2055 .pre_load = spapr_dtb_pre_load, 2056 .fields = (const VMStateField[]) { 2057 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2058 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2059 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2060 fdt_size), 2061 VMSTATE_END_OF_LIST() 2062 }, 2063 }; 2064 2065 static bool spapr_fwnmi_needed(void *opaque) 2066 { 2067 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2068 2069 return spapr->fwnmi_machine_check_addr != -1; 2070 } 2071 2072 static int spapr_fwnmi_pre_save(void *opaque) 2073 { 2074 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2075 2076 /* 2077 * Check if machine check handling is in progress and print a 2078 * warning message. 2079 */ 2080 if (spapr->fwnmi_machine_check_interlock != -1) { 2081 warn_report("A machine check is being handled during migration. The" 2082 "handler may run and log hardware error on the destination"); 2083 } 2084 2085 return 0; 2086 } 2087 2088 static const VMStateDescription vmstate_spapr_fwnmi = { 2089 .name = "spapr_fwnmi", 2090 .version_id = 1, 2091 .minimum_version_id = 1, 2092 .needed = spapr_fwnmi_needed, 2093 .pre_save = spapr_fwnmi_pre_save, 2094 .fields = (const VMStateField[]) { 2095 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2096 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2097 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2098 VMSTATE_END_OF_LIST() 2099 }, 2100 }; 2101 2102 static const VMStateDescription vmstate_spapr = { 2103 .name = "spapr", 2104 .version_id = 3, 2105 .minimum_version_id = 1, 2106 .pre_load = spapr_pre_load, 2107 .post_load = spapr_post_load, 2108 .pre_save = spapr_pre_save, 2109 .fields = (const VMStateField[]) { 2110 /* used to be @next_irq */ 2111 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2112 2113 /* RTC offset */ 2114 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2115 2116 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2117 VMSTATE_END_OF_LIST() 2118 }, 2119 .subsections = (const VMStateDescription * const []) { 2120 &vmstate_spapr_ov5_cas, 2121 &vmstate_spapr_patb_entry, 2122 &vmstate_spapr_pending_events, 2123 &vmstate_spapr_cap_htm, 2124 &vmstate_spapr_cap_vsx, 2125 &vmstate_spapr_cap_dfp, 2126 &vmstate_spapr_cap_cfpc, 2127 &vmstate_spapr_cap_sbbc, 2128 &vmstate_spapr_cap_ibs, 2129 &vmstate_spapr_cap_hpt_maxpagesize, 2130 &vmstate_spapr_irq_map, 2131 &vmstate_spapr_cap_nested_kvm_hv, 2132 &vmstate_spapr_dtb, 2133 &vmstate_spapr_cap_large_decr, 2134 &vmstate_spapr_cap_ccf_assist, 2135 &vmstate_spapr_cap_fwnmi, 2136 &vmstate_spapr_fwnmi, 2137 &vmstate_spapr_cap_rpt_invalidate, 2138 &vmstate_spapr_cap_ail_mode_3, 2139 &vmstate_spapr_cap_nested_papr, 2140 NULL 2141 } 2142 }; 2143 2144 static int htab_save_setup(QEMUFile *f, void *opaque, Error **errp) 2145 { 2146 SpaprMachineState *spapr = opaque; 2147 2148 /* "Iteration" header */ 2149 if (!spapr->htab_shift) { 2150 qemu_put_be32(f, -1); 2151 } else { 2152 qemu_put_be32(f, spapr->htab_shift); 2153 } 2154 2155 if (spapr->htab) { 2156 spapr->htab_save_index = 0; 2157 spapr->htab_first_pass = true; 2158 } else { 2159 if (spapr->htab_shift) { 2160 assert(kvm_enabled()); 2161 } 2162 } 2163 2164 2165 return 0; 2166 } 2167 2168 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2169 int chunkstart, int n_valid, int n_invalid) 2170 { 2171 qemu_put_be32(f, chunkstart); 2172 qemu_put_be16(f, n_valid); 2173 qemu_put_be16(f, n_invalid); 2174 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2175 HASH_PTE_SIZE_64 * n_valid); 2176 } 2177 2178 static void htab_save_end_marker(QEMUFile *f) 2179 { 2180 qemu_put_be32(f, 0); 2181 qemu_put_be16(f, 0); 2182 qemu_put_be16(f, 0); 2183 } 2184 2185 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2186 int64_t max_ns) 2187 { 2188 bool has_timeout = max_ns != -1; 2189 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2190 int index = spapr->htab_save_index; 2191 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2192 2193 assert(spapr->htab_first_pass); 2194 2195 do { 2196 int chunkstart; 2197 2198 /* Consume invalid HPTEs */ 2199 while ((index < htabslots) 2200 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2201 CLEAN_HPTE(HPTE(spapr->htab, index)); 2202 index++; 2203 } 2204 2205 /* Consume valid HPTEs */ 2206 chunkstart = index; 2207 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2208 && HPTE_VALID(HPTE(spapr->htab, index))) { 2209 CLEAN_HPTE(HPTE(spapr->htab, index)); 2210 index++; 2211 } 2212 2213 if (index > chunkstart) { 2214 int n_valid = index - chunkstart; 2215 2216 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2217 2218 if (has_timeout && 2219 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2220 break; 2221 } 2222 } 2223 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2224 2225 if (index >= htabslots) { 2226 assert(index == htabslots); 2227 index = 0; 2228 spapr->htab_first_pass = false; 2229 } 2230 spapr->htab_save_index = index; 2231 } 2232 2233 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2234 int64_t max_ns) 2235 { 2236 bool final = max_ns < 0; 2237 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2238 int examined = 0, sent = 0; 2239 int index = spapr->htab_save_index; 2240 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2241 2242 assert(!spapr->htab_first_pass); 2243 2244 do { 2245 int chunkstart, invalidstart; 2246 2247 /* Consume non-dirty HPTEs */ 2248 while ((index < htabslots) 2249 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2250 index++; 2251 examined++; 2252 } 2253 2254 chunkstart = index; 2255 /* Consume valid dirty HPTEs */ 2256 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2257 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2258 && HPTE_VALID(HPTE(spapr->htab, index))) { 2259 CLEAN_HPTE(HPTE(spapr->htab, index)); 2260 index++; 2261 examined++; 2262 } 2263 2264 invalidstart = index; 2265 /* Consume invalid dirty HPTEs */ 2266 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2267 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2268 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2269 CLEAN_HPTE(HPTE(spapr->htab, index)); 2270 index++; 2271 examined++; 2272 } 2273 2274 if (index > chunkstart) { 2275 int n_valid = invalidstart - chunkstart; 2276 int n_invalid = index - invalidstart; 2277 2278 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2279 sent += index - chunkstart; 2280 2281 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2282 break; 2283 } 2284 } 2285 2286 if (examined >= htabslots) { 2287 break; 2288 } 2289 2290 if (index >= htabslots) { 2291 assert(index == htabslots); 2292 index = 0; 2293 } 2294 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2295 2296 if (index >= htabslots) { 2297 assert(index == htabslots); 2298 index = 0; 2299 } 2300 2301 spapr->htab_save_index = index; 2302 2303 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2304 } 2305 2306 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2307 #define MAX_KVM_BUF_SIZE 2048 2308 2309 static int htab_save_iterate(QEMUFile *f, void *opaque) 2310 { 2311 SpaprMachineState *spapr = opaque; 2312 int fd; 2313 int rc = 0; 2314 2315 /* Iteration header */ 2316 if (!spapr->htab_shift) { 2317 qemu_put_be32(f, -1); 2318 return 1; 2319 } else { 2320 qemu_put_be32(f, 0); 2321 } 2322 2323 if (!spapr->htab) { 2324 assert(kvm_enabled()); 2325 2326 fd = get_htab_fd(spapr); 2327 if (fd < 0) { 2328 return fd; 2329 } 2330 2331 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2332 if (rc < 0) { 2333 return rc; 2334 } 2335 } else if (spapr->htab_first_pass) { 2336 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2337 } else { 2338 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2339 } 2340 2341 htab_save_end_marker(f); 2342 2343 return rc; 2344 } 2345 2346 static int htab_save_complete(QEMUFile *f, void *opaque) 2347 { 2348 SpaprMachineState *spapr = opaque; 2349 int fd; 2350 2351 /* Iteration header */ 2352 if (!spapr->htab_shift) { 2353 qemu_put_be32(f, -1); 2354 return 0; 2355 } else { 2356 qemu_put_be32(f, 0); 2357 } 2358 2359 if (!spapr->htab) { 2360 int rc; 2361 2362 assert(kvm_enabled()); 2363 2364 fd = get_htab_fd(spapr); 2365 if (fd < 0) { 2366 return fd; 2367 } 2368 2369 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2370 if (rc < 0) { 2371 return rc; 2372 } 2373 } else { 2374 if (spapr->htab_first_pass) { 2375 htab_save_first_pass(f, spapr, -1); 2376 } 2377 htab_save_later_pass(f, spapr, -1); 2378 } 2379 2380 /* End marker */ 2381 htab_save_end_marker(f); 2382 2383 return 0; 2384 } 2385 2386 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2387 { 2388 SpaprMachineState *spapr = opaque; 2389 uint32_t section_hdr; 2390 int fd = -1; 2391 Error *local_err = NULL; 2392 2393 if (version_id < 1 || version_id > 1) { 2394 error_report("htab_load() bad version"); 2395 return -EINVAL; 2396 } 2397 2398 section_hdr = qemu_get_be32(f); 2399 2400 if (section_hdr == -1) { 2401 spapr_free_hpt(spapr); 2402 return 0; 2403 } 2404 2405 if (section_hdr) { 2406 int ret; 2407 2408 /* First section gives the htab size */ 2409 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2410 if (ret < 0) { 2411 error_report_err(local_err); 2412 return ret; 2413 } 2414 return 0; 2415 } 2416 2417 if (!spapr->htab) { 2418 assert(kvm_enabled()); 2419 2420 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2421 if (fd < 0) { 2422 error_report_err(local_err); 2423 return fd; 2424 } 2425 } 2426 2427 while (true) { 2428 uint32_t index; 2429 uint16_t n_valid, n_invalid; 2430 2431 index = qemu_get_be32(f); 2432 n_valid = qemu_get_be16(f); 2433 n_invalid = qemu_get_be16(f); 2434 2435 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2436 /* End of Stream */ 2437 break; 2438 } 2439 2440 if ((index + n_valid + n_invalid) > 2441 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2442 /* Bad index in stream */ 2443 error_report( 2444 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2445 index, n_valid, n_invalid, spapr->htab_shift); 2446 return -EINVAL; 2447 } 2448 2449 if (spapr->htab) { 2450 if (n_valid) { 2451 qemu_get_buffer(f, HPTE(spapr->htab, index), 2452 HASH_PTE_SIZE_64 * n_valid); 2453 } 2454 if (n_invalid) { 2455 memset(HPTE(spapr->htab, index + n_valid), 0, 2456 HASH_PTE_SIZE_64 * n_invalid); 2457 } 2458 } else { 2459 int rc; 2460 2461 assert(fd >= 0); 2462 2463 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2464 &local_err); 2465 if (rc < 0) { 2466 error_report_err(local_err); 2467 return rc; 2468 } 2469 } 2470 } 2471 2472 if (!spapr->htab) { 2473 assert(fd >= 0); 2474 close(fd); 2475 } 2476 2477 return 0; 2478 } 2479 2480 static void htab_save_cleanup(void *opaque) 2481 { 2482 SpaprMachineState *spapr = opaque; 2483 2484 close_htab_fd(spapr); 2485 } 2486 2487 static SaveVMHandlers savevm_htab_handlers = { 2488 .save_setup = htab_save_setup, 2489 .save_live_iterate = htab_save_iterate, 2490 .save_live_complete_precopy = htab_save_complete, 2491 .save_cleanup = htab_save_cleanup, 2492 .load_state = htab_load, 2493 }; 2494 2495 static void spapr_boot_set(void *opaque, const char *boot_device, 2496 Error **errp) 2497 { 2498 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2499 2500 g_free(spapr->boot_device); 2501 spapr->boot_device = g_strdup(boot_device); 2502 } 2503 2504 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2505 { 2506 MachineState *machine = MACHINE(spapr); 2507 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2508 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2509 int i; 2510 2511 g_assert(!nr_lmbs || machine->device_memory); 2512 for (i = 0; i < nr_lmbs; i++) { 2513 uint64_t addr; 2514 2515 addr = i * lmb_size + machine->device_memory->base; 2516 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2517 addr / lmb_size); 2518 } 2519 } 2520 2521 /* 2522 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2523 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2524 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2525 */ 2526 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2527 { 2528 int i; 2529 2530 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2531 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2532 " is not aligned to %" PRIu64 " MiB", 2533 machine->ram_size, 2534 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2535 return; 2536 } 2537 2538 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2539 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2540 " is not aligned to %" PRIu64 " MiB", 2541 machine->ram_size, 2542 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2543 return; 2544 } 2545 2546 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2547 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2548 error_setg(errp, 2549 "Node %d memory size 0x%" PRIx64 2550 " is not aligned to %" PRIu64 " MiB", 2551 i, machine->numa_state->nodes[i].node_mem, 2552 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2553 return; 2554 } 2555 } 2556 } 2557 2558 /* find cpu slot in machine->possible_cpus by core_id */ 2559 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2560 { 2561 int index = id / ms->smp.threads; 2562 2563 if (index >= ms->possible_cpus->len) { 2564 return NULL; 2565 } 2566 if (idx) { 2567 *idx = index; 2568 } 2569 return &ms->possible_cpus->cpus[index]; 2570 } 2571 2572 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2573 { 2574 MachineState *ms = MACHINE(spapr); 2575 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2576 Error *local_err = NULL; 2577 bool vsmt_user = !!spapr->vsmt; 2578 int kvm_smt = kvmppc_smt_threads(); 2579 int ret; 2580 unsigned int smp_threads = ms->smp.threads; 2581 2582 if (tcg_enabled()) { 2583 if (smp_threads > 1 && 2584 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2585 spapr->max_compat_pvr)) { 2586 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2587 return; 2588 } 2589 2590 if (smp_threads > 8) { 2591 error_setg(errp, "TCG cannot support more than 8 threads/core " 2592 "on a pseries machine"); 2593 return; 2594 } 2595 } 2596 if (!is_power_of_2(smp_threads)) { 2597 error_setg(errp, "Cannot support %d threads/core on a pseries " 2598 "machine because it must be a power of 2", smp_threads); 2599 return; 2600 } 2601 2602 /* Determine the VSMT mode to use: */ 2603 if (vsmt_user) { 2604 if (spapr->vsmt < smp_threads) { 2605 error_setg(errp, "Cannot support VSMT mode %d" 2606 " because it must be >= threads/core (%d)", 2607 spapr->vsmt, smp_threads); 2608 return; 2609 } 2610 /* In this case, spapr->vsmt has been set by the command line */ 2611 } else if (!smc->smp_threads_vsmt) { 2612 /* 2613 * Default VSMT value is tricky, because we need it to be as 2614 * consistent as possible (for migration), but this requires 2615 * changing it for at least some existing cases. We pick 8 as 2616 * the value that we'd get with KVM on POWER8, the 2617 * overwhelmingly common case in production systems. 2618 */ 2619 spapr->vsmt = MAX(8, smp_threads); 2620 } else { 2621 spapr->vsmt = smp_threads; 2622 } 2623 2624 /* KVM: If necessary, set the SMT mode: */ 2625 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2626 ret = kvmppc_set_smt_threads(spapr->vsmt); 2627 if (ret) { 2628 /* Looks like KVM isn't able to change VSMT mode */ 2629 error_setg(&local_err, 2630 "Failed to set KVM's VSMT mode to %d (errno %d)", 2631 spapr->vsmt, ret); 2632 /* We can live with that if the default one is big enough 2633 * for the number of threads, and a submultiple of the one 2634 * we want. In this case we'll waste some vcpu ids, but 2635 * behaviour will be correct */ 2636 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2637 warn_report_err(local_err); 2638 } else { 2639 if (!vsmt_user) { 2640 error_append_hint(&local_err, 2641 "On PPC, a VM with %d threads/core" 2642 " on a host with %d threads/core" 2643 " requires the use of VSMT mode %d.\n", 2644 smp_threads, kvm_smt, spapr->vsmt); 2645 } 2646 kvmppc_error_append_smt_possible_hint(&local_err); 2647 error_propagate(errp, local_err); 2648 } 2649 } 2650 } 2651 /* else TCG: nothing to do currently */ 2652 } 2653 2654 static void spapr_init_cpus(SpaprMachineState *spapr) 2655 { 2656 MachineState *machine = MACHINE(spapr); 2657 MachineClass *mc = MACHINE_GET_CLASS(machine); 2658 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2659 const CPUArchIdList *possible_cpus; 2660 unsigned int smp_cpus = machine->smp.cpus; 2661 unsigned int smp_threads = machine->smp.threads; 2662 unsigned int max_cpus = machine->smp.max_cpus; 2663 int boot_cores_nr = smp_cpus / smp_threads; 2664 int i; 2665 2666 possible_cpus = mc->possible_cpu_arch_ids(machine); 2667 if (mc->has_hotpluggable_cpus) { 2668 if (smp_cpus % smp_threads) { 2669 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2670 smp_cpus, smp_threads); 2671 exit(1); 2672 } 2673 if (max_cpus % smp_threads) { 2674 error_report("max_cpus (%u) must be multiple of threads (%u)", 2675 max_cpus, smp_threads); 2676 exit(1); 2677 } 2678 } else { 2679 if (max_cpus != smp_cpus) { 2680 error_report("This machine version does not support CPU hotplug"); 2681 exit(1); 2682 } 2683 boot_cores_nr = possible_cpus->len; 2684 } 2685 2686 for (i = 0; i < possible_cpus->len; i++) { 2687 int core_id = i * smp_threads; 2688 2689 if (mc->has_hotpluggable_cpus) { 2690 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2691 spapr_vcpu_id(spapr, core_id)); 2692 } 2693 2694 if (i < boot_cores_nr) { 2695 Object *core = object_new(type); 2696 int nr_threads = smp_threads; 2697 2698 /* Handle the partially filled core for older machine types */ 2699 if ((i + 1) * smp_threads >= smp_cpus) { 2700 nr_threads = smp_cpus - i * smp_threads; 2701 } 2702 2703 object_property_set_int(core, "nr-threads", nr_threads, 2704 &error_fatal); 2705 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2706 &error_fatal); 2707 qdev_realize(DEVICE(core), NULL, &error_fatal); 2708 2709 object_unref(core); 2710 } 2711 } 2712 } 2713 2714 static PCIHostState *spapr_create_default_phb(void) 2715 { 2716 DeviceState *dev; 2717 2718 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2719 qdev_prop_set_uint32(dev, "index", 0); 2720 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2721 2722 return PCI_HOST_BRIDGE(dev); 2723 } 2724 2725 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2726 { 2727 MachineState *machine = MACHINE(spapr); 2728 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2729 hwaddr rma_size = machine->ram_size; 2730 hwaddr node0_size = spapr_node0_size(machine); 2731 2732 /* RMA has to fit in the first NUMA node */ 2733 rma_size = MIN(rma_size, node0_size); 2734 2735 /* 2736 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2737 * never exceed that 2738 */ 2739 rma_size = MIN(rma_size, 1 * TiB); 2740 2741 /* 2742 * Clamp the RMA size based on machine type. This is for 2743 * migration compatibility with older qemu versions, which limited 2744 * the RMA size for complicated and mostly bad reasons. 2745 */ 2746 if (smc->rma_limit) { 2747 rma_size = MIN(rma_size, smc->rma_limit); 2748 } 2749 2750 if (rma_size < MIN_RMA_SLOF) { 2751 error_setg(errp, 2752 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2753 "ldMiB guest RMA (Real Mode Area memory)", 2754 MIN_RMA_SLOF / MiB); 2755 return 0; 2756 } 2757 2758 return rma_size; 2759 } 2760 2761 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2762 { 2763 MachineState *machine = MACHINE(spapr); 2764 int i; 2765 2766 for (i = 0; i < machine->ram_slots; i++) { 2767 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2768 } 2769 } 2770 2771 /* pSeries LPAR / sPAPR hardware init */ 2772 static void spapr_machine_init(MachineState *machine) 2773 { 2774 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2775 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2776 MachineClass *mc = MACHINE_GET_CLASS(machine); 2777 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2778 const char *bios_name = machine->firmware ?: bios_default; 2779 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2780 const char *kernel_filename = machine->kernel_filename; 2781 const char *initrd_filename = machine->initrd_filename; 2782 PCIHostState *phb; 2783 bool has_vga; 2784 int i; 2785 MemoryRegion *sysmem = get_system_memory(); 2786 long load_limit, fw_size; 2787 Error *resize_hpt_err = NULL; 2788 NICInfo *nd; 2789 2790 if (!filename) { 2791 error_report("Could not find LPAR firmware '%s'", bios_name); 2792 exit(1); 2793 } 2794 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2795 if (fw_size <= 0) { 2796 error_report("Could not load LPAR firmware '%s'", filename); 2797 exit(1); 2798 } 2799 2800 /* 2801 * if Secure VM (PEF) support is configured, then initialize it 2802 */ 2803 if (machine->cgs) { 2804 confidential_guest_kvm_init(machine->cgs, &error_fatal); 2805 } 2806 2807 msi_nonbroken = true; 2808 2809 QLIST_INIT(&spapr->phbs); 2810 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2811 2812 /* Determine capabilities to run with */ 2813 spapr_caps_init(spapr); 2814 2815 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2816 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2817 /* 2818 * If the user explicitly requested a mode we should either 2819 * supply it, or fail completely (which we do below). But if 2820 * it's not set explicitly, we reset our mode to something 2821 * that works 2822 */ 2823 if (resize_hpt_err) { 2824 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2825 error_free(resize_hpt_err); 2826 resize_hpt_err = NULL; 2827 } else { 2828 spapr->resize_hpt = smc->resize_hpt_default; 2829 } 2830 } 2831 2832 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2833 2834 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2835 /* 2836 * User requested HPT resize, but this host can't supply it. Bail out 2837 */ 2838 error_report_err(resize_hpt_err); 2839 exit(1); 2840 } 2841 error_free(resize_hpt_err); 2842 2843 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2844 2845 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2846 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2847 2848 /* 2849 * VSMT must be set in order to be able to compute VCPU ids, ie to 2850 * call spapr_max_server_number() or spapr_vcpu_id(). 2851 */ 2852 spapr_set_vsmt_mode(spapr, &error_fatal); 2853 2854 /* Set up Interrupt Controller before we create the VCPUs */ 2855 spapr_irq_init(spapr, &error_fatal); 2856 2857 /* Set up containers for ibm,client-architecture-support negotiated options 2858 */ 2859 spapr->ov5 = spapr_ovec_new(); 2860 spapr->ov5_cas = spapr_ovec_new(); 2861 2862 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2863 spapr_validate_node_memory(machine, &error_fatal); 2864 2865 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2866 2867 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2868 if (!smc->pre_6_2_numa_affinity) { 2869 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2870 } 2871 2872 /* advertise support for dedicated HP event source to guests */ 2873 if (spapr->use_hotplug_event_source) { 2874 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2875 } 2876 2877 /* advertise support for HPT resizing */ 2878 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2879 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2880 } 2881 2882 /* advertise support for ibm,dyamic-memory-v2 */ 2883 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2884 2885 /* advertise XIVE on POWER9 machines */ 2886 if (spapr->irq->xive) { 2887 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2888 } 2889 2890 /* init CPUs */ 2891 spapr_init_cpus(spapr); 2892 2893 /* Init numa_assoc_array */ 2894 spapr_numa_associativity_init(spapr, machine); 2895 2896 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2897 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2898 spapr->max_compat_pvr)) { 2899 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2900 /* KVM and TCG always allow GTSE with radix... */ 2901 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2902 } 2903 /* ... but not with hash (currently). */ 2904 2905 if (kvm_enabled()) { 2906 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2907 kvmppc_enable_logical_ci_hcalls(); 2908 kvmppc_enable_set_mode_hcall(); 2909 2910 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2911 kvmppc_enable_clear_ref_mod_hcalls(); 2912 2913 /* Enable H_PAGE_INIT */ 2914 kvmppc_enable_h_page_init(); 2915 } 2916 2917 /* map RAM */ 2918 memory_region_add_subregion(sysmem, 0, machine->ram); 2919 2920 /* initialize hotplug memory address space */ 2921 if (machine->ram_size < machine->maxram_size) { 2922 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2923 hwaddr device_mem_base; 2924 2925 /* 2926 * Limit the number of hotpluggable memory slots to half the number 2927 * slots that KVM supports, leaving the other half for PCI and other 2928 * devices. However ensure that number of slots doesn't drop below 32. 2929 */ 2930 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2931 SPAPR_MAX_RAM_SLOTS; 2932 2933 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2934 max_memslots = SPAPR_MAX_RAM_SLOTS; 2935 } 2936 if (machine->ram_slots > max_memslots) { 2937 error_report("Specified number of memory slots %" 2938 PRIu64" exceeds max supported %d", 2939 machine->ram_slots, max_memslots); 2940 exit(1); 2941 } 2942 2943 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 2944 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 2945 } 2946 2947 spapr_create_lmb_dr_connectors(spapr); 2948 2949 if (mc->nvdimm_supported) { 2950 spapr_create_nvdimm_dr_connectors(spapr); 2951 } 2952 2953 /* Set up RTAS event infrastructure */ 2954 spapr_events_init(spapr); 2955 2956 /* Set up the RTC RTAS interfaces */ 2957 spapr_rtc_create(spapr); 2958 2959 /* Set up VIO bus */ 2960 spapr->vio_bus = spapr_vio_bus_init(); 2961 2962 for (i = 0; serial_hd(i); i++) { 2963 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2964 } 2965 2966 /* We always have at least the nvram device on VIO */ 2967 spapr_create_nvram(spapr); 2968 2969 /* 2970 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2971 * connectors (described in root DT node's "ibm,drc-types" property) 2972 * are pre-initialized here. additional child connectors (such as 2973 * connectors for a PHBs PCI slots) are added as needed during their 2974 * parent's realization. 2975 */ 2976 if (smc->dr_phb_enabled) { 2977 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2978 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2979 } 2980 } 2981 2982 /* Set up PCI */ 2983 spapr_pci_rtas_init(); 2984 2985 phb = spapr_create_default_phb(); 2986 2987 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 2988 spapr_vlan_create(spapr->vio_bus, nd); 2989 } 2990 2991 pci_init_nic_devices(phb->bus, NULL); 2992 2993 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2994 spapr_vscsi_create(spapr->vio_bus); 2995 } 2996 2997 /* Graphics */ 2998 has_vga = spapr_vga_init(phb->bus, &error_fatal); 2999 if (has_vga) { 3000 spapr->want_stdout_path = !machine->enable_graphics; 3001 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3002 } else { 3003 spapr->want_stdout_path = true; 3004 } 3005 3006 if (machine->usb) { 3007 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3008 3009 if (has_vga) { 3010 USBBus *usb_bus; 3011 3012 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3013 &error_abort)); 3014 usb_create_simple(usb_bus, "usb-kbd"); 3015 usb_create_simple(usb_bus, "usb-mouse"); 3016 } 3017 } 3018 3019 if (kernel_filename) { 3020 uint64_t loaded_addr = 0; 3021 3022 spapr->kernel_size = load_elf(kernel_filename, NULL, 3023 translate_kernel_address, spapr, 3024 NULL, &loaded_addr, NULL, NULL, 3025 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); 3026 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3027 spapr->kernel_size = load_elf(kernel_filename, NULL, 3028 translate_kernel_address, spapr, 3029 NULL, &loaded_addr, NULL, NULL, 3030 ELFDATA2LSB, PPC_ELF_MACHINE, 0, 0); 3031 spapr->kernel_le = spapr->kernel_size > 0; 3032 } 3033 if (spapr->kernel_size < 0) { 3034 error_report("error loading %s: %s", kernel_filename, 3035 load_elf_strerror(spapr->kernel_size)); 3036 exit(1); 3037 } 3038 3039 if (spapr->kernel_addr != loaded_addr) { 3040 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3041 " to 0x%"PRIx64, 3042 spapr->kernel_addr, loaded_addr); 3043 spapr->kernel_addr = loaded_addr; 3044 } 3045 3046 /* load initrd */ 3047 if (initrd_filename) { 3048 /* Try to locate the initrd in the gap between the kernel 3049 * and the firmware. Add a bit of space just in case 3050 */ 3051 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3052 + 0x1ffff) & ~0xffff; 3053 spapr->initrd_size = load_image_targphys(initrd_filename, 3054 spapr->initrd_base, 3055 load_limit 3056 - spapr->initrd_base); 3057 if (spapr->initrd_size < 0) { 3058 error_report("could not load initial ram disk '%s'", 3059 initrd_filename); 3060 exit(1); 3061 } 3062 } 3063 } 3064 3065 /* FIXME: Should register things through the MachineState's qdev 3066 * interface, this is a legacy from the sPAPREnvironment structure 3067 * which predated MachineState but had a similar function */ 3068 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3069 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3070 &savevm_htab_handlers, spapr); 3071 3072 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3073 3074 qemu_register_boot_set(spapr_boot_set, spapr); 3075 3076 /* 3077 * Nothing needs to be done to resume a suspended guest because 3078 * suspending does not change the machine state, so no need for 3079 * a ->wakeup method. 3080 */ 3081 qemu_register_wakeup_support(); 3082 3083 if (kvm_enabled()) { 3084 /* to stop and start vmclock */ 3085 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3086 &spapr->tb); 3087 3088 kvmppc_spapr_enable_inkernel_multitce(); 3089 } 3090 3091 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3092 if (spapr->vof) { 3093 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3094 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3095 } 3096 3097 spapr_watchdog_init(spapr); 3098 } 3099 3100 #define DEFAULT_KVM_TYPE "auto" 3101 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3102 { 3103 /* 3104 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3105 * accommodate the 'HV' and 'PV' formats that exists in the 3106 * wild. The 'auto' mode is being introduced already as 3107 * lower-case, thus we don't need to bother checking for 3108 * "AUTO". 3109 */ 3110 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3111 return 0; 3112 } 3113 3114 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3115 return 1; 3116 } 3117 3118 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3119 return 2; 3120 } 3121 3122 error_report("Unknown kvm-type specified '%s'", vm_type); 3123 return -1; 3124 } 3125 3126 /* 3127 * Implementation of an interface to adjust firmware path 3128 * for the bootindex property handling. 3129 */ 3130 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3131 DeviceState *dev) 3132 { 3133 #define CAST(type, obj, name) \ 3134 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3135 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3136 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3137 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3138 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3139 3140 if (d && bus) { 3141 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3142 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3143 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3144 3145 if (spapr) { 3146 /* 3147 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3148 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3149 * 0x8000 | (target << 8) | (bus << 5) | lun 3150 * (see the "Logical unit addressing format" table in SAM5) 3151 */ 3152 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3153 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3154 (uint64_t)id << 48); 3155 } else if (virtio) { 3156 /* 3157 * We use SRP luns of the form 01000000 | (target << 8) | lun 3158 * in the top 32 bits of the 64-bit LUN 3159 * Note: the quote above is from SLOF and it is wrong, 3160 * the actual binding is: 3161 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3162 */ 3163 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3164 if (d->lun >= 256) { 3165 /* Use the LUN "flat space addressing method" */ 3166 id |= 0x4000; 3167 } 3168 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3169 (uint64_t)id << 32); 3170 } else if (usb) { 3171 /* 3172 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3173 * in the top 32 bits of the 64-bit LUN 3174 */ 3175 unsigned usb_port = atoi(usb->port->path); 3176 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3177 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3178 (uint64_t)id << 32); 3179 } 3180 } 3181 3182 /* 3183 * SLOF probes the USB devices, and if it recognizes that the device is a 3184 * storage device, it changes its name to "storage" instead of "usb-host", 3185 * and additionally adds a child node for the SCSI LUN, so the correct 3186 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3187 */ 3188 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3189 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3190 if (usb_device_is_scsi_storage(usbdev)) { 3191 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3192 } 3193 } 3194 3195 if (phb) { 3196 /* Replace "pci" with "pci@800000020000000" */ 3197 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3198 } 3199 3200 if (vsc) { 3201 /* Same logic as virtio above */ 3202 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3203 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3204 } 3205 3206 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3207 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3208 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3209 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3210 } 3211 3212 if (pcidev) { 3213 return spapr_pci_fw_dev_name(pcidev); 3214 } 3215 3216 return NULL; 3217 } 3218 3219 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3220 { 3221 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3222 3223 return g_strdup(spapr->kvm_type); 3224 } 3225 3226 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3227 { 3228 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3229 3230 g_free(spapr->kvm_type); 3231 spapr->kvm_type = g_strdup(value); 3232 } 3233 3234 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3235 { 3236 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3237 3238 return spapr->use_hotplug_event_source; 3239 } 3240 3241 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3242 Error **errp) 3243 { 3244 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3245 3246 spapr->use_hotplug_event_source = value; 3247 } 3248 3249 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3250 { 3251 return true; 3252 } 3253 3254 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3255 { 3256 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3257 3258 switch (spapr->resize_hpt) { 3259 case SPAPR_RESIZE_HPT_DEFAULT: 3260 return g_strdup("default"); 3261 case SPAPR_RESIZE_HPT_DISABLED: 3262 return g_strdup("disabled"); 3263 case SPAPR_RESIZE_HPT_ENABLED: 3264 return g_strdup("enabled"); 3265 case SPAPR_RESIZE_HPT_REQUIRED: 3266 return g_strdup("required"); 3267 } 3268 g_assert_not_reached(); 3269 } 3270 3271 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3272 { 3273 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3274 3275 if (strcmp(value, "default") == 0) { 3276 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3277 } else if (strcmp(value, "disabled") == 0) { 3278 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3279 } else if (strcmp(value, "enabled") == 0) { 3280 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3281 } else if (strcmp(value, "required") == 0) { 3282 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3283 } else { 3284 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3285 } 3286 } 3287 3288 static bool spapr_get_vof(Object *obj, Error **errp) 3289 { 3290 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3291 3292 return spapr->vof != NULL; 3293 } 3294 3295 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3296 { 3297 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3298 3299 if (spapr->vof) { 3300 vof_cleanup(spapr->vof); 3301 g_free(spapr->vof); 3302 spapr->vof = NULL; 3303 } 3304 if (!value) { 3305 return; 3306 } 3307 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3308 } 3309 3310 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3311 { 3312 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3313 3314 if (spapr->irq == &spapr_irq_xics_legacy) { 3315 return g_strdup("legacy"); 3316 } else if (spapr->irq == &spapr_irq_xics) { 3317 return g_strdup("xics"); 3318 } else if (spapr->irq == &spapr_irq_xive) { 3319 return g_strdup("xive"); 3320 } else if (spapr->irq == &spapr_irq_dual) { 3321 return g_strdup("dual"); 3322 } 3323 g_assert_not_reached(); 3324 } 3325 3326 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3327 { 3328 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3329 3330 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3331 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3332 return; 3333 } 3334 3335 /* The legacy IRQ backend can not be set */ 3336 if (strcmp(value, "xics") == 0) { 3337 spapr->irq = &spapr_irq_xics; 3338 } else if (strcmp(value, "xive") == 0) { 3339 spapr->irq = &spapr_irq_xive; 3340 } else if (strcmp(value, "dual") == 0) { 3341 spapr->irq = &spapr_irq_dual; 3342 } else { 3343 error_setg(errp, "Bad value for \"ic-mode\" property"); 3344 } 3345 } 3346 3347 static char *spapr_get_host_model(Object *obj, Error **errp) 3348 { 3349 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3350 3351 return g_strdup(spapr->host_model); 3352 } 3353 3354 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3355 { 3356 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3357 3358 g_free(spapr->host_model); 3359 spapr->host_model = g_strdup(value); 3360 } 3361 3362 static char *spapr_get_host_serial(Object *obj, Error **errp) 3363 { 3364 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3365 3366 return g_strdup(spapr->host_serial); 3367 } 3368 3369 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3370 { 3371 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3372 3373 g_free(spapr->host_serial); 3374 spapr->host_serial = g_strdup(value); 3375 } 3376 3377 static void spapr_instance_init(Object *obj) 3378 { 3379 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3380 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3381 MachineState *ms = MACHINE(spapr); 3382 MachineClass *mc = MACHINE_GET_CLASS(ms); 3383 3384 /* 3385 * NVDIMM support went live in 5.1 without considering that, in 3386 * other archs, the user needs to enable NVDIMM support with the 3387 * 'nvdimm' machine option and the default behavior is NVDIMM 3388 * support disabled. It is too late to roll back to the standard 3389 * behavior without breaking 5.1 guests. 3390 */ 3391 if (mc->nvdimm_supported) { 3392 ms->nvdimms_state->is_enabled = true; 3393 } 3394 3395 spapr->htab_fd = -1; 3396 spapr->use_hotplug_event_source = true; 3397 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3398 object_property_add_str(obj, "kvm-type", 3399 spapr_get_kvm_type, spapr_set_kvm_type); 3400 object_property_set_description(obj, "kvm-type", 3401 "Specifies the KVM virtualization mode (auto," 3402 " hv, pr). Defaults to 'auto'. This mode will use" 3403 " any available KVM module loaded in the host," 3404 " where kvm_hv takes precedence if both kvm_hv and" 3405 " kvm_pr are loaded."); 3406 object_property_add_bool(obj, "modern-hotplug-events", 3407 spapr_get_modern_hotplug_events, 3408 spapr_set_modern_hotplug_events); 3409 object_property_set_description(obj, "modern-hotplug-events", 3410 "Use dedicated hotplug event mechanism in" 3411 " place of standard EPOW events when possible" 3412 " (required for memory hot-unplug support)"); 3413 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3414 "Maximum permitted CPU compatibility mode"); 3415 3416 object_property_add_str(obj, "resize-hpt", 3417 spapr_get_resize_hpt, spapr_set_resize_hpt); 3418 object_property_set_description(obj, "resize-hpt", 3419 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3420 object_property_add_uint32_ptr(obj, "vsmt", 3421 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3422 object_property_set_description(obj, "vsmt", 3423 "Virtual SMT: KVM behaves as if this were" 3424 " the host's SMT mode"); 3425 3426 object_property_add_bool(obj, "vfio-no-msix-emulation", 3427 spapr_get_msix_emulation, NULL); 3428 3429 object_property_add_uint64_ptr(obj, "kernel-addr", 3430 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3431 object_property_set_description(obj, "kernel-addr", 3432 stringify(KERNEL_LOAD_ADDR) 3433 " for -kernel is the default"); 3434 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3435 3436 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3437 object_property_set_description(obj, "x-vof", 3438 "Enable Virtual Open Firmware (experimental)"); 3439 3440 /* The machine class defines the default interrupt controller mode */ 3441 spapr->irq = smc->irq; 3442 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3443 spapr_set_ic_mode); 3444 object_property_set_description(obj, "ic-mode", 3445 "Specifies the interrupt controller mode (xics, xive, dual)"); 3446 3447 object_property_add_str(obj, "host-model", 3448 spapr_get_host_model, spapr_set_host_model); 3449 object_property_set_description(obj, "host-model", 3450 "Host model to advertise in guest device tree"); 3451 object_property_add_str(obj, "host-serial", 3452 spapr_get_host_serial, spapr_set_host_serial); 3453 object_property_set_description(obj, "host-serial", 3454 "Host serial number to advertise in guest device tree"); 3455 } 3456 3457 static void spapr_machine_finalizefn(Object *obj) 3458 { 3459 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3460 3461 g_free(spapr->kvm_type); 3462 } 3463 3464 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3465 { 3466 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3467 CPUPPCState *env = cpu_env(cs); 3468 3469 cpu_synchronize_state(cs); 3470 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3471 if (spapr->fwnmi_system_reset_addr != -1) { 3472 uint64_t rtas_addr, addr; 3473 3474 /* get rtas addr from fdt */ 3475 rtas_addr = spapr_get_rtas_addr(); 3476 if (!rtas_addr) { 3477 qemu_system_guest_panicked(NULL); 3478 return; 3479 } 3480 3481 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3482 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3483 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3484 env->gpr[3] = addr; 3485 } 3486 ppc_cpu_do_system_reset(cs); 3487 if (spapr->fwnmi_system_reset_addr != -1) { 3488 env->nip = spapr->fwnmi_system_reset_addr; 3489 } 3490 } 3491 3492 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3493 { 3494 CPUState *cs; 3495 3496 CPU_FOREACH(cs) { 3497 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3498 } 3499 } 3500 3501 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3502 void *fdt, int *fdt_start_offset, Error **errp) 3503 { 3504 uint64_t addr; 3505 uint32_t node; 3506 3507 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3508 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3509 &error_abort); 3510 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3511 SPAPR_MEMORY_BLOCK_SIZE); 3512 return 0; 3513 } 3514 3515 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3516 bool dedicated_hp_event_source) 3517 { 3518 SpaprDrc *drc; 3519 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3520 int i; 3521 uint64_t addr = addr_start; 3522 bool hotplugged = spapr_drc_hotplugged(dev); 3523 3524 for (i = 0; i < nr_lmbs; i++) { 3525 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3526 addr / SPAPR_MEMORY_BLOCK_SIZE); 3527 g_assert(drc); 3528 3529 /* 3530 * memory_device_get_free_addr() provided a range of free addresses 3531 * that doesn't overlap with any existing mapping at pre-plug. The 3532 * corresponding LMB DRCs are thus assumed to be all attachable. 3533 */ 3534 spapr_drc_attach(drc, dev); 3535 if (!hotplugged) { 3536 spapr_drc_reset(drc); 3537 } 3538 addr += SPAPR_MEMORY_BLOCK_SIZE; 3539 } 3540 /* send hotplug notification to the 3541 * guest only in case of hotplugged memory 3542 */ 3543 if (hotplugged) { 3544 if (dedicated_hp_event_source) { 3545 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3546 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3547 g_assert(drc); 3548 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3549 nr_lmbs, 3550 spapr_drc_index(drc)); 3551 } else { 3552 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3553 nr_lmbs); 3554 } 3555 } 3556 } 3557 3558 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3559 { 3560 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3561 PCDIMMDevice *dimm = PC_DIMM(dev); 3562 uint64_t size, addr; 3563 int64_t slot; 3564 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3565 3566 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3567 3568 pc_dimm_plug(dimm, MACHINE(ms)); 3569 3570 if (!is_nvdimm) { 3571 addr = object_property_get_uint(OBJECT(dimm), 3572 PC_DIMM_ADDR_PROP, &error_abort); 3573 spapr_add_lmbs(dev, addr, size, 3574 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3575 } else { 3576 slot = object_property_get_int(OBJECT(dimm), 3577 PC_DIMM_SLOT_PROP, &error_abort); 3578 /* We should have valid slot number at this point */ 3579 g_assert(slot >= 0); 3580 spapr_add_nvdimm(dev, slot); 3581 } 3582 } 3583 3584 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3585 Error **errp) 3586 { 3587 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3588 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3589 PCDIMMDevice *dimm = PC_DIMM(dev); 3590 Error *local_err = NULL; 3591 uint64_t size; 3592 Object *memdev; 3593 hwaddr pagesize; 3594 3595 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3596 if (local_err) { 3597 error_propagate(errp, local_err); 3598 return; 3599 } 3600 3601 if (is_nvdimm) { 3602 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3603 return; 3604 } 3605 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3606 error_setg(errp, "Hotplugged memory size must be a multiple of " 3607 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3608 return; 3609 } 3610 3611 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3612 &error_abort); 3613 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3614 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3615 return; 3616 } 3617 3618 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), errp); 3619 } 3620 3621 struct SpaprDimmState { 3622 PCDIMMDevice *dimm; 3623 uint32_t nr_lmbs; 3624 QTAILQ_ENTRY(SpaprDimmState) next; 3625 }; 3626 3627 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3628 PCDIMMDevice *dimm) 3629 { 3630 SpaprDimmState *dimm_state = NULL; 3631 3632 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3633 if (dimm_state->dimm == dimm) { 3634 break; 3635 } 3636 } 3637 return dimm_state; 3638 } 3639 3640 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3641 uint32_t nr_lmbs, 3642 PCDIMMDevice *dimm) 3643 { 3644 SpaprDimmState *ds = NULL; 3645 3646 /* 3647 * If this request is for a DIMM whose removal had failed earlier 3648 * (due to guest's refusal to remove the LMBs), we would have this 3649 * dimm already in the pending_dimm_unplugs list. In that 3650 * case don't add again. 3651 */ 3652 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3653 if (!ds) { 3654 ds = g_new0(SpaprDimmState, 1); 3655 ds->nr_lmbs = nr_lmbs; 3656 ds->dimm = dimm; 3657 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3658 } 3659 return ds; 3660 } 3661 3662 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3663 SpaprDimmState *dimm_state) 3664 { 3665 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3666 g_free(dimm_state); 3667 } 3668 3669 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3670 PCDIMMDevice *dimm) 3671 { 3672 SpaprDrc *drc; 3673 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3674 &error_abort); 3675 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3676 uint32_t avail_lmbs = 0; 3677 uint64_t addr_start, addr; 3678 int i; 3679 3680 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3681 &error_abort); 3682 3683 addr = addr_start; 3684 for (i = 0; i < nr_lmbs; i++) { 3685 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3686 addr / SPAPR_MEMORY_BLOCK_SIZE); 3687 g_assert(drc); 3688 if (drc->dev) { 3689 avail_lmbs++; 3690 } 3691 addr += SPAPR_MEMORY_BLOCK_SIZE; 3692 } 3693 3694 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3695 } 3696 3697 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3698 { 3699 SpaprDimmState *ds; 3700 PCDIMMDevice *dimm; 3701 SpaprDrc *drc; 3702 uint32_t nr_lmbs; 3703 uint64_t size, addr_start, addr; 3704 int i; 3705 3706 if (!dev) { 3707 return; 3708 } 3709 3710 dimm = PC_DIMM(dev); 3711 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3712 3713 /* 3714 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3715 * unplug state, but one of its DRC is marked as unplug_requested. 3716 * This is bad and weird enough to g_assert() out. 3717 */ 3718 g_assert(ds); 3719 3720 spapr_pending_dimm_unplugs_remove(spapr, ds); 3721 3722 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3723 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3724 3725 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3726 &error_abort); 3727 3728 addr = addr_start; 3729 for (i = 0; i < nr_lmbs; i++) { 3730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3731 addr / SPAPR_MEMORY_BLOCK_SIZE); 3732 g_assert(drc); 3733 3734 drc->unplug_requested = false; 3735 addr += SPAPR_MEMORY_BLOCK_SIZE; 3736 } 3737 3738 /* 3739 * Tell QAPI that something happened and the memory 3740 * hotunplug wasn't successful. 3741 */ 3742 qapi_event_send_device_unplug_guest_error(dev->id, 3743 dev->canonical_path); 3744 } 3745 3746 /* Callback to be called during DRC release. */ 3747 void spapr_lmb_release(DeviceState *dev) 3748 { 3749 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3750 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3751 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3752 3753 /* This information will get lost if a migration occurs 3754 * during the unplug process. In this case recover it. */ 3755 if (ds == NULL) { 3756 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3757 g_assert(ds); 3758 /* The DRC being examined by the caller at least must be counted */ 3759 g_assert(ds->nr_lmbs); 3760 } 3761 3762 if (--ds->nr_lmbs) { 3763 return; 3764 } 3765 3766 /* 3767 * Now that all the LMBs have been removed by the guest, call the 3768 * unplug handler chain. This can never fail. 3769 */ 3770 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3771 object_unparent(OBJECT(dev)); 3772 } 3773 3774 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3775 { 3776 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3777 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3778 3779 /* We really shouldn't get this far without anything to unplug */ 3780 g_assert(ds); 3781 3782 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3783 qdev_unrealize(dev); 3784 spapr_pending_dimm_unplugs_remove(spapr, ds); 3785 } 3786 3787 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3788 DeviceState *dev, Error **errp) 3789 { 3790 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3791 PCDIMMDevice *dimm = PC_DIMM(dev); 3792 uint32_t nr_lmbs; 3793 uint64_t size, addr_start, addr; 3794 int i; 3795 SpaprDrc *drc; 3796 3797 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3798 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3799 return; 3800 } 3801 3802 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3803 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3804 3805 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3806 &error_abort); 3807 3808 /* 3809 * An existing pending dimm state for this DIMM means that there is an 3810 * unplug operation in progress, waiting for the spapr_lmb_release 3811 * callback to complete the job (BQL can't cover that far). In this case, 3812 * bail out to avoid detaching DRCs that were already released. 3813 */ 3814 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3815 error_setg(errp, "Memory unplug already in progress for device %s", 3816 dev->id); 3817 return; 3818 } 3819 3820 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3821 3822 addr = addr_start; 3823 for (i = 0; i < nr_lmbs; i++) { 3824 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3825 addr / SPAPR_MEMORY_BLOCK_SIZE); 3826 g_assert(drc); 3827 3828 spapr_drc_unplug_request(drc); 3829 addr += SPAPR_MEMORY_BLOCK_SIZE; 3830 } 3831 3832 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3833 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3834 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3835 nr_lmbs, spapr_drc_index(drc)); 3836 } 3837 3838 /* Callback to be called during DRC release. */ 3839 void spapr_core_release(DeviceState *dev) 3840 { 3841 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3842 3843 /* Call the unplug handler chain. This can never fail. */ 3844 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3845 object_unparent(OBJECT(dev)); 3846 } 3847 3848 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3849 { 3850 MachineState *ms = MACHINE(hotplug_dev); 3851 CPUCore *cc = CPU_CORE(dev); 3852 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3853 3854 assert(core_slot); 3855 core_slot->cpu = NULL; 3856 qdev_unrealize(dev); 3857 } 3858 3859 static 3860 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3861 Error **errp) 3862 { 3863 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3864 int index; 3865 SpaprDrc *drc; 3866 CPUCore *cc = CPU_CORE(dev); 3867 3868 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3869 error_setg(errp, "Unable to find CPU core with core-id: %d", 3870 cc->core_id); 3871 return; 3872 } 3873 if (index == 0) { 3874 error_setg(errp, "Boot CPU core may not be unplugged"); 3875 return; 3876 } 3877 3878 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3879 spapr_vcpu_id(spapr, cc->core_id)); 3880 g_assert(drc); 3881 3882 if (!spapr_drc_unplug_requested(drc)) { 3883 spapr_drc_unplug_request(drc); 3884 } 3885 3886 /* 3887 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3888 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3889 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3890 * attempt (e.g. the kernel will refuse to remove the last online 3891 * CPU), we will never attempt it again because unplug_requested 3892 * will still be 'true' in that case. 3893 */ 3894 spapr_hotplug_req_remove_by_index(drc); 3895 } 3896 3897 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3898 void *fdt, int *fdt_start_offset, Error **errp) 3899 { 3900 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3901 CPUState *cs = CPU(core->threads[0]); 3902 PowerPCCPU *cpu = POWERPC_CPU(cs); 3903 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3904 int id = spapr_get_vcpu_id(cpu); 3905 g_autofree char *nodename = NULL; 3906 int offset; 3907 3908 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3909 offset = fdt_add_subnode(fdt, 0, nodename); 3910 3911 spapr_dt_cpu(cs, fdt, offset, spapr); 3912 3913 /* 3914 * spapr_dt_cpu() does not fill the 'name' property in the 3915 * CPU node. The function is called during boot process, before 3916 * and after CAS, and overwriting the 'name' property written 3917 * by SLOF is not allowed. 3918 * 3919 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3920 * CPUs more compatible with the coldplugged ones, which have 3921 * the 'name' property. Linux Kernel also relies on this 3922 * property to identify CPU nodes. 3923 */ 3924 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3925 3926 *fdt_start_offset = offset; 3927 return 0; 3928 } 3929 3930 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3931 { 3932 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3933 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3934 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3935 CPUCore *cc = CPU_CORE(dev); 3936 SpaprDrc *drc; 3937 CPUArchId *core_slot; 3938 int index; 3939 bool hotplugged = spapr_drc_hotplugged(dev); 3940 int i; 3941 3942 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3943 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3944 3945 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3946 spapr_vcpu_id(spapr, cc->core_id)); 3947 3948 g_assert(drc || !mc->has_hotpluggable_cpus); 3949 3950 if (drc) { 3951 /* 3952 * spapr_core_pre_plug() already buys us this is a brand new 3953 * core being plugged into a free slot. Nothing should already 3954 * be attached to the corresponding DRC. 3955 */ 3956 spapr_drc_attach(drc, dev); 3957 3958 if (hotplugged) { 3959 /* 3960 * Send hotplug notification interrupt to the guest only 3961 * in case of hotplugged CPUs. 3962 */ 3963 spapr_hotplug_req_add_by_index(drc); 3964 } else { 3965 spapr_drc_reset(drc); 3966 } 3967 } 3968 3969 core_slot->cpu = CPU(dev); 3970 3971 /* 3972 * Set compatibility mode to match the boot CPU, which was either set 3973 * by the machine reset code or by CAS. This really shouldn't fail at 3974 * this point. 3975 */ 3976 if (hotplugged) { 3977 for (i = 0; i < cc->nr_threads; i++) { 3978 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3979 &error_abort); 3980 } 3981 } 3982 3983 } 3984 3985 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3986 Error **errp) 3987 { 3988 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3989 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3990 CPUCore *cc = CPU_CORE(dev); 3991 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3992 const char *type = object_get_typename(OBJECT(dev)); 3993 CPUArchId *core_slot; 3994 int index; 3995 unsigned int smp_threads = machine->smp.threads; 3996 3997 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3998 error_setg(errp, "CPU hotplug not supported for this machine"); 3999 return; 4000 } 4001 4002 if (strcmp(base_core_type, type)) { 4003 error_setg(errp, "CPU core type should be %s", base_core_type); 4004 return; 4005 } 4006 4007 if (cc->core_id % smp_threads) { 4008 error_setg(errp, "invalid core id %d", cc->core_id); 4009 return; 4010 } 4011 4012 /* 4013 * In general we should have homogeneous threads-per-core, but old 4014 * (pre hotplug support) machine types allow the last core to have 4015 * reduced threads as a compatibility hack for when we allowed 4016 * total vcpus not a multiple of threads-per-core. 4017 */ 4018 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4019 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4020 smp_threads); 4021 return; 4022 } 4023 4024 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4025 if (!core_slot) { 4026 error_setg(errp, "core id %d out of range", cc->core_id); 4027 return; 4028 } 4029 4030 if (core_slot->cpu) { 4031 error_setg(errp, "core %d already populated", cc->core_id); 4032 return; 4033 } 4034 4035 numa_cpu_pre_plug(core_slot, dev, errp); 4036 } 4037 4038 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4039 void *fdt, int *fdt_start_offset, Error **errp) 4040 { 4041 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4042 int intc_phandle; 4043 4044 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4045 if (intc_phandle <= 0) { 4046 return -1; 4047 } 4048 4049 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4050 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4051 return -1; 4052 } 4053 4054 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4055 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4056 4057 return 0; 4058 } 4059 4060 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4061 Error **errp) 4062 { 4063 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4064 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4065 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4066 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4067 SpaprDrc *drc; 4068 4069 if (dev->hotplugged && !smc->dr_phb_enabled) { 4070 error_setg(errp, "PHB hotplug not supported for this machine"); 4071 return false; 4072 } 4073 4074 if (sphb->index == (uint32_t)-1) { 4075 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4076 return false; 4077 } 4078 4079 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4080 if (drc && drc->dev) { 4081 error_setg(errp, "PHB %d already attached", sphb->index); 4082 return false; 4083 } 4084 4085 /* 4086 * This will check that sphb->index doesn't exceed the maximum number of 4087 * PHBs for the current machine type. 4088 */ 4089 return 4090 smc->phb_placement(spapr, sphb->index, 4091 &sphb->buid, &sphb->io_win_addr, 4092 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4093 windows_supported, sphb->dma_liobn, 4094 errp); 4095 } 4096 4097 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4098 { 4099 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4100 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4101 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4102 SpaprDrc *drc; 4103 bool hotplugged = spapr_drc_hotplugged(dev); 4104 4105 if (!smc->dr_phb_enabled) { 4106 return; 4107 } 4108 4109 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4110 /* hotplug hooks should check it's enabled before getting this far */ 4111 assert(drc); 4112 4113 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4114 spapr_drc_attach(drc, dev); 4115 4116 if (hotplugged) { 4117 spapr_hotplug_req_add_by_index(drc); 4118 } else { 4119 spapr_drc_reset(drc); 4120 } 4121 } 4122 4123 void spapr_phb_release(DeviceState *dev) 4124 { 4125 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4126 4127 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4128 object_unparent(OBJECT(dev)); 4129 } 4130 4131 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4132 { 4133 qdev_unrealize(dev); 4134 } 4135 4136 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4137 DeviceState *dev, Error **errp) 4138 { 4139 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4140 SpaprDrc *drc; 4141 4142 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4143 assert(drc); 4144 4145 if (!spapr_drc_unplug_requested(drc)) { 4146 spapr_drc_unplug_request(drc); 4147 spapr_hotplug_req_remove_by_index(drc); 4148 } else { 4149 error_setg(errp, 4150 "PCI Host Bridge unplug already in progress for device %s", 4151 dev->id); 4152 } 4153 } 4154 4155 static 4156 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4157 Error **errp) 4158 { 4159 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4160 4161 if (spapr->tpm_proxy != NULL) { 4162 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4163 return false; 4164 } 4165 4166 return true; 4167 } 4168 4169 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4170 { 4171 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4172 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4173 4174 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4175 g_assert(spapr->tpm_proxy == NULL); 4176 4177 spapr->tpm_proxy = tpm_proxy; 4178 } 4179 4180 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4181 { 4182 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4183 4184 qdev_unrealize(dev); 4185 object_unparent(OBJECT(dev)); 4186 spapr->tpm_proxy = NULL; 4187 } 4188 4189 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4190 DeviceState *dev, Error **errp) 4191 { 4192 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4193 spapr_memory_plug(hotplug_dev, dev); 4194 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4195 spapr_core_plug(hotplug_dev, dev); 4196 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4197 spapr_phb_plug(hotplug_dev, dev); 4198 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4199 spapr_tpm_proxy_plug(hotplug_dev, dev); 4200 } 4201 } 4202 4203 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4204 DeviceState *dev, Error **errp) 4205 { 4206 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4207 spapr_memory_unplug(hotplug_dev, dev); 4208 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4209 spapr_core_unplug(hotplug_dev, dev); 4210 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4211 spapr_phb_unplug(hotplug_dev, dev); 4212 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4213 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4214 } 4215 } 4216 4217 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4218 { 4219 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4220 /* 4221 * CAS will process all pending unplug requests. 4222 * 4223 * HACK: a guest could theoretically have cleared all bits in OV5, 4224 * but none of the guests we care for do. 4225 */ 4226 spapr_ovec_empty(spapr->ov5_cas); 4227 } 4228 4229 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4230 DeviceState *dev, Error **errp) 4231 { 4232 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4233 MachineClass *mc = MACHINE_GET_CLASS(sms); 4234 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4235 4236 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4237 if (spapr_memory_hot_unplug_supported(sms)) { 4238 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4239 } else { 4240 error_setg(errp, "Memory hot unplug not supported for this guest"); 4241 } 4242 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4243 if (!mc->has_hotpluggable_cpus) { 4244 error_setg(errp, "CPU hot unplug not supported on this machine"); 4245 return; 4246 } 4247 spapr_core_unplug_request(hotplug_dev, dev, errp); 4248 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4249 if (!smc->dr_phb_enabled) { 4250 error_setg(errp, "PHB hot unplug not supported on this machine"); 4251 return; 4252 } 4253 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4254 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4255 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4256 } 4257 } 4258 4259 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4260 DeviceState *dev, Error **errp) 4261 { 4262 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4263 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4264 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4265 spapr_core_pre_plug(hotplug_dev, dev, errp); 4266 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4267 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4268 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4269 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4270 } 4271 } 4272 4273 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4274 DeviceState *dev) 4275 { 4276 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4277 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4278 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4279 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4280 return HOTPLUG_HANDLER(machine); 4281 } 4282 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4283 PCIDevice *pcidev = PCI_DEVICE(dev); 4284 PCIBus *root = pci_device_root_bus(pcidev); 4285 SpaprPhbState *phb = 4286 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4287 TYPE_SPAPR_PCI_HOST_BRIDGE); 4288 4289 if (phb) { 4290 return HOTPLUG_HANDLER(phb); 4291 } 4292 } 4293 return NULL; 4294 } 4295 4296 static CpuInstanceProperties 4297 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4298 { 4299 CPUArchId *core_slot; 4300 MachineClass *mc = MACHINE_GET_CLASS(machine); 4301 4302 /* make sure possible_cpu are initialized */ 4303 mc->possible_cpu_arch_ids(machine); 4304 /* get CPU core slot containing thread that matches cpu_index */ 4305 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4306 assert(core_slot); 4307 return core_slot->props; 4308 } 4309 4310 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4311 { 4312 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4313 } 4314 4315 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4316 { 4317 int i; 4318 unsigned int smp_threads = machine->smp.threads; 4319 unsigned int smp_cpus = machine->smp.cpus; 4320 const char *core_type; 4321 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4322 MachineClass *mc = MACHINE_GET_CLASS(machine); 4323 4324 if (!mc->has_hotpluggable_cpus) { 4325 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4326 } 4327 if (machine->possible_cpus) { 4328 assert(machine->possible_cpus->len == spapr_max_cores); 4329 return machine->possible_cpus; 4330 } 4331 4332 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4333 if (!core_type) { 4334 error_report("Unable to find sPAPR CPU Core definition"); 4335 exit(1); 4336 } 4337 4338 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4339 sizeof(CPUArchId) * spapr_max_cores); 4340 machine->possible_cpus->len = spapr_max_cores; 4341 for (i = 0; i < machine->possible_cpus->len; i++) { 4342 int core_id = i * smp_threads; 4343 4344 machine->possible_cpus->cpus[i].type = core_type; 4345 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4346 machine->possible_cpus->cpus[i].arch_id = core_id; 4347 machine->possible_cpus->cpus[i].props.has_core_id = true; 4348 machine->possible_cpus->cpus[i].props.core_id = core_id; 4349 } 4350 return machine->possible_cpus; 4351 } 4352 4353 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4354 uint64_t *buid, hwaddr *pio, 4355 hwaddr *mmio32, hwaddr *mmio64, 4356 unsigned n_dma, uint32_t *liobns, Error **errp) 4357 { 4358 /* 4359 * New-style PHB window placement. 4360 * 4361 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4362 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4363 * windows. 4364 * 4365 * Some guest kernels can't work with MMIO windows above 1<<46 4366 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4367 * 4368 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4369 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4370 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4371 * 1TiB 64-bit MMIO windows for each PHB. 4372 */ 4373 const uint64_t base_buid = 0x800000020000000ULL; 4374 int i; 4375 4376 /* Sanity check natural alignments */ 4377 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4378 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4379 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4380 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4381 /* Sanity check bounds */ 4382 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4383 SPAPR_PCI_MEM32_WIN_SIZE); 4384 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4385 SPAPR_PCI_MEM64_WIN_SIZE); 4386 4387 if (index >= SPAPR_MAX_PHBS) { 4388 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4389 SPAPR_MAX_PHBS - 1); 4390 return false; 4391 } 4392 4393 *buid = base_buid + index; 4394 for (i = 0; i < n_dma; ++i) { 4395 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4396 } 4397 4398 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4399 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4400 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4401 return true; 4402 } 4403 4404 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4405 { 4406 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4407 4408 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4409 } 4410 4411 static void spapr_ics_resend(XICSFabric *dev) 4412 { 4413 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4414 4415 ics_resend(spapr->ics); 4416 } 4417 4418 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4419 { 4420 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4421 4422 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4423 } 4424 4425 static void spapr_pic_print_info(InterruptStatsProvider *obj, GString *buf) 4426 { 4427 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4428 4429 spapr_irq_print_info(spapr, buf); 4430 g_string_append_printf(buf, "irqchip: %s\n", 4431 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4432 } 4433 4434 /* 4435 * This is a XIVE only operation 4436 */ 4437 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4438 uint8_t nvt_blk, uint32_t nvt_idx, 4439 bool cam_ignore, uint8_t priority, 4440 uint32_t logic_serv, XiveTCTXMatch *match) 4441 { 4442 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4443 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4444 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4445 int count; 4446 4447 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4448 priority, logic_serv, match); 4449 if (count < 0) { 4450 return count; 4451 } 4452 4453 /* 4454 * When we implement the save and restore of the thread interrupt 4455 * contexts in the enter/exit CPU handlers of the machine and the 4456 * escalations in QEMU, we should be able to handle non dispatched 4457 * vCPUs. 4458 * 4459 * Until this is done, the sPAPR machine should find at least one 4460 * matching context always. 4461 */ 4462 if (count == 0) { 4463 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4464 nvt_blk, nvt_idx); 4465 } 4466 4467 return count; 4468 } 4469 4470 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4471 { 4472 return cpu->vcpu_id; 4473 } 4474 4475 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4476 { 4477 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4478 MachineState *ms = MACHINE(spapr); 4479 int vcpu_id; 4480 4481 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4482 4483 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4484 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4485 error_append_hint(errp, "Adjust the number of cpus to %d " 4486 "or try to raise the number of threads per core\n", 4487 vcpu_id * ms->smp.threads / spapr->vsmt); 4488 return false; 4489 } 4490 4491 cpu->vcpu_id = vcpu_id; 4492 return true; 4493 } 4494 4495 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4496 { 4497 CPUState *cs; 4498 4499 CPU_FOREACH(cs) { 4500 PowerPCCPU *cpu = POWERPC_CPU(cs); 4501 4502 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4503 return cpu; 4504 } 4505 } 4506 4507 return NULL; 4508 } 4509 4510 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4511 { 4512 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4513 4514 return spapr_cpu->in_nested; 4515 } 4516 4517 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4518 { 4519 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4520 4521 /* These are only called by TCG, KVM maintains dispatch state */ 4522 4523 spapr_cpu->prod = false; 4524 if (spapr_cpu->vpa_addr) { 4525 CPUState *cs = CPU(cpu); 4526 uint32_t dispatch; 4527 4528 dispatch = ldl_be_phys(cs->as, 4529 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4530 dispatch++; 4531 if ((dispatch & 1) != 0) { 4532 qemu_log_mask(LOG_GUEST_ERROR, 4533 "VPA: incorrect dispatch counter value for " 4534 "dispatched partition %u, correcting.\n", dispatch); 4535 dispatch++; 4536 } 4537 stl_be_phys(cs->as, 4538 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4539 } 4540 } 4541 4542 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4543 { 4544 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4545 4546 if (spapr_cpu->vpa_addr) { 4547 CPUState *cs = CPU(cpu); 4548 uint32_t dispatch; 4549 4550 dispatch = ldl_be_phys(cs->as, 4551 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4552 dispatch++; 4553 if ((dispatch & 1) != 1) { 4554 qemu_log_mask(LOG_GUEST_ERROR, 4555 "VPA: incorrect dispatch counter value for " 4556 "preempted partition %u, correcting.\n", dispatch); 4557 dispatch++; 4558 } 4559 stl_be_phys(cs->as, 4560 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4561 } 4562 } 4563 4564 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4565 { 4566 MachineClass *mc = MACHINE_CLASS(oc); 4567 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4568 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4569 NMIClass *nc = NMI_CLASS(oc); 4570 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4571 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4572 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4573 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4574 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4575 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4576 4577 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4578 mc->ignore_boot_device_suffixes = true; 4579 4580 /* 4581 * We set up the default / latest behaviour here. The class_init 4582 * functions for the specific versioned machine types can override 4583 * these details for backwards compatibility 4584 */ 4585 mc->init = spapr_machine_init; 4586 mc->reset = spapr_machine_reset; 4587 mc->block_default_type = IF_SCSI; 4588 4589 /* 4590 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4591 * In TCG the limit is restricted by the range of CPU IPIs available. 4592 */ 4593 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4594 4595 mc->no_parallel = 1; 4596 mc->default_boot_order = ""; 4597 mc->default_ram_size = 512 * MiB; 4598 mc->default_ram_id = "ppc_spapr.ram"; 4599 mc->default_display = "std"; 4600 mc->kvm_type = spapr_kvm_type; 4601 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4602 mc->pci_allow_0_address = true; 4603 assert(!mc->get_hotplug_handler); 4604 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4605 hc->pre_plug = spapr_machine_device_pre_plug; 4606 hc->plug = spapr_machine_device_plug; 4607 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4608 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4609 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4610 hc->unplug_request = spapr_machine_device_unplug_request; 4611 hc->unplug = spapr_machine_device_unplug; 4612 4613 smc->update_dt_enabled = true; 4614 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4615 mc->has_hotpluggable_cpus = true; 4616 mc->nvdimm_supported = true; 4617 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4618 fwc->get_dev_path = spapr_get_fw_dev_path; 4619 nc->nmi_monitor_handler = spapr_nmi; 4620 smc->phb_placement = spapr_phb_placement; 4621 vhc->cpu_in_nested = spapr_cpu_in_nested; 4622 vhc->deliver_hv_excp = spapr_exit_nested; 4623 vhc->hypercall = emulate_spapr_hypercall; 4624 vhc->hpt_mask = spapr_hpt_mask; 4625 vhc->map_hptes = spapr_map_hptes; 4626 vhc->unmap_hptes = spapr_unmap_hptes; 4627 vhc->hpte_set_c = spapr_hpte_set_c; 4628 vhc->hpte_set_r = spapr_hpte_set_r; 4629 vhc->get_pate = spapr_get_pate; 4630 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4631 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4632 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4633 xic->ics_get = spapr_ics_get; 4634 xic->ics_resend = spapr_ics_resend; 4635 xic->icp_get = spapr_icp_get; 4636 ispc->print_info = spapr_pic_print_info; 4637 /* Force NUMA node memory size to be a multiple of 4638 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4639 * in which LMBs are represented and hot-added 4640 */ 4641 mc->numa_mem_align_shift = 28; 4642 mc->auto_enable_numa = true; 4643 4644 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4645 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4646 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4647 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4648 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4649 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4650 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4651 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4652 smc->default_caps.caps[SPAPR_CAP_NESTED_PAPR] = SPAPR_CAP_OFF; 4653 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4654 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4655 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4656 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4657 4658 /* 4659 * This cap specifies whether the AIL 3 mode for 4660 * H_SET_RESOURCE is supported. The default is modified 4661 * by default_caps_with_cpu(). 4662 */ 4663 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4664 spapr_caps_add_properties(smc); 4665 smc->irq = &spapr_irq_dual; 4666 smc->dr_phb_enabled = true; 4667 smc->linux_pci_probe = true; 4668 smc->smp_threads_vsmt = true; 4669 smc->nr_xirqs = SPAPR_NR_XIRQS; 4670 xfc->match_nvt = spapr_match_nvt; 4671 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4672 vmc->quiesce = spapr_vof_quiesce; 4673 vmc->setprop = spapr_vof_setprop; 4674 } 4675 4676 static const TypeInfo spapr_machine_info = { 4677 .name = TYPE_SPAPR_MACHINE, 4678 .parent = TYPE_MACHINE, 4679 .abstract = true, 4680 .instance_size = sizeof(SpaprMachineState), 4681 .instance_init = spapr_instance_init, 4682 .instance_finalize = spapr_machine_finalizefn, 4683 .class_size = sizeof(SpaprMachineClass), 4684 .class_init = spapr_machine_class_init, 4685 .interfaces = (InterfaceInfo[]) { 4686 { TYPE_FW_PATH_PROVIDER }, 4687 { TYPE_NMI }, 4688 { TYPE_HOTPLUG_HANDLER }, 4689 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4690 { TYPE_XICS_FABRIC }, 4691 { TYPE_INTERRUPT_STATS_PROVIDER }, 4692 { TYPE_XIVE_FABRIC }, 4693 { TYPE_VOF_MACHINE_IF }, 4694 { } 4695 }, 4696 }; 4697 4698 static void spapr_machine_latest_class_options(MachineClass *mc) 4699 { 4700 mc->alias = "pseries"; 4701 mc->is_default = true; 4702 } 4703 4704 #define DEFINE_SPAPR_MACHINE_IMPL(latest, ...) \ 4705 static void MACHINE_VER_SYM(class_init, spapr, __VA_ARGS__)( \ 4706 ObjectClass *oc, \ 4707 void *data) \ 4708 { \ 4709 MachineClass *mc = MACHINE_CLASS(oc); \ 4710 MACHINE_VER_SYM(class_options, spapr, __VA_ARGS__)(mc); \ 4711 MACHINE_VER_DEPRECATION(__VA_ARGS__); \ 4712 if (latest) { \ 4713 spapr_machine_latest_class_options(mc); \ 4714 } \ 4715 } \ 4716 static const TypeInfo MACHINE_VER_SYM(info, spapr, __VA_ARGS__) = \ 4717 { \ 4718 .name = MACHINE_VER_TYPE_NAME("pseries", __VA_ARGS__), \ 4719 .parent = TYPE_SPAPR_MACHINE, \ 4720 .class_init = MACHINE_VER_SYM(class_init, spapr, __VA_ARGS__), \ 4721 }; \ 4722 static void MACHINE_VER_SYM(register, spapr, __VA_ARGS__)(void) \ 4723 { \ 4724 MACHINE_VER_DELETION(__VA_ARGS__); \ 4725 type_register_static(&MACHINE_VER_SYM(info, spapr, __VA_ARGS__)); \ 4726 } \ 4727 type_init(MACHINE_VER_SYM(register, spapr, __VA_ARGS__)) 4728 4729 #define DEFINE_SPAPR_MACHINE_AS_LATEST(major, minor) \ 4730 DEFINE_SPAPR_MACHINE_IMPL(true, major, minor) 4731 #define DEFINE_SPAPR_MACHINE(major, minor) \ 4732 DEFINE_SPAPR_MACHINE_IMPL(false, major, minor) 4733 4734 /* 4735 * pseries-10.0 4736 */ 4737 static void spapr_machine_10_0_class_options(MachineClass *mc) 4738 { 4739 /* Defaults for the latest behaviour inherited from the base class */ 4740 } 4741 4742 DEFINE_SPAPR_MACHINE_AS_LATEST(10, 0); 4743 4744 /* 4745 * pseries-9.2 4746 */ 4747 static void spapr_machine_9_2_class_options(MachineClass *mc) 4748 { 4749 spapr_machine_10_0_class_options(mc); 4750 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len); 4751 } 4752 4753 DEFINE_SPAPR_MACHINE(9, 2); 4754 4755 /* 4756 * pseries-9.1 4757 */ 4758 static void spapr_machine_9_1_class_options(MachineClass *mc) 4759 { 4760 spapr_machine_9_2_class_options(mc); 4761 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); 4762 } 4763 4764 DEFINE_SPAPR_MACHINE(9, 1); 4765 4766 /* 4767 * pseries-9.0 4768 */ 4769 static void spapr_machine_9_0_class_options(MachineClass *mc) 4770 { 4771 spapr_machine_9_1_class_options(mc); 4772 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 4773 } 4774 4775 DEFINE_SPAPR_MACHINE(9, 0); 4776 4777 /* 4778 * pseries-8.2 4779 */ 4780 static void spapr_machine_8_2_class_options(MachineClass *mc) 4781 { 4782 spapr_machine_9_0_class_options(mc); 4783 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4784 } 4785 4786 DEFINE_SPAPR_MACHINE(8, 2); 4787 4788 /* 4789 * pseries-8.1 4790 */ 4791 static void spapr_machine_8_1_class_options(MachineClass *mc) 4792 { 4793 spapr_machine_8_2_class_options(mc); 4794 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4795 } 4796 4797 DEFINE_SPAPR_MACHINE(8, 1); 4798 4799 /* 4800 * pseries-8.0 4801 */ 4802 static void spapr_machine_8_0_class_options(MachineClass *mc) 4803 { 4804 spapr_machine_8_1_class_options(mc); 4805 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4806 } 4807 4808 DEFINE_SPAPR_MACHINE(8, 0); 4809 4810 /* 4811 * pseries-7.2 4812 */ 4813 static void spapr_machine_7_2_class_options(MachineClass *mc) 4814 { 4815 spapr_machine_8_0_class_options(mc); 4816 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4817 } 4818 4819 DEFINE_SPAPR_MACHINE(7, 2); 4820 4821 /* 4822 * pseries-7.1 4823 */ 4824 static void spapr_machine_7_1_class_options(MachineClass *mc) 4825 { 4826 spapr_machine_7_2_class_options(mc); 4827 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4828 } 4829 4830 DEFINE_SPAPR_MACHINE(7, 1); 4831 4832 /* 4833 * pseries-7.0 4834 */ 4835 static void spapr_machine_7_0_class_options(MachineClass *mc) 4836 { 4837 spapr_machine_7_1_class_options(mc); 4838 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4839 } 4840 4841 DEFINE_SPAPR_MACHINE(7, 0); 4842 4843 /* 4844 * pseries-6.2 4845 */ 4846 static void spapr_machine_6_2_class_options(MachineClass *mc) 4847 { 4848 spapr_machine_7_0_class_options(mc); 4849 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4850 } 4851 4852 DEFINE_SPAPR_MACHINE(6, 2); 4853 4854 /* 4855 * pseries-6.1 4856 */ 4857 static void spapr_machine_6_1_class_options(MachineClass *mc) 4858 { 4859 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4860 4861 spapr_machine_6_2_class_options(mc); 4862 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4863 smc->pre_6_2_numa_affinity = true; 4864 mc->smp_props.prefer_sockets = true; 4865 } 4866 4867 DEFINE_SPAPR_MACHINE(6, 1); 4868 4869 /* 4870 * pseries-6.0 4871 */ 4872 static void spapr_machine_6_0_class_options(MachineClass *mc) 4873 { 4874 spapr_machine_6_1_class_options(mc); 4875 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4876 } 4877 4878 DEFINE_SPAPR_MACHINE(6, 0); 4879 4880 /* 4881 * pseries-5.2 4882 */ 4883 static void spapr_machine_5_2_class_options(MachineClass *mc) 4884 { 4885 spapr_machine_6_0_class_options(mc); 4886 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4887 } 4888 4889 DEFINE_SPAPR_MACHINE(5, 2); 4890 4891 /* 4892 * pseries-5.1 4893 */ 4894 static void spapr_machine_5_1_class_options(MachineClass *mc) 4895 { 4896 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4897 4898 spapr_machine_5_2_class_options(mc); 4899 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4900 smc->pre_5_2_numa_associativity = true; 4901 } 4902 4903 DEFINE_SPAPR_MACHINE(5, 1); 4904 4905 /* 4906 * pseries-5.0 4907 */ 4908 static void spapr_machine_5_0_class_options(MachineClass *mc) 4909 { 4910 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4911 static GlobalProperty compat[] = { 4912 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4913 }; 4914 4915 spapr_machine_5_1_class_options(mc); 4916 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4917 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4918 mc->numa_mem_supported = true; 4919 smc->pre_5_1_assoc_refpoints = true; 4920 } 4921 4922 DEFINE_SPAPR_MACHINE(5, 0); 4923 4924 /* 4925 * pseries-4.2 4926 */ 4927 static void spapr_machine_4_2_class_options(MachineClass *mc) 4928 { 4929 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4930 4931 spapr_machine_5_0_class_options(mc); 4932 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4933 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4934 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4935 smc->rma_limit = 16 * GiB; 4936 mc->nvdimm_supported = false; 4937 } 4938 4939 DEFINE_SPAPR_MACHINE(4, 2); 4940 4941 /* 4942 * pseries-4.1 4943 */ 4944 static void spapr_machine_4_1_class_options(MachineClass *mc) 4945 { 4946 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4947 static GlobalProperty compat[] = { 4948 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4949 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4950 }; 4951 4952 spapr_machine_4_2_class_options(mc); 4953 smc->linux_pci_probe = false; 4954 smc->smp_threads_vsmt = false; 4955 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4956 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4957 } 4958 4959 DEFINE_SPAPR_MACHINE(4, 1); 4960 4961 /* 4962 * pseries-4.0 4963 */ 4964 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4965 uint64_t *buid, hwaddr *pio, 4966 hwaddr *mmio32, hwaddr *mmio64, 4967 unsigned n_dma, uint32_t *liobns, Error **errp) 4968 { 4969 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4970 liobns, errp)) { 4971 return false; 4972 } 4973 return true; 4974 } 4975 static void spapr_machine_4_0_class_options(MachineClass *mc) 4976 { 4977 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4978 4979 spapr_machine_4_1_class_options(mc); 4980 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4981 smc->phb_placement = phb_placement_4_0; 4982 smc->irq = &spapr_irq_xics; 4983 smc->pre_4_1_migration = true; 4984 } 4985 4986 DEFINE_SPAPR_MACHINE(4, 0); 4987 4988 /* 4989 * pseries-3.1 4990 */ 4991 static void spapr_machine_3_1_class_options(MachineClass *mc) 4992 { 4993 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4994 4995 spapr_machine_4_0_class_options(mc); 4996 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4997 4998 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4999 smc->update_dt_enabled = false; 5000 smc->dr_phb_enabled = false; 5001 smc->broken_host_serial_model = true; 5002 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5003 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5004 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5005 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5006 } 5007 5008 DEFINE_SPAPR_MACHINE(3, 1); 5009 5010 /* 5011 * pseries-3.0 5012 */ 5013 5014 static void spapr_machine_3_0_class_options(MachineClass *mc) 5015 { 5016 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5017 5018 spapr_machine_3_1_class_options(mc); 5019 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5020 5021 smc->legacy_irq_allocation = true; 5022 smc->nr_xirqs = 0x400; 5023 smc->irq = &spapr_irq_xics_legacy; 5024 } 5025 5026 DEFINE_SPAPR_MACHINE(3, 0); 5027 5028 static void spapr_machine_register_types(void) 5029 { 5030 type_register_static(&spapr_machine_info); 5031 } 5032 5033 type_init(spapr_machine_register_types) 5034