1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define FDT_MAX_SIZE 0x100000 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 /* Populate the "ibm,pa-features" property */ 221 static void spapr_populate_pa_features(SpaprMachineState *spapr, 222 PowerPCCPU *cpu, 223 void *fdt, int offset) 224 { 225 uint8_t pa_features_206[] = { 6, 0, 226 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 227 uint8_t pa_features_207[] = { 24, 0, 228 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 230 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 232 uint8_t pa_features_300[] = { 66, 0, 233 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 234 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 235 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 236 /* 6: DS207 */ 237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 238 /* 16: Vector */ 239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 240 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 242 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 244 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 245 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 246 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 248 /* 42: PM, 44: PC RA, 46: SC vec'd */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 250 /* 48: SIMD, 50: QP BFP, 52: String */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 252 /* 54: DecFP, 56: DecI, 58: SHA */ 253 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 254 /* 60: NM atomic, 62: RNG */ 255 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 256 }; 257 uint8_t *pa_features = NULL; 258 size_t pa_size; 259 260 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 261 pa_features = pa_features_206; 262 pa_size = sizeof(pa_features_206); 263 } 264 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 265 pa_features = pa_features_207; 266 pa_size = sizeof(pa_features_207); 267 } 268 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 269 pa_features = pa_features_300; 270 pa_size = sizeof(pa_features_300); 271 } 272 if (!pa_features) { 273 return; 274 } 275 276 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 277 /* 278 * Note: we keep CI large pages off by default because a 64K capable 279 * guest provisioned with large pages might otherwise try to map a qemu 280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 281 * even if that qemu runs on a 4k host. 282 * We dd this bit back here if we are confident this is not an issue 283 */ 284 pa_features[3] |= 0x20; 285 } 286 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 287 pa_features[24] |= 0x80; /* Transactional memory support */ 288 } 289 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 290 /* Workaround for broken kernels that attempt (guest) radix 291 * mode when they can't handle it, if they see the radix bit set 292 * in pa-features. So hide it from them. */ 293 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 294 } 295 296 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 297 } 298 299 static hwaddr spapr_node0_size(MachineState *machine) 300 { 301 if (machine->numa_state->num_nodes) { 302 int i; 303 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 304 if (machine->numa_state->nodes[i].node_mem) { 305 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 306 machine->ram_size); 307 } 308 } 309 } 310 return machine->ram_size; 311 } 312 313 static void add_str(GString *s, const gchar *s1) 314 { 315 g_string_append_len(s, s1, strlen(s1) + 1); 316 } 317 318 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 319 hwaddr size) 320 { 321 uint32_t associativity[] = { 322 cpu_to_be32(0x4), /* length */ 323 cpu_to_be32(0x0), cpu_to_be32(0x0), 324 cpu_to_be32(0x0), cpu_to_be32(nodeid) 325 }; 326 char mem_name[32]; 327 uint64_t mem_reg_property[2]; 328 int off; 329 330 mem_reg_property[0] = cpu_to_be64(start); 331 mem_reg_property[1] = cpu_to_be64(size); 332 333 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 334 off = fdt_add_subnode(fdt, 0, mem_name); 335 _FDT(off); 336 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 337 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 338 sizeof(mem_reg_property)))); 339 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 340 sizeof(associativity)))); 341 return off; 342 } 343 344 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 345 { 346 MachineState *machine = MACHINE(spapr); 347 hwaddr mem_start, node_size; 348 int i, nb_nodes = machine->numa_state->num_nodes; 349 NodeInfo *nodes = machine->numa_state->nodes; 350 351 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 352 if (!nodes[i].node_mem) { 353 continue; 354 } 355 if (mem_start >= machine->ram_size) { 356 node_size = 0; 357 } else { 358 node_size = nodes[i].node_mem; 359 if (node_size > machine->ram_size - mem_start) { 360 node_size = machine->ram_size - mem_start; 361 } 362 } 363 if (!mem_start) { 364 /* spapr_machine_init() checks for rma_size <= node0_size 365 * already */ 366 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 367 mem_start += spapr->rma_size; 368 node_size -= spapr->rma_size; 369 } 370 for ( ; node_size; ) { 371 hwaddr sizetmp = pow2floor(node_size); 372 373 /* mem_start != 0 here */ 374 if (ctzl(mem_start) < ctzl(sizetmp)) { 375 sizetmp = 1ULL << ctzl(mem_start); 376 } 377 378 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 379 node_size -= sizetmp; 380 mem_start += sizetmp; 381 } 382 } 383 384 return 0; 385 } 386 387 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 388 SpaprMachineState *spapr) 389 { 390 MachineState *ms = MACHINE(spapr); 391 PowerPCCPU *cpu = POWERPC_CPU(cs); 392 CPUPPCState *env = &cpu->env; 393 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 394 int index = spapr_get_vcpu_id(cpu); 395 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 396 0xffffffff, 0xffffffff}; 397 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 398 : SPAPR_TIMEBASE_FREQ; 399 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 400 uint32_t page_sizes_prop[64]; 401 size_t page_sizes_prop_size; 402 unsigned int smp_threads = ms->smp.threads; 403 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 404 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 405 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 406 SpaprDrc *drc; 407 int drc_index; 408 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 409 int i; 410 411 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 412 if (drc) { 413 drc_index = spapr_drc_index(drc); 414 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 415 } 416 417 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 418 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 419 420 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 421 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 422 env->dcache_line_size))); 423 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 424 env->dcache_line_size))); 425 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 426 env->icache_line_size))); 427 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 428 env->icache_line_size))); 429 430 if (pcc->l1_dcache_size) { 431 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 432 pcc->l1_dcache_size))); 433 } else { 434 warn_report("Unknown L1 dcache size for cpu"); 435 } 436 if (pcc->l1_icache_size) { 437 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 438 pcc->l1_icache_size))); 439 } else { 440 warn_report("Unknown L1 icache size for cpu"); 441 } 442 443 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 445 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 447 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 448 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 449 450 if (env->spr_cb[SPR_PURR].oea_read) { 451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 452 } 453 if (env->spr_cb[SPR_SPURR].oea_read) { 454 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 455 } 456 457 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 458 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 459 segs, sizeof(segs)))); 460 } 461 462 /* Advertise VSX (vector extensions) if available 463 * 1 == VMX / Altivec available 464 * 2 == VSX available 465 * 466 * Only CPUs for which we create core types in spapr_cpu_core.c 467 * are possible, and all of those have VMX */ 468 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 469 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 470 } else { 471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 472 } 473 474 /* Advertise DFP (Decimal Floating Point) if available 475 * 0 / no property == no DFP 476 * 1 == DFP available */ 477 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 479 } 480 481 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 482 sizeof(page_sizes_prop)); 483 if (page_sizes_prop_size) { 484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 485 page_sizes_prop, page_sizes_prop_size))); 486 } 487 488 spapr_populate_pa_features(spapr, cpu, fdt, offset); 489 490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 491 cs->cpu_index / vcpus_per_socket))); 492 493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 494 pft_size_prop, sizeof(pft_size_prop)))); 495 496 if (ms->numa_state->num_nodes > 1) { 497 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 498 } 499 500 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 501 502 if (pcc->radix_page_info) { 503 for (i = 0; i < pcc->radix_page_info->count; i++) { 504 radix_AP_encodings[i] = 505 cpu_to_be32(pcc->radix_page_info->entries[i]); 506 } 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 508 radix_AP_encodings, 509 pcc->radix_page_info->count * 510 sizeof(radix_AP_encodings[0])))); 511 } 512 513 /* 514 * We set this property to let the guest know that it can use the large 515 * decrementer and its width in bits. 516 */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 518 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 519 pcc->lrg_decr_bits))); 520 } 521 522 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 523 { 524 CPUState **rev; 525 CPUState *cs; 526 int n_cpus; 527 int cpus_offset; 528 char *nodename; 529 int i; 530 531 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 532 _FDT(cpus_offset); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 534 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 535 536 /* 537 * We walk the CPUs in reverse order to ensure that CPU DT nodes 538 * created by fdt_add_subnode() end up in the right order in FDT 539 * for the guest kernel the enumerate the CPUs correctly. 540 * 541 * The CPU list cannot be traversed in reverse order, so we need 542 * to do extra work. 543 */ 544 n_cpus = 0; 545 rev = NULL; 546 CPU_FOREACH(cs) { 547 rev = g_renew(CPUState *, rev, n_cpus + 1); 548 rev[n_cpus++] = cs; 549 } 550 551 for (i = n_cpus - 1; i >= 0; i--) { 552 CPUState *cs = rev[i]; 553 PowerPCCPU *cpu = POWERPC_CPU(cs); 554 int index = spapr_get_vcpu_id(cpu); 555 DeviceClass *dc = DEVICE_GET_CLASS(cs); 556 int offset; 557 558 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 559 continue; 560 } 561 562 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 563 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 564 g_free(nodename); 565 _FDT(offset); 566 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 567 } 568 569 g_free(rev); 570 } 571 572 static int spapr_rng_populate_dt(void *fdt) 573 { 574 int node; 575 int ret; 576 577 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 578 if (node <= 0) { 579 return -1; 580 } 581 ret = fdt_setprop_string(fdt, node, "device_type", 582 "ibm,platform-facilities"); 583 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 584 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 585 586 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 587 if (node <= 0) { 588 return -1; 589 } 590 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 591 592 return ret ? -1 : 0; 593 } 594 595 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 596 { 597 MemoryDeviceInfoList *info; 598 599 for (info = list; info; info = info->next) { 600 MemoryDeviceInfo *value = info->value; 601 602 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 603 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 604 605 if (addr >= pcdimm_info->addr && 606 addr < (pcdimm_info->addr + pcdimm_info->size)) { 607 return pcdimm_info->node; 608 } 609 } 610 } 611 612 return -1; 613 } 614 615 struct sPAPRDrconfCellV2 { 616 uint32_t seq_lmbs; 617 uint64_t base_addr; 618 uint32_t drc_index; 619 uint32_t aa_index; 620 uint32_t flags; 621 } QEMU_PACKED; 622 623 typedef struct DrconfCellQueue { 624 struct sPAPRDrconfCellV2 cell; 625 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 626 } DrconfCellQueue; 627 628 static DrconfCellQueue * 629 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 630 uint32_t drc_index, uint32_t aa_index, 631 uint32_t flags) 632 { 633 DrconfCellQueue *elem; 634 635 elem = g_malloc0(sizeof(*elem)); 636 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 637 elem->cell.base_addr = cpu_to_be64(base_addr); 638 elem->cell.drc_index = cpu_to_be32(drc_index); 639 elem->cell.aa_index = cpu_to_be32(aa_index); 640 elem->cell.flags = cpu_to_be32(flags); 641 642 return elem; 643 } 644 645 /* ibm,dynamic-memory-v2 */ 646 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 647 int offset, MemoryDeviceInfoList *dimms) 648 { 649 MachineState *machine = MACHINE(spapr); 650 uint8_t *int_buf, *cur_index; 651 int ret; 652 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 653 uint64_t addr, cur_addr, size; 654 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 655 uint64_t mem_end = machine->device_memory->base + 656 memory_region_size(&machine->device_memory->mr); 657 uint32_t node, buf_len, nr_entries = 0; 658 SpaprDrc *drc; 659 DrconfCellQueue *elem, *next; 660 MemoryDeviceInfoList *info; 661 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 662 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 663 664 /* Entry to cover RAM and the gap area */ 665 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 666 SPAPR_LMB_FLAGS_RESERVED | 667 SPAPR_LMB_FLAGS_DRC_INVALID); 668 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 669 nr_entries++; 670 671 cur_addr = machine->device_memory->base; 672 for (info = dimms; info; info = info->next) { 673 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 674 675 addr = di->addr; 676 size = di->size; 677 node = di->node; 678 679 /* 680 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 681 * area is marked hotpluggable in the next iteration for the bigger 682 * chunk including the NVDIMM occupied area. 683 */ 684 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 685 continue; 686 687 /* Entry for hot-pluggable area */ 688 if (cur_addr < addr) { 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 692 cur_addr, spapr_drc_index(drc), -1, 0); 693 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 694 nr_entries++; 695 } 696 697 /* Entry for DIMM */ 698 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 699 g_assert(drc); 700 elem = spapr_get_drconf_cell(size / lmb_size, addr, 701 spapr_drc_index(drc), node, 702 SPAPR_LMB_FLAGS_ASSIGNED); 703 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 704 nr_entries++; 705 cur_addr = addr + size; 706 } 707 708 /* Entry for remaining hotpluggable area */ 709 if (cur_addr < mem_end) { 710 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 711 g_assert(drc); 712 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 713 cur_addr, spapr_drc_index(drc), -1, 0); 714 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 715 nr_entries++; 716 } 717 718 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 719 int_buf = cur_index = g_malloc0(buf_len); 720 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 721 cur_index += sizeof(nr_entries); 722 723 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 724 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 725 cur_index += sizeof(elem->cell); 726 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 727 g_free(elem); 728 } 729 730 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 731 g_free(int_buf); 732 if (ret < 0) { 733 return -1; 734 } 735 return 0; 736 } 737 738 /* ibm,dynamic-memory */ 739 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 740 int offset, MemoryDeviceInfoList *dimms) 741 { 742 MachineState *machine = MACHINE(spapr); 743 int i, ret; 744 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 745 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 746 uint32_t nr_lmbs = (machine->device_memory->base + 747 memory_region_size(&machine->device_memory->mr)) / 748 lmb_size; 749 uint32_t *int_buf, *cur_index, buf_len; 750 751 /* 752 * Allocate enough buffer size to fit in ibm,dynamic-memory 753 */ 754 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 755 cur_index = int_buf = g_malloc0(buf_len); 756 int_buf[0] = cpu_to_be32(nr_lmbs); 757 cur_index++; 758 for (i = 0; i < nr_lmbs; i++) { 759 uint64_t addr = i * lmb_size; 760 uint32_t *dynamic_memory = cur_index; 761 762 if (i >= device_lmb_start) { 763 SpaprDrc *drc; 764 765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 766 g_assert(drc); 767 768 dynamic_memory[0] = cpu_to_be32(addr >> 32); 769 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 770 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 771 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 772 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 773 if (memory_region_present(get_system_memory(), addr)) { 774 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 775 } else { 776 dynamic_memory[5] = cpu_to_be32(0); 777 } 778 } else { 779 /* 780 * LMB information for RMA, boot time RAM and gap b/n RAM and 781 * device memory region -- all these are marked as reserved 782 * and as having no valid DRC. 783 */ 784 dynamic_memory[0] = cpu_to_be32(addr >> 32); 785 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 786 dynamic_memory[2] = cpu_to_be32(0); 787 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 788 dynamic_memory[4] = cpu_to_be32(-1); 789 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 790 SPAPR_LMB_FLAGS_DRC_INVALID); 791 } 792 793 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 794 } 795 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 796 g_free(int_buf); 797 if (ret < 0) { 798 return -1; 799 } 800 return 0; 801 } 802 803 /* 804 * Adds ibm,dynamic-reconfiguration-memory node. 805 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 806 * of this device tree node. 807 */ 808 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 809 { 810 MachineState *machine = MACHINE(spapr); 811 int nb_numa_nodes = machine->numa_state->num_nodes; 812 int ret, i, offset; 813 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 814 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 815 uint32_t *int_buf, *cur_index, buf_len; 816 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 817 MemoryDeviceInfoList *dimms = NULL; 818 819 /* 820 * Don't create the node if there is no device memory 821 */ 822 if (machine->ram_size == machine->maxram_size) { 823 return 0; 824 } 825 826 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 827 828 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 829 sizeof(prop_lmb_size)); 830 if (ret < 0) { 831 return ret; 832 } 833 834 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 835 if (ret < 0) { 836 return ret; 837 } 838 839 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 840 if (ret < 0) { 841 return ret; 842 } 843 844 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 845 dimms = qmp_memory_device_list(); 846 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 847 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 848 } else { 849 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 850 } 851 qapi_free_MemoryDeviceInfoList(dimms); 852 853 if (ret < 0) { 854 return ret; 855 } 856 857 /* ibm,associativity-lookup-arrays */ 858 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 859 cur_index = int_buf = g_malloc0(buf_len); 860 int_buf[0] = cpu_to_be32(nr_nodes); 861 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 862 cur_index += 2; 863 for (i = 0; i < nr_nodes; i++) { 864 uint32_t associativity[] = { 865 cpu_to_be32(0x0), 866 cpu_to_be32(0x0), 867 cpu_to_be32(0x0), 868 cpu_to_be32(i) 869 }; 870 memcpy(cur_index, associativity, sizeof(associativity)); 871 cur_index += 4; 872 } 873 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 874 (cur_index - int_buf) * sizeof(uint32_t)); 875 g_free(int_buf); 876 877 return ret; 878 } 879 880 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 881 SpaprOptionVector *ov5_updates) 882 { 883 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 884 int ret = 0, offset; 885 886 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 887 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 888 g_assert(smc->dr_lmb_enabled); 889 ret = spapr_populate_drconf_memory(spapr, fdt); 890 if (ret) { 891 return ret; 892 } 893 } 894 895 offset = fdt_path_offset(fdt, "/chosen"); 896 if (offset < 0) { 897 offset = fdt_add_subnode(fdt, 0, "chosen"); 898 if (offset < 0) { 899 return offset; 900 } 901 } 902 return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 903 "ibm,architecture-vec-5"); 904 } 905 906 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 907 { 908 MachineState *ms = MACHINE(spapr); 909 int rtas; 910 GString *hypertas = g_string_sized_new(256); 911 GString *qemu_hypertas = g_string_sized_new(256); 912 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 913 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 914 memory_region_size(&MACHINE(spapr)->device_memory->mr); 915 uint32_t lrdr_capacity[] = { 916 cpu_to_be32(max_device_addr >> 32), 917 cpu_to_be32(max_device_addr & 0xffffffff), 918 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 919 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 920 }; 921 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 922 uint32_t maxdomains[] = { 923 cpu_to_be32(4), 924 maxdomain, 925 maxdomain, 926 maxdomain, 927 cpu_to_be32(spapr->gpu_numa_id), 928 }; 929 930 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 931 932 /* hypertas */ 933 add_str(hypertas, "hcall-pft"); 934 add_str(hypertas, "hcall-term"); 935 add_str(hypertas, "hcall-dabr"); 936 add_str(hypertas, "hcall-interrupt"); 937 add_str(hypertas, "hcall-tce"); 938 add_str(hypertas, "hcall-vio"); 939 add_str(hypertas, "hcall-splpar"); 940 add_str(hypertas, "hcall-join"); 941 add_str(hypertas, "hcall-bulk"); 942 add_str(hypertas, "hcall-set-mode"); 943 add_str(hypertas, "hcall-sprg0"); 944 add_str(hypertas, "hcall-copy"); 945 add_str(hypertas, "hcall-debug"); 946 add_str(hypertas, "hcall-vphn"); 947 add_str(qemu_hypertas, "hcall-memop1"); 948 949 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 950 add_str(hypertas, "hcall-multi-tce"); 951 } 952 953 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 954 add_str(hypertas, "hcall-hpt-resize"); 955 } 956 957 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 958 hypertas->str, hypertas->len)); 959 g_string_free(hypertas, TRUE); 960 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 961 qemu_hypertas->str, qemu_hypertas->len)); 962 g_string_free(qemu_hypertas, TRUE); 963 964 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 965 refpoints, sizeof(refpoints))); 966 967 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 968 maxdomains, sizeof(maxdomains))); 969 970 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 971 RTAS_ERROR_LOG_MAX)); 972 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 973 RTAS_EVENT_SCAN_RATE)); 974 975 g_assert(msi_nonbroken); 976 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 977 978 /* 979 * According to PAPR, rtas ibm,os-term does not guarantee a return 980 * back to the guest cpu. 981 * 982 * While an additional ibm,extended-os-term property indicates 983 * that rtas call return will always occur. Set this property. 984 */ 985 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 986 987 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 988 lrdr_capacity, sizeof(lrdr_capacity))); 989 990 spapr_dt_rtas_tokens(fdt, rtas); 991 } 992 993 /* 994 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 995 * and the XIVE features that the guest may request and thus the valid 996 * values for bytes 23..26 of option vector 5: 997 */ 998 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 999 int chosen) 1000 { 1001 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1002 1003 char val[2 * 4] = { 1004 23, 0x00, /* XICS / XIVE mode */ 1005 24, 0x00, /* Hash/Radix, filled in below. */ 1006 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1007 26, 0x40, /* Radix options: GTSE == yes. */ 1008 }; 1009 1010 if (spapr->irq->xics && spapr->irq->xive) { 1011 val[1] = SPAPR_OV5_XIVE_BOTH; 1012 } else if (spapr->irq->xive) { 1013 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1014 } else { 1015 assert(spapr->irq->xics); 1016 val[1] = SPAPR_OV5_XIVE_LEGACY; 1017 } 1018 1019 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1020 first_ppc_cpu->compat_pvr)) { 1021 /* 1022 * If we're in a pre POWER9 compat mode then the guest should 1023 * do hash and use the legacy interrupt mode 1024 */ 1025 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1026 val[3] = 0x00; /* Hash */ 1027 } else if (kvm_enabled()) { 1028 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1029 val[3] = 0x80; /* OV5_MMU_BOTH */ 1030 } else if (kvmppc_has_cap_mmu_radix()) { 1031 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1032 } else { 1033 val[3] = 0x00; /* Hash */ 1034 } 1035 } else { 1036 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1037 val[3] = 0xC0; 1038 } 1039 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1040 val, sizeof(val))); 1041 } 1042 1043 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1044 { 1045 MachineState *machine = MACHINE(spapr); 1046 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1047 int chosen; 1048 const char *boot_device = machine->boot_order; 1049 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1050 size_t cb = 0; 1051 char *bootlist = get_boot_devices_list(&cb); 1052 1053 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1054 1055 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1056 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1057 machine->kernel_cmdline)); 1058 } 1059 if (spapr->initrd_size) { 1060 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1061 spapr->initrd_base)); 1062 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1063 spapr->initrd_base + spapr->initrd_size)); 1064 } 1065 1066 if (spapr->kernel_size) { 1067 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1068 cpu_to_be64(spapr->kernel_size) }; 1069 1070 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1071 &kprop, sizeof(kprop))); 1072 if (spapr->kernel_le) { 1073 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1074 } 1075 } 1076 if (boot_menu) { 1077 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1078 } 1079 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1080 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1081 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1082 1083 if (cb && bootlist) { 1084 int i; 1085 1086 for (i = 0; i < cb; i++) { 1087 if (bootlist[i] == '\n') { 1088 bootlist[i] = ' '; 1089 } 1090 } 1091 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1092 } 1093 1094 if (boot_device && strlen(boot_device)) { 1095 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1096 } 1097 1098 if (!spapr->has_graphics && stdout_path) { 1099 /* 1100 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1101 * kernel. New platforms should only use the "stdout-path" property. Set 1102 * the new property and continue using older property to remain 1103 * compatible with the existing firmware. 1104 */ 1105 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1106 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1107 } 1108 1109 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1110 if (smc->linux_pci_probe) { 1111 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1112 } 1113 1114 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1115 1116 g_free(stdout_path); 1117 g_free(bootlist); 1118 } 1119 1120 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1121 { 1122 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1123 * KVM to work under pHyp with some guest co-operation */ 1124 int hypervisor; 1125 uint8_t hypercall[16]; 1126 1127 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1128 /* indicate KVM hypercall interface */ 1129 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1130 if (kvmppc_has_cap_fixup_hcalls()) { 1131 /* 1132 * Older KVM versions with older guest kernels were broken 1133 * with the magic page, don't allow the guest to map it. 1134 */ 1135 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1136 sizeof(hypercall))) { 1137 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1138 hypercall, sizeof(hypercall))); 1139 } 1140 } 1141 } 1142 1143 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1144 { 1145 MachineState *machine = MACHINE(spapr); 1146 MachineClass *mc = MACHINE_GET_CLASS(machine); 1147 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1148 int ret; 1149 void *fdt; 1150 SpaprPhbState *phb; 1151 char *buf; 1152 1153 fdt = g_malloc0(space); 1154 _FDT((fdt_create_empty_tree(fdt, space))); 1155 1156 /* Root node */ 1157 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1158 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1159 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1160 1161 /* Guest UUID & Name*/ 1162 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1163 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1164 if (qemu_uuid_set) { 1165 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1166 } 1167 g_free(buf); 1168 1169 if (qemu_get_vm_name()) { 1170 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1171 qemu_get_vm_name())); 1172 } 1173 1174 /* Host Model & Serial Number */ 1175 if (spapr->host_model) { 1176 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1177 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1178 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1179 g_free(buf); 1180 } 1181 1182 if (spapr->host_serial) { 1183 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1184 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1185 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1186 g_free(buf); 1187 } 1188 1189 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1190 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1191 1192 /* /interrupt controller */ 1193 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1194 1195 ret = spapr_populate_memory(spapr, fdt); 1196 if (ret < 0) { 1197 error_report("couldn't setup memory nodes in fdt"); 1198 exit(1); 1199 } 1200 1201 /* /vdevice */ 1202 spapr_dt_vdevice(spapr->vio_bus, fdt); 1203 1204 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1205 ret = spapr_rng_populate_dt(fdt); 1206 if (ret < 0) { 1207 error_report("could not set up rng device in the fdt"); 1208 exit(1); 1209 } 1210 } 1211 1212 QLIST_FOREACH(phb, &spapr->phbs, list) { 1213 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1214 if (ret < 0) { 1215 error_report("couldn't setup PCI devices in fdt"); 1216 exit(1); 1217 } 1218 } 1219 1220 /* cpus */ 1221 spapr_populate_cpus_dt_node(fdt, spapr); 1222 1223 if (smc->dr_lmb_enabled) { 1224 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1225 } 1226 1227 if (mc->has_hotpluggable_cpus) { 1228 int offset = fdt_path_offset(fdt, "/cpus"); 1229 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1230 if (ret < 0) { 1231 error_report("Couldn't set up CPU DR device tree properties"); 1232 exit(1); 1233 } 1234 } 1235 1236 /* /event-sources */ 1237 spapr_dt_events(spapr, fdt); 1238 1239 /* /rtas */ 1240 spapr_dt_rtas(spapr, fdt); 1241 1242 /* /chosen */ 1243 if (reset) { 1244 spapr_dt_chosen(spapr, fdt); 1245 } 1246 1247 /* /hypervisor */ 1248 if (kvm_enabled()) { 1249 spapr_dt_hypervisor(spapr, fdt); 1250 } 1251 1252 /* Build memory reserve map */ 1253 if (reset) { 1254 if (spapr->kernel_size) { 1255 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1256 spapr->kernel_size))); 1257 } 1258 if (spapr->initrd_size) { 1259 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1260 spapr->initrd_size))); 1261 } 1262 } 1263 1264 /* ibm,client-architecture-support updates */ 1265 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1266 if (ret < 0) { 1267 error_report("couldn't setup CAS properties fdt"); 1268 exit(1); 1269 } 1270 1271 if (smc->dr_phb_enabled) { 1272 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1273 if (ret < 0) { 1274 error_report("Couldn't set up PHB DR device tree properties"); 1275 exit(1); 1276 } 1277 } 1278 1279 /* NVDIMM devices */ 1280 if (mc->nvdimm_supported) { 1281 spapr_dt_persistent_memory(fdt); 1282 } 1283 1284 return fdt; 1285 } 1286 1287 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1288 { 1289 SpaprMachineState *spapr = opaque; 1290 1291 return (addr & 0x0fffffff) + spapr->kernel_addr; 1292 } 1293 1294 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1295 PowerPCCPU *cpu) 1296 { 1297 CPUPPCState *env = &cpu->env; 1298 1299 /* The TCG path should also be holding the BQL at this point */ 1300 g_assert(qemu_mutex_iothread_locked()); 1301 1302 if (msr_pr) { 1303 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1304 env->gpr[3] = H_PRIVILEGE; 1305 } else { 1306 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1307 } 1308 } 1309 1310 struct LPCRSyncState { 1311 target_ulong value; 1312 target_ulong mask; 1313 }; 1314 1315 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1316 { 1317 struct LPCRSyncState *s = arg.host_ptr; 1318 PowerPCCPU *cpu = POWERPC_CPU(cs); 1319 CPUPPCState *env = &cpu->env; 1320 target_ulong lpcr; 1321 1322 cpu_synchronize_state(cs); 1323 lpcr = env->spr[SPR_LPCR]; 1324 lpcr &= ~s->mask; 1325 lpcr |= s->value; 1326 ppc_store_lpcr(cpu, lpcr); 1327 } 1328 1329 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1330 { 1331 CPUState *cs; 1332 struct LPCRSyncState s = { 1333 .value = value, 1334 .mask = mask 1335 }; 1336 CPU_FOREACH(cs) { 1337 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1338 } 1339 } 1340 1341 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1342 { 1343 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1344 1345 /* Copy PATE1:GR into PATE0:HR */ 1346 entry->dw0 = spapr->patb_entry & PATE0_HR; 1347 entry->dw1 = spapr->patb_entry; 1348 } 1349 1350 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1351 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1352 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1353 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1354 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1355 1356 /* 1357 * Get the fd to access the kernel htab, re-opening it if necessary 1358 */ 1359 static int get_htab_fd(SpaprMachineState *spapr) 1360 { 1361 Error *local_err = NULL; 1362 1363 if (spapr->htab_fd >= 0) { 1364 return spapr->htab_fd; 1365 } 1366 1367 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1368 if (spapr->htab_fd < 0) { 1369 error_report_err(local_err); 1370 } 1371 1372 return spapr->htab_fd; 1373 } 1374 1375 void close_htab_fd(SpaprMachineState *spapr) 1376 { 1377 if (spapr->htab_fd >= 0) { 1378 close(spapr->htab_fd); 1379 } 1380 spapr->htab_fd = -1; 1381 } 1382 1383 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1384 { 1385 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1386 1387 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1388 } 1389 1390 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1391 { 1392 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1393 1394 assert(kvm_enabled()); 1395 1396 if (!spapr->htab) { 1397 return 0; 1398 } 1399 1400 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1401 } 1402 1403 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1404 hwaddr ptex, int n) 1405 { 1406 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1407 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1408 1409 if (!spapr->htab) { 1410 /* 1411 * HTAB is controlled by KVM. Fetch into temporary buffer 1412 */ 1413 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1414 kvmppc_read_hptes(hptes, ptex, n); 1415 return hptes; 1416 } 1417 1418 /* 1419 * HTAB is controlled by QEMU. Just point to the internally 1420 * accessible PTEG. 1421 */ 1422 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1423 } 1424 1425 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1426 const ppc_hash_pte64_t *hptes, 1427 hwaddr ptex, int n) 1428 { 1429 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1430 1431 if (!spapr->htab) { 1432 g_free((void *)hptes); 1433 } 1434 1435 /* Nothing to do for qemu managed HPT */ 1436 } 1437 1438 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1439 uint64_t pte0, uint64_t pte1) 1440 { 1441 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1442 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1443 1444 if (!spapr->htab) { 1445 kvmppc_write_hpte(ptex, pte0, pte1); 1446 } else { 1447 if (pte0 & HPTE64_V_VALID) { 1448 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1449 /* 1450 * When setting valid, we write PTE1 first. This ensures 1451 * proper synchronization with the reading code in 1452 * ppc_hash64_pteg_search() 1453 */ 1454 smp_wmb(); 1455 stq_p(spapr->htab + offset, pte0); 1456 } else { 1457 stq_p(spapr->htab + offset, pte0); 1458 /* 1459 * When clearing it we set PTE0 first. This ensures proper 1460 * synchronization with the reading code in 1461 * ppc_hash64_pteg_search() 1462 */ 1463 smp_wmb(); 1464 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1465 } 1466 } 1467 } 1468 1469 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1470 uint64_t pte1) 1471 { 1472 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1473 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1474 1475 if (!spapr->htab) { 1476 /* There should always be a hash table when this is called */ 1477 error_report("spapr_hpte_set_c called with no hash table !"); 1478 return; 1479 } 1480 1481 /* The HW performs a non-atomic byte update */ 1482 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1483 } 1484 1485 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1486 uint64_t pte1) 1487 { 1488 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1489 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1490 1491 if (!spapr->htab) { 1492 /* There should always be a hash table when this is called */ 1493 error_report("spapr_hpte_set_r called with no hash table !"); 1494 return; 1495 } 1496 1497 /* The HW performs a non-atomic byte update */ 1498 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1499 } 1500 1501 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1502 { 1503 int shift; 1504 1505 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1506 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1507 * that's much more than is needed for Linux guests */ 1508 shift = ctz64(pow2ceil(ramsize)) - 7; 1509 shift = MAX(shift, 18); /* Minimum architected size */ 1510 shift = MIN(shift, 46); /* Maximum architected size */ 1511 return shift; 1512 } 1513 1514 void spapr_free_hpt(SpaprMachineState *spapr) 1515 { 1516 g_free(spapr->htab); 1517 spapr->htab = NULL; 1518 spapr->htab_shift = 0; 1519 close_htab_fd(spapr); 1520 } 1521 1522 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1523 Error **errp) 1524 { 1525 long rc; 1526 1527 /* Clean up any HPT info from a previous boot */ 1528 spapr_free_hpt(spapr); 1529 1530 rc = kvmppc_reset_htab(shift); 1531 if (rc < 0) { 1532 /* kernel-side HPT needed, but couldn't allocate one */ 1533 error_setg_errno(errp, errno, 1534 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1535 shift); 1536 /* This is almost certainly fatal, but if the caller really 1537 * wants to carry on with shift == 0, it's welcome to try */ 1538 } else if (rc > 0) { 1539 /* kernel-side HPT allocated */ 1540 if (rc != shift) { 1541 error_setg(errp, 1542 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1543 shift, rc); 1544 } 1545 1546 spapr->htab_shift = shift; 1547 spapr->htab = NULL; 1548 } else { 1549 /* kernel-side HPT not needed, allocate in userspace instead */ 1550 size_t size = 1ULL << shift; 1551 int i; 1552 1553 spapr->htab = qemu_memalign(size, size); 1554 if (!spapr->htab) { 1555 error_setg_errno(errp, errno, 1556 "Could not allocate HPT of order %d", shift); 1557 return; 1558 } 1559 1560 memset(spapr->htab, 0, size); 1561 spapr->htab_shift = shift; 1562 1563 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1564 DIRTY_HPTE(HPTE(spapr->htab, i)); 1565 } 1566 } 1567 /* We're setting up a hash table, so that means we're not radix */ 1568 spapr->patb_entry = 0; 1569 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1570 } 1571 1572 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1573 { 1574 int hpt_shift; 1575 1576 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1577 || (spapr->cas_reboot 1578 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1579 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1580 } else { 1581 uint64_t current_ram_size; 1582 1583 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1584 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1585 } 1586 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1587 1588 if (spapr->vrma_adjust) { 1589 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1590 1591 spapr->rma_size = MIN(spapr_node0_size(MACHINE(spapr)), vrma_limit); 1592 } 1593 } 1594 1595 static int spapr_reset_drcs(Object *child, void *opaque) 1596 { 1597 SpaprDrc *drc = 1598 (SpaprDrc *) object_dynamic_cast(child, 1599 TYPE_SPAPR_DR_CONNECTOR); 1600 1601 if (drc) { 1602 spapr_drc_reset(drc); 1603 } 1604 1605 return 0; 1606 } 1607 1608 static void spapr_machine_reset(MachineState *machine) 1609 { 1610 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1611 PowerPCCPU *first_ppc_cpu; 1612 hwaddr fdt_addr; 1613 void *fdt; 1614 int rc; 1615 1616 kvmppc_svm_off(&error_fatal); 1617 spapr_caps_apply(spapr); 1618 1619 first_ppc_cpu = POWERPC_CPU(first_cpu); 1620 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1621 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1622 spapr->max_compat_pvr)) { 1623 /* 1624 * If using KVM with radix mode available, VCPUs can be started 1625 * without a HPT because KVM will start them in radix mode. 1626 * Set the GR bit in PATE so that we know there is no HPT. 1627 */ 1628 spapr->patb_entry = PATE1_GR; 1629 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1630 } else { 1631 spapr_setup_hpt_and_vrma(spapr); 1632 } 1633 1634 qemu_devices_reset(); 1635 1636 /* 1637 * If this reset wasn't generated by CAS, we should reset our 1638 * negotiated options and start from scratch 1639 */ 1640 if (!spapr->cas_reboot) { 1641 spapr_ovec_cleanup(spapr->ov5_cas); 1642 spapr->ov5_cas = spapr_ovec_new(); 1643 1644 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1645 } 1646 1647 /* 1648 * This is fixing some of the default configuration of the XIVE 1649 * devices. To be called after the reset of the machine devices. 1650 */ 1651 spapr_irq_reset(spapr, &error_fatal); 1652 1653 /* 1654 * There is no CAS under qtest. Simulate one to please the code that 1655 * depends on spapr->ov5_cas. This is especially needed to test device 1656 * unplug, so we do that before resetting the DRCs. 1657 */ 1658 if (qtest_enabled()) { 1659 spapr_ovec_cleanup(spapr->ov5_cas); 1660 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1661 } 1662 1663 /* DRC reset may cause a device to be unplugged. This will cause troubles 1664 * if this device is used by another device (eg, a running vhost backend 1665 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1666 * situations, we reset DRCs after all devices have been reset. 1667 */ 1668 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1669 1670 spapr_clear_pending_events(spapr); 1671 1672 /* 1673 * We place the device tree and RTAS just below either the top of the RMA, 1674 * or just below 2GB, whichever is lower, so that it can be 1675 * processed with 32-bit real mode code if necessary 1676 */ 1677 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1678 1679 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1680 1681 rc = fdt_pack(fdt); 1682 1683 /* Should only fail if we've built a corrupted tree */ 1684 assert(rc == 0); 1685 1686 /* Load the fdt */ 1687 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1688 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1689 g_free(spapr->fdt_blob); 1690 spapr->fdt_size = fdt_totalsize(fdt); 1691 spapr->fdt_initial_size = spapr->fdt_size; 1692 spapr->fdt_blob = fdt; 1693 1694 /* Set up the entry state */ 1695 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1696 first_ppc_cpu->env.gpr[5] = 0; 1697 1698 spapr->cas_reboot = false; 1699 1700 spapr->mc_status = -1; 1701 spapr->guest_machine_check_addr = -1; 1702 1703 /* Signal all vCPUs waiting on this condition */ 1704 qemu_cond_broadcast(&spapr->mc_delivery_cond); 1705 1706 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1707 } 1708 1709 static void spapr_create_nvram(SpaprMachineState *spapr) 1710 { 1711 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1712 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1713 1714 if (dinfo) { 1715 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1716 &error_fatal); 1717 } 1718 1719 qdev_init_nofail(dev); 1720 1721 spapr->nvram = (struct SpaprNvram *)dev; 1722 } 1723 1724 static void spapr_rtc_create(SpaprMachineState *spapr) 1725 { 1726 object_initialize_child(OBJECT(spapr), "rtc", 1727 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1728 &error_fatal, NULL); 1729 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1730 &error_fatal); 1731 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1732 "date", &error_fatal); 1733 } 1734 1735 /* Returns whether we want to use VGA or not */ 1736 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1737 { 1738 switch (vga_interface_type) { 1739 case VGA_NONE: 1740 return false; 1741 case VGA_DEVICE: 1742 return true; 1743 case VGA_STD: 1744 case VGA_VIRTIO: 1745 case VGA_CIRRUS: 1746 return pci_vga_init(pci_bus) != NULL; 1747 default: 1748 error_setg(errp, 1749 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1750 return false; 1751 } 1752 } 1753 1754 static int spapr_pre_load(void *opaque) 1755 { 1756 int rc; 1757 1758 rc = spapr_caps_pre_load(opaque); 1759 if (rc) { 1760 return rc; 1761 } 1762 1763 return 0; 1764 } 1765 1766 static int spapr_post_load(void *opaque, int version_id) 1767 { 1768 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1769 int err = 0; 1770 1771 err = spapr_caps_post_migration(spapr); 1772 if (err) { 1773 return err; 1774 } 1775 1776 /* 1777 * In earlier versions, there was no separate qdev for the PAPR 1778 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1779 * So when migrating from those versions, poke the incoming offset 1780 * value into the RTC device 1781 */ 1782 if (version_id < 3) { 1783 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1784 if (err) { 1785 return err; 1786 } 1787 } 1788 1789 if (kvm_enabled() && spapr->patb_entry) { 1790 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1791 bool radix = !!(spapr->patb_entry & PATE1_GR); 1792 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1793 1794 /* 1795 * Update LPCR:HR and UPRT as they may not be set properly in 1796 * the stream 1797 */ 1798 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1799 LPCR_HR | LPCR_UPRT); 1800 1801 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1802 if (err) { 1803 error_report("Process table config unsupported by the host"); 1804 return -EINVAL; 1805 } 1806 } 1807 1808 err = spapr_irq_post_load(spapr, version_id); 1809 if (err) { 1810 return err; 1811 } 1812 1813 return err; 1814 } 1815 1816 static int spapr_pre_save(void *opaque) 1817 { 1818 int rc; 1819 1820 rc = spapr_caps_pre_save(opaque); 1821 if (rc) { 1822 return rc; 1823 } 1824 1825 return 0; 1826 } 1827 1828 static bool version_before_3(void *opaque, int version_id) 1829 { 1830 return version_id < 3; 1831 } 1832 1833 static bool spapr_pending_events_needed(void *opaque) 1834 { 1835 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1836 return !QTAILQ_EMPTY(&spapr->pending_events); 1837 } 1838 1839 static const VMStateDescription vmstate_spapr_event_entry = { 1840 .name = "spapr_event_log_entry", 1841 .version_id = 1, 1842 .minimum_version_id = 1, 1843 .fields = (VMStateField[]) { 1844 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1845 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1846 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1847 NULL, extended_length), 1848 VMSTATE_END_OF_LIST() 1849 }, 1850 }; 1851 1852 static const VMStateDescription vmstate_spapr_pending_events = { 1853 .name = "spapr_pending_events", 1854 .version_id = 1, 1855 .minimum_version_id = 1, 1856 .needed = spapr_pending_events_needed, 1857 .fields = (VMStateField[]) { 1858 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1859 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1860 VMSTATE_END_OF_LIST() 1861 }, 1862 }; 1863 1864 static bool spapr_ov5_cas_needed(void *opaque) 1865 { 1866 SpaprMachineState *spapr = opaque; 1867 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1868 bool cas_needed; 1869 1870 /* Prior to the introduction of SpaprOptionVector, we had two option 1871 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1872 * Both of these options encode machine topology into the device-tree 1873 * in such a way that the now-booted OS should still be able to interact 1874 * appropriately with QEMU regardless of what options were actually 1875 * negotiatied on the source side. 1876 * 1877 * As such, we can avoid migrating the CAS-negotiated options if these 1878 * are the only options available on the current machine/platform. 1879 * Since these are the only options available for pseries-2.7 and 1880 * earlier, this allows us to maintain old->new/new->old migration 1881 * compatibility. 1882 * 1883 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1884 * via default pseries-2.8 machines and explicit command-line parameters. 1885 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1886 * of the actual CAS-negotiated values to continue working properly. For 1887 * example, availability of memory unplug depends on knowing whether 1888 * OV5_HP_EVT was negotiated via CAS. 1889 * 1890 * Thus, for any cases where the set of available CAS-negotiatable 1891 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1892 * include the CAS-negotiated options in the migration stream, unless 1893 * if they affect boot time behaviour only. 1894 */ 1895 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1896 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1897 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1898 1899 /* We need extra information if we have any bits outside the mask 1900 * defined above */ 1901 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1902 1903 spapr_ovec_cleanup(ov5_mask); 1904 1905 return cas_needed; 1906 } 1907 1908 static const VMStateDescription vmstate_spapr_ov5_cas = { 1909 .name = "spapr_option_vector_ov5_cas", 1910 .version_id = 1, 1911 .minimum_version_id = 1, 1912 .needed = spapr_ov5_cas_needed, 1913 .fields = (VMStateField[]) { 1914 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1915 vmstate_spapr_ovec, SpaprOptionVector), 1916 VMSTATE_END_OF_LIST() 1917 }, 1918 }; 1919 1920 static bool spapr_patb_entry_needed(void *opaque) 1921 { 1922 SpaprMachineState *spapr = opaque; 1923 1924 return !!spapr->patb_entry; 1925 } 1926 1927 static const VMStateDescription vmstate_spapr_patb_entry = { 1928 .name = "spapr_patb_entry", 1929 .version_id = 1, 1930 .minimum_version_id = 1, 1931 .needed = spapr_patb_entry_needed, 1932 .fields = (VMStateField[]) { 1933 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1934 VMSTATE_END_OF_LIST() 1935 }, 1936 }; 1937 1938 static bool spapr_irq_map_needed(void *opaque) 1939 { 1940 SpaprMachineState *spapr = opaque; 1941 1942 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1943 } 1944 1945 static const VMStateDescription vmstate_spapr_irq_map = { 1946 .name = "spapr_irq_map", 1947 .version_id = 1, 1948 .minimum_version_id = 1, 1949 .needed = spapr_irq_map_needed, 1950 .fields = (VMStateField[]) { 1951 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1952 VMSTATE_END_OF_LIST() 1953 }, 1954 }; 1955 1956 static bool spapr_dtb_needed(void *opaque) 1957 { 1958 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1959 1960 return smc->update_dt_enabled; 1961 } 1962 1963 static int spapr_dtb_pre_load(void *opaque) 1964 { 1965 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1966 1967 g_free(spapr->fdt_blob); 1968 spapr->fdt_blob = NULL; 1969 spapr->fdt_size = 0; 1970 1971 return 0; 1972 } 1973 1974 static const VMStateDescription vmstate_spapr_dtb = { 1975 .name = "spapr_dtb", 1976 .version_id = 1, 1977 .minimum_version_id = 1, 1978 .needed = spapr_dtb_needed, 1979 .pre_load = spapr_dtb_pre_load, 1980 .fields = (VMStateField[]) { 1981 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1982 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1983 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1984 fdt_size), 1985 VMSTATE_END_OF_LIST() 1986 }, 1987 }; 1988 1989 static bool spapr_fwnmi_needed(void *opaque) 1990 { 1991 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1992 1993 return spapr->guest_machine_check_addr != -1; 1994 } 1995 1996 static int spapr_fwnmi_pre_save(void *opaque) 1997 { 1998 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1999 2000 /* 2001 * Check if machine check handling is in progress and print a 2002 * warning message. 2003 */ 2004 if (spapr->mc_status != -1) { 2005 warn_report("A machine check is being handled during migration. The" 2006 "handler may run and log hardware error on the destination"); 2007 } 2008 2009 return 0; 2010 } 2011 2012 static const VMStateDescription vmstate_spapr_machine_check = { 2013 .name = "spapr_machine_check", 2014 .version_id = 1, 2015 .minimum_version_id = 1, 2016 .needed = spapr_fwnmi_needed, 2017 .pre_save = spapr_fwnmi_pre_save, 2018 .fields = (VMStateField[]) { 2019 VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), 2020 VMSTATE_INT32(mc_status, SpaprMachineState), 2021 VMSTATE_END_OF_LIST() 2022 }, 2023 }; 2024 2025 static const VMStateDescription vmstate_spapr = { 2026 .name = "spapr", 2027 .version_id = 3, 2028 .minimum_version_id = 1, 2029 .pre_load = spapr_pre_load, 2030 .post_load = spapr_post_load, 2031 .pre_save = spapr_pre_save, 2032 .fields = (VMStateField[]) { 2033 /* used to be @next_irq */ 2034 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2035 2036 /* RTC offset */ 2037 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2038 2039 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2040 VMSTATE_END_OF_LIST() 2041 }, 2042 .subsections = (const VMStateDescription*[]) { 2043 &vmstate_spapr_ov5_cas, 2044 &vmstate_spapr_patb_entry, 2045 &vmstate_spapr_pending_events, 2046 &vmstate_spapr_cap_htm, 2047 &vmstate_spapr_cap_vsx, 2048 &vmstate_spapr_cap_dfp, 2049 &vmstate_spapr_cap_cfpc, 2050 &vmstate_spapr_cap_sbbc, 2051 &vmstate_spapr_cap_ibs, 2052 &vmstate_spapr_cap_hpt_maxpagesize, 2053 &vmstate_spapr_irq_map, 2054 &vmstate_spapr_cap_nested_kvm_hv, 2055 &vmstate_spapr_dtb, 2056 &vmstate_spapr_cap_large_decr, 2057 &vmstate_spapr_cap_ccf_assist, 2058 &vmstate_spapr_cap_fwnmi, 2059 &vmstate_spapr_machine_check, 2060 NULL 2061 } 2062 }; 2063 2064 static int htab_save_setup(QEMUFile *f, void *opaque) 2065 { 2066 SpaprMachineState *spapr = opaque; 2067 2068 /* "Iteration" header */ 2069 if (!spapr->htab_shift) { 2070 qemu_put_be32(f, -1); 2071 } else { 2072 qemu_put_be32(f, spapr->htab_shift); 2073 } 2074 2075 if (spapr->htab) { 2076 spapr->htab_save_index = 0; 2077 spapr->htab_first_pass = true; 2078 } else { 2079 if (spapr->htab_shift) { 2080 assert(kvm_enabled()); 2081 } 2082 } 2083 2084 2085 return 0; 2086 } 2087 2088 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2089 int chunkstart, int n_valid, int n_invalid) 2090 { 2091 qemu_put_be32(f, chunkstart); 2092 qemu_put_be16(f, n_valid); 2093 qemu_put_be16(f, n_invalid); 2094 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2095 HASH_PTE_SIZE_64 * n_valid); 2096 } 2097 2098 static void htab_save_end_marker(QEMUFile *f) 2099 { 2100 qemu_put_be32(f, 0); 2101 qemu_put_be16(f, 0); 2102 qemu_put_be16(f, 0); 2103 } 2104 2105 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2106 int64_t max_ns) 2107 { 2108 bool has_timeout = max_ns != -1; 2109 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2110 int index = spapr->htab_save_index; 2111 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2112 2113 assert(spapr->htab_first_pass); 2114 2115 do { 2116 int chunkstart; 2117 2118 /* Consume invalid HPTEs */ 2119 while ((index < htabslots) 2120 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2121 CLEAN_HPTE(HPTE(spapr->htab, index)); 2122 index++; 2123 } 2124 2125 /* Consume valid HPTEs */ 2126 chunkstart = index; 2127 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2128 && HPTE_VALID(HPTE(spapr->htab, index))) { 2129 CLEAN_HPTE(HPTE(spapr->htab, index)); 2130 index++; 2131 } 2132 2133 if (index > chunkstart) { 2134 int n_valid = index - chunkstart; 2135 2136 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2137 2138 if (has_timeout && 2139 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2140 break; 2141 } 2142 } 2143 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2144 2145 if (index >= htabslots) { 2146 assert(index == htabslots); 2147 index = 0; 2148 spapr->htab_first_pass = false; 2149 } 2150 spapr->htab_save_index = index; 2151 } 2152 2153 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2154 int64_t max_ns) 2155 { 2156 bool final = max_ns < 0; 2157 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2158 int examined = 0, sent = 0; 2159 int index = spapr->htab_save_index; 2160 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2161 2162 assert(!spapr->htab_first_pass); 2163 2164 do { 2165 int chunkstart, invalidstart; 2166 2167 /* Consume non-dirty HPTEs */ 2168 while ((index < htabslots) 2169 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2170 index++; 2171 examined++; 2172 } 2173 2174 chunkstart = index; 2175 /* Consume valid dirty HPTEs */ 2176 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2177 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2178 && HPTE_VALID(HPTE(spapr->htab, index))) { 2179 CLEAN_HPTE(HPTE(spapr->htab, index)); 2180 index++; 2181 examined++; 2182 } 2183 2184 invalidstart = index; 2185 /* Consume invalid dirty HPTEs */ 2186 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2187 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2188 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2189 CLEAN_HPTE(HPTE(spapr->htab, index)); 2190 index++; 2191 examined++; 2192 } 2193 2194 if (index > chunkstart) { 2195 int n_valid = invalidstart - chunkstart; 2196 int n_invalid = index - invalidstart; 2197 2198 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2199 sent += index - chunkstart; 2200 2201 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2202 break; 2203 } 2204 } 2205 2206 if (examined >= htabslots) { 2207 break; 2208 } 2209 2210 if (index >= htabslots) { 2211 assert(index == htabslots); 2212 index = 0; 2213 } 2214 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2215 2216 if (index >= htabslots) { 2217 assert(index == htabslots); 2218 index = 0; 2219 } 2220 2221 spapr->htab_save_index = index; 2222 2223 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2224 } 2225 2226 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2227 #define MAX_KVM_BUF_SIZE 2048 2228 2229 static int htab_save_iterate(QEMUFile *f, void *opaque) 2230 { 2231 SpaprMachineState *spapr = opaque; 2232 int fd; 2233 int rc = 0; 2234 2235 /* Iteration header */ 2236 if (!spapr->htab_shift) { 2237 qemu_put_be32(f, -1); 2238 return 1; 2239 } else { 2240 qemu_put_be32(f, 0); 2241 } 2242 2243 if (!spapr->htab) { 2244 assert(kvm_enabled()); 2245 2246 fd = get_htab_fd(spapr); 2247 if (fd < 0) { 2248 return fd; 2249 } 2250 2251 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2252 if (rc < 0) { 2253 return rc; 2254 } 2255 } else if (spapr->htab_first_pass) { 2256 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2257 } else { 2258 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2259 } 2260 2261 htab_save_end_marker(f); 2262 2263 return rc; 2264 } 2265 2266 static int htab_save_complete(QEMUFile *f, void *opaque) 2267 { 2268 SpaprMachineState *spapr = opaque; 2269 int fd; 2270 2271 /* Iteration header */ 2272 if (!spapr->htab_shift) { 2273 qemu_put_be32(f, -1); 2274 return 0; 2275 } else { 2276 qemu_put_be32(f, 0); 2277 } 2278 2279 if (!spapr->htab) { 2280 int rc; 2281 2282 assert(kvm_enabled()); 2283 2284 fd = get_htab_fd(spapr); 2285 if (fd < 0) { 2286 return fd; 2287 } 2288 2289 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2290 if (rc < 0) { 2291 return rc; 2292 } 2293 } else { 2294 if (spapr->htab_first_pass) { 2295 htab_save_first_pass(f, spapr, -1); 2296 } 2297 htab_save_later_pass(f, spapr, -1); 2298 } 2299 2300 /* End marker */ 2301 htab_save_end_marker(f); 2302 2303 return 0; 2304 } 2305 2306 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2307 { 2308 SpaprMachineState *spapr = opaque; 2309 uint32_t section_hdr; 2310 int fd = -1; 2311 Error *local_err = NULL; 2312 2313 if (version_id < 1 || version_id > 1) { 2314 error_report("htab_load() bad version"); 2315 return -EINVAL; 2316 } 2317 2318 section_hdr = qemu_get_be32(f); 2319 2320 if (section_hdr == -1) { 2321 spapr_free_hpt(spapr); 2322 return 0; 2323 } 2324 2325 if (section_hdr) { 2326 /* First section gives the htab size */ 2327 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2328 if (local_err) { 2329 error_report_err(local_err); 2330 return -EINVAL; 2331 } 2332 return 0; 2333 } 2334 2335 if (!spapr->htab) { 2336 assert(kvm_enabled()); 2337 2338 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2339 if (fd < 0) { 2340 error_report_err(local_err); 2341 return fd; 2342 } 2343 } 2344 2345 while (true) { 2346 uint32_t index; 2347 uint16_t n_valid, n_invalid; 2348 2349 index = qemu_get_be32(f); 2350 n_valid = qemu_get_be16(f); 2351 n_invalid = qemu_get_be16(f); 2352 2353 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2354 /* End of Stream */ 2355 break; 2356 } 2357 2358 if ((index + n_valid + n_invalid) > 2359 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2360 /* Bad index in stream */ 2361 error_report( 2362 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2363 index, n_valid, n_invalid, spapr->htab_shift); 2364 return -EINVAL; 2365 } 2366 2367 if (spapr->htab) { 2368 if (n_valid) { 2369 qemu_get_buffer(f, HPTE(spapr->htab, index), 2370 HASH_PTE_SIZE_64 * n_valid); 2371 } 2372 if (n_invalid) { 2373 memset(HPTE(spapr->htab, index + n_valid), 0, 2374 HASH_PTE_SIZE_64 * n_invalid); 2375 } 2376 } else { 2377 int rc; 2378 2379 assert(fd >= 0); 2380 2381 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2382 if (rc < 0) { 2383 return rc; 2384 } 2385 } 2386 } 2387 2388 if (!spapr->htab) { 2389 assert(fd >= 0); 2390 close(fd); 2391 } 2392 2393 return 0; 2394 } 2395 2396 static void htab_save_cleanup(void *opaque) 2397 { 2398 SpaprMachineState *spapr = opaque; 2399 2400 close_htab_fd(spapr); 2401 } 2402 2403 static SaveVMHandlers savevm_htab_handlers = { 2404 .save_setup = htab_save_setup, 2405 .save_live_iterate = htab_save_iterate, 2406 .save_live_complete_precopy = htab_save_complete, 2407 .save_cleanup = htab_save_cleanup, 2408 .load_state = htab_load, 2409 }; 2410 2411 static void spapr_boot_set(void *opaque, const char *boot_device, 2412 Error **errp) 2413 { 2414 MachineState *machine = MACHINE(opaque); 2415 machine->boot_order = g_strdup(boot_device); 2416 } 2417 2418 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2419 { 2420 MachineState *machine = MACHINE(spapr); 2421 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2422 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2423 int i; 2424 2425 for (i = 0; i < nr_lmbs; i++) { 2426 uint64_t addr; 2427 2428 addr = i * lmb_size + machine->device_memory->base; 2429 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2430 addr / lmb_size); 2431 } 2432 } 2433 2434 /* 2435 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2436 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2437 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2438 */ 2439 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2440 { 2441 int i; 2442 2443 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2444 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2445 " is not aligned to %" PRIu64 " MiB", 2446 machine->ram_size, 2447 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2448 return; 2449 } 2450 2451 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2452 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2453 " is not aligned to %" PRIu64 " MiB", 2454 machine->ram_size, 2455 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2456 return; 2457 } 2458 2459 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2460 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2461 error_setg(errp, 2462 "Node %d memory size 0x%" PRIx64 2463 " is not aligned to %" PRIu64 " MiB", 2464 i, machine->numa_state->nodes[i].node_mem, 2465 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2466 return; 2467 } 2468 } 2469 } 2470 2471 /* find cpu slot in machine->possible_cpus by core_id */ 2472 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2473 { 2474 int index = id / ms->smp.threads; 2475 2476 if (index >= ms->possible_cpus->len) { 2477 return NULL; 2478 } 2479 if (idx) { 2480 *idx = index; 2481 } 2482 return &ms->possible_cpus->cpus[index]; 2483 } 2484 2485 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2486 { 2487 MachineState *ms = MACHINE(spapr); 2488 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2489 Error *local_err = NULL; 2490 bool vsmt_user = !!spapr->vsmt; 2491 int kvm_smt = kvmppc_smt_threads(); 2492 int ret; 2493 unsigned int smp_threads = ms->smp.threads; 2494 2495 if (!kvm_enabled() && (smp_threads > 1)) { 2496 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2497 "on a pseries machine"); 2498 goto out; 2499 } 2500 if (!is_power_of_2(smp_threads)) { 2501 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2502 "machine because it must be a power of 2", smp_threads); 2503 goto out; 2504 } 2505 2506 /* Detemine the VSMT mode to use: */ 2507 if (vsmt_user) { 2508 if (spapr->vsmt < smp_threads) { 2509 error_setg(&local_err, "Cannot support VSMT mode %d" 2510 " because it must be >= threads/core (%d)", 2511 spapr->vsmt, smp_threads); 2512 goto out; 2513 } 2514 /* In this case, spapr->vsmt has been set by the command line */ 2515 } else if (!smc->smp_threads_vsmt) { 2516 /* 2517 * Default VSMT value is tricky, because we need it to be as 2518 * consistent as possible (for migration), but this requires 2519 * changing it for at least some existing cases. We pick 8 as 2520 * the value that we'd get with KVM on POWER8, the 2521 * overwhelmingly common case in production systems. 2522 */ 2523 spapr->vsmt = MAX(8, smp_threads); 2524 } else { 2525 spapr->vsmt = smp_threads; 2526 } 2527 2528 /* KVM: If necessary, set the SMT mode: */ 2529 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2530 ret = kvmppc_set_smt_threads(spapr->vsmt); 2531 if (ret) { 2532 /* Looks like KVM isn't able to change VSMT mode */ 2533 error_setg(&local_err, 2534 "Failed to set KVM's VSMT mode to %d (errno %d)", 2535 spapr->vsmt, ret); 2536 /* We can live with that if the default one is big enough 2537 * for the number of threads, and a submultiple of the one 2538 * we want. In this case we'll waste some vcpu ids, but 2539 * behaviour will be correct */ 2540 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2541 warn_report_err(local_err); 2542 local_err = NULL; 2543 goto out; 2544 } else { 2545 if (!vsmt_user) { 2546 error_append_hint(&local_err, 2547 "On PPC, a VM with %d threads/core" 2548 " on a host with %d threads/core" 2549 " requires the use of VSMT mode %d.\n", 2550 smp_threads, kvm_smt, spapr->vsmt); 2551 } 2552 kvmppc_error_append_smt_possible_hint(&local_err); 2553 goto out; 2554 } 2555 } 2556 } 2557 /* else TCG: nothing to do currently */ 2558 out: 2559 error_propagate(errp, local_err); 2560 } 2561 2562 static void spapr_init_cpus(SpaprMachineState *spapr) 2563 { 2564 MachineState *machine = MACHINE(spapr); 2565 MachineClass *mc = MACHINE_GET_CLASS(machine); 2566 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2567 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2568 const CPUArchIdList *possible_cpus; 2569 unsigned int smp_cpus = machine->smp.cpus; 2570 unsigned int smp_threads = machine->smp.threads; 2571 unsigned int max_cpus = machine->smp.max_cpus; 2572 int boot_cores_nr = smp_cpus / smp_threads; 2573 int i; 2574 2575 possible_cpus = mc->possible_cpu_arch_ids(machine); 2576 if (mc->has_hotpluggable_cpus) { 2577 if (smp_cpus % smp_threads) { 2578 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2579 smp_cpus, smp_threads); 2580 exit(1); 2581 } 2582 if (max_cpus % smp_threads) { 2583 error_report("max_cpus (%u) must be multiple of threads (%u)", 2584 max_cpus, smp_threads); 2585 exit(1); 2586 } 2587 } else { 2588 if (max_cpus != smp_cpus) { 2589 error_report("This machine version does not support CPU hotplug"); 2590 exit(1); 2591 } 2592 boot_cores_nr = possible_cpus->len; 2593 } 2594 2595 if (smc->pre_2_10_has_unused_icps) { 2596 int i; 2597 2598 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2599 /* Dummy entries get deregistered when real ICPState objects 2600 * are registered during CPU core hotplug. 2601 */ 2602 pre_2_10_vmstate_register_dummy_icp(i); 2603 } 2604 } 2605 2606 for (i = 0; i < possible_cpus->len; i++) { 2607 int core_id = i * smp_threads; 2608 2609 if (mc->has_hotpluggable_cpus) { 2610 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2611 spapr_vcpu_id(spapr, core_id)); 2612 } 2613 2614 if (i < boot_cores_nr) { 2615 Object *core = object_new(type); 2616 int nr_threads = smp_threads; 2617 2618 /* Handle the partially filled core for older machine types */ 2619 if ((i + 1) * smp_threads >= smp_cpus) { 2620 nr_threads = smp_cpus - i * smp_threads; 2621 } 2622 2623 object_property_set_int(core, nr_threads, "nr-threads", 2624 &error_fatal); 2625 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2626 &error_fatal); 2627 object_property_set_bool(core, true, "realized", &error_fatal); 2628 2629 object_unref(core); 2630 } 2631 } 2632 } 2633 2634 static PCIHostState *spapr_create_default_phb(void) 2635 { 2636 DeviceState *dev; 2637 2638 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2639 qdev_prop_set_uint32(dev, "index", 0); 2640 qdev_init_nofail(dev); 2641 2642 return PCI_HOST_BRIDGE(dev); 2643 } 2644 2645 /* pSeries LPAR / sPAPR hardware init */ 2646 static void spapr_machine_init(MachineState *machine) 2647 { 2648 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2649 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2650 MachineClass *mc = MACHINE_GET_CLASS(machine); 2651 const char *kernel_filename = machine->kernel_filename; 2652 const char *initrd_filename = machine->initrd_filename; 2653 PCIHostState *phb; 2654 int i; 2655 MemoryRegion *sysmem = get_system_memory(); 2656 hwaddr node0_size = spapr_node0_size(machine); 2657 long load_limit, fw_size; 2658 char *filename; 2659 Error *resize_hpt_err = NULL; 2660 2661 msi_nonbroken = true; 2662 2663 QLIST_INIT(&spapr->phbs); 2664 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2665 2666 /* Determine capabilities to run with */ 2667 spapr_caps_init(spapr); 2668 2669 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2670 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2671 /* 2672 * If the user explicitly requested a mode we should either 2673 * supply it, or fail completely (which we do below). But if 2674 * it's not set explicitly, we reset our mode to something 2675 * that works 2676 */ 2677 if (resize_hpt_err) { 2678 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2679 error_free(resize_hpt_err); 2680 resize_hpt_err = NULL; 2681 } else { 2682 spapr->resize_hpt = smc->resize_hpt_default; 2683 } 2684 } 2685 2686 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2687 2688 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2689 /* 2690 * User requested HPT resize, but this host can't supply it. Bail out 2691 */ 2692 error_report_err(resize_hpt_err); 2693 exit(1); 2694 } 2695 2696 spapr->rma_size = node0_size; 2697 2698 /* With KVM, we don't actually know whether KVM supports an 2699 * unbounded RMA (PR KVM) or is limited by the hash table size 2700 * (HV KVM using VRMA), so we always assume the latter 2701 * 2702 * In that case, we also limit the initial allocations for RTAS 2703 * etc... to 256M since we have no way to know what the VRMA size 2704 * is going to be as it depends on the size of the hash table 2705 * which isn't determined yet. 2706 */ 2707 if (kvm_enabled()) { 2708 spapr->vrma_adjust = 1; 2709 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2710 } 2711 2712 /* Actually we don't support unbounded RMA anymore since we added 2713 * proper emulation of HV mode. The max we can get is 16G which 2714 * also happens to be what we configure for PAPR mode so make sure 2715 * we don't do anything bigger than that 2716 */ 2717 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2718 2719 if (spapr->rma_size > node0_size) { 2720 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2721 spapr->rma_size); 2722 exit(1); 2723 } 2724 2725 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2726 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2727 2728 /* 2729 * VSMT must be set in order to be able to compute VCPU ids, ie to 2730 * call spapr_max_server_number() or spapr_vcpu_id(). 2731 */ 2732 spapr_set_vsmt_mode(spapr, &error_fatal); 2733 2734 /* Set up Interrupt Controller before we create the VCPUs */ 2735 spapr_irq_init(spapr, &error_fatal); 2736 2737 /* Set up containers for ibm,client-architecture-support negotiated options 2738 */ 2739 spapr->ov5 = spapr_ovec_new(); 2740 spapr->ov5_cas = spapr_ovec_new(); 2741 2742 if (smc->dr_lmb_enabled) { 2743 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2744 spapr_validate_node_memory(machine, &error_fatal); 2745 } 2746 2747 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2748 2749 /* advertise support for dedicated HP event source to guests */ 2750 if (spapr->use_hotplug_event_source) { 2751 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2752 } 2753 2754 /* advertise support for HPT resizing */ 2755 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2756 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2757 } 2758 2759 /* advertise support for ibm,dyamic-memory-v2 */ 2760 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2761 2762 /* advertise XIVE on POWER9 machines */ 2763 if (spapr->irq->xive) { 2764 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2765 } 2766 2767 /* init CPUs */ 2768 spapr_init_cpus(spapr); 2769 2770 /* 2771 * check we don't have a memory-less/cpu-less NUMA node 2772 * Firmware relies on the existing memory/cpu topology to provide the 2773 * NUMA topology to the kernel. 2774 * And the linux kernel needs to know the NUMA topology at start 2775 * to be able to hotplug CPUs later. 2776 */ 2777 if (machine->numa_state->num_nodes) { 2778 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2779 /* check for memory-less node */ 2780 if (machine->numa_state->nodes[i].node_mem == 0) { 2781 CPUState *cs; 2782 int found = 0; 2783 /* check for cpu-less node */ 2784 CPU_FOREACH(cs) { 2785 PowerPCCPU *cpu = POWERPC_CPU(cs); 2786 if (cpu->node_id == i) { 2787 found = 1; 2788 break; 2789 } 2790 } 2791 /* memory-less and cpu-less node */ 2792 if (!found) { 2793 error_report( 2794 "Memory-less/cpu-less nodes are not supported (node %d)", 2795 i); 2796 exit(1); 2797 } 2798 } 2799 } 2800 2801 } 2802 2803 /* 2804 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2805 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2806 * called from vPHB reset handler so we initialize the counter here. 2807 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2808 * must be equally distant from any other node. 2809 * The final value of spapr->gpu_numa_id is going to be written to 2810 * max-associativity-domains in spapr_build_fdt(). 2811 */ 2812 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2813 2814 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2815 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2816 spapr->max_compat_pvr)) { 2817 /* KVM and TCG always allow GTSE with radix... */ 2818 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2819 } 2820 /* ... but not with hash (currently). */ 2821 2822 if (kvm_enabled()) { 2823 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2824 kvmppc_enable_logical_ci_hcalls(); 2825 kvmppc_enable_set_mode_hcall(); 2826 2827 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2828 kvmppc_enable_clear_ref_mod_hcalls(); 2829 2830 /* Enable H_PAGE_INIT */ 2831 kvmppc_enable_h_page_init(); 2832 } 2833 2834 /* map RAM */ 2835 memory_region_add_subregion(sysmem, 0, machine->ram); 2836 2837 /* always allocate the device memory information */ 2838 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2839 2840 /* initialize hotplug memory address space */ 2841 if (machine->ram_size < machine->maxram_size) { 2842 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2843 /* 2844 * Limit the number of hotpluggable memory slots to half the number 2845 * slots that KVM supports, leaving the other half for PCI and other 2846 * devices. However ensure that number of slots doesn't drop below 32. 2847 */ 2848 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2849 SPAPR_MAX_RAM_SLOTS; 2850 2851 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2852 max_memslots = SPAPR_MAX_RAM_SLOTS; 2853 } 2854 if (machine->ram_slots > max_memslots) { 2855 error_report("Specified number of memory slots %" 2856 PRIu64" exceeds max supported %d", 2857 machine->ram_slots, max_memslots); 2858 exit(1); 2859 } 2860 2861 machine->device_memory->base = ROUND_UP(machine->ram_size, 2862 SPAPR_DEVICE_MEM_ALIGN); 2863 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2864 "device-memory", device_mem_size); 2865 memory_region_add_subregion(sysmem, machine->device_memory->base, 2866 &machine->device_memory->mr); 2867 } 2868 2869 if (smc->dr_lmb_enabled) { 2870 spapr_create_lmb_dr_connectors(spapr); 2871 } 2872 2873 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) { 2874 /* Create the error string for live migration blocker */ 2875 error_setg(&spapr->fwnmi_migration_blocker, 2876 "A machine check is being handled during migration. The handler" 2877 "may run and log hardware error on the destination"); 2878 } 2879 2880 if (mc->nvdimm_supported) { 2881 spapr_create_nvdimm_dr_connectors(spapr); 2882 } 2883 2884 /* Set up RTAS event infrastructure */ 2885 spapr_events_init(spapr); 2886 2887 /* Set up the RTC RTAS interfaces */ 2888 spapr_rtc_create(spapr); 2889 2890 /* Set up VIO bus */ 2891 spapr->vio_bus = spapr_vio_bus_init(); 2892 2893 for (i = 0; i < serial_max_hds(); i++) { 2894 if (serial_hd(i)) { 2895 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2896 } 2897 } 2898 2899 /* We always have at least the nvram device on VIO */ 2900 spapr_create_nvram(spapr); 2901 2902 /* 2903 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2904 * connectors (described in root DT node's "ibm,drc-types" property) 2905 * are pre-initialized here. additional child connectors (such as 2906 * connectors for a PHBs PCI slots) are added as needed during their 2907 * parent's realization. 2908 */ 2909 if (smc->dr_phb_enabled) { 2910 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2911 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2912 } 2913 } 2914 2915 /* Set up PCI */ 2916 spapr_pci_rtas_init(); 2917 2918 phb = spapr_create_default_phb(); 2919 2920 for (i = 0; i < nb_nics; i++) { 2921 NICInfo *nd = &nd_table[i]; 2922 2923 if (!nd->model) { 2924 nd->model = g_strdup("spapr-vlan"); 2925 } 2926 2927 if (g_str_equal(nd->model, "spapr-vlan") || 2928 g_str_equal(nd->model, "ibmveth")) { 2929 spapr_vlan_create(spapr->vio_bus, nd); 2930 } else { 2931 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2932 } 2933 } 2934 2935 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2936 spapr_vscsi_create(spapr->vio_bus); 2937 } 2938 2939 /* Graphics */ 2940 if (spapr_vga_init(phb->bus, &error_fatal)) { 2941 spapr->has_graphics = true; 2942 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2943 } 2944 2945 if (machine->usb) { 2946 if (smc->use_ohci_by_default) { 2947 pci_create_simple(phb->bus, -1, "pci-ohci"); 2948 } else { 2949 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2950 } 2951 2952 if (spapr->has_graphics) { 2953 USBBus *usb_bus = usb_bus_find(-1); 2954 2955 usb_create_simple(usb_bus, "usb-kbd"); 2956 usb_create_simple(usb_bus, "usb-mouse"); 2957 } 2958 } 2959 2960 if (spapr->rma_size < MIN_RMA_SLOF) { 2961 error_report( 2962 "pSeries SLOF firmware requires >= %ldMiB guest RMA (Real Mode Area memory)", 2963 MIN_RMA_SLOF / MiB); 2964 exit(1); 2965 } 2966 2967 if (kernel_filename) { 2968 uint64_t lowaddr = 0; 2969 2970 spapr->kernel_size = load_elf(kernel_filename, NULL, 2971 translate_kernel_address, spapr, 2972 NULL, &lowaddr, NULL, NULL, 1, 2973 PPC_ELF_MACHINE, 0, 0); 2974 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2975 spapr->kernel_size = load_elf(kernel_filename, NULL, 2976 translate_kernel_address, spapr, NULL, 2977 &lowaddr, NULL, NULL, 0, 2978 PPC_ELF_MACHINE, 2979 0, 0); 2980 spapr->kernel_le = spapr->kernel_size > 0; 2981 } 2982 if (spapr->kernel_size < 0) { 2983 error_report("error loading %s: %s", kernel_filename, 2984 load_elf_strerror(spapr->kernel_size)); 2985 exit(1); 2986 } 2987 2988 /* load initrd */ 2989 if (initrd_filename) { 2990 /* Try to locate the initrd in the gap between the kernel 2991 * and the firmware. Add a bit of space just in case 2992 */ 2993 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2994 + 0x1ffff) & ~0xffff; 2995 spapr->initrd_size = load_image_targphys(initrd_filename, 2996 spapr->initrd_base, 2997 load_limit 2998 - spapr->initrd_base); 2999 if (spapr->initrd_size < 0) { 3000 error_report("could not load initial ram disk '%s'", 3001 initrd_filename); 3002 exit(1); 3003 } 3004 } 3005 } 3006 3007 if (bios_name == NULL) { 3008 bios_name = FW_FILE_NAME; 3009 } 3010 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3011 if (!filename) { 3012 error_report("Could not find LPAR firmware '%s'", bios_name); 3013 exit(1); 3014 } 3015 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3016 if (fw_size <= 0) { 3017 error_report("Could not load LPAR firmware '%s'", filename); 3018 exit(1); 3019 } 3020 g_free(filename); 3021 3022 /* FIXME: Should register things through the MachineState's qdev 3023 * interface, this is a legacy from the sPAPREnvironment structure 3024 * which predated MachineState but had a similar function */ 3025 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3026 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3027 &savevm_htab_handlers, spapr); 3028 3029 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3030 &error_fatal); 3031 3032 qemu_register_boot_set(spapr_boot_set, spapr); 3033 3034 /* 3035 * Nothing needs to be done to resume a suspended guest because 3036 * suspending does not change the machine state, so no need for 3037 * a ->wakeup method. 3038 */ 3039 qemu_register_wakeup_support(); 3040 3041 if (kvm_enabled()) { 3042 /* to stop and start vmclock */ 3043 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3044 &spapr->tb); 3045 3046 kvmppc_spapr_enable_inkernel_multitce(); 3047 } 3048 3049 qemu_cond_init(&spapr->mc_delivery_cond); 3050 } 3051 3052 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3053 { 3054 if (!vm_type) { 3055 return 0; 3056 } 3057 3058 if (!strcmp(vm_type, "HV")) { 3059 return 1; 3060 } 3061 3062 if (!strcmp(vm_type, "PR")) { 3063 return 2; 3064 } 3065 3066 error_report("Unknown kvm-type specified '%s'", vm_type); 3067 exit(1); 3068 } 3069 3070 /* 3071 * Implementation of an interface to adjust firmware path 3072 * for the bootindex property handling. 3073 */ 3074 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3075 DeviceState *dev) 3076 { 3077 #define CAST(type, obj, name) \ 3078 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3079 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3080 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3081 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3082 3083 if (d) { 3084 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3085 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3086 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3087 3088 if (spapr) { 3089 /* 3090 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3091 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3092 * 0x8000 | (target << 8) | (bus << 5) | lun 3093 * (see the "Logical unit addressing format" table in SAM5) 3094 */ 3095 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3096 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3097 (uint64_t)id << 48); 3098 } else if (virtio) { 3099 /* 3100 * We use SRP luns of the form 01000000 | (target << 8) | lun 3101 * in the top 32 bits of the 64-bit LUN 3102 * Note: the quote above is from SLOF and it is wrong, 3103 * the actual binding is: 3104 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3105 */ 3106 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3107 if (d->lun >= 256) { 3108 /* Use the LUN "flat space addressing method" */ 3109 id |= 0x4000; 3110 } 3111 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3112 (uint64_t)id << 32); 3113 } else if (usb) { 3114 /* 3115 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3116 * in the top 32 bits of the 64-bit LUN 3117 */ 3118 unsigned usb_port = atoi(usb->port->path); 3119 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3120 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3121 (uint64_t)id << 32); 3122 } 3123 } 3124 3125 /* 3126 * SLOF probes the USB devices, and if it recognizes that the device is a 3127 * storage device, it changes its name to "storage" instead of "usb-host", 3128 * and additionally adds a child node for the SCSI LUN, so the correct 3129 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3130 */ 3131 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3132 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3133 if (usb_host_dev_is_scsi_storage(usbdev)) { 3134 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3135 } 3136 } 3137 3138 if (phb) { 3139 /* Replace "pci" with "pci@800000020000000" */ 3140 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3141 } 3142 3143 if (vsc) { 3144 /* Same logic as virtio above */ 3145 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3146 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3147 } 3148 3149 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3150 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3151 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3152 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3153 } 3154 3155 return NULL; 3156 } 3157 3158 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3159 { 3160 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3161 3162 return g_strdup(spapr->kvm_type); 3163 } 3164 3165 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3166 { 3167 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3168 3169 g_free(spapr->kvm_type); 3170 spapr->kvm_type = g_strdup(value); 3171 } 3172 3173 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3174 { 3175 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 return spapr->use_hotplug_event_source; 3178 } 3179 3180 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3181 Error **errp) 3182 { 3183 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3184 3185 spapr->use_hotplug_event_source = value; 3186 } 3187 3188 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3189 { 3190 return true; 3191 } 3192 3193 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3194 { 3195 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3196 3197 switch (spapr->resize_hpt) { 3198 case SPAPR_RESIZE_HPT_DEFAULT: 3199 return g_strdup("default"); 3200 case SPAPR_RESIZE_HPT_DISABLED: 3201 return g_strdup("disabled"); 3202 case SPAPR_RESIZE_HPT_ENABLED: 3203 return g_strdup("enabled"); 3204 case SPAPR_RESIZE_HPT_REQUIRED: 3205 return g_strdup("required"); 3206 } 3207 g_assert_not_reached(); 3208 } 3209 3210 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3211 { 3212 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3213 3214 if (strcmp(value, "default") == 0) { 3215 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3216 } else if (strcmp(value, "disabled") == 0) { 3217 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3218 } else if (strcmp(value, "enabled") == 0) { 3219 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3220 } else if (strcmp(value, "required") == 0) { 3221 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3222 } else { 3223 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3224 } 3225 } 3226 3227 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3228 void *opaque, Error **errp) 3229 { 3230 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3231 } 3232 3233 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3234 void *opaque, Error **errp) 3235 { 3236 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3237 } 3238 3239 static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name, 3240 void *opaque, Error **errp) 3241 { 3242 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3243 } 3244 3245 static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name, 3246 void *opaque, Error **errp) 3247 { 3248 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3249 } 3250 3251 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3252 { 3253 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3254 3255 if (spapr->irq == &spapr_irq_xics_legacy) { 3256 return g_strdup("legacy"); 3257 } else if (spapr->irq == &spapr_irq_xics) { 3258 return g_strdup("xics"); 3259 } else if (spapr->irq == &spapr_irq_xive) { 3260 return g_strdup("xive"); 3261 } else if (spapr->irq == &spapr_irq_dual) { 3262 return g_strdup("dual"); 3263 } 3264 g_assert_not_reached(); 3265 } 3266 3267 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3268 { 3269 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3270 3271 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3272 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3273 return; 3274 } 3275 3276 /* The legacy IRQ backend can not be set */ 3277 if (strcmp(value, "xics") == 0) { 3278 spapr->irq = &spapr_irq_xics; 3279 } else if (strcmp(value, "xive") == 0) { 3280 spapr->irq = &spapr_irq_xive; 3281 } else if (strcmp(value, "dual") == 0) { 3282 spapr->irq = &spapr_irq_dual; 3283 } else { 3284 error_setg(errp, "Bad value for \"ic-mode\" property"); 3285 } 3286 } 3287 3288 static char *spapr_get_host_model(Object *obj, Error **errp) 3289 { 3290 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3291 3292 return g_strdup(spapr->host_model); 3293 } 3294 3295 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3296 { 3297 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3298 3299 g_free(spapr->host_model); 3300 spapr->host_model = g_strdup(value); 3301 } 3302 3303 static char *spapr_get_host_serial(Object *obj, Error **errp) 3304 { 3305 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3306 3307 return g_strdup(spapr->host_serial); 3308 } 3309 3310 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3311 { 3312 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3313 3314 g_free(spapr->host_serial); 3315 spapr->host_serial = g_strdup(value); 3316 } 3317 3318 static void spapr_instance_init(Object *obj) 3319 { 3320 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3321 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3322 3323 spapr->htab_fd = -1; 3324 spapr->use_hotplug_event_source = true; 3325 object_property_add_str(obj, "kvm-type", 3326 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3327 object_property_set_description(obj, "kvm-type", 3328 "Specifies the KVM virtualization mode (HV, PR)", 3329 NULL); 3330 object_property_add_bool(obj, "modern-hotplug-events", 3331 spapr_get_modern_hotplug_events, 3332 spapr_set_modern_hotplug_events, 3333 NULL); 3334 object_property_set_description(obj, "modern-hotplug-events", 3335 "Use dedicated hotplug event mechanism in" 3336 " place of standard EPOW events when possible" 3337 " (required for memory hot-unplug support)", 3338 NULL); 3339 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3340 "Maximum permitted CPU compatibility mode", 3341 &error_fatal); 3342 3343 object_property_add_str(obj, "resize-hpt", 3344 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3345 object_property_set_description(obj, "resize-hpt", 3346 "Resizing of the Hash Page Table (enabled, disabled, required)", 3347 NULL); 3348 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3349 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3350 object_property_set_description(obj, "vsmt", 3351 "Virtual SMT: KVM behaves as if this were" 3352 " the host's SMT mode", &error_abort); 3353 object_property_add_bool(obj, "vfio-no-msix-emulation", 3354 spapr_get_msix_emulation, NULL, NULL); 3355 3356 object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr, 3357 spapr_set_kernel_addr, NULL, &spapr->kernel_addr, 3358 &error_abort); 3359 object_property_set_description(obj, "kernel-addr", 3360 stringify(KERNEL_LOAD_ADDR) 3361 " for -kernel is the default", 3362 NULL); 3363 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3364 /* The machine class defines the default interrupt controller mode */ 3365 spapr->irq = smc->irq; 3366 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3367 spapr_set_ic_mode, NULL); 3368 object_property_set_description(obj, "ic-mode", 3369 "Specifies the interrupt controller mode (xics, xive, dual)", 3370 NULL); 3371 3372 object_property_add_str(obj, "host-model", 3373 spapr_get_host_model, spapr_set_host_model, 3374 &error_abort); 3375 object_property_set_description(obj, "host-model", 3376 "Host model to advertise in guest device tree", &error_abort); 3377 object_property_add_str(obj, "host-serial", 3378 spapr_get_host_serial, spapr_set_host_serial, 3379 &error_abort); 3380 object_property_set_description(obj, "host-serial", 3381 "Host serial number to advertise in guest device tree", &error_abort); 3382 } 3383 3384 static void spapr_machine_finalizefn(Object *obj) 3385 { 3386 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3387 3388 g_free(spapr->kvm_type); 3389 } 3390 3391 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3392 { 3393 cpu_synchronize_state(cs); 3394 ppc_cpu_do_system_reset(cs); 3395 } 3396 3397 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3398 { 3399 CPUState *cs; 3400 3401 CPU_FOREACH(cs) { 3402 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3403 } 3404 } 3405 3406 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3407 void *fdt, int *fdt_start_offset, Error **errp) 3408 { 3409 uint64_t addr; 3410 uint32_t node; 3411 3412 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3413 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3414 &error_abort); 3415 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3416 SPAPR_MEMORY_BLOCK_SIZE); 3417 return 0; 3418 } 3419 3420 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3421 bool dedicated_hp_event_source, Error **errp) 3422 { 3423 SpaprDrc *drc; 3424 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3425 int i; 3426 uint64_t addr = addr_start; 3427 bool hotplugged = spapr_drc_hotplugged(dev); 3428 Error *local_err = NULL; 3429 3430 for (i = 0; i < nr_lmbs; i++) { 3431 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3432 addr / SPAPR_MEMORY_BLOCK_SIZE); 3433 g_assert(drc); 3434 3435 spapr_drc_attach(drc, dev, &local_err); 3436 if (local_err) { 3437 while (addr > addr_start) { 3438 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3439 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3440 addr / SPAPR_MEMORY_BLOCK_SIZE); 3441 spapr_drc_detach(drc); 3442 } 3443 error_propagate(errp, local_err); 3444 return; 3445 } 3446 if (!hotplugged) { 3447 spapr_drc_reset(drc); 3448 } 3449 addr += SPAPR_MEMORY_BLOCK_SIZE; 3450 } 3451 /* send hotplug notification to the 3452 * guest only in case of hotplugged memory 3453 */ 3454 if (hotplugged) { 3455 if (dedicated_hp_event_source) { 3456 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3457 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3458 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3459 nr_lmbs, 3460 spapr_drc_index(drc)); 3461 } else { 3462 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3463 nr_lmbs); 3464 } 3465 } 3466 } 3467 3468 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3469 Error **errp) 3470 { 3471 Error *local_err = NULL; 3472 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3473 PCDIMMDevice *dimm = PC_DIMM(dev); 3474 uint64_t size, addr, slot; 3475 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3476 3477 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3478 3479 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3480 if (local_err) { 3481 goto out; 3482 } 3483 3484 if (!is_nvdimm) { 3485 addr = object_property_get_uint(OBJECT(dimm), 3486 PC_DIMM_ADDR_PROP, &local_err); 3487 if (local_err) { 3488 goto out_unplug; 3489 } 3490 spapr_add_lmbs(dev, addr, size, 3491 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3492 &local_err); 3493 } else { 3494 slot = object_property_get_uint(OBJECT(dimm), 3495 PC_DIMM_SLOT_PROP, &local_err); 3496 if (local_err) { 3497 goto out_unplug; 3498 } 3499 spapr_add_nvdimm(dev, slot, &local_err); 3500 } 3501 3502 if (local_err) { 3503 goto out_unplug; 3504 } 3505 3506 return; 3507 3508 out_unplug: 3509 pc_dimm_unplug(dimm, MACHINE(ms)); 3510 out: 3511 error_propagate(errp, local_err); 3512 } 3513 3514 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3515 Error **errp) 3516 { 3517 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3518 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3519 const MachineClass *mc = MACHINE_CLASS(smc); 3520 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3521 PCDIMMDevice *dimm = PC_DIMM(dev); 3522 Error *local_err = NULL; 3523 uint64_t size; 3524 Object *memdev; 3525 hwaddr pagesize; 3526 3527 if (!smc->dr_lmb_enabled) { 3528 error_setg(errp, "Memory hotplug not supported for this machine"); 3529 return; 3530 } 3531 3532 if (is_nvdimm && !mc->nvdimm_supported) { 3533 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3534 return; 3535 } 3536 3537 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3538 if (local_err) { 3539 error_propagate(errp, local_err); 3540 return; 3541 } 3542 3543 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3544 error_setg(errp, "Hotplugged memory size must be a multiple of " 3545 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3546 return; 3547 } else if (is_nvdimm) { 3548 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3549 if (local_err) { 3550 error_propagate(errp, local_err); 3551 return; 3552 } 3553 } 3554 3555 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3556 &error_abort); 3557 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3558 spapr_check_pagesize(spapr, pagesize, &local_err); 3559 if (local_err) { 3560 error_propagate(errp, local_err); 3561 return; 3562 } 3563 3564 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3565 } 3566 3567 struct SpaprDimmState { 3568 PCDIMMDevice *dimm; 3569 uint32_t nr_lmbs; 3570 QTAILQ_ENTRY(SpaprDimmState) next; 3571 }; 3572 3573 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3574 PCDIMMDevice *dimm) 3575 { 3576 SpaprDimmState *dimm_state = NULL; 3577 3578 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3579 if (dimm_state->dimm == dimm) { 3580 break; 3581 } 3582 } 3583 return dimm_state; 3584 } 3585 3586 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3587 uint32_t nr_lmbs, 3588 PCDIMMDevice *dimm) 3589 { 3590 SpaprDimmState *ds = NULL; 3591 3592 /* 3593 * If this request is for a DIMM whose removal had failed earlier 3594 * (due to guest's refusal to remove the LMBs), we would have this 3595 * dimm already in the pending_dimm_unplugs list. In that 3596 * case don't add again. 3597 */ 3598 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3599 if (!ds) { 3600 ds = g_malloc0(sizeof(SpaprDimmState)); 3601 ds->nr_lmbs = nr_lmbs; 3602 ds->dimm = dimm; 3603 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3604 } 3605 return ds; 3606 } 3607 3608 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3609 SpaprDimmState *dimm_state) 3610 { 3611 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3612 g_free(dimm_state); 3613 } 3614 3615 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3616 PCDIMMDevice *dimm) 3617 { 3618 SpaprDrc *drc; 3619 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3620 &error_abort); 3621 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3622 uint32_t avail_lmbs = 0; 3623 uint64_t addr_start, addr; 3624 int i; 3625 3626 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3627 &error_abort); 3628 3629 addr = addr_start; 3630 for (i = 0; i < nr_lmbs; i++) { 3631 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3632 addr / SPAPR_MEMORY_BLOCK_SIZE); 3633 g_assert(drc); 3634 if (drc->dev) { 3635 avail_lmbs++; 3636 } 3637 addr += SPAPR_MEMORY_BLOCK_SIZE; 3638 } 3639 3640 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3641 } 3642 3643 /* Callback to be called during DRC release. */ 3644 void spapr_lmb_release(DeviceState *dev) 3645 { 3646 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3647 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3648 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3649 3650 /* This information will get lost if a migration occurs 3651 * during the unplug process. In this case recover it. */ 3652 if (ds == NULL) { 3653 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3654 g_assert(ds); 3655 /* The DRC being examined by the caller at least must be counted */ 3656 g_assert(ds->nr_lmbs); 3657 } 3658 3659 if (--ds->nr_lmbs) { 3660 return; 3661 } 3662 3663 /* 3664 * Now that all the LMBs have been removed by the guest, call the 3665 * unplug handler chain. This can never fail. 3666 */ 3667 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3668 object_unparent(OBJECT(dev)); 3669 } 3670 3671 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3672 { 3673 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3674 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3675 3676 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3677 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3678 spapr_pending_dimm_unplugs_remove(spapr, ds); 3679 } 3680 3681 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3682 DeviceState *dev, Error **errp) 3683 { 3684 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3685 Error *local_err = NULL; 3686 PCDIMMDevice *dimm = PC_DIMM(dev); 3687 uint32_t nr_lmbs; 3688 uint64_t size, addr_start, addr; 3689 int i; 3690 SpaprDrc *drc; 3691 3692 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3693 error_setg(&local_err, 3694 "nvdimm device hot unplug is not supported yet."); 3695 goto out; 3696 } 3697 3698 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3699 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3700 3701 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3702 &local_err); 3703 if (local_err) { 3704 goto out; 3705 } 3706 3707 /* 3708 * An existing pending dimm state for this DIMM means that there is an 3709 * unplug operation in progress, waiting for the spapr_lmb_release 3710 * callback to complete the job (BQL can't cover that far). In this case, 3711 * bail out to avoid detaching DRCs that were already released. 3712 */ 3713 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3714 error_setg(&local_err, 3715 "Memory unplug already in progress for device %s", 3716 dev->id); 3717 goto out; 3718 } 3719 3720 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3721 3722 addr = addr_start; 3723 for (i = 0; i < nr_lmbs; i++) { 3724 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3725 addr / SPAPR_MEMORY_BLOCK_SIZE); 3726 g_assert(drc); 3727 3728 spapr_drc_detach(drc); 3729 addr += SPAPR_MEMORY_BLOCK_SIZE; 3730 } 3731 3732 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3733 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3734 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3735 nr_lmbs, spapr_drc_index(drc)); 3736 out: 3737 error_propagate(errp, local_err); 3738 } 3739 3740 /* Callback to be called during DRC release. */ 3741 void spapr_core_release(DeviceState *dev) 3742 { 3743 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3744 3745 /* Call the unplug handler chain. This can never fail. */ 3746 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3747 object_unparent(OBJECT(dev)); 3748 } 3749 3750 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3751 { 3752 MachineState *ms = MACHINE(hotplug_dev); 3753 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3754 CPUCore *cc = CPU_CORE(dev); 3755 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3756 3757 if (smc->pre_2_10_has_unused_icps) { 3758 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3759 int i; 3760 3761 for (i = 0; i < cc->nr_threads; i++) { 3762 CPUState *cs = CPU(sc->threads[i]); 3763 3764 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3765 } 3766 } 3767 3768 assert(core_slot); 3769 core_slot->cpu = NULL; 3770 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3771 } 3772 3773 static 3774 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3775 Error **errp) 3776 { 3777 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3778 int index; 3779 SpaprDrc *drc; 3780 CPUCore *cc = CPU_CORE(dev); 3781 3782 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3783 error_setg(errp, "Unable to find CPU core with core-id: %d", 3784 cc->core_id); 3785 return; 3786 } 3787 if (index == 0) { 3788 error_setg(errp, "Boot CPU core may not be unplugged"); 3789 return; 3790 } 3791 3792 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3793 spapr_vcpu_id(spapr, cc->core_id)); 3794 g_assert(drc); 3795 3796 if (!spapr_drc_unplug_requested(drc)) { 3797 spapr_drc_detach(drc); 3798 spapr_hotplug_req_remove_by_index(drc); 3799 } 3800 } 3801 3802 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3803 void *fdt, int *fdt_start_offset, Error **errp) 3804 { 3805 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3806 CPUState *cs = CPU(core->threads[0]); 3807 PowerPCCPU *cpu = POWERPC_CPU(cs); 3808 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3809 int id = spapr_get_vcpu_id(cpu); 3810 char *nodename; 3811 int offset; 3812 3813 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3814 offset = fdt_add_subnode(fdt, 0, nodename); 3815 g_free(nodename); 3816 3817 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3818 3819 *fdt_start_offset = offset; 3820 return 0; 3821 } 3822 3823 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3824 Error **errp) 3825 { 3826 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3827 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3828 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3829 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3830 CPUCore *cc = CPU_CORE(dev); 3831 CPUState *cs; 3832 SpaprDrc *drc; 3833 Error *local_err = NULL; 3834 CPUArchId *core_slot; 3835 int index; 3836 bool hotplugged = spapr_drc_hotplugged(dev); 3837 int i; 3838 3839 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3840 if (!core_slot) { 3841 error_setg(errp, "Unable to find CPU core with core-id: %d", 3842 cc->core_id); 3843 return; 3844 } 3845 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3846 spapr_vcpu_id(spapr, cc->core_id)); 3847 3848 g_assert(drc || !mc->has_hotpluggable_cpus); 3849 3850 if (drc) { 3851 spapr_drc_attach(drc, dev, &local_err); 3852 if (local_err) { 3853 error_propagate(errp, local_err); 3854 return; 3855 } 3856 3857 if (hotplugged) { 3858 /* 3859 * Send hotplug notification interrupt to the guest only 3860 * in case of hotplugged CPUs. 3861 */ 3862 spapr_hotplug_req_add_by_index(drc); 3863 } else { 3864 spapr_drc_reset(drc); 3865 } 3866 } 3867 3868 core_slot->cpu = OBJECT(dev); 3869 3870 if (smc->pre_2_10_has_unused_icps) { 3871 for (i = 0; i < cc->nr_threads; i++) { 3872 cs = CPU(core->threads[i]); 3873 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3874 } 3875 } 3876 3877 /* 3878 * Set compatibility mode to match the boot CPU, which was either set 3879 * by the machine reset code or by CAS. 3880 */ 3881 if (hotplugged) { 3882 for (i = 0; i < cc->nr_threads; i++) { 3883 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3884 &local_err); 3885 if (local_err) { 3886 error_propagate(errp, local_err); 3887 return; 3888 } 3889 } 3890 } 3891 } 3892 3893 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3894 Error **errp) 3895 { 3896 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3897 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3898 Error *local_err = NULL; 3899 CPUCore *cc = CPU_CORE(dev); 3900 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3901 const char *type = object_get_typename(OBJECT(dev)); 3902 CPUArchId *core_slot; 3903 int index; 3904 unsigned int smp_threads = machine->smp.threads; 3905 3906 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3907 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3908 goto out; 3909 } 3910 3911 if (strcmp(base_core_type, type)) { 3912 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3913 goto out; 3914 } 3915 3916 if (cc->core_id % smp_threads) { 3917 error_setg(&local_err, "invalid core id %d", cc->core_id); 3918 goto out; 3919 } 3920 3921 /* 3922 * In general we should have homogeneous threads-per-core, but old 3923 * (pre hotplug support) machine types allow the last core to have 3924 * reduced threads as a compatibility hack for when we allowed 3925 * total vcpus not a multiple of threads-per-core. 3926 */ 3927 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3928 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3929 cc->nr_threads, smp_threads); 3930 goto out; 3931 } 3932 3933 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3934 if (!core_slot) { 3935 error_setg(&local_err, "core id %d out of range", cc->core_id); 3936 goto out; 3937 } 3938 3939 if (core_slot->cpu) { 3940 error_setg(&local_err, "core %d already populated", cc->core_id); 3941 goto out; 3942 } 3943 3944 numa_cpu_pre_plug(core_slot, dev, &local_err); 3945 3946 out: 3947 error_propagate(errp, local_err); 3948 } 3949 3950 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3951 void *fdt, int *fdt_start_offset, Error **errp) 3952 { 3953 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3954 int intc_phandle; 3955 3956 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3957 if (intc_phandle <= 0) { 3958 return -1; 3959 } 3960 3961 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3962 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3963 return -1; 3964 } 3965 3966 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3967 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3968 3969 return 0; 3970 } 3971 3972 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3973 Error **errp) 3974 { 3975 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3976 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3977 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3978 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3979 3980 if (dev->hotplugged && !smc->dr_phb_enabled) { 3981 error_setg(errp, "PHB hotplug not supported for this machine"); 3982 return; 3983 } 3984 3985 if (sphb->index == (uint32_t)-1) { 3986 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3987 return; 3988 } 3989 3990 /* 3991 * This will check that sphb->index doesn't exceed the maximum number of 3992 * PHBs for the current machine type. 3993 */ 3994 smc->phb_placement(spapr, sphb->index, 3995 &sphb->buid, &sphb->io_win_addr, 3996 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3997 windows_supported, sphb->dma_liobn, 3998 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3999 errp); 4000 } 4001 4002 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4003 Error **errp) 4004 { 4005 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4006 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4007 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4008 SpaprDrc *drc; 4009 bool hotplugged = spapr_drc_hotplugged(dev); 4010 Error *local_err = NULL; 4011 4012 if (!smc->dr_phb_enabled) { 4013 return; 4014 } 4015 4016 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4017 /* hotplug hooks should check it's enabled before getting this far */ 4018 assert(drc); 4019 4020 spapr_drc_attach(drc, DEVICE(dev), &local_err); 4021 if (local_err) { 4022 error_propagate(errp, local_err); 4023 return; 4024 } 4025 4026 if (hotplugged) { 4027 spapr_hotplug_req_add_by_index(drc); 4028 } else { 4029 spapr_drc_reset(drc); 4030 } 4031 } 4032 4033 void spapr_phb_release(DeviceState *dev) 4034 { 4035 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4036 4037 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4038 object_unparent(OBJECT(dev)); 4039 } 4040 4041 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4042 { 4043 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4044 } 4045 4046 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4047 DeviceState *dev, Error **errp) 4048 { 4049 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4050 SpaprDrc *drc; 4051 4052 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4053 assert(drc); 4054 4055 if (!spapr_drc_unplug_requested(drc)) { 4056 spapr_drc_detach(drc); 4057 spapr_hotplug_req_remove_by_index(drc); 4058 } 4059 } 4060 4061 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4062 Error **errp) 4063 { 4064 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4065 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4066 4067 if (spapr->tpm_proxy != NULL) { 4068 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4069 return; 4070 } 4071 4072 spapr->tpm_proxy = tpm_proxy; 4073 } 4074 4075 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4076 { 4077 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4078 4079 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4080 object_unparent(OBJECT(dev)); 4081 spapr->tpm_proxy = NULL; 4082 } 4083 4084 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4085 DeviceState *dev, Error **errp) 4086 { 4087 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4088 spapr_memory_plug(hotplug_dev, dev, errp); 4089 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4090 spapr_core_plug(hotplug_dev, dev, errp); 4091 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4092 spapr_phb_plug(hotplug_dev, dev, errp); 4093 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4094 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4095 } 4096 } 4097 4098 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4099 DeviceState *dev, Error **errp) 4100 { 4101 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4102 spapr_memory_unplug(hotplug_dev, dev); 4103 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4104 spapr_core_unplug(hotplug_dev, dev); 4105 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4106 spapr_phb_unplug(hotplug_dev, dev); 4107 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4108 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4109 } 4110 } 4111 4112 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4113 DeviceState *dev, Error **errp) 4114 { 4115 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4116 MachineClass *mc = MACHINE_GET_CLASS(sms); 4117 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4118 4119 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4120 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4121 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4122 } else { 4123 /* NOTE: this means there is a window after guest reset, prior to 4124 * CAS negotiation, where unplug requests will fail due to the 4125 * capability not being detected yet. This is a bit different than 4126 * the case with PCI unplug, where the events will be queued and 4127 * eventually handled by the guest after boot 4128 */ 4129 error_setg(errp, "Memory hot unplug not supported for this guest"); 4130 } 4131 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4132 if (!mc->has_hotpluggable_cpus) { 4133 error_setg(errp, "CPU hot unplug not supported on this machine"); 4134 return; 4135 } 4136 spapr_core_unplug_request(hotplug_dev, dev, errp); 4137 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4138 if (!smc->dr_phb_enabled) { 4139 error_setg(errp, "PHB hot unplug not supported on this machine"); 4140 return; 4141 } 4142 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4143 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4144 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4145 } 4146 } 4147 4148 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4149 DeviceState *dev, Error **errp) 4150 { 4151 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4152 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4153 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4154 spapr_core_pre_plug(hotplug_dev, dev, errp); 4155 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4156 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4157 } 4158 } 4159 4160 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4161 DeviceState *dev) 4162 { 4163 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4164 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4165 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4166 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4167 return HOTPLUG_HANDLER(machine); 4168 } 4169 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4170 PCIDevice *pcidev = PCI_DEVICE(dev); 4171 PCIBus *root = pci_device_root_bus(pcidev); 4172 SpaprPhbState *phb = 4173 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4174 TYPE_SPAPR_PCI_HOST_BRIDGE); 4175 4176 if (phb) { 4177 return HOTPLUG_HANDLER(phb); 4178 } 4179 } 4180 return NULL; 4181 } 4182 4183 static CpuInstanceProperties 4184 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4185 { 4186 CPUArchId *core_slot; 4187 MachineClass *mc = MACHINE_GET_CLASS(machine); 4188 4189 /* make sure possible_cpu are intialized */ 4190 mc->possible_cpu_arch_ids(machine); 4191 /* get CPU core slot containing thread that matches cpu_index */ 4192 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4193 assert(core_slot); 4194 return core_slot->props; 4195 } 4196 4197 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4198 { 4199 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4200 } 4201 4202 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4203 { 4204 int i; 4205 unsigned int smp_threads = machine->smp.threads; 4206 unsigned int smp_cpus = machine->smp.cpus; 4207 const char *core_type; 4208 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4209 MachineClass *mc = MACHINE_GET_CLASS(machine); 4210 4211 if (!mc->has_hotpluggable_cpus) { 4212 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4213 } 4214 if (machine->possible_cpus) { 4215 assert(machine->possible_cpus->len == spapr_max_cores); 4216 return machine->possible_cpus; 4217 } 4218 4219 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4220 if (!core_type) { 4221 error_report("Unable to find sPAPR CPU Core definition"); 4222 exit(1); 4223 } 4224 4225 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4226 sizeof(CPUArchId) * spapr_max_cores); 4227 machine->possible_cpus->len = spapr_max_cores; 4228 for (i = 0; i < machine->possible_cpus->len; i++) { 4229 int core_id = i * smp_threads; 4230 4231 machine->possible_cpus->cpus[i].type = core_type; 4232 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4233 machine->possible_cpus->cpus[i].arch_id = core_id; 4234 machine->possible_cpus->cpus[i].props.has_core_id = true; 4235 machine->possible_cpus->cpus[i].props.core_id = core_id; 4236 } 4237 return machine->possible_cpus; 4238 } 4239 4240 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4241 uint64_t *buid, hwaddr *pio, 4242 hwaddr *mmio32, hwaddr *mmio64, 4243 unsigned n_dma, uint32_t *liobns, 4244 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4245 { 4246 /* 4247 * New-style PHB window placement. 4248 * 4249 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4250 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4251 * windows. 4252 * 4253 * Some guest kernels can't work with MMIO windows above 1<<46 4254 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4255 * 4256 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4257 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4258 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4259 * 1TiB 64-bit MMIO windows for each PHB. 4260 */ 4261 const uint64_t base_buid = 0x800000020000000ULL; 4262 int i; 4263 4264 /* Sanity check natural alignments */ 4265 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4266 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4267 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4268 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4269 /* Sanity check bounds */ 4270 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4271 SPAPR_PCI_MEM32_WIN_SIZE); 4272 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4273 SPAPR_PCI_MEM64_WIN_SIZE); 4274 4275 if (index >= SPAPR_MAX_PHBS) { 4276 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4277 SPAPR_MAX_PHBS - 1); 4278 return; 4279 } 4280 4281 *buid = base_buid + index; 4282 for (i = 0; i < n_dma; ++i) { 4283 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4284 } 4285 4286 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4287 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4288 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4289 4290 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4291 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4292 } 4293 4294 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4295 { 4296 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4297 4298 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4299 } 4300 4301 static void spapr_ics_resend(XICSFabric *dev) 4302 { 4303 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4304 4305 ics_resend(spapr->ics); 4306 } 4307 4308 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4309 { 4310 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4311 4312 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4313 } 4314 4315 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4316 Monitor *mon) 4317 { 4318 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4319 4320 spapr_irq_print_info(spapr, mon); 4321 monitor_printf(mon, "irqchip: %s\n", 4322 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4323 } 4324 4325 /* 4326 * This is a XIVE only operation 4327 */ 4328 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4329 uint8_t nvt_blk, uint32_t nvt_idx, 4330 bool cam_ignore, uint8_t priority, 4331 uint32_t logic_serv, XiveTCTXMatch *match) 4332 { 4333 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4334 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4335 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4336 int count; 4337 4338 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4339 priority, logic_serv, match); 4340 if (count < 0) { 4341 return count; 4342 } 4343 4344 /* 4345 * When we implement the save and restore of the thread interrupt 4346 * contexts in the enter/exit CPU handlers of the machine and the 4347 * escalations in QEMU, we should be able to handle non dispatched 4348 * vCPUs. 4349 * 4350 * Until this is done, the sPAPR machine should find at least one 4351 * matching context always. 4352 */ 4353 if (count == 0) { 4354 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4355 nvt_blk, nvt_idx); 4356 } 4357 4358 return count; 4359 } 4360 4361 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4362 { 4363 return cpu->vcpu_id; 4364 } 4365 4366 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4367 { 4368 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4369 MachineState *ms = MACHINE(spapr); 4370 int vcpu_id; 4371 4372 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4373 4374 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4375 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4376 error_append_hint(errp, "Adjust the number of cpus to %d " 4377 "or try to raise the number of threads per core\n", 4378 vcpu_id * ms->smp.threads / spapr->vsmt); 4379 return; 4380 } 4381 4382 cpu->vcpu_id = vcpu_id; 4383 } 4384 4385 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4386 { 4387 CPUState *cs; 4388 4389 CPU_FOREACH(cs) { 4390 PowerPCCPU *cpu = POWERPC_CPU(cs); 4391 4392 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4393 return cpu; 4394 } 4395 } 4396 4397 return NULL; 4398 } 4399 4400 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4401 { 4402 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4403 4404 /* These are only called by TCG, KVM maintains dispatch state */ 4405 4406 spapr_cpu->prod = false; 4407 if (spapr_cpu->vpa_addr) { 4408 CPUState *cs = CPU(cpu); 4409 uint32_t dispatch; 4410 4411 dispatch = ldl_be_phys(cs->as, 4412 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4413 dispatch++; 4414 if ((dispatch & 1) != 0) { 4415 qemu_log_mask(LOG_GUEST_ERROR, 4416 "VPA: incorrect dispatch counter value for " 4417 "dispatched partition %u, correcting.\n", dispatch); 4418 dispatch++; 4419 } 4420 stl_be_phys(cs->as, 4421 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4422 } 4423 } 4424 4425 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4426 { 4427 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4428 4429 if (spapr_cpu->vpa_addr) { 4430 CPUState *cs = CPU(cpu); 4431 uint32_t dispatch; 4432 4433 dispatch = ldl_be_phys(cs->as, 4434 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4435 dispatch++; 4436 if ((dispatch & 1) != 1) { 4437 qemu_log_mask(LOG_GUEST_ERROR, 4438 "VPA: incorrect dispatch counter value for " 4439 "preempted partition %u, correcting.\n", dispatch); 4440 dispatch++; 4441 } 4442 stl_be_phys(cs->as, 4443 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4444 } 4445 } 4446 4447 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4448 { 4449 MachineClass *mc = MACHINE_CLASS(oc); 4450 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4451 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4452 NMIClass *nc = NMI_CLASS(oc); 4453 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4454 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4455 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4456 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4457 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4458 4459 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4460 mc->ignore_boot_device_suffixes = true; 4461 4462 /* 4463 * We set up the default / latest behaviour here. The class_init 4464 * functions for the specific versioned machine types can override 4465 * these details for backwards compatibility 4466 */ 4467 mc->init = spapr_machine_init; 4468 mc->reset = spapr_machine_reset; 4469 mc->block_default_type = IF_SCSI; 4470 mc->max_cpus = 1024; 4471 mc->no_parallel = 1; 4472 mc->default_boot_order = ""; 4473 mc->default_ram_size = 512 * MiB; 4474 mc->default_ram_id = "ppc_spapr.ram"; 4475 mc->default_display = "std"; 4476 mc->kvm_type = spapr_kvm_type; 4477 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4478 mc->pci_allow_0_address = true; 4479 assert(!mc->get_hotplug_handler); 4480 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4481 hc->pre_plug = spapr_machine_device_pre_plug; 4482 hc->plug = spapr_machine_device_plug; 4483 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4484 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4485 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4486 hc->unplug_request = spapr_machine_device_unplug_request; 4487 hc->unplug = spapr_machine_device_unplug; 4488 4489 smc->dr_lmb_enabled = true; 4490 smc->update_dt_enabled = true; 4491 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4492 mc->has_hotpluggable_cpus = true; 4493 mc->nvdimm_supported = true; 4494 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4495 fwc->get_dev_path = spapr_get_fw_dev_path; 4496 nc->nmi_monitor_handler = spapr_nmi; 4497 smc->phb_placement = spapr_phb_placement; 4498 vhc->hypercall = emulate_spapr_hypercall; 4499 vhc->hpt_mask = spapr_hpt_mask; 4500 vhc->map_hptes = spapr_map_hptes; 4501 vhc->unmap_hptes = spapr_unmap_hptes; 4502 vhc->hpte_set_c = spapr_hpte_set_c; 4503 vhc->hpte_set_r = spapr_hpte_set_r; 4504 vhc->get_pate = spapr_get_pate; 4505 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4506 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4507 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4508 xic->ics_get = spapr_ics_get; 4509 xic->ics_resend = spapr_ics_resend; 4510 xic->icp_get = spapr_icp_get; 4511 ispc->print_info = spapr_pic_print_info; 4512 /* Force NUMA node memory size to be a multiple of 4513 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4514 * in which LMBs are represented and hot-added 4515 */ 4516 mc->numa_mem_align_shift = 28; 4517 mc->numa_mem_supported = true; 4518 mc->auto_enable_numa = true; 4519 4520 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4521 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4522 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4523 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4524 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4525 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4526 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4527 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4528 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4529 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4530 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON; 4531 spapr_caps_add_properties(smc, &error_abort); 4532 smc->irq = &spapr_irq_dual; 4533 smc->dr_phb_enabled = true; 4534 smc->linux_pci_probe = true; 4535 smc->smp_threads_vsmt = true; 4536 smc->nr_xirqs = SPAPR_NR_XIRQS; 4537 xfc->match_nvt = spapr_match_nvt; 4538 } 4539 4540 static const TypeInfo spapr_machine_info = { 4541 .name = TYPE_SPAPR_MACHINE, 4542 .parent = TYPE_MACHINE, 4543 .abstract = true, 4544 .instance_size = sizeof(SpaprMachineState), 4545 .instance_init = spapr_instance_init, 4546 .instance_finalize = spapr_machine_finalizefn, 4547 .class_size = sizeof(SpaprMachineClass), 4548 .class_init = spapr_machine_class_init, 4549 .interfaces = (InterfaceInfo[]) { 4550 { TYPE_FW_PATH_PROVIDER }, 4551 { TYPE_NMI }, 4552 { TYPE_HOTPLUG_HANDLER }, 4553 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4554 { TYPE_XICS_FABRIC }, 4555 { TYPE_INTERRUPT_STATS_PROVIDER }, 4556 { TYPE_XIVE_FABRIC }, 4557 { } 4558 }, 4559 }; 4560 4561 static void spapr_machine_latest_class_options(MachineClass *mc) 4562 { 4563 mc->alias = "pseries"; 4564 mc->is_default = true; 4565 } 4566 4567 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4568 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4569 void *data) \ 4570 { \ 4571 MachineClass *mc = MACHINE_CLASS(oc); \ 4572 spapr_machine_##suffix##_class_options(mc); \ 4573 if (latest) { \ 4574 spapr_machine_latest_class_options(mc); \ 4575 } \ 4576 } \ 4577 static const TypeInfo spapr_machine_##suffix##_info = { \ 4578 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4579 .parent = TYPE_SPAPR_MACHINE, \ 4580 .class_init = spapr_machine_##suffix##_class_init, \ 4581 }; \ 4582 static void spapr_machine_register_##suffix(void) \ 4583 { \ 4584 type_register(&spapr_machine_##suffix##_info); \ 4585 } \ 4586 type_init(spapr_machine_register_##suffix) 4587 4588 /* 4589 * pseries-5.0 4590 */ 4591 static void spapr_machine_5_0_class_options(MachineClass *mc) 4592 { 4593 /* Defaults for the latest behaviour inherited from the base class */ 4594 } 4595 4596 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4597 4598 /* 4599 * pseries-4.2 4600 */ 4601 static void spapr_machine_4_2_class_options(MachineClass *mc) 4602 { 4603 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4604 4605 spapr_machine_5_0_class_options(mc); 4606 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4607 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4608 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; 4609 mc->nvdimm_supported = false; 4610 } 4611 4612 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4613 4614 /* 4615 * pseries-4.1 4616 */ 4617 static void spapr_machine_4_1_class_options(MachineClass *mc) 4618 { 4619 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4620 static GlobalProperty compat[] = { 4621 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4622 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4623 }; 4624 4625 spapr_machine_4_2_class_options(mc); 4626 smc->linux_pci_probe = false; 4627 smc->smp_threads_vsmt = false; 4628 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4629 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4630 } 4631 4632 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4633 4634 /* 4635 * pseries-4.0 4636 */ 4637 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4638 uint64_t *buid, hwaddr *pio, 4639 hwaddr *mmio32, hwaddr *mmio64, 4640 unsigned n_dma, uint32_t *liobns, 4641 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4642 { 4643 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4644 nv2gpa, nv2atsd, errp); 4645 *nv2gpa = 0; 4646 *nv2atsd = 0; 4647 } 4648 4649 static void spapr_machine_4_0_class_options(MachineClass *mc) 4650 { 4651 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4652 4653 spapr_machine_4_1_class_options(mc); 4654 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4655 smc->phb_placement = phb_placement_4_0; 4656 smc->irq = &spapr_irq_xics; 4657 smc->pre_4_1_migration = true; 4658 } 4659 4660 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4661 4662 /* 4663 * pseries-3.1 4664 */ 4665 static void spapr_machine_3_1_class_options(MachineClass *mc) 4666 { 4667 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4668 4669 spapr_machine_4_0_class_options(mc); 4670 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4671 4672 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4673 smc->update_dt_enabled = false; 4674 smc->dr_phb_enabled = false; 4675 smc->broken_host_serial_model = true; 4676 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4677 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4678 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4679 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4680 } 4681 4682 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4683 4684 /* 4685 * pseries-3.0 4686 */ 4687 4688 static void spapr_machine_3_0_class_options(MachineClass *mc) 4689 { 4690 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4691 4692 spapr_machine_3_1_class_options(mc); 4693 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4694 4695 smc->legacy_irq_allocation = true; 4696 smc->nr_xirqs = 0x400; 4697 smc->irq = &spapr_irq_xics_legacy; 4698 } 4699 4700 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4701 4702 /* 4703 * pseries-2.12 4704 */ 4705 static void spapr_machine_2_12_class_options(MachineClass *mc) 4706 { 4707 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4708 static GlobalProperty compat[] = { 4709 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4710 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4711 }; 4712 4713 spapr_machine_3_0_class_options(mc); 4714 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4715 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4716 4717 /* We depend on kvm_enabled() to choose a default value for the 4718 * hpt-max-page-size capability. Of course we can't do it here 4719 * because this is too early and the HW accelerator isn't initialzed 4720 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4721 */ 4722 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4723 } 4724 4725 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4726 4727 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4728 { 4729 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4730 4731 spapr_machine_2_12_class_options(mc); 4732 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4733 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4734 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4735 } 4736 4737 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4738 4739 /* 4740 * pseries-2.11 4741 */ 4742 4743 static void spapr_machine_2_11_class_options(MachineClass *mc) 4744 { 4745 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4746 4747 spapr_machine_2_12_class_options(mc); 4748 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4749 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4750 } 4751 4752 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4753 4754 /* 4755 * pseries-2.10 4756 */ 4757 4758 static void spapr_machine_2_10_class_options(MachineClass *mc) 4759 { 4760 spapr_machine_2_11_class_options(mc); 4761 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4762 } 4763 4764 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4765 4766 /* 4767 * pseries-2.9 4768 */ 4769 4770 static void spapr_machine_2_9_class_options(MachineClass *mc) 4771 { 4772 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4773 static GlobalProperty compat[] = { 4774 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4775 }; 4776 4777 spapr_machine_2_10_class_options(mc); 4778 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4779 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4780 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4781 smc->pre_2_10_has_unused_icps = true; 4782 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4783 } 4784 4785 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4786 4787 /* 4788 * pseries-2.8 4789 */ 4790 4791 static void spapr_machine_2_8_class_options(MachineClass *mc) 4792 { 4793 static GlobalProperty compat[] = { 4794 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4795 }; 4796 4797 spapr_machine_2_9_class_options(mc); 4798 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4799 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4800 mc->numa_mem_align_shift = 23; 4801 } 4802 4803 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4804 4805 /* 4806 * pseries-2.7 4807 */ 4808 4809 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4810 uint64_t *buid, hwaddr *pio, 4811 hwaddr *mmio32, hwaddr *mmio64, 4812 unsigned n_dma, uint32_t *liobns, 4813 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4814 { 4815 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4816 const uint64_t base_buid = 0x800000020000000ULL; 4817 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4818 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4819 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4820 const uint32_t max_index = 255; 4821 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4822 4823 uint64_t ram_top = MACHINE(spapr)->ram_size; 4824 hwaddr phb0_base, phb_base; 4825 int i; 4826 4827 /* Do we have device memory? */ 4828 if (MACHINE(spapr)->maxram_size > ram_top) { 4829 /* Can't just use maxram_size, because there may be an 4830 * alignment gap between normal and device memory regions 4831 */ 4832 ram_top = MACHINE(spapr)->device_memory->base + 4833 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4834 } 4835 4836 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4837 4838 if (index > max_index) { 4839 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4840 max_index); 4841 return; 4842 } 4843 4844 *buid = base_buid + index; 4845 for (i = 0; i < n_dma; ++i) { 4846 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4847 } 4848 4849 phb_base = phb0_base + index * phb_spacing; 4850 *pio = phb_base + pio_offset; 4851 *mmio32 = phb_base + mmio_offset; 4852 /* 4853 * We don't set the 64-bit MMIO window, relying on the PHB's 4854 * fallback behaviour of automatically splitting a large "32-bit" 4855 * window into contiguous 32-bit and 64-bit windows 4856 */ 4857 4858 *nv2gpa = 0; 4859 *nv2atsd = 0; 4860 } 4861 4862 static void spapr_machine_2_7_class_options(MachineClass *mc) 4863 { 4864 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4865 static GlobalProperty compat[] = { 4866 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4867 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4868 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4869 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4870 }; 4871 4872 spapr_machine_2_8_class_options(mc); 4873 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4874 mc->default_machine_opts = "modern-hotplug-events=off"; 4875 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4876 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4877 smc->phb_placement = phb_placement_2_7; 4878 } 4879 4880 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4881 4882 /* 4883 * pseries-2.6 4884 */ 4885 4886 static void spapr_machine_2_6_class_options(MachineClass *mc) 4887 { 4888 static GlobalProperty compat[] = { 4889 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4890 }; 4891 4892 spapr_machine_2_7_class_options(mc); 4893 mc->has_hotpluggable_cpus = false; 4894 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4895 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4896 } 4897 4898 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4899 4900 /* 4901 * pseries-2.5 4902 */ 4903 4904 static void spapr_machine_2_5_class_options(MachineClass *mc) 4905 { 4906 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4907 static GlobalProperty compat[] = { 4908 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4909 }; 4910 4911 spapr_machine_2_6_class_options(mc); 4912 smc->use_ohci_by_default = true; 4913 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4914 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4915 } 4916 4917 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4918 4919 /* 4920 * pseries-2.4 4921 */ 4922 4923 static void spapr_machine_2_4_class_options(MachineClass *mc) 4924 { 4925 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4926 4927 spapr_machine_2_5_class_options(mc); 4928 smc->dr_lmb_enabled = false; 4929 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4930 } 4931 4932 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4933 4934 /* 4935 * pseries-2.3 4936 */ 4937 4938 static void spapr_machine_2_3_class_options(MachineClass *mc) 4939 { 4940 static GlobalProperty compat[] = { 4941 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4942 }; 4943 spapr_machine_2_4_class_options(mc); 4944 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4945 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4946 } 4947 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4948 4949 /* 4950 * pseries-2.2 4951 */ 4952 4953 static void spapr_machine_2_2_class_options(MachineClass *mc) 4954 { 4955 static GlobalProperty compat[] = { 4956 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4957 }; 4958 4959 spapr_machine_2_3_class_options(mc); 4960 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4961 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4962 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4963 } 4964 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4965 4966 /* 4967 * pseries-2.1 4968 */ 4969 4970 static void spapr_machine_2_1_class_options(MachineClass *mc) 4971 { 4972 spapr_machine_2_2_class_options(mc); 4973 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4974 } 4975 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4976 4977 static void spapr_machine_register_types(void) 4978 { 4979 type_register_static(&spapr_machine_info); 4980 } 4981 4982 type_init(spapr_machine_register_types) 4983