1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "qemu/log.h" 42 #include "hw/fw-path-provider.h" 43 #include "elf.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/cpus.h" 47 #include "sysemu/hw_accel.h" 48 #include "kvm_ppc.h" 49 #include "migration/misc.h" 50 #include "migration/qemu-file-types.h" 51 #include "migration/global_state.h" 52 #include "migration/register.h" 53 #include "migration/blocker.h" 54 #include "mmu-hash64.h" 55 #include "mmu-book3s-v3.h" 56 #include "cpu-models.h" 57 #include "hw/core/cpu.h" 58 59 #include "hw/ppc/ppc.h" 60 #include "hw/loader.h" 61 62 #include "hw/ppc/fdt.h" 63 #include "hw/ppc/spapr.h" 64 #include "hw/ppc/spapr_nested.h" 65 #include "hw/ppc/spapr_vio.h" 66 #include "hw/ppc/vof.h" 67 #include "hw/qdev-properties.h" 68 #include "hw/pci-host/spapr.h" 69 #include "hw/pci/msi.h" 70 71 #include "hw/pci/pci.h" 72 #include "hw/scsi/scsi.h" 73 #include "hw/virtio/virtio-scsi.h" 74 #include "hw/virtio/vhost-scsi-common.h" 75 76 #include "exec/ram_addr.h" 77 #include "hw/usb.h" 78 #include "qemu/config-file.h" 79 #include "qemu/error-report.h" 80 #include "trace.h" 81 #include "hw/nmi.h" 82 #include "hw/intc/intc.h" 83 84 #include "hw/ppc/spapr_cpu_core.h" 85 #include "hw/mem/memory-device.h" 86 #include "hw/ppc/spapr_tpm_proxy.h" 87 #include "hw/ppc/spapr_nvdimm.h" 88 #include "hw/ppc/spapr_numa.h" 89 #include "hw/ppc/pef.h" 90 91 #include "monitor/monitor.h" 92 93 #include <libfdt.h> 94 95 /* SLOF memory layout: 96 * 97 * SLOF raw image loaded at 0, copies its romfs right below the flat 98 * device-tree, then position SLOF itself 31M below that 99 * 100 * So we set FW_OVERHEAD to 40MB which should account for all of that 101 * and more 102 * 103 * We load our kernel at 4M, leaving space for SLOF initial image 104 */ 105 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 106 #define FW_MAX_SIZE 0x400000 107 #define FW_FILE_NAME "slof.bin" 108 #define FW_FILE_NAME_VOF "vof.bin" 109 #define FW_OVERHEAD 0x2800000 110 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 111 112 #define MIN_RMA_SLOF (128 * MiB) 113 114 #define PHANDLE_INTC 0x00001111 115 116 /* These two functions implement the VCPU id numbering: one to compute them 117 * all and one to identify thread 0 of a VCORE. Any change to the first one 118 * is likely to have an impact on the second one, so let's keep them close. 119 */ 120 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 121 { 122 MachineState *ms = MACHINE(spapr); 123 unsigned int smp_threads = ms->smp.threads; 124 125 assert(spapr->vsmt); 126 return 127 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 128 } 129 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 130 PowerPCCPU *cpu) 131 { 132 assert(spapr->vsmt); 133 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 134 } 135 136 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 137 { 138 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 139 * and newer QEMUs don't even have them. In both cases, we don't want 140 * to send anything on the wire. 141 */ 142 return false; 143 } 144 145 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 146 /* 147 * Hack ahead. We can't have two devices with the same name and 148 * instance id. So I rename this to pass make check. 149 * Real help from people who knows the hardware is needed. 150 */ 151 .name = "icp/server", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .needed = pre_2_10_vmstate_dummy_icp_needed, 155 .fields = (const VMStateField[]) { 156 VMSTATE_UNUSED(4), /* uint32_t xirr */ 157 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 158 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 159 VMSTATE_END_OF_LIST() 160 }, 161 }; 162 163 /* 164 * See comment in hw/intc/xics.c:icp_realize() 165 * 166 * You have to remove vmstate_replace_hack_for_ppc() when you remove 167 * the machine types that need the following function. 168 */ 169 static void pre_2_10_vmstate_register_dummy_icp(int i) 170 { 171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 172 (void *)(uintptr_t) i); 173 } 174 175 /* 176 * See comment in hw/intc/xics.c:icp_realize() 177 * 178 * You have to remove vmstate_replace_hack_for_ppc() when you remove 179 * the machine types that need the following function. 180 */ 181 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 182 { 183 /* 184 * This used to be: 185 * 186 * vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 187 * (void *)(uintptr_t) i); 188 */ 189 } 190 191 int spapr_max_server_number(SpaprMachineState *spapr) 192 { 193 MachineState *ms = MACHINE(spapr); 194 195 assert(spapr->vsmt); 196 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 197 } 198 199 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 200 int smt_threads) 201 { 202 int i, ret = 0; 203 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 204 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 205 int index = spapr_get_vcpu_id(cpu); 206 207 if (cpu->compat_pvr) { 208 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 209 if (ret < 0) { 210 return ret; 211 } 212 } 213 214 /* Build interrupt servers and gservers properties */ 215 for (i = 0; i < smt_threads; i++) { 216 servers_prop[i] = cpu_to_be32(index + i); 217 /* Hack, direct the group queues back to cpu 0 */ 218 gservers_prop[i*2] = cpu_to_be32(index + i); 219 gservers_prop[i*2 + 1] = 0; 220 } 221 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 222 servers_prop, sizeof(*servers_prop) * smt_threads); 223 if (ret < 0) { 224 return ret; 225 } 226 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 227 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 228 229 return ret; 230 } 231 232 static void spapr_dt_pa_features(SpaprMachineState *spapr, 233 PowerPCCPU *cpu, 234 void *fdt, int offset) 235 { 236 /* 237 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 238 * but not MTTCG, so disable it. To advertise it, a cap would have 239 * to be added, or support implemented for MTTCG. 240 * 241 * Copy/paste is not supported by TCG, so it is not advertised. KVM 242 * can execute them but it has no accelerator drivers which are usable, 243 * so there isn't much need for it anyway. 244 */ 245 246 /* These should be kept in sync with pnv */ 247 uint8_t pa_features_206[] = { 6, 0, 248 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 249 uint8_t pa_features_207[] = { 24, 0, 250 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 251 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 252 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 254 uint8_t pa_features_300[] = { 66, 0, 255 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 256 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 257 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 258 /* 6: DS207 */ 259 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 260 /* 16: Vector */ 261 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 262 /* 18: Vec. Scalar, 20: Vec. XOR */ 263 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 264 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 265 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 266 /* 32: LE atomic, 34: EBB + ext EBB */ 267 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 268 /* 40: Radix MMU */ 269 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 270 /* 42: PM, 44: PC RA, 46: SC vec'd */ 271 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 272 /* 48: SIMD, 50: QP BFP, 52: String */ 273 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 274 /* 54: DecFP, 56: DecI, 58: SHA */ 275 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 276 /* 60: NM atomic, 62: RNG */ 277 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 278 }; 279 /* 3.1 removes SAO, HTM support */ 280 uint8_t pa_features_31[] = { 74, 0, 281 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 282 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 283 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 284 /* 6: DS207 */ 285 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 286 /* 16: Vector */ 287 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 288 /* 18: Vec. Scalar, 20: Vec. XOR */ 289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 290 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 292 /* 32: LE atomic, 34: EBB + ext EBB */ 293 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 294 /* 40: Radix MMU */ 295 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 296 /* 42: PM, 44: PC RA, 46: SC vec'd */ 297 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 298 /* 48: SIMD, 50: QP BFP, 52: String */ 299 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 300 /* 54: DecFP, 56: DecI, 58: SHA */ 301 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 302 /* 60: NM atomic, 62: RNG */ 303 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 304 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 305 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 306 /* 72: [P]HASHST/[P]HASHCHK */ 307 0x80, 0x00, /* 72 - 73 */ 308 }; 309 uint8_t *pa_features = NULL; 310 size_t pa_size; 311 312 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 313 pa_features = pa_features_206; 314 pa_size = sizeof(pa_features_206); 315 } 316 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 317 pa_features = pa_features_207; 318 pa_size = sizeof(pa_features_207); 319 } 320 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 321 pa_features = pa_features_300; 322 pa_size = sizeof(pa_features_300); 323 } 324 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) { 325 pa_features = pa_features_31; 326 pa_size = sizeof(pa_features_31); 327 } 328 if (!pa_features) { 329 return; 330 } 331 332 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 333 /* 334 * Note: we keep CI large pages off by default because a 64K capable 335 * guest provisioned with large pages might otherwise try to map a qemu 336 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 337 * even if that qemu runs on a 4k host. 338 * We dd this bit back here if we are confident this is not an issue 339 */ 340 pa_features[3] |= 0x20; 341 } 342 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 343 pa_features[24] |= 0x80; /* Transactional memory support */ 344 } 345 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 346 /* Workaround for broken kernels that attempt (guest) radix 347 * mode when they can't handle it, if they see the radix bit set 348 * in pa-features. So hide it from them. */ 349 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 350 } 351 352 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 353 } 354 355 static hwaddr spapr_node0_size(MachineState *machine) 356 { 357 if (machine->numa_state->num_nodes) { 358 int i; 359 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 360 if (machine->numa_state->nodes[i].node_mem) { 361 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 362 machine->ram_size); 363 } 364 } 365 } 366 return machine->ram_size; 367 } 368 369 static void add_str(GString *s, const gchar *s1) 370 { 371 g_string_append_len(s, s1, strlen(s1) + 1); 372 } 373 374 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 375 hwaddr start, hwaddr size) 376 { 377 char mem_name[32]; 378 uint64_t mem_reg_property[2]; 379 int off; 380 381 mem_reg_property[0] = cpu_to_be64(start); 382 mem_reg_property[1] = cpu_to_be64(size); 383 384 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 385 off = fdt_add_subnode(fdt, 0, mem_name); 386 _FDT(off); 387 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 388 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 389 sizeof(mem_reg_property)))); 390 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 391 return off; 392 } 393 394 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 395 { 396 MemoryDeviceInfoList *info; 397 398 for (info = list; info; info = info->next) { 399 MemoryDeviceInfo *value = info->value; 400 401 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 402 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 403 404 if (addr >= pcdimm_info->addr && 405 addr < (pcdimm_info->addr + pcdimm_info->size)) { 406 return pcdimm_info->node; 407 } 408 } 409 } 410 411 return -1; 412 } 413 414 struct sPAPRDrconfCellV2 { 415 uint32_t seq_lmbs; 416 uint64_t base_addr; 417 uint32_t drc_index; 418 uint32_t aa_index; 419 uint32_t flags; 420 } QEMU_PACKED; 421 422 typedef struct DrconfCellQueue { 423 struct sPAPRDrconfCellV2 cell; 424 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 425 } DrconfCellQueue; 426 427 static DrconfCellQueue * 428 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 429 uint32_t drc_index, uint32_t aa_index, 430 uint32_t flags) 431 { 432 DrconfCellQueue *elem; 433 434 elem = g_malloc0(sizeof(*elem)); 435 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 436 elem->cell.base_addr = cpu_to_be64(base_addr); 437 elem->cell.drc_index = cpu_to_be32(drc_index); 438 elem->cell.aa_index = cpu_to_be32(aa_index); 439 elem->cell.flags = cpu_to_be32(flags); 440 441 return elem; 442 } 443 444 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 445 int offset, MemoryDeviceInfoList *dimms) 446 { 447 MachineState *machine = MACHINE(spapr); 448 uint8_t *int_buf, *cur_index; 449 int ret; 450 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 451 uint64_t addr, cur_addr, size; 452 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 453 uint64_t mem_end = machine->device_memory->base + 454 memory_region_size(&machine->device_memory->mr); 455 uint32_t node, buf_len, nr_entries = 0; 456 SpaprDrc *drc; 457 DrconfCellQueue *elem, *next; 458 MemoryDeviceInfoList *info; 459 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 460 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 461 462 /* Entry to cover RAM and the gap area */ 463 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 464 SPAPR_LMB_FLAGS_RESERVED | 465 SPAPR_LMB_FLAGS_DRC_INVALID); 466 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 467 nr_entries++; 468 469 cur_addr = machine->device_memory->base; 470 for (info = dimms; info; info = info->next) { 471 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 472 473 addr = di->addr; 474 size = di->size; 475 node = di->node; 476 477 /* 478 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 479 * area is marked hotpluggable in the next iteration for the bigger 480 * chunk including the NVDIMM occupied area. 481 */ 482 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 483 continue; 484 485 /* Entry for hot-pluggable area */ 486 if (cur_addr < addr) { 487 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 488 g_assert(drc); 489 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 490 cur_addr, spapr_drc_index(drc), -1, 0); 491 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 492 nr_entries++; 493 } 494 495 /* Entry for DIMM */ 496 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 497 g_assert(drc); 498 elem = spapr_get_drconf_cell(size / lmb_size, addr, 499 spapr_drc_index(drc), node, 500 (SPAPR_LMB_FLAGS_ASSIGNED | 501 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 502 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 503 nr_entries++; 504 cur_addr = addr + size; 505 } 506 507 /* Entry for remaining hotpluggable area */ 508 if (cur_addr < mem_end) { 509 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 510 g_assert(drc); 511 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 512 cur_addr, spapr_drc_index(drc), -1, 0); 513 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 514 nr_entries++; 515 } 516 517 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 518 int_buf = cur_index = g_malloc0(buf_len); 519 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 520 cur_index += sizeof(nr_entries); 521 522 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 523 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 524 cur_index += sizeof(elem->cell); 525 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 526 g_free(elem); 527 } 528 529 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 530 g_free(int_buf); 531 if (ret < 0) { 532 return -1; 533 } 534 return 0; 535 } 536 537 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 538 int offset, MemoryDeviceInfoList *dimms) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int i, ret; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 544 uint32_t nr_lmbs = (machine->device_memory->base + 545 memory_region_size(&machine->device_memory->mr)) / 546 lmb_size; 547 uint32_t *int_buf, *cur_index, buf_len; 548 549 /* 550 * Allocate enough buffer size to fit in ibm,dynamic-memory 551 */ 552 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 553 cur_index = int_buf = g_malloc0(buf_len); 554 int_buf[0] = cpu_to_be32(nr_lmbs); 555 cur_index++; 556 for (i = 0; i < nr_lmbs; i++) { 557 uint64_t addr = i * lmb_size; 558 uint32_t *dynamic_memory = cur_index; 559 560 if (i >= device_lmb_start) { 561 SpaprDrc *drc; 562 563 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 564 g_assert(drc); 565 566 dynamic_memory[0] = cpu_to_be32(addr >> 32); 567 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 568 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 569 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 570 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 571 if (memory_region_present(get_system_memory(), addr)) { 572 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 573 } else { 574 dynamic_memory[5] = cpu_to_be32(0); 575 } 576 } else { 577 /* 578 * LMB information for RMA, boot time RAM and gap b/n RAM and 579 * device memory region -- all these are marked as reserved 580 * and as having no valid DRC. 581 */ 582 dynamic_memory[0] = cpu_to_be32(addr >> 32); 583 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 584 dynamic_memory[2] = cpu_to_be32(0); 585 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 586 dynamic_memory[4] = cpu_to_be32(-1); 587 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 588 SPAPR_LMB_FLAGS_DRC_INVALID); 589 } 590 591 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 592 } 593 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 594 g_free(int_buf); 595 if (ret < 0) { 596 return -1; 597 } 598 return 0; 599 } 600 601 /* 602 * Adds ibm,dynamic-reconfiguration-memory node. 603 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 604 * of this device tree node. 605 */ 606 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 607 void *fdt) 608 { 609 MachineState *machine = MACHINE(spapr); 610 int ret, offset; 611 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 612 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 613 cpu_to_be32(lmb_size & 0xffffffff)}; 614 MemoryDeviceInfoList *dimms = NULL; 615 616 /* Don't create the node if there is no device memory. */ 617 if (!machine->device_memory) { 618 return 0; 619 } 620 621 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 622 623 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 624 sizeof(prop_lmb_size)); 625 if (ret < 0) { 626 return ret; 627 } 628 629 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 630 if (ret < 0) { 631 return ret; 632 } 633 634 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 635 if (ret < 0) { 636 return ret; 637 } 638 639 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 640 dimms = qmp_memory_device_list(); 641 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 642 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 643 } else { 644 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 645 } 646 qapi_free_MemoryDeviceInfoList(dimms); 647 648 if (ret < 0) { 649 return ret; 650 } 651 652 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 653 654 return ret; 655 } 656 657 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 658 { 659 MachineState *machine = MACHINE(spapr); 660 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 661 hwaddr mem_start, node_size; 662 int i, nb_nodes = machine->numa_state->num_nodes; 663 NodeInfo *nodes = machine->numa_state->nodes; 664 665 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 666 if (!nodes[i].node_mem) { 667 continue; 668 } 669 if (mem_start >= machine->ram_size) { 670 node_size = 0; 671 } else { 672 node_size = nodes[i].node_mem; 673 if (node_size > machine->ram_size - mem_start) { 674 node_size = machine->ram_size - mem_start; 675 } 676 } 677 if (!mem_start) { 678 /* spapr_machine_init() checks for rma_size <= node0_size 679 * already */ 680 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 681 mem_start += spapr->rma_size; 682 node_size -= spapr->rma_size; 683 } 684 for ( ; node_size; ) { 685 hwaddr sizetmp = pow2floor(node_size); 686 687 /* mem_start != 0 here */ 688 if (ctzl(mem_start) < ctzl(sizetmp)) { 689 sizetmp = 1ULL << ctzl(mem_start); 690 } 691 692 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 693 node_size -= sizetmp; 694 mem_start += sizetmp; 695 } 696 } 697 698 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 699 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 700 int ret; 701 702 g_assert(smc->dr_lmb_enabled); 703 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 704 if (ret) { 705 return ret; 706 } 707 } 708 709 return 0; 710 } 711 712 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 713 SpaprMachineState *spapr) 714 { 715 MachineState *ms = MACHINE(spapr); 716 PowerPCCPU *cpu = POWERPC_CPU(cs); 717 CPUPPCState *env = &cpu->env; 718 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 719 int index = spapr_get_vcpu_id(cpu); 720 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 721 0xffffffff, 0xffffffff}; 722 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 723 : SPAPR_TIMEBASE_FREQ; 724 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 725 uint32_t page_sizes_prop[64]; 726 size_t page_sizes_prop_size; 727 unsigned int smp_threads = ms->smp.threads; 728 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 729 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 730 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 731 SpaprDrc *drc; 732 int drc_index; 733 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 734 int i; 735 736 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 737 if (drc) { 738 drc_index = spapr_drc_index(drc); 739 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 740 } 741 742 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 743 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 744 745 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 746 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 747 env->dcache_line_size))); 748 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 749 env->dcache_line_size))); 750 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 751 env->icache_line_size))); 752 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 753 env->icache_line_size))); 754 755 if (pcc->l1_dcache_size) { 756 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 757 pcc->l1_dcache_size))); 758 } else { 759 warn_report("Unknown L1 dcache size for cpu"); 760 } 761 if (pcc->l1_icache_size) { 762 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 763 pcc->l1_icache_size))); 764 } else { 765 warn_report("Unknown L1 icache size for cpu"); 766 } 767 768 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 769 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 770 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 771 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 772 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 773 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 774 775 if (ppc_has_spr(cpu, SPR_PURR)) { 776 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 777 } 778 if (ppc_has_spr(cpu, SPR_PURR)) { 779 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 780 } 781 782 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 783 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 784 segs, sizeof(segs)))); 785 } 786 787 /* Advertise VSX (vector extensions) if available 788 * 1 == VMX / Altivec available 789 * 2 == VSX available 790 * 791 * Only CPUs for which we create core types in spapr_cpu_core.c 792 * are possible, and all of those have VMX */ 793 if (env->insns_flags & PPC_ALTIVEC) { 794 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 795 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 796 } else { 797 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 798 } 799 } 800 801 /* Advertise DFP (Decimal Floating Point) if available 802 * 0 / no property == no DFP 803 * 1 == DFP available */ 804 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 805 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 806 } 807 808 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 809 sizeof(page_sizes_prop)); 810 if (page_sizes_prop_size) { 811 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 812 page_sizes_prop, page_sizes_prop_size))); 813 } 814 815 spapr_dt_pa_features(spapr, cpu, fdt, offset); 816 817 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 818 cs->cpu_index / vcpus_per_socket))); 819 820 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 821 pft_size_prop, sizeof(pft_size_prop)))); 822 823 if (ms->numa_state->num_nodes > 1) { 824 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 825 } 826 827 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 828 829 if (pcc->radix_page_info) { 830 for (i = 0; i < pcc->radix_page_info->count; i++) { 831 radix_AP_encodings[i] = 832 cpu_to_be32(pcc->radix_page_info->entries[i]); 833 } 834 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 835 radix_AP_encodings, 836 pcc->radix_page_info->count * 837 sizeof(radix_AP_encodings[0])))); 838 } 839 840 /* 841 * We set this property to let the guest know that it can use the large 842 * decrementer and its width in bits. 843 */ 844 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 845 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 846 pcc->lrg_decr_bits))); 847 } 848 849 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 850 int cpus_offset) 851 { 852 PowerPCCPU *cpu = POWERPC_CPU(cs); 853 int index = spapr_get_vcpu_id(cpu); 854 DeviceClass *dc = DEVICE_GET_CLASS(cs); 855 g_autofree char *nodename = NULL; 856 int offset; 857 858 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 859 return; 860 } 861 862 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 863 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 864 _FDT(offset); 865 spapr_dt_cpu(cs, fdt, offset, spapr); 866 } 867 868 869 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 870 { 871 CPUState **rev; 872 CPUState *cs; 873 int n_cpus; 874 int cpus_offset; 875 int i; 876 877 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 878 _FDT(cpus_offset); 879 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 880 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 881 882 /* 883 * We walk the CPUs in reverse order to ensure that CPU DT nodes 884 * created by fdt_add_subnode() end up in the right order in FDT 885 * for the guest kernel the enumerate the CPUs correctly. 886 * 887 * The CPU list cannot be traversed in reverse order, so we need 888 * to do extra work. 889 */ 890 n_cpus = 0; 891 rev = NULL; 892 CPU_FOREACH(cs) { 893 rev = g_renew(CPUState *, rev, n_cpus + 1); 894 rev[n_cpus++] = cs; 895 } 896 897 for (i = n_cpus - 1; i >= 0; i--) { 898 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 899 } 900 901 g_free(rev); 902 } 903 904 static int spapr_dt_rng(void *fdt) 905 { 906 int node; 907 int ret; 908 909 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 910 if (node <= 0) { 911 return -1; 912 } 913 ret = fdt_setprop_string(fdt, node, "device_type", 914 "ibm,platform-facilities"); 915 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 916 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 917 918 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 919 if (node <= 0) { 920 return -1; 921 } 922 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 923 924 return ret ? -1 : 0; 925 } 926 927 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 928 { 929 MachineState *ms = MACHINE(spapr); 930 int rtas; 931 GString *hypertas = g_string_sized_new(256); 932 GString *qemu_hypertas = g_string_sized_new(256); 933 uint32_t lrdr_capacity[] = { 934 0, 935 0, 936 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 937 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 938 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 939 }; 940 941 /* Do we have device memory? */ 942 if (MACHINE(spapr)->device_memory) { 943 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 944 memory_region_size(&MACHINE(spapr)->device_memory->mr); 945 946 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 947 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 948 } 949 950 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 951 952 /* hypertas */ 953 add_str(hypertas, "hcall-pft"); 954 add_str(hypertas, "hcall-term"); 955 add_str(hypertas, "hcall-dabr"); 956 add_str(hypertas, "hcall-interrupt"); 957 add_str(hypertas, "hcall-tce"); 958 add_str(hypertas, "hcall-vio"); 959 add_str(hypertas, "hcall-splpar"); 960 add_str(hypertas, "hcall-join"); 961 add_str(hypertas, "hcall-bulk"); 962 add_str(hypertas, "hcall-set-mode"); 963 add_str(hypertas, "hcall-sprg0"); 964 add_str(hypertas, "hcall-copy"); 965 add_str(hypertas, "hcall-debug"); 966 add_str(hypertas, "hcall-vphn"); 967 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 968 add_str(hypertas, "hcall-rpt-invalidate"); 969 } 970 971 add_str(qemu_hypertas, "hcall-memop1"); 972 973 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 974 add_str(hypertas, "hcall-multi-tce"); 975 } 976 977 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 978 add_str(hypertas, "hcall-hpt-resize"); 979 } 980 981 add_str(hypertas, "hcall-watchdog"); 982 983 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 984 hypertas->str, hypertas->len)); 985 g_string_free(hypertas, TRUE); 986 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 987 qemu_hypertas->str, qemu_hypertas->len)); 988 g_string_free(qemu_hypertas, TRUE); 989 990 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 991 992 /* 993 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 994 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 995 * 996 * The system reset requirements are driven by existing Linux and PowerVM 997 * implementation which (contrary to PAPR) saves r3 in the error log 998 * structure like machine check, so Linux expects to find the saved r3 999 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 1000 * does not look at the error value). 1001 * 1002 * System reset interrupts are not subject to interlock like machine 1003 * check, so this memory area could be corrupted if the sreset is 1004 * interrupted by a machine check (or vice versa) if it was shared. To 1005 * prevent this, system reset uses per-CPU areas for the sreset save 1006 * area. A system reset that interrupts a system reset handler could 1007 * still overwrite this area, but Linux doesn't try to recover in that 1008 * case anyway. 1009 * 1010 * The extra 8 bytes is required because Linux's FWNMI error log check 1011 * is off-by-one. 1012 * 1013 * RTAS_MIN_SIZE is required for the RTAS blob itself. 1014 */ 1015 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 1016 RTAS_ERROR_LOG_MAX + 1017 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 1018 sizeof(uint64_t))); 1019 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1020 RTAS_ERROR_LOG_MAX)); 1021 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1022 RTAS_EVENT_SCAN_RATE)); 1023 1024 g_assert(msi_nonbroken); 1025 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1026 1027 /* 1028 * According to PAPR, rtas ibm,os-term does not guarantee a return 1029 * back to the guest cpu. 1030 * 1031 * While an additional ibm,extended-os-term property indicates 1032 * that rtas call return will always occur. Set this property. 1033 */ 1034 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1035 1036 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1037 lrdr_capacity, sizeof(lrdr_capacity))); 1038 1039 spapr_dt_rtas_tokens(fdt, rtas); 1040 } 1041 1042 /* 1043 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1044 * and the XIVE features that the guest may request and thus the valid 1045 * values for bytes 23..26 of option vector 5: 1046 */ 1047 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1048 int chosen) 1049 { 1050 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1051 1052 char val[2 * 4] = { 1053 23, 0x00, /* XICS / XIVE mode */ 1054 24, 0x00, /* Hash/Radix, filled in below. */ 1055 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1056 26, 0x40, /* Radix options: GTSE == yes. */ 1057 }; 1058 1059 if (spapr->irq->xics && spapr->irq->xive) { 1060 val[1] = SPAPR_OV5_XIVE_BOTH; 1061 } else if (spapr->irq->xive) { 1062 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1063 } else { 1064 assert(spapr->irq->xics); 1065 val[1] = SPAPR_OV5_XIVE_LEGACY; 1066 } 1067 1068 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1069 first_ppc_cpu->compat_pvr)) { 1070 /* 1071 * If we're in a pre POWER9 compat mode then the guest should 1072 * do hash and use the legacy interrupt mode 1073 */ 1074 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1075 val[3] = 0x00; /* Hash */ 1076 spapr_check_mmu_mode(false); 1077 } else if (kvm_enabled()) { 1078 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1079 val[3] = 0x80; /* OV5_MMU_BOTH */ 1080 } else if (kvmppc_has_cap_mmu_radix()) { 1081 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1082 } else { 1083 val[3] = 0x00; /* Hash */ 1084 } 1085 } else { 1086 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1087 val[3] = 0xC0; 1088 } 1089 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1090 val, sizeof(val))); 1091 } 1092 1093 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1094 { 1095 MachineState *machine = MACHINE(spapr); 1096 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1097 int chosen; 1098 1099 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1100 1101 if (reset) { 1102 const char *boot_device = spapr->boot_device; 1103 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1104 size_t cb = 0; 1105 g_autofree char *bootlist = get_boot_devices_list(&cb); 1106 1107 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1108 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1109 machine->kernel_cmdline)); 1110 } 1111 1112 if (spapr->initrd_size) { 1113 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1114 spapr->initrd_base)); 1115 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1116 spapr->initrd_base + spapr->initrd_size)); 1117 } 1118 1119 if (spapr->kernel_size) { 1120 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1121 cpu_to_be64(spapr->kernel_size) }; 1122 1123 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1124 &kprop, sizeof(kprop))); 1125 if (spapr->kernel_le) { 1126 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1127 } 1128 } 1129 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1130 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1131 } 1132 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1133 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1134 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1135 1136 if (cb && bootlist) { 1137 int i; 1138 1139 for (i = 0; i < cb; i++) { 1140 if (bootlist[i] == '\n') { 1141 bootlist[i] = ' '; 1142 } 1143 } 1144 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1145 } 1146 1147 if (boot_device && strlen(boot_device)) { 1148 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1149 } 1150 1151 if (spapr->want_stdout_path && stdout_path) { 1152 /* 1153 * "linux,stdout-path" and "stdout" properties are 1154 * deprecated by linux kernel. New platforms should only 1155 * use the "stdout-path" property. Set the new property 1156 * and continue using older property to remain compatible 1157 * with the existing firmware. 1158 */ 1159 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1160 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1161 } 1162 1163 /* 1164 * We can deal with BAR reallocation just fine, advertise it 1165 * to the guest 1166 */ 1167 if (smc->linux_pci_probe) { 1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1169 } 1170 1171 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1172 } 1173 1174 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1175 1176 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1177 } 1178 1179 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1180 { 1181 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1182 * KVM to work under pHyp with some guest co-operation */ 1183 int hypervisor; 1184 uint8_t hypercall[16]; 1185 1186 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1187 /* indicate KVM hypercall interface */ 1188 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1189 if (kvmppc_has_cap_fixup_hcalls()) { 1190 /* 1191 * Older KVM versions with older guest kernels were broken 1192 * with the magic page, don't allow the guest to map it. 1193 */ 1194 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1195 sizeof(hypercall))) { 1196 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1197 hypercall, sizeof(hypercall))); 1198 } 1199 } 1200 } 1201 1202 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1203 { 1204 MachineState *machine = MACHINE(spapr); 1205 MachineClass *mc = MACHINE_GET_CLASS(machine); 1206 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1207 uint32_t root_drc_type_mask = 0; 1208 int ret; 1209 void *fdt; 1210 SpaprPhbState *phb; 1211 char *buf; 1212 1213 fdt = g_malloc0(space); 1214 _FDT((fdt_create_empty_tree(fdt, space))); 1215 1216 /* Root node */ 1217 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1218 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1219 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1220 1221 /* Guest UUID & Name*/ 1222 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1223 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1224 if (qemu_uuid_set) { 1225 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1226 } 1227 g_free(buf); 1228 1229 if (qemu_get_vm_name()) { 1230 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1231 qemu_get_vm_name())); 1232 } 1233 1234 /* Host Model & Serial Number */ 1235 if (spapr->host_model) { 1236 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1237 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1238 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1239 g_free(buf); 1240 } 1241 1242 if (spapr->host_serial) { 1243 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1244 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1245 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1246 g_free(buf); 1247 } 1248 1249 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1250 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1251 1252 /* /interrupt controller */ 1253 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1254 1255 ret = spapr_dt_memory(spapr, fdt); 1256 if (ret < 0) { 1257 error_report("couldn't setup memory nodes in fdt"); 1258 exit(1); 1259 } 1260 1261 /* /vdevice */ 1262 spapr_dt_vdevice(spapr->vio_bus, fdt); 1263 1264 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1265 ret = spapr_dt_rng(fdt); 1266 if (ret < 0) { 1267 error_report("could not set up rng device in the fdt"); 1268 exit(1); 1269 } 1270 } 1271 1272 QLIST_FOREACH(phb, &spapr->phbs, list) { 1273 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1274 if (ret < 0) { 1275 error_report("couldn't setup PCI devices in fdt"); 1276 exit(1); 1277 } 1278 } 1279 1280 spapr_dt_cpus(fdt, spapr); 1281 1282 /* ibm,drc-indexes and friends */ 1283 if (smc->dr_lmb_enabled) { 1284 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1285 } 1286 if (smc->dr_phb_enabled) { 1287 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1288 } 1289 if (mc->nvdimm_supported) { 1290 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1291 } 1292 if (root_drc_type_mask) { 1293 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1294 } 1295 1296 if (mc->has_hotpluggable_cpus) { 1297 int offset = fdt_path_offset(fdt, "/cpus"); 1298 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1299 if (ret < 0) { 1300 error_report("Couldn't set up CPU DR device tree properties"); 1301 exit(1); 1302 } 1303 } 1304 1305 /* /event-sources */ 1306 spapr_dt_events(spapr, fdt); 1307 1308 /* /rtas */ 1309 spapr_dt_rtas(spapr, fdt); 1310 1311 /* /chosen */ 1312 spapr_dt_chosen(spapr, fdt, reset); 1313 1314 /* /hypervisor */ 1315 if (kvm_enabled()) { 1316 spapr_dt_hypervisor(spapr, fdt); 1317 } 1318 1319 /* Build memory reserve map */ 1320 if (reset) { 1321 if (spapr->kernel_size) { 1322 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1323 spapr->kernel_size))); 1324 } 1325 if (spapr->initrd_size) { 1326 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1327 spapr->initrd_size))); 1328 } 1329 } 1330 1331 /* NVDIMM devices */ 1332 if (mc->nvdimm_supported) { 1333 spapr_dt_persistent_memory(spapr, fdt); 1334 } 1335 1336 return fdt; 1337 } 1338 1339 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1340 { 1341 SpaprMachineState *spapr = opaque; 1342 1343 return (addr & 0x0fffffff) + spapr->kernel_addr; 1344 } 1345 1346 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1347 PowerPCCPU *cpu) 1348 { 1349 CPUPPCState *env = &cpu->env; 1350 1351 /* The TCG path should also be holding the BQL at this point */ 1352 g_assert(bql_locked()); 1353 1354 g_assert(!vhyp_cpu_in_nested(cpu)); 1355 1356 if (FIELD_EX64(env->msr, MSR, PR)) { 1357 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1358 env->gpr[3] = H_PRIVILEGE; 1359 } else { 1360 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1361 } 1362 } 1363 1364 struct LPCRSyncState { 1365 target_ulong value; 1366 target_ulong mask; 1367 }; 1368 1369 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1370 { 1371 struct LPCRSyncState *s = arg.host_ptr; 1372 PowerPCCPU *cpu = POWERPC_CPU(cs); 1373 CPUPPCState *env = &cpu->env; 1374 target_ulong lpcr; 1375 1376 cpu_synchronize_state(cs); 1377 lpcr = env->spr[SPR_LPCR]; 1378 lpcr &= ~s->mask; 1379 lpcr |= s->value; 1380 ppc_store_lpcr(cpu, lpcr); 1381 } 1382 1383 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1384 { 1385 CPUState *cs; 1386 struct LPCRSyncState s = { 1387 .value = value, 1388 .mask = mask 1389 }; 1390 CPU_FOREACH(cs) { 1391 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1392 } 1393 } 1394 1395 /* May be used when the machine is not running */ 1396 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1397 { 1398 CPUState *cs; 1399 CPU_FOREACH(cs) { 1400 PowerPCCPU *cpu = POWERPC_CPU(cs); 1401 CPUPPCState *env = &cpu->env; 1402 target_ulong lpcr; 1403 1404 lpcr = env->spr[SPR_LPCR]; 1405 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1406 ppc_store_lpcr(cpu, lpcr); 1407 } 1408 } 1409 1410 1411 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1412 target_ulong lpid, ppc_v3_pate_t *entry) 1413 { 1414 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1415 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1416 1417 if (!spapr_cpu->in_nested) { 1418 assert(lpid == 0); 1419 1420 /* Copy PATE1:GR into PATE0:HR */ 1421 entry->dw0 = spapr->patb_entry & PATE0_HR; 1422 entry->dw1 = spapr->patb_entry; 1423 1424 } else { 1425 uint64_t patb, pats; 1426 1427 assert(lpid != 0); 1428 1429 patb = spapr->nested_ptcr & PTCR_PATB; 1430 pats = spapr->nested_ptcr & PTCR_PATS; 1431 1432 /* Check if partition table is properly aligned */ 1433 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 1434 return false; 1435 } 1436 1437 /* Calculate number of entries */ 1438 pats = 1ull << (pats + 12 - 4); 1439 if (pats <= lpid) { 1440 return false; 1441 } 1442 1443 /* Grab entry */ 1444 patb += 16 * lpid; 1445 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1446 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1447 } 1448 1449 return true; 1450 } 1451 1452 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1453 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1454 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1455 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1456 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1457 1458 /* 1459 * Get the fd to access the kernel htab, re-opening it if necessary 1460 */ 1461 static int get_htab_fd(SpaprMachineState *spapr) 1462 { 1463 Error *local_err = NULL; 1464 1465 if (spapr->htab_fd >= 0) { 1466 return spapr->htab_fd; 1467 } 1468 1469 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1470 if (spapr->htab_fd < 0) { 1471 error_report_err(local_err); 1472 } 1473 1474 return spapr->htab_fd; 1475 } 1476 1477 void close_htab_fd(SpaprMachineState *spapr) 1478 { 1479 if (spapr->htab_fd >= 0) { 1480 close(spapr->htab_fd); 1481 } 1482 spapr->htab_fd = -1; 1483 } 1484 1485 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1486 { 1487 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1488 1489 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1490 } 1491 1492 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1493 { 1494 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1495 1496 assert(kvm_enabled()); 1497 1498 if (!spapr->htab) { 1499 return 0; 1500 } 1501 1502 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1503 } 1504 1505 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1506 hwaddr ptex, int n) 1507 { 1508 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1509 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1510 1511 if (!spapr->htab) { 1512 /* 1513 * HTAB is controlled by KVM. Fetch into temporary buffer 1514 */ 1515 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1516 kvmppc_read_hptes(hptes, ptex, n); 1517 return hptes; 1518 } 1519 1520 /* 1521 * HTAB is controlled by QEMU. Just point to the internally 1522 * accessible PTEG. 1523 */ 1524 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1525 } 1526 1527 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1528 const ppc_hash_pte64_t *hptes, 1529 hwaddr ptex, int n) 1530 { 1531 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1532 1533 if (!spapr->htab) { 1534 g_free((void *)hptes); 1535 } 1536 1537 /* Nothing to do for qemu managed HPT */ 1538 } 1539 1540 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1541 uint64_t pte0, uint64_t pte1) 1542 { 1543 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1544 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1545 1546 if (!spapr->htab) { 1547 kvmppc_write_hpte(ptex, pte0, pte1); 1548 } else { 1549 if (pte0 & HPTE64_V_VALID) { 1550 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1551 /* 1552 * When setting valid, we write PTE1 first. This ensures 1553 * proper synchronization with the reading code in 1554 * ppc_hash64_pteg_search() 1555 */ 1556 smp_wmb(); 1557 stq_p(spapr->htab + offset, pte0); 1558 } else { 1559 stq_p(spapr->htab + offset, pte0); 1560 /* 1561 * When clearing it we set PTE0 first. This ensures proper 1562 * synchronization with the reading code in 1563 * ppc_hash64_pteg_search() 1564 */ 1565 smp_wmb(); 1566 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1567 } 1568 } 1569 } 1570 1571 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1572 uint64_t pte1) 1573 { 1574 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1575 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1576 1577 if (!spapr->htab) { 1578 /* There should always be a hash table when this is called */ 1579 error_report("spapr_hpte_set_c called with no hash table !"); 1580 return; 1581 } 1582 1583 /* The HW performs a non-atomic byte update */ 1584 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1585 } 1586 1587 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1588 uint64_t pte1) 1589 { 1590 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1591 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1592 1593 if (!spapr->htab) { 1594 /* There should always be a hash table when this is called */ 1595 error_report("spapr_hpte_set_r called with no hash table !"); 1596 return; 1597 } 1598 1599 /* The HW performs a non-atomic byte update */ 1600 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1601 } 1602 1603 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1604 { 1605 int shift; 1606 1607 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1608 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1609 * that's much more than is needed for Linux guests */ 1610 shift = ctz64(pow2ceil(ramsize)) - 7; 1611 shift = MAX(shift, 18); /* Minimum architected size */ 1612 shift = MIN(shift, 46); /* Maximum architected size */ 1613 return shift; 1614 } 1615 1616 void spapr_free_hpt(SpaprMachineState *spapr) 1617 { 1618 qemu_vfree(spapr->htab); 1619 spapr->htab = NULL; 1620 spapr->htab_shift = 0; 1621 close_htab_fd(spapr); 1622 } 1623 1624 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1625 { 1626 ERRP_GUARD(); 1627 long rc; 1628 1629 /* Clean up any HPT info from a previous boot */ 1630 spapr_free_hpt(spapr); 1631 1632 rc = kvmppc_reset_htab(shift); 1633 1634 if (rc == -EOPNOTSUPP) { 1635 error_setg(errp, "HPT not supported in nested guests"); 1636 return -EOPNOTSUPP; 1637 } 1638 1639 if (rc < 0) { 1640 /* kernel-side HPT needed, but couldn't allocate one */ 1641 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1642 shift); 1643 error_append_hint(errp, "Try smaller maxmem?\n"); 1644 return -errno; 1645 } else if (rc > 0) { 1646 /* kernel-side HPT allocated */ 1647 if (rc != shift) { 1648 error_setg(errp, 1649 "Requested order %d HPT, but kernel allocated order %ld", 1650 shift, rc); 1651 error_append_hint(errp, "Try smaller maxmem?\n"); 1652 return -ENOSPC; 1653 } 1654 1655 spapr->htab_shift = shift; 1656 spapr->htab = NULL; 1657 } else { 1658 /* kernel-side HPT not needed, allocate in userspace instead */ 1659 size_t size = 1ULL << shift; 1660 int i; 1661 1662 spapr->htab = qemu_memalign(size, size); 1663 memset(spapr->htab, 0, size); 1664 spapr->htab_shift = shift; 1665 1666 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1667 DIRTY_HPTE(HPTE(spapr->htab, i)); 1668 } 1669 } 1670 /* We're setting up a hash table, so that means we're not radix */ 1671 spapr->patb_entry = 0; 1672 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1673 return 0; 1674 } 1675 1676 void spapr_setup_hpt(SpaprMachineState *spapr) 1677 { 1678 int hpt_shift; 1679 1680 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1681 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1682 } else { 1683 uint64_t current_ram_size; 1684 1685 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1686 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1687 } 1688 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1689 1690 if (kvm_enabled()) { 1691 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1692 1693 /* Check our RMA fits in the possible VRMA */ 1694 if (vrma_limit < spapr->rma_size) { 1695 error_report("Unable to create %" HWADDR_PRIu 1696 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1697 spapr->rma_size / MiB, vrma_limit / MiB); 1698 exit(EXIT_FAILURE); 1699 } 1700 } 1701 } 1702 1703 void spapr_check_mmu_mode(bool guest_radix) 1704 { 1705 if (guest_radix) { 1706 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1707 error_report("Guest requested unavailable MMU mode (radix)."); 1708 exit(EXIT_FAILURE); 1709 } 1710 } else { 1711 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1712 && !kvmppc_has_cap_mmu_hash_v3()) { 1713 error_report("Guest requested unavailable MMU mode (hash)."); 1714 exit(EXIT_FAILURE); 1715 } 1716 } 1717 } 1718 1719 static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) 1720 { 1721 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1722 PowerPCCPU *first_ppc_cpu; 1723 hwaddr fdt_addr; 1724 void *fdt; 1725 int rc; 1726 1727 if (reason != SHUTDOWN_CAUSE_SNAPSHOT_LOAD) { 1728 /* 1729 * Record-replay snapshot load must not consume random, this was 1730 * already replayed from initial machine reset. 1731 */ 1732 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1733 } 1734 1735 pef_kvm_reset(machine->cgs, &error_fatal); 1736 spapr_caps_apply(spapr); 1737 spapr_nested_reset(spapr); 1738 1739 first_ppc_cpu = POWERPC_CPU(first_cpu); 1740 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1741 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1742 spapr->max_compat_pvr)) { 1743 /* 1744 * If using KVM with radix mode available, VCPUs can be started 1745 * without a HPT because KVM will start them in radix mode. 1746 * Set the GR bit in PATE so that we know there is no HPT. 1747 */ 1748 spapr->patb_entry = PATE1_GR; 1749 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1750 } else { 1751 spapr_setup_hpt(spapr); 1752 } 1753 1754 qemu_devices_reset(reason); 1755 1756 spapr_ovec_cleanup(spapr->ov5_cas); 1757 spapr->ov5_cas = spapr_ovec_new(); 1758 1759 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1760 1761 /* 1762 * This is fixing some of the default configuration of the XIVE 1763 * devices. To be called after the reset of the machine devices. 1764 */ 1765 spapr_irq_reset(spapr, &error_fatal); 1766 1767 /* 1768 * There is no CAS under qtest. Simulate one to please the code that 1769 * depends on spapr->ov5_cas. This is especially needed to test device 1770 * unplug, so we do that before resetting the DRCs. 1771 */ 1772 if (qtest_enabled()) { 1773 spapr_ovec_cleanup(spapr->ov5_cas); 1774 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1775 } 1776 1777 spapr_nvdimm_finish_flushes(); 1778 1779 /* DRC reset may cause a device to be unplugged. This will cause troubles 1780 * if this device is used by another device (eg, a running vhost backend 1781 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1782 * situations, we reset DRCs after all devices have been reset. 1783 */ 1784 spapr_drc_reset_all(spapr); 1785 1786 spapr_clear_pending_events(spapr); 1787 1788 /* 1789 * We place the device tree just below either the top of the RMA, 1790 * or just below 2GB, whichever is lower, so that it can be 1791 * processed with 32-bit real mode code if necessary 1792 */ 1793 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1794 1795 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1796 if (spapr->vof) { 1797 spapr_vof_reset(spapr, fdt, &error_fatal); 1798 /* 1799 * Do not pack the FDT as the client may change properties. 1800 * VOF client does not expect the FDT so we do not load it to the VM. 1801 */ 1802 } else { 1803 rc = fdt_pack(fdt); 1804 /* Should only fail if we've built a corrupted tree */ 1805 assert(rc == 0); 1806 1807 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1808 0, fdt_addr, 0); 1809 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1810 } 1811 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1812 1813 g_free(spapr->fdt_blob); 1814 spapr->fdt_size = fdt_totalsize(fdt); 1815 spapr->fdt_initial_size = spapr->fdt_size; 1816 spapr->fdt_blob = fdt; 1817 1818 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1819 machine->fdt = fdt; 1820 1821 /* Set up the entry state */ 1822 first_ppc_cpu->env.gpr[5] = 0; 1823 1824 spapr->fwnmi_system_reset_addr = -1; 1825 spapr->fwnmi_machine_check_addr = -1; 1826 spapr->fwnmi_machine_check_interlock = -1; 1827 1828 /* Signal all vCPUs waiting on this condition */ 1829 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1830 1831 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1832 } 1833 1834 static void spapr_create_nvram(SpaprMachineState *spapr) 1835 { 1836 DeviceState *dev = qdev_new("spapr-nvram"); 1837 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1838 1839 if (dinfo) { 1840 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1841 &error_fatal); 1842 } 1843 1844 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1845 1846 spapr->nvram = (struct SpaprNvram *)dev; 1847 } 1848 1849 static void spapr_rtc_create(SpaprMachineState *spapr) 1850 { 1851 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1852 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1853 &error_fatal, NULL); 1854 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1855 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1856 "date"); 1857 } 1858 1859 /* Returns whether we want to use VGA or not */ 1860 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1861 { 1862 vga_interface_created = true; 1863 switch (vga_interface_type) { 1864 case VGA_NONE: 1865 return false; 1866 case VGA_DEVICE: 1867 return true; 1868 case VGA_STD: 1869 case VGA_VIRTIO: 1870 case VGA_CIRRUS: 1871 return pci_vga_init(pci_bus) != NULL; 1872 default: 1873 error_setg(errp, 1874 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1875 return false; 1876 } 1877 } 1878 1879 static int spapr_pre_load(void *opaque) 1880 { 1881 int rc; 1882 1883 rc = spapr_caps_pre_load(opaque); 1884 if (rc) { 1885 return rc; 1886 } 1887 1888 return 0; 1889 } 1890 1891 static int spapr_post_load(void *opaque, int version_id) 1892 { 1893 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1894 int err = 0; 1895 1896 err = spapr_caps_post_migration(spapr); 1897 if (err) { 1898 return err; 1899 } 1900 1901 /* 1902 * In earlier versions, there was no separate qdev for the PAPR 1903 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1904 * So when migrating from those versions, poke the incoming offset 1905 * value into the RTC device 1906 */ 1907 if (version_id < 3) { 1908 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1909 if (err) { 1910 return err; 1911 } 1912 } 1913 1914 if (kvm_enabled() && spapr->patb_entry) { 1915 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1916 bool radix = !!(spapr->patb_entry & PATE1_GR); 1917 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1918 1919 /* 1920 * Update LPCR:HR and UPRT as they may not be set properly in 1921 * the stream 1922 */ 1923 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1924 LPCR_HR | LPCR_UPRT); 1925 1926 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1927 if (err) { 1928 error_report("Process table config unsupported by the host"); 1929 return -EINVAL; 1930 } 1931 } 1932 1933 err = spapr_irq_post_load(spapr, version_id); 1934 if (err) { 1935 return err; 1936 } 1937 1938 return err; 1939 } 1940 1941 static int spapr_pre_save(void *opaque) 1942 { 1943 int rc; 1944 1945 rc = spapr_caps_pre_save(opaque); 1946 if (rc) { 1947 return rc; 1948 } 1949 1950 return 0; 1951 } 1952 1953 static bool version_before_3(void *opaque, int version_id) 1954 { 1955 return version_id < 3; 1956 } 1957 1958 static bool spapr_pending_events_needed(void *opaque) 1959 { 1960 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1961 return !QTAILQ_EMPTY(&spapr->pending_events); 1962 } 1963 1964 static const VMStateDescription vmstate_spapr_event_entry = { 1965 .name = "spapr_event_log_entry", 1966 .version_id = 1, 1967 .minimum_version_id = 1, 1968 .fields = (const VMStateField[]) { 1969 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1970 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1971 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1972 NULL, extended_length), 1973 VMSTATE_END_OF_LIST() 1974 }, 1975 }; 1976 1977 static const VMStateDescription vmstate_spapr_pending_events = { 1978 .name = "spapr_pending_events", 1979 .version_id = 1, 1980 .minimum_version_id = 1, 1981 .needed = spapr_pending_events_needed, 1982 .fields = (const VMStateField[]) { 1983 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1984 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1985 VMSTATE_END_OF_LIST() 1986 }, 1987 }; 1988 1989 static bool spapr_ov5_cas_needed(void *opaque) 1990 { 1991 SpaprMachineState *spapr = opaque; 1992 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1993 bool cas_needed; 1994 1995 /* Prior to the introduction of SpaprOptionVector, we had two option 1996 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1997 * Both of these options encode machine topology into the device-tree 1998 * in such a way that the now-booted OS should still be able to interact 1999 * appropriately with QEMU regardless of what options were actually 2000 * negotiatied on the source side. 2001 * 2002 * As such, we can avoid migrating the CAS-negotiated options if these 2003 * are the only options available on the current machine/platform. 2004 * Since these are the only options available for pseries-2.7 and 2005 * earlier, this allows us to maintain old->new/new->old migration 2006 * compatibility. 2007 * 2008 * For QEMU 2.8+, there are additional CAS-negotiatable options available 2009 * via default pseries-2.8 machines and explicit command-line parameters. 2010 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 2011 * of the actual CAS-negotiated values to continue working properly. For 2012 * example, availability of memory unplug depends on knowing whether 2013 * OV5_HP_EVT was negotiated via CAS. 2014 * 2015 * Thus, for any cases where the set of available CAS-negotiatable 2016 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 2017 * include the CAS-negotiated options in the migration stream, unless 2018 * if they affect boot time behaviour only. 2019 */ 2020 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 2021 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 2022 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 2023 2024 /* We need extra information if we have any bits outside the mask 2025 * defined above */ 2026 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 2027 2028 spapr_ovec_cleanup(ov5_mask); 2029 2030 return cas_needed; 2031 } 2032 2033 static const VMStateDescription vmstate_spapr_ov5_cas = { 2034 .name = "spapr_option_vector_ov5_cas", 2035 .version_id = 1, 2036 .minimum_version_id = 1, 2037 .needed = spapr_ov5_cas_needed, 2038 .fields = (const VMStateField[]) { 2039 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 2040 vmstate_spapr_ovec, SpaprOptionVector), 2041 VMSTATE_END_OF_LIST() 2042 }, 2043 }; 2044 2045 static bool spapr_patb_entry_needed(void *opaque) 2046 { 2047 SpaprMachineState *spapr = opaque; 2048 2049 return !!spapr->patb_entry; 2050 } 2051 2052 static const VMStateDescription vmstate_spapr_patb_entry = { 2053 .name = "spapr_patb_entry", 2054 .version_id = 1, 2055 .minimum_version_id = 1, 2056 .needed = spapr_patb_entry_needed, 2057 .fields = (const VMStateField[]) { 2058 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2059 VMSTATE_END_OF_LIST() 2060 }, 2061 }; 2062 2063 static bool spapr_irq_map_needed(void *opaque) 2064 { 2065 SpaprMachineState *spapr = opaque; 2066 2067 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2068 } 2069 2070 static const VMStateDescription vmstate_spapr_irq_map = { 2071 .name = "spapr_irq_map", 2072 .version_id = 1, 2073 .minimum_version_id = 1, 2074 .needed = spapr_irq_map_needed, 2075 .fields = (const VMStateField[]) { 2076 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2077 VMSTATE_END_OF_LIST() 2078 }, 2079 }; 2080 2081 static bool spapr_dtb_needed(void *opaque) 2082 { 2083 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2084 2085 return smc->update_dt_enabled; 2086 } 2087 2088 static int spapr_dtb_pre_load(void *opaque) 2089 { 2090 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2091 2092 g_free(spapr->fdt_blob); 2093 spapr->fdt_blob = NULL; 2094 spapr->fdt_size = 0; 2095 2096 return 0; 2097 } 2098 2099 static const VMStateDescription vmstate_spapr_dtb = { 2100 .name = "spapr_dtb", 2101 .version_id = 1, 2102 .minimum_version_id = 1, 2103 .needed = spapr_dtb_needed, 2104 .pre_load = spapr_dtb_pre_load, 2105 .fields = (const VMStateField[]) { 2106 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2107 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2108 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2109 fdt_size), 2110 VMSTATE_END_OF_LIST() 2111 }, 2112 }; 2113 2114 static bool spapr_fwnmi_needed(void *opaque) 2115 { 2116 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2117 2118 return spapr->fwnmi_machine_check_addr != -1; 2119 } 2120 2121 static int spapr_fwnmi_pre_save(void *opaque) 2122 { 2123 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2124 2125 /* 2126 * Check if machine check handling is in progress and print a 2127 * warning message. 2128 */ 2129 if (spapr->fwnmi_machine_check_interlock != -1) { 2130 warn_report("A machine check is being handled during migration. The" 2131 "handler may run and log hardware error on the destination"); 2132 } 2133 2134 return 0; 2135 } 2136 2137 static const VMStateDescription vmstate_spapr_fwnmi = { 2138 .name = "spapr_fwnmi", 2139 .version_id = 1, 2140 .minimum_version_id = 1, 2141 .needed = spapr_fwnmi_needed, 2142 .pre_save = spapr_fwnmi_pre_save, 2143 .fields = (const VMStateField[]) { 2144 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2145 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2146 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2147 VMSTATE_END_OF_LIST() 2148 }, 2149 }; 2150 2151 static const VMStateDescription vmstate_spapr = { 2152 .name = "spapr", 2153 .version_id = 3, 2154 .minimum_version_id = 1, 2155 .pre_load = spapr_pre_load, 2156 .post_load = spapr_post_load, 2157 .pre_save = spapr_pre_save, 2158 .fields = (const VMStateField[]) { 2159 /* used to be @next_irq */ 2160 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2161 2162 /* RTC offset */ 2163 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2164 2165 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2166 VMSTATE_END_OF_LIST() 2167 }, 2168 .subsections = (const VMStateDescription * const []) { 2169 &vmstate_spapr_ov5_cas, 2170 &vmstate_spapr_patb_entry, 2171 &vmstate_spapr_pending_events, 2172 &vmstate_spapr_cap_htm, 2173 &vmstate_spapr_cap_vsx, 2174 &vmstate_spapr_cap_dfp, 2175 &vmstate_spapr_cap_cfpc, 2176 &vmstate_spapr_cap_sbbc, 2177 &vmstate_spapr_cap_ibs, 2178 &vmstate_spapr_cap_hpt_maxpagesize, 2179 &vmstate_spapr_irq_map, 2180 &vmstate_spapr_cap_nested_kvm_hv, 2181 &vmstate_spapr_dtb, 2182 &vmstate_spapr_cap_large_decr, 2183 &vmstate_spapr_cap_ccf_assist, 2184 &vmstate_spapr_cap_fwnmi, 2185 &vmstate_spapr_fwnmi, 2186 &vmstate_spapr_cap_rpt_invalidate, 2187 NULL 2188 } 2189 }; 2190 2191 static int htab_save_setup(QEMUFile *f, void *opaque) 2192 { 2193 SpaprMachineState *spapr = opaque; 2194 2195 /* "Iteration" header */ 2196 if (!spapr->htab_shift) { 2197 qemu_put_be32(f, -1); 2198 } else { 2199 qemu_put_be32(f, spapr->htab_shift); 2200 } 2201 2202 if (spapr->htab) { 2203 spapr->htab_save_index = 0; 2204 spapr->htab_first_pass = true; 2205 } else { 2206 if (spapr->htab_shift) { 2207 assert(kvm_enabled()); 2208 } 2209 } 2210 2211 2212 return 0; 2213 } 2214 2215 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2216 int chunkstart, int n_valid, int n_invalid) 2217 { 2218 qemu_put_be32(f, chunkstart); 2219 qemu_put_be16(f, n_valid); 2220 qemu_put_be16(f, n_invalid); 2221 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2222 HASH_PTE_SIZE_64 * n_valid); 2223 } 2224 2225 static void htab_save_end_marker(QEMUFile *f) 2226 { 2227 qemu_put_be32(f, 0); 2228 qemu_put_be16(f, 0); 2229 qemu_put_be16(f, 0); 2230 } 2231 2232 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2233 int64_t max_ns) 2234 { 2235 bool has_timeout = max_ns != -1; 2236 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2237 int index = spapr->htab_save_index; 2238 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2239 2240 assert(spapr->htab_first_pass); 2241 2242 do { 2243 int chunkstart; 2244 2245 /* Consume invalid HPTEs */ 2246 while ((index < htabslots) 2247 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2248 CLEAN_HPTE(HPTE(spapr->htab, index)); 2249 index++; 2250 } 2251 2252 /* Consume valid HPTEs */ 2253 chunkstart = index; 2254 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2255 && HPTE_VALID(HPTE(spapr->htab, index))) { 2256 CLEAN_HPTE(HPTE(spapr->htab, index)); 2257 index++; 2258 } 2259 2260 if (index > chunkstart) { 2261 int n_valid = index - chunkstart; 2262 2263 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2264 2265 if (has_timeout && 2266 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2267 break; 2268 } 2269 } 2270 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2271 2272 if (index >= htabslots) { 2273 assert(index == htabslots); 2274 index = 0; 2275 spapr->htab_first_pass = false; 2276 } 2277 spapr->htab_save_index = index; 2278 } 2279 2280 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2281 int64_t max_ns) 2282 { 2283 bool final = max_ns < 0; 2284 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2285 int examined = 0, sent = 0; 2286 int index = spapr->htab_save_index; 2287 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2288 2289 assert(!spapr->htab_first_pass); 2290 2291 do { 2292 int chunkstart, invalidstart; 2293 2294 /* Consume non-dirty HPTEs */ 2295 while ((index < htabslots) 2296 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2297 index++; 2298 examined++; 2299 } 2300 2301 chunkstart = index; 2302 /* Consume valid dirty HPTEs */ 2303 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2304 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2305 && HPTE_VALID(HPTE(spapr->htab, index))) { 2306 CLEAN_HPTE(HPTE(spapr->htab, index)); 2307 index++; 2308 examined++; 2309 } 2310 2311 invalidstart = index; 2312 /* Consume invalid dirty HPTEs */ 2313 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2314 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2315 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2316 CLEAN_HPTE(HPTE(spapr->htab, index)); 2317 index++; 2318 examined++; 2319 } 2320 2321 if (index > chunkstart) { 2322 int n_valid = invalidstart - chunkstart; 2323 int n_invalid = index - invalidstart; 2324 2325 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2326 sent += index - chunkstart; 2327 2328 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2329 break; 2330 } 2331 } 2332 2333 if (examined >= htabslots) { 2334 break; 2335 } 2336 2337 if (index >= htabslots) { 2338 assert(index == htabslots); 2339 index = 0; 2340 } 2341 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2342 2343 if (index >= htabslots) { 2344 assert(index == htabslots); 2345 index = 0; 2346 } 2347 2348 spapr->htab_save_index = index; 2349 2350 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2351 } 2352 2353 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2354 #define MAX_KVM_BUF_SIZE 2048 2355 2356 static int htab_save_iterate(QEMUFile *f, void *opaque) 2357 { 2358 SpaprMachineState *spapr = opaque; 2359 int fd; 2360 int rc = 0; 2361 2362 /* Iteration header */ 2363 if (!spapr->htab_shift) { 2364 qemu_put_be32(f, -1); 2365 return 1; 2366 } else { 2367 qemu_put_be32(f, 0); 2368 } 2369 2370 if (!spapr->htab) { 2371 assert(kvm_enabled()); 2372 2373 fd = get_htab_fd(spapr); 2374 if (fd < 0) { 2375 return fd; 2376 } 2377 2378 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2379 if (rc < 0) { 2380 return rc; 2381 } 2382 } else if (spapr->htab_first_pass) { 2383 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2384 } else { 2385 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2386 } 2387 2388 htab_save_end_marker(f); 2389 2390 return rc; 2391 } 2392 2393 static int htab_save_complete(QEMUFile *f, void *opaque) 2394 { 2395 SpaprMachineState *spapr = opaque; 2396 int fd; 2397 2398 /* Iteration header */ 2399 if (!spapr->htab_shift) { 2400 qemu_put_be32(f, -1); 2401 return 0; 2402 } else { 2403 qemu_put_be32(f, 0); 2404 } 2405 2406 if (!spapr->htab) { 2407 int rc; 2408 2409 assert(kvm_enabled()); 2410 2411 fd = get_htab_fd(spapr); 2412 if (fd < 0) { 2413 return fd; 2414 } 2415 2416 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2417 if (rc < 0) { 2418 return rc; 2419 } 2420 } else { 2421 if (spapr->htab_first_pass) { 2422 htab_save_first_pass(f, spapr, -1); 2423 } 2424 htab_save_later_pass(f, spapr, -1); 2425 } 2426 2427 /* End marker */ 2428 htab_save_end_marker(f); 2429 2430 return 0; 2431 } 2432 2433 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2434 { 2435 SpaprMachineState *spapr = opaque; 2436 uint32_t section_hdr; 2437 int fd = -1; 2438 Error *local_err = NULL; 2439 2440 if (version_id < 1 || version_id > 1) { 2441 error_report("htab_load() bad version"); 2442 return -EINVAL; 2443 } 2444 2445 section_hdr = qemu_get_be32(f); 2446 2447 if (section_hdr == -1) { 2448 spapr_free_hpt(spapr); 2449 return 0; 2450 } 2451 2452 if (section_hdr) { 2453 int ret; 2454 2455 /* First section gives the htab size */ 2456 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2457 if (ret < 0) { 2458 error_report_err(local_err); 2459 return ret; 2460 } 2461 return 0; 2462 } 2463 2464 if (!spapr->htab) { 2465 assert(kvm_enabled()); 2466 2467 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2468 if (fd < 0) { 2469 error_report_err(local_err); 2470 return fd; 2471 } 2472 } 2473 2474 while (true) { 2475 uint32_t index; 2476 uint16_t n_valid, n_invalid; 2477 2478 index = qemu_get_be32(f); 2479 n_valid = qemu_get_be16(f); 2480 n_invalid = qemu_get_be16(f); 2481 2482 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2483 /* End of Stream */ 2484 break; 2485 } 2486 2487 if ((index + n_valid + n_invalid) > 2488 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2489 /* Bad index in stream */ 2490 error_report( 2491 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2492 index, n_valid, n_invalid, spapr->htab_shift); 2493 return -EINVAL; 2494 } 2495 2496 if (spapr->htab) { 2497 if (n_valid) { 2498 qemu_get_buffer(f, HPTE(spapr->htab, index), 2499 HASH_PTE_SIZE_64 * n_valid); 2500 } 2501 if (n_invalid) { 2502 memset(HPTE(spapr->htab, index + n_valid), 0, 2503 HASH_PTE_SIZE_64 * n_invalid); 2504 } 2505 } else { 2506 int rc; 2507 2508 assert(fd >= 0); 2509 2510 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2511 &local_err); 2512 if (rc < 0) { 2513 error_report_err(local_err); 2514 return rc; 2515 } 2516 } 2517 } 2518 2519 if (!spapr->htab) { 2520 assert(fd >= 0); 2521 close(fd); 2522 } 2523 2524 return 0; 2525 } 2526 2527 static void htab_save_cleanup(void *opaque) 2528 { 2529 SpaprMachineState *spapr = opaque; 2530 2531 close_htab_fd(spapr); 2532 } 2533 2534 static SaveVMHandlers savevm_htab_handlers = { 2535 .save_setup = htab_save_setup, 2536 .save_live_iterate = htab_save_iterate, 2537 .save_live_complete_precopy = htab_save_complete, 2538 .save_cleanup = htab_save_cleanup, 2539 .load_state = htab_load, 2540 }; 2541 2542 static void spapr_boot_set(void *opaque, const char *boot_device, 2543 Error **errp) 2544 { 2545 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2546 2547 g_free(spapr->boot_device); 2548 spapr->boot_device = g_strdup(boot_device); 2549 } 2550 2551 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2552 { 2553 MachineState *machine = MACHINE(spapr); 2554 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2555 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2556 int i; 2557 2558 g_assert(!nr_lmbs || machine->device_memory); 2559 for (i = 0; i < nr_lmbs; i++) { 2560 uint64_t addr; 2561 2562 addr = i * lmb_size + machine->device_memory->base; 2563 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2564 addr / lmb_size); 2565 } 2566 } 2567 2568 /* 2569 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2570 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2571 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2572 */ 2573 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2574 { 2575 int i; 2576 2577 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2578 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2579 " is not aligned to %" PRIu64 " MiB", 2580 machine->ram_size, 2581 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2582 return; 2583 } 2584 2585 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2586 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2587 " is not aligned to %" PRIu64 " MiB", 2588 machine->ram_size, 2589 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2590 return; 2591 } 2592 2593 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2594 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2595 error_setg(errp, 2596 "Node %d memory size 0x%" PRIx64 2597 " is not aligned to %" PRIu64 " MiB", 2598 i, machine->numa_state->nodes[i].node_mem, 2599 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2600 return; 2601 } 2602 } 2603 } 2604 2605 /* find cpu slot in machine->possible_cpus by core_id */ 2606 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2607 { 2608 int index = id / ms->smp.threads; 2609 2610 if (index >= ms->possible_cpus->len) { 2611 return NULL; 2612 } 2613 if (idx) { 2614 *idx = index; 2615 } 2616 return &ms->possible_cpus->cpus[index]; 2617 } 2618 2619 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2620 { 2621 MachineState *ms = MACHINE(spapr); 2622 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2623 Error *local_err = NULL; 2624 bool vsmt_user = !!spapr->vsmt; 2625 int kvm_smt = kvmppc_smt_threads(); 2626 int ret; 2627 unsigned int smp_threads = ms->smp.threads; 2628 2629 if (tcg_enabled()) { 2630 if (smp_threads > 1 && 2631 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2632 spapr->max_compat_pvr)) { 2633 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2634 return; 2635 } 2636 2637 if (smp_threads > 8) { 2638 error_setg(errp, "TCG cannot support more than 8 threads/core " 2639 "on a pseries machine"); 2640 return; 2641 } 2642 } 2643 if (!is_power_of_2(smp_threads)) { 2644 error_setg(errp, "Cannot support %d threads/core on a pseries " 2645 "machine because it must be a power of 2", smp_threads); 2646 return; 2647 } 2648 2649 /* Determine the VSMT mode to use: */ 2650 if (vsmt_user) { 2651 if (spapr->vsmt < smp_threads) { 2652 error_setg(errp, "Cannot support VSMT mode %d" 2653 " because it must be >= threads/core (%d)", 2654 spapr->vsmt, smp_threads); 2655 return; 2656 } 2657 /* In this case, spapr->vsmt has been set by the command line */ 2658 } else if (!smc->smp_threads_vsmt) { 2659 /* 2660 * Default VSMT value is tricky, because we need it to be as 2661 * consistent as possible (for migration), but this requires 2662 * changing it for at least some existing cases. We pick 8 as 2663 * the value that we'd get with KVM on POWER8, the 2664 * overwhelmingly common case in production systems. 2665 */ 2666 spapr->vsmt = MAX(8, smp_threads); 2667 } else { 2668 spapr->vsmt = smp_threads; 2669 } 2670 2671 /* KVM: If necessary, set the SMT mode: */ 2672 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2673 ret = kvmppc_set_smt_threads(spapr->vsmt); 2674 if (ret) { 2675 /* Looks like KVM isn't able to change VSMT mode */ 2676 error_setg(&local_err, 2677 "Failed to set KVM's VSMT mode to %d (errno %d)", 2678 spapr->vsmt, ret); 2679 /* We can live with that if the default one is big enough 2680 * for the number of threads, and a submultiple of the one 2681 * we want. In this case we'll waste some vcpu ids, but 2682 * behaviour will be correct */ 2683 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2684 warn_report_err(local_err); 2685 } else { 2686 if (!vsmt_user) { 2687 error_append_hint(&local_err, 2688 "On PPC, a VM with %d threads/core" 2689 " on a host with %d threads/core" 2690 " requires the use of VSMT mode %d.\n", 2691 smp_threads, kvm_smt, spapr->vsmt); 2692 } 2693 kvmppc_error_append_smt_possible_hint(&local_err); 2694 error_propagate(errp, local_err); 2695 } 2696 } 2697 } 2698 /* else TCG: nothing to do currently */ 2699 } 2700 2701 static void spapr_init_cpus(SpaprMachineState *spapr) 2702 { 2703 MachineState *machine = MACHINE(spapr); 2704 MachineClass *mc = MACHINE_GET_CLASS(machine); 2705 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2706 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2707 const CPUArchIdList *possible_cpus; 2708 unsigned int smp_cpus = machine->smp.cpus; 2709 unsigned int smp_threads = machine->smp.threads; 2710 unsigned int max_cpus = machine->smp.max_cpus; 2711 int boot_cores_nr = smp_cpus / smp_threads; 2712 int i; 2713 2714 possible_cpus = mc->possible_cpu_arch_ids(machine); 2715 if (mc->has_hotpluggable_cpus) { 2716 if (smp_cpus % smp_threads) { 2717 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2718 smp_cpus, smp_threads); 2719 exit(1); 2720 } 2721 if (max_cpus % smp_threads) { 2722 error_report("max_cpus (%u) must be multiple of threads (%u)", 2723 max_cpus, smp_threads); 2724 exit(1); 2725 } 2726 } else { 2727 if (max_cpus != smp_cpus) { 2728 error_report("This machine version does not support CPU hotplug"); 2729 exit(1); 2730 } 2731 boot_cores_nr = possible_cpus->len; 2732 } 2733 2734 if (smc->pre_2_10_has_unused_icps) { 2735 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2736 /* Dummy entries get deregistered when real ICPState objects 2737 * are registered during CPU core hotplug. 2738 */ 2739 pre_2_10_vmstate_register_dummy_icp(i); 2740 } 2741 } 2742 2743 for (i = 0; i < possible_cpus->len; i++) { 2744 int core_id = i * smp_threads; 2745 2746 if (mc->has_hotpluggable_cpus) { 2747 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2748 spapr_vcpu_id(spapr, core_id)); 2749 } 2750 2751 if (i < boot_cores_nr) { 2752 Object *core = object_new(type); 2753 int nr_threads = smp_threads; 2754 2755 /* Handle the partially filled core for older machine types */ 2756 if ((i + 1) * smp_threads >= smp_cpus) { 2757 nr_threads = smp_cpus - i * smp_threads; 2758 } 2759 2760 object_property_set_int(core, "nr-threads", nr_threads, 2761 &error_fatal); 2762 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2763 &error_fatal); 2764 qdev_realize(DEVICE(core), NULL, &error_fatal); 2765 2766 object_unref(core); 2767 } 2768 } 2769 } 2770 2771 static PCIHostState *spapr_create_default_phb(void) 2772 { 2773 DeviceState *dev; 2774 2775 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2776 qdev_prop_set_uint32(dev, "index", 0); 2777 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2778 2779 return PCI_HOST_BRIDGE(dev); 2780 } 2781 2782 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2783 { 2784 MachineState *machine = MACHINE(spapr); 2785 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2786 hwaddr rma_size = machine->ram_size; 2787 hwaddr node0_size = spapr_node0_size(machine); 2788 2789 /* RMA has to fit in the first NUMA node */ 2790 rma_size = MIN(rma_size, node0_size); 2791 2792 /* 2793 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2794 * never exceed that 2795 */ 2796 rma_size = MIN(rma_size, 1 * TiB); 2797 2798 /* 2799 * Clamp the RMA size based on machine type. This is for 2800 * migration compatibility with older qemu versions, which limited 2801 * the RMA size for complicated and mostly bad reasons. 2802 */ 2803 if (smc->rma_limit) { 2804 rma_size = MIN(rma_size, smc->rma_limit); 2805 } 2806 2807 if (rma_size < MIN_RMA_SLOF) { 2808 error_setg(errp, 2809 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2810 "ldMiB guest RMA (Real Mode Area memory)", 2811 MIN_RMA_SLOF / MiB); 2812 return 0; 2813 } 2814 2815 return rma_size; 2816 } 2817 2818 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2819 { 2820 MachineState *machine = MACHINE(spapr); 2821 int i; 2822 2823 for (i = 0; i < machine->ram_slots; i++) { 2824 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2825 } 2826 } 2827 2828 /* pSeries LPAR / sPAPR hardware init */ 2829 static void spapr_machine_init(MachineState *machine) 2830 { 2831 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2832 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2833 MachineClass *mc = MACHINE_GET_CLASS(machine); 2834 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2835 const char *bios_name = machine->firmware ?: bios_default; 2836 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2837 const char *kernel_filename = machine->kernel_filename; 2838 const char *initrd_filename = machine->initrd_filename; 2839 PCIHostState *phb; 2840 bool has_vga; 2841 int i; 2842 MemoryRegion *sysmem = get_system_memory(); 2843 long load_limit, fw_size; 2844 Error *resize_hpt_err = NULL; 2845 NICInfo *nd; 2846 2847 if (!filename) { 2848 error_report("Could not find LPAR firmware '%s'", bios_name); 2849 exit(1); 2850 } 2851 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2852 if (fw_size <= 0) { 2853 error_report("Could not load LPAR firmware '%s'", filename); 2854 exit(1); 2855 } 2856 2857 /* 2858 * if Secure VM (PEF) support is configured, then initialize it 2859 */ 2860 pef_kvm_init(machine->cgs, &error_fatal); 2861 2862 msi_nonbroken = true; 2863 2864 QLIST_INIT(&spapr->phbs); 2865 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2866 2867 /* Determine capabilities to run with */ 2868 spapr_caps_init(spapr); 2869 2870 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2871 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2872 /* 2873 * If the user explicitly requested a mode we should either 2874 * supply it, or fail completely (which we do below). But if 2875 * it's not set explicitly, we reset our mode to something 2876 * that works 2877 */ 2878 if (resize_hpt_err) { 2879 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2880 error_free(resize_hpt_err); 2881 resize_hpt_err = NULL; 2882 } else { 2883 spapr->resize_hpt = smc->resize_hpt_default; 2884 } 2885 } 2886 2887 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2888 2889 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2890 /* 2891 * User requested HPT resize, but this host can't supply it. Bail out 2892 */ 2893 error_report_err(resize_hpt_err); 2894 exit(1); 2895 } 2896 error_free(resize_hpt_err); 2897 2898 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2899 2900 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2901 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2902 2903 /* 2904 * VSMT must be set in order to be able to compute VCPU ids, ie to 2905 * call spapr_max_server_number() or spapr_vcpu_id(). 2906 */ 2907 spapr_set_vsmt_mode(spapr, &error_fatal); 2908 2909 /* Set up Interrupt Controller before we create the VCPUs */ 2910 spapr_irq_init(spapr, &error_fatal); 2911 2912 /* Set up containers for ibm,client-architecture-support negotiated options 2913 */ 2914 spapr->ov5 = spapr_ovec_new(); 2915 spapr->ov5_cas = spapr_ovec_new(); 2916 2917 if (smc->dr_lmb_enabled) { 2918 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2919 spapr_validate_node_memory(machine, &error_fatal); 2920 } 2921 2922 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2923 2924 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2925 if (!smc->pre_6_2_numa_affinity) { 2926 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2927 } 2928 2929 /* advertise support for dedicated HP event source to guests */ 2930 if (spapr->use_hotplug_event_source) { 2931 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2932 } 2933 2934 /* advertise support for HPT resizing */ 2935 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2936 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2937 } 2938 2939 /* advertise support for ibm,dyamic-memory-v2 */ 2940 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2941 2942 /* advertise XIVE on POWER9 machines */ 2943 if (spapr->irq->xive) { 2944 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2945 } 2946 2947 /* init CPUs */ 2948 spapr_init_cpus(spapr); 2949 2950 /* Init numa_assoc_array */ 2951 spapr_numa_associativity_init(spapr, machine); 2952 2953 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2954 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2955 spapr->max_compat_pvr)) { 2956 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2957 /* KVM and TCG always allow GTSE with radix... */ 2958 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2959 } 2960 /* ... but not with hash (currently). */ 2961 2962 if (kvm_enabled()) { 2963 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2964 kvmppc_enable_logical_ci_hcalls(); 2965 kvmppc_enable_set_mode_hcall(); 2966 2967 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2968 kvmppc_enable_clear_ref_mod_hcalls(); 2969 2970 /* Enable H_PAGE_INIT */ 2971 kvmppc_enable_h_page_init(); 2972 } 2973 2974 /* map RAM */ 2975 memory_region_add_subregion(sysmem, 0, machine->ram); 2976 2977 /* initialize hotplug memory address space */ 2978 if (machine->ram_size < machine->maxram_size) { 2979 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2980 hwaddr device_mem_base; 2981 2982 /* 2983 * Limit the number of hotpluggable memory slots to half the number 2984 * slots that KVM supports, leaving the other half for PCI and other 2985 * devices. However ensure that number of slots doesn't drop below 32. 2986 */ 2987 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2988 SPAPR_MAX_RAM_SLOTS; 2989 2990 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2991 max_memslots = SPAPR_MAX_RAM_SLOTS; 2992 } 2993 if (machine->ram_slots > max_memslots) { 2994 error_report("Specified number of memory slots %" 2995 PRIu64" exceeds max supported %d", 2996 machine->ram_slots, max_memslots); 2997 exit(1); 2998 } 2999 3000 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 3001 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 3002 } 3003 3004 if (smc->dr_lmb_enabled) { 3005 spapr_create_lmb_dr_connectors(spapr); 3006 } 3007 3008 if (mc->nvdimm_supported) { 3009 spapr_create_nvdimm_dr_connectors(spapr); 3010 } 3011 3012 /* Set up RTAS event infrastructure */ 3013 spapr_events_init(spapr); 3014 3015 /* Set up the RTC RTAS interfaces */ 3016 spapr_rtc_create(spapr); 3017 3018 /* Set up VIO bus */ 3019 spapr->vio_bus = spapr_vio_bus_init(); 3020 3021 for (i = 0; serial_hd(i); i++) { 3022 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 3023 } 3024 3025 /* We always have at least the nvram device on VIO */ 3026 spapr_create_nvram(spapr); 3027 3028 /* 3029 * Setup hotplug / dynamic-reconfiguration connectors. top-level 3030 * connectors (described in root DT node's "ibm,drc-types" property) 3031 * are pre-initialized here. additional child connectors (such as 3032 * connectors for a PHBs PCI slots) are added as needed during their 3033 * parent's realization. 3034 */ 3035 if (smc->dr_phb_enabled) { 3036 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 3037 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 3038 } 3039 } 3040 3041 /* Set up PCI */ 3042 spapr_pci_rtas_init(); 3043 3044 phb = spapr_create_default_phb(); 3045 3046 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 3047 spapr_vlan_create(spapr->vio_bus, nd); 3048 } 3049 3050 pci_init_nic_devices(phb->bus, NULL); 3051 3052 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 3053 spapr_vscsi_create(spapr->vio_bus); 3054 } 3055 3056 /* Graphics */ 3057 has_vga = spapr_vga_init(phb->bus, &error_fatal); 3058 if (has_vga) { 3059 spapr->want_stdout_path = !machine->enable_graphics; 3060 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3061 } else { 3062 spapr->want_stdout_path = true; 3063 } 3064 3065 if (machine->usb) { 3066 if (smc->use_ohci_by_default) { 3067 pci_create_simple(phb->bus, -1, "pci-ohci"); 3068 } else { 3069 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3070 } 3071 3072 if (has_vga) { 3073 USBBus *usb_bus; 3074 3075 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3076 &error_abort)); 3077 usb_create_simple(usb_bus, "usb-kbd"); 3078 usb_create_simple(usb_bus, "usb-mouse"); 3079 } 3080 } 3081 3082 if (kernel_filename) { 3083 uint64_t loaded_addr = 0; 3084 3085 spapr->kernel_size = load_elf(kernel_filename, NULL, 3086 translate_kernel_address, spapr, 3087 NULL, &loaded_addr, NULL, NULL, 1, 3088 PPC_ELF_MACHINE, 0, 0); 3089 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3090 spapr->kernel_size = load_elf(kernel_filename, NULL, 3091 translate_kernel_address, spapr, 3092 NULL, &loaded_addr, NULL, NULL, 0, 3093 PPC_ELF_MACHINE, 0, 0); 3094 spapr->kernel_le = spapr->kernel_size > 0; 3095 } 3096 if (spapr->kernel_size < 0) { 3097 error_report("error loading %s: %s", kernel_filename, 3098 load_elf_strerror(spapr->kernel_size)); 3099 exit(1); 3100 } 3101 3102 if (spapr->kernel_addr != loaded_addr) { 3103 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3104 " to 0x%"PRIx64, 3105 spapr->kernel_addr, loaded_addr); 3106 spapr->kernel_addr = loaded_addr; 3107 } 3108 3109 /* load initrd */ 3110 if (initrd_filename) { 3111 /* Try to locate the initrd in the gap between the kernel 3112 * and the firmware. Add a bit of space just in case 3113 */ 3114 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3115 + 0x1ffff) & ~0xffff; 3116 spapr->initrd_size = load_image_targphys(initrd_filename, 3117 spapr->initrd_base, 3118 load_limit 3119 - spapr->initrd_base); 3120 if (spapr->initrd_size < 0) { 3121 error_report("could not load initial ram disk '%s'", 3122 initrd_filename); 3123 exit(1); 3124 } 3125 } 3126 } 3127 3128 /* FIXME: Should register things through the MachineState's qdev 3129 * interface, this is a legacy from the sPAPREnvironment structure 3130 * which predated MachineState but had a similar function */ 3131 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3132 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3133 &savevm_htab_handlers, spapr); 3134 3135 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3136 3137 qemu_register_boot_set(spapr_boot_set, spapr); 3138 3139 /* 3140 * Nothing needs to be done to resume a suspended guest because 3141 * suspending does not change the machine state, so no need for 3142 * a ->wakeup method. 3143 */ 3144 qemu_register_wakeup_support(); 3145 3146 if (kvm_enabled()) { 3147 /* to stop and start vmclock */ 3148 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3149 &spapr->tb); 3150 3151 kvmppc_spapr_enable_inkernel_multitce(); 3152 } 3153 3154 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3155 if (spapr->vof) { 3156 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3157 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3158 } 3159 3160 spapr_watchdog_init(spapr); 3161 } 3162 3163 #define DEFAULT_KVM_TYPE "auto" 3164 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3165 { 3166 /* 3167 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3168 * accommodate the 'HV' and 'PV' formats that exists in the 3169 * wild. The 'auto' mode is being introduced already as 3170 * lower-case, thus we don't need to bother checking for 3171 * "AUTO". 3172 */ 3173 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3174 return 0; 3175 } 3176 3177 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3178 return 1; 3179 } 3180 3181 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3182 return 2; 3183 } 3184 3185 error_report("Unknown kvm-type specified '%s'", vm_type); 3186 return -1; 3187 } 3188 3189 /* 3190 * Implementation of an interface to adjust firmware path 3191 * for the bootindex property handling. 3192 */ 3193 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3194 DeviceState *dev) 3195 { 3196 #define CAST(type, obj, name) \ 3197 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3198 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3199 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3200 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3201 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3202 3203 if (d && bus) { 3204 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3205 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3206 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3207 3208 if (spapr) { 3209 /* 3210 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3211 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3212 * 0x8000 | (target << 8) | (bus << 5) | lun 3213 * (see the "Logical unit addressing format" table in SAM5) 3214 */ 3215 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3216 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3217 (uint64_t)id << 48); 3218 } else if (virtio) { 3219 /* 3220 * We use SRP luns of the form 01000000 | (target << 8) | lun 3221 * in the top 32 bits of the 64-bit LUN 3222 * Note: the quote above is from SLOF and it is wrong, 3223 * the actual binding is: 3224 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3225 */ 3226 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3227 if (d->lun >= 256) { 3228 /* Use the LUN "flat space addressing method" */ 3229 id |= 0x4000; 3230 } 3231 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3232 (uint64_t)id << 32); 3233 } else if (usb) { 3234 /* 3235 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3236 * in the top 32 bits of the 64-bit LUN 3237 */ 3238 unsigned usb_port = atoi(usb->port->path); 3239 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3240 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3241 (uint64_t)id << 32); 3242 } 3243 } 3244 3245 /* 3246 * SLOF probes the USB devices, and if it recognizes that the device is a 3247 * storage device, it changes its name to "storage" instead of "usb-host", 3248 * and additionally adds a child node for the SCSI LUN, so the correct 3249 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3250 */ 3251 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3252 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3253 if (usb_device_is_scsi_storage(usbdev)) { 3254 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3255 } 3256 } 3257 3258 if (phb) { 3259 /* Replace "pci" with "pci@800000020000000" */ 3260 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3261 } 3262 3263 if (vsc) { 3264 /* Same logic as virtio above */ 3265 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3266 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3267 } 3268 3269 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3270 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3271 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3272 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3273 } 3274 3275 if (pcidev) { 3276 return spapr_pci_fw_dev_name(pcidev); 3277 } 3278 3279 return NULL; 3280 } 3281 3282 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3283 { 3284 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3285 3286 return g_strdup(spapr->kvm_type); 3287 } 3288 3289 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3290 { 3291 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3292 3293 g_free(spapr->kvm_type); 3294 spapr->kvm_type = g_strdup(value); 3295 } 3296 3297 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3298 { 3299 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3300 3301 return spapr->use_hotplug_event_source; 3302 } 3303 3304 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3305 Error **errp) 3306 { 3307 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3308 3309 spapr->use_hotplug_event_source = value; 3310 } 3311 3312 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3313 { 3314 return true; 3315 } 3316 3317 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3318 { 3319 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3320 3321 switch (spapr->resize_hpt) { 3322 case SPAPR_RESIZE_HPT_DEFAULT: 3323 return g_strdup("default"); 3324 case SPAPR_RESIZE_HPT_DISABLED: 3325 return g_strdup("disabled"); 3326 case SPAPR_RESIZE_HPT_ENABLED: 3327 return g_strdup("enabled"); 3328 case SPAPR_RESIZE_HPT_REQUIRED: 3329 return g_strdup("required"); 3330 } 3331 g_assert_not_reached(); 3332 } 3333 3334 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3335 { 3336 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3337 3338 if (strcmp(value, "default") == 0) { 3339 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3340 } else if (strcmp(value, "disabled") == 0) { 3341 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3342 } else if (strcmp(value, "enabled") == 0) { 3343 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3344 } else if (strcmp(value, "required") == 0) { 3345 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3346 } else { 3347 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3348 } 3349 } 3350 3351 static bool spapr_get_vof(Object *obj, Error **errp) 3352 { 3353 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3354 3355 return spapr->vof != NULL; 3356 } 3357 3358 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3359 { 3360 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3361 3362 if (spapr->vof) { 3363 vof_cleanup(spapr->vof); 3364 g_free(spapr->vof); 3365 spapr->vof = NULL; 3366 } 3367 if (!value) { 3368 return; 3369 } 3370 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3371 } 3372 3373 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3374 { 3375 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3376 3377 if (spapr->irq == &spapr_irq_xics_legacy) { 3378 return g_strdup("legacy"); 3379 } else if (spapr->irq == &spapr_irq_xics) { 3380 return g_strdup("xics"); 3381 } else if (spapr->irq == &spapr_irq_xive) { 3382 return g_strdup("xive"); 3383 } else if (spapr->irq == &spapr_irq_dual) { 3384 return g_strdup("dual"); 3385 } 3386 g_assert_not_reached(); 3387 } 3388 3389 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3390 { 3391 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3392 3393 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3394 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3395 return; 3396 } 3397 3398 /* The legacy IRQ backend can not be set */ 3399 if (strcmp(value, "xics") == 0) { 3400 spapr->irq = &spapr_irq_xics; 3401 } else if (strcmp(value, "xive") == 0) { 3402 spapr->irq = &spapr_irq_xive; 3403 } else if (strcmp(value, "dual") == 0) { 3404 spapr->irq = &spapr_irq_dual; 3405 } else { 3406 error_setg(errp, "Bad value for \"ic-mode\" property"); 3407 } 3408 } 3409 3410 static char *spapr_get_host_model(Object *obj, Error **errp) 3411 { 3412 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3413 3414 return g_strdup(spapr->host_model); 3415 } 3416 3417 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3418 { 3419 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3420 3421 g_free(spapr->host_model); 3422 spapr->host_model = g_strdup(value); 3423 } 3424 3425 static char *spapr_get_host_serial(Object *obj, Error **errp) 3426 { 3427 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3428 3429 return g_strdup(spapr->host_serial); 3430 } 3431 3432 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3433 { 3434 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3435 3436 g_free(spapr->host_serial); 3437 spapr->host_serial = g_strdup(value); 3438 } 3439 3440 static void spapr_instance_init(Object *obj) 3441 { 3442 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3443 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3444 MachineState *ms = MACHINE(spapr); 3445 MachineClass *mc = MACHINE_GET_CLASS(ms); 3446 3447 /* 3448 * NVDIMM support went live in 5.1 without considering that, in 3449 * other archs, the user needs to enable NVDIMM support with the 3450 * 'nvdimm' machine option and the default behavior is NVDIMM 3451 * support disabled. It is too late to roll back to the standard 3452 * behavior without breaking 5.1 guests. 3453 */ 3454 if (mc->nvdimm_supported) { 3455 ms->nvdimms_state->is_enabled = true; 3456 } 3457 3458 spapr->htab_fd = -1; 3459 spapr->use_hotplug_event_source = true; 3460 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3461 object_property_add_str(obj, "kvm-type", 3462 spapr_get_kvm_type, spapr_set_kvm_type); 3463 object_property_set_description(obj, "kvm-type", 3464 "Specifies the KVM virtualization mode (auto," 3465 " hv, pr). Defaults to 'auto'. This mode will use" 3466 " any available KVM module loaded in the host," 3467 " where kvm_hv takes precedence if both kvm_hv and" 3468 " kvm_pr are loaded."); 3469 object_property_add_bool(obj, "modern-hotplug-events", 3470 spapr_get_modern_hotplug_events, 3471 spapr_set_modern_hotplug_events); 3472 object_property_set_description(obj, "modern-hotplug-events", 3473 "Use dedicated hotplug event mechanism in" 3474 " place of standard EPOW events when possible" 3475 " (required for memory hot-unplug support)"); 3476 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3477 "Maximum permitted CPU compatibility mode"); 3478 3479 object_property_add_str(obj, "resize-hpt", 3480 spapr_get_resize_hpt, spapr_set_resize_hpt); 3481 object_property_set_description(obj, "resize-hpt", 3482 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3483 object_property_add_uint32_ptr(obj, "vsmt", 3484 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3485 object_property_set_description(obj, "vsmt", 3486 "Virtual SMT: KVM behaves as if this were" 3487 " the host's SMT mode"); 3488 3489 object_property_add_bool(obj, "vfio-no-msix-emulation", 3490 spapr_get_msix_emulation, NULL); 3491 3492 object_property_add_uint64_ptr(obj, "kernel-addr", 3493 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3494 object_property_set_description(obj, "kernel-addr", 3495 stringify(KERNEL_LOAD_ADDR) 3496 " for -kernel is the default"); 3497 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3498 3499 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3500 object_property_set_description(obj, "x-vof", 3501 "Enable Virtual Open Firmware (experimental)"); 3502 3503 /* The machine class defines the default interrupt controller mode */ 3504 spapr->irq = smc->irq; 3505 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3506 spapr_set_ic_mode); 3507 object_property_set_description(obj, "ic-mode", 3508 "Specifies the interrupt controller mode (xics, xive, dual)"); 3509 3510 object_property_add_str(obj, "host-model", 3511 spapr_get_host_model, spapr_set_host_model); 3512 object_property_set_description(obj, "host-model", 3513 "Host model to advertise in guest device tree"); 3514 object_property_add_str(obj, "host-serial", 3515 spapr_get_host_serial, spapr_set_host_serial); 3516 object_property_set_description(obj, "host-serial", 3517 "Host serial number to advertise in guest device tree"); 3518 } 3519 3520 static void spapr_machine_finalizefn(Object *obj) 3521 { 3522 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3523 3524 g_free(spapr->kvm_type); 3525 } 3526 3527 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3528 { 3529 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3530 PowerPCCPU *cpu = POWERPC_CPU(cs); 3531 CPUPPCState *env = &cpu->env; 3532 3533 cpu_synchronize_state(cs); 3534 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3535 if (spapr->fwnmi_system_reset_addr != -1) { 3536 uint64_t rtas_addr, addr; 3537 3538 /* get rtas addr from fdt */ 3539 rtas_addr = spapr_get_rtas_addr(); 3540 if (!rtas_addr) { 3541 qemu_system_guest_panicked(NULL); 3542 return; 3543 } 3544 3545 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3546 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3547 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3548 env->gpr[3] = addr; 3549 } 3550 ppc_cpu_do_system_reset(cs); 3551 if (spapr->fwnmi_system_reset_addr != -1) { 3552 env->nip = spapr->fwnmi_system_reset_addr; 3553 } 3554 } 3555 3556 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3557 { 3558 CPUState *cs; 3559 3560 CPU_FOREACH(cs) { 3561 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3562 } 3563 } 3564 3565 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3566 void *fdt, int *fdt_start_offset, Error **errp) 3567 { 3568 uint64_t addr; 3569 uint32_t node; 3570 3571 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3572 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3573 &error_abort); 3574 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3575 SPAPR_MEMORY_BLOCK_SIZE); 3576 return 0; 3577 } 3578 3579 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3580 bool dedicated_hp_event_source) 3581 { 3582 SpaprDrc *drc; 3583 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3584 int i; 3585 uint64_t addr = addr_start; 3586 bool hotplugged = spapr_drc_hotplugged(dev); 3587 3588 for (i = 0; i < nr_lmbs; i++) { 3589 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3590 addr / SPAPR_MEMORY_BLOCK_SIZE); 3591 g_assert(drc); 3592 3593 /* 3594 * memory_device_get_free_addr() provided a range of free addresses 3595 * that doesn't overlap with any existing mapping at pre-plug. The 3596 * corresponding LMB DRCs are thus assumed to be all attachable. 3597 */ 3598 spapr_drc_attach(drc, dev); 3599 if (!hotplugged) { 3600 spapr_drc_reset(drc); 3601 } 3602 addr += SPAPR_MEMORY_BLOCK_SIZE; 3603 } 3604 /* send hotplug notification to the 3605 * guest only in case of hotplugged memory 3606 */ 3607 if (hotplugged) { 3608 if (dedicated_hp_event_source) { 3609 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3610 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3611 g_assert(drc); 3612 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3613 nr_lmbs, 3614 spapr_drc_index(drc)); 3615 } else { 3616 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3617 nr_lmbs); 3618 } 3619 } 3620 } 3621 3622 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3623 { 3624 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3625 PCDIMMDevice *dimm = PC_DIMM(dev); 3626 uint64_t size, addr; 3627 int64_t slot; 3628 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3629 3630 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3631 3632 pc_dimm_plug(dimm, MACHINE(ms)); 3633 3634 if (!is_nvdimm) { 3635 addr = object_property_get_uint(OBJECT(dimm), 3636 PC_DIMM_ADDR_PROP, &error_abort); 3637 spapr_add_lmbs(dev, addr, size, 3638 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3639 } else { 3640 slot = object_property_get_int(OBJECT(dimm), 3641 PC_DIMM_SLOT_PROP, &error_abort); 3642 /* We should have valid slot number at this point */ 3643 g_assert(slot >= 0); 3644 spapr_add_nvdimm(dev, slot); 3645 } 3646 } 3647 3648 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3649 Error **errp) 3650 { 3651 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3652 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3653 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3654 PCDIMMDevice *dimm = PC_DIMM(dev); 3655 Error *local_err = NULL; 3656 uint64_t size; 3657 Object *memdev; 3658 hwaddr pagesize; 3659 3660 if (!smc->dr_lmb_enabled) { 3661 error_setg(errp, "Memory hotplug not supported for this machine"); 3662 return; 3663 } 3664 3665 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3666 if (local_err) { 3667 error_propagate(errp, local_err); 3668 return; 3669 } 3670 3671 if (is_nvdimm) { 3672 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3673 return; 3674 } 3675 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3676 error_setg(errp, "Hotplugged memory size must be a multiple of " 3677 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3678 return; 3679 } 3680 3681 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3682 &error_abort); 3683 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3684 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3685 return; 3686 } 3687 3688 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3689 } 3690 3691 struct SpaprDimmState { 3692 PCDIMMDevice *dimm; 3693 uint32_t nr_lmbs; 3694 QTAILQ_ENTRY(SpaprDimmState) next; 3695 }; 3696 3697 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3698 PCDIMMDevice *dimm) 3699 { 3700 SpaprDimmState *dimm_state = NULL; 3701 3702 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3703 if (dimm_state->dimm == dimm) { 3704 break; 3705 } 3706 } 3707 return dimm_state; 3708 } 3709 3710 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3711 uint32_t nr_lmbs, 3712 PCDIMMDevice *dimm) 3713 { 3714 SpaprDimmState *ds = NULL; 3715 3716 /* 3717 * If this request is for a DIMM whose removal had failed earlier 3718 * (due to guest's refusal to remove the LMBs), we would have this 3719 * dimm already in the pending_dimm_unplugs list. In that 3720 * case don't add again. 3721 */ 3722 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3723 if (!ds) { 3724 ds = g_new0(SpaprDimmState, 1); 3725 ds->nr_lmbs = nr_lmbs; 3726 ds->dimm = dimm; 3727 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3728 } 3729 return ds; 3730 } 3731 3732 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3733 SpaprDimmState *dimm_state) 3734 { 3735 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3736 g_free(dimm_state); 3737 } 3738 3739 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3740 PCDIMMDevice *dimm) 3741 { 3742 SpaprDrc *drc; 3743 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3744 &error_abort); 3745 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3746 uint32_t avail_lmbs = 0; 3747 uint64_t addr_start, addr; 3748 int i; 3749 3750 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3751 &error_abort); 3752 3753 addr = addr_start; 3754 for (i = 0; i < nr_lmbs; i++) { 3755 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3756 addr / SPAPR_MEMORY_BLOCK_SIZE); 3757 g_assert(drc); 3758 if (drc->dev) { 3759 avail_lmbs++; 3760 } 3761 addr += SPAPR_MEMORY_BLOCK_SIZE; 3762 } 3763 3764 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3765 } 3766 3767 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3768 { 3769 SpaprDimmState *ds; 3770 PCDIMMDevice *dimm; 3771 SpaprDrc *drc; 3772 uint32_t nr_lmbs; 3773 uint64_t size, addr_start, addr; 3774 g_autofree char *qapi_error = NULL; 3775 int i; 3776 3777 if (!dev) { 3778 return; 3779 } 3780 3781 dimm = PC_DIMM(dev); 3782 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3783 3784 /* 3785 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3786 * unplug state, but one of its DRC is marked as unplug_requested. 3787 * This is bad and weird enough to g_assert() out. 3788 */ 3789 g_assert(ds); 3790 3791 spapr_pending_dimm_unplugs_remove(spapr, ds); 3792 3793 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3794 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3795 3796 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3797 &error_abort); 3798 3799 addr = addr_start; 3800 for (i = 0; i < nr_lmbs; i++) { 3801 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3802 addr / SPAPR_MEMORY_BLOCK_SIZE); 3803 g_assert(drc); 3804 3805 drc->unplug_requested = false; 3806 addr += SPAPR_MEMORY_BLOCK_SIZE; 3807 } 3808 3809 /* 3810 * Tell QAPI that something happened and the memory 3811 * hotunplug wasn't successful. Keep sending 3812 * MEM_UNPLUG_ERROR even while sending 3813 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3814 * MEM_UNPLUG_ERROR is due. 3815 */ 3816 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3817 "for device %s", dev->id); 3818 3819 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3820 3821 qapi_event_send_device_unplug_guest_error(dev->id, 3822 dev->canonical_path); 3823 } 3824 3825 /* Callback to be called during DRC release. */ 3826 void spapr_lmb_release(DeviceState *dev) 3827 { 3828 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3829 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3830 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3831 3832 /* This information will get lost if a migration occurs 3833 * during the unplug process. In this case recover it. */ 3834 if (ds == NULL) { 3835 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3836 g_assert(ds); 3837 /* The DRC being examined by the caller at least must be counted */ 3838 g_assert(ds->nr_lmbs); 3839 } 3840 3841 if (--ds->nr_lmbs) { 3842 return; 3843 } 3844 3845 /* 3846 * Now that all the LMBs have been removed by the guest, call the 3847 * unplug handler chain. This can never fail. 3848 */ 3849 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3850 object_unparent(OBJECT(dev)); 3851 } 3852 3853 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3854 { 3855 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3856 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3857 3858 /* We really shouldn't get this far without anything to unplug */ 3859 g_assert(ds); 3860 3861 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3862 qdev_unrealize(dev); 3863 spapr_pending_dimm_unplugs_remove(spapr, ds); 3864 } 3865 3866 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3867 DeviceState *dev, Error **errp) 3868 { 3869 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3870 PCDIMMDevice *dimm = PC_DIMM(dev); 3871 uint32_t nr_lmbs; 3872 uint64_t size, addr_start, addr; 3873 int i; 3874 SpaprDrc *drc; 3875 3876 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3877 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3878 return; 3879 } 3880 3881 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3882 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3883 3884 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3885 &error_abort); 3886 3887 /* 3888 * An existing pending dimm state for this DIMM means that there is an 3889 * unplug operation in progress, waiting for the spapr_lmb_release 3890 * callback to complete the job (BQL can't cover that far). In this case, 3891 * bail out to avoid detaching DRCs that were already released. 3892 */ 3893 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3894 error_setg(errp, "Memory unplug already in progress for device %s", 3895 dev->id); 3896 return; 3897 } 3898 3899 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3900 3901 addr = addr_start; 3902 for (i = 0; i < nr_lmbs; i++) { 3903 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3904 addr / SPAPR_MEMORY_BLOCK_SIZE); 3905 g_assert(drc); 3906 3907 spapr_drc_unplug_request(drc); 3908 addr += SPAPR_MEMORY_BLOCK_SIZE; 3909 } 3910 3911 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3912 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3913 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3914 nr_lmbs, spapr_drc_index(drc)); 3915 } 3916 3917 /* Callback to be called during DRC release. */ 3918 void spapr_core_release(DeviceState *dev) 3919 { 3920 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3921 3922 /* Call the unplug handler chain. This can never fail. */ 3923 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3924 object_unparent(OBJECT(dev)); 3925 } 3926 3927 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3928 { 3929 MachineState *ms = MACHINE(hotplug_dev); 3930 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3931 CPUCore *cc = CPU_CORE(dev); 3932 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3933 3934 if (smc->pre_2_10_has_unused_icps) { 3935 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3936 int i; 3937 3938 for (i = 0; i < cc->nr_threads; i++) { 3939 CPUState *cs = CPU(sc->threads[i]); 3940 3941 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3942 } 3943 } 3944 3945 assert(core_slot); 3946 core_slot->cpu = NULL; 3947 qdev_unrealize(dev); 3948 } 3949 3950 static 3951 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3952 Error **errp) 3953 { 3954 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3955 int index; 3956 SpaprDrc *drc; 3957 CPUCore *cc = CPU_CORE(dev); 3958 3959 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3960 error_setg(errp, "Unable to find CPU core with core-id: %d", 3961 cc->core_id); 3962 return; 3963 } 3964 if (index == 0) { 3965 error_setg(errp, "Boot CPU core may not be unplugged"); 3966 return; 3967 } 3968 3969 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3970 spapr_vcpu_id(spapr, cc->core_id)); 3971 g_assert(drc); 3972 3973 if (!spapr_drc_unplug_requested(drc)) { 3974 spapr_drc_unplug_request(drc); 3975 } 3976 3977 /* 3978 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3979 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3980 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3981 * attempt (e.g. the kernel will refuse to remove the last online 3982 * CPU), we will never attempt it again because unplug_requested 3983 * will still be 'true' in that case. 3984 */ 3985 spapr_hotplug_req_remove_by_index(drc); 3986 } 3987 3988 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3989 void *fdt, int *fdt_start_offset, Error **errp) 3990 { 3991 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3992 CPUState *cs = CPU(core->threads[0]); 3993 PowerPCCPU *cpu = POWERPC_CPU(cs); 3994 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3995 int id = spapr_get_vcpu_id(cpu); 3996 g_autofree char *nodename = NULL; 3997 int offset; 3998 3999 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 4000 offset = fdt_add_subnode(fdt, 0, nodename); 4001 4002 spapr_dt_cpu(cs, fdt, offset, spapr); 4003 4004 /* 4005 * spapr_dt_cpu() does not fill the 'name' property in the 4006 * CPU node. The function is called during boot process, before 4007 * and after CAS, and overwriting the 'name' property written 4008 * by SLOF is not allowed. 4009 * 4010 * Write it manually after spapr_dt_cpu(). This makes the hotplug 4011 * CPUs more compatible with the coldplugged ones, which have 4012 * the 'name' property. Linux Kernel also relies on this 4013 * property to identify CPU nodes. 4014 */ 4015 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 4016 4017 *fdt_start_offset = offset; 4018 return 0; 4019 } 4020 4021 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4022 { 4023 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4024 MachineClass *mc = MACHINE_GET_CLASS(spapr); 4025 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4026 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 4027 CPUCore *cc = CPU_CORE(dev); 4028 CPUState *cs; 4029 SpaprDrc *drc; 4030 CPUArchId *core_slot; 4031 int index; 4032 bool hotplugged = spapr_drc_hotplugged(dev); 4033 int i; 4034 4035 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4036 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 4037 4038 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 4039 spapr_vcpu_id(spapr, cc->core_id)); 4040 4041 g_assert(drc || !mc->has_hotpluggable_cpus); 4042 4043 if (drc) { 4044 /* 4045 * spapr_core_pre_plug() already buys us this is a brand new 4046 * core being plugged into a free slot. Nothing should already 4047 * be attached to the corresponding DRC. 4048 */ 4049 spapr_drc_attach(drc, dev); 4050 4051 if (hotplugged) { 4052 /* 4053 * Send hotplug notification interrupt to the guest only 4054 * in case of hotplugged CPUs. 4055 */ 4056 spapr_hotplug_req_add_by_index(drc); 4057 } else { 4058 spapr_drc_reset(drc); 4059 } 4060 } 4061 4062 core_slot->cpu = OBJECT(dev); 4063 4064 /* 4065 * Set compatibility mode to match the boot CPU, which was either set 4066 * by the machine reset code or by CAS. This really shouldn't fail at 4067 * this point. 4068 */ 4069 if (hotplugged) { 4070 for (i = 0; i < cc->nr_threads; i++) { 4071 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 4072 &error_abort); 4073 } 4074 } 4075 4076 if (smc->pre_2_10_has_unused_icps) { 4077 for (i = 0; i < cc->nr_threads; i++) { 4078 cs = CPU(core->threads[i]); 4079 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 4080 } 4081 } 4082 } 4083 4084 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4085 Error **errp) 4086 { 4087 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 4088 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 4089 CPUCore *cc = CPU_CORE(dev); 4090 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4091 const char *type = object_get_typename(OBJECT(dev)); 4092 CPUArchId *core_slot; 4093 int index; 4094 unsigned int smp_threads = machine->smp.threads; 4095 4096 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4097 error_setg(errp, "CPU hotplug not supported for this machine"); 4098 return; 4099 } 4100 4101 if (strcmp(base_core_type, type)) { 4102 error_setg(errp, "CPU core type should be %s", base_core_type); 4103 return; 4104 } 4105 4106 if (cc->core_id % smp_threads) { 4107 error_setg(errp, "invalid core id %d", cc->core_id); 4108 return; 4109 } 4110 4111 /* 4112 * In general we should have homogeneous threads-per-core, but old 4113 * (pre hotplug support) machine types allow the last core to have 4114 * reduced threads as a compatibility hack for when we allowed 4115 * total vcpus not a multiple of threads-per-core. 4116 */ 4117 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4118 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4119 smp_threads); 4120 return; 4121 } 4122 4123 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4124 if (!core_slot) { 4125 error_setg(errp, "core id %d out of range", cc->core_id); 4126 return; 4127 } 4128 4129 if (core_slot->cpu) { 4130 error_setg(errp, "core %d already populated", cc->core_id); 4131 return; 4132 } 4133 4134 numa_cpu_pre_plug(core_slot, dev, errp); 4135 } 4136 4137 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4138 void *fdt, int *fdt_start_offset, Error **errp) 4139 { 4140 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4141 int intc_phandle; 4142 4143 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4144 if (intc_phandle <= 0) { 4145 return -1; 4146 } 4147 4148 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4149 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4150 return -1; 4151 } 4152 4153 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4154 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4155 4156 return 0; 4157 } 4158 4159 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4160 Error **errp) 4161 { 4162 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4163 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4164 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4165 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4166 SpaprDrc *drc; 4167 4168 if (dev->hotplugged && !smc->dr_phb_enabled) { 4169 error_setg(errp, "PHB hotplug not supported for this machine"); 4170 return false; 4171 } 4172 4173 if (sphb->index == (uint32_t)-1) { 4174 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4175 return false; 4176 } 4177 4178 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4179 if (drc && drc->dev) { 4180 error_setg(errp, "PHB %d already attached", sphb->index); 4181 return false; 4182 } 4183 4184 /* 4185 * This will check that sphb->index doesn't exceed the maximum number of 4186 * PHBs for the current machine type. 4187 */ 4188 return 4189 smc->phb_placement(spapr, sphb->index, 4190 &sphb->buid, &sphb->io_win_addr, 4191 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4192 windows_supported, sphb->dma_liobn, 4193 errp); 4194 } 4195 4196 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4197 { 4198 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4199 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4200 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4201 SpaprDrc *drc; 4202 bool hotplugged = spapr_drc_hotplugged(dev); 4203 4204 if (!smc->dr_phb_enabled) { 4205 return; 4206 } 4207 4208 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4209 /* hotplug hooks should check it's enabled before getting this far */ 4210 assert(drc); 4211 4212 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4213 spapr_drc_attach(drc, dev); 4214 4215 if (hotplugged) { 4216 spapr_hotplug_req_add_by_index(drc); 4217 } else { 4218 spapr_drc_reset(drc); 4219 } 4220 } 4221 4222 void spapr_phb_release(DeviceState *dev) 4223 { 4224 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4225 4226 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4227 object_unparent(OBJECT(dev)); 4228 } 4229 4230 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4231 { 4232 qdev_unrealize(dev); 4233 } 4234 4235 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4236 DeviceState *dev, Error **errp) 4237 { 4238 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4239 SpaprDrc *drc; 4240 4241 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4242 assert(drc); 4243 4244 if (!spapr_drc_unplug_requested(drc)) { 4245 spapr_drc_unplug_request(drc); 4246 spapr_hotplug_req_remove_by_index(drc); 4247 } else { 4248 error_setg(errp, 4249 "PCI Host Bridge unplug already in progress for device %s", 4250 dev->id); 4251 } 4252 } 4253 4254 static 4255 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4256 Error **errp) 4257 { 4258 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4259 4260 if (spapr->tpm_proxy != NULL) { 4261 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4262 return false; 4263 } 4264 4265 return true; 4266 } 4267 4268 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4269 { 4270 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4271 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4272 4273 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4274 g_assert(spapr->tpm_proxy == NULL); 4275 4276 spapr->tpm_proxy = tpm_proxy; 4277 } 4278 4279 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4280 { 4281 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4282 4283 qdev_unrealize(dev); 4284 object_unparent(OBJECT(dev)); 4285 spapr->tpm_proxy = NULL; 4286 } 4287 4288 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4289 DeviceState *dev, Error **errp) 4290 { 4291 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4292 spapr_memory_plug(hotplug_dev, dev); 4293 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4294 spapr_core_plug(hotplug_dev, dev); 4295 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4296 spapr_phb_plug(hotplug_dev, dev); 4297 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4298 spapr_tpm_proxy_plug(hotplug_dev, dev); 4299 } 4300 } 4301 4302 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4303 DeviceState *dev, Error **errp) 4304 { 4305 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4306 spapr_memory_unplug(hotplug_dev, dev); 4307 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4308 spapr_core_unplug(hotplug_dev, dev); 4309 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4310 spapr_phb_unplug(hotplug_dev, dev); 4311 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4312 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4313 } 4314 } 4315 4316 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4317 { 4318 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4319 /* 4320 * CAS will process all pending unplug requests. 4321 * 4322 * HACK: a guest could theoretically have cleared all bits in OV5, 4323 * but none of the guests we care for do. 4324 */ 4325 spapr_ovec_empty(spapr->ov5_cas); 4326 } 4327 4328 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4329 DeviceState *dev, Error **errp) 4330 { 4331 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4332 MachineClass *mc = MACHINE_GET_CLASS(sms); 4333 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4334 4335 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4336 if (spapr_memory_hot_unplug_supported(sms)) { 4337 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4338 } else { 4339 error_setg(errp, "Memory hot unplug not supported for this guest"); 4340 } 4341 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4342 if (!mc->has_hotpluggable_cpus) { 4343 error_setg(errp, "CPU hot unplug not supported on this machine"); 4344 return; 4345 } 4346 spapr_core_unplug_request(hotplug_dev, dev, errp); 4347 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4348 if (!smc->dr_phb_enabled) { 4349 error_setg(errp, "PHB hot unplug not supported on this machine"); 4350 return; 4351 } 4352 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4353 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4354 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4355 } 4356 } 4357 4358 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4359 DeviceState *dev, Error **errp) 4360 { 4361 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4362 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4363 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4364 spapr_core_pre_plug(hotplug_dev, dev, errp); 4365 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4366 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4367 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4368 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4369 } 4370 } 4371 4372 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4373 DeviceState *dev) 4374 { 4375 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4376 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4377 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4378 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4379 return HOTPLUG_HANDLER(machine); 4380 } 4381 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4382 PCIDevice *pcidev = PCI_DEVICE(dev); 4383 PCIBus *root = pci_device_root_bus(pcidev); 4384 SpaprPhbState *phb = 4385 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4386 TYPE_SPAPR_PCI_HOST_BRIDGE); 4387 4388 if (phb) { 4389 return HOTPLUG_HANDLER(phb); 4390 } 4391 } 4392 return NULL; 4393 } 4394 4395 static CpuInstanceProperties 4396 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4397 { 4398 CPUArchId *core_slot; 4399 MachineClass *mc = MACHINE_GET_CLASS(machine); 4400 4401 /* make sure possible_cpu are initialized */ 4402 mc->possible_cpu_arch_ids(machine); 4403 /* get CPU core slot containing thread that matches cpu_index */ 4404 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4405 assert(core_slot); 4406 return core_slot->props; 4407 } 4408 4409 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4410 { 4411 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4412 } 4413 4414 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4415 { 4416 int i; 4417 unsigned int smp_threads = machine->smp.threads; 4418 unsigned int smp_cpus = machine->smp.cpus; 4419 const char *core_type; 4420 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4421 MachineClass *mc = MACHINE_GET_CLASS(machine); 4422 4423 if (!mc->has_hotpluggable_cpus) { 4424 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4425 } 4426 if (machine->possible_cpus) { 4427 assert(machine->possible_cpus->len == spapr_max_cores); 4428 return machine->possible_cpus; 4429 } 4430 4431 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4432 if (!core_type) { 4433 error_report("Unable to find sPAPR CPU Core definition"); 4434 exit(1); 4435 } 4436 4437 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4438 sizeof(CPUArchId) * spapr_max_cores); 4439 machine->possible_cpus->len = spapr_max_cores; 4440 for (i = 0; i < machine->possible_cpus->len; i++) { 4441 int core_id = i * smp_threads; 4442 4443 machine->possible_cpus->cpus[i].type = core_type; 4444 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4445 machine->possible_cpus->cpus[i].arch_id = core_id; 4446 machine->possible_cpus->cpus[i].props.has_core_id = true; 4447 machine->possible_cpus->cpus[i].props.core_id = core_id; 4448 } 4449 return machine->possible_cpus; 4450 } 4451 4452 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4453 uint64_t *buid, hwaddr *pio, 4454 hwaddr *mmio32, hwaddr *mmio64, 4455 unsigned n_dma, uint32_t *liobns, Error **errp) 4456 { 4457 /* 4458 * New-style PHB window placement. 4459 * 4460 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4461 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4462 * windows. 4463 * 4464 * Some guest kernels can't work with MMIO windows above 1<<46 4465 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4466 * 4467 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4468 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4469 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4470 * 1TiB 64-bit MMIO windows for each PHB. 4471 */ 4472 const uint64_t base_buid = 0x800000020000000ULL; 4473 int i; 4474 4475 /* Sanity check natural alignments */ 4476 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4477 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4478 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4479 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4480 /* Sanity check bounds */ 4481 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4482 SPAPR_PCI_MEM32_WIN_SIZE); 4483 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4484 SPAPR_PCI_MEM64_WIN_SIZE); 4485 4486 if (index >= SPAPR_MAX_PHBS) { 4487 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4488 SPAPR_MAX_PHBS - 1); 4489 return false; 4490 } 4491 4492 *buid = base_buid + index; 4493 for (i = 0; i < n_dma; ++i) { 4494 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4495 } 4496 4497 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4498 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4499 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4500 return true; 4501 } 4502 4503 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4504 { 4505 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4506 4507 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4508 } 4509 4510 static void spapr_ics_resend(XICSFabric *dev) 4511 { 4512 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4513 4514 ics_resend(spapr->ics); 4515 } 4516 4517 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4518 { 4519 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4520 4521 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4522 } 4523 4524 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4525 Monitor *mon) 4526 { 4527 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4528 4529 spapr_irq_print_info(spapr, mon); 4530 monitor_printf(mon, "irqchip: %s\n", 4531 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4532 } 4533 4534 /* 4535 * This is a XIVE only operation 4536 */ 4537 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4538 uint8_t nvt_blk, uint32_t nvt_idx, 4539 bool cam_ignore, uint8_t priority, 4540 uint32_t logic_serv, XiveTCTXMatch *match) 4541 { 4542 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4543 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4544 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4545 int count; 4546 4547 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4548 priority, logic_serv, match); 4549 if (count < 0) { 4550 return count; 4551 } 4552 4553 /* 4554 * When we implement the save and restore of the thread interrupt 4555 * contexts in the enter/exit CPU handlers of the machine and the 4556 * escalations in QEMU, we should be able to handle non dispatched 4557 * vCPUs. 4558 * 4559 * Until this is done, the sPAPR machine should find at least one 4560 * matching context always. 4561 */ 4562 if (count == 0) { 4563 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4564 nvt_blk, nvt_idx); 4565 } 4566 4567 return count; 4568 } 4569 4570 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4571 { 4572 return cpu->vcpu_id; 4573 } 4574 4575 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4576 { 4577 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4578 MachineState *ms = MACHINE(spapr); 4579 int vcpu_id; 4580 4581 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4582 4583 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4584 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4585 error_append_hint(errp, "Adjust the number of cpus to %d " 4586 "or try to raise the number of threads per core\n", 4587 vcpu_id * ms->smp.threads / spapr->vsmt); 4588 return false; 4589 } 4590 4591 cpu->vcpu_id = vcpu_id; 4592 return true; 4593 } 4594 4595 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4596 { 4597 CPUState *cs; 4598 4599 CPU_FOREACH(cs) { 4600 PowerPCCPU *cpu = POWERPC_CPU(cs); 4601 4602 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4603 return cpu; 4604 } 4605 } 4606 4607 return NULL; 4608 } 4609 4610 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4611 { 4612 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4613 4614 return spapr_cpu->in_nested; 4615 } 4616 4617 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4618 { 4619 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4620 4621 /* These are only called by TCG, KVM maintains dispatch state */ 4622 4623 spapr_cpu->prod = false; 4624 if (spapr_cpu->vpa_addr) { 4625 CPUState *cs = CPU(cpu); 4626 uint32_t dispatch; 4627 4628 dispatch = ldl_be_phys(cs->as, 4629 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4630 dispatch++; 4631 if ((dispatch & 1) != 0) { 4632 qemu_log_mask(LOG_GUEST_ERROR, 4633 "VPA: incorrect dispatch counter value for " 4634 "dispatched partition %u, correcting.\n", dispatch); 4635 dispatch++; 4636 } 4637 stl_be_phys(cs->as, 4638 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4639 } 4640 } 4641 4642 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4643 { 4644 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4645 4646 if (spapr_cpu->vpa_addr) { 4647 CPUState *cs = CPU(cpu); 4648 uint32_t dispatch; 4649 4650 dispatch = ldl_be_phys(cs->as, 4651 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4652 dispatch++; 4653 if ((dispatch & 1) != 1) { 4654 qemu_log_mask(LOG_GUEST_ERROR, 4655 "VPA: incorrect dispatch counter value for " 4656 "preempted partition %u, correcting.\n", dispatch); 4657 dispatch++; 4658 } 4659 stl_be_phys(cs->as, 4660 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4661 } 4662 } 4663 4664 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4665 { 4666 MachineClass *mc = MACHINE_CLASS(oc); 4667 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4668 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4669 NMIClass *nc = NMI_CLASS(oc); 4670 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4671 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4672 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4673 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4674 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4675 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4676 4677 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4678 mc->ignore_boot_device_suffixes = true; 4679 4680 /* 4681 * We set up the default / latest behaviour here. The class_init 4682 * functions for the specific versioned machine types can override 4683 * these details for backwards compatibility 4684 */ 4685 mc->init = spapr_machine_init; 4686 mc->reset = spapr_machine_reset; 4687 mc->block_default_type = IF_SCSI; 4688 4689 /* 4690 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4691 * In TCG the limit is restricted by the range of CPU IPIs available. 4692 */ 4693 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4694 4695 mc->no_parallel = 1; 4696 mc->default_boot_order = ""; 4697 mc->default_ram_size = 512 * MiB; 4698 mc->default_ram_id = "ppc_spapr.ram"; 4699 mc->default_display = "std"; 4700 mc->kvm_type = spapr_kvm_type; 4701 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4702 mc->pci_allow_0_address = true; 4703 assert(!mc->get_hotplug_handler); 4704 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4705 hc->pre_plug = spapr_machine_device_pre_plug; 4706 hc->plug = spapr_machine_device_plug; 4707 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4708 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4709 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4710 hc->unplug_request = spapr_machine_device_unplug_request; 4711 hc->unplug = spapr_machine_device_unplug; 4712 4713 smc->dr_lmb_enabled = true; 4714 smc->update_dt_enabled = true; 4715 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4716 mc->has_hotpluggable_cpus = true; 4717 mc->nvdimm_supported = true; 4718 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4719 fwc->get_dev_path = spapr_get_fw_dev_path; 4720 nc->nmi_monitor_handler = spapr_nmi; 4721 smc->phb_placement = spapr_phb_placement; 4722 vhc->cpu_in_nested = spapr_cpu_in_nested; 4723 vhc->deliver_hv_excp = spapr_exit_nested; 4724 vhc->hypercall = emulate_spapr_hypercall; 4725 vhc->hpt_mask = spapr_hpt_mask; 4726 vhc->map_hptes = spapr_map_hptes; 4727 vhc->unmap_hptes = spapr_unmap_hptes; 4728 vhc->hpte_set_c = spapr_hpte_set_c; 4729 vhc->hpte_set_r = spapr_hpte_set_r; 4730 vhc->get_pate = spapr_get_pate; 4731 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4732 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4733 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4734 xic->ics_get = spapr_ics_get; 4735 xic->ics_resend = spapr_ics_resend; 4736 xic->icp_get = spapr_icp_get; 4737 ispc->print_info = spapr_pic_print_info; 4738 /* Force NUMA node memory size to be a multiple of 4739 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4740 * in which LMBs are represented and hot-added 4741 */ 4742 mc->numa_mem_align_shift = 28; 4743 mc->auto_enable_numa = true; 4744 4745 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4746 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4747 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4748 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4749 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4750 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4751 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4752 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4753 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4754 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4755 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4756 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4757 4758 /* 4759 * This cap specifies whether the AIL 3 mode for 4760 * H_SET_RESOURCE is supported. The default is modified 4761 * by default_caps_with_cpu(). 4762 */ 4763 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4764 spapr_caps_add_properties(smc); 4765 smc->irq = &spapr_irq_dual; 4766 smc->dr_phb_enabled = true; 4767 smc->linux_pci_probe = true; 4768 smc->smp_threads_vsmt = true; 4769 smc->nr_xirqs = SPAPR_NR_XIRQS; 4770 xfc->match_nvt = spapr_match_nvt; 4771 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4772 vmc->quiesce = spapr_vof_quiesce; 4773 vmc->setprop = spapr_vof_setprop; 4774 } 4775 4776 static const TypeInfo spapr_machine_info = { 4777 .name = TYPE_SPAPR_MACHINE, 4778 .parent = TYPE_MACHINE, 4779 .abstract = true, 4780 .instance_size = sizeof(SpaprMachineState), 4781 .instance_init = spapr_instance_init, 4782 .instance_finalize = spapr_machine_finalizefn, 4783 .class_size = sizeof(SpaprMachineClass), 4784 .class_init = spapr_machine_class_init, 4785 .interfaces = (InterfaceInfo[]) { 4786 { TYPE_FW_PATH_PROVIDER }, 4787 { TYPE_NMI }, 4788 { TYPE_HOTPLUG_HANDLER }, 4789 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4790 { TYPE_XICS_FABRIC }, 4791 { TYPE_INTERRUPT_STATS_PROVIDER }, 4792 { TYPE_XIVE_FABRIC }, 4793 { TYPE_VOF_MACHINE_IF }, 4794 { } 4795 }, 4796 }; 4797 4798 static void spapr_machine_latest_class_options(MachineClass *mc) 4799 { 4800 mc->alias = "pseries"; 4801 mc->is_default = true; 4802 } 4803 4804 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4805 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4806 void *data) \ 4807 { \ 4808 MachineClass *mc = MACHINE_CLASS(oc); \ 4809 spapr_machine_##suffix##_class_options(mc); \ 4810 if (latest) { \ 4811 spapr_machine_latest_class_options(mc); \ 4812 } \ 4813 } \ 4814 static const TypeInfo spapr_machine_##suffix##_info = { \ 4815 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4816 .parent = TYPE_SPAPR_MACHINE, \ 4817 .class_init = spapr_machine_##suffix##_class_init, \ 4818 }; \ 4819 static void spapr_machine_register_##suffix(void) \ 4820 { \ 4821 type_register(&spapr_machine_##suffix##_info); \ 4822 } \ 4823 type_init(spapr_machine_register_##suffix) 4824 4825 /* 4826 * pseries-9.0 4827 */ 4828 static void spapr_machine_9_0_class_options(MachineClass *mc) 4829 { 4830 /* Defaults for the latest behaviour inherited from the base class */ 4831 } 4832 4833 DEFINE_SPAPR_MACHINE(9_0, "9.0", true); 4834 4835 /* 4836 * pseries-8.2 4837 */ 4838 static void spapr_machine_8_2_class_options(MachineClass *mc) 4839 { 4840 spapr_machine_9_0_class_options(mc); 4841 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4842 } 4843 4844 DEFINE_SPAPR_MACHINE(8_2, "8.2", false); 4845 4846 /* 4847 * pseries-8.1 4848 */ 4849 static void spapr_machine_8_1_class_options(MachineClass *mc) 4850 { 4851 spapr_machine_8_2_class_options(mc); 4852 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4853 } 4854 4855 DEFINE_SPAPR_MACHINE(8_1, "8.1", false); 4856 4857 /* 4858 * pseries-8.0 4859 */ 4860 static void spapr_machine_8_0_class_options(MachineClass *mc) 4861 { 4862 spapr_machine_8_1_class_options(mc); 4863 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4864 } 4865 4866 DEFINE_SPAPR_MACHINE(8_0, "8.0", false); 4867 4868 /* 4869 * pseries-7.2 4870 */ 4871 static void spapr_machine_7_2_class_options(MachineClass *mc) 4872 { 4873 spapr_machine_8_0_class_options(mc); 4874 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4875 } 4876 4877 DEFINE_SPAPR_MACHINE(7_2, "7.2", false); 4878 4879 /* 4880 * pseries-7.1 4881 */ 4882 static void spapr_machine_7_1_class_options(MachineClass *mc) 4883 { 4884 spapr_machine_7_2_class_options(mc); 4885 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4886 } 4887 4888 DEFINE_SPAPR_MACHINE(7_1, "7.1", false); 4889 4890 /* 4891 * pseries-7.0 4892 */ 4893 static void spapr_machine_7_0_class_options(MachineClass *mc) 4894 { 4895 spapr_machine_7_1_class_options(mc); 4896 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4897 } 4898 4899 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4900 4901 /* 4902 * pseries-6.2 4903 */ 4904 static void spapr_machine_6_2_class_options(MachineClass *mc) 4905 { 4906 spapr_machine_7_0_class_options(mc); 4907 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4908 } 4909 4910 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4911 4912 /* 4913 * pseries-6.1 4914 */ 4915 static void spapr_machine_6_1_class_options(MachineClass *mc) 4916 { 4917 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4918 4919 spapr_machine_6_2_class_options(mc); 4920 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4921 smc->pre_6_2_numa_affinity = true; 4922 mc->smp_props.prefer_sockets = true; 4923 } 4924 4925 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4926 4927 /* 4928 * pseries-6.0 4929 */ 4930 static void spapr_machine_6_0_class_options(MachineClass *mc) 4931 { 4932 spapr_machine_6_1_class_options(mc); 4933 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4934 } 4935 4936 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4937 4938 /* 4939 * pseries-5.2 4940 */ 4941 static void spapr_machine_5_2_class_options(MachineClass *mc) 4942 { 4943 spapr_machine_6_0_class_options(mc); 4944 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4945 } 4946 4947 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4948 4949 /* 4950 * pseries-5.1 4951 */ 4952 static void spapr_machine_5_1_class_options(MachineClass *mc) 4953 { 4954 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4955 4956 spapr_machine_5_2_class_options(mc); 4957 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4958 smc->pre_5_2_numa_associativity = true; 4959 } 4960 4961 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4962 4963 /* 4964 * pseries-5.0 4965 */ 4966 static void spapr_machine_5_0_class_options(MachineClass *mc) 4967 { 4968 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4969 static GlobalProperty compat[] = { 4970 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4971 }; 4972 4973 spapr_machine_5_1_class_options(mc); 4974 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4975 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4976 mc->numa_mem_supported = true; 4977 smc->pre_5_1_assoc_refpoints = true; 4978 } 4979 4980 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4981 4982 /* 4983 * pseries-4.2 4984 */ 4985 static void spapr_machine_4_2_class_options(MachineClass *mc) 4986 { 4987 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4988 4989 spapr_machine_5_0_class_options(mc); 4990 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4991 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4992 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4993 smc->rma_limit = 16 * GiB; 4994 mc->nvdimm_supported = false; 4995 } 4996 4997 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4998 4999 /* 5000 * pseries-4.1 5001 */ 5002 static void spapr_machine_4_1_class_options(MachineClass *mc) 5003 { 5004 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5005 static GlobalProperty compat[] = { 5006 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 5007 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 5008 }; 5009 5010 spapr_machine_4_2_class_options(mc); 5011 smc->linux_pci_probe = false; 5012 smc->smp_threads_vsmt = false; 5013 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 5014 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5015 } 5016 5017 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 5018 5019 /* 5020 * pseries-4.0 5021 */ 5022 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 5023 uint64_t *buid, hwaddr *pio, 5024 hwaddr *mmio32, hwaddr *mmio64, 5025 unsigned n_dma, uint32_t *liobns, Error **errp) 5026 { 5027 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 5028 liobns, errp)) { 5029 return false; 5030 } 5031 return true; 5032 } 5033 static void spapr_machine_4_0_class_options(MachineClass *mc) 5034 { 5035 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5036 5037 spapr_machine_4_1_class_options(mc); 5038 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 5039 smc->phb_placement = phb_placement_4_0; 5040 smc->irq = &spapr_irq_xics; 5041 smc->pre_4_1_migration = true; 5042 } 5043 5044 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 5045 5046 /* 5047 * pseries-3.1 5048 */ 5049 static void spapr_machine_3_1_class_options(MachineClass *mc) 5050 { 5051 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5052 5053 spapr_machine_4_0_class_options(mc); 5054 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 5055 5056 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 5057 smc->update_dt_enabled = false; 5058 smc->dr_phb_enabled = false; 5059 smc->broken_host_serial_model = true; 5060 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5061 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5062 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5063 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5064 } 5065 5066 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 5067 5068 /* 5069 * pseries-3.0 5070 */ 5071 5072 static void spapr_machine_3_0_class_options(MachineClass *mc) 5073 { 5074 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5075 5076 spapr_machine_3_1_class_options(mc); 5077 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5078 5079 smc->legacy_irq_allocation = true; 5080 smc->nr_xirqs = 0x400; 5081 smc->irq = &spapr_irq_xics_legacy; 5082 } 5083 5084 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 5085 5086 /* 5087 * pseries-2.12 5088 */ 5089 static void spapr_machine_2_12_class_options(MachineClass *mc) 5090 { 5091 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5092 static GlobalProperty compat[] = { 5093 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 5094 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 5095 }; 5096 5097 spapr_machine_3_0_class_options(mc); 5098 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 5099 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5100 5101 /* We depend on kvm_enabled() to choose a default value for the 5102 * hpt-max-page-size capability. Of course we can't do it here 5103 * because this is too early and the HW accelerator isn't initialized 5104 * yet. Postpone this to machine init (see default_caps_with_cpu()). 5105 */ 5106 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 5107 } 5108 5109 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 5110 5111 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 5112 { 5113 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5114 5115 spapr_machine_2_12_class_options(mc); 5116 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 5117 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 5118 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 5119 } 5120 5121 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 5122 5123 /* 5124 * pseries-2.11 5125 */ 5126 5127 static void spapr_machine_2_11_class_options(MachineClass *mc) 5128 { 5129 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5130 5131 spapr_machine_2_12_class_options(mc); 5132 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5133 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5134 mc->deprecation_reason = "old and not maintained - use a 2.12+ version"; 5135 } 5136 5137 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 5138 5139 /* 5140 * pseries-2.10 5141 */ 5142 5143 static void spapr_machine_2_10_class_options(MachineClass *mc) 5144 { 5145 spapr_machine_2_11_class_options(mc); 5146 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5147 } 5148 5149 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 5150 5151 /* 5152 * pseries-2.9 5153 */ 5154 5155 static void spapr_machine_2_9_class_options(MachineClass *mc) 5156 { 5157 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5158 static GlobalProperty compat[] = { 5159 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5160 }; 5161 5162 spapr_machine_2_10_class_options(mc); 5163 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5164 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5165 smc->pre_2_10_has_unused_icps = true; 5166 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5167 } 5168 5169 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5170 5171 /* 5172 * pseries-2.8 5173 */ 5174 5175 static void spapr_machine_2_8_class_options(MachineClass *mc) 5176 { 5177 static GlobalProperty compat[] = { 5178 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5179 }; 5180 5181 spapr_machine_2_9_class_options(mc); 5182 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5183 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5184 mc->numa_mem_align_shift = 23; 5185 } 5186 5187 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5188 5189 /* 5190 * pseries-2.7 5191 */ 5192 5193 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5194 uint64_t *buid, hwaddr *pio, 5195 hwaddr *mmio32, hwaddr *mmio64, 5196 unsigned n_dma, uint32_t *liobns, Error **errp) 5197 { 5198 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5199 const uint64_t base_buid = 0x800000020000000ULL; 5200 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5201 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5202 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5203 const uint32_t max_index = 255; 5204 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5205 5206 uint64_t ram_top = MACHINE(spapr)->ram_size; 5207 hwaddr phb0_base, phb_base; 5208 int i; 5209 5210 /* Do we have device memory? */ 5211 if (MACHINE(spapr)->device_memory) { 5212 /* Can't just use maxram_size, because there may be an 5213 * alignment gap between normal and device memory regions 5214 */ 5215 ram_top = MACHINE(spapr)->device_memory->base + 5216 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5217 } 5218 5219 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5220 5221 if (index > max_index) { 5222 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5223 max_index); 5224 return false; 5225 } 5226 5227 *buid = base_buid + index; 5228 for (i = 0; i < n_dma; ++i) { 5229 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5230 } 5231 5232 phb_base = phb0_base + index * phb_spacing; 5233 *pio = phb_base + pio_offset; 5234 *mmio32 = phb_base + mmio_offset; 5235 /* 5236 * We don't set the 64-bit MMIO window, relying on the PHB's 5237 * fallback behaviour of automatically splitting a large "32-bit" 5238 * window into contiguous 32-bit and 64-bit windows 5239 */ 5240 5241 return true; 5242 } 5243 5244 static void spapr_machine_2_7_class_options(MachineClass *mc) 5245 { 5246 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5247 static GlobalProperty compat[] = { 5248 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5249 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5250 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5251 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5252 }; 5253 5254 spapr_machine_2_8_class_options(mc); 5255 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5256 mc->default_machine_opts = "modern-hotplug-events=off"; 5257 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5258 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5259 smc->phb_placement = phb_placement_2_7; 5260 } 5261 5262 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5263 5264 /* 5265 * pseries-2.6 5266 */ 5267 5268 static void spapr_machine_2_6_class_options(MachineClass *mc) 5269 { 5270 static GlobalProperty compat[] = { 5271 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5272 }; 5273 5274 spapr_machine_2_7_class_options(mc); 5275 mc->has_hotpluggable_cpus = false; 5276 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5277 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5278 } 5279 5280 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5281 5282 /* 5283 * pseries-2.5 5284 */ 5285 5286 static void spapr_machine_2_5_class_options(MachineClass *mc) 5287 { 5288 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5289 static GlobalProperty compat[] = { 5290 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5291 }; 5292 5293 spapr_machine_2_6_class_options(mc); 5294 smc->use_ohci_by_default = true; 5295 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5296 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5297 } 5298 5299 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5300 5301 /* 5302 * pseries-2.4 5303 */ 5304 5305 static void spapr_machine_2_4_class_options(MachineClass *mc) 5306 { 5307 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5308 5309 spapr_machine_2_5_class_options(mc); 5310 smc->dr_lmb_enabled = false; 5311 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5312 } 5313 5314 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5315 5316 /* 5317 * pseries-2.3 5318 */ 5319 5320 static void spapr_machine_2_3_class_options(MachineClass *mc) 5321 { 5322 static GlobalProperty compat[] = { 5323 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5324 }; 5325 spapr_machine_2_4_class_options(mc); 5326 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5327 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5328 } 5329 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5330 5331 /* 5332 * pseries-2.2 5333 */ 5334 5335 static void spapr_machine_2_2_class_options(MachineClass *mc) 5336 { 5337 static GlobalProperty compat[] = { 5338 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5339 }; 5340 5341 spapr_machine_2_3_class_options(mc); 5342 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5343 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5344 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5345 } 5346 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5347 5348 /* 5349 * pseries-2.1 5350 */ 5351 5352 static void spapr_machine_2_1_class_options(MachineClass *mc) 5353 { 5354 spapr_machine_2_2_class_options(mc); 5355 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5356 } 5357 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5358 5359 static void spapr_machine_register_types(void) 5360 { 5361 type_register_static(&spapr_machine_info); 5362 } 5363 5364 type_init(spapr_machine_register_types) 5365