1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define FDT_MAX_SIZE 0x100000 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 /* Populate the "ibm,pa-features" property */ 221 static void spapr_populate_pa_features(SpaprMachineState *spapr, 222 PowerPCCPU *cpu, 223 void *fdt, int offset) 224 { 225 uint8_t pa_features_206[] = { 6, 0, 226 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 227 uint8_t pa_features_207[] = { 24, 0, 228 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 230 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 232 uint8_t pa_features_300[] = { 66, 0, 233 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 234 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 235 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 236 /* 6: DS207 */ 237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 238 /* 16: Vector */ 239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 240 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 242 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 244 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 245 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 246 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 248 /* 42: PM, 44: PC RA, 46: SC vec'd */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 250 /* 48: SIMD, 50: QP BFP, 52: String */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 252 /* 54: DecFP, 56: DecI, 58: SHA */ 253 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 254 /* 60: NM atomic, 62: RNG */ 255 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 256 }; 257 uint8_t *pa_features = NULL; 258 size_t pa_size; 259 260 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 261 pa_features = pa_features_206; 262 pa_size = sizeof(pa_features_206); 263 } 264 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 265 pa_features = pa_features_207; 266 pa_size = sizeof(pa_features_207); 267 } 268 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 269 pa_features = pa_features_300; 270 pa_size = sizeof(pa_features_300); 271 } 272 if (!pa_features) { 273 return; 274 } 275 276 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 277 /* 278 * Note: we keep CI large pages off by default because a 64K capable 279 * guest provisioned with large pages might otherwise try to map a qemu 280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 281 * even if that qemu runs on a 4k host. 282 * We dd this bit back here if we are confident this is not an issue 283 */ 284 pa_features[3] |= 0x20; 285 } 286 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 287 pa_features[24] |= 0x80; /* Transactional memory support */ 288 } 289 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 290 /* Workaround for broken kernels that attempt (guest) radix 291 * mode when they can't handle it, if they see the radix bit set 292 * in pa-features. So hide it from them. */ 293 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 294 } 295 296 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 297 } 298 299 static hwaddr spapr_node0_size(MachineState *machine) 300 { 301 if (machine->numa_state->num_nodes) { 302 int i; 303 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 304 if (machine->numa_state->nodes[i].node_mem) { 305 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 306 machine->ram_size); 307 } 308 } 309 } 310 return machine->ram_size; 311 } 312 313 static void add_str(GString *s, const gchar *s1) 314 { 315 g_string_append_len(s, s1, strlen(s1) + 1); 316 } 317 318 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 319 hwaddr size) 320 { 321 uint32_t associativity[] = { 322 cpu_to_be32(0x4), /* length */ 323 cpu_to_be32(0x0), cpu_to_be32(0x0), 324 cpu_to_be32(0x0), cpu_to_be32(nodeid) 325 }; 326 char mem_name[32]; 327 uint64_t mem_reg_property[2]; 328 int off; 329 330 mem_reg_property[0] = cpu_to_be64(start); 331 mem_reg_property[1] = cpu_to_be64(size); 332 333 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 334 off = fdt_add_subnode(fdt, 0, mem_name); 335 _FDT(off); 336 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 337 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 338 sizeof(mem_reg_property)))); 339 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 340 sizeof(associativity)))); 341 return off; 342 } 343 344 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 345 { 346 MachineState *machine = MACHINE(spapr); 347 hwaddr mem_start, node_size; 348 int i, nb_nodes = machine->numa_state->num_nodes; 349 NodeInfo *nodes = machine->numa_state->nodes; 350 351 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 352 if (!nodes[i].node_mem) { 353 continue; 354 } 355 if (mem_start >= machine->ram_size) { 356 node_size = 0; 357 } else { 358 node_size = nodes[i].node_mem; 359 if (node_size > machine->ram_size - mem_start) { 360 node_size = machine->ram_size - mem_start; 361 } 362 } 363 if (!mem_start) { 364 /* spapr_machine_init() checks for rma_size <= node0_size 365 * already */ 366 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 367 mem_start += spapr->rma_size; 368 node_size -= spapr->rma_size; 369 } 370 for ( ; node_size; ) { 371 hwaddr sizetmp = pow2floor(node_size); 372 373 /* mem_start != 0 here */ 374 if (ctzl(mem_start) < ctzl(sizetmp)) { 375 sizetmp = 1ULL << ctzl(mem_start); 376 } 377 378 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 379 node_size -= sizetmp; 380 mem_start += sizetmp; 381 } 382 } 383 384 return 0; 385 } 386 387 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 388 SpaprMachineState *spapr) 389 { 390 MachineState *ms = MACHINE(spapr); 391 PowerPCCPU *cpu = POWERPC_CPU(cs); 392 CPUPPCState *env = &cpu->env; 393 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 394 int index = spapr_get_vcpu_id(cpu); 395 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 396 0xffffffff, 0xffffffff}; 397 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 398 : SPAPR_TIMEBASE_FREQ; 399 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 400 uint32_t page_sizes_prop[64]; 401 size_t page_sizes_prop_size; 402 unsigned int smp_threads = ms->smp.threads; 403 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 404 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 405 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 406 SpaprDrc *drc; 407 int drc_index; 408 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 409 int i; 410 411 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 412 if (drc) { 413 drc_index = spapr_drc_index(drc); 414 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 415 } 416 417 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 418 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 419 420 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 421 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 422 env->dcache_line_size))); 423 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 424 env->dcache_line_size))); 425 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 426 env->icache_line_size))); 427 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 428 env->icache_line_size))); 429 430 if (pcc->l1_dcache_size) { 431 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 432 pcc->l1_dcache_size))); 433 } else { 434 warn_report("Unknown L1 dcache size for cpu"); 435 } 436 if (pcc->l1_icache_size) { 437 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 438 pcc->l1_icache_size))); 439 } else { 440 warn_report("Unknown L1 icache size for cpu"); 441 } 442 443 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 445 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 447 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 448 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 449 450 if (env->spr_cb[SPR_PURR].oea_read) { 451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 452 } 453 if (env->spr_cb[SPR_SPURR].oea_read) { 454 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 455 } 456 457 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 458 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 459 segs, sizeof(segs)))); 460 } 461 462 /* Advertise VSX (vector extensions) if available 463 * 1 == VMX / Altivec available 464 * 2 == VSX available 465 * 466 * Only CPUs for which we create core types in spapr_cpu_core.c 467 * are possible, and all of those have VMX */ 468 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 469 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 470 } else { 471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 472 } 473 474 /* Advertise DFP (Decimal Floating Point) if available 475 * 0 / no property == no DFP 476 * 1 == DFP available */ 477 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 479 } 480 481 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 482 sizeof(page_sizes_prop)); 483 if (page_sizes_prop_size) { 484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 485 page_sizes_prop, page_sizes_prop_size))); 486 } 487 488 spapr_populate_pa_features(spapr, cpu, fdt, offset); 489 490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 491 cs->cpu_index / vcpus_per_socket))); 492 493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 494 pft_size_prop, sizeof(pft_size_prop)))); 495 496 if (ms->numa_state->num_nodes > 1) { 497 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 498 } 499 500 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 501 502 if (pcc->radix_page_info) { 503 for (i = 0; i < pcc->radix_page_info->count; i++) { 504 radix_AP_encodings[i] = 505 cpu_to_be32(pcc->radix_page_info->entries[i]); 506 } 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 508 radix_AP_encodings, 509 pcc->radix_page_info->count * 510 sizeof(radix_AP_encodings[0])))); 511 } 512 513 /* 514 * We set this property to let the guest know that it can use the large 515 * decrementer and its width in bits. 516 */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 518 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 519 pcc->lrg_decr_bits))); 520 } 521 522 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 523 { 524 CPUState **rev; 525 CPUState *cs; 526 int n_cpus; 527 int cpus_offset; 528 char *nodename; 529 int i; 530 531 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 532 _FDT(cpus_offset); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 534 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 535 536 /* 537 * We walk the CPUs in reverse order to ensure that CPU DT nodes 538 * created by fdt_add_subnode() end up in the right order in FDT 539 * for the guest kernel the enumerate the CPUs correctly. 540 * 541 * The CPU list cannot be traversed in reverse order, so we need 542 * to do extra work. 543 */ 544 n_cpus = 0; 545 rev = NULL; 546 CPU_FOREACH(cs) { 547 rev = g_renew(CPUState *, rev, n_cpus + 1); 548 rev[n_cpus++] = cs; 549 } 550 551 for (i = n_cpus - 1; i >= 0; i--) { 552 CPUState *cs = rev[i]; 553 PowerPCCPU *cpu = POWERPC_CPU(cs); 554 int index = spapr_get_vcpu_id(cpu); 555 DeviceClass *dc = DEVICE_GET_CLASS(cs); 556 int offset; 557 558 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 559 continue; 560 } 561 562 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 563 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 564 g_free(nodename); 565 _FDT(offset); 566 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 567 } 568 569 g_free(rev); 570 } 571 572 static int spapr_rng_populate_dt(void *fdt) 573 { 574 int node; 575 int ret; 576 577 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 578 if (node <= 0) { 579 return -1; 580 } 581 ret = fdt_setprop_string(fdt, node, "device_type", 582 "ibm,platform-facilities"); 583 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 584 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 585 586 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 587 if (node <= 0) { 588 return -1; 589 } 590 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 591 592 return ret ? -1 : 0; 593 } 594 595 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 596 { 597 MemoryDeviceInfoList *info; 598 599 for (info = list; info; info = info->next) { 600 MemoryDeviceInfo *value = info->value; 601 602 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 603 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 604 605 if (addr >= pcdimm_info->addr && 606 addr < (pcdimm_info->addr + pcdimm_info->size)) { 607 return pcdimm_info->node; 608 } 609 } 610 } 611 612 return -1; 613 } 614 615 struct sPAPRDrconfCellV2 { 616 uint32_t seq_lmbs; 617 uint64_t base_addr; 618 uint32_t drc_index; 619 uint32_t aa_index; 620 uint32_t flags; 621 } QEMU_PACKED; 622 623 typedef struct DrconfCellQueue { 624 struct sPAPRDrconfCellV2 cell; 625 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 626 } DrconfCellQueue; 627 628 static DrconfCellQueue * 629 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 630 uint32_t drc_index, uint32_t aa_index, 631 uint32_t flags) 632 { 633 DrconfCellQueue *elem; 634 635 elem = g_malloc0(sizeof(*elem)); 636 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 637 elem->cell.base_addr = cpu_to_be64(base_addr); 638 elem->cell.drc_index = cpu_to_be32(drc_index); 639 elem->cell.aa_index = cpu_to_be32(aa_index); 640 elem->cell.flags = cpu_to_be32(flags); 641 642 return elem; 643 } 644 645 /* ibm,dynamic-memory-v2 */ 646 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 647 int offset, MemoryDeviceInfoList *dimms) 648 { 649 MachineState *machine = MACHINE(spapr); 650 uint8_t *int_buf, *cur_index; 651 int ret; 652 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 653 uint64_t addr, cur_addr, size; 654 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 655 uint64_t mem_end = machine->device_memory->base + 656 memory_region_size(&machine->device_memory->mr); 657 uint32_t node, buf_len, nr_entries = 0; 658 SpaprDrc *drc; 659 DrconfCellQueue *elem, *next; 660 MemoryDeviceInfoList *info; 661 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 662 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 663 664 /* Entry to cover RAM and the gap area */ 665 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 666 SPAPR_LMB_FLAGS_RESERVED | 667 SPAPR_LMB_FLAGS_DRC_INVALID); 668 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 669 nr_entries++; 670 671 cur_addr = machine->device_memory->base; 672 for (info = dimms; info; info = info->next) { 673 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 674 675 addr = di->addr; 676 size = di->size; 677 node = di->node; 678 679 /* 680 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 681 * area is marked hotpluggable in the next iteration for the bigger 682 * chunk including the NVDIMM occupied area. 683 */ 684 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 685 continue; 686 687 /* Entry for hot-pluggable area */ 688 if (cur_addr < addr) { 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 692 cur_addr, spapr_drc_index(drc), -1, 0); 693 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 694 nr_entries++; 695 } 696 697 /* Entry for DIMM */ 698 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 699 g_assert(drc); 700 elem = spapr_get_drconf_cell(size / lmb_size, addr, 701 spapr_drc_index(drc), node, 702 SPAPR_LMB_FLAGS_ASSIGNED); 703 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 704 nr_entries++; 705 cur_addr = addr + size; 706 } 707 708 /* Entry for remaining hotpluggable area */ 709 if (cur_addr < mem_end) { 710 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 711 g_assert(drc); 712 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 713 cur_addr, spapr_drc_index(drc), -1, 0); 714 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 715 nr_entries++; 716 } 717 718 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 719 int_buf = cur_index = g_malloc0(buf_len); 720 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 721 cur_index += sizeof(nr_entries); 722 723 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 724 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 725 cur_index += sizeof(elem->cell); 726 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 727 g_free(elem); 728 } 729 730 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 731 g_free(int_buf); 732 if (ret < 0) { 733 return -1; 734 } 735 return 0; 736 } 737 738 /* ibm,dynamic-memory */ 739 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 740 int offset, MemoryDeviceInfoList *dimms) 741 { 742 MachineState *machine = MACHINE(spapr); 743 int i, ret; 744 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 745 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 746 uint32_t nr_lmbs = (machine->device_memory->base + 747 memory_region_size(&machine->device_memory->mr)) / 748 lmb_size; 749 uint32_t *int_buf, *cur_index, buf_len; 750 751 /* 752 * Allocate enough buffer size to fit in ibm,dynamic-memory 753 */ 754 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 755 cur_index = int_buf = g_malloc0(buf_len); 756 int_buf[0] = cpu_to_be32(nr_lmbs); 757 cur_index++; 758 for (i = 0; i < nr_lmbs; i++) { 759 uint64_t addr = i * lmb_size; 760 uint32_t *dynamic_memory = cur_index; 761 762 if (i >= device_lmb_start) { 763 SpaprDrc *drc; 764 765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 766 g_assert(drc); 767 768 dynamic_memory[0] = cpu_to_be32(addr >> 32); 769 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 770 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 771 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 772 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 773 if (memory_region_present(get_system_memory(), addr)) { 774 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 775 } else { 776 dynamic_memory[5] = cpu_to_be32(0); 777 } 778 } else { 779 /* 780 * LMB information for RMA, boot time RAM and gap b/n RAM and 781 * device memory region -- all these are marked as reserved 782 * and as having no valid DRC. 783 */ 784 dynamic_memory[0] = cpu_to_be32(addr >> 32); 785 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 786 dynamic_memory[2] = cpu_to_be32(0); 787 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 788 dynamic_memory[4] = cpu_to_be32(-1); 789 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 790 SPAPR_LMB_FLAGS_DRC_INVALID); 791 } 792 793 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 794 } 795 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 796 g_free(int_buf); 797 if (ret < 0) { 798 return -1; 799 } 800 return 0; 801 } 802 803 /* 804 * Adds ibm,dynamic-reconfiguration-memory node. 805 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 806 * of this device tree node. 807 */ 808 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 809 { 810 MachineState *machine = MACHINE(spapr); 811 int nb_numa_nodes = machine->numa_state->num_nodes; 812 int ret, i, offset; 813 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 814 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 815 uint32_t *int_buf, *cur_index, buf_len; 816 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 817 MemoryDeviceInfoList *dimms = NULL; 818 819 /* 820 * Don't create the node if there is no device memory 821 */ 822 if (machine->ram_size == machine->maxram_size) { 823 return 0; 824 } 825 826 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 827 828 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 829 sizeof(prop_lmb_size)); 830 if (ret < 0) { 831 return ret; 832 } 833 834 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 835 if (ret < 0) { 836 return ret; 837 } 838 839 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 840 if (ret < 0) { 841 return ret; 842 } 843 844 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 845 dimms = qmp_memory_device_list(); 846 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 847 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 848 } else { 849 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 850 } 851 qapi_free_MemoryDeviceInfoList(dimms); 852 853 if (ret < 0) { 854 return ret; 855 } 856 857 /* ibm,associativity-lookup-arrays */ 858 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 859 cur_index = int_buf = g_malloc0(buf_len); 860 int_buf[0] = cpu_to_be32(nr_nodes); 861 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 862 cur_index += 2; 863 for (i = 0; i < nr_nodes; i++) { 864 uint32_t associativity[] = { 865 cpu_to_be32(0x0), 866 cpu_to_be32(0x0), 867 cpu_to_be32(0x0), 868 cpu_to_be32(i) 869 }; 870 memcpy(cur_index, associativity, sizeof(associativity)); 871 cur_index += 4; 872 } 873 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 874 (cur_index - int_buf) * sizeof(uint32_t)); 875 g_free(int_buf); 876 877 return ret; 878 } 879 880 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 881 SpaprOptionVector *ov5_updates) 882 { 883 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 884 int ret = 0, offset; 885 886 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 887 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 888 g_assert(smc->dr_lmb_enabled); 889 ret = spapr_populate_drconf_memory(spapr, fdt); 890 if (ret) { 891 return ret; 892 } 893 } 894 895 offset = fdt_path_offset(fdt, "/chosen"); 896 if (offset < 0) { 897 offset = fdt_add_subnode(fdt, 0, "chosen"); 898 if (offset < 0) { 899 return offset; 900 } 901 } 902 return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 903 "ibm,architecture-vec-5"); 904 } 905 906 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 907 { 908 MachineState *ms = MACHINE(spapr); 909 int rtas; 910 GString *hypertas = g_string_sized_new(256); 911 GString *qemu_hypertas = g_string_sized_new(256); 912 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 913 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 914 memory_region_size(&MACHINE(spapr)->device_memory->mr); 915 uint32_t lrdr_capacity[] = { 916 cpu_to_be32(max_device_addr >> 32), 917 cpu_to_be32(max_device_addr & 0xffffffff), 918 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 919 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 920 }; 921 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 922 uint32_t maxdomains[] = { 923 cpu_to_be32(4), 924 maxdomain, 925 maxdomain, 926 maxdomain, 927 cpu_to_be32(spapr->gpu_numa_id), 928 }; 929 930 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 931 932 /* hypertas */ 933 add_str(hypertas, "hcall-pft"); 934 add_str(hypertas, "hcall-term"); 935 add_str(hypertas, "hcall-dabr"); 936 add_str(hypertas, "hcall-interrupt"); 937 add_str(hypertas, "hcall-tce"); 938 add_str(hypertas, "hcall-vio"); 939 add_str(hypertas, "hcall-splpar"); 940 add_str(hypertas, "hcall-join"); 941 add_str(hypertas, "hcall-bulk"); 942 add_str(hypertas, "hcall-set-mode"); 943 add_str(hypertas, "hcall-sprg0"); 944 add_str(hypertas, "hcall-copy"); 945 add_str(hypertas, "hcall-debug"); 946 add_str(hypertas, "hcall-vphn"); 947 add_str(qemu_hypertas, "hcall-memop1"); 948 949 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 950 add_str(hypertas, "hcall-multi-tce"); 951 } 952 953 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 954 add_str(hypertas, "hcall-hpt-resize"); 955 } 956 957 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 958 hypertas->str, hypertas->len)); 959 g_string_free(hypertas, TRUE); 960 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 961 qemu_hypertas->str, qemu_hypertas->len)); 962 g_string_free(qemu_hypertas, TRUE); 963 964 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 965 refpoints, sizeof(refpoints))); 966 967 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 968 maxdomains, sizeof(maxdomains))); 969 970 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_SIZE)); 971 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 972 RTAS_ERROR_LOG_MAX)); 973 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 974 RTAS_EVENT_SCAN_RATE)); 975 976 g_assert(msi_nonbroken); 977 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 978 979 /* 980 * According to PAPR, rtas ibm,os-term does not guarantee a return 981 * back to the guest cpu. 982 * 983 * While an additional ibm,extended-os-term property indicates 984 * that rtas call return will always occur. Set this property. 985 */ 986 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 987 988 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 989 lrdr_capacity, sizeof(lrdr_capacity))); 990 991 spapr_dt_rtas_tokens(fdt, rtas); 992 } 993 994 /* 995 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 996 * and the XIVE features that the guest may request and thus the valid 997 * values for bytes 23..26 of option vector 5: 998 */ 999 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1000 int chosen) 1001 { 1002 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1003 1004 char val[2 * 4] = { 1005 23, 0x00, /* XICS / XIVE mode */ 1006 24, 0x00, /* Hash/Radix, filled in below. */ 1007 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1008 26, 0x40, /* Radix options: GTSE == yes. */ 1009 }; 1010 1011 if (spapr->irq->xics && spapr->irq->xive) { 1012 val[1] = SPAPR_OV5_XIVE_BOTH; 1013 } else if (spapr->irq->xive) { 1014 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1015 } else { 1016 assert(spapr->irq->xics); 1017 val[1] = SPAPR_OV5_XIVE_LEGACY; 1018 } 1019 1020 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1021 first_ppc_cpu->compat_pvr)) { 1022 /* 1023 * If we're in a pre POWER9 compat mode then the guest should 1024 * do hash and use the legacy interrupt mode 1025 */ 1026 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1027 val[3] = 0x00; /* Hash */ 1028 } else if (kvm_enabled()) { 1029 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1030 val[3] = 0x80; /* OV5_MMU_BOTH */ 1031 } else if (kvmppc_has_cap_mmu_radix()) { 1032 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1033 } else { 1034 val[3] = 0x00; /* Hash */ 1035 } 1036 } else { 1037 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1038 val[3] = 0xC0; 1039 } 1040 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1041 val, sizeof(val))); 1042 } 1043 1044 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1045 { 1046 MachineState *machine = MACHINE(spapr); 1047 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1048 int chosen; 1049 const char *boot_device = machine->boot_order; 1050 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1051 size_t cb = 0; 1052 char *bootlist = get_boot_devices_list(&cb); 1053 1054 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1055 1056 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1057 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1058 machine->kernel_cmdline)); 1059 } 1060 if (spapr->initrd_size) { 1061 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1062 spapr->initrd_base)); 1063 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1064 spapr->initrd_base + spapr->initrd_size)); 1065 } 1066 1067 if (spapr->kernel_size) { 1068 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1069 cpu_to_be64(spapr->kernel_size) }; 1070 1071 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1072 &kprop, sizeof(kprop))); 1073 if (spapr->kernel_le) { 1074 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1075 } 1076 } 1077 if (boot_menu) { 1078 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1079 } 1080 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1081 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1082 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1083 1084 if (cb && bootlist) { 1085 int i; 1086 1087 for (i = 0; i < cb; i++) { 1088 if (bootlist[i] == '\n') { 1089 bootlist[i] = ' '; 1090 } 1091 } 1092 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1093 } 1094 1095 if (boot_device && strlen(boot_device)) { 1096 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1097 } 1098 1099 if (!spapr->has_graphics && stdout_path) { 1100 /* 1101 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1102 * kernel. New platforms should only use the "stdout-path" property. Set 1103 * the new property and continue using older property to remain 1104 * compatible with the existing firmware. 1105 */ 1106 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1107 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1108 } 1109 1110 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1111 if (smc->linux_pci_probe) { 1112 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1113 } 1114 1115 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1116 1117 g_free(stdout_path); 1118 g_free(bootlist); 1119 } 1120 1121 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1122 { 1123 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1124 * KVM to work under pHyp with some guest co-operation */ 1125 int hypervisor; 1126 uint8_t hypercall[16]; 1127 1128 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1129 /* indicate KVM hypercall interface */ 1130 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1131 if (kvmppc_has_cap_fixup_hcalls()) { 1132 /* 1133 * Older KVM versions with older guest kernels were broken 1134 * with the magic page, don't allow the guest to map it. 1135 */ 1136 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1137 sizeof(hypercall))) { 1138 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1139 hypercall, sizeof(hypercall))); 1140 } 1141 } 1142 } 1143 1144 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1145 { 1146 MachineState *machine = MACHINE(spapr); 1147 MachineClass *mc = MACHINE_GET_CLASS(machine); 1148 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1149 int ret; 1150 void *fdt; 1151 SpaprPhbState *phb; 1152 char *buf; 1153 1154 fdt = g_malloc0(space); 1155 _FDT((fdt_create_empty_tree(fdt, space))); 1156 1157 /* Root node */ 1158 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1159 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1160 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1161 1162 /* Guest UUID & Name*/ 1163 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1164 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1165 if (qemu_uuid_set) { 1166 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1167 } 1168 g_free(buf); 1169 1170 if (qemu_get_vm_name()) { 1171 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1172 qemu_get_vm_name())); 1173 } 1174 1175 /* Host Model & Serial Number */ 1176 if (spapr->host_model) { 1177 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1178 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1179 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1180 g_free(buf); 1181 } 1182 1183 if (spapr->host_serial) { 1184 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1185 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1186 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1187 g_free(buf); 1188 } 1189 1190 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1191 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1192 1193 /* /interrupt controller */ 1194 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1195 1196 ret = spapr_populate_memory(spapr, fdt); 1197 if (ret < 0) { 1198 error_report("couldn't setup memory nodes in fdt"); 1199 exit(1); 1200 } 1201 1202 /* /vdevice */ 1203 spapr_dt_vdevice(spapr->vio_bus, fdt); 1204 1205 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1206 ret = spapr_rng_populate_dt(fdt); 1207 if (ret < 0) { 1208 error_report("could not set up rng device in the fdt"); 1209 exit(1); 1210 } 1211 } 1212 1213 QLIST_FOREACH(phb, &spapr->phbs, list) { 1214 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1215 if (ret < 0) { 1216 error_report("couldn't setup PCI devices in fdt"); 1217 exit(1); 1218 } 1219 } 1220 1221 /* cpus */ 1222 spapr_populate_cpus_dt_node(fdt, spapr); 1223 1224 if (smc->dr_lmb_enabled) { 1225 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1226 } 1227 1228 if (mc->has_hotpluggable_cpus) { 1229 int offset = fdt_path_offset(fdt, "/cpus"); 1230 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1231 if (ret < 0) { 1232 error_report("Couldn't set up CPU DR device tree properties"); 1233 exit(1); 1234 } 1235 } 1236 1237 /* /event-sources */ 1238 spapr_dt_events(spapr, fdt); 1239 1240 /* /rtas */ 1241 spapr_dt_rtas(spapr, fdt); 1242 1243 /* /chosen */ 1244 if (reset) { 1245 spapr_dt_chosen(spapr, fdt); 1246 } 1247 1248 /* /hypervisor */ 1249 if (kvm_enabled()) { 1250 spapr_dt_hypervisor(spapr, fdt); 1251 } 1252 1253 /* Build memory reserve map */ 1254 if (reset) { 1255 if (spapr->kernel_size) { 1256 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1257 spapr->kernel_size))); 1258 } 1259 if (spapr->initrd_size) { 1260 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1261 spapr->initrd_size))); 1262 } 1263 } 1264 1265 /* ibm,client-architecture-support updates */ 1266 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1267 if (ret < 0) { 1268 error_report("couldn't setup CAS properties fdt"); 1269 exit(1); 1270 } 1271 1272 if (smc->dr_phb_enabled) { 1273 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1274 if (ret < 0) { 1275 error_report("Couldn't set up PHB DR device tree properties"); 1276 exit(1); 1277 } 1278 } 1279 1280 /* NVDIMM devices */ 1281 if (mc->nvdimm_supported) { 1282 spapr_dt_persistent_memory(fdt); 1283 } 1284 1285 return fdt; 1286 } 1287 1288 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1289 { 1290 SpaprMachineState *spapr = opaque; 1291 1292 return (addr & 0x0fffffff) + spapr->kernel_addr; 1293 } 1294 1295 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1296 PowerPCCPU *cpu) 1297 { 1298 CPUPPCState *env = &cpu->env; 1299 1300 /* The TCG path should also be holding the BQL at this point */ 1301 g_assert(qemu_mutex_iothread_locked()); 1302 1303 if (msr_pr) { 1304 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1305 env->gpr[3] = H_PRIVILEGE; 1306 } else { 1307 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1308 } 1309 } 1310 1311 struct LPCRSyncState { 1312 target_ulong value; 1313 target_ulong mask; 1314 }; 1315 1316 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1317 { 1318 struct LPCRSyncState *s = arg.host_ptr; 1319 PowerPCCPU *cpu = POWERPC_CPU(cs); 1320 CPUPPCState *env = &cpu->env; 1321 target_ulong lpcr; 1322 1323 cpu_synchronize_state(cs); 1324 lpcr = env->spr[SPR_LPCR]; 1325 lpcr &= ~s->mask; 1326 lpcr |= s->value; 1327 ppc_store_lpcr(cpu, lpcr); 1328 } 1329 1330 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1331 { 1332 CPUState *cs; 1333 struct LPCRSyncState s = { 1334 .value = value, 1335 .mask = mask 1336 }; 1337 CPU_FOREACH(cs) { 1338 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1339 } 1340 } 1341 1342 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1343 { 1344 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1345 1346 /* Copy PATE1:GR into PATE0:HR */ 1347 entry->dw0 = spapr->patb_entry & PATE0_HR; 1348 entry->dw1 = spapr->patb_entry; 1349 } 1350 1351 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1352 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1353 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1354 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1355 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1356 1357 /* 1358 * Get the fd to access the kernel htab, re-opening it if necessary 1359 */ 1360 static int get_htab_fd(SpaprMachineState *spapr) 1361 { 1362 Error *local_err = NULL; 1363 1364 if (spapr->htab_fd >= 0) { 1365 return spapr->htab_fd; 1366 } 1367 1368 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1369 if (spapr->htab_fd < 0) { 1370 error_report_err(local_err); 1371 } 1372 1373 return spapr->htab_fd; 1374 } 1375 1376 void close_htab_fd(SpaprMachineState *spapr) 1377 { 1378 if (spapr->htab_fd >= 0) { 1379 close(spapr->htab_fd); 1380 } 1381 spapr->htab_fd = -1; 1382 } 1383 1384 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1385 { 1386 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1387 1388 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1389 } 1390 1391 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1392 { 1393 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1394 1395 assert(kvm_enabled()); 1396 1397 if (!spapr->htab) { 1398 return 0; 1399 } 1400 1401 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1402 } 1403 1404 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1405 hwaddr ptex, int n) 1406 { 1407 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1408 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1409 1410 if (!spapr->htab) { 1411 /* 1412 * HTAB is controlled by KVM. Fetch into temporary buffer 1413 */ 1414 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1415 kvmppc_read_hptes(hptes, ptex, n); 1416 return hptes; 1417 } 1418 1419 /* 1420 * HTAB is controlled by QEMU. Just point to the internally 1421 * accessible PTEG. 1422 */ 1423 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1424 } 1425 1426 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1427 const ppc_hash_pte64_t *hptes, 1428 hwaddr ptex, int n) 1429 { 1430 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1431 1432 if (!spapr->htab) { 1433 g_free((void *)hptes); 1434 } 1435 1436 /* Nothing to do for qemu managed HPT */ 1437 } 1438 1439 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1440 uint64_t pte0, uint64_t pte1) 1441 { 1442 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1443 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1444 1445 if (!spapr->htab) { 1446 kvmppc_write_hpte(ptex, pte0, pte1); 1447 } else { 1448 if (pte0 & HPTE64_V_VALID) { 1449 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1450 /* 1451 * When setting valid, we write PTE1 first. This ensures 1452 * proper synchronization with the reading code in 1453 * ppc_hash64_pteg_search() 1454 */ 1455 smp_wmb(); 1456 stq_p(spapr->htab + offset, pte0); 1457 } else { 1458 stq_p(spapr->htab + offset, pte0); 1459 /* 1460 * When clearing it we set PTE0 first. This ensures proper 1461 * synchronization with the reading code in 1462 * ppc_hash64_pteg_search() 1463 */ 1464 smp_wmb(); 1465 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1466 } 1467 } 1468 } 1469 1470 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1471 uint64_t pte1) 1472 { 1473 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1474 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1475 1476 if (!spapr->htab) { 1477 /* There should always be a hash table when this is called */ 1478 error_report("spapr_hpte_set_c called with no hash table !"); 1479 return; 1480 } 1481 1482 /* The HW performs a non-atomic byte update */ 1483 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1484 } 1485 1486 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1487 uint64_t pte1) 1488 { 1489 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1490 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1491 1492 if (!spapr->htab) { 1493 /* There should always be a hash table when this is called */ 1494 error_report("spapr_hpte_set_r called with no hash table !"); 1495 return; 1496 } 1497 1498 /* The HW performs a non-atomic byte update */ 1499 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1500 } 1501 1502 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1503 { 1504 int shift; 1505 1506 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1507 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1508 * that's much more than is needed for Linux guests */ 1509 shift = ctz64(pow2ceil(ramsize)) - 7; 1510 shift = MAX(shift, 18); /* Minimum architected size */ 1511 shift = MIN(shift, 46); /* Maximum architected size */ 1512 return shift; 1513 } 1514 1515 void spapr_free_hpt(SpaprMachineState *spapr) 1516 { 1517 g_free(spapr->htab); 1518 spapr->htab = NULL; 1519 spapr->htab_shift = 0; 1520 close_htab_fd(spapr); 1521 } 1522 1523 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1524 Error **errp) 1525 { 1526 long rc; 1527 1528 /* Clean up any HPT info from a previous boot */ 1529 spapr_free_hpt(spapr); 1530 1531 rc = kvmppc_reset_htab(shift); 1532 if (rc < 0) { 1533 /* kernel-side HPT needed, but couldn't allocate one */ 1534 error_setg_errno(errp, errno, 1535 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1536 shift); 1537 /* This is almost certainly fatal, but if the caller really 1538 * wants to carry on with shift == 0, it's welcome to try */ 1539 } else if (rc > 0) { 1540 /* kernel-side HPT allocated */ 1541 if (rc != shift) { 1542 error_setg(errp, 1543 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1544 shift, rc); 1545 } 1546 1547 spapr->htab_shift = shift; 1548 spapr->htab = NULL; 1549 } else { 1550 /* kernel-side HPT not needed, allocate in userspace instead */ 1551 size_t size = 1ULL << shift; 1552 int i; 1553 1554 spapr->htab = qemu_memalign(size, size); 1555 if (!spapr->htab) { 1556 error_setg_errno(errp, errno, 1557 "Could not allocate HPT of order %d", shift); 1558 return; 1559 } 1560 1561 memset(spapr->htab, 0, size); 1562 spapr->htab_shift = shift; 1563 1564 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1565 DIRTY_HPTE(HPTE(spapr->htab, i)); 1566 } 1567 } 1568 /* We're setting up a hash table, so that means we're not radix */ 1569 spapr->patb_entry = 0; 1570 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1571 } 1572 1573 void spapr_setup_hpt(SpaprMachineState *spapr) 1574 { 1575 int hpt_shift; 1576 1577 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1578 || (spapr->cas_reboot 1579 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1580 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1581 } else { 1582 uint64_t current_ram_size; 1583 1584 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1585 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1586 } 1587 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1588 1589 if (kvm_enabled()) { 1590 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1591 1592 /* Check our RMA fits in the possible VRMA */ 1593 if (vrma_limit < spapr->rma_size) { 1594 error_report("Unable to create %" HWADDR_PRIu 1595 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1596 spapr->rma_size / MiB, vrma_limit / MiB); 1597 exit(EXIT_FAILURE); 1598 } 1599 } 1600 } 1601 1602 static int spapr_reset_drcs(Object *child, void *opaque) 1603 { 1604 SpaprDrc *drc = 1605 (SpaprDrc *) object_dynamic_cast(child, 1606 TYPE_SPAPR_DR_CONNECTOR); 1607 1608 if (drc) { 1609 spapr_drc_reset(drc); 1610 } 1611 1612 return 0; 1613 } 1614 1615 static void spapr_machine_reset(MachineState *machine) 1616 { 1617 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1618 PowerPCCPU *first_ppc_cpu; 1619 hwaddr fdt_addr; 1620 void *fdt; 1621 int rc; 1622 1623 kvmppc_svm_off(&error_fatal); 1624 spapr_caps_apply(spapr); 1625 1626 first_ppc_cpu = POWERPC_CPU(first_cpu); 1627 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1628 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1629 spapr->max_compat_pvr)) { 1630 /* 1631 * If using KVM with radix mode available, VCPUs can be started 1632 * without a HPT because KVM will start them in radix mode. 1633 * Set the GR bit in PATE so that we know there is no HPT. 1634 */ 1635 spapr->patb_entry = PATE1_GR; 1636 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1637 } else { 1638 spapr_setup_hpt(spapr); 1639 } 1640 1641 qemu_devices_reset(); 1642 1643 /* 1644 * If this reset wasn't generated by CAS, we should reset our 1645 * negotiated options and start from scratch 1646 */ 1647 if (!spapr->cas_reboot) { 1648 spapr_ovec_cleanup(spapr->ov5_cas); 1649 spapr->ov5_cas = spapr_ovec_new(); 1650 1651 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1652 } 1653 1654 /* 1655 * This is fixing some of the default configuration of the XIVE 1656 * devices. To be called after the reset of the machine devices. 1657 */ 1658 spapr_irq_reset(spapr, &error_fatal); 1659 1660 /* 1661 * There is no CAS under qtest. Simulate one to please the code that 1662 * depends on spapr->ov5_cas. This is especially needed to test device 1663 * unplug, so we do that before resetting the DRCs. 1664 */ 1665 if (qtest_enabled()) { 1666 spapr_ovec_cleanup(spapr->ov5_cas); 1667 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1668 } 1669 1670 /* DRC reset may cause a device to be unplugged. This will cause troubles 1671 * if this device is used by another device (eg, a running vhost backend 1672 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1673 * situations, we reset DRCs after all devices have been reset. 1674 */ 1675 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1676 1677 spapr_clear_pending_events(spapr); 1678 1679 /* 1680 * We place the device tree and RTAS just below either the top of the RMA, 1681 * or just below 2GB, whichever is lower, so that it can be 1682 * processed with 32-bit real mode code if necessary 1683 */ 1684 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1685 1686 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1687 1688 rc = fdt_pack(fdt); 1689 1690 /* Should only fail if we've built a corrupted tree */ 1691 assert(rc == 0); 1692 1693 /* Load the fdt */ 1694 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1695 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1696 g_free(spapr->fdt_blob); 1697 spapr->fdt_size = fdt_totalsize(fdt); 1698 spapr->fdt_initial_size = spapr->fdt_size; 1699 spapr->fdt_blob = fdt; 1700 1701 /* Set up the entry state */ 1702 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1703 first_ppc_cpu->env.gpr[5] = 0; 1704 1705 spapr->cas_reboot = false; 1706 1707 spapr->mc_status = -1; 1708 spapr->guest_machine_check_addr = -1; 1709 1710 /* Signal all vCPUs waiting on this condition */ 1711 qemu_cond_broadcast(&spapr->mc_delivery_cond); 1712 1713 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1714 } 1715 1716 static void spapr_create_nvram(SpaprMachineState *spapr) 1717 { 1718 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1719 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1720 1721 if (dinfo) { 1722 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1723 &error_fatal); 1724 } 1725 1726 qdev_init_nofail(dev); 1727 1728 spapr->nvram = (struct SpaprNvram *)dev; 1729 } 1730 1731 static void spapr_rtc_create(SpaprMachineState *spapr) 1732 { 1733 object_initialize_child(OBJECT(spapr), "rtc", 1734 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1735 &error_fatal, NULL); 1736 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1737 &error_fatal); 1738 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1739 "date", &error_fatal); 1740 } 1741 1742 /* Returns whether we want to use VGA or not */ 1743 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1744 { 1745 switch (vga_interface_type) { 1746 case VGA_NONE: 1747 return false; 1748 case VGA_DEVICE: 1749 return true; 1750 case VGA_STD: 1751 case VGA_VIRTIO: 1752 case VGA_CIRRUS: 1753 return pci_vga_init(pci_bus) != NULL; 1754 default: 1755 error_setg(errp, 1756 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1757 return false; 1758 } 1759 } 1760 1761 static int spapr_pre_load(void *opaque) 1762 { 1763 int rc; 1764 1765 rc = spapr_caps_pre_load(opaque); 1766 if (rc) { 1767 return rc; 1768 } 1769 1770 return 0; 1771 } 1772 1773 static int spapr_post_load(void *opaque, int version_id) 1774 { 1775 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1776 int err = 0; 1777 1778 err = spapr_caps_post_migration(spapr); 1779 if (err) { 1780 return err; 1781 } 1782 1783 /* 1784 * In earlier versions, there was no separate qdev for the PAPR 1785 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1786 * So when migrating from those versions, poke the incoming offset 1787 * value into the RTC device 1788 */ 1789 if (version_id < 3) { 1790 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1791 if (err) { 1792 return err; 1793 } 1794 } 1795 1796 if (kvm_enabled() && spapr->patb_entry) { 1797 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1798 bool radix = !!(spapr->patb_entry & PATE1_GR); 1799 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1800 1801 /* 1802 * Update LPCR:HR and UPRT as they may not be set properly in 1803 * the stream 1804 */ 1805 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1806 LPCR_HR | LPCR_UPRT); 1807 1808 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1809 if (err) { 1810 error_report("Process table config unsupported by the host"); 1811 return -EINVAL; 1812 } 1813 } 1814 1815 err = spapr_irq_post_load(spapr, version_id); 1816 if (err) { 1817 return err; 1818 } 1819 1820 return err; 1821 } 1822 1823 static int spapr_pre_save(void *opaque) 1824 { 1825 int rc; 1826 1827 rc = spapr_caps_pre_save(opaque); 1828 if (rc) { 1829 return rc; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static bool version_before_3(void *opaque, int version_id) 1836 { 1837 return version_id < 3; 1838 } 1839 1840 static bool spapr_pending_events_needed(void *opaque) 1841 { 1842 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1843 return !QTAILQ_EMPTY(&spapr->pending_events); 1844 } 1845 1846 static const VMStateDescription vmstate_spapr_event_entry = { 1847 .name = "spapr_event_log_entry", 1848 .version_id = 1, 1849 .minimum_version_id = 1, 1850 .fields = (VMStateField[]) { 1851 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1852 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1853 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1854 NULL, extended_length), 1855 VMSTATE_END_OF_LIST() 1856 }, 1857 }; 1858 1859 static const VMStateDescription vmstate_spapr_pending_events = { 1860 .name = "spapr_pending_events", 1861 .version_id = 1, 1862 .minimum_version_id = 1, 1863 .needed = spapr_pending_events_needed, 1864 .fields = (VMStateField[]) { 1865 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1866 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1867 VMSTATE_END_OF_LIST() 1868 }, 1869 }; 1870 1871 static bool spapr_ov5_cas_needed(void *opaque) 1872 { 1873 SpaprMachineState *spapr = opaque; 1874 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1875 bool cas_needed; 1876 1877 /* Prior to the introduction of SpaprOptionVector, we had two option 1878 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1879 * Both of these options encode machine topology into the device-tree 1880 * in such a way that the now-booted OS should still be able to interact 1881 * appropriately with QEMU regardless of what options were actually 1882 * negotiatied on the source side. 1883 * 1884 * As such, we can avoid migrating the CAS-negotiated options if these 1885 * are the only options available on the current machine/platform. 1886 * Since these are the only options available for pseries-2.7 and 1887 * earlier, this allows us to maintain old->new/new->old migration 1888 * compatibility. 1889 * 1890 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1891 * via default pseries-2.8 machines and explicit command-line parameters. 1892 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1893 * of the actual CAS-negotiated values to continue working properly. For 1894 * example, availability of memory unplug depends on knowing whether 1895 * OV5_HP_EVT was negotiated via CAS. 1896 * 1897 * Thus, for any cases where the set of available CAS-negotiatable 1898 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1899 * include the CAS-negotiated options in the migration stream, unless 1900 * if they affect boot time behaviour only. 1901 */ 1902 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1903 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1904 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1905 1906 /* We need extra information if we have any bits outside the mask 1907 * defined above */ 1908 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1909 1910 spapr_ovec_cleanup(ov5_mask); 1911 1912 return cas_needed; 1913 } 1914 1915 static const VMStateDescription vmstate_spapr_ov5_cas = { 1916 .name = "spapr_option_vector_ov5_cas", 1917 .version_id = 1, 1918 .minimum_version_id = 1, 1919 .needed = spapr_ov5_cas_needed, 1920 .fields = (VMStateField[]) { 1921 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1922 vmstate_spapr_ovec, SpaprOptionVector), 1923 VMSTATE_END_OF_LIST() 1924 }, 1925 }; 1926 1927 static bool spapr_patb_entry_needed(void *opaque) 1928 { 1929 SpaprMachineState *spapr = opaque; 1930 1931 return !!spapr->patb_entry; 1932 } 1933 1934 static const VMStateDescription vmstate_spapr_patb_entry = { 1935 .name = "spapr_patb_entry", 1936 .version_id = 1, 1937 .minimum_version_id = 1, 1938 .needed = spapr_patb_entry_needed, 1939 .fields = (VMStateField[]) { 1940 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1941 VMSTATE_END_OF_LIST() 1942 }, 1943 }; 1944 1945 static bool spapr_irq_map_needed(void *opaque) 1946 { 1947 SpaprMachineState *spapr = opaque; 1948 1949 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1950 } 1951 1952 static const VMStateDescription vmstate_spapr_irq_map = { 1953 .name = "spapr_irq_map", 1954 .version_id = 1, 1955 .minimum_version_id = 1, 1956 .needed = spapr_irq_map_needed, 1957 .fields = (VMStateField[]) { 1958 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1959 VMSTATE_END_OF_LIST() 1960 }, 1961 }; 1962 1963 static bool spapr_dtb_needed(void *opaque) 1964 { 1965 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1966 1967 return smc->update_dt_enabled; 1968 } 1969 1970 static int spapr_dtb_pre_load(void *opaque) 1971 { 1972 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1973 1974 g_free(spapr->fdt_blob); 1975 spapr->fdt_blob = NULL; 1976 spapr->fdt_size = 0; 1977 1978 return 0; 1979 } 1980 1981 static const VMStateDescription vmstate_spapr_dtb = { 1982 .name = "spapr_dtb", 1983 .version_id = 1, 1984 .minimum_version_id = 1, 1985 .needed = spapr_dtb_needed, 1986 .pre_load = spapr_dtb_pre_load, 1987 .fields = (VMStateField[]) { 1988 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1989 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1990 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1991 fdt_size), 1992 VMSTATE_END_OF_LIST() 1993 }, 1994 }; 1995 1996 static bool spapr_fwnmi_needed(void *opaque) 1997 { 1998 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1999 2000 return spapr->guest_machine_check_addr != -1; 2001 } 2002 2003 static int spapr_fwnmi_pre_save(void *opaque) 2004 { 2005 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2006 2007 /* 2008 * Check if machine check handling is in progress and print a 2009 * warning message. 2010 */ 2011 if (spapr->mc_status != -1) { 2012 warn_report("A machine check is being handled during migration. The" 2013 "handler may run and log hardware error on the destination"); 2014 } 2015 2016 return 0; 2017 } 2018 2019 static const VMStateDescription vmstate_spapr_machine_check = { 2020 .name = "spapr_machine_check", 2021 .version_id = 1, 2022 .minimum_version_id = 1, 2023 .needed = spapr_fwnmi_needed, 2024 .pre_save = spapr_fwnmi_pre_save, 2025 .fields = (VMStateField[]) { 2026 VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), 2027 VMSTATE_INT32(mc_status, SpaprMachineState), 2028 VMSTATE_END_OF_LIST() 2029 }, 2030 }; 2031 2032 static const VMStateDescription vmstate_spapr = { 2033 .name = "spapr", 2034 .version_id = 3, 2035 .minimum_version_id = 1, 2036 .pre_load = spapr_pre_load, 2037 .post_load = spapr_post_load, 2038 .pre_save = spapr_pre_save, 2039 .fields = (VMStateField[]) { 2040 /* used to be @next_irq */ 2041 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2042 2043 /* RTC offset */ 2044 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2045 2046 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2047 VMSTATE_END_OF_LIST() 2048 }, 2049 .subsections = (const VMStateDescription*[]) { 2050 &vmstate_spapr_ov5_cas, 2051 &vmstate_spapr_patb_entry, 2052 &vmstate_spapr_pending_events, 2053 &vmstate_spapr_cap_htm, 2054 &vmstate_spapr_cap_vsx, 2055 &vmstate_spapr_cap_dfp, 2056 &vmstate_spapr_cap_cfpc, 2057 &vmstate_spapr_cap_sbbc, 2058 &vmstate_spapr_cap_ibs, 2059 &vmstate_spapr_cap_hpt_maxpagesize, 2060 &vmstate_spapr_irq_map, 2061 &vmstate_spapr_cap_nested_kvm_hv, 2062 &vmstate_spapr_dtb, 2063 &vmstate_spapr_cap_large_decr, 2064 &vmstate_spapr_cap_ccf_assist, 2065 &vmstate_spapr_cap_fwnmi, 2066 &vmstate_spapr_machine_check, 2067 NULL 2068 } 2069 }; 2070 2071 static int htab_save_setup(QEMUFile *f, void *opaque) 2072 { 2073 SpaprMachineState *spapr = opaque; 2074 2075 /* "Iteration" header */ 2076 if (!spapr->htab_shift) { 2077 qemu_put_be32(f, -1); 2078 } else { 2079 qemu_put_be32(f, spapr->htab_shift); 2080 } 2081 2082 if (spapr->htab) { 2083 spapr->htab_save_index = 0; 2084 spapr->htab_first_pass = true; 2085 } else { 2086 if (spapr->htab_shift) { 2087 assert(kvm_enabled()); 2088 } 2089 } 2090 2091 2092 return 0; 2093 } 2094 2095 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2096 int chunkstart, int n_valid, int n_invalid) 2097 { 2098 qemu_put_be32(f, chunkstart); 2099 qemu_put_be16(f, n_valid); 2100 qemu_put_be16(f, n_invalid); 2101 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2102 HASH_PTE_SIZE_64 * n_valid); 2103 } 2104 2105 static void htab_save_end_marker(QEMUFile *f) 2106 { 2107 qemu_put_be32(f, 0); 2108 qemu_put_be16(f, 0); 2109 qemu_put_be16(f, 0); 2110 } 2111 2112 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2113 int64_t max_ns) 2114 { 2115 bool has_timeout = max_ns != -1; 2116 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2117 int index = spapr->htab_save_index; 2118 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2119 2120 assert(spapr->htab_first_pass); 2121 2122 do { 2123 int chunkstart; 2124 2125 /* Consume invalid HPTEs */ 2126 while ((index < htabslots) 2127 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2128 CLEAN_HPTE(HPTE(spapr->htab, index)); 2129 index++; 2130 } 2131 2132 /* Consume valid HPTEs */ 2133 chunkstart = index; 2134 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2135 && HPTE_VALID(HPTE(spapr->htab, index))) { 2136 CLEAN_HPTE(HPTE(spapr->htab, index)); 2137 index++; 2138 } 2139 2140 if (index > chunkstart) { 2141 int n_valid = index - chunkstart; 2142 2143 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2144 2145 if (has_timeout && 2146 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2147 break; 2148 } 2149 } 2150 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2151 2152 if (index >= htabslots) { 2153 assert(index == htabslots); 2154 index = 0; 2155 spapr->htab_first_pass = false; 2156 } 2157 spapr->htab_save_index = index; 2158 } 2159 2160 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2161 int64_t max_ns) 2162 { 2163 bool final = max_ns < 0; 2164 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2165 int examined = 0, sent = 0; 2166 int index = spapr->htab_save_index; 2167 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2168 2169 assert(!spapr->htab_first_pass); 2170 2171 do { 2172 int chunkstart, invalidstart; 2173 2174 /* Consume non-dirty HPTEs */ 2175 while ((index < htabslots) 2176 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2177 index++; 2178 examined++; 2179 } 2180 2181 chunkstart = index; 2182 /* Consume valid dirty HPTEs */ 2183 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2184 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2185 && HPTE_VALID(HPTE(spapr->htab, index))) { 2186 CLEAN_HPTE(HPTE(spapr->htab, index)); 2187 index++; 2188 examined++; 2189 } 2190 2191 invalidstart = index; 2192 /* Consume invalid dirty HPTEs */ 2193 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2194 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2195 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2196 CLEAN_HPTE(HPTE(spapr->htab, index)); 2197 index++; 2198 examined++; 2199 } 2200 2201 if (index > chunkstart) { 2202 int n_valid = invalidstart - chunkstart; 2203 int n_invalid = index - invalidstart; 2204 2205 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2206 sent += index - chunkstart; 2207 2208 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2209 break; 2210 } 2211 } 2212 2213 if (examined >= htabslots) { 2214 break; 2215 } 2216 2217 if (index >= htabslots) { 2218 assert(index == htabslots); 2219 index = 0; 2220 } 2221 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2222 2223 if (index >= htabslots) { 2224 assert(index == htabslots); 2225 index = 0; 2226 } 2227 2228 spapr->htab_save_index = index; 2229 2230 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2231 } 2232 2233 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2234 #define MAX_KVM_BUF_SIZE 2048 2235 2236 static int htab_save_iterate(QEMUFile *f, void *opaque) 2237 { 2238 SpaprMachineState *spapr = opaque; 2239 int fd; 2240 int rc = 0; 2241 2242 /* Iteration header */ 2243 if (!spapr->htab_shift) { 2244 qemu_put_be32(f, -1); 2245 return 1; 2246 } else { 2247 qemu_put_be32(f, 0); 2248 } 2249 2250 if (!spapr->htab) { 2251 assert(kvm_enabled()); 2252 2253 fd = get_htab_fd(spapr); 2254 if (fd < 0) { 2255 return fd; 2256 } 2257 2258 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2259 if (rc < 0) { 2260 return rc; 2261 } 2262 } else if (spapr->htab_first_pass) { 2263 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2264 } else { 2265 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2266 } 2267 2268 htab_save_end_marker(f); 2269 2270 return rc; 2271 } 2272 2273 static int htab_save_complete(QEMUFile *f, void *opaque) 2274 { 2275 SpaprMachineState *spapr = opaque; 2276 int fd; 2277 2278 /* Iteration header */ 2279 if (!spapr->htab_shift) { 2280 qemu_put_be32(f, -1); 2281 return 0; 2282 } else { 2283 qemu_put_be32(f, 0); 2284 } 2285 2286 if (!spapr->htab) { 2287 int rc; 2288 2289 assert(kvm_enabled()); 2290 2291 fd = get_htab_fd(spapr); 2292 if (fd < 0) { 2293 return fd; 2294 } 2295 2296 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2297 if (rc < 0) { 2298 return rc; 2299 } 2300 } else { 2301 if (spapr->htab_first_pass) { 2302 htab_save_first_pass(f, spapr, -1); 2303 } 2304 htab_save_later_pass(f, spapr, -1); 2305 } 2306 2307 /* End marker */ 2308 htab_save_end_marker(f); 2309 2310 return 0; 2311 } 2312 2313 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2314 { 2315 SpaprMachineState *spapr = opaque; 2316 uint32_t section_hdr; 2317 int fd = -1; 2318 Error *local_err = NULL; 2319 2320 if (version_id < 1 || version_id > 1) { 2321 error_report("htab_load() bad version"); 2322 return -EINVAL; 2323 } 2324 2325 section_hdr = qemu_get_be32(f); 2326 2327 if (section_hdr == -1) { 2328 spapr_free_hpt(spapr); 2329 return 0; 2330 } 2331 2332 if (section_hdr) { 2333 /* First section gives the htab size */ 2334 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2335 if (local_err) { 2336 error_report_err(local_err); 2337 return -EINVAL; 2338 } 2339 return 0; 2340 } 2341 2342 if (!spapr->htab) { 2343 assert(kvm_enabled()); 2344 2345 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2346 if (fd < 0) { 2347 error_report_err(local_err); 2348 return fd; 2349 } 2350 } 2351 2352 while (true) { 2353 uint32_t index; 2354 uint16_t n_valid, n_invalid; 2355 2356 index = qemu_get_be32(f); 2357 n_valid = qemu_get_be16(f); 2358 n_invalid = qemu_get_be16(f); 2359 2360 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2361 /* End of Stream */ 2362 break; 2363 } 2364 2365 if ((index + n_valid + n_invalid) > 2366 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2367 /* Bad index in stream */ 2368 error_report( 2369 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2370 index, n_valid, n_invalid, spapr->htab_shift); 2371 return -EINVAL; 2372 } 2373 2374 if (spapr->htab) { 2375 if (n_valid) { 2376 qemu_get_buffer(f, HPTE(spapr->htab, index), 2377 HASH_PTE_SIZE_64 * n_valid); 2378 } 2379 if (n_invalid) { 2380 memset(HPTE(spapr->htab, index + n_valid), 0, 2381 HASH_PTE_SIZE_64 * n_invalid); 2382 } 2383 } else { 2384 int rc; 2385 2386 assert(fd >= 0); 2387 2388 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2389 if (rc < 0) { 2390 return rc; 2391 } 2392 } 2393 } 2394 2395 if (!spapr->htab) { 2396 assert(fd >= 0); 2397 close(fd); 2398 } 2399 2400 return 0; 2401 } 2402 2403 static void htab_save_cleanup(void *opaque) 2404 { 2405 SpaprMachineState *spapr = opaque; 2406 2407 close_htab_fd(spapr); 2408 } 2409 2410 static SaveVMHandlers savevm_htab_handlers = { 2411 .save_setup = htab_save_setup, 2412 .save_live_iterate = htab_save_iterate, 2413 .save_live_complete_precopy = htab_save_complete, 2414 .save_cleanup = htab_save_cleanup, 2415 .load_state = htab_load, 2416 }; 2417 2418 static void spapr_boot_set(void *opaque, const char *boot_device, 2419 Error **errp) 2420 { 2421 MachineState *machine = MACHINE(opaque); 2422 machine->boot_order = g_strdup(boot_device); 2423 } 2424 2425 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2426 { 2427 MachineState *machine = MACHINE(spapr); 2428 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2429 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2430 int i; 2431 2432 for (i = 0; i < nr_lmbs; i++) { 2433 uint64_t addr; 2434 2435 addr = i * lmb_size + machine->device_memory->base; 2436 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2437 addr / lmb_size); 2438 } 2439 } 2440 2441 /* 2442 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2443 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2444 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2445 */ 2446 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2447 { 2448 int i; 2449 2450 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2451 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2452 " is not aligned to %" PRIu64 " MiB", 2453 machine->ram_size, 2454 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2455 return; 2456 } 2457 2458 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2459 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2460 " is not aligned to %" PRIu64 " MiB", 2461 machine->ram_size, 2462 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2463 return; 2464 } 2465 2466 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2467 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2468 error_setg(errp, 2469 "Node %d memory size 0x%" PRIx64 2470 " is not aligned to %" PRIu64 " MiB", 2471 i, machine->numa_state->nodes[i].node_mem, 2472 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2473 return; 2474 } 2475 } 2476 } 2477 2478 /* find cpu slot in machine->possible_cpus by core_id */ 2479 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2480 { 2481 int index = id / ms->smp.threads; 2482 2483 if (index >= ms->possible_cpus->len) { 2484 return NULL; 2485 } 2486 if (idx) { 2487 *idx = index; 2488 } 2489 return &ms->possible_cpus->cpus[index]; 2490 } 2491 2492 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2493 { 2494 MachineState *ms = MACHINE(spapr); 2495 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2496 Error *local_err = NULL; 2497 bool vsmt_user = !!spapr->vsmt; 2498 int kvm_smt = kvmppc_smt_threads(); 2499 int ret; 2500 unsigned int smp_threads = ms->smp.threads; 2501 2502 if (!kvm_enabled() && (smp_threads > 1)) { 2503 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2504 "on a pseries machine"); 2505 goto out; 2506 } 2507 if (!is_power_of_2(smp_threads)) { 2508 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2509 "machine because it must be a power of 2", smp_threads); 2510 goto out; 2511 } 2512 2513 /* Detemine the VSMT mode to use: */ 2514 if (vsmt_user) { 2515 if (spapr->vsmt < smp_threads) { 2516 error_setg(&local_err, "Cannot support VSMT mode %d" 2517 " because it must be >= threads/core (%d)", 2518 spapr->vsmt, smp_threads); 2519 goto out; 2520 } 2521 /* In this case, spapr->vsmt has been set by the command line */ 2522 } else if (!smc->smp_threads_vsmt) { 2523 /* 2524 * Default VSMT value is tricky, because we need it to be as 2525 * consistent as possible (for migration), but this requires 2526 * changing it for at least some existing cases. We pick 8 as 2527 * the value that we'd get with KVM on POWER8, the 2528 * overwhelmingly common case in production systems. 2529 */ 2530 spapr->vsmt = MAX(8, smp_threads); 2531 } else { 2532 spapr->vsmt = smp_threads; 2533 } 2534 2535 /* KVM: If necessary, set the SMT mode: */ 2536 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2537 ret = kvmppc_set_smt_threads(spapr->vsmt); 2538 if (ret) { 2539 /* Looks like KVM isn't able to change VSMT mode */ 2540 error_setg(&local_err, 2541 "Failed to set KVM's VSMT mode to %d (errno %d)", 2542 spapr->vsmt, ret); 2543 /* We can live with that if the default one is big enough 2544 * for the number of threads, and a submultiple of the one 2545 * we want. In this case we'll waste some vcpu ids, but 2546 * behaviour will be correct */ 2547 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2548 warn_report_err(local_err); 2549 local_err = NULL; 2550 goto out; 2551 } else { 2552 if (!vsmt_user) { 2553 error_append_hint(&local_err, 2554 "On PPC, a VM with %d threads/core" 2555 " on a host with %d threads/core" 2556 " requires the use of VSMT mode %d.\n", 2557 smp_threads, kvm_smt, spapr->vsmt); 2558 } 2559 kvmppc_error_append_smt_possible_hint(&local_err); 2560 goto out; 2561 } 2562 } 2563 } 2564 /* else TCG: nothing to do currently */ 2565 out: 2566 error_propagate(errp, local_err); 2567 } 2568 2569 static void spapr_init_cpus(SpaprMachineState *spapr) 2570 { 2571 MachineState *machine = MACHINE(spapr); 2572 MachineClass *mc = MACHINE_GET_CLASS(machine); 2573 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2574 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2575 const CPUArchIdList *possible_cpus; 2576 unsigned int smp_cpus = machine->smp.cpus; 2577 unsigned int smp_threads = machine->smp.threads; 2578 unsigned int max_cpus = machine->smp.max_cpus; 2579 int boot_cores_nr = smp_cpus / smp_threads; 2580 int i; 2581 2582 possible_cpus = mc->possible_cpu_arch_ids(machine); 2583 if (mc->has_hotpluggable_cpus) { 2584 if (smp_cpus % smp_threads) { 2585 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2586 smp_cpus, smp_threads); 2587 exit(1); 2588 } 2589 if (max_cpus % smp_threads) { 2590 error_report("max_cpus (%u) must be multiple of threads (%u)", 2591 max_cpus, smp_threads); 2592 exit(1); 2593 } 2594 } else { 2595 if (max_cpus != smp_cpus) { 2596 error_report("This machine version does not support CPU hotplug"); 2597 exit(1); 2598 } 2599 boot_cores_nr = possible_cpus->len; 2600 } 2601 2602 if (smc->pre_2_10_has_unused_icps) { 2603 int i; 2604 2605 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2606 /* Dummy entries get deregistered when real ICPState objects 2607 * are registered during CPU core hotplug. 2608 */ 2609 pre_2_10_vmstate_register_dummy_icp(i); 2610 } 2611 } 2612 2613 for (i = 0; i < possible_cpus->len; i++) { 2614 int core_id = i * smp_threads; 2615 2616 if (mc->has_hotpluggable_cpus) { 2617 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2618 spapr_vcpu_id(spapr, core_id)); 2619 } 2620 2621 if (i < boot_cores_nr) { 2622 Object *core = object_new(type); 2623 int nr_threads = smp_threads; 2624 2625 /* Handle the partially filled core for older machine types */ 2626 if ((i + 1) * smp_threads >= smp_cpus) { 2627 nr_threads = smp_cpus - i * smp_threads; 2628 } 2629 2630 object_property_set_int(core, nr_threads, "nr-threads", 2631 &error_fatal); 2632 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2633 &error_fatal); 2634 object_property_set_bool(core, true, "realized", &error_fatal); 2635 2636 object_unref(core); 2637 } 2638 } 2639 } 2640 2641 static PCIHostState *spapr_create_default_phb(void) 2642 { 2643 DeviceState *dev; 2644 2645 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2646 qdev_prop_set_uint32(dev, "index", 0); 2647 qdev_init_nofail(dev); 2648 2649 return PCI_HOST_BRIDGE(dev); 2650 } 2651 2652 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2653 { 2654 MachineState *machine = MACHINE(spapr); 2655 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2656 hwaddr rma_size = machine->ram_size; 2657 hwaddr node0_size = spapr_node0_size(machine); 2658 2659 /* RMA has to fit in the first NUMA node */ 2660 rma_size = MIN(rma_size, node0_size); 2661 2662 /* 2663 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2664 * never exceed that 2665 */ 2666 rma_size = MIN(rma_size, 1 * TiB); 2667 2668 /* 2669 * Clamp the RMA size based on machine type. This is for 2670 * migration compatibility with older qemu versions, which limited 2671 * the RMA size for complicated and mostly bad reasons. 2672 */ 2673 if (smc->rma_limit) { 2674 rma_size = MIN(rma_size, smc->rma_limit); 2675 } 2676 2677 if (rma_size < MIN_RMA_SLOF) { 2678 error_setg(errp, 2679 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2680 "ldMiB guest RMA (Real Mode Area memory)", 2681 MIN_RMA_SLOF / MiB); 2682 return 0; 2683 } 2684 2685 return rma_size; 2686 } 2687 2688 /* pSeries LPAR / sPAPR hardware init */ 2689 static void spapr_machine_init(MachineState *machine) 2690 { 2691 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2692 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2693 MachineClass *mc = MACHINE_GET_CLASS(machine); 2694 const char *kernel_filename = machine->kernel_filename; 2695 const char *initrd_filename = machine->initrd_filename; 2696 PCIHostState *phb; 2697 int i; 2698 MemoryRegion *sysmem = get_system_memory(); 2699 long load_limit, fw_size; 2700 char *filename; 2701 Error *resize_hpt_err = NULL; 2702 2703 msi_nonbroken = true; 2704 2705 QLIST_INIT(&spapr->phbs); 2706 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2707 2708 /* Determine capabilities to run with */ 2709 spapr_caps_init(spapr); 2710 2711 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2712 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2713 /* 2714 * If the user explicitly requested a mode we should either 2715 * supply it, or fail completely (which we do below). But if 2716 * it's not set explicitly, we reset our mode to something 2717 * that works 2718 */ 2719 if (resize_hpt_err) { 2720 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2721 error_free(resize_hpt_err); 2722 resize_hpt_err = NULL; 2723 } else { 2724 spapr->resize_hpt = smc->resize_hpt_default; 2725 } 2726 } 2727 2728 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2729 2730 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2731 /* 2732 * User requested HPT resize, but this host can't supply it. Bail out 2733 */ 2734 error_report_err(resize_hpt_err); 2735 exit(1); 2736 } 2737 2738 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2739 2740 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2741 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2742 2743 /* 2744 * VSMT must be set in order to be able to compute VCPU ids, ie to 2745 * call spapr_max_server_number() or spapr_vcpu_id(). 2746 */ 2747 spapr_set_vsmt_mode(spapr, &error_fatal); 2748 2749 /* Set up Interrupt Controller before we create the VCPUs */ 2750 spapr_irq_init(spapr, &error_fatal); 2751 2752 /* Set up containers for ibm,client-architecture-support negotiated options 2753 */ 2754 spapr->ov5 = spapr_ovec_new(); 2755 spapr->ov5_cas = spapr_ovec_new(); 2756 2757 if (smc->dr_lmb_enabled) { 2758 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2759 spapr_validate_node_memory(machine, &error_fatal); 2760 } 2761 2762 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2763 2764 /* advertise support for dedicated HP event source to guests */ 2765 if (spapr->use_hotplug_event_source) { 2766 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2767 } 2768 2769 /* advertise support for HPT resizing */ 2770 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2771 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2772 } 2773 2774 /* advertise support for ibm,dyamic-memory-v2 */ 2775 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2776 2777 /* advertise XIVE on POWER9 machines */ 2778 if (spapr->irq->xive) { 2779 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2780 } 2781 2782 /* init CPUs */ 2783 spapr_init_cpus(spapr); 2784 2785 /* 2786 * check we don't have a memory-less/cpu-less NUMA node 2787 * Firmware relies on the existing memory/cpu topology to provide the 2788 * NUMA topology to the kernel. 2789 * And the linux kernel needs to know the NUMA topology at start 2790 * to be able to hotplug CPUs later. 2791 */ 2792 if (machine->numa_state->num_nodes) { 2793 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2794 /* check for memory-less node */ 2795 if (machine->numa_state->nodes[i].node_mem == 0) { 2796 CPUState *cs; 2797 int found = 0; 2798 /* check for cpu-less node */ 2799 CPU_FOREACH(cs) { 2800 PowerPCCPU *cpu = POWERPC_CPU(cs); 2801 if (cpu->node_id == i) { 2802 found = 1; 2803 break; 2804 } 2805 } 2806 /* memory-less and cpu-less node */ 2807 if (!found) { 2808 error_report( 2809 "Memory-less/cpu-less nodes are not supported (node %d)", 2810 i); 2811 exit(1); 2812 } 2813 } 2814 } 2815 2816 } 2817 2818 /* 2819 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2820 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2821 * called from vPHB reset handler so we initialize the counter here. 2822 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2823 * must be equally distant from any other node. 2824 * The final value of spapr->gpu_numa_id is going to be written to 2825 * max-associativity-domains in spapr_build_fdt(). 2826 */ 2827 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2828 2829 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2830 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2831 spapr->max_compat_pvr)) { 2832 /* KVM and TCG always allow GTSE with radix... */ 2833 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2834 } 2835 /* ... but not with hash (currently). */ 2836 2837 if (kvm_enabled()) { 2838 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2839 kvmppc_enable_logical_ci_hcalls(); 2840 kvmppc_enable_set_mode_hcall(); 2841 2842 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2843 kvmppc_enable_clear_ref_mod_hcalls(); 2844 2845 /* Enable H_PAGE_INIT */ 2846 kvmppc_enable_h_page_init(); 2847 } 2848 2849 /* map RAM */ 2850 memory_region_add_subregion(sysmem, 0, machine->ram); 2851 2852 /* always allocate the device memory information */ 2853 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2854 2855 /* initialize hotplug memory address space */ 2856 if (machine->ram_size < machine->maxram_size) { 2857 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2858 /* 2859 * Limit the number of hotpluggable memory slots to half the number 2860 * slots that KVM supports, leaving the other half for PCI and other 2861 * devices. However ensure that number of slots doesn't drop below 32. 2862 */ 2863 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2864 SPAPR_MAX_RAM_SLOTS; 2865 2866 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2867 max_memslots = SPAPR_MAX_RAM_SLOTS; 2868 } 2869 if (machine->ram_slots > max_memslots) { 2870 error_report("Specified number of memory slots %" 2871 PRIu64" exceeds max supported %d", 2872 machine->ram_slots, max_memslots); 2873 exit(1); 2874 } 2875 2876 machine->device_memory->base = ROUND_UP(machine->ram_size, 2877 SPAPR_DEVICE_MEM_ALIGN); 2878 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2879 "device-memory", device_mem_size); 2880 memory_region_add_subregion(sysmem, machine->device_memory->base, 2881 &machine->device_memory->mr); 2882 } 2883 2884 if (smc->dr_lmb_enabled) { 2885 spapr_create_lmb_dr_connectors(spapr); 2886 } 2887 2888 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) { 2889 /* Create the error string for live migration blocker */ 2890 error_setg(&spapr->fwnmi_migration_blocker, 2891 "A machine check is being handled during migration. The handler" 2892 "may run and log hardware error on the destination"); 2893 } 2894 2895 if (mc->nvdimm_supported) { 2896 spapr_create_nvdimm_dr_connectors(spapr); 2897 } 2898 2899 /* Set up RTAS event infrastructure */ 2900 spapr_events_init(spapr); 2901 2902 /* Set up the RTC RTAS interfaces */ 2903 spapr_rtc_create(spapr); 2904 2905 /* Set up VIO bus */ 2906 spapr->vio_bus = spapr_vio_bus_init(); 2907 2908 for (i = 0; i < serial_max_hds(); i++) { 2909 if (serial_hd(i)) { 2910 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2911 } 2912 } 2913 2914 /* We always have at least the nvram device on VIO */ 2915 spapr_create_nvram(spapr); 2916 2917 /* 2918 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2919 * connectors (described in root DT node's "ibm,drc-types" property) 2920 * are pre-initialized here. additional child connectors (such as 2921 * connectors for a PHBs PCI slots) are added as needed during their 2922 * parent's realization. 2923 */ 2924 if (smc->dr_phb_enabled) { 2925 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2926 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2927 } 2928 } 2929 2930 /* Set up PCI */ 2931 spapr_pci_rtas_init(); 2932 2933 phb = spapr_create_default_phb(); 2934 2935 for (i = 0; i < nb_nics; i++) { 2936 NICInfo *nd = &nd_table[i]; 2937 2938 if (!nd->model) { 2939 nd->model = g_strdup("spapr-vlan"); 2940 } 2941 2942 if (g_str_equal(nd->model, "spapr-vlan") || 2943 g_str_equal(nd->model, "ibmveth")) { 2944 spapr_vlan_create(spapr->vio_bus, nd); 2945 } else { 2946 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2947 } 2948 } 2949 2950 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2951 spapr_vscsi_create(spapr->vio_bus); 2952 } 2953 2954 /* Graphics */ 2955 if (spapr_vga_init(phb->bus, &error_fatal)) { 2956 spapr->has_graphics = true; 2957 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2958 } 2959 2960 if (machine->usb) { 2961 if (smc->use_ohci_by_default) { 2962 pci_create_simple(phb->bus, -1, "pci-ohci"); 2963 } else { 2964 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2965 } 2966 2967 if (spapr->has_graphics) { 2968 USBBus *usb_bus = usb_bus_find(-1); 2969 2970 usb_create_simple(usb_bus, "usb-kbd"); 2971 usb_create_simple(usb_bus, "usb-mouse"); 2972 } 2973 } 2974 2975 if (kernel_filename) { 2976 uint64_t lowaddr = 0; 2977 2978 spapr->kernel_size = load_elf(kernel_filename, NULL, 2979 translate_kernel_address, spapr, 2980 NULL, &lowaddr, NULL, NULL, 1, 2981 PPC_ELF_MACHINE, 0, 0); 2982 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2983 spapr->kernel_size = load_elf(kernel_filename, NULL, 2984 translate_kernel_address, spapr, NULL, 2985 &lowaddr, NULL, NULL, 0, 2986 PPC_ELF_MACHINE, 2987 0, 0); 2988 spapr->kernel_le = spapr->kernel_size > 0; 2989 } 2990 if (spapr->kernel_size < 0) { 2991 error_report("error loading %s: %s", kernel_filename, 2992 load_elf_strerror(spapr->kernel_size)); 2993 exit(1); 2994 } 2995 2996 /* load initrd */ 2997 if (initrd_filename) { 2998 /* Try to locate the initrd in the gap between the kernel 2999 * and the firmware. Add a bit of space just in case 3000 */ 3001 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3002 + 0x1ffff) & ~0xffff; 3003 spapr->initrd_size = load_image_targphys(initrd_filename, 3004 spapr->initrd_base, 3005 load_limit 3006 - spapr->initrd_base); 3007 if (spapr->initrd_size < 0) { 3008 error_report("could not load initial ram disk '%s'", 3009 initrd_filename); 3010 exit(1); 3011 } 3012 } 3013 } 3014 3015 if (bios_name == NULL) { 3016 bios_name = FW_FILE_NAME; 3017 } 3018 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3019 if (!filename) { 3020 error_report("Could not find LPAR firmware '%s'", bios_name); 3021 exit(1); 3022 } 3023 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3024 if (fw_size <= 0) { 3025 error_report("Could not load LPAR firmware '%s'", filename); 3026 exit(1); 3027 } 3028 g_free(filename); 3029 3030 /* FIXME: Should register things through the MachineState's qdev 3031 * interface, this is a legacy from the sPAPREnvironment structure 3032 * which predated MachineState but had a similar function */ 3033 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3034 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3035 &savevm_htab_handlers, spapr); 3036 3037 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3038 &error_fatal); 3039 3040 qemu_register_boot_set(spapr_boot_set, spapr); 3041 3042 /* 3043 * Nothing needs to be done to resume a suspended guest because 3044 * suspending does not change the machine state, so no need for 3045 * a ->wakeup method. 3046 */ 3047 qemu_register_wakeup_support(); 3048 3049 if (kvm_enabled()) { 3050 /* to stop and start vmclock */ 3051 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3052 &spapr->tb); 3053 3054 kvmppc_spapr_enable_inkernel_multitce(); 3055 } 3056 3057 qemu_cond_init(&spapr->mc_delivery_cond); 3058 } 3059 3060 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3061 { 3062 if (!vm_type) { 3063 return 0; 3064 } 3065 3066 if (!strcmp(vm_type, "HV")) { 3067 return 1; 3068 } 3069 3070 if (!strcmp(vm_type, "PR")) { 3071 return 2; 3072 } 3073 3074 error_report("Unknown kvm-type specified '%s'", vm_type); 3075 exit(1); 3076 } 3077 3078 /* 3079 * Implementation of an interface to adjust firmware path 3080 * for the bootindex property handling. 3081 */ 3082 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3083 DeviceState *dev) 3084 { 3085 #define CAST(type, obj, name) \ 3086 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3087 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3088 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3089 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3090 3091 if (d) { 3092 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3093 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3094 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3095 3096 if (spapr) { 3097 /* 3098 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3099 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3100 * 0x8000 | (target << 8) | (bus << 5) | lun 3101 * (see the "Logical unit addressing format" table in SAM5) 3102 */ 3103 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3104 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3105 (uint64_t)id << 48); 3106 } else if (virtio) { 3107 /* 3108 * We use SRP luns of the form 01000000 | (target << 8) | lun 3109 * in the top 32 bits of the 64-bit LUN 3110 * Note: the quote above is from SLOF and it is wrong, 3111 * the actual binding is: 3112 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3113 */ 3114 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3115 if (d->lun >= 256) { 3116 /* Use the LUN "flat space addressing method" */ 3117 id |= 0x4000; 3118 } 3119 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3120 (uint64_t)id << 32); 3121 } else if (usb) { 3122 /* 3123 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3124 * in the top 32 bits of the 64-bit LUN 3125 */ 3126 unsigned usb_port = atoi(usb->port->path); 3127 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3128 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3129 (uint64_t)id << 32); 3130 } 3131 } 3132 3133 /* 3134 * SLOF probes the USB devices, and if it recognizes that the device is a 3135 * storage device, it changes its name to "storage" instead of "usb-host", 3136 * and additionally adds a child node for the SCSI LUN, so the correct 3137 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3138 */ 3139 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3140 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3141 if (usb_host_dev_is_scsi_storage(usbdev)) { 3142 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3143 } 3144 } 3145 3146 if (phb) { 3147 /* Replace "pci" with "pci@800000020000000" */ 3148 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3149 } 3150 3151 if (vsc) { 3152 /* Same logic as virtio above */ 3153 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3154 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3155 } 3156 3157 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3158 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3159 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3160 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3161 } 3162 3163 return NULL; 3164 } 3165 3166 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3167 { 3168 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3169 3170 return g_strdup(spapr->kvm_type); 3171 } 3172 3173 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3174 { 3175 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 g_free(spapr->kvm_type); 3178 spapr->kvm_type = g_strdup(value); 3179 } 3180 3181 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3182 { 3183 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3184 3185 return spapr->use_hotplug_event_source; 3186 } 3187 3188 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3189 Error **errp) 3190 { 3191 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3192 3193 spapr->use_hotplug_event_source = value; 3194 } 3195 3196 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3197 { 3198 return true; 3199 } 3200 3201 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3202 { 3203 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3204 3205 switch (spapr->resize_hpt) { 3206 case SPAPR_RESIZE_HPT_DEFAULT: 3207 return g_strdup("default"); 3208 case SPAPR_RESIZE_HPT_DISABLED: 3209 return g_strdup("disabled"); 3210 case SPAPR_RESIZE_HPT_ENABLED: 3211 return g_strdup("enabled"); 3212 case SPAPR_RESIZE_HPT_REQUIRED: 3213 return g_strdup("required"); 3214 } 3215 g_assert_not_reached(); 3216 } 3217 3218 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3219 { 3220 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3221 3222 if (strcmp(value, "default") == 0) { 3223 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3224 } else if (strcmp(value, "disabled") == 0) { 3225 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3226 } else if (strcmp(value, "enabled") == 0) { 3227 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3228 } else if (strcmp(value, "required") == 0) { 3229 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3230 } else { 3231 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3232 } 3233 } 3234 3235 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3236 void *opaque, Error **errp) 3237 { 3238 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3239 } 3240 3241 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3242 void *opaque, Error **errp) 3243 { 3244 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3245 } 3246 3247 static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name, 3248 void *opaque, Error **errp) 3249 { 3250 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3251 } 3252 3253 static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name, 3254 void *opaque, Error **errp) 3255 { 3256 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3257 } 3258 3259 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3260 { 3261 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3262 3263 if (spapr->irq == &spapr_irq_xics_legacy) { 3264 return g_strdup("legacy"); 3265 } else if (spapr->irq == &spapr_irq_xics) { 3266 return g_strdup("xics"); 3267 } else if (spapr->irq == &spapr_irq_xive) { 3268 return g_strdup("xive"); 3269 } else if (spapr->irq == &spapr_irq_dual) { 3270 return g_strdup("dual"); 3271 } 3272 g_assert_not_reached(); 3273 } 3274 3275 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3276 { 3277 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3278 3279 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3280 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3281 return; 3282 } 3283 3284 /* The legacy IRQ backend can not be set */ 3285 if (strcmp(value, "xics") == 0) { 3286 spapr->irq = &spapr_irq_xics; 3287 } else if (strcmp(value, "xive") == 0) { 3288 spapr->irq = &spapr_irq_xive; 3289 } else if (strcmp(value, "dual") == 0) { 3290 spapr->irq = &spapr_irq_dual; 3291 } else { 3292 error_setg(errp, "Bad value for \"ic-mode\" property"); 3293 } 3294 } 3295 3296 static char *spapr_get_host_model(Object *obj, Error **errp) 3297 { 3298 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3299 3300 return g_strdup(spapr->host_model); 3301 } 3302 3303 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3304 { 3305 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3306 3307 g_free(spapr->host_model); 3308 spapr->host_model = g_strdup(value); 3309 } 3310 3311 static char *spapr_get_host_serial(Object *obj, Error **errp) 3312 { 3313 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3314 3315 return g_strdup(spapr->host_serial); 3316 } 3317 3318 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3319 { 3320 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3321 3322 g_free(spapr->host_serial); 3323 spapr->host_serial = g_strdup(value); 3324 } 3325 3326 static void spapr_instance_init(Object *obj) 3327 { 3328 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3329 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3330 3331 spapr->htab_fd = -1; 3332 spapr->use_hotplug_event_source = true; 3333 object_property_add_str(obj, "kvm-type", 3334 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3335 object_property_set_description(obj, "kvm-type", 3336 "Specifies the KVM virtualization mode (HV, PR)", 3337 NULL); 3338 object_property_add_bool(obj, "modern-hotplug-events", 3339 spapr_get_modern_hotplug_events, 3340 spapr_set_modern_hotplug_events, 3341 NULL); 3342 object_property_set_description(obj, "modern-hotplug-events", 3343 "Use dedicated hotplug event mechanism in" 3344 " place of standard EPOW events when possible" 3345 " (required for memory hot-unplug support)", 3346 NULL); 3347 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3348 "Maximum permitted CPU compatibility mode", 3349 &error_fatal); 3350 3351 object_property_add_str(obj, "resize-hpt", 3352 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3353 object_property_set_description(obj, "resize-hpt", 3354 "Resizing of the Hash Page Table (enabled, disabled, required)", 3355 NULL); 3356 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3357 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3358 object_property_set_description(obj, "vsmt", 3359 "Virtual SMT: KVM behaves as if this were" 3360 " the host's SMT mode", &error_abort); 3361 object_property_add_bool(obj, "vfio-no-msix-emulation", 3362 spapr_get_msix_emulation, NULL, NULL); 3363 3364 object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr, 3365 spapr_set_kernel_addr, NULL, &spapr->kernel_addr, 3366 &error_abort); 3367 object_property_set_description(obj, "kernel-addr", 3368 stringify(KERNEL_LOAD_ADDR) 3369 " for -kernel is the default", 3370 NULL); 3371 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3372 /* The machine class defines the default interrupt controller mode */ 3373 spapr->irq = smc->irq; 3374 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3375 spapr_set_ic_mode, NULL); 3376 object_property_set_description(obj, "ic-mode", 3377 "Specifies the interrupt controller mode (xics, xive, dual)", 3378 NULL); 3379 3380 object_property_add_str(obj, "host-model", 3381 spapr_get_host_model, spapr_set_host_model, 3382 &error_abort); 3383 object_property_set_description(obj, "host-model", 3384 "Host model to advertise in guest device tree", &error_abort); 3385 object_property_add_str(obj, "host-serial", 3386 spapr_get_host_serial, spapr_set_host_serial, 3387 &error_abort); 3388 object_property_set_description(obj, "host-serial", 3389 "Host serial number to advertise in guest device tree", &error_abort); 3390 } 3391 3392 static void spapr_machine_finalizefn(Object *obj) 3393 { 3394 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3395 3396 g_free(spapr->kvm_type); 3397 } 3398 3399 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3400 { 3401 cpu_synchronize_state(cs); 3402 ppc_cpu_do_system_reset(cs); 3403 } 3404 3405 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3406 { 3407 CPUState *cs; 3408 3409 CPU_FOREACH(cs) { 3410 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3411 } 3412 } 3413 3414 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3415 void *fdt, int *fdt_start_offset, Error **errp) 3416 { 3417 uint64_t addr; 3418 uint32_t node; 3419 3420 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3421 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3422 &error_abort); 3423 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3424 SPAPR_MEMORY_BLOCK_SIZE); 3425 return 0; 3426 } 3427 3428 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3429 bool dedicated_hp_event_source, Error **errp) 3430 { 3431 SpaprDrc *drc; 3432 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3433 int i; 3434 uint64_t addr = addr_start; 3435 bool hotplugged = spapr_drc_hotplugged(dev); 3436 Error *local_err = NULL; 3437 3438 for (i = 0; i < nr_lmbs; i++) { 3439 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3440 addr / SPAPR_MEMORY_BLOCK_SIZE); 3441 g_assert(drc); 3442 3443 spapr_drc_attach(drc, dev, &local_err); 3444 if (local_err) { 3445 while (addr > addr_start) { 3446 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3447 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3448 addr / SPAPR_MEMORY_BLOCK_SIZE); 3449 spapr_drc_detach(drc); 3450 } 3451 error_propagate(errp, local_err); 3452 return; 3453 } 3454 if (!hotplugged) { 3455 spapr_drc_reset(drc); 3456 } 3457 addr += SPAPR_MEMORY_BLOCK_SIZE; 3458 } 3459 /* send hotplug notification to the 3460 * guest only in case of hotplugged memory 3461 */ 3462 if (hotplugged) { 3463 if (dedicated_hp_event_source) { 3464 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3465 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3466 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3467 nr_lmbs, 3468 spapr_drc_index(drc)); 3469 } else { 3470 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3471 nr_lmbs); 3472 } 3473 } 3474 } 3475 3476 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3477 Error **errp) 3478 { 3479 Error *local_err = NULL; 3480 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3481 PCDIMMDevice *dimm = PC_DIMM(dev); 3482 uint64_t size, addr, slot; 3483 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3484 3485 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3486 3487 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3488 if (local_err) { 3489 goto out; 3490 } 3491 3492 if (!is_nvdimm) { 3493 addr = object_property_get_uint(OBJECT(dimm), 3494 PC_DIMM_ADDR_PROP, &local_err); 3495 if (local_err) { 3496 goto out_unplug; 3497 } 3498 spapr_add_lmbs(dev, addr, size, 3499 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3500 &local_err); 3501 } else { 3502 slot = object_property_get_uint(OBJECT(dimm), 3503 PC_DIMM_SLOT_PROP, &local_err); 3504 if (local_err) { 3505 goto out_unplug; 3506 } 3507 spapr_add_nvdimm(dev, slot, &local_err); 3508 } 3509 3510 if (local_err) { 3511 goto out_unplug; 3512 } 3513 3514 return; 3515 3516 out_unplug: 3517 pc_dimm_unplug(dimm, MACHINE(ms)); 3518 out: 3519 error_propagate(errp, local_err); 3520 } 3521 3522 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3523 Error **errp) 3524 { 3525 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3526 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3527 const MachineClass *mc = MACHINE_CLASS(smc); 3528 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3529 PCDIMMDevice *dimm = PC_DIMM(dev); 3530 Error *local_err = NULL; 3531 uint64_t size; 3532 Object *memdev; 3533 hwaddr pagesize; 3534 3535 if (!smc->dr_lmb_enabled) { 3536 error_setg(errp, "Memory hotplug not supported for this machine"); 3537 return; 3538 } 3539 3540 if (is_nvdimm && !mc->nvdimm_supported) { 3541 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3542 return; 3543 } 3544 3545 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3546 if (local_err) { 3547 error_propagate(errp, local_err); 3548 return; 3549 } 3550 3551 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3552 error_setg(errp, "Hotplugged memory size must be a multiple of " 3553 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3554 return; 3555 } else if (is_nvdimm) { 3556 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3557 if (local_err) { 3558 error_propagate(errp, local_err); 3559 return; 3560 } 3561 } 3562 3563 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3564 &error_abort); 3565 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3566 spapr_check_pagesize(spapr, pagesize, &local_err); 3567 if (local_err) { 3568 error_propagate(errp, local_err); 3569 return; 3570 } 3571 3572 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3573 } 3574 3575 struct SpaprDimmState { 3576 PCDIMMDevice *dimm; 3577 uint32_t nr_lmbs; 3578 QTAILQ_ENTRY(SpaprDimmState) next; 3579 }; 3580 3581 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3582 PCDIMMDevice *dimm) 3583 { 3584 SpaprDimmState *dimm_state = NULL; 3585 3586 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3587 if (dimm_state->dimm == dimm) { 3588 break; 3589 } 3590 } 3591 return dimm_state; 3592 } 3593 3594 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3595 uint32_t nr_lmbs, 3596 PCDIMMDevice *dimm) 3597 { 3598 SpaprDimmState *ds = NULL; 3599 3600 /* 3601 * If this request is for a DIMM whose removal had failed earlier 3602 * (due to guest's refusal to remove the LMBs), we would have this 3603 * dimm already in the pending_dimm_unplugs list. In that 3604 * case don't add again. 3605 */ 3606 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3607 if (!ds) { 3608 ds = g_malloc0(sizeof(SpaprDimmState)); 3609 ds->nr_lmbs = nr_lmbs; 3610 ds->dimm = dimm; 3611 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3612 } 3613 return ds; 3614 } 3615 3616 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3617 SpaprDimmState *dimm_state) 3618 { 3619 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3620 g_free(dimm_state); 3621 } 3622 3623 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3624 PCDIMMDevice *dimm) 3625 { 3626 SpaprDrc *drc; 3627 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3628 &error_abort); 3629 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3630 uint32_t avail_lmbs = 0; 3631 uint64_t addr_start, addr; 3632 int i; 3633 3634 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3635 &error_abort); 3636 3637 addr = addr_start; 3638 for (i = 0; i < nr_lmbs; i++) { 3639 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3640 addr / SPAPR_MEMORY_BLOCK_SIZE); 3641 g_assert(drc); 3642 if (drc->dev) { 3643 avail_lmbs++; 3644 } 3645 addr += SPAPR_MEMORY_BLOCK_SIZE; 3646 } 3647 3648 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3649 } 3650 3651 /* Callback to be called during DRC release. */ 3652 void spapr_lmb_release(DeviceState *dev) 3653 { 3654 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3655 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3656 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3657 3658 /* This information will get lost if a migration occurs 3659 * during the unplug process. In this case recover it. */ 3660 if (ds == NULL) { 3661 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3662 g_assert(ds); 3663 /* The DRC being examined by the caller at least must be counted */ 3664 g_assert(ds->nr_lmbs); 3665 } 3666 3667 if (--ds->nr_lmbs) { 3668 return; 3669 } 3670 3671 /* 3672 * Now that all the LMBs have been removed by the guest, call the 3673 * unplug handler chain. This can never fail. 3674 */ 3675 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3676 object_unparent(OBJECT(dev)); 3677 } 3678 3679 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3680 { 3681 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3682 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3683 3684 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3685 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3686 spapr_pending_dimm_unplugs_remove(spapr, ds); 3687 } 3688 3689 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3690 DeviceState *dev, Error **errp) 3691 { 3692 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3693 Error *local_err = NULL; 3694 PCDIMMDevice *dimm = PC_DIMM(dev); 3695 uint32_t nr_lmbs; 3696 uint64_t size, addr_start, addr; 3697 int i; 3698 SpaprDrc *drc; 3699 3700 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3701 error_setg(&local_err, 3702 "nvdimm device hot unplug is not supported yet."); 3703 goto out; 3704 } 3705 3706 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3707 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3708 3709 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3710 &local_err); 3711 if (local_err) { 3712 goto out; 3713 } 3714 3715 /* 3716 * An existing pending dimm state for this DIMM means that there is an 3717 * unplug operation in progress, waiting for the spapr_lmb_release 3718 * callback to complete the job (BQL can't cover that far). In this case, 3719 * bail out to avoid detaching DRCs that were already released. 3720 */ 3721 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3722 error_setg(&local_err, 3723 "Memory unplug already in progress for device %s", 3724 dev->id); 3725 goto out; 3726 } 3727 3728 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3729 3730 addr = addr_start; 3731 for (i = 0; i < nr_lmbs; i++) { 3732 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3733 addr / SPAPR_MEMORY_BLOCK_SIZE); 3734 g_assert(drc); 3735 3736 spapr_drc_detach(drc); 3737 addr += SPAPR_MEMORY_BLOCK_SIZE; 3738 } 3739 3740 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3741 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3742 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3743 nr_lmbs, spapr_drc_index(drc)); 3744 out: 3745 error_propagate(errp, local_err); 3746 } 3747 3748 /* Callback to be called during DRC release. */ 3749 void spapr_core_release(DeviceState *dev) 3750 { 3751 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3752 3753 /* Call the unplug handler chain. This can never fail. */ 3754 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3755 object_unparent(OBJECT(dev)); 3756 } 3757 3758 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3759 { 3760 MachineState *ms = MACHINE(hotplug_dev); 3761 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3762 CPUCore *cc = CPU_CORE(dev); 3763 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3764 3765 if (smc->pre_2_10_has_unused_icps) { 3766 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3767 int i; 3768 3769 for (i = 0; i < cc->nr_threads; i++) { 3770 CPUState *cs = CPU(sc->threads[i]); 3771 3772 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3773 } 3774 } 3775 3776 assert(core_slot); 3777 core_slot->cpu = NULL; 3778 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3779 } 3780 3781 static 3782 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3783 Error **errp) 3784 { 3785 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3786 int index; 3787 SpaprDrc *drc; 3788 CPUCore *cc = CPU_CORE(dev); 3789 3790 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3791 error_setg(errp, "Unable to find CPU core with core-id: %d", 3792 cc->core_id); 3793 return; 3794 } 3795 if (index == 0) { 3796 error_setg(errp, "Boot CPU core may not be unplugged"); 3797 return; 3798 } 3799 3800 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3801 spapr_vcpu_id(spapr, cc->core_id)); 3802 g_assert(drc); 3803 3804 if (!spapr_drc_unplug_requested(drc)) { 3805 spapr_drc_detach(drc); 3806 spapr_hotplug_req_remove_by_index(drc); 3807 } 3808 } 3809 3810 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3811 void *fdt, int *fdt_start_offset, Error **errp) 3812 { 3813 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3814 CPUState *cs = CPU(core->threads[0]); 3815 PowerPCCPU *cpu = POWERPC_CPU(cs); 3816 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3817 int id = spapr_get_vcpu_id(cpu); 3818 char *nodename; 3819 int offset; 3820 3821 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3822 offset = fdt_add_subnode(fdt, 0, nodename); 3823 g_free(nodename); 3824 3825 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3826 3827 *fdt_start_offset = offset; 3828 return 0; 3829 } 3830 3831 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3832 Error **errp) 3833 { 3834 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3835 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3836 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3837 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3838 CPUCore *cc = CPU_CORE(dev); 3839 CPUState *cs; 3840 SpaprDrc *drc; 3841 Error *local_err = NULL; 3842 CPUArchId *core_slot; 3843 int index; 3844 bool hotplugged = spapr_drc_hotplugged(dev); 3845 int i; 3846 3847 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3848 if (!core_slot) { 3849 error_setg(errp, "Unable to find CPU core with core-id: %d", 3850 cc->core_id); 3851 return; 3852 } 3853 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3854 spapr_vcpu_id(spapr, cc->core_id)); 3855 3856 g_assert(drc || !mc->has_hotpluggable_cpus); 3857 3858 if (drc) { 3859 spapr_drc_attach(drc, dev, &local_err); 3860 if (local_err) { 3861 error_propagate(errp, local_err); 3862 return; 3863 } 3864 3865 if (hotplugged) { 3866 /* 3867 * Send hotplug notification interrupt to the guest only 3868 * in case of hotplugged CPUs. 3869 */ 3870 spapr_hotplug_req_add_by_index(drc); 3871 } else { 3872 spapr_drc_reset(drc); 3873 } 3874 } 3875 3876 core_slot->cpu = OBJECT(dev); 3877 3878 if (smc->pre_2_10_has_unused_icps) { 3879 for (i = 0; i < cc->nr_threads; i++) { 3880 cs = CPU(core->threads[i]); 3881 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3882 } 3883 } 3884 3885 /* 3886 * Set compatibility mode to match the boot CPU, which was either set 3887 * by the machine reset code or by CAS. 3888 */ 3889 if (hotplugged) { 3890 for (i = 0; i < cc->nr_threads; i++) { 3891 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3892 &local_err); 3893 if (local_err) { 3894 error_propagate(errp, local_err); 3895 return; 3896 } 3897 } 3898 } 3899 } 3900 3901 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3902 Error **errp) 3903 { 3904 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3905 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3906 Error *local_err = NULL; 3907 CPUCore *cc = CPU_CORE(dev); 3908 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3909 const char *type = object_get_typename(OBJECT(dev)); 3910 CPUArchId *core_slot; 3911 int index; 3912 unsigned int smp_threads = machine->smp.threads; 3913 3914 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3915 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3916 goto out; 3917 } 3918 3919 if (strcmp(base_core_type, type)) { 3920 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3921 goto out; 3922 } 3923 3924 if (cc->core_id % smp_threads) { 3925 error_setg(&local_err, "invalid core id %d", cc->core_id); 3926 goto out; 3927 } 3928 3929 /* 3930 * In general we should have homogeneous threads-per-core, but old 3931 * (pre hotplug support) machine types allow the last core to have 3932 * reduced threads as a compatibility hack for when we allowed 3933 * total vcpus not a multiple of threads-per-core. 3934 */ 3935 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3936 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3937 cc->nr_threads, smp_threads); 3938 goto out; 3939 } 3940 3941 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3942 if (!core_slot) { 3943 error_setg(&local_err, "core id %d out of range", cc->core_id); 3944 goto out; 3945 } 3946 3947 if (core_slot->cpu) { 3948 error_setg(&local_err, "core %d already populated", cc->core_id); 3949 goto out; 3950 } 3951 3952 numa_cpu_pre_plug(core_slot, dev, &local_err); 3953 3954 out: 3955 error_propagate(errp, local_err); 3956 } 3957 3958 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3959 void *fdt, int *fdt_start_offset, Error **errp) 3960 { 3961 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3962 int intc_phandle; 3963 3964 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3965 if (intc_phandle <= 0) { 3966 return -1; 3967 } 3968 3969 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3970 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3971 return -1; 3972 } 3973 3974 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3975 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3976 3977 return 0; 3978 } 3979 3980 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3981 Error **errp) 3982 { 3983 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3984 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3985 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3986 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3987 3988 if (dev->hotplugged && !smc->dr_phb_enabled) { 3989 error_setg(errp, "PHB hotplug not supported for this machine"); 3990 return; 3991 } 3992 3993 if (sphb->index == (uint32_t)-1) { 3994 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3995 return; 3996 } 3997 3998 /* 3999 * This will check that sphb->index doesn't exceed the maximum number of 4000 * PHBs for the current machine type. 4001 */ 4002 smc->phb_placement(spapr, sphb->index, 4003 &sphb->buid, &sphb->io_win_addr, 4004 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4005 windows_supported, sphb->dma_liobn, 4006 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4007 errp); 4008 } 4009 4010 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4011 Error **errp) 4012 { 4013 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4014 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4015 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4016 SpaprDrc *drc; 4017 bool hotplugged = spapr_drc_hotplugged(dev); 4018 Error *local_err = NULL; 4019 4020 if (!smc->dr_phb_enabled) { 4021 return; 4022 } 4023 4024 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4025 /* hotplug hooks should check it's enabled before getting this far */ 4026 assert(drc); 4027 4028 spapr_drc_attach(drc, DEVICE(dev), &local_err); 4029 if (local_err) { 4030 error_propagate(errp, local_err); 4031 return; 4032 } 4033 4034 if (hotplugged) { 4035 spapr_hotplug_req_add_by_index(drc); 4036 } else { 4037 spapr_drc_reset(drc); 4038 } 4039 } 4040 4041 void spapr_phb_release(DeviceState *dev) 4042 { 4043 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4044 4045 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4046 object_unparent(OBJECT(dev)); 4047 } 4048 4049 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4050 { 4051 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4052 } 4053 4054 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4055 DeviceState *dev, Error **errp) 4056 { 4057 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4058 SpaprDrc *drc; 4059 4060 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4061 assert(drc); 4062 4063 if (!spapr_drc_unplug_requested(drc)) { 4064 spapr_drc_detach(drc); 4065 spapr_hotplug_req_remove_by_index(drc); 4066 } 4067 } 4068 4069 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4070 Error **errp) 4071 { 4072 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4073 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4074 4075 if (spapr->tpm_proxy != NULL) { 4076 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4077 return; 4078 } 4079 4080 spapr->tpm_proxy = tpm_proxy; 4081 } 4082 4083 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4084 { 4085 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4086 4087 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4088 object_unparent(OBJECT(dev)); 4089 spapr->tpm_proxy = NULL; 4090 } 4091 4092 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4093 DeviceState *dev, Error **errp) 4094 { 4095 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4096 spapr_memory_plug(hotplug_dev, dev, errp); 4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4098 spapr_core_plug(hotplug_dev, dev, errp); 4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4100 spapr_phb_plug(hotplug_dev, dev, errp); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4102 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4103 } 4104 } 4105 4106 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4107 DeviceState *dev, Error **errp) 4108 { 4109 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4110 spapr_memory_unplug(hotplug_dev, dev); 4111 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4112 spapr_core_unplug(hotplug_dev, dev); 4113 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4114 spapr_phb_unplug(hotplug_dev, dev); 4115 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4116 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4117 } 4118 } 4119 4120 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4121 DeviceState *dev, Error **errp) 4122 { 4123 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4124 MachineClass *mc = MACHINE_GET_CLASS(sms); 4125 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4126 4127 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4128 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4129 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4130 } else { 4131 /* NOTE: this means there is a window after guest reset, prior to 4132 * CAS negotiation, where unplug requests will fail due to the 4133 * capability not being detected yet. This is a bit different than 4134 * the case with PCI unplug, where the events will be queued and 4135 * eventually handled by the guest after boot 4136 */ 4137 error_setg(errp, "Memory hot unplug not supported for this guest"); 4138 } 4139 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4140 if (!mc->has_hotpluggable_cpus) { 4141 error_setg(errp, "CPU hot unplug not supported on this machine"); 4142 return; 4143 } 4144 spapr_core_unplug_request(hotplug_dev, dev, errp); 4145 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4146 if (!smc->dr_phb_enabled) { 4147 error_setg(errp, "PHB hot unplug not supported on this machine"); 4148 return; 4149 } 4150 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4151 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4152 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4153 } 4154 } 4155 4156 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4157 DeviceState *dev, Error **errp) 4158 { 4159 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4160 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4161 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4162 spapr_core_pre_plug(hotplug_dev, dev, errp); 4163 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4164 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4165 } 4166 } 4167 4168 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4169 DeviceState *dev) 4170 { 4171 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4172 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4173 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4174 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4175 return HOTPLUG_HANDLER(machine); 4176 } 4177 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4178 PCIDevice *pcidev = PCI_DEVICE(dev); 4179 PCIBus *root = pci_device_root_bus(pcidev); 4180 SpaprPhbState *phb = 4181 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4182 TYPE_SPAPR_PCI_HOST_BRIDGE); 4183 4184 if (phb) { 4185 return HOTPLUG_HANDLER(phb); 4186 } 4187 } 4188 return NULL; 4189 } 4190 4191 static CpuInstanceProperties 4192 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4193 { 4194 CPUArchId *core_slot; 4195 MachineClass *mc = MACHINE_GET_CLASS(machine); 4196 4197 /* make sure possible_cpu are intialized */ 4198 mc->possible_cpu_arch_ids(machine); 4199 /* get CPU core slot containing thread that matches cpu_index */ 4200 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4201 assert(core_slot); 4202 return core_slot->props; 4203 } 4204 4205 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4206 { 4207 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4208 } 4209 4210 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4211 { 4212 int i; 4213 unsigned int smp_threads = machine->smp.threads; 4214 unsigned int smp_cpus = machine->smp.cpus; 4215 const char *core_type; 4216 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4217 MachineClass *mc = MACHINE_GET_CLASS(machine); 4218 4219 if (!mc->has_hotpluggable_cpus) { 4220 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4221 } 4222 if (machine->possible_cpus) { 4223 assert(machine->possible_cpus->len == spapr_max_cores); 4224 return machine->possible_cpus; 4225 } 4226 4227 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4228 if (!core_type) { 4229 error_report("Unable to find sPAPR CPU Core definition"); 4230 exit(1); 4231 } 4232 4233 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4234 sizeof(CPUArchId) * spapr_max_cores); 4235 machine->possible_cpus->len = spapr_max_cores; 4236 for (i = 0; i < machine->possible_cpus->len; i++) { 4237 int core_id = i * smp_threads; 4238 4239 machine->possible_cpus->cpus[i].type = core_type; 4240 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4241 machine->possible_cpus->cpus[i].arch_id = core_id; 4242 machine->possible_cpus->cpus[i].props.has_core_id = true; 4243 machine->possible_cpus->cpus[i].props.core_id = core_id; 4244 } 4245 return machine->possible_cpus; 4246 } 4247 4248 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4249 uint64_t *buid, hwaddr *pio, 4250 hwaddr *mmio32, hwaddr *mmio64, 4251 unsigned n_dma, uint32_t *liobns, 4252 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4253 { 4254 /* 4255 * New-style PHB window placement. 4256 * 4257 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4258 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4259 * windows. 4260 * 4261 * Some guest kernels can't work with MMIO windows above 1<<46 4262 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4263 * 4264 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4265 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4266 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4267 * 1TiB 64-bit MMIO windows for each PHB. 4268 */ 4269 const uint64_t base_buid = 0x800000020000000ULL; 4270 int i; 4271 4272 /* Sanity check natural alignments */ 4273 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4274 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4275 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4276 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4277 /* Sanity check bounds */ 4278 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4279 SPAPR_PCI_MEM32_WIN_SIZE); 4280 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4281 SPAPR_PCI_MEM64_WIN_SIZE); 4282 4283 if (index >= SPAPR_MAX_PHBS) { 4284 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4285 SPAPR_MAX_PHBS - 1); 4286 return; 4287 } 4288 4289 *buid = base_buid + index; 4290 for (i = 0; i < n_dma; ++i) { 4291 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4292 } 4293 4294 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4295 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4296 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4297 4298 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4299 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4300 } 4301 4302 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4303 { 4304 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4305 4306 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4307 } 4308 4309 static void spapr_ics_resend(XICSFabric *dev) 4310 { 4311 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4312 4313 ics_resend(spapr->ics); 4314 } 4315 4316 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4317 { 4318 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4319 4320 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4321 } 4322 4323 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4324 Monitor *mon) 4325 { 4326 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4327 4328 spapr_irq_print_info(spapr, mon); 4329 monitor_printf(mon, "irqchip: %s\n", 4330 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4331 } 4332 4333 /* 4334 * This is a XIVE only operation 4335 */ 4336 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4337 uint8_t nvt_blk, uint32_t nvt_idx, 4338 bool cam_ignore, uint8_t priority, 4339 uint32_t logic_serv, XiveTCTXMatch *match) 4340 { 4341 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4342 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4343 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4344 int count; 4345 4346 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4347 priority, logic_serv, match); 4348 if (count < 0) { 4349 return count; 4350 } 4351 4352 /* 4353 * When we implement the save and restore of the thread interrupt 4354 * contexts in the enter/exit CPU handlers of the machine and the 4355 * escalations in QEMU, we should be able to handle non dispatched 4356 * vCPUs. 4357 * 4358 * Until this is done, the sPAPR machine should find at least one 4359 * matching context always. 4360 */ 4361 if (count == 0) { 4362 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4363 nvt_blk, nvt_idx); 4364 } 4365 4366 return count; 4367 } 4368 4369 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4370 { 4371 return cpu->vcpu_id; 4372 } 4373 4374 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4375 { 4376 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4377 MachineState *ms = MACHINE(spapr); 4378 int vcpu_id; 4379 4380 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4381 4382 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4383 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4384 error_append_hint(errp, "Adjust the number of cpus to %d " 4385 "or try to raise the number of threads per core\n", 4386 vcpu_id * ms->smp.threads / spapr->vsmt); 4387 return; 4388 } 4389 4390 cpu->vcpu_id = vcpu_id; 4391 } 4392 4393 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4394 { 4395 CPUState *cs; 4396 4397 CPU_FOREACH(cs) { 4398 PowerPCCPU *cpu = POWERPC_CPU(cs); 4399 4400 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4401 return cpu; 4402 } 4403 } 4404 4405 return NULL; 4406 } 4407 4408 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4409 { 4410 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4411 4412 /* These are only called by TCG, KVM maintains dispatch state */ 4413 4414 spapr_cpu->prod = false; 4415 if (spapr_cpu->vpa_addr) { 4416 CPUState *cs = CPU(cpu); 4417 uint32_t dispatch; 4418 4419 dispatch = ldl_be_phys(cs->as, 4420 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4421 dispatch++; 4422 if ((dispatch & 1) != 0) { 4423 qemu_log_mask(LOG_GUEST_ERROR, 4424 "VPA: incorrect dispatch counter value for " 4425 "dispatched partition %u, correcting.\n", dispatch); 4426 dispatch++; 4427 } 4428 stl_be_phys(cs->as, 4429 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4430 } 4431 } 4432 4433 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4434 { 4435 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4436 4437 if (spapr_cpu->vpa_addr) { 4438 CPUState *cs = CPU(cpu); 4439 uint32_t dispatch; 4440 4441 dispatch = ldl_be_phys(cs->as, 4442 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4443 dispatch++; 4444 if ((dispatch & 1) != 1) { 4445 qemu_log_mask(LOG_GUEST_ERROR, 4446 "VPA: incorrect dispatch counter value for " 4447 "preempted partition %u, correcting.\n", dispatch); 4448 dispatch++; 4449 } 4450 stl_be_phys(cs->as, 4451 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4452 } 4453 } 4454 4455 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4456 { 4457 MachineClass *mc = MACHINE_CLASS(oc); 4458 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4459 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4460 NMIClass *nc = NMI_CLASS(oc); 4461 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4462 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4463 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4464 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4465 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4466 4467 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4468 mc->ignore_boot_device_suffixes = true; 4469 4470 /* 4471 * We set up the default / latest behaviour here. The class_init 4472 * functions for the specific versioned machine types can override 4473 * these details for backwards compatibility 4474 */ 4475 mc->init = spapr_machine_init; 4476 mc->reset = spapr_machine_reset; 4477 mc->block_default_type = IF_SCSI; 4478 mc->max_cpus = 1024; 4479 mc->no_parallel = 1; 4480 mc->default_boot_order = ""; 4481 mc->default_ram_size = 512 * MiB; 4482 mc->default_ram_id = "ppc_spapr.ram"; 4483 mc->default_display = "std"; 4484 mc->kvm_type = spapr_kvm_type; 4485 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4486 mc->pci_allow_0_address = true; 4487 assert(!mc->get_hotplug_handler); 4488 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4489 hc->pre_plug = spapr_machine_device_pre_plug; 4490 hc->plug = spapr_machine_device_plug; 4491 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4492 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4493 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4494 hc->unplug_request = spapr_machine_device_unplug_request; 4495 hc->unplug = spapr_machine_device_unplug; 4496 4497 smc->dr_lmb_enabled = true; 4498 smc->update_dt_enabled = true; 4499 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4500 mc->has_hotpluggable_cpus = true; 4501 mc->nvdimm_supported = true; 4502 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4503 fwc->get_dev_path = spapr_get_fw_dev_path; 4504 nc->nmi_monitor_handler = spapr_nmi; 4505 smc->phb_placement = spapr_phb_placement; 4506 vhc->hypercall = emulate_spapr_hypercall; 4507 vhc->hpt_mask = spapr_hpt_mask; 4508 vhc->map_hptes = spapr_map_hptes; 4509 vhc->unmap_hptes = spapr_unmap_hptes; 4510 vhc->hpte_set_c = spapr_hpte_set_c; 4511 vhc->hpte_set_r = spapr_hpte_set_r; 4512 vhc->get_pate = spapr_get_pate; 4513 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4514 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4515 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4516 xic->ics_get = spapr_ics_get; 4517 xic->ics_resend = spapr_ics_resend; 4518 xic->icp_get = spapr_icp_get; 4519 ispc->print_info = spapr_pic_print_info; 4520 /* Force NUMA node memory size to be a multiple of 4521 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4522 * in which LMBs are represented and hot-added 4523 */ 4524 mc->numa_mem_align_shift = 28; 4525 mc->numa_mem_supported = true; 4526 mc->auto_enable_numa = true; 4527 4528 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4529 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4530 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4531 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4532 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4533 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4534 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4535 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4536 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4537 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4538 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON; 4539 spapr_caps_add_properties(smc, &error_abort); 4540 smc->irq = &spapr_irq_dual; 4541 smc->dr_phb_enabled = true; 4542 smc->linux_pci_probe = true; 4543 smc->smp_threads_vsmt = true; 4544 smc->nr_xirqs = SPAPR_NR_XIRQS; 4545 xfc->match_nvt = spapr_match_nvt; 4546 } 4547 4548 static const TypeInfo spapr_machine_info = { 4549 .name = TYPE_SPAPR_MACHINE, 4550 .parent = TYPE_MACHINE, 4551 .abstract = true, 4552 .instance_size = sizeof(SpaprMachineState), 4553 .instance_init = spapr_instance_init, 4554 .instance_finalize = spapr_machine_finalizefn, 4555 .class_size = sizeof(SpaprMachineClass), 4556 .class_init = spapr_machine_class_init, 4557 .interfaces = (InterfaceInfo[]) { 4558 { TYPE_FW_PATH_PROVIDER }, 4559 { TYPE_NMI }, 4560 { TYPE_HOTPLUG_HANDLER }, 4561 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4562 { TYPE_XICS_FABRIC }, 4563 { TYPE_INTERRUPT_STATS_PROVIDER }, 4564 { TYPE_XIVE_FABRIC }, 4565 { } 4566 }, 4567 }; 4568 4569 static void spapr_machine_latest_class_options(MachineClass *mc) 4570 { 4571 mc->alias = "pseries"; 4572 mc->is_default = true; 4573 } 4574 4575 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4576 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4577 void *data) \ 4578 { \ 4579 MachineClass *mc = MACHINE_CLASS(oc); \ 4580 spapr_machine_##suffix##_class_options(mc); \ 4581 if (latest) { \ 4582 spapr_machine_latest_class_options(mc); \ 4583 } \ 4584 } \ 4585 static const TypeInfo spapr_machine_##suffix##_info = { \ 4586 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4587 .parent = TYPE_SPAPR_MACHINE, \ 4588 .class_init = spapr_machine_##suffix##_class_init, \ 4589 }; \ 4590 static void spapr_machine_register_##suffix(void) \ 4591 { \ 4592 type_register(&spapr_machine_##suffix##_info); \ 4593 } \ 4594 type_init(spapr_machine_register_##suffix) 4595 4596 /* 4597 * pseries-5.0 4598 */ 4599 static void spapr_machine_5_0_class_options(MachineClass *mc) 4600 { 4601 /* Defaults for the latest behaviour inherited from the base class */ 4602 } 4603 4604 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4605 4606 /* 4607 * pseries-4.2 4608 */ 4609 static void spapr_machine_4_2_class_options(MachineClass *mc) 4610 { 4611 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4612 4613 spapr_machine_5_0_class_options(mc); 4614 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4615 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4616 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; 4617 smc->rma_limit = 16 * GiB; 4618 mc->nvdimm_supported = false; 4619 } 4620 4621 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4622 4623 /* 4624 * pseries-4.1 4625 */ 4626 static void spapr_machine_4_1_class_options(MachineClass *mc) 4627 { 4628 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4629 static GlobalProperty compat[] = { 4630 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4631 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4632 }; 4633 4634 spapr_machine_4_2_class_options(mc); 4635 smc->linux_pci_probe = false; 4636 smc->smp_threads_vsmt = false; 4637 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4638 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4639 } 4640 4641 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4642 4643 /* 4644 * pseries-4.0 4645 */ 4646 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4647 uint64_t *buid, hwaddr *pio, 4648 hwaddr *mmio32, hwaddr *mmio64, 4649 unsigned n_dma, uint32_t *liobns, 4650 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4651 { 4652 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4653 nv2gpa, nv2atsd, errp); 4654 *nv2gpa = 0; 4655 *nv2atsd = 0; 4656 } 4657 4658 static void spapr_machine_4_0_class_options(MachineClass *mc) 4659 { 4660 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4661 4662 spapr_machine_4_1_class_options(mc); 4663 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4664 smc->phb_placement = phb_placement_4_0; 4665 smc->irq = &spapr_irq_xics; 4666 smc->pre_4_1_migration = true; 4667 } 4668 4669 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4670 4671 /* 4672 * pseries-3.1 4673 */ 4674 static void spapr_machine_3_1_class_options(MachineClass *mc) 4675 { 4676 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4677 4678 spapr_machine_4_0_class_options(mc); 4679 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4680 4681 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4682 smc->update_dt_enabled = false; 4683 smc->dr_phb_enabled = false; 4684 smc->broken_host_serial_model = true; 4685 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4686 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4687 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4688 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4689 } 4690 4691 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4692 4693 /* 4694 * pseries-3.0 4695 */ 4696 4697 static void spapr_machine_3_0_class_options(MachineClass *mc) 4698 { 4699 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4700 4701 spapr_machine_3_1_class_options(mc); 4702 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4703 4704 smc->legacy_irq_allocation = true; 4705 smc->nr_xirqs = 0x400; 4706 smc->irq = &spapr_irq_xics_legacy; 4707 } 4708 4709 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4710 4711 /* 4712 * pseries-2.12 4713 */ 4714 static void spapr_machine_2_12_class_options(MachineClass *mc) 4715 { 4716 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4717 static GlobalProperty compat[] = { 4718 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4719 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4720 }; 4721 4722 spapr_machine_3_0_class_options(mc); 4723 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4724 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4725 4726 /* We depend on kvm_enabled() to choose a default value for the 4727 * hpt-max-page-size capability. Of course we can't do it here 4728 * because this is too early and the HW accelerator isn't initialzed 4729 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4730 */ 4731 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4732 } 4733 4734 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4735 4736 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4737 { 4738 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4739 4740 spapr_machine_2_12_class_options(mc); 4741 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4742 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4743 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4744 } 4745 4746 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4747 4748 /* 4749 * pseries-2.11 4750 */ 4751 4752 static void spapr_machine_2_11_class_options(MachineClass *mc) 4753 { 4754 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4755 4756 spapr_machine_2_12_class_options(mc); 4757 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4758 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4759 } 4760 4761 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4762 4763 /* 4764 * pseries-2.10 4765 */ 4766 4767 static void spapr_machine_2_10_class_options(MachineClass *mc) 4768 { 4769 spapr_machine_2_11_class_options(mc); 4770 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4771 } 4772 4773 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4774 4775 /* 4776 * pseries-2.9 4777 */ 4778 4779 static void spapr_machine_2_9_class_options(MachineClass *mc) 4780 { 4781 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4782 static GlobalProperty compat[] = { 4783 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4784 }; 4785 4786 spapr_machine_2_10_class_options(mc); 4787 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4788 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4789 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4790 smc->pre_2_10_has_unused_icps = true; 4791 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4792 } 4793 4794 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4795 4796 /* 4797 * pseries-2.8 4798 */ 4799 4800 static void spapr_machine_2_8_class_options(MachineClass *mc) 4801 { 4802 static GlobalProperty compat[] = { 4803 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4804 }; 4805 4806 spapr_machine_2_9_class_options(mc); 4807 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4808 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4809 mc->numa_mem_align_shift = 23; 4810 } 4811 4812 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4813 4814 /* 4815 * pseries-2.7 4816 */ 4817 4818 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4819 uint64_t *buid, hwaddr *pio, 4820 hwaddr *mmio32, hwaddr *mmio64, 4821 unsigned n_dma, uint32_t *liobns, 4822 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4823 { 4824 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4825 const uint64_t base_buid = 0x800000020000000ULL; 4826 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4827 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4828 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4829 const uint32_t max_index = 255; 4830 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4831 4832 uint64_t ram_top = MACHINE(spapr)->ram_size; 4833 hwaddr phb0_base, phb_base; 4834 int i; 4835 4836 /* Do we have device memory? */ 4837 if (MACHINE(spapr)->maxram_size > ram_top) { 4838 /* Can't just use maxram_size, because there may be an 4839 * alignment gap between normal and device memory regions 4840 */ 4841 ram_top = MACHINE(spapr)->device_memory->base + 4842 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4843 } 4844 4845 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4846 4847 if (index > max_index) { 4848 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4849 max_index); 4850 return; 4851 } 4852 4853 *buid = base_buid + index; 4854 for (i = 0; i < n_dma; ++i) { 4855 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4856 } 4857 4858 phb_base = phb0_base + index * phb_spacing; 4859 *pio = phb_base + pio_offset; 4860 *mmio32 = phb_base + mmio_offset; 4861 /* 4862 * We don't set the 64-bit MMIO window, relying on the PHB's 4863 * fallback behaviour of automatically splitting a large "32-bit" 4864 * window into contiguous 32-bit and 64-bit windows 4865 */ 4866 4867 *nv2gpa = 0; 4868 *nv2atsd = 0; 4869 } 4870 4871 static void spapr_machine_2_7_class_options(MachineClass *mc) 4872 { 4873 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4874 static GlobalProperty compat[] = { 4875 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4876 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4877 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4878 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4879 }; 4880 4881 spapr_machine_2_8_class_options(mc); 4882 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4883 mc->default_machine_opts = "modern-hotplug-events=off"; 4884 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4885 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4886 smc->phb_placement = phb_placement_2_7; 4887 } 4888 4889 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4890 4891 /* 4892 * pseries-2.6 4893 */ 4894 4895 static void spapr_machine_2_6_class_options(MachineClass *mc) 4896 { 4897 static GlobalProperty compat[] = { 4898 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4899 }; 4900 4901 spapr_machine_2_7_class_options(mc); 4902 mc->has_hotpluggable_cpus = false; 4903 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4904 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4905 } 4906 4907 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4908 4909 /* 4910 * pseries-2.5 4911 */ 4912 4913 static void spapr_machine_2_5_class_options(MachineClass *mc) 4914 { 4915 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4916 static GlobalProperty compat[] = { 4917 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4918 }; 4919 4920 spapr_machine_2_6_class_options(mc); 4921 smc->use_ohci_by_default = true; 4922 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4923 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4924 } 4925 4926 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4927 4928 /* 4929 * pseries-2.4 4930 */ 4931 4932 static void spapr_machine_2_4_class_options(MachineClass *mc) 4933 { 4934 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4935 4936 spapr_machine_2_5_class_options(mc); 4937 smc->dr_lmb_enabled = false; 4938 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4939 } 4940 4941 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4942 4943 /* 4944 * pseries-2.3 4945 */ 4946 4947 static void spapr_machine_2_3_class_options(MachineClass *mc) 4948 { 4949 static GlobalProperty compat[] = { 4950 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4951 }; 4952 spapr_machine_2_4_class_options(mc); 4953 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4954 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4955 } 4956 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4957 4958 /* 4959 * pseries-2.2 4960 */ 4961 4962 static void spapr_machine_2_2_class_options(MachineClass *mc) 4963 { 4964 static GlobalProperty compat[] = { 4965 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4966 }; 4967 4968 spapr_machine_2_3_class_options(mc); 4969 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4970 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4971 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4972 } 4973 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4974 4975 /* 4976 * pseries-2.1 4977 */ 4978 4979 static void spapr_machine_2_1_class_options(MachineClass *mc) 4980 { 4981 spapr_machine_2_2_class_options(mc); 4982 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4983 } 4984 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4985 4986 static void spapr_machine_register_types(void) 4987 { 4988 type_register_static(&spapr_machine_info); 4989 } 4990 4991 type_init(spapr_machine_register_types) 4992