1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/tcg.h" 39 #include "sysemu/qtest.h" 40 #include "sysemu/reset.h" 41 #include "sysemu/runstate.h" 42 #include "qemu/log.h" 43 #include "hw/fw-path-provider.h" 44 #include "elf.h" 45 #include "net/net.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/cpus.h" 48 #include "sysemu/hw_accel.h" 49 #include "kvm_ppc.h" 50 #include "migration/misc.h" 51 #include "migration/qemu-file-types.h" 52 #include "migration/global_state.h" 53 #include "migration/register.h" 54 #include "migration/blocker.h" 55 #include "mmu-hash64.h" 56 #include "mmu-book3s-v3.h" 57 #include "cpu-models.h" 58 #include "hw/core/cpu.h" 59 60 #include "hw/ppc/ppc.h" 61 #include "hw/loader.h" 62 63 #include "hw/ppc/fdt.h" 64 #include "hw/ppc/spapr.h" 65 #include "hw/ppc/spapr_nested.h" 66 #include "hw/ppc/spapr_vio.h" 67 #include "hw/ppc/vof.h" 68 #include "hw/qdev-properties.h" 69 #include "hw/pci-host/spapr.h" 70 #include "hw/pci/msi.h" 71 72 #include "hw/pci/pci.h" 73 #include "hw/scsi/scsi.h" 74 #include "hw/virtio/virtio-scsi.h" 75 #include "hw/virtio/vhost-scsi-common.h" 76 77 #include "exec/ram_addr.h" 78 #include "exec/confidential-guest-support.h" 79 #include "hw/usb.h" 80 #include "qemu/config-file.h" 81 #include "qemu/error-report.h" 82 #include "trace.h" 83 #include "hw/nmi.h" 84 #include "hw/intc/intc.h" 85 86 #include "hw/ppc/spapr_cpu_core.h" 87 #include "hw/mem/memory-device.h" 88 #include "hw/ppc/spapr_tpm_proxy.h" 89 #include "hw/ppc/spapr_nvdimm.h" 90 #include "hw/ppc/spapr_numa.h" 91 92 #include <libfdt.h> 93 94 /* SLOF memory layout: 95 * 96 * SLOF raw image loaded at 0, copies its romfs right below the flat 97 * device-tree, then position SLOF itself 31M below that 98 * 99 * So we set FW_OVERHEAD to 40MB which should account for all of that 100 * and more 101 * 102 * We load our kernel at 4M, leaving space for SLOF initial image 103 */ 104 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 105 #define FW_MAX_SIZE 0x400000 106 #define FW_FILE_NAME "slof.bin" 107 #define FW_FILE_NAME_VOF "vof.bin" 108 #define FW_OVERHEAD 0x2800000 109 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 110 111 #define MIN_RMA_SLOF (128 * MiB) 112 113 #define PHANDLE_INTC 0x00001111 114 115 /* These two functions implement the VCPU id numbering: one to compute them 116 * all and one to identify thread 0 of a VCORE. Any change to the first one 117 * is likely to have an impact on the second one, so let's keep them close. 118 */ 119 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 120 { 121 MachineState *ms = MACHINE(spapr); 122 unsigned int smp_threads = ms->smp.threads; 123 124 assert(spapr->vsmt); 125 return 126 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 127 } 128 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 129 PowerPCCPU *cpu) 130 { 131 assert(spapr->vsmt); 132 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 133 } 134 135 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 136 { 137 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 138 * and newer QEMUs don't even have them. In both cases, we don't want 139 * to send anything on the wire. 140 */ 141 return false; 142 } 143 144 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 145 /* 146 * Hack ahead. We can't have two devices with the same name and 147 * instance id. So I rename this to pass make check. 148 * Real help from people who knows the hardware is needed. 149 */ 150 .name = "icp/server", 151 .version_id = 1, 152 .minimum_version_id = 1, 153 .needed = pre_2_10_vmstate_dummy_icp_needed, 154 .fields = (const VMStateField[]) { 155 VMSTATE_UNUSED(4), /* uint32_t xirr */ 156 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 157 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 158 VMSTATE_END_OF_LIST() 159 }, 160 }; 161 162 /* 163 * See comment in hw/intc/xics.c:icp_realize() 164 * 165 * You have to remove vmstate_replace_hack_for_ppc() when you remove 166 * the machine types that need the following function. 167 */ 168 static void pre_2_10_vmstate_register_dummy_icp(int i) 169 { 170 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 171 (void *)(uintptr_t) i); 172 } 173 174 /* 175 * See comment in hw/intc/xics.c:icp_realize() 176 * 177 * You have to remove vmstate_replace_hack_for_ppc() when you remove 178 * the machine types that need the following function. 179 */ 180 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 181 { 182 /* 183 * This used to be: 184 * 185 * vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 186 * (void *)(uintptr_t) i); 187 */ 188 } 189 190 int spapr_max_server_number(SpaprMachineState *spapr) 191 { 192 MachineState *ms = MACHINE(spapr); 193 194 assert(spapr->vsmt); 195 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 196 } 197 198 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 199 int smt_threads) 200 { 201 int i, ret = 0; 202 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 203 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 204 int index = spapr_get_vcpu_id(cpu); 205 206 if (cpu->compat_pvr) { 207 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 208 if (ret < 0) { 209 return ret; 210 } 211 } 212 213 /* Build interrupt servers and gservers properties */ 214 for (i = 0; i < smt_threads; i++) { 215 servers_prop[i] = cpu_to_be32(index + i); 216 /* Hack, direct the group queues back to cpu 0 */ 217 gservers_prop[i*2] = cpu_to_be32(index + i); 218 gservers_prop[i*2 + 1] = 0; 219 } 220 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 221 servers_prop, sizeof(*servers_prop) * smt_threads); 222 if (ret < 0) { 223 return ret; 224 } 225 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 226 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 227 228 return ret; 229 } 230 231 static void spapr_dt_pa_features(SpaprMachineState *spapr, 232 PowerPCCPU *cpu, 233 void *fdt, int offset) 234 { 235 /* 236 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 237 * but not MTTCG, so disable it. To advertise it, a cap would have 238 * to be added, or support implemented for MTTCG. 239 * 240 * Copy/paste is not supported by TCG, so it is not advertised. KVM 241 * can execute them but it has no accelerator drivers which are usable, 242 * so there isn't much need for it anyway. 243 */ 244 245 /* These should be kept in sync with pnv */ 246 uint8_t pa_features_206[] = { 6, 0, 247 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 248 uint8_t pa_features_207[] = { 24, 0, 249 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 250 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 251 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 252 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 253 uint8_t pa_features_300[] = { 66, 0, 254 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 255 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 256 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 257 /* 6: DS207 */ 258 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 259 /* 16: Vector */ 260 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 261 /* 18: Vec. Scalar, 20: Vec. XOR */ 262 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 263 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 264 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 265 /* 32: LE atomic, 34: EBB + ext EBB */ 266 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 267 /* 40: Radix MMU */ 268 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 269 /* 42: PM, 44: PC RA, 46: SC vec'd */ 270 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 271 /* 48: SIMD, 50: QP BFP, 52: String */ 272 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 273 /* 54: DecFP, 56: DecI, 58: SHA */ 274 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 275 /* 60: NM atomic, 62: RNG */ 276 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 277 }; 278 /* 3.1 removes SAO, HTM support */ 279 uint8_t pa_features_31[] = { 74, 0, 280 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 281 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 282 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 283 /* 6: DS207 */ 284 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 285 /* 16: Vector */ 286 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 287 /* 18: Vec. Scalar, 20: Vec. XOR */ 288 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 289 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 291 /* 32: LE atomic, 34: EBB + ext EBB */ 292 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 293 /* 40: Radix MMU */ 294 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 295 /* 42: PM, 44: PC RA, 46: SC vec'd */ 296 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 297 /* 48: SIMD, 50: QP BFP, 52: String */ 298 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 299 /* 54: DecFP, 56: DecI, 58: SHA */ 300 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 301 /* 60: NM atomic, 62: RNG */ 302 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 303 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 304 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 305 /* 72: [P]HASHST/[P]HASHCHK */ 306 0x80, 0x00, /* 72 - 73 */ 307 }; 308 uint8_t *pa_features = NULL; 309 size_t pa_size; 310 311 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 312 pa_features = pa_features_206; 313 pa_size = sizeof(pa_features_206); 314 } 315 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 316 pa_features = pa_features_207; 317 pa_size = sizeof(pa_features_207); 318 } 319 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 320 pa_features = pa_features_300; 321 pa_size = sizeof(pa_features_300); 322 } 323 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) { 324 pa_features = pa_features_31; 325 pa_size = sizeof(pa_features_31); 326 } 327 if (!pa_features) { 328 return; 329 } 330 331 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 332 /* 333 * Note: we keep CI large pages off by default because a 64K capable 334 * guest provisioned with large pages might otherwise try to map a qemu 335 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 336 * even if that qemu runs on a 4k host. 337 * We dd this bit back here if we are confident this is not an issue 338 */ 339 pa_features[3] |= 0x20; 340 } 341 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 342 pa_features[24] |= 0x80; /* Transactional memory support */ 343 } 344 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 345 /* Workaround for broken kernels that attempt (guest) radix 346 * mode when they can't handle it, if they see the radix bit set 347 * in pa-features. So hide it from them. */ 348 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 349 } 350 351 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 352 } 353 354 static void spapr_dt_pi_features(SpaprMachineState *spapr, 355 PowerPCCPU *cpu, 356 void *fdt, int offset) 357 { 358 uint8_t pi_features[] = { 1, 0, 359 0x00 }; 360 361 if (kvm_enabled() && ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 362 0, cpu->compat_pvr)) { 363 /* 364 * POWER9 and later CPUs with KVM run in LPAR-per-thread mode where 365 * all threads are essentially independent CPUs, and msgsndp does not 366 * work (because it is physically-addressed) and therefore is 367 * emulated by KVM, so disable it here to ensure XIVE will be used. 368 * This is both KVM and CPU implementation-specific behaviour so a KVM 369 * cap would be cleanest, but for now this works. If KVM ever permits 370 * native msgsndp execution by guests, a cap could be added at that 371 * time. 372 */ 373 pi_features[2] |= 0x08; /* 4: No msgsndp */ 374 } 375 376 _FDT((fdt_setprop(fdt, offset, "ibm,pi-features", pi_features, 377 sizeof(pi_features)))); 378 } 379 380 static hwaddr spapr_node0_size(MachineState *machine) 381 { 382 if (machine->numa_state->num_nodes) { 383 int i; 384 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 385 if (machine->numa_state->nodes[i].node_mem) { 386 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 387 machine->ram_size); 388 } 389 } 390 } 391 return machine->ram_size; 392 } 393 394 static void add_str(GString *s, const gchar *s1) 395 { 396 g_string_append_len(s, s1, strlen(s1) + 1); 397 } 398 399 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 400 hwaddr start, hwaddr size) 401 { 402 char mem_name[32]; 403 uint64_t mem_reg_property[2]; 404 int off; 405 406 mem_reg_property[0] = cpu_to_be64(start); 407 mem_reg_property[1] = cpu_to_be64(size); 408 409 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 410 off = fdt_add_subnode(fdt, 0, mem_name); 411 _FDT(off); 412 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 413 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 414 sizeof(mem_reg_property)))); 415 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 416 return off; 417 } 418 419 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 420 { 421 MemoryDeviceInfoList *info; 422 423 for (info = list; info; info = info->next) { 424 MemoryDeviceInfo *value = info->value; 425 426 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 427 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 428 429 if (addr >= pcdimm_info->addr && 430 addr < (pcdimm_info->addr + pcdimm_info->size)) { 431 return pcdimm_info->node; 432 } 433 } 434 } 435 436 return -1; 437 } 438 439 struct sPAPRDrconfCellV2 { 440 uint32_t seq_lmbs; 441 uint64_t base_addr; 442 uint32_t drc_index; 443 uint32_t aa_index; 444 uint32_t flags; 445 } QEMU_PACKED; 446 447 typedef struct DrconfCellQueue { 448 struct sPAPRDrconfCellV2 cell; 449 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 450 } DrconfCellQueue; 451 452 static DrconfCellQueue * 453 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 454 uint32_t drc_index, uint32_t aa_index, 455 uint32_t flags) 456 { 457 DrconfCellQueue *elem; 458 459 elem = g_malloc0(sizeof(*elem)); 460 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 461 elem->cell.base_addr = cpu_to_be64(base_addr); 462 elem->cell.drc_index = cpu_to_be32(drc_index); 463 elem->cell.aa_index = cpu_to_be32(aa_index); 464 elem->cell.flags = cpu_to_be32(flags); 465 466 return elem; 467 } 468 469 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 470 int offset, MemoryDeviceInfoList *dimms) 471 { 472 MachineState *machine = MACHINE(spapr); 473 uint8_t *int_buf, *cur_index; 474 int ret; 475 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 476 uint64_t addr, cur_addr, size; 477 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 478 uint64_t mem_end = machine->device_memory->base + 479 memory_region_size(&machine->device_memory->mr); 480 uint32_t node, buf_len, nr_entries = 0; 481 SpaprDrc *drc; 482 DrconfCellQueue *elem, *next; 483 MemoryDeviceInfoList *info; 484 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 485 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 486 487 /* Entry to cover RAM and the gap area */ 488 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 489 SPAPR_LMB_FLAGS_RESERVED | 490 SPAPR_LMB_FLAGS_DRC_INVALID); 491 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 492 nr_entries++; 493 494 cur_addr = machine->device_memory->base; 495 for (info = dimms; info; info = info->next) { 496 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 497 498 addr = di->addr; 499 size = di->size; 500 node = di->node; 501 502 /* 503 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 504 * area is marked hotpluggable in the next iteration for the bigger 505 * chunk including the NVDIMM occupied area. 506 */ 507 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 508 continue; 509 510 /* Entry for hot-pluggable area */ 511 if (cur_addr < addr) { 512 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 513 g_assert(drc); 514 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 515 cur_addr, spapr_drc_index(drc), -1, 0); 516 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 517 nr_entries++; 518 } 519 520 /* Entry for DIMM */ 521 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 522 g_assert(drc); 523 elem = spapr_get_drconf_cell(size / lmb_size, addr, 524 spapr_drc_index(drc), node, 525 (SPAPR_LMB_FLAGS_ASSIGNED | 526 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 527 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 528 nr_entries++; 529 cur_addr = addr + size; 530 } 531 532 /* Entry for remaining hotpluggable area */ 533 if (cur_addr < mem_end) { 534 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 535 g_assert(drc); 536 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 537 cur_addr, spapr_drc_index(drc), -1, 0); 538 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 539 nr_entries++; 540 } 541 542 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 543 int_buf = cur_index = g_malloc0(buf_len); 544 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 545 cur_index += sizeof(nr_entries); 546 547 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 548 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 549 cur_index += sizeof(elem->cell); 550 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 551 g_free(elem); 552 } 553 554 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 555 g_free(int_buf); 556 if (ret < 0) { 557 return -1; 558 } 559 return 0; 560 } 561 562 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 563 int offset, MemoryDeviceInfoList *dimms) 564 { 565 MachineState *machine = MACHINE(spapr); 566 int i, ret; 567 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 568 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 569 uint32_t nr_lmbs = (machine->device_memory->base + 570 memory_region_size(&machine->device_memory->mr)) / 571 lmb_size; 572 uint32_t *int_buf, *cur_index, buf_len; 573 574 /* 575 * Allocate enough buffer size to fit in ibm,dynamic-memory 576 */ 577 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 578 cur_index = int_buf = g_malloc0(buf_len); 579 int_buf[0] = cpu_to_be32(nr_lmbs); 580 cur_index++; 581 for (i = 0; i < nr_lmbs; i++) { 582 uint64_t addr = i * lmb_size; 583 uint32_t *dynamic_memory = cur_index; 584 585 if (i >= device_lmb_start) { 586 SpaprDrc *drc; 587 588 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 589 g_assert(drc); 590 591 dynamic_memory[0] = cpu_to_be32(addr >> 32); 592 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 593 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 594 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 595 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 596 if (memory_region_present(get_system_memory(), addr)) { 597 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 598 } else { 599 dynamic_memory[5] = cpu_to_be32(0); 600 } 601 } else { 602 /* 603 * LMB information for RMA, boot time RAM and gap b/n RAM and 604 * device memory region -- all these are marked as reserved 605 * and as having no valid DRC. 606 */ 607 dynamic_memory[0] = cpu_to_be32(addr >> 32); 608 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 609 dynamic_memory[2] = cpu_to_be32(0); 610 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 611 dynamic_memory[4] = cpu_to_be32(-1); 612 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 613 SPAPR_LMB_FLAGS_DRC_INVALID); 614 } 615 616 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 617 } 618 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 619 g_free(int_buf); 620 if (ret < 0) { 621 return -1; 622 } 623 return 0; 624 } 625 626 /* 627 * Adds ibm,dynamic-reconfiguration-memory node. 628 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 629 * of this device tree node. 630 */ 631 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 632 void *fdt) 633 { 634 MachineState *machine = MACHINE(spapr); 635 int ret, offset; 636 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 637 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 638 cpu_to_be32(lmb_size & 0xffffffff)}; 639 MemoryDeviceInfoList *dimms = NULL; 640 641 /* Don't create the node if there is no device memory. */ 642 if (!machine->device_memory) { 643 return 0; 644 } 645 646 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 647 648 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 649 sizeof(prop_lmb_size)); 650 if (ret < 0) { 651 return ret; 652 } 653 654 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 655 if (ret < 0) { 656 return ret; 657 } 658 659 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 660 if (ret < 0) { 661 return ret; 662 } 663 664 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 665 dimms = qmp_memory_device_list(); 666 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 667 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 668 } else { 669 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 670 } 671 qapi_free_MemoryDeviceInfoList(dimms); 672 673 if (ret < 0) { 674 return ret; 675 } 676 677 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 678 679 return ret; 680 } 681 682 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 683 { 684 MachineState *machine = MACHINE(spapr); 685 hwaddr mem_start, node_size; 686 int i, nb_nodes = machine->numa_state->num_nodes; 687 NodeInfo *nodes = machine->numa_state->nodes; 688 689 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 690 if (!nodes[i].node_mem) { 691 continue; 692 } 693 if (mem_start >= machine->ram_size) { 694 node_size = 0; 695 } else { 696 node_size = nodes[i].node_mem; 697 if (node_size > machine->ram_size - mem_start) { 698 node_size = machine->ram_size - mem_start; 699 } 700 } 701 if (!mem_start) { 702 /* spapr_machine_init() checks for rma_size <= node0_size 703 * already */ 704 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 705 mem_start += spapr->rma_size; 706 node_size -= spapr->rma_size; 707 } 708 for ( ; node_size; ) { 709 hwaddr sizetmp = pow2floor(node_size); 710 711 /* mem_start != 0 here */ 712 if (ctzl(mem_start) < ctzl(sizetmp)) { 713 sizetmp = 1ULL << ctzl(mem_start); 714 } 715 716 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 717 node_size -= sizetmp; 718 mem_start += sizetmp; 719 } 720 } 721 722 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 723 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 724 int ret; 725 726 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 727 if (ret) { 728 return ret; 729 } 730 } 731 732 return 0; 733 } 734 735 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 736 SpaprMachineState *spapr) 737 { 738 MachineState *ms = MACHINE(spapr); 739 PowerPCCPU *cpu = POWERPC_CPU(cs); 740 CPUPPCState *env = &cpu->env; 741 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 742 int index = spapr_get_vcpu_id(cpu); 743 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 744 0xffffffff, 0xffffffff}; 745 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 746 : SPAPR_TIMEBASE_FREQ; 747 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 748 uint32_t page_sizes_prop[64]; 749 size_t page_sizes_prop_size; 750 unsigned int smp_threads = ms->smp.threads; 751 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 752 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 753 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 754 SpaprDrc *drc; 755 int drc_index; 756 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 757 int i; 758 759 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 760 if (drc) { 761 drc_index = spapr_drc_index(drc); 762 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 763 } 764 765 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 766 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 767 768 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 769 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 770 env->dcache_line_size))); 771 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 772 env->dcache_line_size))); 773 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 774 env->icache_line_size))); 775 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 776 env->icache_line_size))); 777 778 if (pcc->l1_dcache_size) { 779 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 780 pcc->l1_dcache_size))); 781 } else { 782 warn_report("Unknown L1 dcache size for cpu"); 783 } 784 if (pcc->l1_icache_size) { 785 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 786 pcc->l1_icache_size))); 787 } else { 788 warn_report("Unknown L1 icache size for cpu"); 789 } 790 791 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 792 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 793 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 794 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 795 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 796 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 797 798 if (ppc_has_spr(cpu, SPR_PURR)) { 799 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 800 } 801 if (ppc_has_spr(cpu, SPR_PURR)) { 802 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 803 } 804 805 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 806 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 807 segs, sizeof(segs)))); 808 } 809 810 /* Advertise VSX (vector extensions) if available 811 * 1 == VMX / Altivec available 812 * 2 == VSX available 813 * 814 * Only CPUs for which we create core types in spapr_cpu_core.c 815 * are possible, and all of those have VMX */ 816 if (env->insns_flags & PPC_ALTIVEC) { 817 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 818 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 819 } else { 820 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 821 } 822 } 823 824 /* Advertise DFP (Decimal Floating Point) if available 825 * 0 / no property == no DFP 826 * 1 == DFP available */ 827 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 828 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 829 } 830 831 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 832 sizeof(page_sizes_prop)); 833 if (page_sizes_prop_size) { 834 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 835 page_sizes_prop, page_sizes_prop_size))); 836 } 837 838 spapr_dt_pa_features(spapr, cpu, fdt, offset); 839 840 spapr_dt_pi_features(spapr, cpu, fdt, offset); 841 842 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 843 cs->cpu_index / vcpus_per_socket))); 844 845 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 846 pft_size_prop, sizeof(pft_size_prop)))); 847 848 if (ms->numa_state->num_nodes > 1) { 849 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 850 } 851 852 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 853 854 if (pcc->radix_page_info) { 855 for (i = 0; i < pcc->radix_page_info->count; i++) { 856 radix_AP_encodings[i] = 857 cpu_to_be32(pcc->radix_page_info->entries[i]); 858 } 859 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 860 radix_AP_encodings, 861 pcc->radix_page_info->count * 862 sizeof(radix_AP_encodings[0])))); 863 } 864 865 /* 866 * We set this property to let the guest know that it can use the large 867 * decrementer and its width in bits. 868 */ 869 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 870 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 871 pcc->lrg_decr_bits))); 872 } 873 874 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 875 int cpus_offset) 876 { 877 PowerPCCPU *cpu = POWERPC_CPU(cs); 878 int index = spapr_get_vcpu_id(cpu); 879 DeviceClass *dc = DEVICE_GET_CLASS(cs); 880 g_autofree char *nodename = NULL; 881 int offset; 882 883 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 884 return; 885 } 886 887 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 888 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 889 _FDT(offset); 890 spapr_dt_cpu(cs, fdt, offset, spapr); 891 } 892 893 894 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 895 { 896 CPUState **rev; 897 CPUState *cs; 898 int n_cpus; 899 int cpus_offset; 900 int i; 901 902 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 903 _FDT(cpus_offset); 904 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 905 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 906 907 /* 908 * We walk the CPUs in reverse order to ensure that CPU DT nodes 909 * created by fdt_add_subnode() end up in the right order in FDT 910 * for the guest kernel the enumerate the CPUs correctly. 911 * 912 * The CPU list cannot be traversed in reverse order, so we need 913 * to do extra work. 914 */ 915 n_cpus = 0; 916 rev = NULL; 917 CPU_FOREACH(cs) { 918 rev = g_renew(CPUState *, rev, n_cpus + 1); 919 rev[n_cpus++] = cs; 920 } 921 922 for (i = n_cpus - 1; i >= 0; i--) { 923 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 924 } 925 926 g_free(rev); 927 } 928 929 static int spapr_dt_rng(void *fdt) 930 { 931 int node; 932 int ret; 933 934 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 935 if (node <= 0) { 936 return -1; 937 } 938 ret = fdt_setprop_string(fdt, node, "device_type", 939 "ibm,platform-facilities"); 940 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 941 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 942 943 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 944 if (node <= 0) { 945 return -1; 946 } 947 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 948 949 return ret ? -1 : 0; 950 } 951 952 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 953 { 954 MachineState *ms = MACHINE(spapr); 955 int rtas; 956 GString *hypertas = g_string_sized_new(256); 957 GString *qemu_hypertas = g_string_sized_new(256); 958 uint32_t lrdr_capacity[] = { 959 0, 960 0, 961 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 962 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 963 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 964 }; 965 966 /* Do we have device memory? */ 967 if (MACHINE(spapr)->device_memory) { 968 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 969 memory_region_size(&MACHINE(spapr)->device_memory->mr); 970 971 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 972 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 973 } 974 975 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 976 977 /* hypertas */ 978 add_str(hypertas, "hcall-pft"); 979 add_str(hypertas, "hcall-term"); 980 add_str(hypertas, "hcall-dabr"); 981 add_str(hypertas, "hcall-interrupt"); 982 add_str(hypertas, "hcall-tce"); 983 add_str(hypertas, "hcall-vio"); 984 add_str(hypertas, "hcall-splpar"); 985 add_str(hypertas, "hcall-join"); 986 add_str(hypertas, "hcall-bulk"); 987 add_str(hypertas, "hcall-set-mode"); 988 add_str(hypertas, "hcall-sprg0"); 989 add_str(hypertas, "hcall-copy"); 990 add_str(hypertas, "hcall-debug"); 991 add_str(hypertas, "hcall-vphn"); 992 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 993 add_str(hypertas, "hcall-rpt-invalidate"); 994 } 995 996 add_str(qemu_hypertas, "hcall-memop1"); 997 998 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 999 add_str(hypertas, "hcall-multi-tce"); 1000 } 1001 1002 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1003 add_str(hypertas, "hcall-hpt-resize"); 1004 } 1005 1006 add_str(hypertas, "hcall-watchdog"); 1007 1008 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1009 hypertas->str, hypertas->len)); 1010 g_string_free(hypertas, TRUE); 1011 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1012 qemu_hypertas->str, qemu_hypertas->len)); 1013 g_string_free(qemu_hypertas, TRUE); 1014 1015 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 1016 1017 /* 1018 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 1019 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 1020 * 1021 * The system reset requirements are driven by existing Linux and PowerVM 1022 * implementation which (contrary to PAPR) saves r3 in the error log 1023 * structure like machine check, so Linux expects to find the saved r3 1024 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 1025 * does not look at the error value). 1026 * 1027 * System reset interrupts are not subject to interlock like machine 1028 * check, so this memory area could be corrupted if the sreset is 1029 * interrupted by a machine check (or vice versa) if it was shared. To 1030 * prevent this, system reset uses per-CPU areas for the sreset save 1031 * area. A system reset that interrupts a system reset handler could 1032 * still overwrite this area, but Linux doesn't try to recover in that 1033 * case anyway. 1034 * 1035 * The extra 8 bytes is required because Linux's FWNMI error log check 1036 * is off-by-one. 1037 * 1038 * RTAS_MIN_SIZE is required for the RTAS blob itself. 1039 */ 1040 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 1041 RTAS_ERROR_LOG_MAX + 1042 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 1043 sizeof(uint64_t))); 1044 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1045 RTAS_ERROR_LOG_MAX)); 1046 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1047 RTAS_EVENT_SCAN_RATE)); 1048 1049 g_assert(msi_nonbroken); 1050 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1051 1052 /* 1053 * According to PAPR, rtas ibm,os-term does not guarantee a return 1054 * back to the guest cpu. 1055 * 1056 * While an additional ibm,extended-os-term property indicates 1057 * that rtas call return will always occur. Set this property. 1058 */ 1059 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1060 1061 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1062 lrdr_capacity, sizeof(lrdr_capacity))); 1063 1064 spapr_dt_rtas_tokens(fdt, rtas); 1065 } 1066 1067 /* 1068 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1069 * and the XIVE features that the guest may request and thus the valid 1070 * values for bytes 23..26 of option vector 5: 1071 */ 1072 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1073 int chosen) 1074 { 1075 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1076 1077 char val[2 * 4] = { 1078 23, 0x00, /* XICS / XIVE mode */ 1079 24, 0x00, /* Hash/Radix, filled in below. */ 1080 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1081 26, 0x40, /* Radix options: GTSE == yes. */ 1082 }; 1083 1084 if (spapr->irq->xics && spapr->irq->xive) { 1085 val[1] = SPAPR_OV5_XIVE_BOTH; 1086 } else if (spapr->irq->xive) { 1087 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1088 } else { 1089 assert(spapr->irq->xics); 1090 val[1] = SPAPR_OV5_XIVE_LEGACY; 1091 } 1092 1093 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1094 first_ppc_cpu->compat_pvr)) { 1095 /* 1096 * If we're in a pre POWER9 compat mode then the guest should 1097 * do hash and use the legacy interrupt mode 1098 */ 1099 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1100 val[3] = 0x00; /* Hash */ 1101 spapr_check_mmu_mode(false); 1102 } else if (kvm_enabled()) { 1103 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1104 val[3] = 0x80; /* OV5_MMU_BOTH */ 1105 } else if (kvmppc_has_cap_mmu_radix()) { 1106 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1107 } else { 1108 val[3] = 0x00; /* Hash */ 1109 } 1110 } else { 1111 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1112 val[3] = 0xC0; 1113 } 1114 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1115 val, sizeof(val))); 1116 } 1117 1118 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1119 { 1120 MachineState *machine = MACHINE(spapr); 1121 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1122 int chosen; 1123 1124 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1125 1126 if (reset) { 1127 const char *boot_device = spapr->boot_device; 1128 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1129 size_t cb = 0; 1130 g_autofree char *bootlist = get_boot_devices_list(&cb); 1131 1132 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1133 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1134 machine->kernel_cmdline)); 1135 } 1136 1137 if (spapr->initrd_size) { 1138 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1139 spapr->initrd_base)); 1140 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1141 spapr->initrd_base + spapr->initrd_size)); 1142 } 1143 1144 if (spapr->kernel_size) { 1145 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1146 cpu_to_be64(spapr->kernel_size) }; 1147 1148 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1149 &kprop, sizeof(kprop))); 1150 if (spapr->kernel_le) { 1151 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1152 } 1153 } 1154 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1155 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1156 } 1157 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1158 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1159 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1160 1161 if (cb && bootlist) { 1162 int i; 1163 1164 for (i = 0; i < cb; i++) { 1165 if (bootlist[i] == '\n') { 1166 bootlist[i] = ' '; 1167 } 1168 } 1169 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1170 } 1171 1172 if (boot_device && strlen(boot_device)) { 1173 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1174 } 1175 1176 if (spapr->want_stdout_path && stdout_path) { 1177 /* 1178 * "linux,stdout-path" and "stdout" properties are 1179 * deprecated by linux kernel. New platforms should only 1180 * use the "stdout-path" property. Set the new property 1181 * and continue using older property to remain compatible 1182 * with the existing firmware. 1183 */ 1184 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1185 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1186 } 1187 1188 /* 1189 * We can deal with BAR reallocation just fine, advertise it 1190 * to the guest 1191 */ 1192 if (smc->linux_pci_probe) { 1193 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1194 } 1195 1196 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1197 } 1198 1199 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1200 1201 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1202 } 1203 1204 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1205 { 1206 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1207 * KVM to work under pHyp with some guest co-operation */ 1208 int hypervisor; 1209 uint8_t hypercall[16]; 1210 1211 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1212 /* indicate KVM hypercall interface */ 1213 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1214 if (kvmppc_has_cap_fixup_hcalls()) { 1215 /* 1216 * Older KVM versions with older guest kernels were broken 1217 * with the magic page, don't allow the guest to map it. 1218 */ 1219 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1220 sizeof(hypercall))) { 1221 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1222 hypercall, sizeof(hypercall))); 1223 } 1224 } 1225 } 1226 1227 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1228 { 1229 MachineState *machine = MACHINE(spapr); 1230 MachineClass *mc = MACHINE_GET_CLASS(machine); 1231 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1232 uint32_t root_drc_type_mask = 0; 1233 int ret; 1234 void *fdt; 1235 SpaprPhbState *phb; 1236 char *buf; 1237 1238 fdt = g_malloc0(space); 1239 _FDT((fdt_create_empty_tree(fdt, space))); 1240 1241 /* Root node */ 1242 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1243 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1244 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1245 1246 /* Guest UUID & Name*/ 1247 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1248 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1249 if (qemu_uuid_set) { 1250 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1251 } 1252 g_free(buf); 1253 1254 if (qemu_get_vm_name()) { 1255 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1256 qemu_get_vm_name())); 1257 } 1258 1259 /* Host Model & Serial Number */ 1260 if (spapr->host_model) { 1261 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1262 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1263 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1264 g_free(buf); 1265 } 1266 1267 if (spapr->host_serial) { 1268 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1269 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1270 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1271 g_free(buf); 1272 } 1273 1274 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1275 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1276 1277 /* /interrupt controller */ 1278 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1279 1280 ret = spapr_dt_memory(spapr, fdt); 1281 if (ret < 0) { 1282 error_report("couldn't setup memory nodes in fdt"); 1283 exit(1); 1284 } 1285 1286 /* /vdevice */ 1287 spapr_dt_vdevice(spapr->vio_bus, fdt); 1288 1289 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1290 ret = spapr_dt_rng(fdt); 1291 if (ret < 0) { 1292 error_report("could not set up rng device in the fdt"); 1293 exit(1); 1294 } 1295 } 1296 1297 QLIST_FOREACH(phb, &spapr->phbs, list) { 1298 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1299 if (ret < 0) { 1300 error_report("couldn't setup PCI devices in fdt"); 1301 exit(1); 1302 } 1303 } 1304 1305 spapr_dt_cpus(fdt, spapr); 1306 1307 /* ibm,drc-indexes and friends */ 1308 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1309 if (smc->dr_phb_enabled) { 1310 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1311 } 1312 if (mc->nvdimm_supported) { 1313 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1314 } 1315 if (root_drc_type_mask) { 1316 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1317 } 1318 1319 if (mc->has_hotpluggable_cpus) { 1320 int offset = fdt_path_offset(fdt, "/cpus"); 1321 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1322 if (ret < 0) { 1323 error_report("Couldn't set up CPU DR device tree properties"); 1324 exit(1); 1325 } 1326 } 1327 1328 /* /event-sources */ 1329 spapr_dt_events(spapr, fdt); 1330 1331 /* /rtas */ 1332 spapr_dt_rtas(spapr, fdt); 1333 1334 /* /chosen */ 1335 spapr_dt_chosen(spapr, fdt, reset); 1336 1337 /* /hypervisor */ 1338 if (kvm_enabled()) { 1339 spapr_dt_hypervisor(spapr, fdt); 1340 } 1341 1342 /* Build memory reserve map */ 1343 if (reset) { 1344 if (spapr->kernel_size) { 1345 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1346 spapr->kernel_size))); 1347 } 1348 if (spapr->initrd_size) { 1349 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1350 spapr->initrd_size))); 1351 } 1352 } 1353 1354 /* NVDIMM devices */ 1355 if (mc->nvdimm_supported) { 1356 spapr_dt_persistent_memory(spapr, fdt); 1357 } 1358 1359 return fdt; 1360 } 1361 1362 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1363 { 1364 SpaprMachineState *spapr = opaque; 1365 1366 return (addr & 0x0fffffff) + spapr->kernel_addr; 1367 } 1368 1369 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1370 PowerPCCPU *cpu) 1371 { 1372 CPUPPCState *env = &cpu->env; 1373 1374 /* The TCG path should also be holding the BQL at this point */ 1375 g_assert(bql_locked()); 1376 1377 g_assert(!vhyp_cpu_in_nested(cpu)); 1378 1379 if (FIELD_EX64(env->msr, MSR, PR)) { 1380 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1381 env->gpr[3] = H_PRIVILEGE; 1382 } else { 1383 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1384 } 1385 } 1386 1387 struct LPCRSyncState { 1388 target_ulong value; 1389 target_ulong mask; 1390 }; 1391 1392 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1393 { 1394 struct LPCRSyncState *s = arg.host_ptr; 1395 PowerPCCPU *cpu = POWERPC_CPU(cs); 1396 CPUPPCState *env = &cpu->env; 1397 target_ulong lpcr; 1398 1399 cpu_synchronize_state(cs); 1400 lpcr = env->spr[SPR_LPCR]; 1401 lpcr &= ~s->mask; 1402 lpcr |= s->value; 1403 ppc_store_lpcr(cpu, lpcr); 1404 } 1405 1406 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1407 { 1408 CPUState *cs; 1409 struct LPCRSyncState s = { 1410 .value = value, 1411 .mask = mask 1412 }; 1413 CPU_FOREACH(cs) { 1414 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1415 } 1416 } 1417 1418 /* May be used when the machine is not running */ 1419 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1420 { 1421 CPUState *cs; 1422 CPU_FOREACH(cs) { 1423 PowerPCCPU *cpu = POWERPC_CPU(cs); 1424 CPUPPCState *env = &cpu->env; 1425 target_ulong lpcr; 1426 1427 lpcr = env->spr[SPR_LPCR]; 1428 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1429 ppc_store_lpcr(cpu, lpcr); 1430 } 1431 } 1432 1433 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1434 target_ulong lpid, ppc_v3_pate_t *entry) 1435 { 1436 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1437 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1438 1439 if (!spapr_cpu->in_nested) { 1440 assert(lpid == 0); 1441 1442 /* Copy PATE1:GR into PATE0:HR */ 1443 entry->dw0 = spapr->patb_entry & PATE0_HR; 1444 entry->dw1 = spapr->patb_entry; 1445 return true; 1446 } else { 1447 if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) { 1448 return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); 1449 } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) { 1450 return spapr_get_pate_nested_papr(spapr, cpu, lpid, entry); 1451 } else { 1452 g_assert_not_reached(); 1453 } 1454 } 1455 } 1456 1457 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1458 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1459 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1460 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1461 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1462 1463 /* 1464 * Get the fd to access the kernel htab, re-opening it if necessary 1465 */ 1466 static int get_htab_fd(SpaprMachineState *spapr) 1467 { 1468 Error *local_err = NULL; 1469 1470 if (spapr->htab_fd >= 0) { 1471 return spapr->htab_fd; 1472 } 1473 1474 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1475 if (spapr->htab_fd < 0) { 1476 error_report_err(local_err); 1477 } 1478 1479 return spapr->htab_fd; 1480 } 1481 1482 void close_htab_fd(SpaprMachineState *spapr) 1483 { 1484 if (spapr->htab_fd >= 0) { 1485 close(spapr->htab_fd); 1486 } 1487 spapr->htab_fd = -1; 1488 } 1489 1490 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1491 { 1492 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1493 1494 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1495 } 1496 1497 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1498 { 1499 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1500 1501 assert(kvm_enabled()); 1502 1503 if (!spapr->htab) { 1504 return 0; 1505 } 1506 1507 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1508 } 1509 1510 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1511 hwaddr ptex, int n) 1512 { 1513 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1514 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1515 1516 if (!spapr->htab) { 1517 /* 1518 * HTAB is controlled by KVM. Fetch into temporary buffer 1519 */ 1520 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1521 kvmppc_read_hptes(hptes, ptex, n); 1522 return hptes; 1523 } 1524 1525 /* 1526 * HTAB is controlled by QEMU. Just point to the internally 1527 * accessible PTEG. 1528 */ 1529 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1530 } 1531 1532 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1533 const ppc_hash_pte64_t *hptes, 1534 hwaddr ptex, int n) 1535 { 1536 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1537 1538 if (!spapr->htab) { 1539 g_free((void *)hptes); 1540 } 1541 1542 /* Nothing to do for qemu managed HPT */ 1543 } 1544 1545 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1546 uint64_t pte0, uint64_t pte1) 1547 { 1548 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1549 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1550 1551 if (!spapr->htab) { 1552 kvmppc_write_hpte(ptex, pte0, pte1); 1553 } else { 1554 if (pte0 & HPTE64_V_VALID) { 1555 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1556 /* 1557 * When setting valid, we write PTE1 first. This ensures 1558 * proper synchronization with the reading code in 1559 * ppc_hash64_pteg_search() 1560 */ 1561 smp_wmb(); 1562 stq_p(spapr->htab + offset, pte0); 1563 } else { 1564 stq_p(spapr->htab + offset, pte0); 1565 /* 1566 * When clearing it we set PTE0 first. This ensures proper 1567 * synchronization with the reading code in 1568 * ppc_hash64_pteg_search() 1569 */ 1570 smp_wmb(); 1571 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1572 } 1573 } 1574 } 1575 1576 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1577 uint64_t pte1) 1578 { 1579 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1580 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1581 1582 if (!spapr->htab) { 1583 /* There should always be a hash table when this is called */ 1584 error_report("spapr_hpte_set_c called with no hash table !"); 1585 return; 1586 } 1587 1588 /* The HW performs a non-atomic byte update */ 1589 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1590 } 1591 1592 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1593 uint64_t pte1) 1594 { 1595 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1596 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1597 1598 if (!spapr->htab) { 1599 /* There should always be a hash table when this is called */ 1600 error_report("spapr_hpte_set_r called with no hash table !"); 1601 return; 1602 } 1603 1604 /* The HW performs a non-atomic byte update */ 1605 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1606 } 1607 1608 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1609 { 1610 int shift; 1611 1612 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1613 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1614 * that's much more than is needed for Linux guests */ 1615 shift = ctz64(pow2ceil(ramsize)) - 7; 1616 shift = MAX(shift, 18); /* Minimum architected size */ 1617 shift = MIN(shift, 46); /* Maximum architected size */ 1618 return shift; 1619 } 1620 1621 void spapr_free_hpt(SpaprMachineState *spapr) 1622 { 1623 qemu_vfree(spapr->htab); 1624 spapr->htab = NULL; 1625 spapr->htab_shift = 0; 1626 close_htab_fd(spapr); 1627 } 1628 1629 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1630 { 1631 ERRP_GUARD(); 1632 long rc; 1633 1634 /* Clean up any HPT info from a previous boot */ 1635 spapr_free_hpt(spapr); 1636 1637 rc = kvmppc_reset_htab(shift); 1638 1639 if (rc == -EOPNOTSUPP) { 1640 error_setg(errp, "HPT not supported in nested guests"); 1641 return -EOPNOTSUPP; 1642 } 1643 1644 if (rc < 0) { 1645 /* kernel-side HPT needed, but couldn't allocate one */ 1646 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1647 shift); 1648 error_append_hint(errp, "Try smaller maxmem?\n"); 1649 return -errno; 1650 } else if (rc > 0) { 1651 /* kernel-side HPT allocated */ 1652 if (rc != shift) { 1653 error_setg(errp, 1654 "Requested order %d HPT, but kernel allocated order %ld", 1655 shift, rc); 1656 error_append_hint(errp, "Try smaller maxmem?\n"); 1657 return -ENOSPC; 1658 } 1659 1660 spapr->htab_shift = shift; 1661 spapr->htab = NULL; 1662 } else { 1663 /* kernel-side HPT not needed, allocate in userspace instead */ 1664 size_t size = 1ULL << shift; 1665 int i; 1666 1667 spapr->htab = qemu_memalign(size, size); 1668 memset(spapr->htab, 0, size); 1669 spapr->htab_shift = shift; 1670 1671 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1672 DIRTY_HPTE(HPTE(spapr->htab, i)); 1673 } 1674 } 1675 /* We're setting up a hash table, so that means we're not radix */ 1676 spapr->patb_entry = 0; 1677 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1678 return 0; 1679 } 1680 1681 void spapr_setup_hpt(SpaprMachineState *spapr) 1682 { 1683 int hpt_shift; 1684 1685 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1686 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1687 } else { 1688 uint64_t current_ram_size; 1689 1690 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1691 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1692 } 1693 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1694 1695 if (kvm_enabled()) { 1696 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1697 1698 /* Check our RMA fits in the possible VRMA */ 1699 if (vrma_limit < spapr->rma_size) { 1700 error_report("Unable to create %" HWADDR_PRIu 1701 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1702 spapr->rma_size / MiB, vrma_limit / MiB); 1703 exit(EXIT_FAILURE); 1704 } 1705 } 1706 } 1707 1708 void spapr_check_mmu_mode(bool guest_radix) 1709 { 1710 if (guest_radix) { 1711 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1712 error_report("Guest requested unavailable MMU mode (radix)."); 1713 exit(EXIT_FAILURE); 1714 } 1715 } else { 1716 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1717 && !kvmppc_has_cap_mmu_hash_v3()) { 1718 error_report("Guest requested unavailable MMU mode (hash)."); 1719 exit(EXIT_FAILURE); 1720 } 1721 } 1722 } 1723 1724 static void spapr_machine_reset(MachineState *machine, ResetType type) 1725 { 1726 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1727 PowerPCCPU *first_ppc_cpu; 1728 hwaddr fdt_addr; 1729 void *fdt; 1730 int rc; 1731 1732 if (type != RESET_TYPE_SNAPSHOT_LOAD) { 1733 /* 1734 * Record-replay snapshot load must not consume random, this was 1735 * already replayed from initial machine reset. 1736 */ 1737 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1738 } 1739 1740 if (machine->cgs) { 1741 confidential_guest_kvm_reset(machine->cgs, &error_fatal); 1742 } 1743 spapr_caps_apply(spapr); 1744 spapr_nested_reset(spapr); 1745 1746 first_ppc_cpu = POWERPC_CPU(first_cpu); 1747 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1748 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1749 spapr->max_compat_pvr)) { 1750 /* 1751 * If using KVM with radix mode available, VCPUs can be started 1752 * without a HPT because KVM will start them in radix mode. 1753 * Set the GR bit in PATE so that we know there is no HPT. 1754 */ 1755 spapr->patb_entry = PATE1_GR; 1756 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1757 } else { 1758 spapr_setup_hpt(spapr); 1759 } 1760 1761 qemu_devices_reset(type); 1762 1763 spapr_ovec_cleanup(spapr->ov5_cas); 1764 spapr->ov5_cas = spapr_ovec_new(); 1765 1766 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1767 1768 /* 1769 * This is fixing some of the default configuration of the XIVE 1770 * devices. To be called after the reset of the machine devices. 1771 */ 1772 spapr_irq_reset(spapr, &error_fatal); 1773 1774 /* 1775 * There is no CAS under qtest. Simulate one to please the code that 1776 * depends on spapr->ov5_cas. This is especially needed to test device 1777 * unplug, so we do that before resetting the DRCs. 1778 */ 1779 if (qtest_enabled()) { 1780 spapr_ovec_cleanup(spapr->ov5_cas); 1781 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1782 } 1783 1784 spapr_nvdimm_finish_flushes(); 1785 1786 /* DRC reset may cause a device to be unplugged. This will cause troubles 1787 * if this device is used by another device (eg, a running vhost backend 1788 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1789 * situations, we reset DRCs after all devices have been reset. 1790 */ 1791 spapr_drc_reset_all(spapr); 1792 1793 spapr_clear_pending_events(spapr); 1794 1795 /* 1796 * We place the device tree just below either the top of the RMA, 1797 * or just below 2GB, whichever is lower, so that it can be 1798 * processed with 32-bit real mode code if necessary 1799 */ 1800 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1801 1802 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1803 if (spapr->vof) { 1804 spapr_vof_reset(spapr, fdt, &error_fatal); 1805 /* 1806 * Do not pack the FDT as the client may change properties. 1807 * VOF client does not expect the FDT so we do not load it to the VM. 1808 */ 1809 } else { 1810 rc = fdt_pack(fdt); 1811 /* Should only fail if we've built a corrupted tree */ 1812 assert(rc == 0); 1813 1814 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1815 0, fdt_addr, 0); 1816 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1817 } 1818 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1819 1820 g_free(spapr->fdt_blob); 1821 spapr->fdt_size = fdt_totalsize(fdt); 1822 spapr->fdt_initial_size = spapr->fdt_size; 1823 spapr->fdt_blob = fdt; 1824 1825 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1826 machine->fdt = fdt; 1827 1828 /* Set up the entry state */ 1829 first_ppc_cpu->env.gpr[5] = 0; 1830 1831 spapr->fwnmi_system_reset_addr = -1; 1832 spapr->fwnmi_machine_check_addr = -1; 1833 spapr->fwnmi_machine_check_interlock = -1; 1834 1835 /* Signal all vCPUs waiting on this condition */ 1836 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1837 1838 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1839 } 1840 1841 static void spapr_create_nvram(SpaprMachineState *spapr) 1842 { 1843 DeviceState *dev = qdev_new("spapr-nvram"); 1844 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1845 1846 if (dinfo) { 1847 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1848 &error_fatal); 1849 } 1850 1851 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1852 1853 spapr->nvram = (struct SpaprNvram *)dev; 1854 } 1855 1856 static void spapr_rtc_create(SpaprMachineState *spapr) 1857 { 1858 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1859 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1860 &error_fatal, NULL); 1861 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1862 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1863 "date"); 1864 } 1865 1866 /* Returns whether we want to use VGA or not */ 1867 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1868 { 1869 vga_interface_created = true; 1870 switch (vga_interface_type) { 1871 case VGA_NONE: 1872 return false; 1873 case VGA_DEVICE: 1874 return true; 1875 case VGA_STD: 1876 case VGA_VIRTIO: 1877 case VGA_CIRRUS: 1878 return pci_vga_init(pci_bus) != NULL; 1879 default: 1880 error_setg(errp, 1881 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1882 return false; 1883 } 1884 } 1885 1886 static int spapr_pre_load(void *opaque) 1887 { 1888 int rc; 1889 1890 rc = spapr_caps_pre_load(opaque); 1891 if (rc) { 1892 return rc; 1893 } 1894 1895 return 0; 1896 } 1897 1898 static int spapr_post_load(void *opaque, int version_id) 1899 { 1900 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1901 int err = 0; 1902 1903 err = spapr_caps_post_migration(spapr); 1904 if (err) { 1905 return err; 1906 } 1907 1908 /* 1909 * In earlier versions, there was no separate qdev for the PAPR 1910 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1911 * So when migrating from those versions, poke the incoming offset 1912 * value into the RTC device 1913 */ 1914 if (version_id < 3) { 1915 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1916 if (err) { 1917 return err; 1918 } 1919 } 1920 1921 if (kvm_enabled() && spapr->patb_entry) { 1922 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1923 bool radix = !!(spapr->patb_entry & PATE1_GR); 1924 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1925 1926 /* 1927 * Update LPCR:HR and UPRT as they may not be set properly in 1928 * the stream 1929 */ 1930 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1931 LPCR_HR | LPCR_UPRT); 1932 1933 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1934 if (err) { 1935 error_report("Process table config unsupported by the host"); 1936 return -EINVAL; 1937 } 1938 } 1939 1940 err = spapr_irq_post_load(spapr, version_id); 1941 if (err) { 1942 return err; 1943 } 1944 1945 return err; 1946 } 1947 1948 static int spapr_pre_save(void *opaque) 1949 { 1950 int rc; 1951 1952 rc = spapr_caps_pre_save(opaque); 1953 if (rc) { 1954 return rc; 1955 } 1956 1957 return 0; 1958 } 1959 1960 static bool version_before_3(void *opaque, int version_id) 1961 { 1962 return version_id < 3; 1963 } 1964 1965 static bool spapr_pending_events_needed(void *opaque) 1966 { 1967 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1968 return !QTAILQ_EMPTY(&spapr->pending_events); 1969 } 1970 1971 static const VMStateDescription vmstate_spapr_event_entry = { 1972 .name = "spapr_event_log_entry", 1973 .version_id = 1, 1974 .minimum_version_id = 1, 1975 .fields = (const VMStateField[]) { 1976 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1977 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1978 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1979 NULL, extended_length), 1980 VMSTATE_END_OF_LIST() 1981 }, 1982 }; 1983 1984 static const VMStateDescription vmstate_spapr_pending_events = { 1985 .name = "spapr_pending_events", 1986 .version_id = 1, 1987 .minimum_version_id = 1, 1988 .needed = spapr_pending_events_needed, 1989 .fields = (const VMStateField[]) { 1990 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1991 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1992 VMSTATE_END_OF_LIST() 1993 }, 1994 }; 1995 1996 static bool spapr_ov5_cas_needed(void *opaque) 1997 { 1998 SpaprMachineState *spapr = opaque; 1999 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 2000 bool cas_needed; 2001 2002 /* Prior to the introduction of SpaprOptionVector, we had two option 2003 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 2004 * Both of these options encode machine topology into the device-tree 2005 * in such a way that the now-booted OS should still be able to interact 2006 * appropriately with QEMU regardless of what options were actually 2007 * negotiatied on the source side. 2008 * 2009 * As such, we can avoid migrating the CAS-negotiated options if these 2010 * are the only options available on the current machine/platform. 2011 * Since these are the only options available for pseries-2.7 and 2012 * earlier, this allows us to maintain old->new/new->old migration 2013 * compatibility. 2014 * 2015 * For QEMU 2.8+, there are additional CAS-negotiatable options available 2016 * via default pseries-2.8 machines and explicit command-line parameters. 2017 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 2018 * of the actual CAS-negotiated values to continue working properly. For 2019 * example, availability of memory unplug depends on knowing whether 2020 * OV5_HP_EVT was negotiated via CAS. 2021 * 2022 * Thus, for any cases where the set of available CAS-negotiatable 2023 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 2024 * include the CAS-negotiated options in the migration stream, unless 2025 * if they affect boot time behaviour only. 2026 */ 2027 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 2028 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 2029 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 2030 2031 /* We need extra information if we have any bits outside the mask 2032 * defined above */ 2033 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 2034 2035 spapr_ovec_cleanup(ov5_mask); 2036 2037 return cas_needed; 2038 } 2039 2040 static const VMStateDescription vmstate_spapr_ov5_cas = { 2041 .name = "spapr_option_vector_ov5_cas", 2042 .version_id = 1, 2043 .minimum_version_id = 1, 2044 .needed = spapr_ov5_cas_needed, 2045 .fields = (const VMStateField[]) { 2046 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 2047 vmstate_spapr_ovec, SpaprOptionVector), 2048 VMSTATE_END_OF_LIST() 2049 }, 2050 }; 2051 2052 static bool spapr_patb_entry_needed(void *opaque) 2053 { 2054 SpaprMachineState *spapr = opaque; 2055 2056 return !!spapr->patb_entry; 2057 } 2058 2059 static const VMStateDescription vmstate_spapr_patb_entry = { 2060 .name = "spapr_patb_entry", 2061 .version_id = 1, 2062 .minimum_version_id = 1, 2063 .needed = spapr_patb_entry_needed, 2064 .fields = (const VMStateField[]) { 2065 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2066 VMSTATE_END_OF_LIST() 2067 }, 2068 }; 2069 2070 static bool spapr_irq_map_needed(void *opaque) 2071 { 2072 SpaprMachineState *spapr = opaque; 2073 2074 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2075 } 2076 2077 static const VMStateDescription vmstate_spapr_irq_map = { 2078 .name = "spapr_irq_map", 2079 .version_id = 1, 2080 .minimum_version_id = 1, 2081 .needed = spapr_irq_map_needed, 2082 .fields = (const VMStateField[]) { 2083 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2084 VMSTATE_END_OF_LIST() 2085 }, 2086 }; 2087 2088 static bool spapr_dtb_needed(void *opaque) 2089 { 2090 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2091 2092 return smc->update_dt_enabled; 2093 } 2094 2095 static int spapr_dtb_pre_load(void *opaque) 2096 { 2097 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2098 2099 g_free(spapr->fdt_blob); 2100 spapr->fdt_blob = NULL; 2101 spapr->fdt_size = 0; 2102 2103 return 0; 2104 } 2105 2106 static const VMStateDescription vmstate_spapr_dtb = { 2107 .name = "spapr_dtb", 2108 .version_id = 1, 2109 .minimum_version_id = 1, 2110 .needed = spapr_dtb_needed, 2111 .pre_load = spapr_dtb_pre_load, 2112 .fields = (const VMStateField[]) { 2113 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2114 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2115 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2116 fdt_size), 2117 VMSTATE_END_OF_LIST() 2118 }, 2119 }; 2120 2121 static bool spapr_fwnmi_needed(void *opaque) 2122 { 2123 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2124 2125 return spapr->fwnmi_machine_check_addr != -1; 2126 } 2127 2128 static int spapr_fwnmi_pre_save(void *opaque) 2129 { 2130 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2131 2132 /* 2133 * Check if machine check handling is in progress and print a 2134 * warning message. 2135 */ 2136 if (spapr->fwnmi_machine_check_interlock != -1) { 2137 warn_report("A machine check is being handled during migration. The" 2138 "handler may run and log hardware error on the destination"); 2139 } 2140 2141 return 0; 2142 } 2143 2144 static const VMStateDescription vmstate_spapr_fwnmi = { 2145 .name = "spapr_fwnmi", 2146 .version_id = 1, 2147 .minimum_version_id = 1, 2148 .needed = spapr_fwnmi_needed, 2149 .pre_save = spapr_fwnmi_pre_save, 2150 .fields = (const VMStateField[]) { 2151 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2152 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2153 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2154 VMSTATE_END_OF_LIST() 2155 }, 2156 }; 2157 2158 static const VMStateDescription vmstate_spapr = { 2159 .name = "spapr", 2160 .version_id = 3, 2161 .minimum_version_id = 1, 2162 .pre_load = spapr_pre_load, 2163 .post_load = spapr_post_load, 2164 .pre_save = spapr_pre_save, 2165 .fields = (const VMStateField[]) { 2166 /* used to be @next_irq */ 2167 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2168 2169 /* RTC offset */ 2170 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2171 2172 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2173 VMSTATE_END_OF_LIST() 2174 }, 2175 .subsections = (const VMStateDescription * const []) { 2176 &vmstate_spapr_ov5_cas, 2177 &vmstate_spapr_patb_entry, 2178 &vmstate_spapr_pending_events, 2179 &vmstate_spapr_cap_htm, 2180 &vmstate_spapr_cap_vsx, 2181 &vmstate_spapr_cap_dfp, 2182 &vmstate_spapr_cap_cfpc, 2183 &vmstate_spapr_cap_sbbc, 2184 &vmstate_spapr_cap_ibs, 2185 &vmstate_spapr_cap_hpt_maxpagesize, 2186 &vmstate_spapr_irq_map, 2187 &vmstate_spapr_cap_nested_kvm_hv, 2188 &vmstate_spapr_dtb, 2189 &vmstate_spapr_cap_large_decr, 2190 &vmstate_spapr_cap_ccf_assist, 2191 &vmstate_spapr_cap_fwnmi, 2192 &vmstate_spapr_fwnmi, 2193 &vmstate_spapr_cap_rpt_invalidate, 2194 &vmstate_spapr_cap_ail_mode_3, 2195 &vmstate_spapr_cap_nested_papr, 2196 NULL 2197 } 2198 }; 2199 2200 static int htab_save_setup(QEMUFile *f, void *opaque, Error **errp) 2201 { 2202 SpaprMachineState *spapr = opaque; 2203 2204 /* "Iteration" header */ 2205 if (!spapr->htab_shift) { 2206 qemu_put_be32(f, -1); 2207 } else { 2208 qemu_put_be32(f, spapr->htab_shift); 2209 } 2210 2211 if (spapr->htab) { 2212 spapr->htab_save_index = 0; 2213 spapr->htab_first_pass = true; 2214 } else { 2215 if (spapr->htab_shift) { 2216 assert(kvm_enabled()); 2217 } 2218 } 2219 2220 2221 return 0; 2222 } 2223 2224 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2225 int chunkstart, int n_valid, int n_invalid) 2226 { 2227 qemu_put_be32(f, chunkstart); 2228 qemu_put_be16(f, n_valid); 2229 qemu_put_be16(f, n_invalid); 2230 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2231 HASH_PTE_SIZE_64 * n_valid); 2232 } 2233 2234 static void htab_save_end_marker(QEMUFile *f) 2235 { 2236 qemu_put_be32(f, 0); 2237 qemu_put_be16(f, 0); 2238 qemu_put_be16(f, 0); 2239 } 2240 2241 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2242 int64_t max_ns) 2243 { 2244 bool has_timeout = max_ns != -1; 2245 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2246 int index = spapr->htab_save_index; 2247 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2248 2249 assert(spapr->htab_first_pass); 2250 2251 do { 2252 int chunkstart; 2253 2254 /* Consume invalid HPTEs */ 2255 while ((index < htabslots) 2256 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2257 CLEAN_HPTE(HPTE(spapr->htab, index)); 2258 index++; 2259 } 2260 2261 /* Consume valid HPTEs */ 2262 chunkstart = index; 2263 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2264 && HPTE_VALID(HPTE(spapr->htab, index))) { 2265 CLEAN_HPTE(HPTE(spapr->htab, index)); 2266 index++; 2267 } 2268 2269 if (index > chunkstart) { 2270 int n_valid = index - chunkstart; 2271 2272 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2273 2274 if (has_timeout && 2275 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2276 break; 2277 } 2278 } 2279 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2280 2281 if (index >= htabslots) { 2282 assert(index == htabslots); 2283 index = 0; 2284 spapr->htab_first_pass = false; 2285 } 2286 spapr->htab_save_index = index; 2287 } 2288 2289 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2290 int64_t max_ns) 2291 { 2292 bool final = max_ns < 0; 2293 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2294 int examined = 0, sent = 0; 2295 int index = spapr->htab_save_index; 2296 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2297 2298 assert(!spapr->htab_first_pass); 2299 2300 do { 2301 int chunkstart, invalidstart; 2302 2303 /* Consume non-dirty HPTEs */ 2304 while ((index < htabslots) 2305 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2306 index++; 2307 examined++; 2308 } 2309 2310 chunkstart = index; 2311 /* Consume valid dirty HPTEs */ 2312 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2313 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2314 && HPTE_VALID(HPTE(spapr->htab, index))) { 2315 CLEAN_HPTE(HPTE(spapr->htab, index)); 2316 index++; 2317 examined++; 2318 } 2319 2320 invalidstart = index; 2321 /* Consume invalid dirty HPTEs */ 2322 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2323 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2324 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2325 CLEAN_HPTE(HPTE(spapr->htab, index)); 2326 index++; 2327 examined++; 2328 } 2329 2330 if (index > chunkstart) { 2331 int n_valid = invalidstart - chunkstart; 2332 int n_invalid = index - invalidstart; 2333 2334 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2335 sent += index - chunkstart; 2336 2337 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2338 break; 2339 } 2340 } 2341 2342 if (examined >= htabslots) { 2343 break; 2344 } 2345 2346 if (index >= htabslots) { 2347 assert(index == htabslots); 2348 index = 0; 2349 } 2350 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2351 2352 if (index >= htabslots) { 2353 assert(index == htabslots); 2354 index = 0; 2355 } 2356 2357 spapr->htab_save_index = index; 2358 2359 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2360 } 2361 2362 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2363 #define MAX_KVM_BUF_SIZE 2048 2364 2365 static int htab_save_iterate(QEMUFile *f, void *opaque) 2366 { 2367 SpaprMachineState *spapr = opaque; 2368 int fd; 2369 int rc = 0; 2370 2371 /* Iteration header */ 2372 if (!spapr->htab_shift) { 2373 qemu_put_be32(f, -1); 2374 return 1; 2375 } else { 2376 qemu_put_be32(f, 0); 2377 } 2378 2379 if (!spapr->htab) { 2380 assert(kvm_enabled()); 2381 2382 fd = get_htab_fd(spapr); 2383 if (fd < 0) { 2384 return fd; 2385 } 2386 2387 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2388 if (rc < 0) { 2389 return rc; 2390 } 2391 } else if (spapr->htab_first_pass) { 2392 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2393 } else { 2394 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2395 } 2396 2397 htab_save_end_marker(f); 2398 2399 return rc; 2400 } 2401 2402 static int htab_save_complete(QEMUFile *f, void *opaque) 2403 { 2404 SpaprMachineState *spapr = opaque; 2405 int fd; 2406 2407 /* Iteration header */ 2408 if (!spapr->htab_shift) { 2409 qemu_put_be32(f, -1); 2410 return 0; 2411 } else { 2412 qemu_put_be32(f, 0); 2413 } 2414 2415 if (!spapr->htab) { 2416 int rc; 2417 2418 assert(kvm_enabled()); 2419 2420 fd = get_htab_fd(spapr); 2421 if (fd < 0) { 2422 return fd; 2423 } 2424 2425 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2426 if (rc < 0) { 2427 return rc; 2428 } 2429 } else { 2430 if (spapr->htab_first_pass) { 2431 htab_save_first_pass(f, spapr, -1); 2432 } 2433 htab_save_later_pass(f, spapr, -1); 2434 } 2435 2436 /* End marker */ 2437 htab_save_end_marker(f); 2438 2439 return 0; 2440 } 2441 2442 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2443 { 2444 SpaprMachineState *spapr = opaque; 2445 uint32_t section_hdr; 2446 int fd = -1; 2447 Error *local_err = NULL; 2448 2449 if (version_id < 1 || version_id > 1) { 2450 error_report("htab_load() bad version"); 2451 return -EINVAL; 2452 } 2453 2454 section_hdr = qemu_get_be32(f); 2455 2456 if (section_hdr == -1) { 2457 spapr_free_hpt(spapr); 2458 return 0; 2459 } 2460 2461 if (section_hdr) { 2462 int ret; 2463 2464 /* First section gives the htab size */ 2465 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2466 if (ret < 0) { 2467 error_report_err(local_err); 2468 return ret; 2469 } 2470 return 0; 2471 } 2472 2473 if (!spapr->htab) { 2474 assert(kvm_enabled()); 2475 2476 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2477 if (fd < 0) { 2478 error_report_err(local_err); 2479 return fd; 2480 } 2481 } 2482 2483 while (true) { 2484 uint32_t index; 2485 uint16_t n_valid, n_invalid; 2486 2487 index = qemu_get_be32(f); 2488 n_valid = qemu_get_be16(f); 2489 n_invalid = qemu_get_be16(f); 2490 2491 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2492 /* End of Stream */ 2493 break; 2494 } 2495 2496 if ((index + n_valid + n_invalid) > 2497 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2498 /* Bad index in stream */ 2499 error_report( 2500 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2501 index, n_valid, n_invalid, spapr->htab_shift); 2502 return -EINVAL; 2503 } 2504 2505 if (spapr->htab) { 2506 if (n_valid) { 2507 qemu_get_buffer(f, HPTE(spapr->htab, index), 2508 HASH_PTE_SIZE_64 * n_valid); 2509 } 2510 if (n_invalid) { 2511 memset(HPTE(spapr->htab, index + n_valid), 0, 2512 HASH_PTE_SIZE_64 * n_invalid); 2513 } 2514 } else { 2515 int rc; 2516 2517 assert(fd >= 0); 2518 2519 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2520 &local_err); 2521 if (rc < 0) { 2522 error_report_err(local_err); 2523 return rc; 2524 } 2525 } 2526 } 2527 2528 if (!spapr->htab) { 2529 assert(fd >= 0); 2530 close(fd); 2531 } 2532 2533 return 0; 2534 } 2535 2536 static void htab_save_cleanup(void *opaque) 2537 { 2538 SpaprMachineState *spapr = opaque; 2539 2540 close_htab_fd(spapr); 2541 } 2542 2543 static SaveVMHandlers savevm_htab_handlers = { 2544 .save_setup = htab_save_setup, 2545 .save_live_iterate = htab_save_iterate, 2546 .save_live_complete_precopy = htab_save_complete, 2547 .save_cleanup = htab_save_cleanup, 2548 .load_state = htab_load, 2549 }; 2550 2551 static void spapr_boot_set(void *opaque, const char *boot_device, 2552 Error **errp) 2553 { 2554 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2555 2556 g_free(spapr->boot_device); 2557 spapr->boot_device = g_strdup(boot_device); 2558 } 2559 2560 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2561 { 2562 MachineState *machine = MACHINE(spapr); 2563 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2564 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2565 int i; 2566 2567 g_assert(!nr_lmbs || machine->device_memory); 2568 for (i = 0; i < nr_lmbs; i++) { 2569 uint64_t addr; 2570 2571 addr = i * lmb_size + machine->device_memory->base; 2572 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2573 addr / lmb_size); 2574 } 2575 } 2576 2577 /* 2578 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2579 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2580 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2581 */ 2582 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2583 { 2584 int i; 2585 2586 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2587 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2588 " is not aligned to %" PRIu64 " MiB", 2589 machine->ram_size, 2590 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2591 return; 2592 } 2593 2594 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2595 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2596 " is not aligned to %" PRIu64 " MiB", 2597 machine->ram_size, 2598 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2599 return; 2600 } 2601 2602 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2603 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2604 error_setg(errp, 2605 "Node %d memory size 0x%" PRIx64 2606 " is not aligned to %" PRIu64 " MiB", 2607 i, machine->numa_state->nodes[i].node_mem, 2608 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2609 return; 2610 } 2611 } 2612 } 2613 2614 /* find cpu slot in machine->possible_cpus by core_id */ 2615 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2616 { 2617 int index = id / ms->smp.threads; 2618 2619 if (index >= ms->possible_cpus->len) { 2620 return NULL; 2621 } 2622 if (idx) { 2623 *idx = index; 2624 } 2625 return &ms->possible_cpus->cpus[index]; 2626 } 2627 2628 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2629 { 2630 MachineState *ms = MACHINE(spapr); 2631 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2632 Error *local_err = NULL; 2633 bool vsmt_user = !!spapr->vsmt; 2634 int kvm_smt = kvmppc_smt_threads(); 2635 int ret; 2636 unsigned int smp_threads = ms->smp.threads; 2637 2638 if (tcg_enabled()) { 2639 if (smp_threads > 1 && 2640 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2641 spapr->max_compat_pvr)) { 2642 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2643 return; 2644 } 2645 2646 if (smp_threads > 8) { 2647 error_setg(errp, "TCG cannot support more than 8 threads/core " 2648 "on a pseries machine"); 2649 return; 2650 } 2651 } 2652 if (!is_power_of_2(smp_threads)) { 2653 error_setg(errp, "Cannot support %d threads/core on a pseries " 2654 "machine because it must be a power of 2", smp_threads); 2655 return; 2656 } 2657 2658 /* Determine the VSMT mode to use: */ 2659 if (vsmt_user) { 2660 if (spapr->vsmt < smp_threads) { 2661 error_setg(errp, "Cannot support VSMT mode %d" 2662 " because it must be >= threads/core (%d)", 2663 spapr->vsmt, smp_threads); 2664 return; 2665 } 2666 /* In this case, spapr->vsmt has been set by the command line */ 2667 } else if (!smc->smp_threads_vsmt) { 2668 /* 2669 * Default VSMT value is tricky, because we need it to be as 2670 * consistent as possible (for migration), but this requires 2671 * changing it for at least some existing cases. We pick 8 as 2672 * the value that we'd get with KVM on POWER8, the 2673 * overwhelmingly common case in production systems. 2674 */ 2675 spapr->vsmt = MAX(8, smp_threads); 2676 } else { 2677 spapr->vsmt = smp_threads; 2678 } 2679 2680 /* KVM: If necessary, set the SMT mode: */ 2681 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2682 ret = kvmppc_set_smt_threads(spapr->vsmt); 2683 if (ret) { 2684 /* Looks like KVM isn't able to change VSMT mode */ 2685 error_setg(&local_err, 2686 "Failed to set KVM's VSMT mode to %d (errno %d)", 2687 spapr->vsmt, ret); 2688 /* We can live with that if the default one is big enough 2689 * for the number of threads, and a submultiple of the one 2690 * we want. In this case we'll waste some vcpu ids, but 2691 * behaviour will be correct */ 2692 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2693 warn_report_err(local_err); 2694 } else { 2695 if (!vsmt_user) { 2696 error_append_hint(&local_err, 2697 "On PPC, a VM with %d threads/core" 2698 " on a host with %d threads/core" 2699 " requires the use of VSMT mode %d.\n", 2700 smp_threads, kvm_smt, spapr->vsmt); 2701 } 2702 kvmppc_error_append_smt_possible_hint(&local_err); 2703 error_propagate(errp, local_err); 2704 } 2705 } 2706 } 2707 /* else TCG: nothing to do currently */ 2708 } 2709 2710 static void spapr_init_cpus(SpaprMachineState *spapr) 2711 { 2712 MachineState *machine = MACHINE(spapr); 2713 MachineClass *mc = MACHINE_GET_CLASS(machine); 2714 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2715 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2716 const CPUArchIdList *possible_cpus; 2717 unsigned int smp_cpus = machine->smp.cpus; 2718 unsigned int smp_threads = machine->smp.threads; 2719 unsigned int max_cpus = machine->smp.max_cpus; 2720 int boot_cores_nr = smp_cpus / smp_threads; 2721 int i; 2722 2723 possible_cpus = mc->possible_cpu_arch_ids(machine); 2724 if (mc->has_hotpluggable_cpus) { 2725 if (smp_cpus % smp_threads) { 2726 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2727 smp_cpus, smp_threads); 2728 exit(1); 2729 } 2730 if (max_cpus % smp_threads) { 2731 error_report("max_cpus (%u) must be multiple of threads (%u)", 2732 max_cpus, smp_threads); 2733 exit(1); 2734 } 2735 } else { 2736 if (max_cpus != smp_cpus) { 2737 error_report("This machine version does not support CPU hotplug"); 2738 exit(1); 2739 } 2740 boot_cores_nr = possible_cpus->len; 2741 } 2742 2743 if (smc->pre_2_10_has_unused_icps) { 2744 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2745 /* Dummy entries get deregistered when real ICPState objects 2746 * are registered during CPU core hotplug. 2747 */ 2748 pre_2_10_vmstate_register_dummy_icp(i); 2749 } 2750 } 2751 2752 for (i = 0; i < possible_cpus->len; i++) { 2753 int core_id = i * smp_threads; 2754 2755 if (mc->has_hotpluggable_cpus) { 2756 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2757 spapr_vcpu_id(spapr, core_id)); 2758 } 2759 2760 if (i < boot_cores_nr) { 2761 Object *core = object_new(type); 2762 int nr_threads = smp_threads; 2763 2764 /* Handle the partially filled core for older machine types */ 2765 if ((i + 1) * smp_threads >= smp_cpus) { 2766 nr_threads = smp_cpus - i * smp_threads; 2767 } 2768 2769 object_property_set_int(core, "nr-threads", nr_threads, 2770 &error_fatal); 2771 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2772 &error_fatal); 2773 qdev_realize(DEVICE(core), NULL, &error_fatal); 2774 2775 object_unref(core); 2776 } 2777 } 2778 } 2779 2780 static PCIHostState *spapr_create_default_phb(void) 2781 { 2782 DeviceState *dev; 2783 2784 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2785 qdev_prop_set_uint32(dev, "index", 0); 2786 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2787 2788 return PCI_HOST_BRIDGE(dev); 2789 } 2790 2791 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2792 { 2793 MachineState *machine = MACHINE(spapr); 2794 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2795 hwaddr rma_size = machine->ram_size; 2796 hwaddr node0_size = spapr_node0_size(machine); 2797 2798 /* RMA has to fit in the first NUMA node */ 2799 rma_size = MIN(rma_size, node0_size); 2800 2801 /* 2802 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2803 * never exceed that 2804 */ 2805 rma_size = MIN(rma_size, 1 * TiB); 2806 2807 /* 2808 * Clamp the RMA size based on machine type. This is for 2809 * migration compatibility with older qemu versions, which limited 2810 * the RMA size for complicated and mostly bad reasons. 2811 */ 2812 if (smc->rma_limit) { 2813 rma_size = MIN(rma_size, smc->rma_limit); 2814 } 2815 2816 if (rma_size < MIN_RMA_SLOF) { 2817 error_setg(errp, 2818 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2819 "ldMiB guest RMA (Real Mode Area memory)", 2820 MIN_RMA_SLOF / MiB); 2821 return 0; 2822 } 2823 2824 return rma_size; 2825 } 2826 2827 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2828 { 2829 MachineState *machine = MACHINE(spapr); 2830 int i; 2831 2832 for (i = 0; i < machine->ram_slots; i++) { 2833 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2834 } 2835 } 2836 2837 /* pSeries LPAR / sPAPR hardware init */ 2838 static void spapr_machine_init(MachineState *machine) 2839 { 2840 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2841 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2842 MachineClass *mc = MACHINE_GET_CLASS(machine); 2843 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2844 const char *bios_name = machine->firmware ?: bios_default; 2845 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2846 const char *kernel_filename = machine->kernel_filename; 2847 const char *initrd_filename = machine->initrd_filename; 2848 PCIHostState *phb; 2849 bool has_vga; 2850 int i; 2851 MemoryRegion *sysmem = get_system_memory(); 2852 long load_limit, fw_size; 2853 Error *resize_hpt_err = NULL; 2854 NICInfo *nd; 2855 2856 if (!filename) { 2857 error_report("Could not find LPAR firmware '%s'", bios_name); 2858 exit(1); 2859 } 2860 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2861 if (fw_size <= 0) { 2862 error_report("Could not load LPAR firmware '%s'", filename); 2863 exit(1); 2864 } 2865 2866 /* 2867 * if Secure VM (PEF) support is configured, then initialize it 2868 */ 2869 if (machine->cgs) { 2870 confidential_guest_kvm_init(machine->cgs, &error_fatal); 2871 } 2872 2873 msi_nonbroken = true; 2874 2875 QLIST_INIT(&spapr->phbs); 2876 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2877 2878 /* Determine capabilities to run with */ 2879 spapr_caps_init(spapr); 2880 2881 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2882 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2883 /* 2884 * If the user explicitly requested a mode we should either 2885 * supply it, or fail completely (which we do below). But if 2886 * it's not set explicitly, we reset our mode to something 2887 * that works 2888 */ 2889 if (resize_hpt_err) { 2890 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2891 error_free(resize_hpt_err); 2892 resize_hpt_err = NULL; 2893 } else { 2894 spapr->resize_hpt = smc->resize_hpt_default; 2895 } 2896 } 2897 2898 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2899 2900 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2901 /* 2902 * User requested HPT resize, but this host can't supply it. Bail out 2903 */ 2904 error_report_err(resize_hpt_err); 2905 exit(1); 2906 } 2907 error_free(resize_hpt_err); 2908 2909 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2910 2911 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2912 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2913 2914 /* 2915 * VSMT must be set in order to be able to compute VCPU ids, ie to 2916 * call spapr_max_server_number() or spapr_vcpu_id(). 2917 */ 2918 spapr_set_vsmt_mode(spapr, &error_fatal); 2919 2920 /* Set up Interrupt Controller before we create the VCPUs */ 2921 spapr_irq_init(spapr, &error_fatal); 2922 2923 /* Set up containers for ibm,client-architecture-support negotiated options 2924 */ 2925 spapr->ov5 = spapr_ovec_new(); 2926 spapr->ov5_cas = spapr_ovec_new(); 2927 2928 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2929 spapr_validate_node_memory(machine, &error_fatal); 2930 2931 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2932 2933 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2934 if (!smc->pre_6_2_numa_affinity) { 2935 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2936 } 2937 2938 /* advertise support for dedicated HP event source to guests */ 2939 if (spapr->use_hotplug_event_source) { 2940 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2941 } 2942 2943 /* advertise support for HPT resizing */ 2944 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2945 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2946 } 2947 2948 /* advertise support for ibm,dyamic-memory-v2 */ 2949 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2950 2951 /* advertise XIVE on POWER9 machines */ 2952 if (spapr->irq->xive) { 2953 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2954 } 2955 2956 /* init CPUs */ 2957 spapr_init_cpus(spapr); 2958 2959 /* Init numa_assoc_array */ 2960 spapr_numa_associativity_init(spapr, machine); 2961 2962 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2963 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2964 spapr->max_compat_pvr)) { 2965 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2966 /* KVM and TCG always allow GTSE with radix... */ 2967 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2968 } 2969 /* ... but not with hash (currently). */ 2970 2971 if (kvm_enabled()) { 2972 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2973 kvmppc_enable_logical_ci_hcalls(); 2974 kvmppc_enable_set_mode_hcall(); 2975 2976 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2977 kvmppc_enable_clear_ref_mod_hcalls(); 2978 2979 /* Enable H_PAGE_INIT */ 2980 kvmppc_enable_h_page_init(); 2981 } 2982 2983 /* map RAM */ 2984 memory_region_add_subregion(sysmem, 0, machine->ram); 2985 2986 /* initialize hotplug memory address space */ 2987 if (machine->ram_size < machine->maxram_size) { 2988 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2989 hwaddr device_mem_base; 2990 2991 /* 2992 * Limit the number of hotpluggable memory slots to half the number 2993 * slots that KVM supports, leaving the other half for PCI and other 2994 * devices. However ensure that number of slots doesn't drop below 32. 2995 */ 2996 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2997 SPAPR_MAX_RAM_SLOTS; 2998 2999 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 3000 max_memslots = SPAPR_MAX_RAM_SLOTS; 3001 } 3002 if (machine->ram_slots > max_memslots) { 3003 error_report("Specified number of memory slots %" 3004 PRIu64" exceeds max supported %d", 3005 machine->ram_slots, max_memslots); 3006 exit(1); 3007 } 3008 3009 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 3010 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 3011 } 3012 3013 spapr_create_lmb_dr_connectors(spapr); 3014 3015 if (mc->nvdimm_supported) { 3016 spapr_create_nvdimm_dr_connectors(spapr); 3017 } 3018 3019 /* Set up RTAS event infrastructure */ 3020 spapr_events_init(spapr); 3021 3022 /* Set up the RTC RTAS interfaces */ 3023 spapr_rtc_create(spapr); 3024 3025 /* Set up VIO bus */ 3026 spapr->vio_bus = spapr_vio_bus_init(); 3027 3028 for (i = 0; serial_hd(i); i++) { 3029 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 3030 } 3031 3032 /* We always have at least the nvram device on VIO */ 3033 spapr_create_nvram(spapr); 3034 3035 /* 3036 * Setup hotplug / dynamic-reconfiguration connectors. top-level 3037 * connectors (described in root DT node's "ibm,drc-types" property) 3038 * are pre-initialized here. additional child connectors (such as 3039 * connectors for a PHBs PCI slots) are added as needed during their 3040 * parent's realization. 3041 */ 3042 if (smc->dr_phb_enabled) { 3043 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 3044 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 3045 } 3046 } 3047 3048 /* Set up PCI */ 3049 spapr_pci_rtas_init(); 3050 3051 phb = spapr_create_default_phb(); 3052 3053 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 3054 spapr_vlan_create(spapr->vio_bus, nd); 3055 } 3056 3057 pci_init_nic_devices(phb->bus, NULL); 3058 3059 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 3060 spapr_vscsi_create(spapr->vio_bus); 3061 } 3062 3063 /* Graphics */ 3064 has_vga = spapr_vga_init(phb->bus, &error_fatal); 3065 if (has_vga) { 3066 spapr->want_stdout_path = !machine->enable_graphics; 3067 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3068 } else { 3069 spapr->want_stdout_path = true; 3070 } 3071 3072 if (machine->usb) { 3073 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3074 3075 if (has_vga) { 3076 USBBus *usb_bus; 3077 3078 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3079 &error_abort)); 3080 usb_create_simple(usb_bus, "usb-kbd"); 3081 usb_create_simple(usb_bus, "usb-mouse"); 3082 } 3083 } 3084 3085 if (kernel_filename) { 3086 uint64_t loaded_addr = 0; 3087 3088 spapr->kernel_size = load_elf(kernel_filename, NULL, 3089 translate_kernel_address, spapr, 3090 NULL, &loaded_addr, NULL, NULL, 1, 3091 PPC_ELF_MACHINE, 0, 0); 3092 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3093 spapr->kernel_size = load_elf(kernel_filename, NULL, 3094 translate_kernel_address, spapr, 3095 NULL, &loaded_addr, NULL, NULL, 0, 3096 PPC_ELF_MACHINE, 0, 0); 3097 spapr->kernel_le = spapr->kernel_size > 0; 3098 } 3099 if (spapr->kernel_size < 0) { 3100 error_report("error loading %s: %s", kernel_filename, 3101 load_elf_strerror(spapr->kernel_size)); 3102 exit(1); 3103 } 3104 3105 if (spapr->kernel_addr != loaded_addr) { 3106 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3107 " to 0x%"PRIx64, 3108 spapr->kernel_addr, loaded_addr); 3109 spapr->kernel_addr = loaded_addr; 3110 } 3111 3112 /* load initrd */ 3113 if (initrd_filename) { 3114 /* Try to locate the initrd in the gap between the kernel 3115 * and the firmware. Add a bit of space just in case 3116 */ 3117 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3118 + 0x1ffff) & ~0xffff; 3119 spapr->initrd_size = load_image_targphys(initrd_filename, 3120 spapr->initrd_base, 3121 load_limit 3122 - spapr->initrd_base); 3123 if (spapr->initrd_size < 0) { 3124 error_report("could not load initial ram disk '%s'", 3125 initrd_filename); 3126 exit(1); 3127 } 3128 } 3129 } 3130 3131 /* FIXME: Should register things through the MachineState's qdev 3132 * interface, this is a legacy from the sPAPREnvironment structure 3133 * which predated MachineState but had a similar function */ 3134 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3135 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3136 &savevm_htab_handlers, spapr); 3137 3138 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3139 3140 qemu_register_boot_set(spapr_boot_set, spapr); 3141 3142 /* 3143 * Nothing needs to be done to resume a suspended guest because 3144 * suspending does not change the machine state, so no need for 3145 * a ->wakeup method. 3146 */ 3147 qemu_register_wakeup_support(); 3148 3149 if (kvm_enabled()) { 3150 /* to stop and start vmclock */ 3151 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3152 &spapr->tb); 3153 3154 kvmppc_spapr_enable_inkernel_multitce(); 3155 } 3156 3157 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3158 if (spapr->vof) { 3159 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3160 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3161 } 3162 3163 spapr_watchdog_init(spapr); 3164 } 3165 3166 #define DEFAULT_KVM_TYPE "auto" 3167 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3168 { 3169 /* 3170 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3171 * accommodate the 'HV' and 'PV' formats that exists in the 3172 * wild. The 'auto' mode is being introduced already as 3173 * lower-case, thus we don't need to bother checking for 3174 * "AUTO". 3175 */ 3176 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3177 return 0; 3178 } 3179 3180 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3181 return 1; 3182 } 3183 3184 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3185 return 2; 3186 } 3187 3188 error_report("Unknown kvm-type specified '%s'", vm_type); 3189 return -1; 3190 } 3191 3192 /* 3193 * Implementation of an interface to adjust firmware path 3194 * for the bootindex property handling. 3195 */ 3196 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3197 DeviceState *dev) 3198 { 3199 #define CAST(type, obj, name) \ 3200 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3201 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3202 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3203 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3204 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3205 3206 if (d && bus) { 3207 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3208 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3209 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3210 3211 if (spapr) { 3212 /* 3213 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3214 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3215 * 0x8000 | (target << 8) | (bus << 5) | lun 3216 * (see the "Logical unit addressing format" table in SAM5) 3217 */ 3218 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3219 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3220 (uint64_t)id << 48); 3221 } else if (virtio) { 3222 /* 3223 * We use SRP luns of the form 01000000 | (target << 8) | lun 3224 * in the top 32 bits of the 64-bit LUN 3225 * Note: the quote above is from SLOF and it is wrong, 3226 * the actual binding is: 3227 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3228 */ 3229 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3230 if (d->lun >= 256) { 3231 /* Use the LUN "flat space addressing method" */ 3232 id |= 0x4000; 3233 } 3234 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3235 (uint64_t)id << 32); 3236 } else if (usb) { 3237 /* 3238 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3239 * in the top 32 bits of the 64-bit LUN 3240 */ 3241 unsigned usb_port = atoi(usb->port->path); 3242 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3243 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3244 (uint64_t)id << 32); 3245 } 3246 } 3247 3248 /* 3249 * SLOF probes the USB devices, and if it recognizes that the device is a 3250 * storage device, it changes its name to "storage" instead of "usb-host", 3251 * and additionally adds a child node for the SCSI LUN, so the correct 3252 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3253 */ 3254 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3255 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3256 if (usb_device_is_scsi_storage(usbdev)) { 3257 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3258 } 3259 } 3260 3261 if (phb) { 3262 /* Replace "pci" with "pci@800000020000000" */ 3263 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3264 } 3265 3266 if (vsc) { 3267 /* Same logic as virtio above */ 3268 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3269 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3270 } 3271 3272 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3273 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3274 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3275 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3276 } 3277 3278 if (pcidev) { 3279 return spapr_pci_fw_dev_name(pcidev); 3280 } 3281 3282 return NULL; 3283 } 3284 3285 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3286 { 3287 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3288 3289 return g_strdup(spapr->kvm_type); 3290 } 3291 3292 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3293 { 3294 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3295 3296 g_free(spapr->kvm_type); 3297 spapr->kvm_type = g_strdup(value); 3298 } 3299 3300 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3301 { 3302 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3303 3304 return spapr->use_hotplug_event_source; 3305 } 3306 3307 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3308 Error **errp) 3309 { 3310 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3311 3312 spapr->use_hotplug_event_source = value; 3313 } 3314 3315 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3316 { 3317 return true; 3318 } 3319 3320 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3321 { 3322 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3323 3324 switch (spapr->resize_hpt) { 3325 case SPAPR_RESIZE_HPT_DEFAULT: 3326 return g_strdup("default"); 3327 case SPAPR_RESIZE_HPT_DISABLED: 3328 return g_strdup("disabled"); 3329 case SPAPR_RESIZE_HPT_ENABLED: 3330 return g_strdup("enabled"); 3331 case SPAPR_RESIZE_HPT_REQUIRED: 3332 return g_strdup("required"); 3333 } 3334 g_assert_not_reached(); 3335 } 3336 3337 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3338 { 3339 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3340 3341 if (strcmp(value, "default") == 0) { 3342 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3343 } else if (strcmp(value, "disabled") == 0) { 3344 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3345 } else if (strcmp(value, "enabled") == 0) { 3346 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3347 } else if (strcmp(value, "required") == 0) { 3348 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3349 } else { 3350 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3351 } 3352 } 3353 3354 static bool spapr_get_vof(Object *obj, Error **errp) 3355 { 3356 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3357 3358 return spapr->vof != NULL; 3359 } 3360 3361 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3362 { 3363 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3364 3365 if (spapr->vof) { 3366 vof_cleanup(spapr->vof); 3367 g_free(spapr->vof); 3368 spapr->vof = NULL; 3369 } 3370 if (!value) { 3371 return; 3372 } 3373 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3374 } 3375 3376 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3377 { 3378 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3379 3380 if (spapr->irq == &spapr_irq_xics_legacy) { 3381 return g_strdup("legacy"); 3382 } else if (spapr->irq == &spapr_irq_xics) { 3383 return g_strdup("xics"); 3384 } else if (spapr->irq == &spapr_irq_xive) { 3385 return g_strdup("xive"); 3386 } else if (spapr->irq == &spapr_irq_dual) { 3387 return g_strdup("dual"); 3388 } 3389 g_assert_not_reached(); 3390 } 3391 3392 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3393 { 3394 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3395 3396 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3397 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3398 return; 3399 } 3400 3401 /* The legacy IRQ backend can not be set */ 3402 if (strcmp(value, "xics") == 0) { 3403 spapr->irq = &spapr_irq_xics; 3404 } else if (strcmp(value, "xive") == 0) { 3405 spapr->irq = &spapr_irq_xive; 3406 } else if (strcmp(value, "dual") == 0) { 3407 spapr->irq = &spapr_irq_dual; 3408 } else { 3409 error_setg(errp, "Bad value for \"ic-mode\" property"); 3410 } 3411 } 3412 3413 static char *spapr_get_host_model(Object *obj, Error **errp) 3414 { 3415 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3416 3417 return g_strdup(spapr->host_model); 3418 } 3419 3420 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3421 { 3422 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3423 3424 g_free(spapr->host_model); 3425 spapr->host_model = g_strdup(value); 3426 } 3427 3428 static char *spapr_get_host_serial(Object *obj, Error **errp) 3429 { 3430 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3431 3432 return g_strdup(spapr->host_serial); 3433 } 3434 3435 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3436 { 3437 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3438 3439 g_free(spapr->host_serial); 3440 spapr->host_serial = g_strdup(value); 3441 } 3442 3443 static void spapr_instance_init(Object *obj) 3444 { 3445 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3446 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3447 MachineState *ms = MACHINE(spapr); 3448 MachineClass *mc = MACHINE_GET_CLASS(ms); 3449 3450 /* 3451 * NVDIMM support went live in 5.1 without considering that, in 3452 * other archs, the user needs to enable NVDIMM support with the 3453 * 'nvdimm' machine option and the default behavior is NVDIMM 3454 * support disabled. It is too late to roll back to the standard 3455 * behavior without breaking 5.1 guests. 3456 */ 3457 if (mc->nvdimm_supported) { 3458 ms->nvdimms_state->is_enabled = true; 3459 } 3460 3461 spapr->htab_fd = -1; 3462 spapr->use_hotplug_event_source = true; 3463 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3464 object_property_add_str(obj, "kvm-type", 3465 spapr_get_kvm_type, spapr_set_kvm_type); 3466 object_property_set_description(obj, "kvm-type", 3467 "Specifies the KVM virtualization mode (auto," 3468 " hv, pr). Defaults to 'auto'. This mode will use" 3469 " any available KVM module loaded in the host," 3470 " where kvm_hv takes precedence if both kvm_hv and" 3471 " kvm_pr are loaded."); 3472 object_property_add_bool(obj, "modern-hotplug-events", 3473 spapr_get_modern_hotplug_events, 3474 spapr_set_modern_hotplug_events); 3475 object_property_set_description(obj, "modern-hotplug-events", 3476 "Use dedicated hotplug event mechanism in" 3477 " place of standard EPOW events when possible" 3478 " (required for memory hot-unplug support)"); 3479 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3480 "Maximum permitted CPU compatibility mode"); 3481 3482 object_property_add_str(obj, "resize-hpt", 3483 spapr_get_resize_hpt, spapr_set_resize_hpt); 3484 object_property_set_description(obj, "resize-hpt", 3485 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3486 object_property_add_uint32_ptr(obj, "vsmt", 3487 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3488 object_property_set_description(obj, "vsmt", 3489 "Virtual SMT: KVM behaves as if this were" 3490 " the host's SMT mode"); 3491 3492 object_property_add_bool(obj, "vfio-no-msix-emulation", 3493 spapr_get_msix_emulation, NULL); 3494 3495 object_property_add_uint64_ptr(obj, "kernel-addr", 3496 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3497 object_property_set_description(obj, "kernel-addr", 3498 stringify(KERNEL_LOAD_ADDR) 3499 " for -kernel is the default"); 3500 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3501 3502 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3503 object_property_set_description(obj, "x-vof", 3504 "Enable Virtual Open Firmware (experimental)"); 3505 3506 /* The machine class defines the default interrupt controller mode */ 3507 spapr->irq = smc->irq; 3508 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3509 spapr_set_ic_mode); 3510 object_property_set_description(obj, "ic-mode", 3511 "Specifies the interrupt controller mode (xics, xive, dual)"); 3512 3513 object_property_add_str(obj, "host-model", 3514 spapr_get_host_model, spapr_set_host_model); 3515 object_property_set_description(obj, "host-model", 3516 "Host model to advertise in guest device tree"); 3517 object_property_add_str(obj, "host-serial", 3518 spapr_get_host_serial, spapr_set_host_serial); 3519 object_property_set_description(obj, "host-serial", 3520 "Host serial number to advertise in guest device tree"); 3521 } 3522 3523 static void spapr_machine_finalizefn(Object *obj) 3524 { 3525 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3526 3527 g_free(spapr->kvm_type); 3528 } 3529 3530 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3531 { 3532 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3533 CPUPPCState *env = cpu_env(cs); 3534 3535 cpu_synchronize_state(cs); 3536 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3537 if (spapr->fwnmi_system_reset_addr != -1) { 3538 uint64_t rtas_addr, addr; 3539 3540 /* get rtas addr from fdt */ 3541 rtas_addr = spapr_get_rtas_addr(); 3542 if (!rtas_addr) { 3543 qemu_system_guest_panicked(NULL); 3544 return; 3545 } 3546 3547 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3548 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3549 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3550 env->gpr[3] = addr; 3551 } 3552 ppc_cpu_do_system_reset(cs); 3553 if (spapr->fwnmi_system_reset_addr != -1) { 3554 env->nip = spapr->fwnmi_system_reset_addr; 3555 } 3556 } 3557 3558 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3559 { 3560 CPUState *cs; 3561 3562 CPU_FOREACH(cs) { 3563 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3564 } 3565 } 3566 3567 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3568 void *fdt, int *fdt_start_offset, Error **errp) 3569 { 3570 uint64_t addr; 3571 uint32_t node; 3572 3573 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3574 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3575 &error_abort); 3576 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3577 SPAPR_MEMORY_BLOCK_SIZE); 3578 return 0; 3579 } 3580 3581 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3582 bool dedicated_hp_event_source) 3583 { 3584 SpaprDrc *drc; 3585 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3586 int i; 3587 uint64_t addr = addr_start; 3588 bool hotplugged = spapr_drc_hotplugged(dev); 3589 3590 for (i = 0; i < nr_lmbs; i++) { 3591 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3592 addr / SPAPR_MEMORY_BLOCK_SIZE); 3593 g_assert(drc); 3594 3595 /* 3596 * memory_device_get_free_addr() provided a range of free addresses 3597 * that doesn't overlap with any existing mapping at pre-plug. The 3598 * corresponding LMB DRCs are thus assumed to be all attachable. 3599 */ 3600 spapr_drc_attach(drc, dev); 3601 if (!hotplugged) { 3602 spapr_drc_reset(drc); 3603 } 3604 addr += SPAPR_MEMORY_BLOCK_SIZE; 3605 } 3606 /* send hotplug notification to the 3607 * guest only in case of hotplugged memory 3608 */ 3609 if (hotplugged) { 3610 if (dedicated_hp_event_source) { 3611 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3612 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3613 g_assert(drc); 3614 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3615 nr_lmbs, 3616 spapr_drc_index(drc)); 3617 } else { 3618 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3619 nr_lmbs); 3620 } 3621 } 3622 } 3623 3624 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3625 { 3626 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3627 PCDIMMDevice *dimm = PC_DIMM(dev); 3628 uint64_t size, addr; 3629 int64_t slot; 3630 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3631 3632 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3633 3634 pc_dimm_plug(dimm, MACHINE(ms)); 3635 3636 if (!is_nvdimm) { 3637 addr = object_property_get_uint(OBJECT(dimm), 3638 PC_DIMM_ADDR_PROP, &error_abort); 3639 spapr_add_lmbs(dev, addr, size, 3640 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3641 } else { 3642 slot = object_property_get_int(OBJECT(dimm), 3643 PC_DIMM_SLOT_PROP, &error_abort); 3644 /* We should have valid slot number at this point */ 3645 g_assert(slot >= 0); 3646 spapr_add_nvdimm(dev, slot); 3647 } 3648 } 3649 3650 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3651 Error **errp) 3652 { 3653 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3654 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3655 PCDIMMDevice *dimm = PC_DIMM(dev); 3656 Error *local_err = NULL; 3657 uint64_t size; 3658 Object *memdev; 3659 hwaddr pagesize; 3660 3661 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3662 if (local_err) { 3663 error_propagate(errp, local_err); 3664 return; 3665 } 3666 3667 if (is_nvdimm) { 3668 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3669 return; 3670 } 3671 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3672 error_setg(errp, "Hotplugged memory size must be a multiple of " 3673 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3674 return; 3675 } 3676 3677 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3678 &error_abort); 3679 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3680 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3681 return; 3682 } 3683 3684 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), errp); 3685 } 3686 3687 struct SpaprDimmState { 3688 PCDIMMDevice *dimm; 3689 uint32_t nr_lmbs; 3690 QTAILQ_ENTRY(SpaprDimmState) next; 3691 }; 3692 3693 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3694 PCDIMMDevice *dimm) 3695 { 3696 SpaprDimmState *dimm_state = NULL; 3697 3698 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3699 if (dimm_state->dimm == dimm) { 3700 break; 3701 } 3702 } 3703 return dimm_state; 3704 } 3705 3706 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3707 uint32_t nr_lmbs, 3708 PCDIMMDevice *dimm) 3709 { 3710 SpaprDimmState *ds = NULL; 3711 3712 /* 3713 * If this request is for a DIMM whose removal had failed earlier 3714 * (due to guest's refusal to remove the LMBs), we would have this 3715 * dimm already in the pending_dimm_unplugs list. In that 3716 * case don't add again. 3717 */ 3718 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3719 if (!ds) { 3720 ds = g_new0(SpaprDimmState, 1); 3721 ds->nr_lmbs = nr_lmbs; 3722 ds->dimm = dimm; 3723 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3724 } 3725 return ds; 3726 } 3727 3728 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3729 SpaprDimmState *dimm_state) 3730 { 3731 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3732 g_free(dimm_state); 3733 } 3734 3735 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3736 PCDIMMDevice *dimm) 3737 { 3738 SpaprDrc *drc; 3739 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3740 &error_abort); 3741 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3742 uint32_t avail_lmbs = 0; 3743 uint64_t addr_start, addr; 3744 int i; 3745 3746 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3747 &error_abort); 3748 3749 addr = addr_start; 3750 for (i = 0; i < nr_lmbs; i++) { 3751 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3752 addr / SPAPR_MEMORY_BLOCK_SIZE); 3753 g_assert(drc); 3754 if (drc->dev) { 3755 avail_lmbs++; 3756 } 3757 addr += SPAPR_MEMORY_BLOCK_SIZE; 3758 } 3759 3760 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3761 } 3762 3763 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3764 { 3765 SpaprDimmState *ds; 3766 PCDIMMDevice *dimm; 3767 SpaprDrc *drc; 3768 uint32_t nr_lmbs; 3769 uint64_t size, addr_start, addr; 3770 int i; 3771 3772 if (!dev) { 3773 return; 3774 } 3775 3776 dimm = PC_DIMM(dev); 3777 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3778 3779 /* 3780 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3781 * unplug state, but one of its DRC is marked as unplug_requested. 3782 * This is bad and weird enough to g_assert() out. 3783 */ 3784 g_assert(ds); 3785 3786 spapr_pending_dimm_unplugs_remove(spapr, ds); 3787 3788 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3789 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3790 3791 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3792 &error_abort); 3793 3794 addr = addr_start; 3795 for (i = 0; i < nr_lmbs; i++) { 3796 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3797 addr / SPAPR_MEMORY_BLOCK_SIZE); 3798 g_assert(drc); 3799 3800 drc->unplug_requested = false; 3801 addr += SPAPR_MEMORY_BLOCK_SIZE; 3802 } 3803 3804 /* 3805 * Tell QAPI that something happened and the memory 3806 * hotunplug wasn't successful. 3807 */ 3808 qapi_event_send_device_unplug_guest_error(dev->id, 3809 dev->canonical_path); 3810 } 3811 3812 /* Callback to be called during DRC release. */ 3813 void spapr_lmb_release(DeviceState *dev) 3814 { 3815 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3816 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3817 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3818 3819 /* This information will get lost if a migration occurs 3820 * during the unplug process. In this case recover it. */ 3821 if (ds == NULL) { 3822 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3823 g_assert(ds); 3824 /* The DRC being examined by the caller at least must be counted */ 3825 g_assert(ds->nr_lmbs); 3826 } 3827 3828 if (--ds->nr_lmbs) { 3829 return; 3830 } 3831 3832 /* 3833 * Now that all the LMBs have been removed by the guest, call the 3834 * unplug handler chain. This can never fail. 3835 */ 3836 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3837 object_unparent(OBJECT(dev)); 3838 } 3839 3840 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3841 { 3842 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3843 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3844 3845 /* We really shouldn't get this far without anything to unplug */ 3846 g_assert(ds); 3847 3848 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3849 qdev_unrealize(dev); 3850 spapr_pending_dimm_unplugs_remove(spapr, ds); 3851 } 3852 3853 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3854 DeviceState *dev, Error **errp) 3855 { 3856 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3857 PCDIMMDevice *dimm = PC_DIMM(dev); 3858 uint32_t nr_lmbs; 3859 uint64_t size, addr_start, addr; 3860 int i; 3861 SpaprDrc *drc; 3862 3863 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3864 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3865 return; 3866 } 3867 3868 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3869 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3870 3871 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3872 &error_abort); 3873 3874 /* 3875 * An existing pending dimm state for this DIMM means that there is an 3876 * unplug operation in progress, waiting for the spapr_lmb_release 3877 * callback to complete the job (BQL can't cover that far). In this case, 3878 * bail out to avoid detaching DRCs that were already released. 3879 */ 3880 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3881 error_setg(errp, "Memory unplug already in progress for device %s", 3882 dev->id); 3883 return; 3884 } 3885 3886 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3887 3888 addr = addr_start; 3889 for (i = 0; i < nr_lmbs; i++) { 3890 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3891 addr / SPAPR_MEMORY_BLOCK_SIZE); 3892 g_assert(drc); 3893 3894 spapr_drc_unplug_request(drc); 3895 addr += SPAPR_MEMORY_BLOCK_SIZE; 3896 } 3897 3898 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3899 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3900 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3901 nr_lmbs, spapr_drc_index(drc)); 3902 } 3903 3904 /* Callback to be called during DRC release. */ 3905 void spapr_core_release(DeviceState *dev) 3906 { 3907 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3908 3909 /* Call the unplug handler chain. This can never fail. */ 3910 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3911 object_unparent(OBJECT(dev)); 3912 } 3913 3914 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3915 { 3916 MachineState *ms = MACHINE(hotplug_dev); 3917 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3918 CPUCore *cc = CPU_CORE(dev); 3919 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3920 3921 if (smc->pre_2_10_has_unused_icps) { 3922 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3923 int i; 3924 3925 for (i = 0; i < cc->nr_threads; i++) { 3926 CPUState *cs = CPU(sc->threads[i]); 3927 3928 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3929 } 3930 } 3931 3932 assert(core_slot); 3933 core_slot->cpu = NULL; 3934 qdev_unrealize(dev); 3935 } 3936 3937 static 3938 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3939 Error **errp) 3940 { 3941 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3942 int index; 3943 SpaprDrc *drc; 3944 CPUCore *cc = CPU_CORE(dev); 3945 3946 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3947 error_setg(errp, "Unable to find CPU core with core-id: %d", 3948 cc->core_id); 3949 return; 3950 } 3951 if (index == 0) { 3952 error_setg(errp, "Boot CPU core may not be unplugged"); 3953 return; 3954 } 3955 3956 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3957 spapr_vcpu_id(spapr, cc->core_id)); 3958 g_assert(drc); 3959 3960 if (!spapr_drc_unplug_requested(drc)) { 3961 spapr_drc_unplug_request(drc); 3962 } 3963 3964 /* 3965 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3966 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3967 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3968 * attempt (e.g. the kernel will refuse to remove the last online 3969 * CPU), we will never attempt it again because unplug_requested 3970 * will still be 'true' in that case. 3971 */ 3972 spapr_hotplug_req_remove_by_index(drc); 3973 } 3974 3975 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3976 void *fdt, int *fdt_start_offset, Error **errp) 3977 { 3978 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3979 CPUState *cs = CPU(core->threads[0]); 3980 PowerPCCPU *cpu = POWERPC_CPU(cs); 3981 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3982 int id = spapr_get_vcpu_id(cpu); 3983 g_autofree char *nodename = NULL; 3984 int offset; 3985 3986 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3987 offset = fdt_add_subnode(fdt, 0, nodename); 3988 3989 spapr_dt_cpu(cs, fdt, offset, spapr); 3990 3991 /* 3992 * spapr_dt_cpu() does not fill the 'name' property in the 3993 * CPU node. The function is called during boot process, before 3994 * and after CAS, and overwriting the 'name' property written 3995 * by SLOF is not allowed. 3996 * 3997 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3998 * CPUs more compatible with the coldplugged ones, which have 3999 * the 'name' property. Linux Kernel also relies on this 4000 * property to identify CPU nodes. 4001 */ 4002 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 4003 4004 *fdt_start_offset = offset; 4005 return 0; 4006 } 4007 4008 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4009 { 4010 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4011 MachineClass *mc = MACHINE_GET_CLASS(spapr); 4012 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4013 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 4014 CPUCore *cc = CPU_CORE(dev); 4015 SpaprDrc *drc; 4016 CPUArchId *core_slot; 4017 int index; 4018 bool hotplugged = spapr_drc_hotplugged(dev); 4019 int i; 4020 4021 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4022 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 4023 4024 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 4025 spapr_vcpu_id(spapr, cc->core_id)); 4026 4027 g_assert(drc || !mc->has_hotpluggable_cpus); 4028 4029 if (drc) { 4030 /* 4031 * spapr_core_pre_plug() already buys us this is a brand new 4032 * core being plugged into a free slot. Nothing should already 4033 * be attached to the corresponding DRC. 4034 */ 4035 spapr_drc_attach(drc, dev); 4036 4037 if (hotplugged) { 4038 /* 4039 * Send hotplug notification interrupt to the guest only 4040 * in case of hotplugged CPUs. 4041 */ 4042 spapr_hotplug_req_add_by_index(drc); 4043 } else { 4044 spapr_drc_reset(drc); 4045 } 4046 } 4047 4048 core_slot->cpu = CPU(dev); 4049 4050 /* 4051 * Set compatibility mode to match the boot CPU, which was either set 4052 * by the machine reset code or by CAS. This really shouldn't fail at 4053 * this point. 4054 */ 4055 if (hotplugged) { 4056 for (i = 0; i < cc->nr_threads; i++) { 4057 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 4058 &error_abort); 4059 } 4060 } 4061 4062 if (smc->pre_2_10_has_unused_icps) { 4063 for (i = 0; i < cc->nr_threads; i++) { 4064 CPUState *cs = CPU(core->threads[i]); 4065 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 4066 } 4067 } 4068 } 4069 4070 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4071 Error **errp) 4072 { 4073 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 4074 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 4075 CPUCore *cc = CPU_CORE(dev); 4076 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4077 const char *type = object_get_typename(OBJECT(dev)); 4078 CPUArchId *core_slot; 4079 int index; 4080 unsigned int smp_threads = machine->smp.threads; 4081 4082 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4083 error_setg(errp, "CPU hotplug not supported for this machine"); 4084 return; 4085 } 4086 4087 if (strcmp(base_core_type, type)) { 4088 error_setg(errp, "CPU core type should be %s", base_core_type); 4089 return; 4090 } 4091 4092 if (cc->core_id % smp_threads) { 4093 error_setg(errp, "invalid core id %d", cc->core_id); 4094 return; 4095 } 4096 4097 /* 4098 * In general we should have homogeneous threads-per-core, but old 4099 * (pre hotplug support) machine types allow the last core to have 4100 * reduced threads as a compatibility hack for when we allowed 4101 * total vcpus not a multiple of threads-per-core. 4102 */ 4103 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4104 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4105 smp_threads); 4106 return; 4107 } 4108 4109 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4110 if (!core_slot) { 4111 error_setg(errp, "core id %d out of range", cc->core_id); 4112 return; 4113 } 4114 4115 if (core_slot->cpu) { 4116 error_setg(errp, "core %d already populated", cc->core_id); 4117 return; 4118 } 4119 4120 numa_cpu_pre_plug(core_slot, dev, errp); 4121 } 4122 4123 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4124 void *fdt, int *fdt_start_offset, Error **errp) 4125 { 4126 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4127 int intc_phandle; 4128 4129 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4130 if (intc_phandle <= 0) { 4131 return -1; 4132 } 4133 4134 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4135 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4136 return -1; 4137 } 4138 4139 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4140 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4141 4142 return 0; 4143 } 4144 4145 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4146 Error **errp) 4147 { 4148 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4149 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4150 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4151 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4152 SpaprDrc *drc; 4153 4154 if (dev->hotplugged && !smc->dr_phb_enabled) { 4155 error_setg(errp, "PHB hotplug not supported for this machine"); 4156 return false; 4157 } 4158 4159 if (sphb->index == (uint32_t)-1) { 4160 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4161 return false; 4162 } 4163 4164 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4165 if (drc && drc->dev) { 4166 error_setg(errp, "PHB %d already attached", sphb->index); 4167 return false; 4168 } 4169 4170 /* 4171 * This will check that sphb->index doesn't exceed the maximum number of 4172 * PHBs for the current machine type. 4173 */ 4174 return 4175 smc->phb_placement(spapr, sphb->index, 4176 &sphb->buid, &sphb->io_win_addr, 4177 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4178 windows_supported, sphb->dma_liobn, 4179 errp); 4180 } 4181 4182 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4183 { 4184 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4185 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4186 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4187 SpaprDrc *drc; 4188 bool hotplugged = spapr_drc_hotplugged(dev); 4189 4190 if (!smc->dr_phb_enabled) { 4191 return; 4192 } 4193 4194 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4195 /* hotplug hooks should check it's enabled before getting this far */ 4196 assert(drc); 4197 4198 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4199 spapr_drc_attach(drc, dev); 4200 4201 if (hotplugged) { 4202 spapr_hotplug_req_add_by_index(drc); 4203 } else { 4204 spapr_drc_reset(drc); 4205 } 4206 } 4207 4208 void spapr_phb_release(DeviceState *dev) 4209 { 4210 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4211 4212 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4213 object_unparent(OBJECT(dev)); 4214 } 4215 4216 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4217 { 4218 qdev_unrealize(dev); 4219 } 4220 4221 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4222 DeviceState *dev, Error **errp) 4223 { 4224 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4225 SpaprDrc *drc; 4226 4227 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4228 assert(drc); 4229 4230 if (!spapr_drc_unplug_requested(drc)) { 4231 spapr_drc_unplug_request(drc); 4232 spapr_hotplug_req_remove_by_index(drc); 4233 } else { 4234 error_setg(errp, 4235 "PCI Host Bridge unplug already in progress for device %s", 4236 dev->id); 4237 } 4238 } 4239 4240 static 4241 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4242 Error **errp) 4243 { 4244 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4245 4246 if (spapr->tpm_proxy != NULL) { 4247 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4248 return false; 4249 } 4250 4251 return true; 4252 } 4253 4254 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4255 { 4256 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4257 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4258 4259 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4260 g_assert(spapr->tpm_proxy == NULL); 4261 4262 spapr->tpm_proxy = tpm_proxy; 4263 } 4264 4265 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4266 { 4267 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4268 4269 qdev_unrealize(dev); 4270 object_unparent(OBJECT(dev)); 4271 spapr->tpm_proxy = NULL; 4272 } 4273 4274 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4275 DeviceState *dev, Error **errp) 4276 { 4277 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4278 spapr_memory_plug(hotplug_dev, dev); 4279 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4280 spapr_core_plug(hotplug_dev, dev); 4281 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4282 spapr_phb_plug(hotplug_dev, dev); 4283 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4284 spapr_tpm_proxy_plug(hotplug_dev, dev); 4285 } 4286 } 4287 4288 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4289 DeviceState *dev, Error **errp) 4290 { 4291 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4292 spapr_memory_unplug(hotplug_dev, dev); 4293 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4294 spapr_core_unplug(hotplug_dev, dev); 4295 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4296 spapr_phb_unplug(hotplug_dev, dev); 4297 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4298 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4299 } 4300 } 4301 4302 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4303 { 4304 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4305 /* 4306 * CAS will process all pending unplug requests. 4307 * 4308 * HACK: a guest could theoretically have cleared all bits in OV5, 4309 * but none of the guests we care for do. 4310 */ 4311 spapr_ovec_empty(spapr->ov5_cas); 4312 } 4313 4314 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4315 DeviceState *dev, Error **errp) 4316 { 4317 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4318 MachineClass *mc = MACHINE_GET_CLASS(sms); 4319 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4320 4321 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4322 if (spapr_memory_hot_unplug_supported(sms)) { 4323 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4324 } else { 4325 error_setg(errp, "Memory hot unplug not supported for this guest"); 4326 } 4327 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4328 if (!mc->has_hotpluggable_cpus) { 4329 error_setg(errp, "CPU hot unplug not supported on this machine"); 4330 return; 4331 } 4332 spapr_core_unplug_request(hotplug_dev, dev, errp); 4333 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4334 if (!smc->dr_phb_enabled) { 4335 error_setg(errp, "PHB hot unplug not supported on this machine"); 4336 return; 4337 } 4338 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4339 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4340 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4341 } 4342 } 4343 4344 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4345 DeviceState *dev, Error **errp) 4346 { 4347 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4348 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4349 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4350 spapr_core_pre_plug(hotplug_dev, dev, errp); 4351 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4352 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4353 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4354 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4355 } 4356 } 4357 4358 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4359 DeviceState *dev) 4360 { 4361 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4362 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4363 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4364 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4365 return HOTPLUG_HANDLER(machine); 4366 } 4367 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4368 PCIDevice *pcidev = PCI_DEVICE(dev); 4369 PCIBus *root = pci_device_root_bus(pcidev); 4370 SpaprPhbState *phb = 4371 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4372 TYPE_SPAPR_PCI_HOST_BRIDGE); 4373 4374 if (phb) { 4375 return HOTPLUG_HANDLER(phb); 4376 } 4377 } 4378 return NULL; 4379 } 4380 4381 static CpuInstanceProperties 4382 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4383 { 4384 CPUArchId *core_slot; 4385 MachineClass *mc = MACHINE_GET_CLASS(machine); 4386 4387 /* make sure possible_cpu are initialized */ 4388 mc->possible_cpu_arch_ids(machine); 4389 /* get CPU core slot containing thread that matches cpu_index */ 4390 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4391 assert(core_slot); 4392 return core_slot->props; 4393 } 4394 4395 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4396 { 4397 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4398 } 4399 4400 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4401 { 4402 int i; 4403 unsigned int smp_threads = machine->smp.threads; 4404 unsigned int smp_cpus = machine->smp.cpus; 4405 const char *core_type; 4406 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4407 MachineClass *mc = MACHINE_GET_CLASS(machine); 4408 4409 if (!mc->has_hotpluggable_cpus) { 4410 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4411 } 4412 if (machine->possible_cpus) { 4413 assert(machine->possible_cpus->len == spapr_max_cores); 4414 return machine->possible_cpus; 4415 } 4416 4417 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4418 if (!core_type) { 4419 error_report("Unable to find sPAPR CPU Core definition"); 4420 exit(1); 4421 } 4422 4423 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4424 sizeof(CPUArchId) * spapr_max_cores); 4425 machine->possible_cpus->len = spapr_max_cores; 4426 for (i = 0; i < machine->possible_cpus->len; i++) { 4427 int core_id = i * smp_threads; 4428 4429 machine->possible_cpus->cpus[i].type = core_type; 4430 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4431 machine->possible_cpus->cpus[i].arch_id = core_id; 4432 machine->possible_cpus->cpus[i].props.has_core_id = true; 4433 machine->possible_cpus->cpus[i].props.core_id = core_id; 4434 } 4435 return machine->possible_cpus; 4436 } 4437 4438 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4439 uint64_t *buid, hwaddr *pio, 4440 hwaddr *mmio32, hwaddr *mmio64, 4441 unsigned n_dma, uint32_t *liobns, Error **errp) 4442 { 4443 /* 4444 * New-style PHB window placement. 4445 * 4446 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4447 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4448 * windows. 4449 * 4450 * Some guest kernels can't work with MMIO windows above 1<<46 4451 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4452 * 4453 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4454 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4455 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4456 * 1TiB 64-bit MMIO windows for each PHB. 4457 */ 4458 const uint64_t base_buid = 0x800000020000000ULL; 4459 int i; 4460 4461 /* Sanity check natural alignments */ 4462 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4463 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4464 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4465 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4466 /* Sanity check bounds */ 4467 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4468 SPAPR_PCI_MEM32_WIN_SIZE); 4469 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4470 SPAPR_PCI_MEM64_WIN_SIZE); 4471 4472 if (index >= SPAPR_MAX_PHBS) { 4473 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4474 SPAPR_MAX_PHBS - 1); 4475 return false; 4476 } 4477 4478 *buid = base_buid + index; 4479 for (i = 0; i < n_dma; ++i) { 4480 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4481 } 4482 4483 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4484 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4485 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4486 return true; 4487 } 4488 4489 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4490 { 4491 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4492 4493 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4494 } 4495 4496 static void spapr_ics_resend(XICSFabric *dev) 4497 { 4498 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4499 4500 ics_resend(spapr->ics); 4501 } 4502 4503 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4504 { 4505 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4506 4507 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4508 } 4509 4510 static void spapr_pic_print_info(InterruptStatsProvider *obj, GString *buf) 4511 { 4512 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4513 4514 spapr_irq_print_info(spapr, buf); 4515 g_string_append_printf(buf, "irqchip: %s\n", 4516 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4517 } 4518 4519 /* 4520 * This is a XIVE only operation 4521 */ 4522 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4523 uint8_t nvt_blk, uint32_t nvt_idx, 4524 bool cam_ignore, uint8_t priority, 4525 uint32_t logic_serv, XiveTCTXMatch *match) 4526 { 4527 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4528 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4529 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4530 int count; 4531 4532 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4533 priority, logic_serv, match); 4534 if (count < 0) { 4535 return count; 4536 } 4537 4538 /* 4539 * When we implement the save and restore of the thread interrupt 4540 * contexts in the enter/exit CPU handlers of the machine and the 4541 * escalations in QEMU, we should be able to handle non dispatched 4542 * vCPUs. 4543 * 4544 * Until this is done, the sPAPR machine should find at least one 4545 * matching context always. 4546 */ 4547 if (count == 0) { 4548 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4549 nvt_blk, nvt_idx); 4550 } 4551 4552 return count; 4553 } 4554 4555 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4556 { 4557 return cpu->vcpu_id; 4558 } 4559 4560 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4561 { 4562 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4563 MachineState *ms = MACHINE(spapr); 4564 int vcpu_id; 4565 4566 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4567 4568 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4569 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4570 error_append_hint(errp, "Adjust the number of cpus to %d " 4571 "or try to raise the number of threads per core\n", 4572 vcpu_id * ms->smp.threads / spapr->vsmt); 4573 return false; 4574 } 4575 4576 cpu->vcpu_id = vcpu_id; 4577 return true; 4578 } 4579 4580 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4581 { 4582 CPUState *cs; 4583 4584 CPU_FOREACH(cs) { 4585 PowerPCCPU *cpu = POWERPC_CPU(cs); 4586 4587 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4588 return cpu; 4589 } 4590 } 4591 4592 return NULL; 4593 } 4594 4595 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4596 { 4597 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4598 4599 return spapr_cpu->in_nested; 4600 } 4601 4602 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4603 { 4604 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4605 4606 /* These are only called by TCG, KVM maintains dispatch state */ 4607 4608 spapr_cpu->prod = false; 4609 if (spapr_cpu->vpa_addr) { 4610 CPUState *cs = CPU(cpu); 4611 uint32_t dispatch; 4612 4613 dispatch = ldl_be_phys(cs->as, 4614 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4615 dispatch++; 4616 if ((dispatch & 1) != 0) { 4617 qemu_log_mask(LOG_GUEST_ERROR, 4618 "VPA: incorrect dispatch counter value for " 4619 "dispatched partition %u, correcting.\n", dispatch); 4620 dispatch++; 4621 } 4622 stl_be_phys(cs->as, 4623 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4624 } 4625 } 4626 4627 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4628 { 4629 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4630 4631 if (spapr_cpu->vpa_addr) { 4632 CPUState *cs = CPU(cpu); 4633 uint32_t dispatch; 4634 4635 dispatch = ldl_be_phys(cs->as, 4636 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4637 dispatch++; 4638 if ((dispatch & 1) != 1) { 4639 qemu_log_mask(LOG_GUEST_ERROR, 4640 "VPA: incorrect dispatch counter value for " 4641 "preempted partition %u, correcting.\n", dispatch); 4642 dispatch++; 4643 } 4644 stl_be_phys(cs->as, 4645 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4646 } 4647 } 4648 4649 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4650 { 4651 MachineClass *mc = MACHINE_CLASS(oc); 4652 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4653 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4654 NMIClass *nc = NMI_CLASS(oc); 4655 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4656 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4657 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4658 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4659 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4660 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4661 4662 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4663 mc->ignore_boot_device_suffixes = true; 4664 4665 /* 4666 * We set up the default / latest behaviour here. The class_init 4667 * functions for the specific versioned machine types can override 4668 * these details for backwards compatibility 4669 */ 4670 mc->init = spapr_machine_init; 4671 mc->reset = spapr_machine_reset; 4672 mc->block_default_type = IF_SCSI; 4673 4674 /* 4675 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4676 * In TCG the limit is restricted by the range of CPU IPIs available. 4677 */ 4678 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4679 4680 mc->no_parallel = 1; 4681 mc->default_boot_order = ""; 4682 mc->default_ram_size = 512 * MiB; 4683 mc->default_ram_id = "ppc_spapr.ram"; 4684 mc->default_display = "std"; 4685 mc->kvm_type = spapr_kvm_type; 4686 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4687 mc->pci_allow_0_address = true; 4688 assert(!mc->get_hotplug_handler); 4689 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4690 hc->pre_plug = spapr_machine_device_pre_plug; 4691 hc->plug = spapr_machine_device_plug; 4692 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4693 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4694 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4695 hc->unplug_request = spapr_machine_device_unplug_request; 4696 hc->unplug = spapr_machine_device_unplug; 4697 4698 smc->update_dt_enabled = true; 4699 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4700 mc->has_hotpluggable_cpus = true; 4701 mc->nvdimm_supported = true; 4702 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4703 fwc->get_dev_path = spapr_get_fw_dev_path; 4704 nc->nmi_monitor_handler = spapr_nmi; 4705 smc->phb_placement = spapr_phb_placement; 4706 vhc->cpu_in_nested = spapr_cpu_in_nested; 4707 vhc->deliver_hv_excp = spapr_exit_nested; 4708 vhc->hypercall = emulate_spapr_hypercall; 4709 vhc->hpt_mask = spapr_hpt_mask; 4710 vhc->map_hptes = spapr_map_hptes; 4711 vhc->unmap_hptes = spapr_unmap_hptes; 4712 vhc->hpte_set_c = spapr_hpte_set_c; 4713 vhc->hpte_set_r = spapr_hpte_set_r; 4714 vhc->get_pate = spapr_get_pate; 4715 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4716 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4717 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4718 xic->ics_get = spapr_ics_get; 4719 xic->ics_resend = spapr_ics_resend; 4720 xic->icp_get = spapr_icp_get; 4721 ispc->print_info = spapr_pic_print_info; 4722 /* Force NUMA node memory size to be a multiple of 4723 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4724 * in which LMBs are represented and hot-added 4725 */ 4726 mc->numa_mem_align_shift = 28; 4727 mc->auto_enable_numa = true; 4728 4729 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4730 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4731 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4732 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4733 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4734 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4735 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4736 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4737 smc->default_caps.caps[SPAPR_CAP_NESTED_PAPR] = SPAPR_CAP_OFF; 4738 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4739 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4740 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4741 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4742 4743 /* 4744 * This cap specifies whether the AIL 3 mode for 4745 * H_SET_RESOURCE is supported. The default is modified 4746 * by default_caps_with_cpu(). 4747 */ 4748 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4749 spapr_caps_add_properties(smc); 4750 smc->irq = &spapr_irq_dual; 4751 smc->dr_phb_enabled = true; 4752 smc->linux_pci_probe = true; 4753 smc->smp_threads_vsmt = true; 4754 smc->nr_xirqs = SPAPR_NR_XIRQS; 4755 xfc->match_nvt = spapr_match_nvt; 4756 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4757 vmc->quiesce = spapr_vof_quiesce; 4758 vmc->setprop = spapr_vof_setprop; 4759 } 4760 4761 static const TypeInfo spapr_machine_info = { 4762 .name = TYPE_SPAPR_MACHINE, 4763 .parent = TYPE_MACHINE, 4764 .abstract = true, 4765 .instance_size = sizeof(SpaprMachineState), 4766 .instance_init = spapr_instance_init, 4767 .instance_finalize = spapr_machine_finalizefn, 4768 .class_size = sizeof(SpaprMachineClass), 4769 .class_init = spapr_machine_class_init, 4770 .interfaces = (InterfaceInfo[]) { 4771 { TYPE_FW_PATH_PROVIDER }, 4772 { TYPE_NMI }, 4773 { TYPE_HOTPLUG_HANDLER }, 4774 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4775 { TYPE_XICS_FABRIC }, 4776 { TYPE_INTERRUPT_STATS_PROVIDER }, 4777 { TYPE_XIVE_FABRIC }, 4778 { TYPE_VOF_MACHINE_IF }, 4779 { } 4780 }, 4781 }; 4782 4783 static void spapr_machine_latest_class_options(MachineClass *mc) 4784 { 4785 mc->alias = "pseries"; 4786 mc->is_default = true; 4787 } 4788 4789 #define DEFINE_SPAPR_MACHINE_IMPL(latest, ...) \ 4790 static void MACHINE_VER_SYM(class_init, spapr, __VA_ARGS__)( \ 4791 ObjectClass *oc, \ 4792 void *data) \ 4793 { \ 4794 MachineClass *mc = MACHINE_CLASS(oc); \ 4795 MACHINE_VER_SYM(class_options, spapr, __VA_ARGS__)(mc); \ 4796 MACHINE_VER_DEPRECATION(__VA_ARGS__); \ 4797 if (latest) { \ 4798 spapr_machine_latest_class_options(mc); \ 4799 } \ 4800 } \ 4801 static const TypeInfo MACHINE_VER_SYM(info, spapr, __VA_ARGS__) = \ 4802 { \ 4803 .name = MACHINE_VER_TYPE_NAME("pseries", __VA_ARGS__), \ 4804 .parent = TYPE_SPAPR_MACHINE, \ 4805 .class_init = MACHINE_VER_SYM(class_init, spapr, __VA_ARGS__), \ 4806 }; \ 4807 static void MACHINE_VER_SYM(register, spapr, __VA_ARGS__)(void) \ 4808 { \ 4809 MACHINE_VER_DELETION(__VA_ARGS__); \ 4810 type_register(&MACHINE_VER_SYM(info, spapr, __VA_ARGS__)); \ 4811 } \ 4812 type_init(MACHINE_VER_SYM(register, spapr, __VA_ARGS__)) 4813 4814 #define DEFINE_SPAPR_MACHINE_AS_LATEST(major, minor) \ 4815 DEFINE_SPAPR_MACHINE_IMPL(true, major, minor) 4816 #define DEFINE_SPAPR_MACHINE(major, minor) \ 4817 DEFINE_SPAPR_MACHINE_IMPL(false, major, minor) 4818 #define DEFINE_SPAPR_MACHINE_TAGGED(major, minor, tag) \ 4819 DEFINE_SPAPR_MACHINE_IMPL(false, major, minor, _, tag) 4820 4821 /* 4822 * pseries-9.2 4823 */ 4824 static void spapr_machine_9_2_class_options(MachineClass *mc) 4825 { 4826 /* Defaults for the latest behaviour inherited from the base class */ 4827 } 4828 4829 DEFINE_SPAPR_MACHINE_AS_LATEST(9, 2); 4830 4831 /* 4832 * pseries-9.1 4833 */ 4834 static void spapr_machine_9_1_class_options(MachineClass *mc) 4835 { 4836 spapr_machine_9_2_class_options(mc); 4837 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); 4838 } 4839 4840 DEFINE_SPAPR_MACHINE(9, 1); 4841 4842 /* 4843 * pseries-9.0 4844 */ 4845 static void spapr_machine_9_0_class_options(MachineClass *mc) 4846 { 4847 spapr_machine_9_1_class_options(mc); 4848 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 4849 } 4850 4851 DEFINE_SPAPR_MACHINE(9, 0); 4852 4853 /* 4854 * pseries-8.2 4855 */ 4856 static void spapr_machine_8_2_class_options(MachineClass *mc) 4857 { 4858 spapr_machine_9_0_class_options(mc); 4859 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4860 } 4861 4862 DEFINE_SPAPR_MACHINE(8, 2); 4863 4864 /* 4865 * pseries-8.1 4866 */ 4867 static void spapr_machine_8_1_class_options(MachineClass *mc) 4868 { 4869 spapr_machine_8_2_class_options(mc); 4870 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4871 } 4872 4873 DEFINE_SPAPR_MACHINE(8, 1); 4874 4875 /* 4876 * pseries-8.0 4877 */ 4878 static void spapr_machine_8_0_class_options(MachineClass *mc) 4879 { 4880 spapr_machine_8_1_class_options(mc); 4881 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4882 } 4883 4884 DEFINE_SPAPR_MACHINE(8, 0); 4885 4886 /* 4887 * pseries-7.2 4888 */ 4889 static void spapr_machine_7_2_class_options(MachineClass *mc) 4890 { 4891 spapr_machine_8_0_class_options(mc); 4892 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4893 } 4894 4895 DEFINE_SPAPR_MACHINE(7, 2); 4896 4897 /* 4898 * pseries-7.1 4899 */ 4900 static void spapr_machine_7_1_class_options(MachineClass *mc) 4901 { 4902 spapr_machine_7_2_class_options(mc); 4903 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4904 } 4905 4906 DEFINE_SPAPR_MACHINE(7, 1); 4907 4908 /* 4909 * pseries-7.0 4910 */ 4911 static void spapr_machine_7_0_class_options(MachineClass *mc) 4912 { 4913 spapr_machine_7_1_class_options(mc); 4914 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4915 } 4916 4917 DEFINE_SPAPR_MACHINE(7, 0); 4918 4919 /* 4920 * pseries-6.2 4921 */ 4922 static void spapr_machine_6_2_class_options(MachineClass *mc) 4923 { 4924 spapr_machine_7_0_class_options(mc); 4925 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4926 } 4927 4928 DEFINE_SPAPR_MACHINE(6, 2); 4929 4930 /* 4931 * pseries-6.1 4932 */ 4933 static void spapr_machine_6_1_class_options(MachineClass *mc) 4934 { 4935 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4936 4937 spapr_machine_6_2_class_options(mc); 4938 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4939 smc->pre_6_2_numa_affinity = true; 4940 mc->smp_props.prefer_sockets = true; 4941 } 4942 4943 DEFINE_SPAPR_MACHINE(6, 1); 4944 4945 /* 4946 * pseries-6.0 4947 */ 4948 static void spapr_machine_6_0_class_options(MachineClass *mc) 4949 { 4950 spapr_machine_6_1_class_options(mc); 4951 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4952 } 4953 4954 DEFINE_SPAPR_MACHINE(6, 0); 4955 4956 /* 4957 * pseries-5.2 4958 */ 4959 static void spapr_machine_5_2_class_options(MachineClass *mc) 4960 { 4961 spapr_machine_6_0_class_options(mc); 4962 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4963 } 4964 4965 DEFINE_SPAPR_MACHINE(5, 2); 4966 4967 /* 4968 * pseries-5.1 4969 */ 4970 static void spapr_machine_5_1_class_options(MachineClass *mc) 4971 { 4972 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4973 4974 spapr_machine_5_2_class_options(mc); 4975 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4976 smc->pre_5_2_numa_associativity = true; 4977 } 4978 4979 DEFINE_SPAPR_MACHINE(5, 1); 4980 4981 /* 4982 * pseries-5.0 4983 */ 4984 static void spapr_machine_5_0_class_options(MachineClass *mc) 4985 { 4986 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4987 static GlobalProperty compat[] = { 4988 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4989 }; 4990 4991 spapr_machine_5_1_class_options(mc); 4992 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4993 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4994 mc->numa_mem_supported = true; 4995 smc->pre_5_1_assoc_refpoints = true; 4996 } 4997 4998 DEFINE_SPAPR_MACHINE(5, 0); 4999 5000 /* 5001 * pseries-4.2 5002 */ 5003 static void spapr_machine_4_2_class_options(MachineClass *mc) 5004 { 5005 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5006 5007 spapr_machine_5_0_class_options(mc); 5008 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 5009 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 5010 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 5011 smc->rma_limit = 16 * GiB; 5012 mc->nvdimm_supported = false; 5013 } 5014 5015 DEFINE_SPAPR_MACHINE(4, 2); 5016 5017 /* 5018 * pseries-4.1 5019 */ 5020 static void spapr_machine_4_1_class_options(MachineClass *mc) 5021 { 5022 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5023 static GlobalProperty compat[] = { 5024 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 5025 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 5026 }; 5027 5028 spapr_machine_4_2_class_options(mc); 5029 smc->linux_pci_probe = false; 5030 smc->smp_threads_vsmt = false; 5031 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 5032 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5033 } 5034 5035 DEFINE_SPAPR_MACHINE(4, 1); 5036 5037 /* 5038 * pseries-4.0 5039 */ 5040 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 5041 uint64_t *buid, hwaddr *pio, 5042 hwaddr *mmio32, hwaddr *mmio64, 5043 unsigned n_dma, uint32_t *liobns, Error **errp) 5044 { 5045 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 5046 liobns, errp)) { 5047 return false; 5048 } 5049 return true; 5050 } 5051 static void spapr_machine_4_0_class_options(MachineClass *mc) 5052 { 5053 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5054 5055 spapr_machine_4_1_class_options(mc); 5056 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 5057 smc->phb_placement = phb_placement_4_0; 5058 smc->irq = &spapr_irq_xics; 5059 smc->pre_4_1_migration = true; 5060 } 5061 5062 DEFINE_SPAPR_MACHINE(4, 0); 5063 5064 /* 5065 * pseries-3.1 5066 */ 5067 static void spapr_machine_3_1_class_options(MachineClass *mc) 5068 { 5069 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5070 5071 spapr_machine_4_0_class_options(mc); 5072 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 5073 5074 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 5075 smc->update_dt_enabled = false; 5076 smc->dr_phb_enabled = false; 5077 smc->broken_host_serial_model = true; 5078 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5079 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5080 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5081 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5082 } 5083 5084 DEFINE_SPAPR_MACHINE(3, 1); 5085 5086 /* 5087 * pseries-3.0 5088 */ 5089 5090 static void spapr_machine_3_0_class_options(MachineClass *mc) 5091 { 5092 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5093 5094 spapr_machine_3_1_class_options(mc); 5095 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5096 5097 smc->legacy_irq_allocation = true; 5098 smc->nr_xirqs = 0x400; 5099 smc->irq = &spapr_irq_xics_legacy; 5100 } 5101 5102 DEFINE_SPAPR_MACHINE(3, 0); 5103 5104 /* 5105 * pseries-2.12 5106 */ 5107 static void spapr_machine_2_12_class_options(MachineClass *mc) 5108 { 5109 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5110 static GlobalProperty compat[] = { 5111 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 5112 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 5113 }; 5114 5115 spapr_machine_3_0_class_options(mc); 5116 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 5117 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5118 5119 /* We depend on kvm_enabled() to choose a default value for the 5120 * hpt-max-page-size capability. Of course we can't do it here 5121 * because this is too early and the HW accelerator isn't initialized 5122 * yet. Postpone this to machine init (see default_caps_with_cpu()). 5123 */ 5124 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 5125 } 5126 5127 DEFINE_SPAPR_MACHINE(2, 12); 5128 5129 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 5130 { 5131 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5132 5133 spapr_machine_2_12_class_options(mc); 5134 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 5135 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 5136 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 5137 } 5138 5139 DEFINE_SPAPR_MACHINE_TAGGED(2, 12, sxxm); 5140 5141 /* 5142 * pseries-2.11 5143 */ 5144 5145 static void spapr_machine_2_11_class_options(MachineClass *mc) 5146 { 5147 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5148 5149 spapr_machine_2_12_class_options(mc); 5150 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5151 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5152 } 5153 5154 DEFINE_SPAPR_MACHINE(2, 11); 5155 5156 /* 5157 * pseries-2.10 5158 */ 5159 5160 static void spapr_machine_2_10_class_options(MachineClass *mc) 5161 { 5162 spapr_machine_2_11_class_options(mc); 5163 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5164 } 5165 5166 DEFINE_SPAPR_MACHINE(2, 10); 5167 5168 /* 5169 * pseries-2.9 5170 */ 5171 5172 static void spapr_machine_2_9_class_options(MachineClass *mc) 5173 { 5174 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5175 static GlobalProperty compat[] = { 5176 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5177 }; 5178 5179 spapr_machine_2_10_class_options(mc); 5180 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5181 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5182 smc->pre_2_10_has_unused_icps = true; 5183 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5184 } 5185 5186 DEFINE_SPAPR_MACHINE(2, 9); 5187 5188 static void spapr_machine_register_types(void) 5189 { 5190 type_register_static(&spapr_machine_info); 5191 } 5192 5193 type_init(spapr_machine_register_types) 5194