1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/hostmem.h" 34 #include "sysemu/numa.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/runstate.h" 38 #include "qemu/log.h" 39 #include "hw/fw-path-provider.h" 40 #include "elf.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/cpus.h" 44 #include "sysemu/hw_accel.h" 45 #include "kvm_ppc.h" 46 #include "migration/misc.h" 47 #include "migration/qemu-file-types.h" 48 #include "migration/global_state.h" 49 #include "migration/register.h" 50 #include "migration/blocker.h" 51 #include "mmu-hash64.h" 52 #include "mmu-book3s-v3.h" 53 #include "cpu-models.h" 54 #include "hw/core/cpu.h" 55 56 #include "hw/boards.h" 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/address-spaces.h" 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_OVERHEAD 0x2800000 106 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 107 108 #define MIN_RMA_SLOF (128 * MiB) 109 110 #define PHANDLE_INTC 0x00001111 111 112 /* These two functions implement the VCPU id numbering: one to compute them 113 * all and one to identify thread 0 of a VCORE. Any change to the first one 114 * is likely to have an impact on the second one, so let's keep them close. 115 */ 116 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 117 { 118 MachineState *ms = MACHINE(spapr); 119 unsigned int smp_threads = ms->smp.threads; 120 121 assert(spapr->vsmt); 122 return 123 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 124 } 125 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 126 PowerPCCPU *cpu) 127 { 128 assert(spapr->vsmt); 129 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 130 } 131 132 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 133 { 134 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 135 * and newer QEMUs don't even have them. In both cases, we don't want 136 * to send anything on the wire. 137 */ 138 return false; 139 } 140 141 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 142 .name = "icp/server", 143 .version_id = 1, 144 .minimum_version_id = 1, 145 .needed = pre_2_10_vmstate_dummy_icp_needed, 146 .fields = (VMStateField[]) { 147 VMSTATE_UNUSED(4), /* uint32_t xirr */ 148 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 149 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 150 VMSTATE_END_OF_LIST() 151 }, 152 }; 153 154 static void pre_2_10_vmstate_register_dummy_icp(int i) 155 { 156 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 157 (void *)(uintptr_t) i); 158 } 159 160 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 161 { 162 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 163 (void *)(uintptr_t) i); 164 } 165 166 int spapr_max_server_number(SpaprMachineState *spapr) 167 { 168 MachineState *ms = MACHINE(spapr); 169 170 assert(spapr->vsmt); 171 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 172 } 173 174 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 175 int smt_threads) 176 { 177 int i, ret = 0; 178 uint32_t servers_prop[smt_threads]; 179 uint32_t gservers_prop[smt_threads * 2]; 180 int index = spapr_get_vcpu_id(cpu); 181 182 if (cpu->compat_pvr) { 183 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 184 if (ret < 0) { 185 return ret; 186 } 187 } 188 189 /* Build interrupt servers and gservers properties */ 190 for (i = 0; i < smt_threads; i++) { 191 servers_prop[i] = cpu_to_be32(index + i); 192 /* Hack, direct the group queues back to cpu 0 */ 193 gservers_prop[i*2] = cpu_to_be32(index + i); 194 gservers_prop[i*2 + 1] = 0; 195 } 196 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 197 servers_prop, sizeof(servers_prop)); 198 if (ret < 0) { 199 return ret; 200 } 201 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 202 gservers_prop, sizeof(gservers_prop)); 203 204 return ret; 205 } 206 207 static void spapr_dt_pa_features(SpaprMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset) 210 { 211 uint8_t pa_features_206[] = { 6, 0, 212 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 213 uint8_t pa_features_207[] = { 24, 0, 214 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 215 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 216 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 217 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 218 uint8_t pa_features_300[] = { 66, 0, 219 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 220 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 221 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 222 /* 6: DS207 */ 223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 224 /* 16: Vector */ 225 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 226 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 227 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 228 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 229 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 230 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 231 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 232 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 234 /* 42: PM, 44: PC RA, 46: SC vec'd */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 236 /* 48: SIMD, 50: QP BFP, 52: String */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 238 /* 54: DecFP, 56: DecI, 58: SHA */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 240 /* 60: NM atomic, 62: RNG */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 242 }; 243 uint8_t *pa_features = NULL; 244 size_t pa_size; 245 246 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 247 pa_features = pa_features_206; 248 pa_size = sizeof(pa_features_206); 249 } 250 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 251 pa_features = pa_features_207; 252 pa_size = sizeof(pa_features_207); 253 } 254 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 255 pa_features = pa_features_300; 256 pa_size = sizeof(pa_features_300); 257 } 258 if (!pa_features) { 259 return; 260 } 261 262 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 263 /* 264 * Note: we keep CI large pages off by default because a 64K capable 265 * guest provisioned with large pages might otherwise try to map a qemu 266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 267 * even if that qemu runs on a 4k host. 268 * We dd this bit back here if we are confident this is not an issue 269 */ 270 pa_features[3] |= 0x20; 271 } 272 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 273 pa_features[24] |= 0x80; /* Transactional memory support */ 274 } 275 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 276 /* Workaround for broken kernels that attempt (guest) radix 277 * mode when they can't handle it, if they see the radix bit set 278 * in pa-features. So hide it from them. */ 279 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 280 } 281 282 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 283 } 284 285 static hwaddr spapr_node0_size(MachineState *machine) 286 { 287 if (machine->numa_state->num_nodes) { 288 int i; 289 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 290 if (machine->numa_state->nodes[i].node_mem) { 291 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 292 machine->ram_size); 293 } 294 } 295 } 296 return machine->ram_size; 297 } 298 299 static void add_str(GString *s, const gchar *s1) 300 { 301 g_string_append_len(s, s1, strlen(s1) + 1); 302 } 303 304 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 305 hwaddr start, hwaddr size) 306 { 307 char mem_name[32]; 308 uint64_t mem_reg_property[2]; 309 int off; 310 311 mem_reg_property[0] = cpu_to_be64(start); 312 mem_reg_property[1] = cpu_to_be64(size); 313 314 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 315 off = fdt_add_subnode(fdt, 0, mem_name); 316 _FDT(off); 317 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 318 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 319 sizeof(mem_reg_property)))); 320 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 321 return off; 322 } 323 324 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 325 { 326 MemoryDeviceInfoList *info; 327 328 for (info = list; info; info = info->next) { 329 MemoryDeviceInfo *value = info->value; 330 331 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 332 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 333 334 if (addr >= pcdimm_info->addr && 335 addr < (pcdimm_info->addr + pcdimm_info->size)) { 336 return pcdimm_info->node; 337 } 338 } 339 } 340 341 return -1; 342 } 343 344 struct sPAPRDrconfCellV2 { 345 uint32_t seq_lmbs; 346 uint64_t base_addr; 347 uint32_t drc_index; 348 uint32_t aa_index; 349 uint32_t flags; 350 } QEMU_PACKED; 351 352 typedef struct DrconfCellQueue { 353 struct sPAPRDrconfCellV2 cell; 354 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 355 } DrconfCellQueue; 356 357 static DrconfCellQueue * 358 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 359 uint32_t drc_index, uint32_t aa_index, 360 uint32_t flags) 361 { 362 DrconfCellQueue *elem; 363 364 elem = g_malloc0(sizeof(*elem)); 365 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 366 elem->cell.base_addr = cpu_to_be64(base_addr); 367 elem->cell.drc_index = cpu_to_be32(drc_index); 368 elem->cell.aa_index = cpu_to_be32(aa_index); 369 elem->cell.flags = cpu_to_be32(flags); 370 371 return elem; 372 } 373 374 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 375 int offset, MemoryDeviceInfoList *dimms) 376 { 377 MachineState *machine = MACHINE(spapr); 378 uint8_t *int_buf, *cur_index; 379 int ret; 380 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 381 uint64_t addr, cur_addr, size; 382 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 383 uint64_t mem_end = machine->device_memory->base + 384 memory_region_size(&machine->device_memory->mr); 385 uint32_t node, buf_len, nr_entries = 0; 386 SpaprDrc *drc; 387 DrconfCellQueue *elem, *next; 388 MemoryDeviceInfoList *info; 389 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 390 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 391 392 /* Entry to cover RAM and the gap area */ 393 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 394 SPAPR_LMB_FLAGS_RESERVED | 395 SPAPR_LMB_FLAGS_DRC_INVALID); 396 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 397 nr_entries++; 398 399 cur_addr = machine->device_memory->base; 400 for (info = dimms; info; info = info->next) { 401 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 402 403 addr = di->addr; 404 size = di->size; 405 node = di->node; 406 407 /* 408 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 409 * area is marked hotpluggable in the next iteration for the bigger 410 * chunk including the NVDIMM occupied area. 411 */ 412 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 413 continue; 414 415 /* Entry for hot-pluggable area */ 416 if (cur_addr < addr) { 417 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 418 g_assert(drc); 419 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 420 cur_addr, spapr_drc_index(drc), -1, 0); 421 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 422 nr_entries++; 423 } 424 425 /* Entry for DIMM */ 426 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 427 g_assert(drc); 428 elem = spapr_get_drconf_cell(size / lmb_size, addr, 429 spapr_drc_index(drc), node, 430 (SPAPR_LMB_FLAGS_ASSIGNED | 431 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 432 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 433 nr_entries++; 434 cur_addr = addr + size; 435 } 436 437 /* Entry for remaining hotpluggable area */ 438 if (cur_addr < mem_end) { 439 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 440 g_assert(drc); 441 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 442 cur_addr, spapr_drc_index(drc), -1, 0); 443 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 444 nr_entries++; 445 } 446 447 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 448 int_buf = cur_index = g_malloc0(buf_len); 449 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 450 cur_index += sizeof(nr_entries); 451 452 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 453 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 454 cur_index += sizeof(elem->cell); 455 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 456 g_free(elem); 457 } 458 459 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 460 g_free(int_buf); 461 if (ret < 0) { 462 return -1; 463 } 464 return 0; 465 } 466 467 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 468 int offset, MemoryDeviceInfoList *dimms) 469 { 470 MachineState *machine = MACHINE(spapr); 471 int i, ret; 472 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 473 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 474 uint32_t nr_lmbs = (machine->device_memory->base + 475 memory_region_size(&machine->device_memory->mr)) / 476 lmb_size; 477 uint32_t *int_buf, *cur_index, buf_len; 478 479 /* 480 * Allocate enough buffer size to fit in ibm,dynamic-memory 481 */ 482 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 483 cur_index = int_buf = g_malloc0(buf_len); 484 int_buf[0] = cpu_to_be32(nr_lmbs); 485 cur_index++; 486 for (i = 0; i < nr_lmbs; i++) { 487 uint64_t addr = i * lmb_size; 488 uint32_t *dynamic_memory = cur_index; 489 490 if (i >= device_lmb_start) { 491 SpaprDrc *drc; 492 493 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 494 g_assert(drc); 495 496 dynamic_memory[0] = cpu_to_be32(addr >> 32); 497 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 498 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 499 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 500 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 501 if (memory_region_present(get_system_memory(), addr)) { 502 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 503 } else { 504 dynamic_memory[5] = cpu_to_be32(0); 505 } 506 } else { 507 /* 508 * LMB information for RMA, boot time RAM and gap b/n RAM and 509 * device memory region -- all these are marked as reserved 510 * and as having no valid DRC. 511 */ 512 dynamic_memory[0] = cpu_to_be32(addr >> 32); 513 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 514 dynamic_memory[2] = cpu_to_be32(0); 515 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 516 dynamic_memory[4] = cpu_to_be32(-1); 517 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 518 SPAPR_LMB_FLAGS_DRC_INVALID); 519 } 520 521 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 522 } 523 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 524 g_free(int_buf); 525 if (ret < 0) { 526 return -1; 527 } 528 return 0; 529 } 530 531 /* 532 * Adds ibm,dynamic-reconfiguration-memory node. 533 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 534 * of this device tree node. 535 */ 536 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 537 void *fdt) 538 { 539 MachineState *machine = MACHINE(spapr); 540 int ret, offset; 541 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 542 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 543 cpu_to_be32(lmb_size & 0xffffffff)}; 544 MemoryDeviceInfoList *dimms = NULL; 545 546 /* 547 * Don't create the node if there is no device memory 548 */ 549 if (machine->ram_size == machine->maxram_size) { 550 return 0; 551 } 552 553 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 554 555 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 556 sizeof(prop_lmb_size)); 557 if (ret < 0) { 558 return ret; 559 } 560 561 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 562 if (ret < 0) { 563 return ret; 564 } 565 566 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 567 if (ret < 0) { 568 return ret; 569 } 570 571 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 572 dimms = qmp_memory_device_list(); 573 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 574 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 575 } else { 576 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 577 } 578 qapi_free_MemoryDeviceInfoList(dimms); 579 580 if (ret < 0) { 581 return ret; 582 } 583 584 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 585 586 return ret; 587 } 588 589 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 590 { 591 MachineState *machine = MACHINE(spapr); 592 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 593 hwaddr mem_start, node_size; 594 int i, nb_nodes = machine->numa_state->num_nodes; 595 NodeInfo *nodes = machine->numa_state->nodes; 596 597 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 598 if (!nodes[i].node_mem) { 599 continue; 600 } 601 if (mem_start >= machine->ram_size) { 602 node_size = 0; 603 } else { 604 node_size = nodes[i].node_mem; 605 if (node_size > machine->ram_size - mem_start) { 606 node_size = machine->ram_size - mem_start; 607 } 608 } 609 if (!mem_start) { 610 /* spapr_machine_init() checks for rma_size <= node0_size 611 * already */ 612 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 613 mem_start += spapr->rma_size; 614 node_size -= spapr->rma_size; 615 } 616 for ( ; node_size; ) { 617 hwaddr sizetmp = pow2floor(node_size); 618 619 /* mem_start != 0 here */ 620 if (ctzl(mem_start) < ctzl(sizetmp)) { 621 sizetmp = 1ULL << ctzl(mem_start); 622 } 623 624 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 625 node_size -= sizetmp; 626 mem_start += sizetmp; 627 } 628 } 629 630 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 631 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 632 int ret; 633 634 g_assert(smc->dr_lmb_enabled); 635 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 636 if (ret) { 637 return ret; 638 } 639 } 640 641 return 0; 642 } 643 644 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 645 SpaprMachineState *spapr) 646 { 647 MachineState *ms = MACHINE(spapr); 648 PowerPCCPU *cpu = POWERPC_CPU(cs); 649 CPUPPCState *env = &cpu->env; 650 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 651 int index = spapr_get_vcpu_id(cpu); 652 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 653 0xffffffff, 0xffffffff}; 654 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 655 : SPAPR_TIMEBASE_FREQ; 656 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 657 uint32_t page_sizes_prop[64]; 658 size_t page_sizes_prop_size; 659 unsigned int smp_threads = ms->smp.threads; 660 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 661 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 662 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 663 SpaprDrc *drc; 664 int drc_index; 665 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 666 int i; 667 668 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 669 if (drc) { 670 drc_index = spapr_drc_index(drc); 671 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 672 } 673 674 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 675 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 676 677 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 678 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 679 env->dcache_line_size))); 680 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 681 env->dcache_line_size))); 682 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 683 env->icache_line_size))); 684 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 685 env->icache_line_size))); 686 687 if (pcc->l1_dcache_size) { 688 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 689 pcc->l1_dcache_size))); 690 } else { 691 warn_report("Unknown L1 dcache size for cpu"); 692 } 693 if (pcc->l1_icache_size) { 694 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 695 pcc->l1_icache_size))); 696 } else { 697 warn_report("Unknown L1 icache size for cpu"); 698 } 699 700 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 701 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 703 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 705 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 706 707 if (env->spr_cb[SPR_PURR].oea_read) { 708 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 709 } 710 if (env->spr_cb[SPR_SPURR].oea_read) { 711 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 712 } 713 714 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 715 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 716 segs, sizeof(segs)))); 717 } 718 719 /* Advertise VSX (vector extensions) if available 720 * 1 == VMX / Altivec available 721 * 2 == VSX available 722 * 723 * Only CPUs for which we create core types in spapr_cpu_core.c 724 * are possible, and all of those have VMX */ 725 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 726 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 727 } else { 728 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 729 } 730 731 /* Advertise DFP (Decimal Floating Point) if available 732 * 0 / no property == no DFP 733 * 1 == DFP available */ 734 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 735 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 736 } 737 738 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 739 sizeof(page_sizes_prop)); 740 if (page_sizes_prop_size) { 741 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 742 page_sizes_prop, page_sizes_prop_size))); 743 } 744 745 spapr_dt_pa_features(spapr, cpu, fdt, offset); 746 747 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 748 cs->cpu_index / vcpus_per_socket))); 749 750 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 751 pft_size_prop, sizeof(pft_size_prop)))); 752 753 if (ms->numa_state->num_nodes > 1) { 754 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 755 } 756 757 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 758 759 if (pcc->radix_page_info) { 760 for (i = 0; i < pcc->radix_page_info->count; i++) { 761 radix_AP_encodings[i] = 762 cpu_to_be32(pcc->radix_page_info->entries[i]); 763 } 764 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 765 radix_AP_encodings, 766 pcc->radix_page_info->count * 767 sizeof(radix_AP_encodings[0])))); 768 } 769 770 /* 771 * We set this property to let the guest know that it can use the large 772 * decrementer and its width in bits. 773 */ 774 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 775 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 776 pcc->lrg_decr_bits))); 777 } 778 779 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 780 { 781 CPUState **rev; 782 CPUState *cs; 783 int n_cpus; 784 int cpus_offset; 785 int i; 786 787 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 788 _FDT(cpus_offset); 789 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 790 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 791 792 /* 793 * We walk the CPUs in reverse order to ensure that CPU DT nodes 794 * created by fdt_add_subnode() end up in the right order in FDT 795 * for the guest kernel the enumerate the CPUs correctly. 796 * 797 * The CPU list cannot be traversed in reverse order, so we need 798 * to do extra work. 799 */ 800 n_cpus = 0; 801 rev = NULL; 802 CPU_FOREACH(cs) { 803 rev = g_renew(CPUState *, rev, n_cpus + 1); 804 rev[n_cpus++] = cs; 805 } 806 807 for (i = n_cpus - 1; i >= 0; i--) { 808 CPUState *cs = rev[i]; 809 PowerPCCPU *cpu = POWERPC_CPU(cs); 810 int index = spapr_get_vcpu_id(cpu); 811 DeviceClass *dc = DEVICE_GET_CLASS(cs); 812 g_autofree char *nodename = NULL; 813 int offset; 814 815 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 816 continue; 817 } 818 819 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 820 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 821 _FDT(offset); 822 spapr_dt_cpu(cs, fdt, offset, spapr); 823 } 824 825 g_free(rev); 826 } 827 828 static int spapr_dt_rng(void *fdt) 829 { 830 int node; 831 int ret; 832 833 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 834 if (node <= 0) { 835 return -1; 836 } 837 ret = fdt_setprop_string(fdt, node, "device_type", 838 "ibm,platform-facilities"); 839 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 840 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 841 842 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 843 if (node <= 0) { 844 return -1; 845 } 846 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 847 848 return ret ? -1 : 0; 849 } 850 851 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 852 { 853 MachineState *ms = MACHINE(spapr); 854 int rtas; 855 GString *hypertas = g_string_sized_new(256); 856 GString *qemu_hypertas = g_string_sized_new(256); 857 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 858 memory_region_size(&MACHINE(spapr)->device_memory->mr); 859 uint32_t lrdr_capacity[] = { 860 cpu_to_be32(max_device_addr >> 32), 861 cpu_to_be32(max_device_addr & 0xffffffff), 862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 863 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 864 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 865 }; 866 867 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 868 869 /* hypertas */ 870 add_str(hypertas, "hcall-pft"); 871 add_str(hypertas, "hcall-term"); 872 add_str(hypertas, "hcall-dabr"); 873 add_str(hypertas, "hcall-interrupt"); 874 add_str(hypertas, "hcall-tce"); 875 add_str(hypertas, "hcall-vio"); 876 add_str(hypertas, "hcall-splpar"); 877 add_str(hypertas, "hcall-join"); 878 add_str(hypertas, "hcall-bulk"); 879 add_str(hypertas, "hcall-set-mode"); 880 add_str(hypertas, "hcall-sprg0"); 881 add_str(hypertas, "hcall-copy"); 882 add_str(hypertas, "hcall-debug"); 883 add_str(hypertas, "hcall-vphn"); 884 add_str(qemu_hypertas, "hcall-memop1"); 885 886 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 887 add_str(hypertas, "hcall-multi-tce"); 888 } 889 890 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 891 add_str(hypertas, "hcall-hpt-resize"); 892 } 893 894 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 895 hypertas->str, hypertas->len)); 896 g_string_free(hypertas, TRUE); 897 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 898 qemu_hypertas->str, qemu_hypertas->len)); 899 g_string_free(qemu_hypertas, TRUE); 900 901 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 902 903 /* 904 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 905 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 906 * 907 * The system reset requirements are driven by existing Linux and PowerVM 908 * implementation which (contrary to PAPR) saves r3 in the error log 909 * structure like machine check, so Linux expects to find the saved r3 910 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 911 * does not look at the error value). 912 * 913 * System reset interrupts are not subject to interlock like machine 914 * check, so this memory area could be corrupted if the sreset is 915 * interrupted by a machine check (or vice versa) if it was shared. To 916 * prevent this, system reset uses per-CPU areas for the sreset save 917 * area. A system reset that interrupts a system reset handler could 918 * still overwrite this area, but Linux doesn't try to recover in that 919 * case anyway. 920 * 921 * The extra 8 bytes is required because Linux's FWNMI error log check 922 * is off-by-one. 923 */ 924 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 925 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 926 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 927 RTAS_ERROR_LOG_MAX)); 928 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 929 RTAS_EVENT_SCAN_RATE)); 930 931 g_assert(msi_nonbroken); 932 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 933 934 /* 935 * According to PAPR, rtas ibm,os-term does not guarantee a return 936 * back to the guest cpu. 937 * 938 * While an additional ibm,extended-os-term property indicates 939 * that rtas call return will always occur. Set this property. 940 */ 941 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 942 943 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 944 lrdr_capacity, sizeof(lrdr_capacity))); 945 946 spapr_dt_rtas_tokens(fdt, rtas); 947 } 948 949 /* 950 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 951 * and the XIVE features that the guest may request and thus the valid 952 * values for bytes 23..26 of option vector 5: 953 */ 954 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 955 int chosen) 956 { 957 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 958 959 char val[2 * 4] = { 960 23, 0x00, /* XICS / XIVE mode */ 961 24, 0x00, /* Hash/Radix, filled in below. */ 962 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 963 26, 0x40, /* Radix options: GTSE == yes. */ 964 }; 965 966 if (spapr->irq->xics && spapr->irq->xive) { 967 val[1] = SPAPR_OV5_XIVE_BOTH; 968 } else if (spapr->irq->xive) { 969 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 970 } else { 971 assert(spapr->irq->xics); 972 val[1] = SPAPR_OV5_XIVE_LEGACY; 973 } 974 975 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 976 first_ppc_cpu->compat_pvr)) { 977 /* 978 * If we're in a pre POWER9 compat mode then the guest should 979 * do hash and use the legacy interrupt mode 980 */ 981 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 982 val[3] = 0x00; /* Hash */ 983 } else if (kvm_enabled()) { 984 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 985 val[3] = 0x80; /* OV5_MMU_BOTH */ 986 } else if (kvmppc_has_cap_mmu_radix()) { 987 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 988 } else { 989 val[3] = 0x00; /* Hash */ 990 } 991 } else { 992 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 993 val[3] = 0xC0; 994 } 995 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 996 val, sizeof(val))); 997 } 998 999 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1000 { 1001 MachineState *machine = MACHINE(spapr); 1002 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1003 int chosen; 1004 1005 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1006 1007 if (reset) { 1008 const char *boot_device = machine->boot_order; 1009 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1010 size_t cb = 0; 1011 char *bootlist = get_boot_devices_list(&cb); 1012 1013 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1014 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1015 machine->kernel_cmdline)); 1016 } 1017 1018 if (spapr->initrd_size) { 1019 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1020 spapr->initrd_base)); 1021 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1022 spapr->initrd_base + spapr->initrd_size)); 1023 } 1024 1025 if (spapr->kernel_size) { 1026 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1027 cpu_to_be64(spapr->kernel_size) }; 1028 1029 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1030 &kprop, sizeof(kprop))); 1031 if (spapr->kernel_le) { 1032 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1033 } 1034 } 1035 if (boot_menu) { 1036 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1037 } 1038 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1039 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1040 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1041 1042 if (cb && bootlist) { 1043 int i; 1044 1045 for (i = 0; i < cb; i++) { 1046 if (bootlist[i] == '\n') { 1047 bootlist[i] = ' '; 1048 } 1049 } 1050 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1051 } 1052 1053 if (boot_device && strlen(boot_device)) { 1054 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1055 } 1056 1057 if (!spapr->has_graphics && stdout_path) { 1058 /* 1059 * "linux,stdout-path" and "stdout" properties are 1060 * deprecated by linux kernel. New platforms should only 1061 * use the "stdout-path" property. Set the new property 1062 * and continue using older property to remain compatible 1063 * with the existing firmware. 1064 */ 1065 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1066 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1067 } 1068 1069 /* 1070 * We can deal with BAR reallocation just fine, advertise it 1071 * to the guest 1072 */ 1073 if (smc->linux_pci_probe) { 1074 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1075 } 1076 1077 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1078 1079 g_free(stdout_path); 1080 g_free(bootlist); 1081 } 1082 1083 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1084 } 1085 1086 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1087 { 1088 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1089 * KVM to work under pHyp with some guest co-operation */ 1090 int hypervisor; 1091 uint8_t hypercall[16]; 1092 1093 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1094 /* indicate KVM hypercall interface */ 1095 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1096 if (kvmppc_has_cap_fixup_hcalls()) { 1097 /* 1098 * Older KVM versions with older guest kernels were broken 1099 * with the magic page, don't allow the guest to map it. 1100 */ 1101 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1102 sizeof(hypercall))) { 1103 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1104 hypercall, sizeof(hypercall))); 1105 } 1106 } 1107 } 1108 1109 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1110 { 1111 MachineState *machine = MACHINE(spapr); 1112 MachineClass *mc = MACHINE_GET_CLASS(machine); 1113 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1114 uint32_t root_drc_type_mask = 0; 1115 int ret; 1116 void *fdt; 1117 SpaprPhbState *phb; 1118 char *buf; 1119 1120 fdt = g_malloc0(space); 1121 _FDT((fdt_create_empty_tree(fdt, space))); 1122 1123 /* Root node */ 1124 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1125 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1126 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1127 1128 /* Guest UUID & Name*/ 1129 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1130 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1131 if (qemu_uuid_set) { 1132 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1133 } 1134 g_free(buf); 1135 1136 if (qemu_get_vm_name()) { 1137 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1138 qemu_get_vm_name())); 1139 } 1140 1141 /* Host Model & Serial Number */ 1142 if (spapr->host_model) { 1143 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1144 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1145 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1146 g_free(buf); 1147 } 1148 1149 if (spapr->host_serial) { 1150 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1151 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1153 g_free(buf); 1154 } 1155 1156 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1157 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1158 1159 /* /interrupt controller */ 1160 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1161 1162 ret = spapr_dt_memory(spapr, fdt); 1163 if (ret < 0) { 1164 error_report("couldn't setup memory nodes in fdt"); 1165 exit(1); 1166 } 1167 1168 /* /vdevice */ 1169 spapr_dt_vdevice(spapr->vio_bus, fdt); 1170 1171 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1172 ret = spapr_dt_rng(fdt); 1173 if (ret < 0) { 1174 error_report("could not set up rng device in the fdt"); 1175 exit(1); 1176 } 1177 } 1178 1179 QLIST_FOREACH(phb, &spapr->phbs, list) { 1180 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1181 if (ret < 0) { 1182 error_report("couldn't setup PCI devices in fdt"); 1183 exit(1); 1184 } 1185 } 1186 1187 spapr_dt_cpus(fdt, spapr); 1188 1189 /* ibm,drc-indexes and friends */ 1190 if (smc->dr_lmb_enabled) { 1191 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1192 } 1193 if (smc->dr_phb_enabled) { 1194 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1195 } 1196 if (mc->nvdimm_supported) { 1197 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1198 } 1199 if (root_drc_type_mask) { 1200 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1201 } 1202 1203 if (mc->has_hotpluggable_cpus) { 1204 int offset = fdt_path_offset(fdt, "/cpus"); 1205 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1206 if (ret < 0) { 1207 error_report("Couldn't set up CPU DR device tree properties"); 1208 exit(1); 1209 } 1210 } 1211 1212 /* /event-sources */ 1213 spapr_dt_events(spapr, fdt); 1214 1215 /* /rtas */ 1216 spapr_dt_rtas(spapr, fdt); 1217 1218 /* /chosen */ 1219 spapr_dt_chosen(spapr, fdt, reset); 1220 1221 /* /hypervisor */ 1222 if (kvm_enabled()) { 1223 spapr_dt_hypervisor(spapr, fdt); 1224 } 1225 1226 /* Build memory reserve map */ 1227 if (reset) { 1228 if (spapr->kernel_size) { 1229 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1230 spapr->kernel_size))); 1231 } 1232 if (spapr->initrd_size) { 1233 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1234 spapr->initrd_size))); 1235 } 1236 } 1237 1238 /* NVDIMM devices */ 1239 if (mc->nvdimm_supported) { 1240 spapr_dt_persistent_memory(spapr, fdt); 1241 } 1242 1243 return fdt; 1244 } 1245 1246 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1247 { 1248 SpaprMachineState *spapr = opaque; 1249 1250 return (addr & 0x0fffffff) + spapr->kernel_addr; 1251 } 1252 1253 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1254 PowerPCCPU *cpu) 1255 { 1256 CPUPPCState *env = &cpu->env; 1257 1258 /* The TCG path should also be holding the BQL at this point */ 1259 g_assert(qemu_mutex_iothread_locked()); 1260 1261 if (msr_pr) { 1262 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1263 env->gpr[3] = H_PRIVILEGE; 1264 } else { 1265 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1266 } 1267 } 1268 1269 struct LPCRSyncState { 1270 target_ulong value; 1271 target_ulong mask; 1272 }; 1273 1274 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1275 { 1276 struct LPCRSyncState *s = arg.host_ptr; 1277 PowerPCCPU *cpu = POWERPC_CPU(cs); 1278 CPUPPCState *env = &cpu->env; 1279 target_ulong lpcr; 1280 1281 cpu_synchronize_state(cs); 1282 lpcr = env->spr[SPR_LPCR]; 1283 lpcr &= ~s->mask; 1284 lpcr |= s->value; 1285 ppc_store_lpcr(cpu, lpcr); 1286 } 1287 1288 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1289 { 1290 CPUState *cs; 1291 struct LPCRSyncState s = { 1292 .value = value, 1293 .mask = mask 1294 }; 1295 CPU_FOREACH(cs) { 1296 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1297 } 1298 } 1299 1300 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1301 { 1302 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1303 1304 /* Copy PATE1:GR into PATE0:HR */ 1305 entry->dw0 = spapr->patb_entry & PATE0_HR; 1306 entry->dw1 = spapr->patb_entry; 1307 } 1308 1309 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1310 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1311 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1312 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1313 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1314 1315 /* 1316 * Get the fd to access the kernel htab, re-opening it if necessary 1317 */ 1318 static int get_htab_fd(SpaprMachineState *spapr) 1319 { 1320 Error *local_err = NULL; 1321 1322 if (spapr->htab_fd >= 0) { 1323 return spapr->htab_fd; 1324 } 1325 1326 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1327 if (spapr->htab_fd < 0) { 1328 error_report_err(local_err); 1329 } 1330 1331 return spapr->htab_fd; 1332 } 1333 1334 void close_htab_fd(SpaprMachineState *spapr) 1335 { 1336 if (spapr->htab_fd >= 0) { 1337 close(spapr->htab_fd); 1338 } 1339 spapr->htab_fd = -1; 1340 } 1341 1342 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1343 { 1344 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1345 1346 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1347 } 1348 1349 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1350 { 1351 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1352 1353 assert(kvm_enabled()); 1354 1355 if (!spapr->htab) { 1356 return 0; 1357 } 1358 1359 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1360 } 1361 1362 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1363 hwaddr ptex, int n) 1364 { 1365 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1366 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1367 1368 if (!spapr->htab) { 1369 /* 1370 * HTAB is controlled by KVM. Fetch into temporary buffer 1371 */ 1372 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1373 kvmppc_read_hptes(hptes, ptex, n); 1374 return hptes; 1375 } 1376 1377 /* 1378 * HTAB is controlled by QEMU. Just point to the internally 1379 * accessible PTEG. 1380 */ 1381 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1382 } 1383 1384 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1385 const ppc_hash_pte64_t *hptes, 1386 hwaddr ptex, int n) 1387 { 1388 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1389 1390 if (!spapr->htab) { 1391 g_free((void *)hptes); 1392 } 1393 1394 /* Nothing to do for qemu managed HPT */ 1395 } 1396 1397 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1398 uint64_t pte0, uint64_t pte1) 1399 { 1400 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1401 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1402 1403 if (!spapr->htab) { 1404 kvmppc_write_hpte(ptex, pte0, pte1); 1405 } else { 1406 if (pte0 & HPTE64_V_VALID) { 1407 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1408 /* 1409 * When setting valid, we write PTE1 first. This ensures 1410 * proper synchronization with the reading code in 1411 * ppc_hash64_pteg_search() 1412 */ 1413 smp_wmb(); 1414 stq_p(spapr->htab + offset, pte0); 1415 } else { 1416 stq_p(spapr->htab + offset, pte0); 1417 /* 1418 * When clearing it we set PTE0 first. This ensures proper 1419 * synchronization with the reading code in 1420 * ppc_hash64_pteg_search() 1421 */ 1422 smp_wmb(); 1423 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1424 } 1425 } 1426 } 1427 1428 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1429 uint64_t pte1) 1430 { 1431 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1432 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1433 1434 if (!spapr->htab) { 1435 /* There should always be a hash table when this is called */ 1436 error_report("spapr_hpte_set_c called with no hash table !"); 1437 return; 1438 } 1439 1440 /* The HW performs a non-atomic byte update */ 1441 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1442 } 1443 1444 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1445 uint64_t pte1) 1446 { 1447 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1448 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1449 1450 if (!spapr->htab) { 1451 /* There should always be a hash table when this is called */ 1452 error_report("spapr_hpte_set_r called with no hash table !"); 1453 return; 1454 } 1455 1456 /* The HW performs a non-atomic byte update */ 1457 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1458 } 1459 1460 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1461 { 1462 int shift; 1463 1464 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1465 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1466 * that's much more than is needed for Linux guests */ 1467 shift = ctz64(pow2ceil(ramsize)) - 7; 1468 shift = MAX(shift, 18); /* Minimum architected size */ 1469 shift = MIN(shift, 46); /* Maximum architected size */ 1470 return shift; 1471 } 1472 1473 void spapr_free_hpt(SpaprMachineState *spapr) 1474 { 1475 g_free(spapr->htab); 1476 spapr->htab = NULL; 1477 spapr->htab_shift = 0; 1478 close_htab_fd(spapr); 1479 } 1480 1481 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1482 { 1483 ERRP_GUARD(); 1484 long rc; 1485 1486 /* Clean up any HPT info from a previous boot */ 1487 spapr_free_hpt(spapr); 1488 1489 rc = kvmppc_reset_htab(shift); 1490 1491 if (rc == -EOPNOTSUPP) { 1492 error_setg(errp, "HPT not supported in nested guests"); 1493 return -EOPNOTSUPP; 1494 } 1495 1496 if (rc < 0) { 1497 /* kernel-side HPT needed, but couldn't allocate one */ 1498 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1499 shift); 1500 error_append_hint(errp, "Try smaller maxmem?\n"); 1501 return -errno; 1502 } else if (rc > 0) { 1503 /* kernel-side HPT allocated */ 1504 if (rc != shift) { 1505 error_setg(errp, 1506 "Requested order %d HPT, but kernel allocated order %ld", 1507 shift, rc); 1508 error_append_hint(errp, "Try smaller maxmem?\n"); 1509 return -ENOSPC; 1510 } 1511 1512 spapr->htab_shift = shift; 1513 spapr->htab = NULL; 1514 } else { 1515 /* kernel-side HPT not needed, allocate in userspace instead */ 1516 size_t size = 1ULL << shift; 1517 int i; 1518 1519 spapr->htab = qemu_memalign(size, size); 1520 memset(spapr->htab, 0, size); 1521 spapr->htab_shift = shift; 1522 1523 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1524 DIRTY_HPTE(HPTE(spapr->htab, i)); 1525 } 1526 } 1527 /* We're setting up a hash table, so that means we're not radix */ 1528 spapr->patb_entry = 0; 1529 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1530 return 0; 1531 } 1532 1533 void spapr_setup_hpt(SpaprMachineState *spapr) 1534 { 1535 int hpt_shift; 1536 1537 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1538 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1539 } else { 1540 uint64_t current_ram_size; 1541 1542 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1543 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1544 } 1545 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1546 1547 if (kvm_enabled()) { 1548 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1549 1550 /* Check our RMA fits in the possible VRMA */ 1551 if (vrma_limit < spapr->rma_size) { 1552 error_report("Unable to create %" HWADDR_PRIu 1553 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1554 spapr->rma_size / MiB, vrma_limit / MiB); 1555 exit(EXIT_FAILURE); 1556 } 1557 } 1558 } 1559 1560 static void spapr_machine_reset(MachineState *machine) 1561 { 1562 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1563 PowerPCCPU *first_ppc_cpu; 1564 hwaddr fdt_addr; 1565 void *fdt; 1566 int rc; 1567 1568 pef_kvm_reset(machine->cgs, &error_fatal); 1569 spapr_caps_apply(spapr); 1570 1571 first_ppc_cpu = POWERPC_CPU(first_cpu); 1572 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1573 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1574 spapr->max_compat_pvr)) { 1575 /* 1576 * If using KVM with radix mode available, VCPUs can be started 1577 * without a HPT because KVM will start them in radix mode. 1578 * Set the GR bit in PATE so that we know there is no HPT. 1579 */ 1580 spapr->patb_entry = PATE1_GR; 1581 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1582 } else { 1583 spapr_setup_hpt(spapr); 1584 } 1585 1586 qemu_devices_reset(); 1587 1588 spapr_ovec_cleanup(spapr->ov5_cas); 1589 spapr->ov5_cas = spapr_ovec_new(); 1590 1591 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1592 1593 /* 1594 * This is fixing some of the default configuration of the XIVE 1595 * devices. To be called after the reset of the machine devices. 1596 */ 1597 spapr_irq_reset(spapr, &error_fatal); 1598 1599 /* 1600 * There is no CAS under qtest. Simulate one to please the code that 1601 * depends on spapr->ov5_cas. This is especially needed to test device 1602 * unplug, so we do that before resetting the DRCs. 1603 */ 1604 if (qtest_enabled()) { 1605 spapr_ovec_cleanup(spapr->ov5_cas); 1606 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1607 } 1608 1609 /* DRC reset may cause a device to be unplugged. This will cause troubles 1610 * if this device is used by another device (eg, a running vhost backend 1611 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1612 * situations, we reset DRCs after all devices have been reset. 1613 */ 1614 spapr_drc_reset_all(spapr); 1615 1616 spapr_clear_pending_events(spapr); 1617 1618 /* 1619 * We place the device tree and RTAS just below either the top of the RMA, 1620 * or just below 2GB, whichever is lower, so that it can be 1621 * processed with 32-bit real mode code if necessary 1622 */ 1623 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1624 1625 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1626 1627 rc = fdt_pack(fdt); 1628 1629 /* Should only fail if we've built a corrupted tree */ 1630 assert(rc == 0); 1631 1632 /* Load the fdt */ 1633 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1634 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1635 g_free(spapr->fdt_blob); 1636 spapr->fdt_size = fdt_totalsize(fdt); 1637 spapr->fdt_initial_size = spapr->fdt_size; 1638 spapr->fdt_blob = fdt; 1639 1640 /* Set up the entry state */ 1641 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1642 first_ppc_cpu->env.gpr[5] = 0; 1643 1644 spapr->fwnmi_system_reset_addr = -1; 1645 spapr->fwnmi_machine_check_addr = -1; 1646 spapr->fwnmi_machine_check_interlock = -1; 1647 1648 /* Signal all vCPUs waiting on this condition */ 1649 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1650 1651 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1652 } 1653 1654 static void spapr_create_nvram(SpaprMachineState *spapr) 1655 { 1656 DeviceState *dev = qdev_new("spapr-nvram"); 1657 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1658 1659 if (dinfo) { 1660 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1661 &error_fatal); 1662 } 1663 1664 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1665 1666 spapr->nvram = (struct SpaprNvram *)dev; 1667 } 1668 1669 static void spapr_rtc_create(SpaprMachineState *spapr) 1670 { 1671 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1672 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1673 &error_fatal, NULL); 1674 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1675 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1676 "date"); 1677 } 1678 1679 /* Returns whether we want to use VGA or not */ 1680 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1681 { 1682 switch (vga_interface_type) { 1683 case VGA_NONE: 1684 return false; 1685 case VGA_DEVICE: 1686 return true; 1687 case VGA_STD: 1688 case VGA_VIRTIO: 1689 case VGA_CIRRUS: 1690 return pci_vga_init(pci_bus) != NULL; 1691 default: 1692 error_setg(errp, 1693 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1694 return false; 1695 } 1696 } 1697 1698 static int spapr_pre_load(void *opaque) 1699 { 1700 int rc; 1701 1702 rc = spapr_caps_pre_load(opaque); 1703 if (rc) { 1704 return rc; 1705 } 1706 1707 return 0; 1708 } 1709 1710 static int spapr_post_load(void *opaque, int version_id) 1711 { 1712 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1713 int err = 0; 1714 1715 err = spapr_caps_post_migration(spapr); 1716 if (err) { 1717 return err; 1718 } 1719 1720 /* 1721 * In earlier versions, there was no separate qdev for the PAPR 1722 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1723 * So when migrating from those versions, poke the incoming offset 1724 * value into the RTC device 1725 */ 1726 if (version_id < 3) { 1727 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1728 if (err) { 1729 return err; 1730 } 1731 } 1732 1733 if (kvm_enabled() && spapr->patb_entry) { 1734 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1735 bool radix = !!(spapr->patb_entry & PATE1_GR); 1736 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1737 1738 /* 1739 * Update LPCR:HR and UPRT as they may not be set properly in 1740 * the stream 1741 */ 1742 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1743 LPCR_HR | LPCR_UPRT); 1744 1745 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1746 if (err) { 1747 error_report("Process table config unsupported by the host"); 1748 return -EINVAL; 1749 } 1750 } 1751 1752 err = spapr_irq_post_load(spapr, version_id); 1753 if (err) { 1754 return err; 1755 } 1756 1757 return err; 1758 } 1759 1760 static int spapr_pre_save(void *opaque) 1761 { 1762 int rc; 1763 1764 rc = spapr_caps_pre_save(opaque); 1765 if (rc) { 1766 return rc; 1767 } 1768 1769 return 0; 1770 } 1771 1772 static bool version_before_3(void *opaque, int version_id) 1773 { 1774 return version_id < 3; 1775 } 1776 1777 static bool spapr_pending_events_needed(void *opaque) 1778 { 1779 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1780 return !QTAILQ_EMPTY(&spapr->pending_events); 1781 } 1782 1783 static const VMStateDescription vmstate_spapr_event_entry = { 1784 .name = "spapr_event_log_entry", 1785 .version_id = 1, 1786 .minimum_version_id = 1, 1787 .fields = (VMStateField[]) { 1788 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1789 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1790 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1791 NULL, extended_length), 1792 VMSTATE_END_OF_LIST() 1793 }, 1794 }; 1795 1796 static const VMStateDescription vmstate_spapr_pending_events = { 1797 .name = "spapr_pending_events", 1798 .version_id = 1, 1799 .minimum_version_id = 1, 1800 .needed = spapr_pending_events_needed, 1801 .fields = (VMStateField[]) { 1802 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1803 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1804 VMSTATE_END_OF_LIST() 1805 }, 1806 }; 1807 1808 static bool spapr_ov5_cas_needed(void *opaque) 1809 { 1810 SpaprMachineState *spapr = opaque; 1811 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1812 bool cas_needed; 1813 1814 /* Prior to the introduction of SpaprOptionVector, we had two option 1815 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1816 * Both of these options encode machine topology into the device-tree 1817 * in such a way that the now-booted OS should still be able to interact 1818 * appropriately with QEMU regardless of what options were actually 1819 * negotiatied on the source side. 1820 * 1821 * As such, we can avoid migrating the CAS-negotiated options if these 1822 * are the only options available on the current machine/platform. 1823 * Since these are the only options available for pseries-2.7 and 1824 * earlier, this allows us to maintain old->new/new->old migration 1825 * compatibility. 1826 * 1827 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1828 * via default pseries-2.8 machines and explicit command-line parameters. 1829 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1830 * of the actual CAS-negotiated values to continue working properly. For 1831 * example, availability of memory unplug depends on knowing whether 1832 * OV5_HP_EVT was negotiated via CAS. 1833 * 1834 * Thus, for any cases where the set of available CAS-negotiatable 1835 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1836 * include the CAS-negotiated options in the migration stream, unless 1837 * if they affect boot time behaviour only. 1838 */ 1839 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1840 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1841 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1842 1843 /* We need extra information if we have any bits outside the mask 1844 * defined above */ 1845 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1846 1847 spapr_ovec_cleanup(ov5_mask); 1848 1849 return cas_needed; 1850 } 1851 1852 static const VMStateDescription vmstate_spapr_ov5_cas = { 1853 .name = "spapr_option_vector_ov5_cas", 1854 .version_id = 1, 1855 .minimum_version_id = 1, 1856 .needed = spapr_ov5_cas_needed, 1857 .fields = (VMStateField[]) { 1858 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1859 vmstate_spapr_ovec, SpaprOptionVector), 1860 VMSTATE_END_OF_LIST() 1861 }, 1862 }; 1863 1864 static bool spapr_patb_entry_needed(void *opaque) 1865 { 1866 SpaprMachineState *spapr = opaque; 1867 1868 return !!spapr->patb_entry; 1869 } 1870 1871 static const VMStateDescription vmstate_spapr_patb_entry = { 1872 .name = "spapr_patb_entry", 1873 .version_id = 1, 1874 .minimum_version_id = 1, 1875 .needed = spapr_patb_entry_needed, 1876 .fields = (VMStateField[]) { 1877 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1878 VMSTATE_END_OF_LIST() 1879 }, 1880 }; 1881 1882 static bool spapr_irq_map_needed(void *opaque) 1883 { 1884 SpaprMachineState *spapr = opaque; 1885 1886 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1887 } 1888 1889 static const VMStateDescription vmstate_spapr_irq_map = { 1890 .name = "spapr_irq_map", 1891 .version_id = 1, 1892 .minimum_version_id = 1, 1893 .needed = spapr_irq_map_needed, 1894 .fields = (VMStateField[]) { 1895 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1896 VMSTATE_END_OF_LIST() 1897 }, 1898 }; 1899 1900 static bool spapr_dtb_needed(void *opaque) 1901 { 1902 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1903 1904 return smc->update_dt_enabled; 1905 } 1906 1907 static int spapr_dtb_pre_load(void *opaque) 1908 { 1909 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1910 1911 g_free(spapr->fdt_blob); 1912 spapr->fdt_blob = NULL; 1913 spapr->fdt_size = 0; 1914 1915 return 0; 1916 } 1917 1918 static const VMStateDescription vmstate_spapr_dtb = { 1919 .name = "spapr_dtb", 1920 .version_id = 1, 1921 .minimum_version_id = 1, 1922 .needed = spapr_dtb_needed, 1923 .pre_load = spapr_dtb_pre_load, 1924 .fields = (VMStateField[]) { 1925 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1926 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1927 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1928 fdt_size), 1929 VMSTATE_END_OF_LIST() 1930 }, 1931 }; 1932 1933 static bool spapr_fwnmi_needed(void *opaque) 1934 { 1935 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1936 1937 return spapr->fwnmi_machine_check_addr != -1; 1938 } 1939 1940 static int spapr_fwnmi_pre_save(void *opaque) 1941 { 1942 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1943 1944 /* 1945 * Check if machine check handling is in progress and print a 1946 * warning message. 1947 */ 1948 if (spapr->fwnmi_machine_check_interlock != -1) { 1949 warn_report("A machine check is being handled during migration. The" 1950 "handler may run and log hardware error on the destination"); 1951 } 1952 1953 return 0; 1954 } 1955 1956 static const VMStateDescription vmstate_spapr_fwnmi = { 1957 .name = "spapr_fwnmi", 1958 .version_id = 1, 1959 .minimum_version_id = 1, 1960 .needed = spapr_fwnmi_needed, 1961 .pre_save = spapr_fwnmi_pre_save, 1962 .fields = (VMStateField[]) { 1963 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1964 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1965 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1966 VMSTATE_END_OF_LIST() 1967 }, 1968 }; 1969 1970 static const VMStateDescription vmstate_spapr = { 1971 .name = "spapr", 1972 .version_id = 3, 1973 .minimum_version_id = 1, 1974 .pre_load = spapr_pre_load, 1975 .post_load = spapr_post_load, 1976 .pre_save = spapr_pre_save, 1977 .fields = (VMStateField[]) { 1978 /* used to be @next_irq */ 1979 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1980 1981 /* RTC offset */ 1982 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1983 1984 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 1985 VMSTATE_END_OF_LIST() 1986 }, 1987 .subsections = (const VMStateDescription*[]) { 1988 &vmstate_spapr_ov5_cas, 1989 &vmstate_spapr_patb_entry, 1990 &vmstate_spapr_pending_events, 1991 &vmstate_spapr_cap_htm, 1992 &vmstate_spapr_cap_vsx, 1993 &vmstate_spapr_cap_dfp, 1994 &vmstate_spapr_cap_cfpc, 1995 &vmstate_spapr_cap_sbbc, 1996 &vmstate_spapr_cap_ibs, 1997 &vmstate_spapr_cap_hpt_maxpagesize, 1998 &vmstate_spapr_irq_map, 1999 &vmstate_spapr_cap_nested_kvm_hv, 2000 &vmstate_spapr_dtb, 2001 &vmstate_spapr_cap_large_decr, 2002 &vmstate_spapr_cap_ccf_assist, 2003 &vmstate_spapr_cap_fwnmi, 2004 &vmstate_spapr_fwnmi, 2005 NULL 2006 } 2007 }; 2008 2009 static int htab_save_setup(QEMUFile *f, void *opaque) 2010 { 2011 SpaprMachineState *spapr = opaque; 2012 2013 /* "Iteration" header */ 2014 if (!spapr->htab_shift) { 2015 qemu_put_be32(f, -1); 2016 } else { 2017 qemu_put_be32(f, spapr->htab_shift); 2018 } 2019 2020 if (spapr->htab) { 2021 spapr->htab_save_index = 0; 2022 spapr->htab_first_pass = true; 2023 } else { 2024 if (spapr->htab_shift) { 2025 assert(kvm_enabled()); 2026 } 2027 } 2028 2029 2030 return 0; 2031 } 2032 2033 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2034 int chunkstart, int n_valid, int n_invalid) 2035 { 2036 qemu_put_be32(f, chunkstart); 2037 qemu_put_be16(f, n_valid); 2038 qemu_put_be16(f, n_invalid); 2039 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2040 HASH_PTE_SIZE_64 * n_valid); 2041 } 2042 2043 static void htab_save_end_marker(QEMUFile *f) 2044 { 2045 qemu_put_be32(f, 0); 2046 qemu_put_be16(f, 0); 2047 qemu_put_be16(f, 0); 2048 } 2049 2050 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2051 int64_t max_ns) 2052 { 2053 bool has_timeout = max_ns != -1; 2054 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2055 int index = spapr->htab_save_index; 2056 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2057 2058 assert(spapr->htab_first_pass); 2059 2060 do { 2061 int chunkstart; 2062 2063 /* Consume invalid HPTEs */ 2064 while ((index < htabslots) 2065 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2066 CLEAN_HPTE(HPTE(spapr->htab, index)); 2067 index++; 2068 } 2069 2070 /* Consume valid HPTEs */ 2071 chunkstart = index; 2072 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2073 && HPTE_VALID(HPTE(spapr->htab, index))) { 2074 CLEAN_HPTE(HPTE(spapr->htab, index)); 2075 index++; 2076 } 2077 2078 if (index > chunkstart) { 2079 int n_valid = index - chunkstart; 2080 2081 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2082 2083 if (has_timeout && 2084 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2085 break; 2086 } 2087 } 2088 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2089 2090 if (index >= htabslots) { 2091 assert(index == htabslots); 2092 index = 0; 2093 spapr->htab_first_pass = false; 2094 } 2095 spapr->htab_save_index = index; 2096 } 2097 2098 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2099 int64_t max_ns) 2100 { 2101 bool final = max_ns < 0; 2102 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2103 int examined = 0, sent = 0; 2104 int index = spapr->htab_save_index; 2105 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2106 2107 assert(!spapr->htab_first_pass); 2108 2109 do { 2110 int chunkstart, invalidstart; 2111 2112 /* Consume non-dirty HPTEs */ 2113 while ((index < htabslots) 2114 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2115 index++; 2116 examined++; 2117 } 2118 2119 chunkstart = index; 2120 /* Consume valid dirty HPTEs */ 2121 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2122 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2123 && HPTE_VALID(HPTE(spapr->htab, index))) { 2124 CLEAN_HPTE(HPTE(spapr->htab, index)); 2125 index++; 2126 examined++; 2127 } 2128 2129 invalidstart = index; 2130 /* Consume invalid dirty HPTEs */ 2131 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2132 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2133 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2134 CLEAN_HPTE(HPTE(spapr->htab, index)); 2135 index++; 2136 examined++; 2137 } 2138 2139 if (index > chunkstart) { 2140 int n_valid = invalidstart - chunkstart; 2141 int n_invalid = index - invalidstart; 2142 2143 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2144 sent += index - chunkstart; 2145 2146 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2147 break; 2148 } 2149 } 2150 2151 if (examined >= htabslots) { 2152 break; 2153 } 2154 2155 if (index >= htabslots) { 2156 assert(index == htabslots); 2157 index = 0; 2158 } 2159 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2160 2161 if (index >= htabslots) { 2162 assert(index == htabslots); 2163 index = 0; 2164 } 2165 2166 spapr->htab_save_index = index; 2167 2168 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2169 } 2170 2171 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2172 #define MAX_KVM_BUF_SIZE 2048 2173 2174 static int htab_save_iterate(QEMUFile *f, void *opaque) 2175 { 2176 SpaprMachineState *spapr = opaque; 2177 int fd; 2178 int rc = 0; 2179 2180 /* Iteration header */ 2181 if (!spapr->htab_shift) { 2182 qemu_put_be32(f, -1); 2183 return 1; 2184 } else { 2185 qemu_put_be32(f, 0); 2186 } 2187 2188 if (!spapr->htab) { 2189 assert(kvm_enabled()); 2190 2191 fd = get_htab_fd(spapr); 2192 if (fd < 0) { 2193 return fd; 2194 } 2195 2196 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2197 if (rc < 0) { 2198 return rc; 2199 } 2200 } else if (spapr->htab_first_pass) { 2201 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2202 } else { 2203 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2204 } 2205 2206 htab_save_end_marker(f); 2207 2208 return rc; 2209 } 2210 2211 static int htab_save_complete(QEMUFile *f, void *opaque) 2212 { 2213 SpaprMachineState *spapr = opaque; 2214 int fd; 2215 2216 /* Iteration header */ 2217 if (!spapr->htab_shift) { 2218 qemu_put_be32(f, -1); 2219 return 0; 2220 } else { 2221 qemu_put_be32(f, 0); 2222 } 2223 2224 if (!spapr->htab) { 2225 int rc; 2226 2227 assert(kvm_enabled()); 2228 2229 fd = get_htab_fd(spapr); 2230 if (fd < 0) { 2231 return fd; 2232 } 2233 2234 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2235 if (rc < 0) { 2236 return rc; 2237 } 2238 } else { 2239 if (spapr->htab_first_pass) { 2240 htab_save_first_pass(f, spapr, -1); 2241 } 2242 htab_save_later_pass(f, spapr, -1); 2243 } 2244 2245 /* End marker */ 2246 htab_save_end_marker(f); 2247 2248 return 0; 2249 } 2250 2251 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2252 { 2253 SpaprMachineState *spapr = opaque; 2254 uint32_t section_hdr; 2255 int fd = -1; 2256 Error *local_err = NULL; 2257 2258 if (version_id < 1 || version_id > 1) { 2259 error_report("htab_load() bad version"); 2260 return -EINVAL; 2261 } 2262 2263 section_hdr = qemu_get_be32(f); 2264 2265 if (section_hdr == -1) { 2266 spapr_free_hpt(spapr); 2267 return 0; 2268 } 2269 2270 if (section_hdr) { 2271 int ret; 2272 2273 /* First section gives the htab size */ 2274 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2275 if (ret < 0) { 2276 error_report_err(local_err); 2277 return ret; 2278 } 2279 return 0; 2280 } 2281 2282 if (!spapr->htab) { 2283 assert(kvm_enabled()); 2284 2285 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2286 if (fd < 0) { 2287 error_report_err(local_err); 2288 return fd; 2289 } 2290 } 2291 2292 while (true) { 2293 uint32_t index; 2294 uint16_t n_valid, n_invalid; 2295 2296 index = qemu_get_be32(f); 2297 n_valid = qemu_get_be16(f); 2298 n_invalid = qemu_get_be16(f); 2299 2300 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2301 /* End of Stream */ 2302 break; 2303 } 2304 2305 if ((index + n_valid + n_invalid) > 2306 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2307 /* Bad index in stream */ 2308 error_report( 2309 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2310 index, n_valid, n_invalid, spapr->htab_shift); 2311 return -EINVAL; 2312 } 2313 2314 if (spapr->htab) { 2315 if (n_valid) { 2316 qemu_get_buffer(f, HPTE(spapr->htab, index), 2317 HASH_PTE_SIZE_64 * n_valid); 2318 } 2319 if (n_invalid) { 2320 memset(HPTE(spapr->htab, index + n_valid), 0, 2321 HASH_PTE_SIZE_64 * n_invalid); 2322 } 2323 } else { 2324 int rc; 2325 2326 assert(fd >= 0); 2327 2328 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2329 &local_err); 2330 if (rc < 0) { 2331 error_report_err(local_err); 2332 return rc; 2333 } 2334 } 2335 } 2336 2337 if (!spapr->htab) { 2338 assert(fd >= 0); 2339 close(fd); 2340 } 2341 2342 return 0; 2343 } 2344 2345 static void htab_save_cleanup(void *opaque) 2346 { 2347 SpaprMachineState *spapr = opaque; 2348 2349 close_htab_fd(spapr); 2350 } 2351 2352 static SaveVMHandlers savevm_htab_handlers = { 2353 .save_setup = htab_save_setup, 2354 .save_live_iterate = htab_save_iterate, 2355 .save_live_complete_precopy = htab_save_complete, 2356 .save_cleanup = htab_save_cleanup, 2357 .load_state = htab_load, 2358 }; 2359 2360 static void spapr_boot_set(void *opaque, const char *boot_device, 2361 Error **errp) 2362 { 2363 MachineState *machine = MACHINE(opaque); 2364 machine->boot_order = g_strdup(boot_device); 2365 } 2366 2367 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2368 { 2369 MachineState *machine = MACHINE(spapr); 2370 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2371 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2372 int i; 2373 2374 for (i = 0; i < nr_lmbs; i++) { 2375 uint64_t addr; 2376 2377 addr = i * lmb_size + machine->device_memory->base; 2378 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2379 addr / lmb_size); 2380 } 2381 } 2382 2383 /* 2384 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2385 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2386 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2387 */ 2388 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2389 { 2390 int i; 2391 2392 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2393 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2394 " is not aligned to %" PRIu64 " MiB", 2395 machine->ram_size, 2396 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2397 return; 2398 } 2399 2400 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2401 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2402 " is not aligned to %" PRIu64 " MiB", 2403 machine->ram_size, 2404 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2405 return; 2406 } 2407 2408 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2409 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2410 error_setg(errp, 2411 "Node %d memory size 0x%" PRIx64 2412 " is not aligned to %" PRIu64 " MiB", 2413 i, machine->numa_state->nodes[i].node_mem, 2414 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2415 return; 2416 } 2417 } 2418 } 2419 2420 /* find cpu slot in machine->possible_cpus by core_id */ 2421 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2422 { 2423 int index = id / ms->smp.threads; 2424 2425 if (index >= ms->possible_cpus->len) { 2426 return NULL; 2427 } 2428 if (idx) { 2429 *idx = index; 2430 } 2431 return &ms->possible_cpus->cpus[index]; 2432 } 2433 2434 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2435 { 2436 MachineState *ms = MACHINE(spapr); 2437 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2438 Error *local_err = NULL; 2439 bool vsmt_user = !!spapr->vsmt; 2440 int kvm_smt = kvmppc_smt_threads(); 2441 int ret; 2442 unsigned int smp_threads = ms->smp.threads; 2443 2444 if (!kvm_enabled() && (smp_threads > 1)) { 2445 error_setg(errp, "TCG cannot support more than 1 thread/core " 2446 "on a pseries machine"); 2447 return; 2448 } 2449 if (!is_power_of_2(smp_threads)) { 2450 error_setg(errp, "Cannot support %d threads/core on a pseries " 2451 "machine because it must be a power of 2", smp_threads); 2452 return; 2453 } 2454 2455 /* Detemine the VSMT mode to use: */ 2456 if (vsmt_user) { 2457 if (spapr->vsmt < smp_threads) { 2458 error_setg(errp, "Cannot support VSMT mode %d" 2459 " because it must be >= threads/core (%d)", 2460 spapr->vsmt, smp_threads); 2461 return; 2462 } 2463 /* In this case, spapr->vsmt has been set by the command line */ 2464 } else if (!smc->smp_threads_vsmt) { 2465 /* 2466 * Default VSMT value is tricky, because we need it to be as 2467 * consistent as possible (for migration), but this requires 2468 * changing it for at least some existing cases. We pick 8 as 2469 * the value that we'd get with KVM on POWER8, the 2470 * overwhelmingly common case in production systems. 2471 */ 2472 spapr->vsmt = MAX(8, smp_threads); 2473 } else { 2474 spapr->vsmt = smp_threads; 2475 } 2476 2477 /* KVM: If necessary, set the SMT mode: */ 2478 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2479 ret = kvmppc_set_smt_threads(spapr->vsmt); 2480 if (ret) { 2481 /* Looks like KVM isn't able to change VSMT mode */ 2482 error_setg(&local_err, 2483 "Failed to set KVM's VSMT mode to %d (errno %d)", 2484 spapr->vsmt, ret); 2485 /* We can live with that if the default one is big enough 2486 * for the number of threads, and a submultiple of the one 2487 * we want. In this case we'll waste some vcpu ids, but 2488 * behaviour will be correct */ 2489 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2490 warn_report_err(local_err); 2491 } else { 2492 if (!vsmt_user) { 2493 error_append_hint(&local_err, 2494 "On PPC, a VM with %d threads/core" 2495 " on a host with %d threads/core" 2496 " requires the use of VSMT mode %d.\n", 2497 smp_threads, kvm_smt, spapr->vsmt); 2498 } 2499 kvmppc_error_append_smt_possible_hint(&local_err); 2500 error_propagate(errp, local_err); 2501 } 2502 } 2503 } 2504 /* else TCG: nothing to do currently */ 2505 } 2506 2507 static void spapr_init_cpus(SpaprMachineState *spapr) 2508 { 2509 MachineState *machine = MACHINE(spapr); 2510 MachineClass *mc = MACHINE_GET_CLASS(machine); 2511 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2512 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2513 const CPUArchIdList *possible_cpus; 2514 unsigned int smp_cpus = machine->smp.cpus; 2515 unsigned int smp_threads = machine->smp.threads; 2516 unsigned int max_cpus = machine->smp.max_cpus; 2517 int boot_cores_nr = smp_cpus / smp_threads; 2518 int i; 2519 2520 possible_cpus = mc->possible_cpu_arch_ids(machine); 2521 if (mc->has_hotpluggable_cpus) { 2522 if (smp_cpus % smp_threads) { 2523 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2524 smp_cpus, smp_threads); 2525 exit(1); 2526 } 2527 if (max_cpus % smp_threads) { 2528 error_report("max_cpus (%u) must be multiple of threads (%u)", 2529 max_cpus, smp_threads); 2530 exit(1); 2531 } 2532 } else { 2533 if (max_cpus != smp_cpus) { 2534 error_report("This machine version does not support CPU hotplug"); 2535 exit(1); 2536 } 2537 boot_cores_nr = possible_cpus->len; 2538 } 2539 2540 if (smc->pre_2_10_has_unused_icps) { 2541 int i; 2542 2543 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2544 /* Dummy entries get deregistered when real ICPState objects 2545 * are registered during CPU core hotplug. 2546 */ 2547 pre_2_10_vmstate_register_dummy_icp(i); 2548 } 2549 } 2550 2551 for (i = 0; i < possible_cpus->len; i++) { 2552 int core_id = i * smp_threads; 2553 2554 if (mc->has_hotpluggable_cpus) { 2555 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2556 spapr_vcpu_id(spapr, core_id)); 2557 } 2558 2559 if (i < boot_cores_nr) { 2560 Object *core = object_new(type); 2561 int nr_threads = smp_threads; 2562 2563 /* Handle the partially filled core for older machine types */ 2564 if ((i + 1) * smp_threads >= smp_cpus) { 2565 nr_threads = smp_cpus - i * smp_threads; 2566 } 2567 2568 object_property_set_int(core, "nr-threads", nr_threads, 2569 &error_fatal); 2570 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2571 &error_fatal); 2572 qdev_realize(DEVICE(core), NULL, &error_fatal); 2573 2574 object_unref(core); 2575 } 2576 } 2577 } 2578 2579 static PCIHostState *spapr_create_default_phb(void) 2580 { 2581 DeviceState *dev; 2582 2583 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2584 qdev_prop_set_uint32(dev, "index", 0); 2585 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2586 2587 return PCI_HOST_BRIDGE(dev); 2588 } 2589 2590 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2591 { 2592 MachineState *machine = MACHINE(spapr); 2593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2594 hwaddr rma_size = machine->ram_size; 2595 hwaddr node0_size = spapr_node0_size(machine); 2596 2597 /* RMA has to fit in the first NUMA node */ 2598 rma_size = MIN(rma_size, node0_size); 2599 2600 /* 2601 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2602 * never exceed that 2603 */ 2604 rma_size = MIN(rma_size, 1 * TiB); 2605 2606 /* 2607 * Clamp the RMA size based on machine type. This is for 2608 * migration compatibility with older qemu versions, which limited 2609 * the RMA size for complicated and mostly bad reasons. 2610 */ 2611 if (smc->rma_limit) { 2612 rma_size = MIN(rma_size, smc->rma_limit); 2613 } 2614 2615 if (rma_size < MIN_RMA_SLOF) { 2616 error_setg(errp, 2617 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2618 "ldMiB guest RMA (Real Mode Area memory)", 2619 MIN_RMA_SLOF / MiB); 2620 return 0; 2621 } 2622 2623 return rma_size; 2624 } 2625 2626 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2627 { 2628 MachineState *machine = MACHINE(spapr); 2629 int i; 2630 2631 for (i = 0; i < machine->ram_slots; i++) { 2632 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2633 } 2634 } 2635 2636 /* pSeries LPAR / sPAPR hardware init */ 2637 static void spapr_machine_init(MachineState *machine) 2638 { 2639 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2640 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2641 MachineClass *mc = MACHINE_GET_CLASS(machine); 2642 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2643 const char *kernel_filename = machine->kernel_filename; 2644 const char *initrd_filename = machine->initrd_filename; 2645 PCIHostState *phb; 2646 int i; 2647 MemoryRegion *sysmem = get_system_memory(); 2648 long load_limit, fw_size; 2649 char *filename; 2650 Error *resize_hpt_err = NULL; 2651 2652 /* 2653 * if Secure VM (PEF) support is configured, then initialize it 2654 */ 2655 pef_kvm_init(machine->cgs, &error_fatal); 2656 2657 msi_nonbroken = true; 2658 2659 QLIST_INIT(&spapr->phbs); 2660 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2661 2662 /* Determine capabilities to run with */ 2663 spapr_caps_init(spapr); 2664 2665 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2666 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2667 /* 2668 * If the user explicitly requested a mode we should either 2669 * supply it, or fail completely (which we do below). But if 2670 * it's not set explicitly, we reset our mode to something 2671 * that works 2672 */ 2673 if (resize_hpt_err) { 2674 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2675 error_free(resize_hpt_err); 2676 resize_hpt_err = NULL; 2677 } else { 2678 spapr->resize_hpt = smc->resize_hpt_default; 2679 } 2680 } 2681 2682 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2683 2684 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2685 /* 2686 * User requested HPT resize, but this host can't supply it. Bail out 2687 */ 2688 error_report_err(resize_hpt_err); 2689 exit(1); 2690 } 2691 error_free(resize_hpt_err); 2692 2693 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2694 2695 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2696 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2697 2698 /* 2699 * VSMT must be set in order to be able to compute VCPU ids, ie to 2700 * call spapr_max_server_number() or spapr_vcpu_id(). 2701 */ 2702 spapr_set_vsmt_mode(spapr, &error_fatal); 2703 2704 /* Set up Interrupt Controller before we create the VCPUs */ 2705 spapr_irq_init(spapr, &error_fatal); 2706 2707 /* Set up containers for ibm,client-architecture-support negotiated options 2708 */ 2709 spapr->ov5 = spapr_ovec_new(); 2710 spapr->ov5_cas = spapr_ovec_new(); 2711 2712 if (smc->dr_lmb_enabled) { 2713 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2714 spapr_validate_node_memory(machine, &error_fatal); 2715 } 2716 2717 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2718 2719 /* advertise support for dedicated HP event source to guests */ 2720 if (spapr->use_hotplug_event_source) { 2721 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2722 } 2723 2724 /* advertise support for HPT resizing */ 2725 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2726 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2727 } 2728 2729 /* advertise support for ibm,dyamic-memory-v2 */ 2730 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2731 2732 /* advertise XIVE on POWER9 machines */ 2733 if (spapr->irq->xive) { 2734 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2735 } 2736 2737 /* init CPUs */ 2738 spapr_init_cpus(spapr); 2739 2740 /* 2741 * check we don't have a memory-less/cpu-less NUMA node 2742 * Firmware relies on the existing memory/cpu topology to provide the 2743 * NUMA topology to the kernel. 2744 * And the linux kernel needs to know the NUMA topology at start 2745 * to be able to hotplug CPUs later. 2746 */ 2747 if (machine->numa_state->num_nodes) { 2748 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2749 /* check for memory-less node */ 2750 if (machine->numa_state->nodes[i].node_mem == 0) { 2751 CPUState *cs; 2752 int found = 0; 2753 /* check for cpu-less node */ 2754 CPU_FOREACH(cs) { 2755 PowerPCCPU *cpu = POWERPC_CPU(cs); 2756 if (cpu->node_id == i) { 2757 found = 1; 2758 break; 2759 } 2760 } 2761 /* memory-less and cpu-less node */ 2762 if (!found) { 2763 error_report( 2764 "Memory-less/cpu-less nodes are not supported (node %d)", 2765 i); 2766 exit(1); 2767 } 2768 } 2769 } 2770 2771 } 2772 2773 /* 2774 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2775 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2776 * called from vPHB reset handler so we initialize the counter here. 2777 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2778 * must be equally distant from any other node. 2779 * The final value of spapr->gpu_numa_id is going to be written to 2780 * max-associativity-domains in spapr_build_fdt(). 2781 */ 2782 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2783 2784 /* Init numa_assoc_array */ 2785 spapr_numa_associativity_init(spapr, machine); 2786 2787 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2788 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2789 spapr->max_compat_pvr)) { 2790 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2791 /* KVM and TCG always allow GTSE with radix... */ 2792 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2793 } 2794 /* ... but not with hash (currently). */ 2795 2796 if (kvm_enabled()) { 2797 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2798 kvmppc_enable_logical_ci_hcalls(); 2799 kvmppc_enable_set_mode_hcall(); 2800 2801 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2802 kvmppc_enable_clear_ref_mod_hcalls(); 2803 2804 /* Enable H_PAGE_INIT */ 2805 kvmppc_enable_h_page_init(); 2806 } 2807 2808 /* map RAM */ 2809 memory_region_add_subregion(sysmem, 0, machine->ram); 2810 2811 /* always allocate the device memory information */ 2812 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2813 2814 /* initialize hotplug memory address space */ 2815 if (machine->ram_size < machine->maxram_size) { 2816 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2817 /* 2818 * Limit the number of hotpluggable memory slots to half the number 2819 * slots that KVM supports, leaving the other half for PCI and other 2820 * devices. However ensure that number of slots doesn't drop below 32. 2821 */ 2822 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2823 SPAPR_MAX_RAM_SLOTS; 2824 2825 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2826 max_memslots = SPAPR_MAX_RAM_SLOTS; 2827 } 2828 if (machine->ram_slots > max_memslots) { 2829 error_report("Specified number of memory slots %" 2830 PRIu64" exceeds max supported %d", 2831 machine->ram_slots, max_memslots); 2832 exit(1); 2833 } 2834 2835 machine->device_memory->base = ROUND_UP(machine->ram_size, 2836 SPAPR_DEVICE_MEM_ALIGN); 2837 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2838 "device-memory", device_mem_size); 2839 memory_region_add_subregion(sysmem, machine->device_memory->base, 2840 &machine->device_memory->mr); 2841 } 2842 2843 if (smc->dr_lmb_enabled) { 2844 spapr_create_lmb_dr_connectors(spapr); 2845 } 2846 2847 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2848 /* Create the error string for live migration blocker */ 2849 error_setg(&spapr->fwnmi_migration_blocker, 2850 "A machine check is being handled during migration. The handler" 2851 "may run and log hardware error on the destination"); 2852 } 2853 2854 if (mc->nvdimm_supported) { 2855 spapr_create_nvdimm_dr_connectors(spapr); 2856 } 2857 2858 /* Set up RTAS event infrastructure */ 2859 spapr_events_init(spapr); 2860 2861 /* Set up the RTC RTAS interfaces */ 2862 spapr_rtc_create(spapr); 2863 2864 /* Set up VIO bus */ 2865 spapr->vio_bus = spapr_vio_bus_init(); 2866 2867 for (i = 0; serial_hd(i); i++) { 2868 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2869 } 2870 2871 /* We always have at least the nvram device on VIO */ 2872 spapr_create_nvram(spapr); 2873 2874 /* 2875 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2876 * connectors (described in root DT node's "ibm,drc-types" property) 2877 * are pre-initialized here. additional child connectors (such as 2878 * connectors for a PHBs PCI slots) are added as needed during their 2879 * parent's realization. 2880 */ 2881 if (smc->dr_phb_enabled) { 2882 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2883 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2884 } 2885 } 2886 2887 /* Set up PCI */ 2888 spapr_pci_rtas_init(); 2889 2890 phb = spapr_create_default_phb(); 2891 2892 for (i = 0; i < nb_nics; i++) { 2893 NICInfo *nd = &nd_table[i]; 2894 2895 if (!nd->model) { 2896 nd->model = g_strdup("spapr-vlan"); 2897 } 2898 2899 if (g_str_equal(nd->model, "spapr-vlan") || 2900 g_str_equal(nd->model, "ibmveth")) { 2901 spapr_vlan_create(spapr->vio_bus, nd); 2902 } else { 2903 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2904 } 2905 } 2906 2907 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2908 spapr_vscsi_create(spapr->vio_bus); 2909 } 2910 2911 /* Graphics */ 2912 if (spapr_vga_init(phb->bus, &error_fatal)) { 2913 spapr->has_graphics = true; 2914 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2915 } 2916 2917 if (machine->usb) { 2918 if (smc->use_ohci_by_default) { 2919 pci_create_simple(phb->bus, -1, "pci-ohci"); 2920 } else { 2921 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2922 } 2923 2924 if (spapr->has_graphics) { 2925 USBBus *usb_bus = usb_bus_find(-1); 2926 2927 usb_create_simple(usb_bus, "usb-kbd"); 2928 usb_create_simple(usb_bus, "usb-mouse"); 2929 } 2930 } 2931 2932 if (kernel_filename) { 2933 spapr->kernel_size = load_elf(kernel_filename, NULL, 2934 translate_kernel_address, spapr, 2935 NULL, NULL, NULL, NULL, 1, 2936 PPC_ELF_MACHINE, 0, 0); 2937 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2938 spapr->kernel_size = load_elf(kernel_filename, NULL, 2939 translate_kernel_address, spapr, 2940 NULL, NULL, NULL, NULL, 0, 2941 PPC_ELF_MACHINE, 0, 0); 2942 spapr->kernel_le = spapr->kernel_size > 0; 2943 } 2944 if (spapr->kernel_size < 0) { 2945 error_report("error loading %s: %s", kernel_filename, 2946 load_elf_strerror(spapr->kernel_size)); 2947 exit(1); 2948 } 2949 2950 /* load initrd */ 2951 if (initrd_filename) { 2952 /* Try to locate the initrd in the gap between the kernel 2953 * and the firmware. Add a bit of space just in case 2954 */ 2955 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2956 + 0x1ffff) & ~0xffff; 2957 spapr->initrd_size = load_image_targphys(initrd_filename, 2958 spapr->initrd_base, 2959 load_limit 2960 - spapr->initrd_base); 2961 if (spapr->initrd_size < 0) { 2962 error_report("could not load initial ram disk '%s'", 2963 initrd_filename); 2964 exit(1); 2965 } 2966 } 2967 } 2968 2969 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2970 if (!filename) { 2971 error_report("Could not find LPAR firmware '%s'", bios_name); 2972 exit(1); 2973 } 2974 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2975 if (fw_size <= 0) { 2976 error_report("Could not load LPAR firmware '%s'", filename); 2977 exit(1); 2978 } 2979 g_free(filename); 2980 2981 /* FIXME: Should register things through the MachineState's qdev 2982 * interface, this is a legacy from the sPAPREnvironment structure 2983 * which predated MachineState but had a similar function */ 2984 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2985 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2986 &savevm_htab_handlers, spapr); 2987 2988 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2989 2990 qemu_register_boot_set(spapr_boot_set, spapr); 2991 2992 /* 2993 * Nothing needs to be done to resume a suspended guest because 2994 * suspending does not change the machine state, so no need for 2995 * a ->wakeup method. 2996 */ 2997 qemu_register_wakeup_support(); 2998 2999 if (kvm_enabled()) { 3000 /* to stop and start vmclock */ 3001 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3002 &spapr->tb); 3003 3004 kvmppc_spapr_enable_inkernel_multitce(); 3005 } 3006 3007 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3008 } 3009 3010 #define DEFAULT_KVM_TYPE "auto" 3011 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3012 { 3013 /* 3014 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3015 * accomodate the 'HV' and 'PV' formats that exists in the 3016 * wild. The 'auto' mode is being introduced already as 3017 * lower-case, thus we don't need to bother checking for 3018 * "AUTO". 3019 */ 3020 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3021 return 0; 3022 } 3023 3024 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3025 return 1; 3026 } 3027 3028 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3029 return 2; 3030 } 3031 3032 error_report("Unknown kvm-type specified '%s'", vm_type); 3033 exit(1); 3034 } 3035 3036 /* 3037 * Implementation of an interface to adjust firmware path 3038 * for the bootindex property handling. 3039 */ 3040 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3041 DeviceState *dev) 3042 { 3043 #define CAST(type, obj, name) \ 3044 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3045 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3046 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3047 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3048 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3049 3050 if (d) { 3051 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3052 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3053 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3054 3055 if (spapr) { 3056 /* 3057 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3058 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3059 * 0x8000 | (target << 8) | (bus << 5) | lun 3060 * (see the "Logical unit addressing format" table in SAM5) 3061 */ 3062 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3063 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3064 (uint64_t)id << 48); 3065 } else if (virtio) { 3066 /* 3067 * We use SRP luns of the form 01000000 | (target << 8) | lun 3068 * in the top 32 bits of the 64-bit LUN 3069 * Note: the quote above is from SLOF and it is wrong, 3070 * the actual binding is: 3071 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3072 */ 3073 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3074 if (d->lun >= 256) { 3075 /* Use the LUN "flat space addressing method" */ 3076 id |= 0x4000; 3077 } 3078 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3079 (uint64_t)id << 32); 3080 } else if (usb) { 3081 /* 3082 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3083 * in the top 32 bits of the 64-bit LUN 3084 */ 3085 unsigned usb_port = atoi(usb->port->path); 3086 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3087 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3088 (uint64_t)id << 32); 3089 } 3090 } 3091 3092 /* 3093 * SLOF probes the USB devices, and if it recognizes that the device is a 3094 * storage device, it changes its name to "storage" instead of "usb-host", 3095 * and additionally adds a child node for the SCSI LUN, so the correct 3096 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3097 */ 3098 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3099 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3100 if (usb_host_dev_is_scsi_storage(usbdev)) { 3101 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3102 } 3103 } 3104 3105 if (phb) { 3106 /* Replace "pci" with "pci@800000020000000" */ 3107 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3108 } 3109 3110 if (vsc) { 3111 /* Same logic as virtio above */ 3112 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3113 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3114 } 3115 3116 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3117 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3118 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3119 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3120 } 3121 3122 if (pcidev) { 3123 return spapr_pci_fw_dev_name(pcidev); 3124 } 3125 3126 return NULL; 3127 } 3128 3129 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3130 { 3131 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3132 3133 return g_strdup(spapr->kvm_type); 3134 } 3135 3136 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3137 { 3138 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3139 3140 g_free(spapr->kvm_type); 3141 spapr->kvm_type = g_strdup(value); 3142 } 3143 3144 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3145 { 3146 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3147 3148 return spapr->use_hotplug_event_source; 3149 } 3150 3151 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3152 Error **errp) 3153 { 3154 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3155 3156 spapr->use_hotplug_event_source = value; 3157 } 3158 3159 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3160 { 3161 return true; 3162 } 3163 3164 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3165 { 3166 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3167 3168 switch (spapr->resize_hpt) { 3169 case SPAPR_RESIZE_HPT_DEFAULT: 3170 return g_strdup("default"); 3171 case SPAPR_RESIZE_HPT_DISABLED: 3172 return g_strdup("disabled"); 3173 case SPAPR_RESIZE_HPT_ENABLED: 3174 return g_strdup("enabled"); 3175 case SPAPR_RESIZE_HPT_REQUIRED: 3176 return g_strdup("required"); 3177 } 3178 g_assert_not_reached(); 3179 } 3180 3181 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3182 { 3183 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3184 3185 if (strcmp(value, "default") == 0) { 3186 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3187 } else if (strcmp(value, "disabled") == 0) { 3188 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3189 } else if (strcmp(value, "enabled") == 0) { 3190 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3191 } else if (strcmp(value, "required") == 0) { 3192 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3193 } else { 3194 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3195 } 3196 } 3197 3198 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3199 { 3200 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3201 3202 if (spapr->irq == &spapr_irq_xics_legacy) { 3203 return g_strdup("legacy"); 3204 } else if (spapr->irq == &spapr_irq_xics) { 3205 return g_strdup("xics"); 3206 } else if (spapr->irq == &spapr_irq_xive) { 3207 return g_strdup("xive"); 3208 } else if (spapr->irq == &spapr_irq_dual) { 3209 return g_strdup("dual"); 3210 } 3211 g_assert_not_reached(); 3212 } 3213 3214 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3215 { 3216 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3217 3218 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3219 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3220 return; 3221 } 3222 3223 /* The legacy IRQ backend can not be set */ 3224 if (strcmp(value, "xics") == 0) { 3225 spapr->irq = &spapr_irq_xics; 3226 } else if (strcmp(value, "xive") == 0) { 3227 spapr->irq = &spapr_irq_xive; 3228 } else if (strcmp(value, "dual") == 0) { 3229 spapr->irq = &spapr_irq_dual; 3230 } else { 3231 error_setg(errp, "Bad value for \"ic-mode\" property"); 3232 } 3233 } 3234 3235 static char *spapr_get_host_model(Object *obj, Error **errp) 3236 { 3237 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3238 3239 return g_strdup(spapr->host_model); 3240 } 3241 3242 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3243 { 3244 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3245 3246 g_free(spapr->host_model); 3247 spapr->host_model = g_strdup(value); 3248 } 3249 3250 static char *spapr_get_host_serial(Object *obj, Error **errp) 3251 { 3252 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3253 3254 return g_strdup(spapr->host_serial); 3255 } 3256 3257 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3258 { 3259 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3260 3261 g_free(spapr->host_serial); 3262 spapr->host_serial = g_strdup(value); 3263 } 3264 3265 static void spapr_instance_init(Object *obj) 3266 { 3267 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3268 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3269 MachineState *ms = MACHINE(spapr); 3270 MachineClass *mc = MACHINE_GET_CLASS(ms); 3271 3272 /* 3273 * NVDIMM support went live in 5.1 without considering that, in 3274 * other archs, the user needs to enable NVDIMM support with the 3275 * 'nvdimm' machine option and the default behavior is NVDIMM 3276 * support disabled. It is too late to roll back to the standard 3277 * behavior without breaking 5.1 guests. 3278 */ 3279 if (mc->nvdimm_supported) { 3280 ms->nvdimms_state->is_enabled = true; 3281 } 3282 3283 spapr->htab_fd = -1; 3284 spapr->use_hotplug_event_source = true; 3285 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3286 object_property_add_str(obj, "kvm-type", 3287 spapr_get_kvm_type, spapr_set_kvm_type); 3288 object_property_set_description(obj, "kvm-type", 3289 "Specifies the KVM virtualization mode (auto," 3290 " hv, pr). Defaults to 'auto'. This mode will use" 3291 " any available KVM module loaded in the host," 3292 " where kvm_hv takes precedence if both kvm_hv and" 3293 " kvm_pr are loaded."); 3294 object_property_add_bool(obj, "modern-hotplug-events", 3295 spapr_get_modern_hotplug_events, 3296 spapr_set_modern_hotplug_events); 3297 object_property_set_description(obj, "modern-hotplug-events", 3298 "Use dedicated hotplug event mechanism in" 3299 " place of standard EPOW events when possible" 3300 " (required for memory hot-unplug support)"); 3301 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3302 "Maximum permitted CPU compatibility mode"); 3303 3304 object_property_add_str(obj, "resize-hpt", 3305 spapr_get_resize_hpt, spapr_set_resize_hpt); 3306 object_property_set_description(obj, "resize-hpt", 3307 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3308 object_property_add_uint32_ptr(obj, "vsmt", 3309 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3310 object_property_set_description(obj, "vsmt", 3311 "Virtual SMT: KVM behaves as if this were" 3312 " the host's SMT mode"); 3313 3314 object_property_add_bool(obj, "vfio-no-msix-emulation", 3315 spapr_get_msix_emulation, NULL); 3316 3317 object_property_add_uint64_ptr(obj, "kernel-addr", 3318 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3319 object_property_set_description(obj, "kernel-addr", 3320 stringify(KERNEL_LOAD_ADDR) 3321 " for -kernel is the default"); 3322 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3323 /* The machine class defines the default interrupt controller mode */ 3324 spapr->irq = smc->irq; 3325 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3326 spapr_set_ic_mode); 3327 object_property_set_description(obj, "ic-mode", 3328 "Specifies the interrupt controller mode (xics, xive, dual)"); 3329 3330 object_property_add_str(obj, "host-model", 3331 spapr_get_host_model, spapr_set_host_model); 3332 object_property_set_description(obj, "host-model", 3333 "Host model to advertise in guest device tree"); 3334 object_property_add_str(obj, "host-serial", 3335 spapr_get_host_serial, spapr_set_host_serial); 3336 object_property_set_description(obj, "host-serial", 3337 "Host serial number to advertise in guest device tree"); 3338 } 3339 3340 static void spapr_machine_finalizefn(Object *obj) 3341 { 3342 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3343 3344 g_free(spapr->kvm_type); 3345 } 3346 3347 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3348 { 3349 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3350 PowerPCCPU *cpu = POWERPC_CPU(cs); 3351 CPUPPCState *env = &cpu->env; 3352 3353 cpu_synchronize_state(cs); 3354 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3355 if (spapr->fwnmi_system_reset_addr != -1) { 3356 uint64_t rtas_addr, addr; 3357 3358 /* get rtas addr from fdt */ 3359 rtas_addr = spapr_get_rtas_addr(); 3360 if (!rtas_addr) { 3361 qemu_system_guest_panicked(NULL); 3362 return; 3363 } 3364 3365 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3366 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3367 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3368 env->gpr[3] = addr; 3369 } 3370 ppc_cpu_do_system_reset(cs); 3371 if (spapr->fwnmi_system_reset_addr != -1) { 3372 env->nip = spapr->fwnmi_system_reset_addr; 3373 } 3374 } 3375 3376 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3377 { 3378 CPUState *cs; 3379 3380 CPU_FOREACH(cs) { 3381 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3382 } 3383 } 3384 3385 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3386 void *fdt, int *fdt_start_offset, Error **errp) 3387 { 3388 uint64_t addr; 3389 uint32_t node; 3390 3391 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3392 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3393 &error_abort); 3394 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3395 SPAPR_MEMORY_BLOCK_SIZE); 3396 return 0; 3397 } 3398 3399 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3400 bool dedicated_hp_event_source) 3401 { 3402 SpaprDrc *drc; 3403 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3404 int i; 3405 uint64_t addr = addr_start; 3406 bool hotplugged = spapr_drc_hotplugged(dev); 3407 3408 for (i = 0; i < nr_lmbs; i++) { 3409 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3410 addr / SPAPR_MEMORY_BLOCK_SIZE); 3411 g_assert(drc); 3412 3413 /* 3414 * memory_device_get_free_addr() provided a range of free addresses 3415 * that doesn't overlap with any existing mapping at pre-plug. The 3416 * corresponding LMB DRCs are thus assumed to be all attachable. 3417 */ 3418 spapr_drc_attach(drc, dev); 3419 if (!hotplugged) { 3420 spapr_drc_reset(drc); 3421 } 3422 addr += SPAPR_MEMORY_BLOCK_SIZE; 3423 } 3424 /* send hotplug notification to the 3425 * guest only in case of hotplugged memory 3426 */ 3427 if (hotplugged) { 3428 if (dedicated_hp_event_source) { 3429 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3430 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3431 g_assert(drc); 3432 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3433 nr_lmbs, 3434 spapr_drc_index(drc)); 3435 } else { 3436 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3437 nr_lmbs); 3438 } 3439 } 3440 } 3441 3442 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3443 { 3444 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3445 PCDIMMDevice *dimm = PC_DIMM(dev); 3446 uint64_t size, addr; 3447 int64_t slot; 3448 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3449 3450 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3451 3452 pc_dimm_plug(dimm, MACHINE(ms)); 3453 3454 if (!is_nvdimm) { 3455 addr = object_property_get_uint(OBJECT(dimm), 3456 PC_DIMM_ADDR_PROP, &error_abort); 3457 spapr_add_lmbs(dev, addr, size, 3458 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3459 } else { 3460 slot = object_property_get_int(OBJECT(dimm), 3461 PC_DIMM_SLOT_PROP, &error_abort); 3462 /* We should have valid slot number at this point */ 3463 g_assert(slot >= 0); 3464 spapr_add_nvdimm(dev, slot); 3465 } 3466 } 3467 3468 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3469 Error **errp) 3470 { 3471 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3472 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3473 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3474 PCDIMMDevice *dimm = PC_DIMM(dev); 3475 Error *local_err = NULL; 3476 uint64_t size; 3477 Object *memdev; 3478 hwaddr pagesize; 3479 3480 if (!smc->dr_lmb_enabled) { 3481 error_setg(errp, "Memory hotplug not supported for this machine"); 3482 return; 3483 } 3484 3485 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3486 if (local_err) { 3487 error_propagate(errp, local_err); 3488 return; 3489 } 3490 3491 if (is_nvdimm) { 3492 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3493 return; 3494 } 3495 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3496 error_setg(errp, "Hotplugged memory size must be a multiple of " 3497 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3498 return; 3499 } 3500 3501 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3502 &error_abort); 3503 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3504 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3505 return; 3506 } 3507 3508 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3509 } 3510 3511 struct SpaprDimmState { 3512 PCDIMMDevice *dimm; 3513 uint32_t nr_lmbs; 3514 QTAILQ_ENTRY(SpaprDimmState) next; 3515 }; 3516 3517 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3518 PCDIMMDevice *dimm) 3519 { 3520 SpaprDimmState *dimm_state = NULL; 3521 3522 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3523 if (dimm_state->dimm == dimm) { 3524 break; 3525 } 3526 } 3527 return dimm_state; 3528 } 3529 3530 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3531 uint32_t nr_lmbs, 3532 PCDIMMDevice *dimm) 3533 { 3534 SpaprDimmState *ds = NULL; 3535 3536 /* 3537 * If this request is for a DIMM whose removal had failed earlier 3538 * (due to guest's refusal to remove the LMBs), we would have this 3539 * dimm already in the pending_dimm_unplugs list. In that 3540 * case don't add again. 3541 */ 3542 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3543 if (!ds) { 3544 ds = g_malloc0(sizeof(SpaprDimmState)); 3545 ds->nr_lmbs = nr_lmbs; 3546 ds->dimm = dimm; 3547 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3548 } 3549 return ds; 3550 } 3551 3552 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3553 SpaprDimmState *dimm_state) 3554 { 3555 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3556 g_free(dimm_state); 3557 } 3558 3559 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3560 PCDIMMDevice *dimm) 3561 { 3562 SpaprDrc *drc; 3563 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3564 &error_abort); 3565 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3566 uint32_t avail_lmbs = 0; 3567 uint64_t addr_start, addr; 3568 int i; 3569 3570 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3571 &error_abort); 3572 3573 addr = addr_start; 3574 for (i = 0; i < nr_lmbs; i++) { 3575 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3576 addr / SPAPR_MEMORY_BLOCK_SIZE); 3577 g_assert(drc); 3578 if (drc->dev) { 3579 avail_lmbs++; 3580 } 3581 addr += SPAPR_MEMORY_BLOCK_SIZE; 3582 } 3583 3584 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3585 } 3586 3587 /* Callback to be called during DRC release. */ 3588 void spapr_lmb_release(DeviceState *dev) 3589 { 3590 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3591 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3592 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3593 3594 /* This information will get lost if a migration occurs 3595 * during the unplug process. In this case recover it. */ 3596 if (ds == NULL) { 3597 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3598 g_assert(ds); 3599 /* The DRC being examined by the caller at least must be counted */ 3600 g_assert(ds->nr_lmbs); 3601 } 3602 3603 if (--ds->nr_lmbs) { 3604 return; 3605 } 3606 3607 /* 3608 * Now that all the LMBs have been removed by the guest, call the 3609 * unplug handler chain. This can never fail. 3610 */ 3611 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3612 object_unparent(OBJECT(dev)); 3613 } 3614 3615 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3616 { 3617 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3618 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3619 3620 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3621 qdev_unrealize(dev); 3622 spapr_pending_dimm_unplugs_remove(spapr, ds); 3623 } 3624 3625 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3626 DeviceState *dev, Error **errp) 3627 { 3628 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3629 PCDIMMDevice *dimm = PC_DIMM(dev); 3630 uint32_t nr_lmbs; 3631 uint64_t size, addr_start, addr; 3632 int i; 3633 SpaprDrc *drc; 3634 3635 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3636 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3637 return; 3638 } 3639 3640 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3641 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3642 3643 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3644 &error_abort); 3645 3646 /* 3647 * An existing pending dimm state for this DIMM means that there is an 3648 * unplug operation in progress, waiting for the spapr_lmb_release 3649 * callback to complete the job (BQL can't cover that far). In this case, 3650 * bail out to avoid detaching DRCs that were already released. 3651 */ 3652 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3653 error_setg(errp, "Memory unplug already in progress for device %s", 3654 dev->id); 3655 return; 3656 } 3657 3658 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3659 3660 addr = addr_start; 3661 for (i = 0; i < nr_lmbs; i++) { 3662 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3663 addr / SPAPR_MEMORY_BLOCK_SIZE); 3664 g_assert(drc); 3665 3666 spapr_drc_detach(drc); 3667 addr += SPAPR_MEMORY_BLOCK_SIZE; 3668 } 3669 3670 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3671 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3672 g_assert(drc); 3673 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3674 nr_lmbs, spapr_drc_index(drc)); 3675 } 3676 3677 /* Callback to be called during DRC release. */ 3678 void spapr_core_release(DeviceState *dev) 3679 { 3680 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3681 3682 /* Call the unplug handler chain. This can never fail. */ 3683 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3684 object_unparent(OBJECT(dev)); 3685 } 3686 3687 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3688 { 3689 MachineState *ms = MACHINE(hotplug_dev); 3690 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3691 CPUCore *cc = CPU_CORE(dev); 3692 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3693 3694 if (smc->pre_2_10_has_unused_icps) { 3695 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3696 int i; 3697 3698 for (i = 0; i < cc->nr_threads; i++) { 3699 CPUState *cs = CPU(sc->threads[i]); 3700 3701 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3702 } 3703 } 3704 3705 assert(core_slot); 3706 core_slot->cpu = NULL; 3707 qdev_unrealize(dev); 3708 } 3709 3710 static 3711 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3712 Error **errp) 3713 { 3714 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3715 int index; 3716 SpaprDrc *drc; 3717 CPUCore *cc = CPU_CORE(dev); 3718 3719 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3720 error_setg(errp, "Unable to find CPU core with core-id: %d", 3721 cc->core_id); 3722 return; 3723 } 3724 if (index == 0) { 3725 error_setg(errp, "Boot CPU core may not be unplugged"); 3726 return; 3727 } 3728 3729 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3730 spapr_vcpu_id(spapr, cc->core_id)); 3731 g_assert(drc); 3732 3733 if (!spapr_drc_unplug_requested(drc)) { 3734 spapr_drc_detach(drc); 3735 spapr_hotplug_req_remove_by_index(drc); 3736 } 3737 } 3738 3739 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3740 void *fdt, int *fdt_start_offset, Error **errp) 3741 { 3742 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3743 CPUState *cs = CPU(core->threads[0]); 3744 PowerPCCPU *cpu = POWERPC_CPU(cs); 3745 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3746 int id = spapr_get_vcpu_id(cpu); 3747 g_autofree char *nodename = NULL; 3748 int offset; 3749 3750 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3751 offset = fdt_add_subnode(fdt, 0, nodename); 3752 3753 spapr_dt_cpu(cs, fdt, offset, spapr); 3754 3755 /* 3756 * spapr_dt_cpu() does not fill the 'name' property in the 3757 * CPU node. The function is called during boot process, before 3758 * and after CAS, and overwriting the 'name' property written 3759 * by SLOF is not allowed. 3760 * 3761 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3762 * CPUs more compatible with the coldplugged ones, which have 3763 * the 'name' property. Linux Kernel also relies on this 3764 * property to identify CPU nodes. 3765 */ 3766 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3767 3768 *fdt_start_offset = offset; 3769 return 0; 3770 } 3771 3772 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3773 { 3774 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3775 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3776 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3777 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3778 CPUCore *cc = CPU_CORE(dev); 3779 CPUState *cs; 3780 SpaprDrc *drc; 3781 CPUArchId *core_slot; 3782 int index; 3783 bool hotplugged = spapr_drc_hotplugged(dev); 3784 int i; 3785 3786 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3787 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3788 3789 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3790 spapr_vcpu_id(spapr, cc->core_id)); 3791 3792 g_assert(drc || !mc->has_hotpluggable_cpus); 3793 3794 if (drc) { 3795 /* 3796 * spapr_core_pre_plug() already buys us this is a brand new 3797 * core being plugged into a free slot. Nothing should already 3798 * be attached to the corresponding DRC. 3799 */ 3800 spapr_drc_attach(drc, dev); 3801 3802 if (hotplugged) { 3803 /* 3804 * Send hotplug notification interrupt to the guest only 3805 * in case of hotplugged CPUs. 3806 */ 3807 spapr_hotplug_req_add_by_index(drc); 3808 } else { 3809 spapr_drc_reset(drc); 3810 } 3811 } 3812 3813 core_slot->cpu = OBJECT(dev); 3814 3815 /* 3816 * Set compatibility mode to match the boot CPU, which was either set 3817 * by the machine reset code or by CAS. This really shouldn't fail at 3818 * this point. 3819 */ 3820 if (hotplugged) { 3821 for (i = 0; i < cc->nr_threads; i++) { 3822 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3823 &error_abort); 3824 } 3825 } 3826 3827 if (smc->pre_2_10_has_unused_icps) { 3828 for (i = 0; i < cc->nr_threads; i++) { 3829 cs = CPU(core->threads[i]); 3830 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3831 } 3832 } 3833 } 3834 3835 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3836 Error **errp) 3837 { 3838 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3839 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3840 CPUCore *cc = CPU_CORE(dev); 3841 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3842 const char *type = object_get_typename(OBJECT(dev)); 3843 CPUArchId *core_slot; 3844 int index; 3845 unsigned int smp_threads = machine->smp.threads; 3846 3847 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3848 error_setg(errp, "CPU hotplug not supported for this machine"); 3849 return; 3850 } 3851 3852 if (strcmp(base_core_type, type)) { 3853 error_setg(errp, "CPU core type should be %s", base_core_type); 3854 return; 3855 } 3856 3857 if (cc->core_id % smp_threads) { 3858 error_setg(errp, "invalid core id %d", cc->core_id); 3859 return; 3860 } 3861 3862 /* 3863 * In general we should have homogeneous threads-per-core, but old 3864 * (pre hotplug support) machine types allow the last core to have 3865 * reduced threads as a compatibility hack for when we allowed 3866 * total vcpus not a multiple of threads-per-core. 3867 */ 3868 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3869 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3870 smp_threads); 3871 return; 3872 } 3873 3874 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3875 if (!core_slot) { 3876 error_setg(errp, "core id %d out of range", cc->core_id); 3877 return; 3878 } 3879 3880 if (core_slot->cpu) { 3881 error_setg(errp, "core %d already populated", cc->core_id); 3882 return; 3883 } 3884 3885 numa_cpu_pre_plug(core_slot, dev, errp); 3886 } 3887 3888 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3889 void *fdt, int *fdt_start_offset, Error **errp) 3890 { 3891 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3892 int intc_phandle; 3893 3894 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3895 if (intc_phandle <= 0) { 3896 return -1; 3897 } 3898 3899 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3900 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3901 return -1; 3902 } 3903 3904 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3905 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3906 3907 return 0; 3908 } 3909 3910 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3911 Error **errp) 3912 { 3913 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3914 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3915 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3916 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3917 SpaprDrc *drc; 3918 3919 if (dev->hotplugged && !smc->dr_phb_enabled) { 3920 error_setg(errp, "PHB hotplug not supported for this machine"); 3921 return false; 3922 } 3923 3924 if (sphb->index == (uint32_t)-1) { 3925 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3926 return false; 3927 } 3928 3929 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3930 if (drc && drc->dev) { 3931 error_setg(errp, "PHB %d already attached", sphb->index); 3932 return false; 3933 } 3934 3935 /* 3936 * This will check that sphb->index doesn't exceed the maximum number of 3937 * PHBs for the current machine type. 3938 */ 3939 return 3940 smc->phb_placement(spapr, sphb->index, 3941 &sphb->buid, &sphb->io_win_addr, 3942 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3943 windows_supported, sphb->dma_liobn, 3944 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3945 errp); 3946 } 3947 3948 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3949 { 3950 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3951 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3952 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3953 SpaprDrc *drc; 3954 bool hotplugged = spapr_drc_hotplugged(dev); 3955 3956 if (!smc->dr_phb_enabled) { 3957 return; 3958 } 3959 3960 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3961 /* hotplug hooks should check it's enabled before getting this far */ 3962 assert(drc); 3963 3964 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 3965 spapr_drc_attach(drc, dev); 3966 3967 if (hotplugged) { 3968 spapr_hotplug_req_add_by_index(drc); 3969 } else { 3970 spapr_drc_reset(drc); 3971 } 3972 } 3973 3974 void spapr_phb_release(DeviceState *dev) 3975 { 3976 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3977 3978 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3979 object_unparent(OBJECT(dev)); 3980 } 3981 3982 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3983 { 3984 qdev_unrealize(dev); 3985 } 3986 3987 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3988 DeviceState *dev, Error **errp) 3989 { 3990 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3991 SpaprDrc *drc; 3992 3993 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3994 assert(drc); 3995 3996 if (!spapr_drc_unplug_requested(drc)) { 3997 spapr_drc_detach(drc); 3998 spapr_hotplug_req_remove_by_index(drc); 3999 } 4000 } 4001 4002 static 4003 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4004 Error **errp) 4005 { 4006 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4007 4008 if (spapr->tpm_proxy != NULL) { 4009 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4010 return false; 4011 } 4012 4013 return true; 4014 } 4015 4016 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4017 { 4018 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4019 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4020 4021 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4022 g_assert(spapr->tpm_proxy == NULL); 4023 4024 spapr->tpm_proxy = tpm_proxy; 4025 } 4026 4027 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4028 { 4029 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4030 4031 qdev_unrealize(dev); 4032 object_unparent(OBJECT(dev)); 4033 spapr->tpm_proxy = NULL; 4034 } 4035 4036 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4037 DeviceState *dev, Error **errp) 4038 { 4039 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4040 spapr_memory_plug(hotplug_dev, dev); 4041 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4042 spapr_core_plug(hotplug_dev, dev); 4043 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4044 spapr_phb_plug(hotplug_dev, dev); 4045 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4046 spapr_tpm_proxy_plug(hotplug_dev, dev); 4047 } 4048 } 4049 4050 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4051 DeviceState *dev, Error **errp) 4052 { 4053 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4054 spapr_memory_unplug(hotplug_dev, dev); 4055 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4056 spapr_core_unplug(hotplug_dev, dev); 4057 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4058 spapr_phb_unplug(hotplug_dev, dev); 4059 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4060 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4061 } 4062 } 4063 4064 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4065 { 4066 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4067 /* 4068 * CAS will process all pending unplug requests. 4069 * 4070 * HACK: a guest could theoretically have cleared all bits in OV5, 4071 * but none of the guests we care for do. 4072 */ 4073 spapr_ovec_empty(spapr->ov5_cas); 4074 } 4075 4076 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4077 DeviceState *dev, Error **errp) 4078 { 4079 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4080 MachineClass *mc = MACHINE_GET_CLASS(sms); 4081 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4082 4083 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4084 if (spapr_memory_hot_unplug_supported(sms)) { 4085 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4086 } else { 4087 error_setg(errp, "Memory hot unplug not supported for this guest"); 4088 } 4089 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4090 if (!mc->has_hotpluggable_cpus) { 4091 error_setg(errp, "CPU hot unplug not supported on this machine"); 4092 return; 4093 } 4094 spapr_core_unplug_request(hotplug_dev, dev, errp); 4095 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4096 if (!smc->dr_phb_enabled) { 4097 error_setg(errp, "PHB hot unplug not supported on this machine"); 4098 return; 4099 } 4100 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4102 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4103 } 4104 } 4105 4106 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4107 DeviceState *dev, Error **errp) 4108 { 4109 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4110 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4111 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4112 spapr_core_pre_plug(hotplug_dev, dev, errp); 4113 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4114 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4115 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4116 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4117 } 4118 } 4119 4120 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4121 DeviceState *dev) 4122 { 4123 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4124 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4125 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4126 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4127 return HOTPLUG_HANDLER(machine); 4128 } 4129 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4130 PCIDevice *pcidev = PCI_DEVICE(dev); 4131 PCIBus *root = pci_device_root_bus(pcidev); 4132 SpaprPhbState *phb = 4133 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4134 TYPE_SPAPR_PCI_HOST_BRIDGE); 4135 4136 if (phb) { 4137 return HOTPLUG_HANDLER(phb); 4138 } 4139 } 4140 return NULL; 4141 } 4142 4143 static CpuInstanceProperties 4144 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4145 { 4146 CPUArchId *core_slot; 4147 MachineClass *mc = MACHINE_GET_CLASS(machine); 4148 4149 /* make sure possible_cpu are intialized */ 4150 mc->possible_cpu_arch_ids(machine); 4151 /* get CPU core slot containing thread that matches cpu_index */ 4152 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4153 assert(core_slot); 4154 return core_slot->props; 4155 } 4156 4157 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4158 { 4159 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4160 } 4161 4162 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4163 { 4164 int i; 4165 unsigned int smp_threads = machine->smp.threads; 4166 unsigned int smp_cpus = machine->smp.cpus; 4167 const char *core_type; 4168 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4169 MachineClass *mc = MACHINE_GET_CLASS(machine); 4170 4171 if (!mc->has_hotpluggable_cpus) { 4172 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4173 } 4174 if (machine->possible_cpus) { 4175 assert(machine->possible_cpus->len == spapr_max_cores); 4176 return machine->possible_cpus; 4177 } 4178 4179 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4180 if (!core_type) { 4181 error_report("Unable to find sPAPR CPU Core definition"); 4182 exit(1); 4183 } 4184 4185 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4186 sizeof(CPUArchId) * spapr_max_cores); 4187 machine->possible_cpus->len = spapr_max_cores; 4188 for (i = 0; i < machine->possible_cpus->len; i++) { 4189 int core_id = i * smp_threads; 4190 4191 machine->possible_cpus->cpus[i].type = core_type; 4192 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4193 machine->possible_cpus->cpus[i].arch_id = core_id; 4194 machine->possible_cpus->cpus[i].props.has_core_id = true; 4195 machine->possible_cpus->cpus[i].props.core_id = core_id; 4196 } 4197 return machine->possible_cpus; 4198 } 4199 4200 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4201 uint64_t *buid, hwaddr *pio, 4202 hwaddr *mmio32, hwaddr *mmio64, 4203 unsigned n_dma, uint32_t *liobns, 4204 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4205 { 4206 /* 4207 * New-style PHB window placement. 4208 * 4209 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4210 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4211 * windows. 4212 * 4213 * Some guest kernels can't work with MMIO windows above 1<<46 4214 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4215 * 4216 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4217 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4218 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4219 * 1TiB 64-bit MMIO windows for each PHB. 4220 */ 4221 const uint64_t base_buid = 0x800000020000000ULL; 4222 int i; 4223 4224 /* Sanity check natural alignments */ 4225 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4226 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4227 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4228 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4229 /* Sanity check bounds */ 4230 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4231 SPAPR_PCI_MEM32_WIN_SIZE); 4232 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4233 SPAPR_PCI_MEM64_WIN_SIZE); 4234 4235 if (index >= SPAPR_MAX_PHBS) { 4236 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4237 SPAPR_MAX_PHBS - 1); 4238 return false; 4239 } 4240 4241 *buid = base_buid + index; 4242 for (i = 0; i < n_dma; ++i) { 4243 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4244 } 4245 4246 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4247 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4248 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4249 4250 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4251 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4252 return true; 4253 } 4254 4255 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4256 { 4257 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4258 4259 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4260 } 4261 4262 static void spapr_ics_resend(XICSFabric *dev) 4263 { 4264 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4265 4266 ics_resend(spapr->ics); 4267 } 4268 4269 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4270 { 4271 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4272 4273 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4274 } 4275 4276 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4277 Monitor *mon) 4278 { 4279 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4280 4281 spapr_irq_print_info(spapr, mon); 4282 monitor_printf(mon, "irqchip: %s\n", 4283 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4284 } 4285 4286 /* 4287 * This is a XIVE only operation 4288 */ 4289 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4290 uint8_t nvt_blk, uint32_t nvt_idx, 4291 bool cam_ignore, uint8_t priority, 4292 uint32_t logic_serv, XiveTCTXMatch *match) 4293 { 4294 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4295 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4296 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4297 int count; 4298 4299 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4300 priority, logic_serv, match); 4301 if (count < 0) { 4302 return count; 4303 } 4304 4305 /* 4306 * When we implement the save and restore of the thread interrupt 4307 * contexts in the enter/exit CPU handlers of the machine and the 4308 * escalations in QEMU, we should be able to handle non dispatched 4309 * vCPUs. 4310 * 4311 * Until this is done, the sPAPR machine should find at least one 4312 * matching context always. 4313 */ 4314 if (count == 0) { 4315 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4316 nvt_blk, nvt_idx); 4317 } 4318 4319 return count; 4320 } 4321 4322 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4323 { 4324 return cpu->vcpu_id; 4325 } 4326 4327 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4328 { 4329 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4330 MachineState *ms = MACHINE(spapr); 4331 int vcpu_id; 4332 4333 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4334 4335 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4336 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4337 error_append_hint(errp, "Adjust the number of cpus to %d " 4338 "or try to raise the number of threads per core\n", 4339 vcpu_id * ms->smp.threads / spapr->vsmt); 4340 return false; 4341 } 4342 4343 cpu->vcpu_id = vcpu_id; 4344 return true; 4345 } 4346 4347 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4348 { 4349 CPUState *cs; 4350 4351 CPU_FOREACH(cs) { 4352 PowerPCCPU *cpu = POWERPC_CPU(cs); 4353 4354 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4355 return cpu; 4356 } 4357 } 4358 4359 return NULL; 4360 } 4361 4362 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4363 { 4364 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4365 4366 /* These are only called by TCG, KVM maintains dispatch state */ 4367 4368 spapr_cpu->prod = false; 4369 if (spapr_cpu->vpa_addr) { 4370 CPUState *cs = CPU(cpu); 4371 uint32_t dispatch; 4372 4373 dispatch = ldl_be_phys(cs->as, 4374 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4375 dispatch++; 4376 if ((dispatch & 1) != 0) { 4377 qemu_log_mask(LOG_GUEST_ERROR, 4378 "VPA: incorrect dispatch counter value for " 4379 "dispatched partition %u, correcting.\n", dispatch); 4380 dispatch++; 4381 } 4382 stl_be_phys(cs->as, 4383 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4384 } 4385 } 4386 4387 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4388 { 4389 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4390 4391 if (spapr_cpu->vpa_addr) { 4392 CPUState *cs = CPU(cpu); 4393 uint32_t dispatch; 4394 4395 dispatch = ldl_be_phys(cs->as, 4396 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4397 dispatch++; 4398 if ((dispatch & 1) != 1) { 4399 qemu_log_mask(LOG_GUEST_ERROR, 4400 "VPA: incorrect dispatch counter value for " 4401 "preempted partition %u, correcting.\n", dispatch); 4402 dispatch++; 4403 } 4404 stl_be_phys(cs->as, 4405 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4406 } 4407 } 4408 4409 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4410 { 4411 MachineClass *mc = MACHINE_CLASS(oc); 4412 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4413 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4414 NMIClass *nc = NMI_CLASS(oc); 4415 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4416 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4417 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4418 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4419 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4420 4421 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4422 mc->ignore_boot_device_suffixes = true; 4423 4424 /* 4425 * We set up the default / latest behaviour here. The class_init 4426 * functions for the specific versioned machine types can override 4427 * these details for backwards compatibility 4428 */ 4429 mc->init = spapr_machine_init; 4430 mc->reset = spapr_machine_reset; 4431 mc->block_default_type = IF_SCSI; 4432 mc->max_cpus = 1024; 4433 mc->no_parallel = 1; 4434 mc->default_boot_order = ""; 4435 mc->default_ram_size = 512 * MiB; 4436 mc->default_ram_id = "ppc_spapr.ram"; 4437 mc->default_display = "std"; 4438 mc->kvm_type = spapr_kvm_type; 4439 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4440 mc->pci_allow_0_address = true; 4441 assert(!mc->get_hotplug_handler); 4442 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4443 hc->pre_plug = spapr_machine_device_pre_plug; 4444 hc->plug = spapr_machine_device_plug; 4445 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4446 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4447 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4448 hc->unplug_request = spapr_machine_device_unplug_request; 4449 hc->unplug = spapr_machine_device_unplug; 4450 4451 smc->dr_lmb_enabled = true; 4452 smc->update_dt_enabled = true; 4453 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4454 mc->has_hotpluggable_cpus = true; 4455 mc->nvdimm_supported = true; 4456 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4457 fwc->get_dev_path = spapr_get_fw_dev_path; 4458 nc->nmi_monitor_handler = spapr_nmi; 4459 smc->phb_placement = spapr_phb_placement; 4460 vhc->hypercall = emulate_spapr_hypercall; 4461 vhc->hpt_mask = spapr_hpt_mask; 4462 vhc->map_hptes = spapr_map_hptes; 4463 vhc->unmap_hptes = spapr_unmap_hptes; 4464 vhc->hpte_set_c = spapr_hpte_set_c; 4465 vhc->hpte_set_r = spapr_hpte_set_r; 4466 vhc->get_pate = spapr_get_pate; 4467 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4468 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4469 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4470 xic->ics_get = spapr_ics_get; 4471 xic->ics_resend = spapr_ics_resend; 4472 xic->icp_get = spapr_icp_get; 4473 ispc->print_info = spapr_pic_print_info; 4474 /* Force NUMA node memory size to be a multiple of 4475 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4476 * in which LMBs are represented and hot-added 4477 */ 4478 mc->numa_mem_align_shift = 28; 4479 mc->auto_enable_numa = true; 4480 4481 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4482 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4483 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4484 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4485 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4486 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4487 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4488 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4489 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4490 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4491 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4492 spapr_caps_add_properties(smc); 4493 smc->irq = &spapr_irq_dual; 4494 smc->dr_phb_enabled = true; 4495 smc->linux_pci_probe = true; 4496 smc->smp_threads_vsmt = true; 4497 smc->nr_xirqs = SPAPR_NR_XIRQS; 4498 xfc->match_nvt = spapr_match_nvt; 4499 } 4500 4501 static const TypeInfo spapr_machine_info = { 4502 .name = TYPE_SPAPR_MACHINE, 4503 .parent = TYPE_MACHINE, 4504 .abstract = true, 4505 .instance_size = sizeof(SpaprMachineState), 4506 .instance_init = spapr_instance_init, 4507 .instance_finalize = spapr_machine_finalizefn, 4508 .class_size = sizeof(SpaprMachineClass), 4509 .class_init = spapr_machine_class_init, 4510 .interfaces = (InterfaceInfo[]) { 4511 { TYPE_FW_PATH_PROVIDER }, 4512 { TYPE_NMI }, 4513 { TYPE_HOTPLUG_HANDLER }, 4514 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4515 { TYPE_XICS_FABRIC }, 4516 { TYPE_INTERRUPT_STATS_PROVIDER }, 4517 { TYPE_XIVE_FABRIC }, 4518 { } 4519 }, 4520 }; 4521 4522 static void spapr_machine_latest_class_options(MachineClass *mc) 4523 { 4524 mc->alias = "pseries"; 4525 mc->is_default = true; 4526 } 4527 4528 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4529 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4530 void *data) \ 4531 { \ 4532 MachineClass *mc = MACHINE_CLASS(oc); \ 4533 spapr_machine_##suffix##_class_options(mc); \ 4534 if (latest) { \ 4535 spapr_machine_latest_class_options(mc); \ 4536 } \ 4537 } \ 4538 static const TypeInfo spapr_machine_##suffix##_info = { \ 4539 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4540 .parent = TYPE_SPAPR_MACHINE, \ 4541 .class_init = spapr_machine_##suffix##_class_init, \ 4542 }; \ 4543 static void spapr_machine_register_##suffix(void) \ 4544 { \ 4545 type_register(&spapr_machine_##suffix##_info); \ 4546 } \ 4547 type_init(spapr_machine_register_##suffix) 4548 4549 /* 4550 * pseries-6.0 4551 */ 4552 static void spapr_machine_6_0_class_options(MachineClass *mc) 4553 { 4554 /* Defaults for the latest behaviour inherited from the base class */ 4555 } 4556 4557 DEFINE_SPAPR_MACHINE(6_0, "6.0", true); 4558 4559 /* 4560 * pseries-5.2 4561 */ 4562 static void spapr_machine_5_2_class_options(MachineClass *mc) 4563 { 4564 spapr_machine_6_0_class_options(mc); 4565 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4566 } 4567 4568 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4569 4570 /* 4571 * pseries-5.1 4572 */ 4573 static void spapr_machine_5_1_class_options(MachineClass *mc) 4574 { 4575 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4576 4577 spapr_machine_5_2_class_options(mc); 4578 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4579 smc->pre_5_2_numa_associativity = true; 4580 } 4581 4582 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4583 4584 /* 4585 * pseries-5.0 4586 */ 4587 static void spapr_machine_5_0_class_options(MachineClass *mc) 4588 { 4589 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4590 static GlobalProperty compat[] = { 4591 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4592 }; 4593 4594 spapr_machine_5_1_class_options(mc); 4595 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4596 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4597 mc->numa_mem_supported = true; 4598 smc->pre_5_1_assoc_refpoints = true; 4599 } 4600 4601 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4602 4603 /* 4604 * pseries-4.2 4605 */ 4606 static void spapr_machine_4_2_class_options(MachineClass *mc) 4607 { 4608 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4609 4610 spapr_machine_5_0_class_options(mc); 4611 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4612 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4613 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4614 smc->rma_limit = 16 * GiB; 4615 mc->nvdimm_supported = false; 4616 } 4617 4618 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4619 4620 /* 4621 * pseries-4.1 4622 */ 4623 static void spapr_machine_4_1_class_options(MachineClass *mc) 4624 { 4625 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4626 static GlobalProperty compat[] = { 4627 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4628 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4629 }; 4630 4631 spapr_machine_4_2_class_options(mc); 4632 smc->linux_pci_probe = false; 4633 smc->smp_threads_vsmt = false; 4634 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4635 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4636 } 4637 4638 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4639 4640 /* 4641 * pseries-4.0 4642 */ 4643 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4644 uint64_t *buid, hwaddr *pio, 4645 hwaddr *mmio32, hwaddr *mmio64, 4646 unsigned n_dma, uint32_t *liobns, 4647 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4648 { 4649 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4650 liobns, nv2gpa, nv2atsd, errp)) { 4651 return false; 4652 } 4653 4654 *nv2gpa = 0; 4655 *nv2atsd = 0; 4656 return true; 4657 } 4658 static void spapr_machine_4_0_class_options(MachineClass *mc) 4659 { 4660 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4661 4662 spapr_machine_4_1_class_options(mc); 4663 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4664 smc->phb_placement = phb_placement_4_0; 4665 smc->irq = &spapr_irq_xics; 4666 smc->pre_4_1_migration = true; 4667 } 4668 4669 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4670 4671 /* 4672 * pseries-3.1 4673 */ 4674 static void spapr_machine_3_1_class_options(MachineClass *mc) 4675 { 4676 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4677 4678 spapr_machine_4_0_class_options(mc); 4679 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4680 4681 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4682 smc->update_dt_enabled = false; 4683 smc->dr_phb_enabled = false; 4684 smc->broken_host_serial_model = true; 4685 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4686 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4687 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4688 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4689 } 4690 4691 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4692 4693 /* 4694 * pseries-3.0 4695 */ 4696 4697 static void spapr_machine_3_0_class_options(MachineClass *mc) 4698 { 4699 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4700 4701 spapr_machine_3_1_class_options(mc); 4702 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4703 4704 smc->legacy_irq_allocation = true; 4705 smc->nr_xirqs = 0x400; 4706 smc->irq = &spapr_irq_xics_legacy; 4707 } 4708 4709 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4710 4711 /* 4712 * pseries-2.12 4713 */ 4714 static void spapr_machine_2_12_class_options(MachineClass *mc) 4715 { 4716 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4717 static GlobalProperty compat[] = { 4718 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4719 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4720 }; 4721 4722 spapr_machine_3_0_class_options(mc); 4723 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4724 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4725 4726 /* We depend on kvm_enabled() to choose a default value for the 4727 * hpt-max-page-size capability. Of course we can't do it here 4728 * because this is too early and the HW accelerator isn't initialzed 4729 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4730 */ 4731 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4732 } 4733 4734 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4735 4736 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4737 { 4738 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4739 4740 spapr_machine_2_12_class_options(mc); 4741 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4742 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4743 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4744 } 4745 4746 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4747 4748 /* 4749 * pseries-2.11 4750 */ 4751 4752 static void spapr_machine_2_11_class_options(MachineClass *mc) 4753 { 4754 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4755 4756 spapr_machine_2_12_class_options(mc); 4757 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4758 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4759 } 4760 4761 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4762 4763 /* 4764 * pseries-2.10 4765 */ 4766 4767 static void spapr_machine_2_10_class_options(MachineClass *mc) 4768 { 4769 spapr_machine_2_11_class_options(mc); 4770 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4771 } 4772 4773 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4774 4775 /* 4776 * pseries-2.9 4777 */ 4778 4779 static void spapr_machine_2_9_class_options(MachineClass *mc) 4780 { 4781 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4782 static GlobalProperty compat[] = { 4783 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4784 }; 4785 4786 spapr_machine_2_10_class_options(mc); 4787 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4788 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4789 smc->pre_2_10_has_unused_icps = true; 4790 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4791 } 4792 4793 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4794 4795 /* 4796 * pseries-2.8 4797 */ 4798 4799 static void spapr_machine_2_8_class_options(MachineClass *mc) 4800 { 4801 static GlobalProperty compat[] = { 4802 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4803 }; 4804 4805 spapr_machine_2_9_class_options(mc); 4806 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4807 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4808 mc->numa_mem_align_shift = 23; 4809 } 4810 4811 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4812 4813 /* 4814 * pseries-2.7 4815 */ 4816 4817 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4818 uint64_t *buid, hwaddr *pio, 4819 hwaddr *mmio32, hwaddr *mmio64, 4820 unsigned n_dma, uint32_t *liobns, 4821 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4822 { 4823 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4824 const uint64_t base_buid = 0x800000020000000ULL; 4825 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4826 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4827 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4828 const uint32_t max_index = 255; 4829 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4830 4831 uint64_t ram_top = MACHINE(spapr)->ram_size; 4832 hwaddr phb0_base, phb_base; 4833 int i; 4834 4835 /* Do we have device memory? */ 4836 if (MACHINE(spapr)->maxram_size > ram_top) { 4837 /* Can't just use maxram_size, because there may be an 4838 * alignment gap between normal and device memory regions 4839 */ 4840 ram_top = MACHINE(spapr)->device_memory->base + 4841 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4842 } 4843 4844 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4845 4846 if (index > max_index) { 4847 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4848 max_index); 4849 return false; 4850 } 4851 4852 *buid = base_buid + index; 4853 for (i = 0; i < n_dma; ++i) { 4854 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4855 } 4856 4857 phb_base = phb0_base + index * phb_spacing; 4858 *pio = phb_base + pio_offset; 4859 *mmio32 = phb_base + mmio_offset; 4860 /* 4861 * We don't set the 64-bit MMIO window, relying on the PHB's 4862 * fallback behaviour of automatically splitting a large "32-bit" 4863 * window into contiguous 32-bit and 64-bit windows 4864 */ 4865 4866 *nv2gpa = 0; 4867 *nv2atsd = 0; 4868 return true; 4869 } 4870 4871 static void spapr_machine_2_7_class_options(MachineClass *mc) 4872 { 4873 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4874 static GlobalProperty compat[] = { 4875 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4876 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4877 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4878 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4879 }; 4880 4881 spapr_machine_2_8_class_options(mc); 4882 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4883 mc->default_machine_opts = "modern-hotplug-events=off"; 4884 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4885 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4886 smc->phb_placement = phb_placement_2_7; 4887 } 4888 4889 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4890 4891 /* 4892 * pseries-2.6 4893 */ 4894 4895 static void spapr_machine_2_6_class_options(MachineClass *mc) 4896 { 4897 static GlobalProperty compat[] = { 4898 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4899 }; 4900 4901 spapr_machine_2_7_class_options(mc); 4902 mc->has_hotpluggable_cpus = false; 4903 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4904 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4905 } 4906 4907 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4908 4909 /* 4910 * pseries-2.5 4911 */ 4912 4913 static void spapr_machine_2_5_class_options(MachineClass *mc) 4914 { 4915 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4916 static GlobalProperty compat[] = { 4917 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4918 }; 4919 4920 spapr_machine_2_6_class_options(mc); 4921 smc->use_ohci_by_default = true; 4922 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4923 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4924 } 4925 4926 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4927 4928 /* 4929 * pseries-2.4 4930 */ 4931 4932 static void spapr_machine_2_4_class_options(MachineClass *mc) 4933 { 4934 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4935 4936 spapr_machine_2_5_class_options(mc); 4937 smc->dr_lmb_enabled = false; 4938 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4939 } 4940 4941 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4942 4943 /* 4944 * pseries-2.3 4945 */ 4946 4947 static void spapr_machine_2_3_class_options(MachineClass *mc) 4948 { 4949 static GlobalProperty compat[] = { 4950 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4951 }; 4952 spapr_machine_2_4_class_options(mc); 4953 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4954 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4955 } 4956 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4957 4958 /* 4959 * pseries-2.2 4960 */ 4961 4962 static void spapr_machine_2_2_class_options(MachineClass *mc) 4963 { 4964 static GlobalProperty compat[] = { 4965 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4966 }; 4967 4968 spapr_machine_2_3_class_options(mc); 4969 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4970 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4971 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4972 } 4973 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4974 4975 /* 4976 * pseries-2.1 4977 */ 4978 4979 static void spapr_machine_2_1_class_options(MachineClass *mc) 4980 { 4981 spapr_machine_2_2_class_options(mc); 4982 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4983 } 4984 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4985 4986 static void spapr_machine_register_types(void) 4987 { 4988 type_register_static(&spapr_machine_info); 4989 } 4990 4991 type_init(spapr_machine_register_types) 4992