1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "mmu-hash64.h" 50 #include "mmu-book3s-v3.h" 51 #include "cpu-models.h" 52 #include "hw/core/cpu.h" 53 54 #include "hw/boards.h" 55 #include "hw/ppc/ppc.h" 56 #include "hw/loader.h" 57 58 #include "hw/ppc/fdt.h" 59 #include "hw/ppc/spapr.h" 60 #include "hw/ppc/spapr_vio.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/pci-host/spapr.h" 63 #include "hw/pci/msi.h" 64 65 #include "hw/pci/pci.h" 66 #include "hw/scsi/scsi.h" 67 #include "hw/virtio/virtio-scsi.h" 68 #include "hw/virtio/vhost-scsi-common.h" 69 70 #include "exec/address-spaces.h" 71 #include "exec/ram_addr.h" 72 #include "hw/usb.h" 73 #include "qemu/config-file.h" 74 #include "qemu/error-report.h" 75 #include "trace.h" 76 #include "hw/nmi.h" 77 #include "hw/intc/intc.h" 78 79 #include "qemu/cutils.h" 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 84 #include "monitor/monitor.h" 85 86 #include <libfdt.h> 87 88 /* SLOF memory layout: 89 * 90 * SLOF raw image loaded at 0, copies its romfs right below the flat 91 * device-tree, then position SLOF itself 31M below that 92 * 93 * So we set FW_OVERHEAD to 40MB which should account for all of that 94 * and more 95 * 96 * We load our kernel at 4M, leaving space for SLOF initial image 97 */ 98 #define FDT_MAX_SIZE 0x100000 99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 100 #define FW_MAX_SIZE 0x400000 101 #define FW_FILE_NAME "slof.bin" 102 #define FW_OVERHEAD 0x2800000 103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 104 105 #define MIN_RMA_SLOF 128UL 106 107 #define PHANDLE_INTC 0x00001111 108 109 /* These two functions implement the VCPU id numbering: one to compute them 110 * all and one to identify thread 0 of a VCORE. Any change to the first one 111 * is likely to have an impact on the second one, so let's keep them close. 112 */ 113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 114 { 115 MachineState *ms = MACHINE(spapr); 116 unsigned int smp_threads = ms->smp.threads; 117 118 assert(spapr->vsmt); 119 return 120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 121 } 122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 123 PowerPCCPU *cpu) 124 { 125 assert(spapr->vsmt); 126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 int spapr_max_server_number(SpaprMachineState *spapr) 164 { 165 MachineState *ms = MACHINE(spapr); 166 167 assert(spapr->vsmt); 168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 169 } 170 171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 172 int smt_threads) 173 { 174 int i, ret = 0; 175 uint32_t servers_prop[smt_threads]; 176 uint32_t gservers_prop[smt_threads * 2]; 177 int index = spapr_get_vcpu_id(cpu); 178 179 if (cpu->compat_pvr) { 180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 181 if (ret < 0) { 182 return ret; 183 } 184 } 185 186 /* Build interrupt servers and gservers properties */ 187 for (i = 0; i < smt_threads; i++) { 188 servers_prop[i] = cpu_to_be32(index + i); 189 /* Hack, direct the group queues back to cpu 0 */ 190 gservers_prop[i*2] = cpu_to_be32(index + i); 191 gservers_prop[i*2 + 1] = 0; 192 } 193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 194 servers_prop, sizeof(servers_prop)); 195 if (ret < 0) { 196 return ret; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 199 gservers_prop, sizeof(gservers_prop)); 200 201 return ret; 202 } 203 204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 205 { 206 int index = spapr_get_vcpu_id(cpu); 207 uint32_t associativity[] = {cpu_to_be32(0x5), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(cpu->node_id), 212 cpu_to_be32(index)}; 213 214 /* Advertise NUMA via ibm,associativity */ 215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 216 sizeof(associativity)); 217 } 218 219 /* Populate the "ibm,pa-features" property */ 220 static void spapr_populate_pa_features(SpaprMachineState *spapr, 221 PowerPCCPU *cpu, 222 void *fdt, int offset) 223 { 224 uint8_t pa_features_206[] = { 6, 0, 225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 226 uint8_t pa_features_207[] = { 24, 0, 227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 231 uint8_t pa_features_300[] = { 66, 0, 232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 235 /* 6: DS207 */ 236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 237 /* 16: Vector */ 238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 247 /* 42: PM, 44: PC RA, 46: SC vec'd */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 249 /* 48: SIMD, 50: QP BFP, 52: String */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 251 /* 54: DecFP, 56: DecI, 58: SHA */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 253 /* 60: NM atomic, 62: RNG */ 254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (!pa_features) { 272 return; 273 } 274 275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 276 /* 277 * Note: we keep CI large pages off by default because a 64K capable 278 * guest provisioned with large pages might otherwise try to map a qemu 279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 280 * even if that qemu runs on a 4k host. 281 * We dd this bit back here if we are confident this is not an issue 282 */ 283 pa_features[3] |= 0x20; 284 } 285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 286 pa_features[24] |= 0x80; /* Transactional memory support */ 287 } 288 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 289 /* Workaround for broken kernels that attempt (guest) radix 290 * mode when they can't handle it, if they see the radix bit set 291 * in pa-features. So hide it from them. */ 292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 293 } 294 295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 296 } 297 298 static hwaddr spapr_node0_size(MachineState *machine) 299 { 300 if (machine->numa_state->num_nodes) { 301 int i; 302 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 303 if (machine->numa_state->nodes[i].node_mem) { 304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 305 machine->ram_size); 306 } 307 } 308 } 309 return machine->ram_size; 310 } 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 318 hwaddr size) 319 { 320 uint32_t associativity[] = { 321 cpu_to_be32(0x4), /* length */ 322 cpu_to_be32(0x0), cpu_to_be32(0x0), 323 cpu_to_be32(0x0), cpu_to_be32(nodeid) 324 }; 325 char mem_name[32]; 326 uint64_t mem_reg_property[2]; 327 int off; 328 329 mem_reg_property[0] = cpu_to_be64(start); 330 mem_reg_property[1] = cpu_to_be64(size); 331 332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 333 off = fdt_add_subnode(fdt, 0, mem_name); 334 _FDT(off); 335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 337 sizeof(mem_reg_property)))); 338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 339 sizeof(associativity)))); 340 return off; 341 } 342 343 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 344 { 345 MachineState *machine = MACHINE(spapr); 346 hwaddr mem_start, node_size; 347 int i, nb_nodes = machine->numa_state->num_nodes; 348 NodeInfo *nodes = machine->numa_state->nodes; 349 350 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 351 if (!nodes[i].node_mem) { 352 continue; 353 } 354 if (mem_start >= machine->ram_size) { 355 node_size = 0; 356 } else { 357 node_size = nodes[i].node_mem; 358 if (node_size > machine->ram_size - mem_start) { 359 node_size = machine->ram_size - mem_start; 360 } 361 } 362 if (!mem_start) { 363 /* spapr_machine_init() checks for rma_size <= node0_size 364 * already */ 365 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 366 mem_start += spapr->rma_size; 367 node_size -= spapr->rma_size; 368 } 369 for ( ; node_size; ) { 370 hwaddr sizetmp = pow2floor(node_size); 371 372 /* mem_start != 0 here */ 373 if (ctzl(mem_start) < ctzl(sizetmp)) { 374 sizetmp = 1ULL << ctzl(mem_start); 375 } 376 377 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 378 node_size -= sizetmp; 379 mem_start += sizetmp; 380 } 381 } 382 383 return 0; 384 } 385 386 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 387 SpaprMachineState *spapr) 388 { 389 MachineState *ms = MACHINE(spapr); 390 PowerPCCPU *cpu = POWERPC_CPU(cs); 391 CPUPPCState *env = &cpu->env; 392 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 393 int index = spapr_get_vcpu_id(cpu); 394 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 395 0xffffffff, 0xffffffff}; 396 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 397 : SPAPR_TIMEBASE_FREQ; 398 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 399 uint32_t page_sizes_prop[64]; 400 size_t page_sizes_prop_size; 401 unsigned int smp_threads = ms->smp.threads; 402 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 403 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 404 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 405 SpaprDrc *drc; 406 int drc_index; 407 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 408 int i; 409 410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 411 if (drc) { 412 drc_index = spapr_drc_index(drc); 413 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 414 } 415 416 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 417 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 418 419 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 420 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 421 env->dcache_line_size))); 422 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 423 env->dcache_line_size))); 424 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 425 env->icache_line_size))); 426 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 427 env->icache_line_size))); 428 429 if (pcc->l1_dcache_size) { 430 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 431 pcc->l1_dcache_size))); 432 } else { 433 warn_report("Unknown L1 dcache size for cpu"); 434 } 435 if (pcc->l1_icache_size) { 436 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 437 pcc->l1_icache_size))); 438 } else { 439 warn_report("Unknown L1 icache size for cpu"); 440 } 441 442 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 443 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 445 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 447 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 448 449 if (env->spr_cb[SPR_PURR].oea_read) { 450 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 451 } 452 if (env->spr_cb[SPR_SPURR].oea_read) { 453 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 454 } 455 456 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 457 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 458 segs, sizeof(segs)))); 459 } 460 461 /* Advertise VSX (vector extensions) if available 462 * 1 == VMX / Altivec available 463 * 2 == VSX available 464 * 465 * Only CPUs for which we create core types in spapr_cpu_core.c 466 * are possible, and all of those have VMX */ 467 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 468 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 469 } else { 470 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 471 } 472 473 /* Advertise DFP (Decimal Floating Point) if available 474 * 0 / no property == no DFP 475 * 1 == DFP available */ 476 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 477 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 478 } 479 480 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 481 sizeof(page_sizes_prop)); 482 if (page_sizes_prop_size) { 483 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 484 page_sizes_prop, page_sizes_prop_size))); 485 } 486 487 spapr_populate_pa_features(spapr, cpu, fdt, offset); 488 489 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 490 cs->cpu_index / vcpus_per_socket))); 491 492 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 493 pft_size_prop, sizeof(pft_size_prop)))); 494 495 if (ms->numa_state->num_nodes > 1) { 496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 497 } 498 499 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 500 501 if (pcc->radix_page_info) { 502 for (i = 0; i < pcc->radix_page_info->count; i++) { 503 radix_AP_encodings[i] = 504 cpu_to_be32(pcc->radix_page_info->entries[i]); 505 } 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 507 radix_AP_encodings, 508 pcc->radix_page_info->count * 509 sizeof(radix_AP_encodings[0])))); 510 } 511 512 /* 513 * We set this property to let the guest know that it can use the large 514 * decrementer and its width in bits. 515 */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 517 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 518 pcc->lrg_decr_bits))); 519 } 520 521 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 522 { 523 CPUState **rev; 524 CPUState *cs; 525 int n_cpus; 526 int cpus_offset; 527 char *nodename; 528 int i; 529 530 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 531 _FDT(cpus_offset); 532 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 534 535 /* 536 * We walk the CPUs in reverse order to ensure that CPU DT nodes 537 * created by fdt_add_subnode() end up in the right order in FDT 538 * for the guest kernel the enumerate the CPUs correctly. 539 * 540 * The CPU list cannot be traversed in reverse order, so we need 541 * to do extra work. 542 */ 543 n_cpus = 0; 544 rev = NULL; 545 CPU_FOREACH(cs) { 546 rev = g_renew(CPUState *, rev, n_cpus + 1); 547 rev[n_cpus++] = cs; 548 } 549 550 for (i = n_cpus - 1; i >= 0; i--) { 551 CPUState *cs = rev[i]; 552 PowerPCCPU *cpu = POWERPC_CPU(cs); 553 int index = spapr_get_vcpu_id(cpu); 554 DeviceClass *dc = DEVICE_GET_CLASS(cs); 555 int offset; 556 557 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 558 continue; 559 } 560 561 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 562 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 563 g_free(nodename); 564 _FDT(offset); 565 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 566 } 567 568 g_free(rev); 569 } 570 571 static int spapr_rng_populate_dt(void *fdt) 572 { 573 int node; 574 int ret; 575 576 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 577 if (node <= 0) { 578 return -1; 579 } 580 ret = fdt_setprop_string(fdt, node, "device_type", 581 "ibm,platform-facilities"); 582 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 583 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 584 585 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 586 if (node <= 0) { 587 return -1; 588 } 589 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 590 591 return ret ? -1 : 0; 592 } 593 594 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 595 { 596 MemoryDeviceInfoList *info; 597 598 for (info = list; info; info = info->next) { 599 MemoryDeviceInfo *value = info->value; 600 601 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 602 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 603 604 if (addr >= pcdimm_info->addr && 605 addr < (pcdimm_info->addr + pcdimm_info->size)) { 606 return pcdimm_info->node; 607 } 608 } 609 } 610 611 return -1; 612 } 613 614 struct sPAPRDrconfCellV2 { 615 uint32_t seq_lmbs; 616 uint64_t base_addr; 617 uint32_t drc_index; 618 uint32_t aa_index; 619 uint32_t flags; 620 } QEMU_PACKED; 621 622 typedef struct DrconfCellQueue { 623 struct sPAPRDrconfCellV2 cell; 624 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 625 } DrconfCellQueue; 626 627 static DrconfCellQueue * 628 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 629 uint32_t drc_index, uint32_t aa_index, 630 uint32_t flags) 631 { 632 DrconfCellQueue *elem; 633 634 elem = g_malloc0(sizeof(*elem)); 635 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 636 elem->cell.base_addr = cpu_to_be64(base_addr); 637 elem->cell.drc_index = cpu_to_be32(drc_index); 638 elem->cell.aa_index = cpu_to_be32(aa_index); 639 elem->cell.flags = cpu_to_be32(flags); 640 641 return elem; 642 } 643 644 /* ibm,dynamic-memory-v2 */ 645 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 646 int offset, MemoryDeviceInfoList *dimms) 647 { 648 MachineState *machine = MACHINE(spapr); 649 uint8_t *int_buf, *cur_index; 650 int ret; 651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 652 uint64_t addr, cur_addr, size; 653 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 654 uint64_t mem_end = machine->device_memory->base + 655 memory_region_size(&machine->device_memory->mr); 656 uint32_t node, buf_len, nr_entries = 0; 657 SpaprDrc *drc; 658 DrconfCellQueue *elem, *next; 659 MemoryDeviceInfoList *info; 660 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 661 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 662 663 /* Entry to cover RAM and the gap area */ 664 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 665 SPAPR_LMB_FLAGS_RESERVED | 666 SPAPR_LMB_FLAGS_DRC_INVALID); 667 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 668 nr_entries++; 669 670 cur_addr = machine->device_memory->base; 671 for (info = dimms; info; info = info->next) { 672 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 673 674 addr = di->addr; 675 size = di->size; 676 node = di->node; 677 678 /* Entry for hot-pluggable area */ 679 if (cur_addr < addr) { 680 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 681 g_assert(drc); 682 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 683 cur_addr, spapr_drc_index(drc), -1, 0); 684 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 685 nr_entries++; 686 } 687 688 /* Entry for DIMM */ 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell(size / lmb_size, addr, 692 spapr_drc_index(drc), node, 693 SPAPR_LMB_FLAGS_ASSIGNED); 694 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 695 nr_entries++; 696 cur_addr = addr + size; 697 } 698 699 /* Entry for remaining hotpluggable area */ 700 if (cur_addr < mem_end) { 701 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 702 g_assert(drc); 703 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 704 cur_addr, spapr_drc_index(drc), -1, 0); 705 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 706 nr_entries++; 707 } 708 709 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 710 int_buf = cur_index = g_malloc0(buf_len); 711 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 712 cur_index += sizeof(nr_entries); 713 714 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 715 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 716 cur_index += sizeof(elem->cell); 717 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 718 g_free(elem); 719 } 720 721 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 722 g_free(int_buf); 723 if (ret < 0) { 724 return -1; 725 } 726 return 0; 727 } 728 729 /* ibm,dynamic-memory */ 730 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 731 int offset, MemoryDeviceInfoList *dimms) 732 { 733 MachineState *machine = MACHINE(spapr); 734 int i, ret; 735 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 736 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 737 uint32_t nr_lmbs = (machine->device_memory->base + 738 memory_region_size(&machine->device_memory->mr)) / 739 lmb_size; 740 uint32_t *int_buf, *cur_index, buf_len; 741 742 /* 743 * Allocate enough buffer size to fit in ibm,dynamic-memory 744 */ 745 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 746 cur_index = int_buf = g_malloc0(buf_len); 747 int_buf[0] = cpu_to_be32(nr_lmbs); 748 cur_index++; 749 for (i = 0; i < nr_lmbs; i++) { 750 uint64_t addr = i * lmb_size; 751 uint32_t *dynamic_memory = cur_index; 752 753 if (i >= device_lmb_start) { 754 SpaprDrc *drc; 755 756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 757 g_assert(drc); 758 759 dynamic_memory[0] = cpu_to_be32(addr >> 32); 760 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 761 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 762 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 763 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 764 if (memory_region_present(get_system_memory(), addr)) { 765 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 766 } else { 767 dynamic_memory[5] = cpu_to_be32(0); 768 } 769 } else { 770 /* 771 * LMB information for RMA, boot time RAM and gap b/n RAM and 772 * device memory region -- all these are marked as reserved 773 * and as having no valid DRC. 774 */ 775 dynamic_memory[0] = cpu_to_be32(addr >> 32); 776 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 777 dynamic_memory[2] = cpu_to_be32(0); 778 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 779 dynamic_memory[4] = cpu_to_be32(-1); 780 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 781 SPAPR_LMB_FLAGS_DRC_INVALID); 782 } 783 784 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 785 } 786 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 787 g_free(int_buf); 788 if (ret < 0) { 789 return -1; 790 } 791 return 0; 792 } 793 794 /* 795 * Adds ibm,dynamic-reconfiguration-memory node. 796 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 797 * of this device tree node. 798 */ 799 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 800 { 801 MachineState *machine = MACHINE(spapr); 802 int nb_numa_nodes = machine->numa_state->num_nodes; 803 int ret, i, offset; 804 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 805 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 806 uint32_t *int_buf, *cur_index, buf_len; 807 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 808 MemoryDeviceInfoList *dimms = NULL; 809 810 /* 811 * Don't create the node if there is no device memory 812 */ 813 if (machine->ram_size == machine->maxram_size) { 814 return 0; 815 } 816 817 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 818 819 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 820 sizeof(prop_lmb_size)); 821 if (ret < 0) { 822 return ret; 823 } 824 825 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 826 if (ret < 0) { 827 return ret; 828 } 829 830 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 831 if (ret < 0) { 832 return ret; 833 } 834 835 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 836 dimms = qmp_memory_device_list(); 837 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 838 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 839 } else { 840 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 841 } 842 qapi_free_MemoryDeviceInfoList(dimms); 843 844 if (ret < 0) { 845 return ret; 846 } 847 848 /* ibm,associativity-lookup-arrays */ 849 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 850 cur_index = int_buf = g_malloc0(buf_len); 851 int_buf[0] = cpu_to_be32(nr_nodes); 852 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 853 cur_index += 2; 854 for (i = 0; i < nr_nodes; i++) { 855 uint32_t associativity[] = { 856 cpu_to_be32(0x0), 857 cpu_to_be32(0x0), 858 cpu_to_be32(0x0), 859 cpu_to_be32(i) 860 }; 861 memcpy(cur_index, associativity, sizeof(associativity)); 862 cur_index += 4; 863 } 864 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 865 (cur_index - int_buf) * sizeof(uint32_t)); 866 g_free(int_buf); 867 868 return ret; 869 } 870 871 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 872 SpaprOptionVector *ov5_updates) 873 { 874 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 875 int ret = 0, offset; 876 877 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 878 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 879 g_assert(smc->dr_lmb_enabled); 880 ret = spapr_populate_drconf_memory(spapr, fdt); 881 if (ret) { 882 goto out; 883 } 884 } 885 886 offset = fdt_path_offset(fdt, "/chosen"); 887 if (offset < 0) { 888 offset = fdt_add_subnode(fdt, 0, "chosen"); 889 if (offset < 0) { 890 return offset; 891 } 892 } 893 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 894 "ibm,architecture-vec-5"); 895 896 out: 897 return ret; 898 } 899 900 static bool spapr_hotplugged_dev_before_cas(void) 901 { 902 Object *drc_container, *obj; 903 ObjectProperty *prop; 904 ObjectPropertyIterator iter; 905 906 drc_container = container_get(object_get_root(), "/dr-connector"); 907 object_property_iter_init(&iter, drc_container); 908 while ((prop = object_property_iter_next(&iter))) { 909 if (!strstart(prop->type, "link<", NULL)) { 910 continue; 911 } 912 obj = object_property_get_link(drc_container, prop->name, NULL); 913 if (spapr_drc_needed(obj)) { 914 return true; 915 } 916 } 917 return false; 918 } 919 920 static void *spapr_build_fdt(SpaprMachineState *spapr); 921 922 int spapr_h_cas_compose_response(SpaprMachineState *spapr, 923 target_ulong addr, target_ulong size, 924 SpaprOptionVector *ov5_updates) 925 { 926 void *fdt; 927 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 928 929 if (spapr_hotplugged_dev_before_cas()) { 930 return 1; 931 } 932 933 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 934 error_report("SLOF provided an unexpected CAS buffer size " 935 TARGET_FMT_lu " (min: %zu, max: %u)", 936 size, sizeof(hdr), FW_MAX_SIZE); 937 exit(EXIT_FAILURE); 938 } 939 940 size -= sizeof(hdr); 941 942 fdt = spapr_build_fdt(spapr); 943 _FDT((fdt_pack(fdt))); 944 945 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 946 g_free(fdt); 947 trace_spapr_cas_failed(size); 948 return -1; 949 } 950 951 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 952 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 953 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 954 955 g_free(spapr->fdt_blob); 956 spapr->fdt_size = fdt_totalsize(fdt); 957 spapr->fdt_initial_size = spapr->fdt_size; 958 spapr->fdt_blob = fdt; 959 960 return 0; 961 } 962 963 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 964 { 965 MachineState *ms = MACHINE(spapr); 966 int rtas; 967 GString *hypertas = g_string_sized_new(256); 968 GString *qemu_hypertas = g_string_sized_new(256); 969 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 970 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 971 memory_region_size(&MACHINE(spapr)->device_memory->mr); 972 uint32_t lrdr_capacity[] = { 973 cpu_to_be32(max_device_addr >> 32), 974 cpu_to_be32(max_device_addr & 0xffffffff), 975 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 976 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 977 }; 978 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 979 uint32_t maxdomains[] = { 980 cpu_to_be32(4), 981 maxdomain, 982 maxdomain, 983 maxdomain, 984 cpu_to_be32(spapr->gpu_numa_id), 985 }; 986 987 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 988 989 /* hypertas */ 990 add_str(hypertas, "hcall-pft"); 991 add_str(hypertas, "hcall-term"); 992 add_str(hypertas, "hcall-dabr"); 993 add_str(hypertas, "hcall-interrupt"); 994 add_str(hypertas, "hcall-tce"); 995 add_str(hypertas, "hcall-vio"); 996 add_str(hypertas, "hcall-splpar"); 997 add_str(hypertas, "hcall-join"); 998 add_str(hypertas, "hcall-bulk"); 999 add_str(hypertas, "hcall-set-mode"); 1000 add_str(hypertas, "hcall-sprg0"); 1001 add_str(hypertas, "hcall-copy"); 1002 add_str(hypertas, "hcall-debug"); 1003 add_str(hypertas, "hcall-vphn"); 1004 add_str(qemu_hypertas, "hcall-memop1"); 1005 1006 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1007 add_str(hypertas, "hcall-multi-tce"); 1008 } 1009 1010 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1011 add_str(hypertas, "hcall-hpt-resize"); 1012 } 1013 1014 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1015 hypertas->str, hypertas->len)); 1016 g_string_free(hypertas, TRUE); 1017 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1018 qemu_hypertas->str, qemu_hypertas->len)); 1019 g_string_free(qemu_hypertas, TRUE); 1020 1021 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1022 refpoints, sizeof(refpoints))); 1023 1024 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1025 maxdomains, sizeof(maxdomains))); 1026 1027 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1028 RTAS_ERROR_LOG_MAX)); 1029 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1030 RTAS_EVENT_SCAN_RATE)); 1031 1032 g_assert(msi_nonbroken); 1033 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1034 1035 /* 1036 * According to PAPR, rtas ibm,os-term does not guarantee a return 1037 * back to the guest cpu. 1038 * 1039 * While an additional ibm,extended-os-term property indicates 1040 * that rtas call return will always occur. Set this property. 1041 */ 1042 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1043 1044 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1045 lrdr_capacity, sizeof(lrdr_capacity))); 1046 1047 spapr_dt_rtas_tokens(fdt, rtas); 1048 } 1049 1050 /* 1051 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1052 * and the XIVE features that the guest may request and thus the valid 1053 * values for bytes 23..26 of option vector 5: 1054 */ 1055 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1056 int chosen) 1057 { 1058 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1059 1060 char val[2 * 4] = { 1061 23, 0x00, /* XICS / XIVE mode */ 1062 24, 0x00, /* Hash/Radix, filled in below. */ 1063 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1064 26, 0x40, /* Radix options: GTSE == yes. */ 1065 }; 1066 1067 if (spapr->irq->xics && spapr->irq->xive) { 1068 val[1] = SPAPR_OV5_XIVE_BOTH; 1069 } else if (spapr->irq->xive) { 1070 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1071 } else { 1072 assert(spapr->irq->xics); 1073 val[1] = SPAPR_OV5_XIVE_LEGACY; 1074 } 1075 1076 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1077 first_ppc_cpu->compat_pvr)) { 1078 /* 1079 * If we're in a pre POWER9 compat mode then the guest should 1080 * do hash and use the legacy interrupt mode 1081 */ 1082 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1083 val[3] = 0x00; /* Hash */ 1084 } else if (kvm_enabled()) { 1085 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1086 val[3] = 0x80; /* OV5_MMU_BOTH */ 1087 } else if (kvmppc_has_cap_mmu_radix()) { 1088 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1089 } else { 1090 val[3] = 0x00; /* Hash */ 1091 } 1092 } else { 1093 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1094 val[3] = 0xC0; 1095 } 1096 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1097 val, sizeof(val))); 1098 } 1099 1100 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1101 { 1102 MachineState *machine = MACHINE(spapr); 1103 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1104 int chosen; 1105 const char *boot_device = machine->boot_order; 1106 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1107 size_t cb = 0; 1108 char *bootlist = get_boot_devices_list(&cb); 1109 1110 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1111 1112 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1113 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1114 machine->kernel_cmdline)); 1115 } 1116 if (spapr->initrd_size) { 1117 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1118 spapr->initrd_base)); 1119 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1120 spapr->initrd_base + spapr->initrd_size)); 1121 } 1122 1123 if (spapr->kernel_size) { 1124 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1125 cpu_to_be64(spapr->kernel_size) }; 1126 1127 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1128 &kprop, sizeof(kprop))); 1129 if (spapr->kernel_le) { 1130 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1131 } 1132 } 1133 if (boot_menu) { 1134 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1135 } 1136 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1137 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1138 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1139 1140 if (cb && bootlist) { 1141 int i; 1142 1143 for (i = 0; i < cb; i++) { 1144 if (bootlist[i] == '\n') { 1145 bootlist[i] = ' '; 1146 } 1147 } 1148 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1149 } 1150 1151 if (boot_device && strlen(boot_device)) { 1152 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1153 } 1154 1155 if (!spapr->has_graphics && stdout_path) { 1156 /* 1157 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1158 * kernel. New platforms should only use the "stdout-path" property. Set 1159 * the new property and continue using older property to remain 1160 * compatible with the existing firmware. 1161 */ 1162 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1163 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1164 } 1165 1166 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1167 if (smc->linux_pci_probe) { 1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1169 } 1170 1171 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1172 1173 g_free(stdout_path); 1174 g_free(bootlist); 1175 } 1176 1177 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1178 { 1179 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1180 * KVM to work under pHyp with some guest co-operation */ 1181 int hypervisor; 1182 uint8_t hypercall[16]; 1183 1184 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1185 /* indicate KVM hypercall interface */ 1186 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1187 if (kvmppc_has_cap_fixup_hcalls()) { 1188 /* 1189 * Older KVM versions with older guest kernels were broken 1190 * with the magic page, don't allow the guest to map it. 1191 */ 1192 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1193 sizeof(hypercall))) { 1194 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1195 hypercall, sizeof(hypercall))); 1196 } 1197 } 1198 } 1199 1200 static void *spapr_build_fdt(SpaprMachineState *spapr) 1201 { 1202 MachineState *machine = MACHINE(spapr); 1203 MachineClass *mc = MACHINE_GET_CLASS(machine); 1204 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1205 int ret; 1206 void *fdt; 1207 SpaprPhbState *phb; 1208 char *buf; 1209 1210 fdt = g_malloc0(FDT_MAX_SIZE); 1211 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1212 1213 /* Root node */ 1214 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1215 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1216 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1217 1218 /* Guest UUID & Name*/ 1219 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1220 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1221 if (qemu_uuid_set) { 1222 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1223 } 1224 g_free(buf); 1225 1226 if (qemu_get_vm_name()) { 1227 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1228 qemu_get_vm_name())); 1229 } 1230 1231 /* Host Model & Serial Number */ 1232 if (spapr->host_model) { 1233 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1234 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1235 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1236 g_free(buf); 1237 } 1238 1239 if (spapr->host_serial) { 1240 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1241 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1242 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1243 g_free(buf); 1244 } 1245 1246 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1247 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1248 1249 /* /interrupt controller */ 1250 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, 1251 PHANDLE_INTC); 1252 1253 ret = spapr_populate_memory(spapr, fdt); 1254 if (ret < 0) { 1255 error_report("couldn't setup memory nodes in fdt"); 1256 exit(1); 1257 } 1258 1259 /* /vdevice */ 1260 spapr_dt_vdevice(spapr->vio_bus, fdt); 1261 1262 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1263 ret = spapr_rng_populate_dt(fdt); 1264 if (ret < 0) { 1265 error_report("could not set up rng device in the fdt"); 1266 exit(1); 1267 } 1268 } 1269 1270 QLIST_FOREACH(phb, &spapr->phbs, list) { 1271 ret = spapr_dt_phb(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis, NULL); 1272 if (ret < 0) { 1273 error_report("couldn't setup PCI devices in fdt"); 1274 exit(1); 1275 } 1276 } 1277 1278 /* cpus */ 1279 spapr_populate_cpus_dt_node(fdt, spapr); 1280 1281 if (smc->dr_lmb_enabled) { 1282 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1283 } 1284 1285 if (mc->has_hotpluggable_cpus) { 1286 int offset = fdt_path_offset(fdt, "/cpus"); 1287 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1288 if (ret < 0) { 1289 error_report("Couldn't set up CPU DR device tree properties"); 1290 exit(1); 1291 } 1292 } 1293 1294 /* /event-sources */ 1295 spapr_dt_events(spapr, fdt); 1296 1297 /* /rtas */ 1298 spapr_dt_rtas(spapr, fdt); 1299 1300 /* /chosen */ 1301 spapr_dt_chosen(spapr, fdt); 1302 1303 /* /hypervisor */ 1304 if (kvm_enabled()) { 1305 spapr_dt_hypervisor(spapr, fdt); 1306 } 1307 1308 /* Build memory reserve map */ 1309 if (spapr->kernel_size) { 1310 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1311 } 1312 if (spapr->initrd_size) { 1313 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1314 } 1315 1316 /* ibm,client-architecture-support updates */ 1317 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1318 if (ret < 0) { 1319 error_report("couldn't setup CAS properties fdt"); 1320 exit(1); 1321 } 1322 1323 if (smc->dr_phb_enabled) { 1324 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1325 if (ret < 0) { 1326 error_report("Couldn't set up PHB DR device tree properties"); 1327 exit(1); 1328 } 1329 } 1330 1331 return fdt; 1332 } 1333 1334 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1335 { 1336 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1337 } 1338 1339 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1340 PowerPCCPU *cpu) 1341 { 1342 CPUPPCState *env = &cpu->env; 1343 1344 /* The TCG path should also be holding the BQL at this point */ 1345 g_assert(qemu_mutex_iothread_locked()); 1346 1347 if (msr_pr) { 1348 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1349 env->gpr[3] = H_PRIVILEGE; 1350 } else { 1351 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1352 } 1353 } 1354 1355 struct LPCRSyncState { 1356 target_ulong value; 1357 target_ulong mask; 1358 }; 1359 1360 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1361 { 1362 struct LPCRSyncState *s = arg.host_ptr; 1363 PowerPCCPU *cpu = POWERPC_CPU(cs); 1364 CPUPPCState *env = &cpu->env; 1365 target_ulong lpcr; 1366 1367 cpu_synchronize_state(cs); 1368 lpcr = env->spr[SPR_LPCR]; 1369 lpcr &= ~s->mask; 1370 lpcr |= s->value; 1371 ppc_store_lpcr(cpu, lpcr); 1372 } 1373 1374 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1375 { 1376 CPUState *cs; 1377 struct LPCRSyncState s = { 1378 .value = value, 1379 .mask = mask 1380 }; 1381 CPU_FOREACH(cs) { 1382 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1383 } 1384 } 1385 1386 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1387 { 1388 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1389 1390 /* Copy PATE1:GR into PATE0:HR */ 1391 entry->dw0 = spapr->patb_entry & PATE0_HR; 1392 entry->dw1 = spapr->patb_entry; 1393 } 1394 1395 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1396 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1397 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1398 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1399 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1400 1401 /* 1402 * Get the fd to access the kernel htab, re-opening it if necessary 1403 */ 1404 static int get_htab_fd(SpaprMachineState *spapr) 1405 { 1406 Error *local_err = NULL; 1407 1408 if (spapr->htab_fd >= 0) { 1409 return spapr->htab_fd; 1410 } 1411 1412 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1413 if (spapr->htab_fd < 0) { 1414 error_report_err(local_err); 1415 } 1416 1417 return spapr->htab_fd; 1418 } 1419 1420 void close_htab_fd(SpaprMachineState *spapr) 1421 { 1422 if (spapr->htab_fd >= 0) { 1423 close(spapr->htab_fd); 1424 } 1425 spapr->htab_fd = -1; 1426 } 1427 1428 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1429 { 1430 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1431 1432 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1433 } 1434 1435 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1436 { 1437 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1438 1439 assert(kvm_enabled()); 1440 1441 if (!spapr->htab) { 1442 return 0; 1443 } 1444 1445 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1446 } 1447 1448 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1449 hwaddr ptex, int n) 1450 { 1451 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1452 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1453 1454 if (!spapr->htab) { 1455 /* 1456 * HTAB is controlled by KVM. Fetch into temporary buffer 1457 */ 1458 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1459 kvmppc_read_hptes(hptes, ptex, n); 1460 return hptes; 1461 } 1462 1463 /* 1464 * HTAB is controlled by QEMU. Just point to the internally 1465 * accessible PTEG. 1466 */ 1467 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1468 } 1469 1470 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1471 const ppc_hash_pte64_t *hptes, 1472 hwaddr ptex, int n) 1473 { 1474 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1475 1476 if (!spapr->htab) { 1477 g_free((void *)hptes); 1478 } 1479 1480 /* Nothing to do for qemu managed HPT */ 1481 } 1482 1483 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1484 uint64_t pte0, uint64_t pte1) 1485 { 1486 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1487 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1488 1489 if (!spapr->htab) { 1490 kvmppc_write_hpte(ptex, pte0, pte1); 1491 } else { 1492 if (pte0 & HPTE64_V_VALID) { 1493 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1494 /* 1495 * When setting valid, we write PTE1 first. This ensures 1496 * proper synchronization with the reading code in 1497 * ppc_hash64_pteg_search() 1498 */ 1499 smp_wmb(); 1500 stq_p(spapr->htab + offset, pte0); 1501 } else { 1502 stq_p(spapr->htab + offset, pte0); 1503 /* 1504 * When clearing it we set PTE0 first. This ensures proper 1505 * synchronization with the reading code in 1506 * ppc_hash64_pteg_search() 1507 */ 1508 smp_wmb(); 1509 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1510 } 1511 } 1512 } 1513 1514 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1515 uint64_t pte1) 1516 { 1517 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1518 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1519 1520 if (!spapr->htab) { 1521 /* There should always be a hash table when this is called */ 1522 error_report("spapr_hpte_set_c called with no hash table !"); 1523 return; 1524 } 1525 1526 /* The HW performs a non-atomic byte update */ 1527 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1528 } 1529 1530 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1531 uint64_t pte1) 1532 { 1533 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1534 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1535 1536 if (!spapr->htab) { 1537 /* There should always be a hash table when this is called */ 1538 error_report("spapr_hpte_set_r called with no hash table !"); 1539 return; 1540 } 1541 1542 /* The HW performs a non-atomic byte update */ 1543 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1544 } 1545 1546 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1547 { 1548 int shift; 1549 1550 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1551 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1552 * that's much more than is needed for Linux guests */ 1553 shift = ctz64(pow2ceil(ramsize)) - 7; 1554 shift = MAX(shift, 18); /* Minimum architected size */ 1555 shift = MIN(shift, 46); /* Maximum architected size */ 1556 return shift; 1557 } 1558 1559 void spapr_free_hpt(SpaprMachineState *spapr) 1560 { 1561 g_free(spapr->htab); 1562 spapr->htab = NULL; 1563 spapr->htab_shift = 0; 1564 close_htab_fd(spapr); 1565 } 1566 1567 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1568 Error **errp) 1569 { 1570 long rc; 1571 1572 /* Clean up any HPT info from a previous boot */ 1573 spapr_free_hpt(spapr); 1574 1575 rc = kvmppc_reset_htab(shift); 1576 if (rc < 0) { 1577 /* kernel-side HPT needed, but couldn't allocate one */ 1578 error_setg_errno(errp, errno, 1579 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1580 shift); 1581 /* This is almost certainly fatal, but if the caller really 1582 * wants to carry on with shift == 0, it's welcome to try */ 1583 } else if (rc > 0) { 1584 /* kernel-side HPT allocated */ 1585 if (rc != shift) { 1586 error_setg(errp, 1587 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1588 shift, rc); 1589 } 1590 1591 spapr->htab_shift = shift; 1592 spapr->htab = NULL; 1593 } else { 1594 /* kernel-side HPT not needed, allocate in userspace instead */ 1595 size_t size = 1ULL << shift; 1596 int i; 1597 1598 spapr->htab = qemu_memalign(size, size); 1599 if (!spapr->htab) { 1600 error_setg_errno(errp, errno, 1601 "Could not allocate HPT of order %d", shift); 1602 return; 1603 } 1604 1605 memset(spapr->htab, 0, size); 1606 spapr->htab_shift = shift; 1607 1608 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1609 DIRTY_HPTE(HPTE(spapr->htab, i)); 1610 } 1611 } 1612 /* We're setting up a hash table, so that means we're not radix */ 1613 spapr->patb_entry = 0; 1614 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1615 } 1616 1617 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1618 { 1619 int hpt_shift; 1620 1621 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1622 || (spapr->cas_reboot 1623 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1624 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1625 } else { 1626 uint64_t current_ram_size; 1627 1628 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1629 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1630 } 1631 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1632 1633 if (spapr->vrma_adjust) { 1634 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1635 spapr->htab_shift); 1636 } 1637 } 1638 1639 static int spapr_reset_drcs(Object *child, void *opaque) 1640 { 1641 SpaprDrc *drc = 1642 (SpaprDrc *) object_dynamic_cast(child, 1643 TYPE_SPAPR_DR_CONNECTOR); 1644 1645 if (drc) { 1646 spapr_drc_reset(drc); 1647 } 1648 1649 return 0; 1650 } 1651 1652 static void spapr_machine_reset(MachineState *machine) 1653 { 1654 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1655 PowerPCCPU *first_ppc_cpu; 1656 hwaddr fdt_addr; 1657 void *fdt; 1658 int rc; 1659 1660 spapr_caps_apply(spapr); 1661 1662 first_ppc_cpu = POWERPC_CPU(first_cpu); 1663 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1664 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1665 spapr->max_compat_pvr)) { 1666 /* 1667 * If using KVM with radix mode available, VCPUs can be started 1668 * without a HPT because KVM will start them in radix mode. 1669 * Set the GR bit in PATE so that we know there is no HPT. 1670 */ 1671 spapr->patb_entry = PATE1_GR; 1672 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1673 } else { 1674 spapr_setup_hpt_and_vrma(spapr); 1675 } 1676 1677 qemu_devices_reset(); 1678 1679 /* 1680 * If this reset wasn't generated by CAS, we should reset our 1681 * negotiated options and start from scratch 1682 */ 1683 if (!spapr->cas_reboot) { 1684 spapr_ovec_cleanup(spapr->ov5_cas); 1685 spapr->ov5_cas = spapr_ovec_new(); 1686 1687 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1688 } 1689 1690 /* 1691 * This is fixing some of the default configuration of the XIVE 1692 * devices. To be called after the reset of the machine devices. 1693 */ 1694 spapr_irq_reset(spapr, &error_fatal); 1695 1696 /* 1697 * There is no CAS under qtest. Simulate one to please the code that 1698 * depends on spapr->ov5_cas. This is especially needed to test device 1699 * unplug, so we do that before resetting the DRCs. 1700 */ 1701 if (qtest_enabled()) { 1702 spapr_ovec_cleanup(spapr->ov5_cas); 1703 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1704 } 1705 1706 /* DRC reset may cause a device to be unplugged. This will cause troubles 1707 * if this device is used by another device (eg, a running vhost backend 1708 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1709 * situations, we reset DRCs after all devices have been reset. 1710 */ 1711 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1712 1713 spapr_clear_pending_events(spapr); 1714 1715 /* 1716 * We place the device tree and RTAS just below either the top of the RMA, 1717 * or just below 2GB, whichever is lower, so that it can be 1718 * processed with 32-bit real mode code if necessary 1719 */ 1720 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1721 1722 fdt = spapr_build_fdt(spapr); 1723 1724 rc = fdt_pack(fdt); 1725 1726 /* Should only fail if we've built a corrupted tree */ 1727 assert(rc == 0); 1728 1729 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1730 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1731 fdt_totalsize(fdt), FDT_MAX_SIZE); 1732 exit(1); 1733 } 1734 1735 /* Load the fdt */ 1736 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1737 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1738 g_free(spapr->fdt_blob); 1739 spapr->fdt_size = fdt_totalsize(fdt); 1740 spapr->fdt_initial_size = spapr->fdt_size; 1741 spapr->fdt_blob = fdt; 1742 1743 /* Set up the entry state */ 1744 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1745 first_ppc_cpu->env.gpr[5] = 0; 1746 1747 spapr->cas_reboot = false; 1748 } 1749 1750 static void spapr_create_nvram(SpaprMachineState *spapr) 1751 { 1752 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1753 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1754 1755 if (dinfo) { 1756 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1757 &error_fatal); 1758 } 1759 1760 qdev_init_nofail(dev); 1761 1762 spapr->nvram = (struct SpaprNvram *)dev; 1763 } 1764 1765 static void spapr_rtc_create(SpaprMachineState *spapr) 1766 { 1767 object_initialize_child(OBJECT(spapr), "rtc", 1768 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1769 &error_fatal, NULL); 1770 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1771 &error_fatal); 1772 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1773 "date", &error_fatal); 1774 } 1775 1776 /* Returns whether we want to use VGA or not */ 1777 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1778 { 1779 switch (vga_interface_type) { 1780 case VGA_NONE: 1781 return false; 1782 case VGA_DEVICE: 1783 return true; 1784 case VGA_STD: 1785 case VGA_VIRTIO: 1786 case VGA_CIRRUS: 1787 return pci_vga_init(pci_bus) != NULL; 1788 default: 1789 error_setg(errp, 1790 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1791 return false; 1792 } 1793 } 1794 1795 static int spapr_pre_load(void *opaque) 1796 { 1797 int rc; 1798 1799 rc = spapr_caps_pre_load(opaque); 1800 if (rc) { 1801 return rc; 1802 } 1803 1804 return 0; 1805 } 1806 1807 static int spapr_post_load(void *opaque, int version_id) 1808 { 1809 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1810 int err = 0; 1811 1812 err = spapr_caps_post_migration(spapr); 1813 if (err) { 1814 return err; 1815 } 1816 1817 /* 1818 * In earlier versions, there was no separate qdev for the PAPR 1819 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1820 * So when migrating from those versions, poke the incoming offset 1821 * value into the RTC device 1822 */ 1823 if (version_id < 3) { 1824 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1825 if (err) { 1826 return err; 1827 } 1828 } 1829 1830 if (kvm_enabled() && spapr->patb_entry) { 1831 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1832 bool radix = !!(spapr->patb_entry & PATE1_GR); 1833 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1834 1835 /* 1836 * Update LPCR:HR and UPRT as they may not be set properly in 1837 * the stream 1838 */ 1839 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1840 LPCR_HR | LPCR_UPRT); 1841 1842 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1843 if (err) { 1844 error_report("Process table config unsupported by the host"); 1845 return -EINVAL; 1846 } 1847 } 1848 1849 err = spapr_irq_post_load(spapr, version_id); 1850 if (err) { 1851 return err; 1852 } 1853 1854 return err; 1855 } 1856 1857 static int spapr_pre_save(void *opaque) 1858 { 1859 int rc; 1860 1861 rc = spapr_caps_pre_save(opaque); 1862 if (rc) { 1863 return rc; 1864 } 1865 1866 return 0; 1867 } 1868 1869 static bool version_before_3(void *opaque, int version_id) 1870 { 1871 return version_id < 3; 1872 } 1873 1874 static bool spapr_pending_events_needed(void *opaque) 1875 { 1876 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1877 return !QTAILQ_EMPTY(&spapr->pending_events); 1878 } 1879 1880 static const VMStateDescription vmstate_spapr_event_entry = { 1881 .name = "spapr_event_log_entry", 1882 .version_id = 1, 1883 .minimum_version_id = 1, 1884 .fields = (VMStateField[]) { 1885 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1886 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1887 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1888 NULL, extended_length), 1889 VMSTATE_END_OF_LIST() 1890 }, 1891 }; 1892 1893 static const VMStateDescription vmstate_spapr_pending_events = { 1894 .name = "spapr_pending_events", 1895 .version_id = 1, 1896 .minimum_version_id = 1, 1897 .needed = spapr_pending_events_needed, 1898 .fields = (VMStateField[]) { 1899 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1900 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1901 VMSTATE_END_OF_LIST() 1902 }, 1903 }; 1904 1905 static bool spapr_ov5_cas_needed(void *opaque) 1906 { 1907 SpaprMachineState *spapr = opaque; 1908 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1909 SpaprOptionVector *ov5_legacy = spapr_ovec_new(); 1910 SpaprOptionVector *ov5_removed = spapr_ovec_new(); 1911 bool cas_needed; 1912 1913 /* Prior to the introduction of SpaprOptionVector, we had two option 1914 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1915 * Both of these options encode machine topology into the device-tree 1916 * in such a way that the now-booted OS should still be able to interact 1917 * appropriately with QEMU regardless of what options were actually 1918 * negotiatied on the source side. 1919 * 1920 * As such, we can avoid migrating the CAS-negotiated options if these 1921 * are the only options available on the current machine/platform. 1922 * Since these are the only options available for pseries-2.7 and 1923 * earlier, this allows us to maintain old->new/new->old migration 1924 * compatibility. 1925 * 1926 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1927 * via default pseries-2.8 machines and explicit command-line parameters. 1928 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1929 * of the actual CAS-negotiated values to continue working properly. For 1930 * example, availability of memory unplug depends on knowing whether 1931 * OV5_HP_EVT was negotiated via CAS. 1932 * 1933 * Thus, for any cases where the set of available CAS-negotiatable 1934 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1935 * include the CAS-negotiated options in the migration stream, unless 1936 * if they affect boot time behaviour only. 1937 */ 1938 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1939 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1940 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1941 1942 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1943 * the mask itself since in the future it's possible "legacy" bits may be 1944 * removed via machine options, which could generate a false positive 1945 * that breaks migration. 1946 */ 1947 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1948 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1949 1950 spapr_ovec_cleanup(ov5_mask); 1951 spapr_ovec_cleanup(ov5_legacy); 1952 spapr_ovec_cleanup(ov5_removed); 1953 1954 return cas_needed; 1955 } 1956 1957 static const VMStateDescription vmstate_spapr_ov5_cas = { 1958 .name = "spapr_option_vector_ov5_cas", 1959 .version_id = 1, 1960 .minimum_version_id = 1, 1961 .needed = spapr_ov5_cas_needed, 1962 .fields = (VMStateField[]) { 1963 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1964 vmstate_spapr_ovec, SpaprOptionVector), 1965 VMSTATE_END_OF_LIST() 1966 }, 1967 }; 1968 1969 static bool spapr_patb_entry_needed(void *opaque) 1970 { 1971 SpaprMachineState *spapr = opaque; 1972 1973 return !!spapr->patb_entry; 1974 } 1975 1976 static const VMStateDescription vmstate_spapr_patb_entry = { 1977 .name = "spapr_patb_entry", 1978 .version_id = 1, 1979 .minimum_version_id = 1, 1980 .needed = spapr_patb_entry_needed, 1981 .fields = (VMStateField[]) { 1982 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1983 VMSTATE_END_OF_LIST() 1984 }, 1985 }; 1986 1987 static bool spapr_irq_map_needed(void *opaque) 1988 { 1989 SpaprMachineState *spapr = opaque; 1990 1991 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1992 } 1993 1994 static const VMStateDescription vmstate_spapr_irq_map = { 1995 .name = "spapr_irq_map", 1996 .version_id = 1, 1997 .minimum_version_id = 1, 1998 .needed = spapr_irq_map_needed, 1999 .fields = (VMStateField[]) { 2000 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2001 VMSTATE_END_OF_LIST() 2002 }, 2003 }; 2004 2005 static bool spapr_dtb_needed(void *opaque) 2006 { 2007 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2008 2009 return smc->update_dt_enabled; 2010 } 2011 2012 static int spapr_dtb_pre_load(void *opaque) 2013 { 2014 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2015 2016 g_free(spapr->fdt_blob); 2017 spapr->fdt_blob = NULL; 2018 spapr->fdt_size = 0; 2019 2020 return 0; 2021 } 2022 2023 static const VMStateDescription vmstate_spapr_dtb = { 2024 .name = "spapr_dtb", 2025 .version_id = 1, 2026 .minimum_version_id = 1, 2027 .needed = spapr_dtb_needed, 2028 .pre_load = spapr_dtb_pre_load, 2029 .fields = (VMStateField[]) { 2030 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2031 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2032 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2033 fdt_size), 2034 VMSTATE_END_OF_LIST() 2035 }, 2036 }; 2037 2038 static const VMStateDescription vmstate_spapr = { 2039 .name = "spapr", 2040 .version_id = 3, 2041 .minimum_version_id = 1, 2042 .pre_load = spapr_pre_load, 2043 .post_load = spapr_post_load, 2044 .pre_save = spapr_pre_save, 2045 .fields = (VMStateField[]) { 2046 /* used to be @next_irq */ 2047 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2048 2049 /* RTC offset */ 2050 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2051 2052 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2053 VMSTATE_END_OF_LIST() 2054 }, 2055 .subsections = (const VMStateDescription*[]) { 2056 &vmstate_spapr_ov5_cas, 2057 &vmstate_spapr_patb_entry, 2058 &vmstate_spapr_pending_events, 2059 &vmstate_spapr_cap_htm, 2060 &vmstate_spapr_cap_vsx, 2061 &vmstate_spapr_cap_dfp, 2062 &vmstate_spapr_cap_cfpc, 2063 &vmstate_spapr_cap_sbbc, 2064 &vmstate_spapr_cap_ibs, 2065 &vmstate_spapr_cap_hpt_maxpagesize, 2066 &vmstate_spapr_irq_map, 2067 &vmstate_spapr_cap_nested_kvm_hv, 2068 &vmstate_spapr_dtb, 2069 &vmstate_spapr_cap_large_decr, 2070 &vmstate_spapr_cap_ccf_assist, 2071 NULL 2072 } 2073 }; 2074 2075 static int htab_save_setup(QEMUFile *f, void *opaque) 2076 { 2077 SpaprMachineState *spapr = opaque; 2078 2079 /* "Iteration" header */ 2080 if (!spapr->htab_shift) { 2081 qemu_put_be32(f, -1); 2082 } else { 2083 qemu_put_be32(f, spapr->htab_shift); 2084 } 2085 2086 if (spapr->htab) { 2087 spapr->htab_save_index = 0; 2088 spapr->htab_first_pass = true; 2089 } else { 2090 if (spapr->htab_shift) { 2091 assert(kvm_enabled()); 2092 } 2093 } 2094 2095 2096 return 0; 2097 } 2098 2099 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2100 int chunkstart, int n_valid, int n_invalid) 2101 { 2102 qemu_put_be32(f, chunkstart); 2103 qemu_put_be16(f, n_valid); 2104 qemu_put_be16(f, n_invalid); 2105 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2106 HASH_PTE_SIZE_64 * n_valid); 2107 } 2108 2109 static void htab_save_end_marker(QEMUFile *f) 2110 { 2111 qemu_put_be32(f, 0); 2112 qemu_put_be16(f, 0); 2113 qemu_put_be16(f, 0); 2114 } 2115 2116 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2117 int64_t max_ns) 2118 { 2119 bool has_timeout = max_ns != -1; 2120 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2121 int index = spapr->htab_save_index; 2122 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2123 2124 assert(spapr->htab_first_pass); 2125 2126 do { 2127 int chunkstart; 2128 2129 /* Consume invalid HPTEs */ 2130 while ((index < htabslots) 2131 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2132 CLEAN_HPTE(HPTE(spapr->htab, index)); 2133 index++; 2134 } 2135 2136 /* Consume valid HPTEs */ 2137 chunkstart = index; 2138 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2139 && HPTE_VALID(HPTE(spapr->htab, index))) { 2140 CLEAN_HPTE(HPTE(spapr->htab, index)); 2141 index++; 2142 } 2143 2144 if (index > chunkstart) { 2145 int n_valid = index - chunkstart; 2146 2147 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2148 2149 if (has_timeout && 2150 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2151 break; 2152 } 2153 } 2154 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2155 2156 if (index >= htabslots) { 2157 assert(index == htabslots); 2158 index = 0; 2159 spapr->htab_first_pass = false; 2160 } 2161 spapr->htab_save_index = index; 2162 } 2163 2164 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2165 int64_t max_ns) 2166 { 2167 bool final = max_ns < 0; 2168 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2169 int examined = 0, sent = 0; 2170 int index = spapr->htab_save_index; 2171 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2172 2173 assert(!spapr->htab_first_pass); 2174 2175 do { 2176 int chunkstart, invalidstart; 2177 2178 /* Consume non-dirty HPTEs */ 2179 while ((index < htabslots) 2180 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2181 index++; 2182 examined++; 2183 } 2184 2185 chunkstart = index; 2186 /* Consume valid dirty HPTEs */ 2187 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2188 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2189 && HPTE_VALID(HPTE(spapr->htab, index))) { 2190 CLEAN_HPTE(HPTE(spapr->htab, index)); 2191 index++; 2192 examined++; 2193 } 2194 2195 invalidstart = index; 2196 /* Consume invalid dirty HPTEs */ 2197 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2198 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2199 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2200 CLEAN_HPTE(HPTE(spapr->htab, index)); 2201 index++; 2202 examined++; 2203 } 2204 2205 if (index > chunkstart) { 2206 int n_valid = invalidstart - chunkstart; 2207 int n_invalid = index - invalidstart; 2208 2209 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2210 sent += index - chunkstart; 2211 2212 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2213 break; 2214 } 2215 } 2216 2217 if (examined >= htabslots) { 2218 break; 2219 } 2220 2221 if (index >= htabslots) { 2222 assert(index == htabslots); 2223 index = 0; 2224 } 2225 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2226 2227 if (index >= htabslots) { 2228 assert(index == htabslots); 2229 index = 0; 2230 } 2231 2232 spapr->htab_save_index = index; 2233 2234 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2235 } 2236 2237 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2238 #define MAX_KVM_BUF_SIZE 2048 2239 2240 static int htab_save_iterate(QEMUFile *f, void *opaque) 2241 { 2242 SpaprMachineState *spapr = opaque; 2243 int fd; 2244 int rc = 0; 2245 2246 /* Iteration header */ 2247 if (!spapr->htab_shift) { 2248 qemu_put_be32(f, -1); 2249 return 1; 2250 } else { 2251 qemu_put_be32(f, 0); 2252 } 2253 2254 if (!spapr->htab) { 2255 assert(kvm_enabled()); 2256 2257 fd = get_htab_fd(spapr); 2258 if (fd < 0) { 2259 return fd; 2260 } 2261 2262 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2263 if (rc < 0) { 2264 return rc; 2265 } 2266 } else if (spapr->htab_first_pass) { 2267 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2268 } else { 2269 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2270 } 2271 2272 htab_save_end_marker(f); 2273 2274 return rc; 2275 } 2276 2277 static int htab_save_complete(QEMUFile *f, void *opaque) 2278 { 2279 SpaprMachineState *spapr = opaque; 2280 int fd; 2281 2282 /* Iteration header */ 2283 if (!spapr->htab_shift) { 2284 qemu_put_be32(f, -1); 2285 return 0; 2286 } else { 2287 qemu_put_be32(f, 0); 2288 } 2289 2290 if (!spapr->htab) { 2291 int rc; 2292 2293 assert(kvm_enabled()); 2294 2295 fd = get_htab_fd(spapr); 2296 if (fd < 0) { 2297 return fd; 2298 } 2299 2300 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2301 if (rc < 0) { 2302 return rc; 2303 } 2304 } else { 2305 if (spapr->htab_first_pass) { 2306 htab_save_first_pass(f, spapr, -1); 2307 } 2308 htab_save_later_pass(f, spapr, -1); 2309 } 2310 2311 /* End marker */ 2312 htab_save_end_marker(f); 2313 2314 return 0; 2315 } 2316 2317 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2318 { 2319 SpaprMachineState *spapr = opaque; 2320 uint32_t section_hdr; 2321 int fd = -1; 2322 Error *local_err = NULL; 2323 2324 if (version_id < 1 || version_id > 1) { 2325 error_report("htab_load() bad version"); 2326 return -EINVAL; 2327 } 2328 2329 section_hdr = qemu_get_be32(f); 2330 2331 if (section_hdr == -1) { 2332 spapr_free_hpt(spapr); 2333 return 0; 2334 } 2335 2336 if (section_hdr) { 2337 /* First section gives the htab size */ 2338 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2339 if (local_err) { 2340 error_report_err(local_err); 2341 return -EINVAL; 2342 } 2343 return 0; 2344 } 2345 2346 if (!spapr->htab) { 2347 assert(kvm_enabled()); 2348 2349 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2350 if (fd < 0) { 2351 error_report_err(local_err); 2352 return fd; 2353 } 2354 } 2355 2356 while (true) { 2357 uint32_t index; 2358 uint16_t n_valid, n_invalid; 2359 2360 index = qemu_get_be32(f); 2361 n_valid = qemu_get_be16(f); 2362 n_invalid = qemu_get_be16(f); 2363 2364 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2365 /* End of Stream */ 2366 break; 2367 } 2368 2369 if ((index + n_valid + n_invalid) > 2370 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2371 /* Bad index in stream */ 2372 error_report( 2373 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2374 index, n_valid, n_invalid, spapr->htab_shift); 2375 return -EINVAL; 2376 } 2377 2378 if (spapr->htab) { 2379 if (n_valid) { 2380 qemu_get_buffer(f, HPTE(spapr->htab, index), 2381 HASH_PTE_SIZE_64 * n_valid); 2382 } 2383 if (n_invalid) { 2384 memset(HPTE(spapr->htab, index + n_valid), 0, 2385 HASH_PTE_SIZE_64 * n_invalid); 2386 } 2387 } else { 2388 int rc; 2389 2390 assert(fd >= 0); 2391 2392 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2393 if (rc < 0) { 2394 return rc; 2395 } 2396 } 2397 } 2398 2399 if (!spapr->htab) { 2400 assert(fd >= 0); 2401 close(fd); 2402 } 2403 2404 return 0; 2405 } 2406 2407 static void htab_save_cleanup(void *opaque) 2408 { 2409 SpaprMachineState *spapr = opaque; 2410 2411 close_htab_fd(spapr); 2412 } 2413 2414 static SaveVMHandlers savevm_htab_handlers = { 2415 .save_setup = htab_save_setup, 2416 .save_live_iterate = htab_save_iterate, 2417 .save_live_complete_precopy = htab_save_complete, 2418 .save_cleanup = htab_save_cleanup, 2419 .load_state = htab_load, 2420 }; 2421 2422 static void spapr_boot_set(void *opaque, const char *boot_device, 2423 Error **errp) 2424 { 2425 MachineState *machine = MACHINE(opaque); 2426 machine->boot_order = g_strdup(boot_device); 2427 } 2428 2429 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2430 { 2431 MachineState *machine = MACHINE(spapr); 2432 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2433 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2434 int i; 2435 2436 for (i = 0; i < nr_lmbs; i++) { 2437 uint64_t addr; 2438 2439 addr = i * lmb_size + machine->device_memory->base; 2440 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2441 addr / lmb_size); 2442 } 2443 } 2444 2445 /* 2446 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2447 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2448 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2449 */ 2450 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2451 { 2452 int i; 2453 2454 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2455 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2456 " is not aligned to %" PRIu64 " MiB", 2457 machine->ram_size, 2458 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2459 return; 2460 } 2461 2462 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2463 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2464 " is not aligned to %" PRIu64 " MiB", 2465 machine->ram_size, 2466 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2467 return; 2468 } 2469 2470 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2471 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2472 error_setg(errp, 2473 "Node %d memory size 0x%" PRIx64 2474 " is not aligned to %" PRIu64 " MiB", 2475 i, machine->numa_state->nodes[i].node_mem, 2476 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2477 return; 2478 } 2479 } 2480 } 2481 2482 /* find cpu slot in machine->possible_cpus by core_id */ 2483 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2484 { 2485 int index = id / ms->smp.threads; 2486 2487 if (index >= ms->possible_cpus->len) { 2488 return NULL; 2489 } 2490 if (idx) { 2491 *idx = index; 2492 } 2493 return &ms->possible_cpus->cpus[index]; 2494 } 2495 2496 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2497 { 2498 MachineState *ms = MACHINE(spapr); 2499 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2500 Error *local_err = NULL; 2501 bool vsmt_user = !!spapr->vsmt; 2502 int kvm_smt = kvmppc_smt_threads(); 2503 int ret; 2504 unsigned int smp_threads = ms->smp.threads; 2505 2506 if (!kvm_enabled() && (smp_threads > 1)) { 2507 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2508 "on a pseries machine"); 2509 goto out; 2510 } 2511 if (!is_power_of_2(smp_threads)) { 2512 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2513 "machine because it must be a power of 2", smp_threads); 2514 goto out; 2515 } 2516 2517 /* Detemine the VSMT mode to use: */ 2518 if (vsmt_user) { 2519 if (spapr->vsmt < smp_threads) { 2520 error_setg(&local_err, "Cannot support VSMT mode %d" 2521 " because it must be >= threads/core (%d)", 2522 spapr->vsmt, smp_threads); 2523 goto out; 2524 } 2525 /* In this case, spapr->vsmt has been set by the command line */ 2526 } else if (!smc->smp_threads_vsmt) { 2527 /* 2528 * Default VSMT value is tricky, because we need it to be as 2529 * consistent as possible (for migration), but this requires 2530 * changing it for at least some existing cases. We pick 8 as 2531 * the value that we'd get with KVM on POWER8, the 2532 * overwhelmingly common case in production systems. 2533 */ 2534 spapr->vsmt = MAX(8, smp_threads); 2535 } else { 2536 spapr->vsmt = smp_threads; 2537 } 2538 2539 /* KVM: If necessary, set the SMT mode: */ 2540 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2541 ret = kvmppc_set_smt_threads(spapr->vsmt); 2542 if (ret) { 2543 /* Looks like KVM isn't able to change VSMT mode */ 2544 error_setg(&local_err, 2545 "Failed to set KVM's VSMT mode to %d (errno %d)", 2546 spapr->vsmt, ret); 2547 /* We can live with that if the default one is big enough 2548 * for the number of threads, and a submultiple of the one 2549 * we want. In this case we'll waste some vcpu ids, but 2550 * behaviour will be correct */ 2551 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2552 warn_report_err(local_err); 2553 local_err = NULL; 2554 goto out; 2555 } else { 2556 if (!vsmt_user) { 2557 error_append_hint(&local_err, 2558 "On PPC, a VM with %d threads/core" 2559 " on a host with %d threads/core" 2560 " requires the use of VSMT mode %d.\n", 2561 smp_threads, kvm_smt, spapr->vsmt); 2562 } 2563 kvmppc_hint_smt_possible(&local_err); 2564 goto out; 2565 } 2566 } 2567 } 2568 /* else TCG: nothing to do currently */ 2569 out: 2570 error_propagate(errp, local_err); 2571 } 2572 2573 static void spapr_init_cpus(SpaprMachineState *spapr) 2574 { 2575 MachineState *machine = MACHINE(spapr); 2576 MachineClass *mc = MACHINE_GET_CLASS(machine); 2577 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2578 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2579 const CPUArchIdList *possible_cpus; 2580 unsigned int smp_cpus = machine->smp.cpus; 2581 unsigned int smp_threads = machine->smp.threads; 2582 unsigned int max_cpus = machine->smp.max_cpus; 2583 int boot_cores_nr = smp_cpus / smp_threads; 2584 int i; 2585 2586 possible_cpus = mc->possible_cpu_arch_ids(machine); 2587 if (mc->has_hotpluggable_cpus) { 2588 if (smp_cpus % smp_threads) { 2589 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2590 smp_cpus, smp_threads); 2591 exit(1); 2592 } 2593 if (max_cpus % smp_threads) { 2594 error_report("max_cpus (%u) must be multiple of threads (%u)", 2595 max_cpus, smp_threads); 2596 exit(1); 2597 } 2598 } else { 2599 if (max_cpus != smp_cpus) { 2600 error_report("This machine version does not support CPU hotplug"); 2601 exit(1); 2602 } 2603 boot_cores_nr = possible_cpus->len; 2604 } 2605 2606 if (smc->pre_2_10_has_unused_icps) { 2607 int i; 2608 2609 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2610 /* Dummy entries get deregistered when real ICPState objects 2611 * are registered during CPU core hotplug. 2612 */ 2613 pre_2_10_vmstate_register_dummy_icp(i); 2614 } 2615 } 2616 2617 for (i = 0; i < possible_cpus->len; i++) { 2618 int core_id = i * smp_threads; 2619 2620 if (mc->has_hotpluggable_cpus) { 2621 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2622 spapr_vcpu_id(spapr, core_id)); 2623 } 2624 2625 if (i < boot_cores_nr) { 2626 Object *core = object_new(type); 2627 int nr_threads = smp_threads; 2628 2629 /* Handle the partially filled core for older machine types */ 2630 if ((i + 1) * smp_threads >= smp_cpus) { 2631 nr_threads = smp_cpus - i * smp_threads; 2632 } 2633 2634 object_property_set_int(core, nr_threads, "nr-threads", 2635 &error_fatal); 2636 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2637 &error_fatal); 2638 object_property_set_bool(core, true, "realized", &error_fatal); 2639 2640 object_unref(core); 2641 } 2642 } 2643 } 2644 2645 static PCIHostState *spapr_create_default_phb(void) 2646 { 2647 DeviceState *dev; 2648 2649 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2650 qdev_prop_set_uint32(dev, "index", 0); 2651 qdev_init_nofail(dev); 2652 2653 return PCI_HOST_BRIDGE(dev); 2654 } 2655 2656 /* pSeries LPAR / sPAPR hardware init */ 2657 static void spapr_machine_init(MachineState *machine) 2658 { 2659 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2660 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2661 const char *kernel_filename = machine->kernel_filename; 2662 const char *initrd_filename = machine->initrd_filename; 2663 PCIHostState *phb; 2664 int i; 2665 MemoryRegion *sysmem = get_system_memory(); 2666 MemoryRegion *ram = g_new(MemoryRegion, 1); 2667 hwaddr node0_size = spapr_node0_size(machine); 2668 long load_limit, fw_size; 2669 char *filename; 2670 Error *resize_hpt_err = NULL; 2671 2672 msi_nonbroken = true; 2673 2674 QLIST_INIT(&spapr->phbs); 2675 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2676 2677 /* Determine capabilities to run with */ 2678 spapr_caps_init(spapr); 2679 2680 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2681 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2682 /* 2683 * If the user explicitly requested a mode we should either 2684 * supply it, or fail completely (which we do below). But if 2685 * it's not set explicitly, we reset our mode to something 2686 * that works 2687 */ 2688 if (resize_hpt_err) { 2689 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2690 error_free(resize_hpt_err); 2691 resize_hpt_err = NULL; 2692 } else { 2693 spapr->resize_hpt = smc->resize_hpt_default; 2694 } 2695 } 2696 2697 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2698 2699 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2700 /* 2701 * User requested HPT resize, but this host can't supply it. Bail out 2702 */ 2703 error_report_err(resize_hpt_err); 2704 exit(1); 2705 } 2706 2707 spapr->rma_size = node0_size; 2708 2709 /* With KVM, we don't actually know whether KVM supports an 2710 * unbounded RMA (PR KVM) or is limited by the hash table size 2711 * (HV KVM using VRMA), so we always assume the latter 2712 * 2713 * In that case, we also limit the initial allocations for RTAS 2714 * etc... to 256M since we have no way to know what the VRMA size 2715 * is going to be as it depends on the size of the hash table 2716 * which isn't determined yet. 2717 */ 2718 if (kvm_enabled()) { 2719 spapr->vrma_adjust = 1; 2720 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2721 } 2722 2723 /* Actually we don't support unbounded RMA anymore since we added 2724 * proper emulation of HV mode. The max we can get is 16G which 2725 * also happens to be what we configure for PAPR mode so make sure 2726 * we don't do anything bigger than that 2727 */ 2728 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2729 2730 if (spapr->rma_size > node0_size) { 2731 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2732 spapr->rma_size); 2733 exit(1); 2734 } 2735 2736 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2737 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2738 2739 /* 2740 * VSMT must be set in order to be able to compute VCPU ids, ie to 2741 * call spapr_max_server_number() or spapr_vcpu_id(). 2742 */ 2743 spapr_set_vsmt_mode(spapr, &error_fatal); 2744 2745 /* Set up Interrupt Controller before we create the VCPUs */ 2746 spapr_irq_init(spapr, &error_fatal); 2747 2748 /* Set up containers for ibm,client-architecture-support negotiated options 2749 */ 2750 spapr->ov5 = spapr_ovec_new(); 2751 spapr->ov5_cas = spapr_ovec_new(); 2752 2753 if (smc->dr_lmb_enabled) { 2754 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2755 spapr_validate_node_memory(machine, &error_fatal); 2756 } 2757 2758 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2759 2760 /* advertise support for dedicated HP event source to guests */ 2761 if (spapr->use_hotplug_event_source) { 2762 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2763 } 2764 2765 /* advertise support for HPT resizing */ 2766 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2767 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2768 } 2769 2770 /* advertise support for ibm,dyamic-memory-v2 */ 2771 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2772 2773 /* advertise XIVE on POWER9 machines */ 2774 if (spapr->irq->xive) { 2775 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2776 } 2777 2778 /* init CPUs */ 2779 spapr_init_cpus(spapr); 2780 2781 /* 2782 * check we don't have a memory-less/cpu-less NUMA node 2783 * Firmware relies on the existing memory/cpu topology to provide the 2784 * NUMA topology to the kernel. 2785 * And the linux kernel needs to know the NUMA topology at start 2786 * to be able to hotplug CPUs later. 2787 */ 2788 if (machine->numa_state->num_nodes) { 2789 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2790 /* check for memory-less node */ 2791 if (machine->numa_state->nodes[i].node_mem == 0) { 2792 CPUState *cs; 2793 int found = 0; 2794 /* check for cpu-less node */ 2795 CPU_FOREACH(cs) { 2796 PowerPCCPU *cpu = POWERPC_CPU(cs); 2797 if (cpu->node_id == i) { 2798 found = 1; 2799 break; 2800 } 2801 } 2802 /* memory-less and cpu-less node */ 2803 if (!found) { 2804 error_report( 2805 "Memory-less/cpu-less nodes are not supported (node %d)", 2806 i); 2807 exit(1); 2808 } 2809 } 2810 } 2811 2812 } 2813 2814 /* 2815 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2816 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2817 * called from vPHB reset handler so we initialize the counter here. 2818 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2819 * must be equally distant from any other node. 2820 * The final value of spapr->gpu_numa_id is going to be written to 2821 * max-associativity-domains in spapr_build_fdt(). 2822 */ 2823 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2824 2825 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2826 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2827 spapr->max_compat_pvr)) { 2828 /* KVM and TCG always allow GTSE with radix... */ 2829 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2830 } 2831 /* ... but not with hash (currently). */ 2832 2833 if (kvm_enabled()) { 2834 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2835 kvmppc_enable_logical_ci_hcalls(); 2836 kvmppc_enable_set_mode_hcall(); 2837 2838 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2839 kvmppc_enable_clear_ref_mod_hcalls(); 2840 2841 /* Enable H_PAGE_INIT */ 2842 kvmppc_enable_h_page_init(); 2843 } 2844 2845 /* allocate RAM */ 2846 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2847 machine->ram_size); 2848 memory_region_add_subregion(sysmem, 0, ram); 2849 2850 /* always allocate the device memory information */ 2851 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2852 2853 /* initialize hotplug memory address space */ 2854 if (machine->ram_size < machine->maxram_size) { 2855 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2856 /* 2857 * Limit the number of hotpluggable memory slots to half the number 2858 * slots that KVM supports, leaving the other half for PCI and other 2859 * devices. However ensure that number of slots doesn't drop below 32. 2860 */ 2861 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2862 SPAPR_MAX_RAM_SLOTS; 2863 2864 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2865 max_memslots = SPAPR_MAX_RAM_SLOTS; 2866 } 2867 if (machine->ram_slots > max_memslots) { 2868 error_report("Specified number of memory slots %" 2869 PRIu64" exceeds max supported %d", 2870 machine->ram_slots, max_memslots); 2871 exit(1); 2872 } 2873 2874 machine->device_memory->base = ROUND_UP(machine->ram_size, 2875 SPAPR_DEVICE_MEM_ALIGN); 2876 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2877 "device-memory", device_mem_size); 2878 memory_region_add_subregion(sysmem, machine->device_memory->base, 2879 &machine->device_memory->mr); 2880 } 2881 2882 if (smc->dr_lmb_enabled) { 2883 spapr_create_lmb_dr_connectors(spapr); 2884 } 2885 2886 /* Set up RTAS event infrastructure */ 2887 spapr_events_init(spapr); 2888 2889 /* Set up the RTC RTAS interfaces */ 2890 spapr_rtc_create(spapr); 2891 2892 /* Set up VIO bus */ 2893 spapr->vio_bus = spapr_vio_bus_init(); 2894 2895 for (i = 0; i < serial_max_hds(); i++) { 2896 if (serial_hd(i)) { 2897 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2898 } 2899 } 2900 2901 /* We always have at least the nvram device on VIO */ 2902 spapr_create_nvram(spapr); 2903 2904 /* 2905 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2906 * connectors (described in root DT node's "ibm,drc-types" property) 2907 * are pre-initialized here. additional child connectors (such as 2908 * connectors for a PHBs PCI slots) are added as needed during their 2909 * parent's realization. 2910 */ 2911 if (smc->dr_phb_enabled) { 2912 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2913 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2914 } 2915 } 2916 2917 /* Set up PCI */ 2918 spapr_pci_rtas_init(); 2919 2920 phb = spapr_create_default_phb(); 2921 2922 for (i = 0; i < nb_nics; i++) { 2923 NICInfo *nd = &nd_table[i]; 2924 2925 if (!nd->model) { 2926 nd->model = g_strdup("spapr-vlan"); 2927 } 2928 2929 if (g_str_equal(nd->model, "spapr-vlan") || 2930 g_str_equal(nd->model, "ibmveth")) { 2931 spapr_vlan_create(spapr->vio_bus, nd); 2932 } else { 2933 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2934 } 2935 } 2936 2937 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2938 spapr_vscsi_create(spapr->vio_bus); 2939 } 2940 2941 /* Graphics */ 2942 if (spapr_vga_init(phb->bus, &error_fatal)) { 2943 spapr->has_graphics = true; 2944 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2945 } 2946 2947 if (machine->usb) { 2948 if (smc->use_ohci_by_default) { 2949 pci_create_simple(phb->bus, -1, "pci-ohci"); 2950 } else { 2951 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2952 } 2953 2954 if (spapr->has_graphics) { 2955 USBBus *usb_bus = usb_bus_find(-1); 2956 2957 usb_create_simple(usb_bus, "usb-kbd"); 2958 usb_create_simple(usb_bus, "usb-mouse"); 2959 } 2960 } 2961 2962 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2963 error_report( 2964 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2965 MIN_RMA_SLOF); 2966 exit(1); 2967 } 2968 2969 if (kernel_filename) { 2970 uint64_t lowaddr = 0; 2971 2972 spapr->kernel_size = load_elf(kernel_filename, NULL, 2973 translate_kernel_address, NULL, 2974 NULL, &lowaddr, NULL, 1, 2975 PPC_ELF_MACHINE, 0, 0); 2976 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2977 spapr->kernel_size = load_elf(kernel_filename, NULL, 2978 translate_kernel_address, NULL, NULL, 2979 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2980 0, 0); 2981 spapr->kernel_le = spapr->kernel_size > 0; 2982 } 2983 if (spapr->kernel_size < 0) { 2984 error_report("error loading %s: %s", kernel_filename, 2985 load_elf_strerror(spapr->kernel_size)); 2986 exit(1); 2987 } 2988 2989 /* load initrd */ 2990 if (initrd_filename) { 2991 /* Try to locate the initrd in the gap between the kernel 2992 * and the firmware. Add a bit of space just in case 2993 */ 2994 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2995 + 0x1ffff) & ~0xffff; 2996 spapr->initrd_size = load_image_targphys(initrd_filename, 2997 spapr->initrd_base, 2998 load_limit 2999 - spapr->initrd_base); 3000 if (spapr->initrd_size < 0) { 3001 error_report("could not load initial ram disk '%s'", 3002 initrd_filename); 3003 exit(1); 3004 } 3005 } 3006 } 3007 3008 if (bios_name == NULL) { 3009 bios_name = FW_FILE_NAME; 3010 } 3011 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3012 if (!filename) { 3013 error_report("Could not find LPAR firmware '%s'", bios_name); 3014 exit(1); 3015 } 3016 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3017 if (fw_size <= 0) { 3018 error_report("Could not load LPAR firmware '%s'", filename); 3019 exit(1); 3020 } 3021 g_free(filename); 3022 3023 /* FIXME: Should register things through the MachineState's qdev 3024 * interface, this is a legacy from the sPAPREnvironment structure 3025 * which predated MachineState but had a similar function */ 3026 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3027 register_savevm_live("spapr/htab", -1, 1, 3028 &savevm_htab_handlers, spapr); 3029 3030 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3031 &error_fatal); 3032 3033 qemu_register_boot_set(spapr_boot_set, spapr); 3034 3035 /* 3036 * Nothing needs to be done to resume a suspended guest because 3037 * suspending does not change the machine state, so no need for 3038 * a ->wakeup method. 3039 */ 3040 qemu_register_wakeup_support(); 3041 3042 if (kvm_enabled()) { 3043 /* to stop and start vmclock */ 3044 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3045 &spapr->tb); 3046 3047 kvmppc_spapr_enable_inkernel_multitce(); 3048 } 3049 } 3050 3051 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3052 { 3053 if (!vm_type) { 3054 return 0; 3055 } 3056 3057 if (!strcmp(vm_type, "HV")) { 3058 return 1; 3059 } 3060 3061 if (!strcmp(vm_type, "PR")) { 3062 return 2; 3063 } 3064 3065 error_report("Unknown kvm-type specified '%s'", vm_type); 3066 exit(1); 3067 } 3068 3069 /* 3070 * Implementation of an interface to adjust firmware path 3071 * for the bootindex property handling. 3072 */ 3073 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3074 DeviceState *dev) 3075 { 3076 #define CAST(type, obj, name) \ 3077 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3078 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3079 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3080 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3081 3082 if (d) { 3083 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3084 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3085 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3086 3087 if (spapr) { 3088 /* 3089 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3090 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3091 * 0x8000 | (target << 8) | (bus << 5) | lun 3092 * (see the "Logical unit addressing format" table in SAM5) 3093 */ 3094 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3095 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3096 (uint64_t)id << 48); 3097 } else if (virtio) { 3098 /* 3099 * We use SRP luns of the form 01000000 | (target << 8) | lun 3100 * in the top 32 bits of the 64-bit LUN 3101 * Note: the quote above is from SLOF and it is wrong, 3102 * the actual binding is: 3103 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3104 */ 3105 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3106 if (d->lun >= 256) { 3107 /* Use the LUN "flat space addressing method" */ 3108 id |= 0x4000; 3109 } 3110 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3111 (uint64_t)id << 32); 3112 } else if (usb) { 3113 /* 3114 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3115 * in the top 32 bits of the 64-bit LUN 3116 */ 3117 unsigned usb_port = atoi(usb->port->path); 3118 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3119 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3120 (uint64_t)id << 32); 3121 } 3122 } 3123 3124 /* 3125 * SLOF probes the USB devices, and if it recognizes that the device is a 3126 * storage device, it changes its name to "storage" instead of "usb-host", 3127 * and additionally adds a child node for the SCSI LUN, so the correct 3128 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3129 */ 3130 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3131 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3132 if (usb_host_dev_is_scsi_storage(usbdev)) { 3133 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3134 } 3135 } 3136 3137 if (phb) { 3138 /* Replace "pci" with "pci@800000020000000" */ 3139 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3140 } 3141 3142 if (vsc) { 3143 /* Same logic as virtio above */ 3144 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3145 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3146 } 3147 3148 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3149 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3150 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3151 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3152 } 3153 3154 return NULL; 3155 } 3156 3157 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3158 { 3159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3160 3161 return g_strdup(spapr->kvm_type); 3162 } 3163 3164 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3165 { 3166 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3167 3168 g_free(spapr->kvm_type); 3169 spapr->kvm_type = g_strdup(value); 3170 } 3171 3172 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3173 { 3174 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3175 3176 return spapr->use_hotplug_event_source; 3177 } 3178 3179 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3180 Error **errp) 3181 { 3182 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3183 3184 spapr->use_hotplug_event_source = value; 3185 } 3186 3187 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3188 { 3189 return true; 3190 } 3191 3192 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3193 { 3194 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3195 3196 switch (spapr->resize_hpt) { 3197 case SPAPR_RESIZE_HPT_DEFAULT: 3198 return g_strdup("default"); 3199 case SPAPR_RESIZE_HPT_DISABLED: 3200 return g_strdup("disabled"); 3201 case SPAPR_RESIZE_HPT_ENABLED: 3202 return g_strdup("enabled"); 3203 case SPAPR_RESIZE_HPT_REQUIRED: 3204 return g_strdup("required"); 3205 } 3206 g_assert_not_reached(); 3207 } 3208 3209 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3210 { 3211 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3212 3213 if (strcmp(value, "default") == 0) { 3214 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3215 } else if (strcmp(value, "disabled") == 0) { 3216 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3217 } else if (strcmp(value, "enabled") == 0) { 3218 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3219 } else if (strcmp(value, "required") == 0) { 3220 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3221 } else { 3222 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3223 } 3224 } 3225 3226 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3227 void *opaque, Error **errp) 3228 { 3229 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3230 } 3231 3232 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3233 void *opaque, Error **errp) 3234 { 3235 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3236 } 3237 3238 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3239 { 3240 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3241 3242 if (spapr->irq == &spapr_irq_xics_legacy) { 3243 return g_strdup("legacy"); 3244 } else if (spapr->irq == &spapr_irq_xics) { 3245 return g_strdup("xics"); 3246 } else if (spapr->irq == &spapr_irq_xive) { 3247 return g_strdup("xive"); 3248 } else if (spapr->irq == &spapr_irq_dual) { 3249 return g_strdup("dual"); 3250 } 3251 g_assert_not_reached(); 3252 } 3253 3254 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3255 { 3256 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3257 3258 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3259 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3260 return; 3261 } 3262 3263 /* The legacy IRQ backend can not be set */ 3264 if (strcmp(value, "xics") == 0) { 3265 spapr->irq = &spapr_irq_xics; 3266 } else if (strcmp(value, "xive") == 0) { 3267 spapr->irq = &spapr_irq_xive; 3268 } else if (strcmp(value, "dual") == 0) { 3269 spapr->irq = &spapr_irq_dual; 3270 } else { 3271 error_setg(errp, "Bad value for \"ic-mode\" property"); 3272 } 3273 } 3274 3275 static char *spapr_get_host_model(Object *obj, Error **errp) 3276 { 3277 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3278 3279 return g_strdup(spapr->host_model); 3280 } 3281 3282 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3283 { 3284 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3285 3286 g_free(spapr->host_model); 3287 spapr->host_model = g_strdup(value); 3288 } 3289 3290 static char *spapr_get_host_serial(Object *obj, Error **errp) 3291 { 3292 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3293 3294 return g_strdup(spapr->host_serial); 3295 } 3296 3297 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3298 { 3299 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3300 3301 g_free(spapr->host_serial); 3302 spapr->host_serial = g_strdup(value); 3303 } 3304 3305 static void spapr_instance_init(Object *obj) 3306 { 3307 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3308 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3309 3310 spapr->htab_fd = -1; 3311 spapr->use_hotplug_event_source = true; 3312 object_property_add_str(obj, "kvm-type", 3313 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3314 object_property_set_description(obj, "kvm-type", 3315 "Specifies the KVM virtualization mode (HV, PR)", 3316 NULL); 3317 object_property_add_bool(obj, "modern-hotplug-events", 3318 spapr_get_modern_hotplug_events, 3319 spapr_set_modern_hotplug_events, 3320 NULL); 3321 object_property_set_description(obj, "modern-hotplug-events", 3322 "Use dedicated hotplug event mechanism in" 3323 " place of standard EPOW events when possible" 3324 " (required for memory hot-unplug support)", 3325 NULL); 3326 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3327 "Maximum permitted CPU compatibility mode", 3328 &error_fatal); 3329 3330 object_property_add_str(obj, "resize-hpt", 3331 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3332 object_property_set_description(obj, "resize-hpt", 3333 "Resizing of the Hash Page Table (enabled, disabled, required)", 3334 NULL); 3335 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3336 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3337 object_property_set_description(obj, "vsmt", 3338 "Virtual SMT: KVM behaves as if this were" 3339 " the host's SMT mode", &error_abort); 3340 object_property_add_bool(obj, "vfio-no-msix-emulation", 3341 spapr_get_msix_emulation, NULL, NULL); 3342 3343 /* The machine class defines the default interrupt controller mode */ 3344 spapr->irq = smc->irq; 3345 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3346 spapr_set_ic_mode, NULL); 3347 object_property_set_description(obj, "ic-mode", 3348 "Specifies the interrupt controller mode (xics, xive, dual)", 3349 NULL); 3350 3351 object_property_add_str(obj, "host-model", 3352 spapr_get_host_model, spapr_set_host_model, 3353 &error_abort); 3354 object_property_set_description(obj, "host-model", 3355 "Host model to advertise in guest device tree", &error_abort); 3356 object_property_add_str(obj, "host-serial", 3357 spapr_get_host_serial, spapr_set_host_serial, 3358 &error_abort); 3359 object_property_set_description(obj, "host-serial", 3360 "Host serial number to advertise in guest device tree", &error_abort); 3361 } 3362 3363 static void spapr_machine_finalizefn(Object *obj) 3364 { 3365 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3366 3367 g_free(spapr->kvm_type); 3368 } 3369 3370 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3371 { 3372 cpu_synchronize_state(cs); 3373 ppc_cpu_do_system_reset(cs); 3374 } 3375 3376 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3377 { 3378 CPUState *cs; 3379 3380 CPU_FOREACH(cs) { 3381 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3382 } 3383 } 3384 3385 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3386 void *fdt, int *fdt_start_offset, Error **errp) 3387 { 3388 uint64_t addr; 3389 uint32_t node; 3390 3391 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3392 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3393 &error_abort); 3394 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3395 SPAPR_MEMORY_BLOCK_SIZE); 3396 return 0; 3397 } 3398 3399 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3400 bool dedicated_hp_event_source, Error **errp) 3401 { 3402 SpaprDrc *drc; 3403 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3404 int i; 3405 uint64_t addr = addr_start; 3406 bool hotplugged = spapr_drc_hotplugged(dev); 3407 Error *local_err = NULL; 3408 3409 for (i = 0; i < nr_lmbs; i++) { 3410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3411 addr / SPAPR_MEMORY_BLOCK_SIZE); 3412 g_assert(drc); 3413 3414 spapr_drc_attach(drc, dev, &local_err); 3415 if (local_err) { 3416 while (addr > addr_start) { 3417 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3419 addr / SPAPR_MEMORY_BLOCK_SIZE); 3420 spapr_drc_detach(drc); 3421 } 3422 error_propagate(errp, local_err); 3423 return; 3424 } 3425 if (!hotplugged) { 3426 spapr_drc_reset(drc); 3427 } 3428 addr += SPAPR_MEMORY_BLOCK_SIZE; 3429 } 3430 /* send hotplug notification to the 3431 * guest only in case of hotplugged memory 3432 */ 3433 if (hotplugged) { 3434 if (dedicated_hp_event_source) { 3435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3436 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3437 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3438 nr_lmbs, 3439 spapr_drc_index(drc)); 3440 } else { 3441 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3442 nr_lmbs); 3443 } 3444 } 3445 } 3446 3447 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3448 Error **errp) 3449 { 3450 Error *local_err = NULL; 3451 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3452 PCDIMMDevice *dimm = PC_DIMM(dev); 3453 uint64_t size, addr; 3454 3455 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3456 3457 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3458 if (local_err) { 3459 goto out; 3460 } 3461 3462 addr = object_property_get_uint(OBJECT(dimm), 3463 PC_DIMM_ADDR_PROP, &local_err); 3464 if (local_err) { 3465 goto out_unplug; 3466 } 3467 3468 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3469 &local_err); 3470 if (local_err) { 3471 goto out_unplug; 3472 } 3473 3474 return; 3475 3476 out_unplug: 3477 pc_dimm_unplug(dimm, MACHINE(ms)); 3478 out: 3479 error_propagate(errp, local_err); 3480 } 3481 3482 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3483 Error **errp) 3484 { 3485 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3486 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3487 PCDIMMDevice *dimm = PC_DIMM(dev); 3488 Error *local_err = NULL; 3489 uint64_t size; 3490 Object *memdev; 3491 hwaddr pagesize; 3492 3493 if (!smc->dr_lmb_enabled) { 3494 error_setg(errp, "Memory hotplug not supported for this machine"); 3495 return; 3496 } 3497 3498 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3499 if (local_err) { 3500 error_propagate(errp, local_err); 3501 return; 3502 } 3503 3504 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3505 error_setg(errp, "Hotplugged memory size must be a multiple of " 3506 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3507 return; 3508 } 3509 3510 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3511 &error_abort); 3512 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3513 spapr_check_pagesize(spapr, pagesize, &local_err); 3514 if (local_err) { 3515 error_propagate(errp, local_err); 3516 return; 3517 } 3518 3519 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3520 } 3521 3522 struct SpaprDimmState { 3523 PCDIMMDevice *dimm; 3524 uint32_t nr_lmbs; 3525 QTAILQ_ENTRY(SpaprDimmState) next; 3526 }; 3527 3528 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3529 PCDIMMDevice *dimm) 3530 { 3531 SpaprDimmState *dimm_state = NULL; 3532 3533 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3534 if (dimm_state->dimm == dimm) { 3535 break; 3536 } 3537 } 3538 return dimm_state; 3539 } 3540 3541 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3542 uint32_t nr_lmbs, 3543 PCDIMMDevice *dimm) 3544 { 3545 SpaprDimmState *ds = NULL; 3546 3547 /* 3548 * If this request is for a DIMM whose removal had failed earlier 3549 * (due to guest's refusal to remove the LMBs), we would have this 3550 * dimm already in the pending_dimm_unplugs list. In that 3551 * case don't add again. 3552 */ 3553 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3554 if (!ds) { 3555 ds = g_malloc0(sizeof(SpaprDimmState)); 3556 ds->nr_lmbs = nr_lmbs; 3557 ds->dimm = dimm; 3558 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3559 } 3560 return ds; 3561 } 3562 3563 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3564 SpaprDimmState *dimm_state) 3565 { 3566 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3567 g_free(dimm_state); 3568 } 3569 3570 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3571 PCDIMMDevice *dimm) 3572 { 3573 SpaprDrc *drc; 3574 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3575 &error_abort); 3576 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3577 uint32_t avail_lmbs = 0; 3578 uint64_t addr_start, addr; 3579 int i; 3580 3581 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3582 &error_abort); 3583 3584 addr = addr_start; 3585 for (i = 0; i < nr_lmbs; i++) { 3586 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3587 addr / SPAPR_MEMORY_BLOCK_SIZE); 3588 g_assert(drc); 3589 if (drc->dev) { 3590 avail_lmbs++; 3591 } 3592 addr += SPAPR_MEMORY_BLOCK_SIZE; 3593 } 3594 3595 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3596 } 3597 3598 /* Callback to be called during DRC release. */ 3599 void spapr_lmb_release(DeviceState *dev) 3600 { 3601 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3602 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3603 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3604 3605 /* This information will get lost if a migration occurs 3606 * during the unplug process. In this case recover it. */ 3607 if (ds == NULL) { 3608 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3609 g_assert(ds); 3610 /* The DRC being examined by the caller at least must be counted */ 3611 g_assert(ds->nr_lmbs); 3612 } 3613 3614 if (--ds->nr_lmbs) { 3615 return; 3616 } 3617 3618 /* 3619 * Now that all the LMBs have been removed by the guest, call the 3620 * unplug handler chain. This can never fail. 3621 */ 3622 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3623 object_unparent(OBJECT(dev)); 3624 } 3625 3626 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3627 { 3628 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3629 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3630 3631 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3632 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3633 spapr_pending_dimm_unplugs_remove(spapr, ds); 3634 } 3635 3636 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3637 DeviceState *dev, Error **errp) 3638 { 3639 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3640 Error *local_err = NULL; 3641 PCDIMMDevice *dimm = PC_DIMM(dev); 3642 uint32_t nr_lmbs; 3643 uint64_t size, addr_start, addr; 3644 int i; 3645 SpaprDrc *drc; 3646 3647 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3648 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3649 3650 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3651 &local_err); 3652 if (local_err) { 3653 goto out; 3654 } 3655 3656 /* 3657 * An existing pending dimm state for this DIMM means that there is an 3658 * unplug operation in progress, waiting for the spapr_lmb_release 3659 * callback to complete the job (BQL can't cover that far). In this case, 3660 * bail out to avoid detaching DRCs that were already released. 3661 */ 3662 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3663 error_setg(&local_err, 3664 "Memory unplug already in progress for device %s", 3665 dev->id); 3666 goto out; 3667 } 3668 3669 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3670 3671 addr = addr_start; 3672 for (i = 0; i < nr_lmbs; i++) { 3673 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3674 addr / SPAPR_MEMORY_BLOCK_SIZE); 3675 g_assert(drc); 3676 3677 spapr_drc_detach(drc); 3678 addr += SPAPR_MEMORY_BLOCK_SIZE; 3679 } 3680 3681 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3682 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3683 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3684 nr_lmbs, spapr_drc_index(drc)); 3685 out: 3686 error_propagate(errp, local_err); 3687 } 3688 3689 /* Callback to be called during DRC release. */ 3690 void spapr_core_release(DeviceState *dev) 3691 { 3692 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3693 3694 /* Call the unplug handler chain. This can never fail. */ 3695 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3696 object_unparent(OBJECT(dev)); 3697 } 3698 3699 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3700 { 3701 MachineState *ms = MACHINE(hotplug_dev); 3702 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3703 CPUCore *cc = CPU_CORE(dev); 3704 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3705 3706 if (smc->pre_2_10_has_unused_icps) { 3707 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3708 int i; 3709 3710 for (i = 0; i < cc->nr_threads; i++) { 3711 CPUState *cs = CPU(sc->threads[i]); 3712 3713 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3714 } 3715 } 3716 3717 assert(core_slot); 3718 core_slot->cpu = NULL; 3719 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3720 } 3721 3722 static 3723 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3724 Error **errp) 3725 { 3726 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3727 int index; 3728 SpaprDrc *drc; 3729 CPUCore *cc = CPU_CORE(dev); 3730 3731 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3732 error_setg(errp, "Unable to find CPU core with core-id: %d", 3733 cc->core_id); 3734 return; 3735 } 3736 if (index == 0) { 3737 error_setg(errp, "Boot CPU core may not be unplugged"); 3738 return; 3739 } 3740 3741 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3742 spapr_vcpu_id(spapr, cc->core_id)); 3743 g_assert(drc); 3744 3745 spapr_drc_detach(drc); 3746 3747 spapr_hotplug_req_remove_by_index(drc); 3748 } 3749 3750 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3751 void *fdt, int *fdt_start_offset, Error **errp) 3752 { 3753 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3754 CPUState *cs = CPU(core->threads[0]); 3755 PowerPCCPU *cpu = POWERPC_CPU(cs); 3756 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3757 int id = spapr_get_vcpu_id(cpu); 3758 char *nodename; 3759 int offset; 3760 3761 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3762 offset = fdt_add_subnode(fdt, 0, nodename); 3763 g_free(nodename); 3764 3765 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3766 3767 *fdt_start_offset = offset; 3768 return 0; 3769 } 3770 3771 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3772 Error **errp) 3773 { 3774 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3775 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3776 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3777 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3778 CPUCore *cc = CPU_CORE(dev); 3779 CPUState *cs; 3780 SpaprDrc *drc; 3781 Error *local_err = NULL; 3782 CPUArchId *core_slot; 3783 int index; 3784 bool hotplugged = spapr_drc_hotplugged(dev); 3785 int i; 3786 3787 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3788 if (!core_slot) { 3789 error_setg(errp, "Unable to find CPU core with core-id: %d", 3790 cc->core_id); 3791 return; 3792 } 3793 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3794 spapr_vcpu_id(spapr, cc->core_id)); 3795 3796 g_assert(drc || !mc->has_hotpluggable_cpus); 3797 3798 if (drc) { 3799 spapr_drc_attach(drc, dev, &local_err); 3800 if (local_err) { 3801 error_propagate(errp, local_err); 3802 return; 3803 } 3804 3805 if (hotplugged) { 3806 /* 3807 * Send hotplug notification interrupt to the guest only 3808 * in case of hotplugged CPUs. 3809 */ 3810 spapr_hotplug_req_add_by_index(drc); 3811 } else { 3812 spapr_drc_reset(drc); 3813 } 3814 } 3815 3816 core_slot->cpu = OBJECT(dev); 3817 3818 if (smc->pre_2_10_has_unused_icps) { 3819 for (i = 0; i < cc->nr_threads; i++) { 3820 cs = CPU(core->threads[i]); 3821 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3822 } 3823 } 3824 3825 /* 3826 * Set compatibility mode to match the boot CPU, which was either set 3827 * by the machine reset code or by CAS. 3828 */ 3829 if (hotplugged) { 3830 for (i = 0; i < cc->nr_threads; i++) { 3831 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3832 &local_err); 3833 if (local_err) { 3834 error_propagate(errp, local_err); 3835 return; 3836 } 3837 } 3838 } 3839 } 3840 3841 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3842 Error **errp) 3843 { 3844 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3845 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3846 Error *local_err = NULL; 3847 CPUCore *cc = CPU_CORE(dev); 3848 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3849 const char *type = object_get_typename(OBJECT(dev)); 3850 CPUArchId *core_slot; 3851 int index; 3852 unsigned int smp_threads = machine->smp.threads; 3853 3854 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3855 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3856 goto out; 3857 } 3858 3859 if (strcmp(base_core_type, type)) { 3860 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3861 goto out; 3862 } 3863 3864 if (cc->core_id % smp_threads) { 3865 error_setg(&local_err, "invalid core id %d", cc->core_id); 3866 goto out; 3867 } 3868 3869 /* 3870 * In general we should have homogeneous threads-per-core, but old 3871 * (pre hotplug support) machine types allow the last core to have 3872 * reduced threads as a compatibility hack for when we allowed 3873 * total vcpus not a multiple of threads-per-core. 3874 */ 3875 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3876 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3877 cc->nr_threads, smp_threads); 3878 goto out; 3879 } 3880 3881 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3882 if (!core_slot) { 3883 error_setg(&local_err, "core id %d out of range", cc->core_id); 3884 goto out; 3885 } 3886 3887 if (core_slot->cpu) { 3888 error_setg(&local_err, "core %d already populated", cc->core_id); 3889 goto out; 3890 } 3891 3892 numa_cpu_pre_plug(core_slot, dev, &local_err); 3893 3894 out: 3895 error_propagate(errp, local_err); 3896 } 3897 3898 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3899 void *fdt, int *fdt_start_offset, Error **errp) 3900 { 3901 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3902 int intc_phandle; 3903 3904 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3905 if (intc_phandle <= 0) { 3906 return -1; 3907 } 3908 3909 if (spapr_dt_phb(sphb, intc_phandle, fdt, spapr->irq->nr_msis, 3910 fdt_start_offset)) { 3911 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3912 return -1; 3913 } 3914 3915 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3916 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3917 3918 return 0; 3919 } 3920 3921 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3922 Error **errp) 3923 { 3924 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3925 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3926 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3927 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3928 3929 if (dev->hotplugged && !smc->dr_phb_enabled) { 3930 error_setg(errp, "PHB hotplug not supported for this machine"); 3931 return; 3932 } 3933 3934 if (sphb->index == (uint32_t)-1) { 3935 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3936 return; 3937 } 3938 3939 /* 3940 * This will check that sphb->index doesn't exceed the maximum number of 3941 * PHBs for the current machine type. 3942 */ 3943 smc->phb_placement(spapr, sphb->index, 3944 &sphb->buid, &sphb->io_win_addr, 3945 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3946 windows_supported, sphb->dma_liobn, 3947 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3948 errp); 3949 } 3950 3951 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3952 Error **errp) 3953 { 3954 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3955 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3956 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3957 SpaprDrc *drc; 3958 bool hotplugged = spapr_drc_hotplugged(dev); 3959 Error *local_err = NULL; 3960 3961 if (!smc->dr_phb_enabled) { 3962 return; 3963 } 3964 3965 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3966 /* hotplug hooks should check it's enabled before getting this far */ 3967 assert(drc); 3968 3969 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3970 if (local_err) { 3971 error_propagate(errp, local_err); 3972 return; 3973 } 3974 3975 if (hotplugged) { 3976 spapr_hotplug_req_add_by_index(drc); 3977 } else { 3978 spapr_drc_reset(drc); 3979 } 3980 } 3981 3982 void spapr_phb_release(DeviceState *dev) 3983 { 3984 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3985 3986 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3987 object_unparent(OBJECT(dev)); 3988 } 3989 3990 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3991 { 3992 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3993 } 3994 3995 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3996 DeviceState *dev, Error **errp) 3997 { 3998 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3999 SpaprDrc *drc; 4000 4001 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4002 assert(drc); 4003 4004 if (!spapr_drc_unplug_requested(drc)) { 4005 spapr_drc_detach(drc); 4006 spapr_hotplug_req_remove_by_index(drc); 4007 } 4008 } 4009 4010 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4011 Error **errp) 4012 { 4013 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4014 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4015 4016 if (spapr->tpm_proxy != NULL) { 4017 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4018 return; 4019 } 4020 4021 spapr->tpm_proxy = tpm_proxy; 4022 } 4023 4024 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4025 { 4026 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4027 4028 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4029 object_unparent(OBJECT(dev)); 4030 spapr->tpm_proxy = NULL; 4031 } 4032 4033 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4034 DeviceState *dev, Error **errp) 4035 { 4036 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4037 spapr_memory_plug(hotplug_dev, dev, errp); 4038 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4039 spapr_core_plug(hotplug_dev, dev, errp); 4040 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4041 spapr_phb_plug(hotplug_dev, dev, errp); 4042 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4043 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4044 } 4045 } 4046 4047 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4048 DeviceState *dev, Error **errp) 4049 { 4050 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4051 spapr_memory_unplug(hotplug_dev, dev); 4052 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4053 spapr_core_unplug(hotplug_dev, dev); 4054 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4055 spapr_phb_unplug(hotplug_dev, dev); 4056 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4057 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4058 } 4059 } 4060 4061 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4062 DeviceState *dev, Error **errp) 4063 { 4064 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4065 MachineClass *mc = MACHINE_GET_CLASS(sms); 4066 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4067 4068 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4069 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4070 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4071 } else { 4072 /* NOTE: this means there is a window after guest reset, prior to 4073 * CAS negotiation, where unplug requests will fail due to the 4074 * capability not being detected yet. This is a bit different than 4075 * the case with PCI unplug, where the events will be queued and 4076 * eventually handled by the guest after boot 4077 */ 4078 error_setg(errp, "Memory hot unplug not supported for this guest"); 4079 } 4080 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4081 if (!mc->has_hotpluggable_cpus) { 4082 error_setg(errp, "CPU hot unplug not supported on this machine"); 4083 return; 4084 } 4085 spapr_core_unplug_request(hotplug_dev, dev, errp); 4086 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4087 if (!smc->dr_phb_enabled) { 4088 error_setg(errp, "PHB hot unplug not supported on this machine"); 4089 return; 4090 } 4091 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4092 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4093 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4094 } 4095 } 4096 4097 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4098 DeviceState *dev, Error **errp) 4099 { 4100 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4101 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4102 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4103 spapr_core_pre_plug(hotplug_dev, dev, errp); 4104 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4105 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4106 } 4107 } 4108 4109 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4110 DeviceState *dev) 4111 { 4112 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4113 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4114 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4115 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4116 return HOTPLUG_HANDLER(machine); 4117 } 4118 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4119 PCIDevice *pcidev = PCI_DEVICE(dev); 4120 PCIBus *root = pci_device_root_bus(pcidev); 4121 SpaprPhbState *phb = 4122 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4123 TYPE_SPAPR_PCI_HOST_BRIDGE); 4124 4125 if (phb) { 4126 return HOTPLUG_HANDLER(phb); 4127 } 4128 } 4129 return NULL; 4130 } 4131 4132 static CpuInstanceProperties 4133 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4134 { 4135 CPUArchId *core_slot; 4136 MachineClass *mc = MACHINE_GET_CLASS(machine); 4137 4138 /* make sure possible_cpu are intialized */ 4139 mc->possible_cpu_arch_ids(machine); 4140 /* get CPU core slot containing thread that matches cpu_index */ 4141 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4142 assert(core_slot); 4143 return core_slot->props; 4144 } 4145 4146 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4147 { 4148 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4149 } 4150 4151 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4152 { 4153 int i; 4154 unsigned int smp_threads = machine->smp.threads; 4155 unsigned int smp_cpus = machine->smp.cpus; 4156 const char *core_type; 4157 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4158 MachineClass *mc = MACHINE_GET_CLASS(machine); 4159 4160 if (!mc->has_hotpluggable_cpus) { 4161 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4162 } 4163 if (machine->possible_cpus) { 4164 assert(machine->possible_cpus->len == spapr_max_cores); 4165 return machine->possible_cpus; 4166 } 4167 4168 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4169 if (!core_type) { 4170 error_report("Unable to find sPAPR CPU Core definition"); 4171 exit(1); 4172 } 4173 4174 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4175 sizeof(CPUArchId) * spapr_max_cores); 4176 machine->possible_cpus->len = spapr_max_cores; 4177 for (i = 0; i < machine->possible_cpus->len; i++) { 4178 int core_id = i * smp_threads; 4179 4180 machine->possible_cpus->cpus[i].type = core_type; 4181 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4182 machine->possible_cpus->cpus[i].arch_id = core_id; 4183 machine->possible_cpus->cpus[i].props.has_core_id = true; 4184 machine->possible_cpus->cpus[i].props.core_id = core_id; 4185 } 4186 return machine->possible_cpus; 4187 } 4188 4189 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4190 uint64_t *buid, hwaddr *pio, 4191 hwaddr *mmio32, hwaddr *mmio64, 4192 unsigned n_dma, uint32_t *liobns, 4193 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4194 { 4195 /* 4196 * New-style PHB window placement. 4197 * 4198 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4199 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4200 * windows. 4201 * 4202 * Some guest kernels can't work with MMIO windows above 1<<46 4203 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4204 * 4205 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4206 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4207 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4208 * 1TiB 64-bit MMIO windows for each PHB. 4209 */ 4210 const uint64_t base_buid = 0x800000020000000ULL; 4211 int i; 4212 4213 /* Sanity check natural alignments */ 4214 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4215 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4216 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4217 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4218 /* Sanity check bounds */ 4219 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4220 SPAPR_PCI_MEM32_WIN_SIZE); 4221 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4222 SPAPR_PCI_MEM64_WIN_SIZE); 4223 4224 if (index >= SPAPR_MAX_PHBS) { 4225 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4226 SPAPR_MAX_PHBS - 1); 4227 return; 4228 } 4229 4230 *buid = base_buid + index; 4231 for (i = 0; i < n_dma; ++i) { 4232 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4233 } 4234 4235 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4236 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4237 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4238 4239 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4240 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4241 } 4242 4243 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4244 { 4245 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4246 4247 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4248 } 4249 4250 static void spapr_ics_resend(XICSFabric *dev) 4251 { 4252 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4253 4254 ics_resend(spapr->ics); 4255 } 4256 4257 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4258 { 4259 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4260 4261 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4262 } 4263 4264 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4265 Monitor *mon) 4266 { 4267 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4268 4269 spapr_irq_print_info(spapr, mon); 4270 monitor_printf(mon, "irqchip: %s\n", 4271 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4272 } 4273 4274 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4275 { 4276 return cpu->vcpu_id; 4277 } 4278 4279 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4280 { 4281 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4282 MachineState *ms = MACHINE(spapr); 4283 int vcpu_id; 4284 4285 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4286 4287 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4288 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4289 error_append_hint(errp, "Adjust the number of cpus to %d " 4290 "or try to raise the number of threads per core\n", 4291 vcpu_id * ms->smp.threads / spapr->vsmt); 4292 return; 4293 } 4294 4295 cpu->vcpu_id = vcpu_id; 4296 } 4297 4298 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4299 { 4300 CPUState *cs; 4301 4302 CPU_FOREACH(cs) { 4303 PowerPCCPU *cpu = POWERPC_CPU(cs); 4304 4305 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4306 return cpu; 4307 } 4308 } 4309 4310 return NULL; 4311 } 4312 4313 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4314 { 4315 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4316 4317 /* These are only called by TCG, KVM maintains dispatch state */ 4318 4319 spapr_cpu->prod = false; 4320 if (spapr_cpu->vpa_addr) { 4321 CPUState *cs = CPU(cpu); 4322 uint32_t dispatch; 4323 4324 dispatch = ldl_be_phys(cs->as, 4325 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4326 dispatch++; 4327 if ((dispatch & 1) != 0) { 4328 qemu_log_mask(LOG_GUEST_ERROR, 4329 "VPA: incorrect dispatch counter value for " 4330 "dispatched partition %u, correcting.\n", dispatch); 4331 dispatch++; 4332 } 4333 stl_be_phys(cs->as, 4334 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4335 } 4336 } 4337 4338 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4339 { 4340 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4341 4342 if (spapr_cpu->vpa_addr) { 4343 CPUState *cs = CPU(cpu); 4344 uint32_t dispatch; 4345 4346 dispatch = ldl_be_phys(cs->as, 4347 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4348 dispatch++; 4349 if ((dispatch & 1) != 1) { 4350 qemu_log_mask(LOG_GUEST_ERROR, 4351 "VPA: incorrect dispatch counter value for " 4352 "preempted partition %u, correcting.\n", dispatch); 4353 dispatch++; 4354 } 4355 stl_be_phys(cs->as, 4356 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4357 } 4358 } 4359 4360 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4361 { 4362 MachineClass *mc = MACHINE_CLASS(oc); 4363 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4364 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4365 NMIClass *nc = NMI_CLASS(oc); 4366 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4367 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4368 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4369 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4370 4371 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4372 mc->ignore_boot_device_suffixes = true; 4373 4374 /* 4375 * We set up the default / latest behaviour here. The class_init 4376 * functions for the specific versioned machine types can override 4377 * these details for backwards compatibility 4378 */ 4379 mc->init = spapr_machine_init; 4380 mc->reset = spapr_machine_reset; 4381 mc->block_default_type = IF_SCSI; 4382 mc->max_cpus = 1024; 4383 mc->no_parallel = 1; 4384 mc->default_boot_order = ""; 4385 mc->default_ram_size = 512 * MiB; 4386 mc->default_display = "std"; 4387 mc->kvm_type = spapr_kvm_type; 4388 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4389 mc->pci_allow_0_address = true; 4390 assert(!mc->get_hotplug_handler); 4391 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4392 hc->pre_plug = spapr_machine_device_pre_plug; 4393 hc->plug = spapr_machine_device_plug; 4394 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4395 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4396 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4397 hc->unplug_request = spapr_machine_device_unplug_request; 4398 hc->unplug = spapr_machine_device_unplug; 4399 4400 smc->dr_lmb_enabled = true; 4401 smc->update_dt_enabled = true; 4402 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4403 mc->has_hotpluggable_cpus = true; 4404 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4405 fwc->get_dev_path = spapr_get_fw_dev_path; 4406 nc->nmi_monitor_handler = spapr_nmi; 4407 smc->phb_placement = spapr_phb_placement; 4408 vhc->hypercall = emulate_spapr_hypercall; 4409 vhc->hpt_mask = spapr_hpt_mask; 4410 vhc->map_hptes = spapr_map_hptes; 4411 vhc->unmap_hptes = spapr_unmap_hptes; 4412 vhc->hpte_set_c = spapr_hpte_set_c; 4413 vhc->hpte_set_r = spapr_hpte_set_r; 4414 vhc->get_pate = spapr_get_pate; 4415 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4416 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4417 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4418 xic->ics_get = spapr_ics_get; 4419 xic->ics_resend = spapr_ics_resend; 4420 xic->icp_get = spapr_icp_get; 4421 ispc->print_info = spapr_pic_print_info; 4422 /* Force NUMA node memory size to be a multiple of 4423 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4424 * in which LMBs are represented and hot-added 4425 */ 4426 mc->numa_mem_align_shift = 28; 4427 mc->numa_mem_supported = true; 4428 mc->auto_enable_numa = true; 4429 4430 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4431 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4432 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4433 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4434 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4435 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4436 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4437 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4438 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4439 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4440 spapr_caps_add_properties(smc, &error_abort); 4441 smc->irq = &spapr_irq_dual; 4442 smc->dr_phb_enabled = true; 4443 smc->linux_pci_probe = true; 4444 smc->smp_threads_vsmt = true; 4445 } 4446 4447 static const TypeInfo spapr_machine_info = { 4448 .name = TYPE_SPAPR_MACHINE, 4449 .parent = TYPE_MACHINE, 4450 .abstract = true, 4451 .instance_size = sizeof(SpaprMachineState), 4452 .instance_init = spapr_instance_init, 4453 .instance_finalize = spapr_machine_finalizefn, 4454 .class_size = sizeof(SpaprMachineClass), 4455 .class_init = spapr_machine_class_init, 4456 .interfaces = (InterfaceInfo[]) { 4457 { TYPE_FW_PATH_PROVIDER }, 4458 { TYPE_NMI }, 4459 { TYPE_HOTPLUG_HANDLER }, 4460 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4461 { TYPE_XICS_FABRIC }, 4462 { TYPE_INTERRUPT_STATS_PROVIDER }, 4463 { } 4464 }, 4465 }; 4466 4467 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4468 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4469 void *data) \ 4470 { \ 4471 MachineClass *mc = MACHINE_CLASS(oc); \ 4472 spapr_machine_##suffix##_class_options(mc); \ 4473 if (latest) { \ 4474 mc->alias = "pseries"; \ 4475 mc->is_default = 1; \ 4476 } \ 4477 } \ 4478 static const TypeInfo spapr_machine_##suffix##_info = { \ 4479 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4480 .parent = TYPE_SPAPR_MACHINE, \ 4481 .class_init = spapr_machine_##suffix##_class_init, \ 4482 }; \ 4483 static void spapr_machine_register_##suffix(void) \ 4484 { \ 4485 type_register(&spapr_machine_##suffix##_info); \ 4486 } \ 4487 type_init(spapr_machine_register_##suffix) 4488 4489 /* 4490 * pseries-4.2 4491 */ 4492 static void spapr_machine_4_2_class_options(MachineClass *mc) 4493 { 4494 /* Defaults for the latest behaviour inherited from the base class */ 4495 } 4496 4497 DEFINE_SPAPR_MACHINE(4_2, "4.2", true); 4498 4499 /* 4500 * pseries-4.1 4501 */ 4502 static void spapr_machine_4_1_class_options(MachineClass *mc) 4503 { 4504 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4505 static GlobalProperty compat[] = { 4506 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4507 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4508 }; 4509 4510 spapr_machine_4_2_class_options(mc); 4511 smc->linux_pci_probe = false; 4512 smc->smp_threads_vsmt = false; 4513 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4514 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4515 } 4516 4517 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4518 4519 /* 4520 * pseries-4.0 4521 */ 4522 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4523 uint64_t *buid, hwaddr *pio, 4524 hwaddr *mmio32, hwaddr *mmio64, 4525 unsigned n_dma, uint32_t *liobns, 4526 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4527 { 4528 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4529 nv2gpa, nv2atsd, errp); 4530 *nv2gpa = 0; 4531 *nv2atsd = 0; 4532 } 4533 4534 static void spapr_machine_4_0_class_options(MachineClass *mc) 4535 { 4536 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4537 4538 spapr_machine_4_1_class_options(mc); 4539 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4540 smc->phb_placement = phb_placement_4_0; 4541 smc->irq = &spapr_irq_xics; 4542 smc->pre_4_1_migration = true; 4543 } 4544 4545 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4546 4547 /* 4548 * pseries-3.1 4549 */ 4550 static void spapr_machine_3_1_class_options(MachineClass *mc) 4551 { 4552 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4553 4554 spapr_machine_4_0_class_options(mc); 4555 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4556 4557 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4558 smc->update_dt_enabled = false; 4559 smc->dr_phb_enabled = false; 4560 smc->broken_host_serial_model = true; 4561 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4562 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4563 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4564 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4565 } 4566 4567 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4568 4569 /* 4570 * pseries-3.0 4571 */ 4572 4573 static void spapr_machine_3_0_class_options(MachineClass *mc) 4574 { 4575 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4576 4577 spapr_machine_3_1_class_options(mc); 4578 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4579 4580 smc->legacy_irq_allocation = true; 4581 smc->irq = &spapr_irq_xics_legacy; 4582 } 4583 4584 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4585 4586 /* 4587 * pseries-2.12 4588 */ 4589 static void spapr_machine_2_12_class_options(MachineClass *mc) 4590 { 4591 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4592 static GlobalProperty compat[] = { 4593 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4594 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4595 }; 4596 4597 spapr_machine_3_0_class_options(mc); 4598 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4599 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4600 4601 /* We depend on kvm_enabled() to choose a default value for the 4602 * hpt-max-page-size capability. Of course we can't do it here 4603 * because this is too early and the HW accelerator isn't initialzed 4604 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4605 */ 4606 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4607 } 4608 4609 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4610 4611 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4612 { 4613 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4614 4615 spapr_machine_2_12_class_options(mc); 4616 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4617 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4618 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4619 } 4620 4621 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4622 4623 /* 4624 * pseries-2.11 4625 */ 4626 4627 static void spapr_machine_2_11_class_options(MachineClass *mc) 4628 { 4629 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4630 4631 spapr_machine_2_12_class_options(mc); 4632 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4633 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4634 } 4635 4636 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4637 4638 /* 4639 * pseries-2.10 4640 */ 4641 4642 static void spapr_machine_2_10_class_options(MachineClass *mc) 4643 { 4644 spapr_machine_2_11_class_options(mc); 4645 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4646 } 4647 4648 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4649 4650 /* 4651 * pseries-2.9 4652 */ 4653 4654 static void spapr_machine_2_9_class_options(MachineClass *mc) 4655 { 4656 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4657 static GlobalProperty compat[] = { 4658 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4659 }; 4660 4661 spapr_machine_2_10_class_options(mc); 4662 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4663 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4664 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4665 smc->pre_2_10_has_unused_icps = true; 4666 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4667 } 4668 4669 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4670 4671 /* 4672 * pseries-2.8 4673 */ 4674 4675 static void spapr_machine_2_8_class_options(MachineClass *mc) 4676 { 4677 static GlobalProperty compat[] = { 4678 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4679 }; 4680 4681 spapr_machine_2_9_class_options(mc); 4682 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4683 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4684 mc->numa_mem_align_shift = 23; 4685 } 4686 4687 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4688 4689 /* 4690 * pseries-2.7 4691 */ 4692 4693 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4694 uint64_t *buid, hwaddr *pio, 4695 hwaddr *mmio32, hwaddr *mmio64, 4696 unsigned n_dma, uint32_t *liobns, 4697 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4698 { 4699 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4700 const uint64_t base_buid = 0x800000020000000ULL; 4701 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4702 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4703 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4704 const uint32_t max_index = 255; 4705 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4706 4707 uint64_t ram_top = MACHINE(spapr)->ram_size; 4708 hwaddr phb0_base, phb_base; 4709 int i; 4710 4711 /* Do we have device memory? */ 4712 if (MACHINE(spapr)->maxram_size > ram_top) { 4713 /* Can't just use maxram_size, because there may be an 4714 * alignment gap between normal and device memory regions 4715 */ 4716 ram_top = MACHINE(spapr)->device_memory->base + 4717 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4718 } 4719 4720 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4721 4722 if (index > max_index) { 4723 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4724 max_index); 4725 return; 4726 } 4727 4728 *buid = base_buid + index; 4729 for (i = 0; i < n_dma; ++i) { 4730 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4731 } 4732 4733 phb_base = phb0_base + index * phb_spacing; 4734 *pio = phb_base + pio_offset; 4735 *mmio32 = phb_base + mmio_offset; 4736 /* 4737 * We don't set the 64-bit MMIO window, relying on the PHB's 4738 * fallback behaviour of automatically splitting a large "32-bit" 4739 * window into contiguous 32-bit and 64-bit windows 4740 */ 4741 4742 *nv2gpa = 0; 4743 *nv2atsd = 0; 4744 } 4745 4746 static void spapr_machine_2_7_class_options(MachineClass *mc) 4747 { 4748 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4749 static GlobalProperty compat[] = { 4750 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4751 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4752 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4753 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4754 }; 4755 4756 spapr_machine_2_8_class_options(mc); 4757 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4758 mc->default_machine_opts = "modern-hotplug-events=off"; 4759 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4760 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4761 smc->phb_placement = phb_placement_2_7; 4762 } 4763 4764 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4765 4766 /* 4767 * pseries-2.6 4768 */ 4769 4770 static void spapr_machine_2_6_class_options(MachineClass *mc) 4771 { 4772 static GlobalProperty compat[] = { 4773 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4774 }; 4775 4776 spapr_machine_2_7_class_options(mc); 4777 mc->has_hotpluggable_cpus = false; 4778 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4779 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4780 } 4781 4782 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4783 4784 /* 4785 * pseries-2.5 4786 */ 4787 4788 static void spapr_machine_2_5_class_options(MachineClass *mc) 4789 { 4790 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4791 static GlobalProperty compat[] = { 4792 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4793 }; 4794 4795 spapr_machine_2_6_class_options(mc); 4796 smc->use_ohci_by_default = true; 4797 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4798 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4799 } 4800 4801 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4802 4803 /* 4804 * pseries-2.4 4805 */ 4806 4807 static void spapr_machine_2_4_class_options(MachineClass *mc) 4808 { 4809 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4810 4811 spapr_machine_2_5_class_options(mc); 4812 smc->dr_lmb_enabled = false; 4813 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4814 } 4815 4816 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4817 4818 /* 4819 * pseries-2.3 4820 */ 4821 4822 static void spapr_machine_2_3_class_options(MachineClass *mc) 4823 { 4824 static GlobalProperty compat[] = { 4825 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4826 }; 4827 spapr_machine_2_4_class_options(mc); 4828 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4829 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4830 } 4831 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4832 4833 /* 4834 * pseries-2.2 4835 */ 4836 4837 static void spapr_machine_2_2_class_options(MachineClass *mc) 4838 { 4839 static GlobalProperty compat[] = { 4840 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4841 }; 4842 4843 spapr_machine_2_3_class_options(mc); 4844 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4845 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4846 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4847 } 4848 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4849 4850 /* 4851 * pseries-2.1 4852 */ 4853 4854 static void spapr_machine_2_1_class_options(MachineClass *mc) 4855 { 4856 spapr_machine_2_2_class_options(mc); 4857 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4858 } 4859 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4860 4861 static void spapr_machine_register_types(void) 4862 { 4863 type_register_static(&spapr_machine_info); 4864 } 4865 4866 type_init(spapr_machine_register_types) 4867