1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "hw/mem/memory-device.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_INTC 0x00001111 100 101 /* These two functions implement the VCPU id numbering: one to compute them 102 * all and one to identify thread 0 of a VCORE. Any change to the first one 103 * is likely to have an impact on the second one, so let's keep them close. 104 */ 105 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 106 { 107 assert(spapr->vsmt); 108 return 109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 110 } 111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 112 PowerPCCPU *cpu) 113 { 114 assert(spapr->vsmt); 115 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 116 } 117 118 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 119 { 120 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 121 * and newer QEMUs don't even have them. In both cases, we don't want 122 * to send anything on the wire. 123 */ 124 return false; 125 } 126 127 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 128 .name = "icp/server", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .needed = pre_2_10_vmstate_dummy_icp_needed, 132 .fields = (VMStateField[]) { 133 VMSTATE_UNUSED(4), /* uint32_t xirr */ 134 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 135 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 136 VMSTATE_END_OF_LIST() 137 }, 138 }; 139 140 static void pre_2_10_vmstate_register_dummy_icp(int i) 141 { 142 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 143 (void *)(uintptr_t) i); 144 } 145 146 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 147 { 148 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 149 (void *)(uintptr_t) i); 150 } 151 152 int spapr_max_server_number(sPAPRMachineState *spapr) 153 { 154 assert(spapr->vsmt); 155 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 156 } 157 158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 159 int smt_threads) 160 { 161 int i, ret = 0; 162 uint32_t servers_prop[smt_threads]; 163 uint32_t gservers_prop[smt_threads * 2]; 164 int index = spapr_get_vcpu_id(cpu); 165 166 if (cpu->compat_pvr) { 167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 168 if (ret < 0) { 169 return ret; 170 } 171 } 172 173 /* Build interrupt servers and gservers properties */ 174 for (i = 0; i < smt_threads; i++) { 175 servers_prop[i] = cpu_to_be32(index + i); 176 /* Hack, direct the group queues back to cpu 0 */ 177 gservers_prop[i*2] = cpu_to_be32(index + i); 178 gservers_prop[i*2 + 1] = 0; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 181 servers_prop, sizeof(servers_prop)); 182 if (ret < 0) { 183 return ret; 184 } 185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 186 gservers_prop, sizeof(gservers_prop)); 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 192 { 193 int index = spapr_get_vcpu_id(cpu); 194 uint32_t associativity[] = {cpu_to_be32(0x5), 195 cpu_to_be32(0x0), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(cpu->node_id), 199 cpu_to_be32(index)}; 200 201 /* Advertise NUMA via ibm,associativity */ 202 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 203 sizeof(associativity)); 204 } 205 206 /* Populate the "ibm,pa-features" property */ 207 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset, 210 bool legacy_guest) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (legacy_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 287 { 288 int ret = 0, offset, cpus_offset; 289 CPUState *cs; 290 char cpu_model[32]; 291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 292 293 CPU_FOREACH(cs) { 294 PowerPCCPU *cpu = POWERPC_CPU(cs); 295 DeviceClass *dc = DEVICE_GET_CLASS(cs); 296 int index = spapr_get_vcpu_id(cpu); 297 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 298 299 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 300 continue; 301 } 302 303 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 304 305 cpus_offset = fdt_path_offset(fdt, "/cpus"); 306 if (cpus_offset < 0) { 307 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 308 if (cpus_offset < 0) { 309 return cpus_offset; 310 } 311 } 312 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 313 if (offset < 0) { 314 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 315 if (offset < 0) { 316 return offset; 317 } 318 } 319 320 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 321 pft_size_prop, sizeof(pft_size_prop)); 322 if (ret < 0) { 323 return ret; 324 } 325 326 if (nb_numa_nodes > 1) { 327 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 328 if (ret < 0) { 329 return ret; 330 } 331 } 332 333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 334 if (ret < 0) { 335 return ret; 336 } 337 338 spapr_populate_pa_features(spapr, cpu, fdt, offset, 339 spapr->cas_legacy_guest_workaround); 340 } 341 return ret; 342 } 343 344 static hwaddr spapr_node0_size(MachineState *machine) 345 { 346 if (nb_numa_nodes) { 347 int i; 348 for (i = 0; i < nb_numa_nodes; ++i) { 349 if (numa_info[i].node_mem) { 350 return MIN(pow2floor(numa_info[i].node_mem), 351 machine->ram_size); 352 } 353 } 354 } 355 return machine->ram_size; 356 } 357 358 static void add_str(GString *s, const gchar *s1) 359 { 360 g_string_append_len(s, s1, strlen(s1) + 1); 361 } 362 363 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 364 hwaddr size) 365 { 366 uint32_t associativity[] = { 367 cpu_to_be32(0x4), /* length */ 368 cpu_to_be32(0x0), cpu_to_be32(0x0), 369 cpu_to_be32(0x0), cpu_to_be32(nodeid) 370 }; 371 char mem_name[32]; 372 uint64_t mem_reg_property[2]; 373 int off; 374 375 mem_reg_property[0] = cpu_to_be64(start); 376 mem_reg_property[1] = cpu_to_be64(size); 377 378 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 379 off = fdt_add_subnode(fdt, 0, mem_name); 380 _FDT(off); 381 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 382 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 383 sizeof(mem_reg_property)))); 384 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 385 sizeof(associativity)))); 386 return off; 387 } 388 389 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 390 { 391 MachineState *machine = MACHINE(spapr); 392 hwaddr mem_start, node_size; 393 int i, nb_nodes = nb_numa_nodes; 394 NodeInfo *nodes = numa_info; 395 NodeInfo ramnode; 396 397 /* No NUMA nodes, assume there is just one node with whole RAM */ 398 if (!nb_numa_nodes) { 399 nb_nodes = 1; 400 ramnode.node_mem = machine->ram_size; 401 nodes = &ramnode; 402 } 403 404 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 405 if (!nodes[i].node_mem) { 406 continue; 407 } 408 if (mem_start >= machine->ram_size) { 409 node_size = 0; 410 } else { 411 node_size = nodes[i].node_mem; 412 if (node_size > machine->ram_size - mem_start) { 413 node_size = machine->ram_size - mem_start; 414 } 415 } 416 if (!mem_start) { 417 /* spapr_machine_init() checks for rma_size <= node0_size 418 * already */ 419 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 420 mem_start += spapr->rma_size; 421 node_size -= spapr->rma_size; 422 } 423 for ( ; node_size; ) { 424 hwaddr sizetmp = pow2floor(node_size); 425 426 /* mem_start != 0 here */ 427 if (ctzl(mem_start) < ctzl(sizetmp)) { 428 sizetmp = 1ULL << ctzl(mem_start); 429 } 430 431 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 432 node_size -= sizetmp; 433 mem_start += sizetmp; 434 } 435 } 436 437 return 0; 438 } 439 440 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 441 sPAPRMachineState *spapr) 442 { 443 PowerPCCPU *cpu = POWERPC_CPU(cs); 444 CPUPPCState *env = &cpu->env; 445 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 446 int index = spapr_get_vcpu_id(cpu); 447 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 448 0xffffffff, 0xffffffff}; 449 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 450 : SPAPR_TIMEBASE_FREQ; 451 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 452 uint32_t page_sizes_prop[64]; 453 size_t page_sizes_prop_size; 454 uint32_t vcpus_per_socket = smp_threads * smp_cores; 455 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 456 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 457 sPAPRDRConnector *drc; 458 int drc_index; 459 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 460 int i; 461 462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 463 if (drc) { 464 drc_index = spapr_drc_index(drc); 465 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 466 } 467 468 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 469 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 470 471 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 472 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 473 env->dcache_line_size))); 474 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 475 env->dcache_line_size))); 476 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 477 env->icache_line_size))); 478 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 479 env->icache_line_size))); 480 481 if (pcc->l1_dcache_size) { 482 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 483 pcc->l1_dcache_size))); 484 } else { 485 warn_report("Unknown L1 dcache size for cpu"); 486 } 487 if (pcc->l1_icache_size) { 488 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 489 pcc->l1_icache_size))); 490 } else { 491 warn_report("Unknown L1 icache size for cpu"); 492 } 493 494 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 497 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 499 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 500 501 if (env->spr_cb[SPR_PURR].oea_read) { 502 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 503 } 504 505 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 507 segs, sizeof(segs)))); 508 } 509 510 /* Advertise VSX (vector extensions) if available 511 * 1 == VMX / Altivec available 512 * 2 == VSX available 513 * 514 * Only CPUs for which we create core types in spapr_cpu_core.c 515 * are possible, and all of those have VMX */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 518 } else { 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 520 } 521 522 /* Advertise DFP (Decimal Floating Point) if available 523 * 0 / no property == no DFP 524 * 1 == DFP available */ 525 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 527 } 528 529 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 530 sizeof(page_sizes_prop)); 531 if (page_sizes_prop_size) { 532 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 533 page_sizes_prop, page_sizes_prop_size))); 534 } 535 536 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 537 538 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 539 cs->cpu_index / vcpus_per_socket))); 540 541 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 542 pft_size_prop, sizeof(pft_size_prop)))); 543 544 if (nb_numa_nodes > 1) { 545 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 546 } 547 548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 549 550 if (pcc->radix_page_info) { 551 for (i = 0; i < pcc->radix_page_info->count; i++) { 552 radix_AP_encodings[i] = 553 cpu_to_be32(pcc->radix_page_info->entries[i]); 554 } 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 556 radix_AP_encodings, 557 pcc->radix_page_info->count * 558 sizeof(radix_AP_encodings[0])))); 559 } 560 } 561 562 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 563 { 564 CPUState **rev; 565 CPUState *cs; 566 int n_cpus; 567 int cpus_offset; 568 char *nodename; 569 int i; 570 571 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 572 _FDT(cpus_offset); 573 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 575 576 /* 577 * We walk the CPUs in reverse order to ensure that CPU DT nodes 578 * created by fdt_add_subnode() end up in the right order in FDT 579 * for the guest kernel the enumerate the CPUs correctly. 580 * 581 * The CPU list cannot be traversed in reverse order, so we need 582 * to do extra work. 583 */ 584 n_cpus = 0; 585 rev = NULL; 586 CPU_FOREACH(cs) { 587 rev = g_renew(CPUState *, rev, n_cpus + 1); 588 rev[n_cpus++] = cs; 589 } 590 591 for (i = n_cpus - 1; i >= 0; i--) { 592 CPUState *cs = rev[i]; 593 PowerPCCPU *cpu = POWERPC_CPU(cs); 594 int index = spapr_get_vcpu_id(cpu); 595 DeviceClass *dc = DEVICE_GET_CLASS(cs); 596 int offset; 597 598 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 599 continue; 600 } 601 602 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 603 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 604 g_free(nodename); 605 _FDT(offset); 606 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 607 } 608 609 g_free(rev); 610 } 611 612 static int spapr_rng_populate_dt(void *fdt) 613 { 614 int node; 615 int ret; 616 617 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 618 if (node <= 0) { 619 return -1; 620 } 621 ret = fdt_setprop_string(fdt, node, "device_type", 622 "ibm,platform-facilities"); 623 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 624 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 625 626 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 627 if (node <= 0) { 628 return -1; 629 } 630 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 631 632 return ret ? -1 : 0; 633 } 634 635 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 636 { 637 MemoryDeviceInfoList *info; 638 639 for (info = list; info; info = info->next) { 640 MemoryDeviceInfo *value = info->value; 641 642 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 643 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 644 645 if (addr >= pcdimm_info->addr && 646 addr < (pcdimm_info->addr + pcdimm_info->size)) { 647 return pcdimm_info->node; 648 } 649 } 650 } 651 652 return -1; 653 } 654 655 struct sPAPRDrconfCellV2 { 656 uint32_t seq_lmbs; 657 uint64_t base_addr; 658 uint32_t drc_index; 659 uint32_t aa_index; 660 uint32_t flags; 661 } QEMU_PACKED; 662 663 typedef struct DrconfCellQueue { 664 struct sPAPRDrconfCellV2 cell; 665 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 666 } DrconfCellQueue; 667 668 static DrconfCellQueue * 669 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 670 uint32_t drc_index, uint32_t aa_index, 671 uint32_t flags) 672 { 673 DrconfCellQueue *elem; 674 675 elem = g_malloc0(sizeof(*elem)); 676 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 677 elem->cell.base_addr = cpu_to_be64(base_addr); 678 elem->cell.drc_index = cpu_to_be32(drc_index); 679 elem->cell.aa_index = cpu_to_be32(aa_index); 680 elem->cell.flags = cpu_to_be32(flags); 681 682 return elem; 683 } 684 685 /* ibm,dynamic-memory-v2 */ 686 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 687 int offset, MemoryDeviceInfoList *dimms) 688 { 689 MachineState *machine = MACHINE(spapr); 690 uint8_t *int_buf, *cur_index; 691 int ret; 692 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 693 uint64_t addr, cur_addr, size; 694 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 695 uint64_t mem_end = machine->device_memory->base + 696 memory_region_size(&machine->device_memory->mr); 697 uint32_t node, buf_len, nr_entries = 0; 698 sPAPRDRConnector *drc; 699 DrconfCellQueue *elem, *next; 700 MemoryDeviceInfoList *info; 701 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 702 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 703 704 /* Entry to cover RAM and the gap area */ 705 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 706 SPAPR_LMB_FLAGS_RESERVED | 707 SPAPR_LMB_FLAGS_DRC_INVALID); 708 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 709 nr_entries++; 710 711 cur_addr = machine->device_memory->base; 712 for (info = dimms; info; info = info->next) { 713 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 714 715 addr = di->addr; 716 size = di->size; 717 node = di->node; 718 719 /* Entry for hot-pluggable area */ 720 if (cur_addr < addr) { 721 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 722 g_assert(drc); 723 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 724 cur_addr, spapr_drc_index(drc), -1, 0); 725 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 726 nr_entries++; 727 } 728 729 /* Entry for DIMM */ 730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 731 g_assert(drc); 732 elem = spapr_get_drconf_cell(size / lmb_size, addr, 733 spapr_drc_index(drc), node, 734 SPAPR_LMB_FLAGS_ASSIGNED); 735 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 736 nr_entries++; 737 cur_addr = addr + size; 738 } 739 740 /* Entry for remaining hotpluggable area */ 741 if (cur_addr < mem_end) { 742 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 743 g_assert(drc); 744 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 745 cur_addr, spapr_drc_index(drc), -1, 0); 746 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 747 nr_entries++; 748 } 749 750 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 751 int_buf = cur_index = g_malloc0(buf_len); 752 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 753 cur_index += sizeof(nr_entries); 754 755 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 756 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 757 cur_index += sizeof(elem->cell); 758 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 759 g_free(elem); 760 } 761 762 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 763 g_free(int_buf); 764 if (ret < 0) { 765 return -1; 766 } 767 return 0; 768 } 769 770 /* ibm,dynamic-memory */ 771 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 772 int offset, MemoryDeviceInfoList *dimms) 773 { 774 MachineState *machine = MACHINE(spapr); 775 int i, ret; 776 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 777 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 778 uint32_t nr_lmbs = (machine->device_memory->base + 779 memory_region_size(&machine->device_memory->mr)) / 780 lmb_size; 781 uint32_t *int_buf, *cur_index, buf_len; 782 783 /* 784 * Allocate enough buffer size to fit in ibm,dynamic-memory 785 */ 786 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 787 cur_index = int_buf = g_malloc0(buf_len); 788 int_buf[0] = cpu_to_be32(nr_lmbs); 789 cur_index++; 790 for (i = 0; i < nr_lmbs; i++) { 791 uint64_t addr = i * lmb_size; 792 uint32_t *dynamic_memory = cur_index; 793 794 if (i >= device_lmb_start) { 795 sPAPRDRConnector *drc; 796 797 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 798 g_assert(drc); 799 800 dynamic_memory[0] = cpu_to_be32(addr >> 32); 801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 802 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 804 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 805 if (memory_region_present(get_system_memory(), addr)) { 806 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 807 } else { 808 dynamic_memory[5] = cpu_to_be32(0); 809 } 810 } else { 811 /* 812 * LMB information for RMA, boot time RAM and gap b/n RAM and 813 * device memory region -- all these are marked as reserved 814 * and as having no valid DRC. 815 */ 816 dynamic_memory[0] = cpu_to_be32(addr >> 32); 817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 818 dynamic_memory[2] = cpu_to_be32(0); 819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 820 dynamic_memory[4] = cpu_to_be32(-1); 821 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 822 SPAPR_LMB_FLAGS_DRC_INVALID); 823 } 824 825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 826 } 827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 828 g_free(int_buf); 829 if (ret < 0) { 830 return -1; 831 } 832 return 0; 833 } 834 835 /* 836 * Adds ibm,dynamic-reconfiguration-memory node. 837 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 838 * of this device tree node. 839 */ 840 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 841 { 842 MachineState *machine = MACHINE(spapr); 843 int ret, i, offset; 844 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 845 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 846 uint32_t *int_buf, *cur_index, buf_len; 847 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 848 MemoryDeviceInfoList *dimms = NULL; 849 850 /* 851 * Don't create the node if there is no device memory 852 */ 853 if (machine->ram_size == machine->maxram_size) { 854 return 0; 855 } 856 857 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 858 859 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 860 sizeof(prop_lmb_size)); 861 if (ret < 0) { 862 return ret; 863 } 864 865 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 866 if (ret < 0) { 867 return ret; 868 } 869 870 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 871 if (ret < 0) { 872 return ret; 873 } 874 875 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 876 dimms = qmp_memory_device_list(); 877 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 878 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 879 } else { 880 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 881 } 882 qapi_free_MemoryDeviceInfoList(dimms); 883 884 if (ret < 0) { 885 return ret; 886 } 887 888 /* ibm,associativity-lookup-arrays */ 889 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 890 cur_index = int_buf = g_malloc0(buf_len); 891 int_buf[0] = cpu_to_be32(nr_nodes); 892 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 893 cur_index += 2; 894 for (i = 0; i < nr_nodes; i++) { 895 uint32_t associativity[] = { 896 cpu_to_be32(0x0), 897 cpu_to_be32(0x0), 898 cpu_to_be32(0x0), 899 cpu_to_be32(i) 900 }; 901 memcpy(cur_index, associativity, sizeof(associativity)); 902 cur_index += 4; 903 } 904 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 905 (cur_index - int_buf) * sizeof(uint32_t)); 906 g_free(int_buf); 907 908 return ret; 909 } 910 911 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 912 sPAPROptionVector *ov5_updates) 913 { 914 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 915 int ret = 0, offset; 916 917 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 918 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 919 g_assert(smc->dr_lmb_enabled); 920 ret = spapr_populate_drconf_memory(spapr, fdt); 921 if (ret) { 922 goto out; 923 } 924 } 925 926 offset = fdt_path_offset(fdt, "/chosen"); 927 if (offset < 0) { 928 offset = fdt_add_subnode(fdt, 0, "chosen"); 929 if (offset < 0) { 930 return offset; 931 } 932 } 933 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 934 "ibm,architecture-vec-5"); 935 936 out: 937 return ret; 938 } 939 940 static bool spapr_hotplugged_dev_before_cas(void) 941 { 942 Object *drc_container, *obj; 943 ObjectProperty *prop; 944 ObjectPropertyIterator iter; 945 946 drc_container = container_get(object_get_root(), "/dr-connector"); 947 object_property_iter_init(&iter, drc_container); 948 while ((prop = object_property_iter_next(&iter))) { 949 if (!strstart(prop->type, "link<", NULL)) { 950 continue; 951 } 952 obj = object_property_get_link(drc_container, prop->name, NULL); 953 if (spapr_drc_needed(obj)) { 954 return true; 955 } 956 } 957 return false; 958 } 959 960 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 961 target_ulong addr, target_ulong size, 962 sPAPROptionVector *ov5_updates) 963 { 964 void *fdt, *fdt_skel; 965 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 966 967 if (spapr_hotplugged_dev_before_cas()) { 968 return 1; 969 } 970 971 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 972 error_report("SLOF provided an unexpected CAS buffer size " 973 TARGET_FMT_lu " (min: %zu, max: %u)", 974 size, sizeof(hdr), FW_MAX_SIZE); 975 exit(EXIT_FAILURE); 976 } 977 978 size -= sizeof(hdr); 979 980 /* Create skeleton */ 981 fdt_skel = g_malloc0(size); 982 _FDT((fdt_create(fdt_skel, size))); 983 _FDT((fdt_finish_reservemap(fdt_skel))); 984 _FDT((fdt_begin_node(fdt_skel, ""))); 985 _FDT((fdt_end_node(fdt_skel))); 986 _FDT((fdt_finish(fdt_skel))); 987 fdt = g_malloc0(size); 988 _FDT((fdt_open_into(fdt_skel, fdt, size))); 989 g_free(fdt_skel); 990 991 /* Fixup cpu nodes */ 992 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 993 994 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 995 return -1; 996 } 997 998 /* Pack resulting tree */ 999 _FDT((fdt_pack(fdt))); 1000 1001 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1002 trace_spapr_cas_failed(size); 1003 return -1; 1004 } 1005 1006 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1007 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1008 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1009 g_free(fdt); 1010 1011 return 0; 1012 } 1013 1014 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1015 { 1016 int rtas; 1017 GString *hypertas = g_string_sized_new(256); 1018 GString *qemu_hypertas = g_string_sized_new(256); 1019 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1020 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1021 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1022 uint32_t lrdr_capacity[] = { 1023 cpu_to_be32(max_device_addr >> 32), 1024 cpu_to_be32(max_device_addr & 0xffffffff), 1025 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1026 cpu_to_be32(max_cpus / smp_threads), 1027 }; 1028 uint32_t maxdomains[] = { 1029 cpu_to_be32(4), 1030 cpu_to_be32(0), 1031 cpu_to_be32(0), 1032 cpu_to_be32(0), 1033 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1), 1034 }; 1035 1036 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1037 1038 /* hypertas */ 1039 add_str(hypertas, "hcall-pft"); 1040 add_str(hypertas, "hcall-term"); 1041 add_str(hypertas, "hcall-dabr"); 1042 add_str(hypertas, "hcall-interrupt"); 1043 add_str(hypertas, "hcall-tce"); 1044 add_str(hypertas, "hcall-vio"); 1045 add_str(hypertas, "hcall-splpar"); 1046 add_str(hypertas, "hcall-bulk"); 1047 add_str(hypertas, "hcall-set-mode"); 1048 add_str(hypertas, "hcall-sprg0"); 1049 add_str(hypertas, "hcall-copy"); 1050 add_str(hypertas, "hcall-debug"); 1051 add_str(hypertas, "hcall-vphn"); 1052 add_str(qemu_hypertas, "hcall-memop1"); 1053 1054 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1055 add_str(hypertas, "hcall-multi-tce"); 1056 } 1057 1058 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1059 add_str(hypertas, "hcall-hpt-resize"); 1060 } 1061 1062 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1063 hypertas->str, hypertas->len)); 1064 g_string_free(hypertas, TRUE); 1065 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1066 qemu_hypertas->str, qemu_hypertas->len)); 1067 g_string_free(qemu_hypertas, TRUE); 1068 1069 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1070 refpoints, sizeof(refpoints))); 1071 1072 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1073 maxdomains, sizeof(maxdomains))); 1074 1075 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1076 RTAS_ERROR_LOG_MAX)); 1077 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1078 RTAS_EVENT_SCAN_RATE)); 1079 1080 g_assert(msi_nonbroken); 1081 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1082 1083 /* 1084 * According to PAPR, rtas ibm,os-term does not guarantee a return 1085 * back to the guest cpu. 1086 * 1087 * While an additional ibm,extended-os-term property indicates 1088 * that rtas call return will always occur. Set this property. 1089 */ 1090 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1091 1092 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1093 lrdr_capacity, sizeof(lrdr_capacity))); 1094 1095 spapr_dt_rtas_tokens(fdt, rtas); 1096 } 1097 1098 /* 1099 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1100 * and the XIVE features that the guest may request and thus the valid 1101 * values for bytes 23..26 of option vector 5: 1102 */ 1103 static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt, 1104 int chosen) 1105 { 1106 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1107 1108 char val[2 * 4] = { 1109 23, spapr->irq->ov5, /* Xive mode. */ 1110 24, 0x00, /* Hash/Radix, filled in below. */ 1111 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1112 26, 0x40, /* Radix options: GTSE == yes. */ 1113 }; 1114 1115 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1116 first_ppc_cpu->compat_pvr)) { 1117 /* 1118 * If we're in a pre POWER9 compat mode then the guest should 1119 * do hash and use the legacy interrupt mode 1120 */ 1121 val[1] = 0x00; /* XICS */ 1122 val[3] = 0x00; /* Hash */ 1123 } else if (kvm_enabled()) { 1124 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1125 val[3] = 0x80; /* OV5_MMU_BOTH */ 1126 } else if (kvmppc_has_cap_mmu_radix()) { 1127 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1128 } else { 1129 val[3] = 0x00; /* Hash */ 1130 } 1131 } else { 1132 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1133 val[3] = 0xC0; 1134 } 1135 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1136 val, sizeof(val))); 1137 } 1138 1139 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1140 { 1141 MachineState *machine = MACHINE(spapr); 1142 int chosen; 1143 const char *boot_device = machine->boot_order; 1144 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1145 size_t cb = 0; 1146 char *bootlist = get_boot_devices_list(&cb); 1147 1148 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1149 1150 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1151 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1152 spapr->initrd_base)); 1153 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1154 spapr->initrd_base + spapr->initrd_size)); 1155 1156 if (spapr->kernel_size) { 1157 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1158 cpu_to_be64(spapr->kernel_size) }; 1159 1160 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1161 &kprop, sizeof(kprop))); 1162 if (spapr->kernel_le) { 1163 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1164 } 1165 } 1166 if (boot_menu) { 1167 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1168 } 1169 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1170 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1171 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1172 1173 if (cb && bootlist) { 1174 int i; 1175 1176 for (i = 0; i < cb; i++) { 1177 if (bootlist[i] == '\n') { 1178 bootlist[i] = ' '; 1179 } 1180 } 1181 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1182 } 1183 1184 if (boot_device && strlen(boot_device)) { 1185 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1186 } 1187 1188 if (!spapr->has_graphics && stdout_path) { 1189 /* 1190 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1191 * kernel. New platforms should only use the "stdout-path" property. Set 1192 * the new property and continue using older property to remain 1193 * compatible with the existing firmware. 1194 */ 1195 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1196 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1197 } 1198 1199 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1200 1201 g_free(stdout_path); 1202 g_free(bootlist); 1203 } 1204 1205 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1206 { 1207 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1208 * KVM to work under pHyp with some guest co-operation */ 1209 int hypervisor; 1210 uint8_t hypercall[16]; 1211 1212 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1213 /* indicate KVM hypercall interface */ 1214 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1215 if (kvmppc_has_cap_fixup_hcalls()) { 1216 /* 1217 * Older KVM versions with older guest kernels were broken 1218 * with the magic page, don't allow the guest to map it. 1219 */ 1220 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1221 sizeof(hypercall))) { 1222 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1223 hypercall, sizeof(hypercall))); 1224 } 1225 } 1226 } 1227 1228 static void *spapr_build_fdt(sPAPRMachineState *spapr) 1229 { 1230 MachineState *machine = MACHINE(spapr); 1231 MachineClass *mc = MACHINE_GET_CLASS(machine); 1232 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1233 int ret; 1234 void *fdt; 1235 sPAPRPHBState *phb; 1236 char *buf; 1237 1238 fdt = g_malloc0(FDT_MAX_SIZE); 1239 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1240 1241 /* Root node */ 1242 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1243 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1244 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1245 1246 /* 1247 * Add info to guest to indentify which host is it being run on 1248 * and what is the uuid of the guest 1249 */ 1250 if (spapr->host_model && !g_str_equal(spapr->host_model, "none")) { 1251 if (g_str_equal(spapr->host_model, "passthrough")) { 1252 /* -M host-model=passthrough */ 1253 if (kvmppc_get_host_model(&buf)) { 1254 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1255 g_free(buf); 1256 } 1257 } else { 1258 /* -M host-model=<user-string> */ 1259 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1260 } 1261 } 1262 1263 if (spapr->host_serial && !g_str_equal(spapr->host_serial, "none")) { 1264 if (g_str_equal(spapr->host_serial, "passthrough")) { 1265 /* -M host-serial=passthrough */ 1266 if (kvmppc_get_host_serial(&buf)) { 1267 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1268 g_free(buf); 1269 } 1270 } else { 1271 /* -M host-serial=<user-string> */ 1272 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1273 } 1274 } 1275 1276 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1277 1278 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1279 if (qemu_uuid_set) { 1280 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1281 } 1282 g_free(buf); 1283 1284 if (qemu_get_vm_name()) { 1285 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1286 qemu_get_vm_name())); 1287 } 1288 1289 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1290 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1291 1292 /* /interrupt controller */ 1293 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, 1294 PHANDLE_INTC); 1295 1296 ret = spapr_populate_memory(spapr, fdt); 1297 if (ret < 0) { 1298 error_report("couldn't setup memory nodes in fdt"); 1299 exit(1); 1300 } 1301 1302 /* /vdevice */ 1303 spapr_dt_vdevice(spapr->vio_bus, fdt); 1304 1305 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1306 ret = spapr_rng_populate_dt(fdt); 1307 if (ret < 0) { 1308 error_report("could not set up rng device in the fdt"); 1309 exit(1); 1310 } 1311 } 1312 1313 QLIST_FOREACH(phb, &spapr->phbs, list) { 1314 ret = spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt, 1315 spapr->irq->nr_msis); 1316 if (ret < 0) { 1317 error_report("couldn't setup PCI devices in fdt"); 1318 exit(1); 1319 } 1320 } 1321 1322 /* cpus */ 1323 spapr_populate_cpus_dt_node(fdt, spapr); 1324 1325 if (smc->dr_lmb_enabled) { 1326 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1327 } 1328 1329 if (mc->has_hotpluggable_cpus) { 1330 int offset = fdt_path_offset(fdt, "/cpus"); 1331 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1332 SPAPR_DR_CONNECTOR_TYPE_CPU); 1333 if (ret < 0) { 1334 error_report("Couldn't set up CPU DR device tree properties"); 1335 exit(1); 1336 } 1337 } 1338 1339 /* /event-sources */ 1340 spapr_dt_events(spapr, fdt); 1341 1342 /* /rtas */ 1343 spapr_dt_rtas(spapr, fdt); 1344 1345 /* /chosen */ 1346 spapr_dt_chosen(spapr, fdt); 1347 1348 /* /hypervisor */ 1349 if (kvm_enabled()) { 1350 spapr_dt_hypervisor(spapr, fdt); 1351 } 1352 1353 /* Build memory reserve map */ 1354 if (spapr->kernel_size) { 1355 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1356 } 1357 if (spapr->initrd_size) { 1358 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1359 } 1360 1361 /* ibm,client-architecture-support updates */ 1362 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1363 if (ret < 0) { 1364 error_report("couldn't setup CAS properties fdt"); 1365 exit(1); 1366 } 1367 1368 return fdt; 1369 } 1370 1371 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1372 { 1373 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1374 } 1375 1376 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1377 PowerPCCPU *cpu) 1378 { 1379 CPUPPCState *env = &cpu->env; 1380 1381 /* The TCG path should also be holding the BQL at this point */ 1382 g_assert(qemu_mutex_iothread_locked()); 1383 1384 if (msr_pr) { 1385 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1386 env->gpr[3] = H_PRIVILEGE; 1387 } else { 1388 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1389 } 1390 } 1391 1392 struct LPCRSyncState { 1393 target_ulong value; 1394 target_ulong mask; 1395 }; 1396 1397 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1398 { 1399 struct LPCRSyncState *s = arg.host_ptr; 1400 PowerPCCPU *cpu = POWERPC_CPU(cs); 1401 CPUPPCState *env = &cpu->env; 1402 target_ulong lpcr; 1403 1404 cpu_synchronize_state(cs); 1405 lpcr = env->spr[SPR_LPCR]; 1406 lpcr &= ~s->mask; 1407 lpcr |= s->value; 1408 ppc_store_lpcr(cpu, lpcr); 1409 } 1410 1411 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1412 { 1413 CPUState *cs; 1414 struct LPCRSyncState s = { 1415 .value = value, 1416 .mask = mask 1417 }; 1418 CPU_FOREACH(cs) { 1419 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1420 } 1421 } 1422 1423 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1424 { 1425 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1426 1427 return spapr->patb_entry; 1428 } 1429 1430 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1431 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1432 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1433 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1434 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1435 1436 /* 1437 * Get the fd to access the kernel htab, re-opening it if necessary 1438 */ 1439 static int get_htab_fd(sPAPRMachineState *spapr) 1440 { 1441 Error *local_err = NULL; 1442 1443 if (spapr->htab_fd >= 0) { 1444 return spapr->htab_fd; 1445 } 1446 1447 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1448 if (spapr->htab_fd < 0) { 1449 error_report_err(local_err); 1450 } 1451 1452 return spapr->htab_fd; 1453 } 1454 1455 void close_htab_fd(sPAPRMachineState *spapr) 1456 { 1457 if (spapr->htab_fd >= 0) { 1458 close(spapr->htab_fd); 1459 } 1460 spapr->htab_fd = -1; 1461 } 1462 1463 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1464 { 1465 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1466 1467 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1468 } 1469 1470 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1471 { 1472 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1473 1474 assert(kvm_enabled()); 1475 1476 if (!spapr->htab) { 1477 return 0; 1478 } 1479 1480 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1481 } 1482 1483 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1484 hwaddr ptex, int n) 1485 { 1486 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1487 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1488 1489 if (!spapr->htab) { 1490 /* 1491 * HTAB is controlled by KVM. Fetch into temporary buffer 1492 */ 1493 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1494 kvmppc_read_hptes(hptes, ptex, n); 1495 return hptes; 1496 } 1497 1498 /* 1499 * HTAB is controlled by QEMU. Just point to the internally 1500 * accessible PTEG. 1501 */ 1502 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1503 } 1504 1505 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1506 const ppc_hash_pte64_t *hptes, 1507 hwaddr ptex, int n) 1508 { 1509 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1510 1511 if (!spapr->htab) { 1512 g_free((void *)hptes); 1513 } 1514 1515 /* Nothing to do for qemu managed HPT */ 1516 } 1517 1518 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1519 uint64_t pte0, uint64_t pte1) 1520 { 1521 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1522 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1523 1524 if (!spapr->htab) { 1525 kvmppc_write_hpte(ptex, pte0, pte1); 1526 } else { 1527 if (pte0 & HPTE64_V_VALID) { 1528 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1529 /* 1530 * When setting valid, we write PTE1 first. This ensures 1531 * proper synchronization with the reading code in 1532 * ppc_hash64_pteg_search() 1533 */ 1534 smp_wmb(); 1535 stq_p(spapr->htab + offset, pte0); 1536 } else { 1537 stq_p(spapr->htab + offset, pte0); 1538 /* 1539 * When clearing it we set PTE0 first. This ensures proper 1540 * synchronization with the reading code in 1541 * ppc_hash64_pteg_search() 1542 */ 1543 smp_wmb(); 1544 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1545 } 1546 } 1547 } 1548 1549 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1550 { 1551 int shift; 1552 1553 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1554 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1555 * that's much more than is needed for Linux guests */ 1556 shift = ctz64(pow2ceil(ramsize)) - 7; 1557 shift = MAX(shift, 18); /* Minimum architected size */ 1558 shift = MIN(shift, 46); /* Maximum architected size */ 1559 return shift; 1560 } 1561 1562 void spapr_free_hpt(sPAPRMachineState *spapr) 1563 { 1564 g_free(spapr->htab); 1565 spapr->htab = NULL; 1566 spapr->htab_shift = 0; 1567 close_htab_fd(spapr); 1568 } 1569 1570 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1571 Error **errp) 1572 { 1573 long rc; 1574 1575 /* Clean up any HPT info from a previous boot */ 1576 spapr_free_hpt(spapr); 1577 1578 rc = kvmppc_reset_htab(shift); 1579 if (rc < 0) { 1580 /* kernel-side HPT needed, but couldn't allocate one */ 1581 error_setg_errno(errp, errno, 1582 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1583 shift); 1584 /* This is almost certainly fatal, but if the caller really 1585 * wants to carry on with shift == 0, it's welcome to try */ 1586 } else if (rc > 0) { 1587 /* kernel-side HPT allocated */ 1588 if (rc != shift) { 1589 error_setg(errp, 1590 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1591 shift, rc); 1592 } 1593 1594 spapr->htab_shift = shift; 1595 spapr->htab = NULL; 1596 } else { 1597 /* kernel-side HPT not needed, allocate in userspace instead */ 1598 size_t size = 1ULL << shift; 1599 int i; 1600 1601 spapr->htab = qemu_memalign(size, size); 1602 if (!spapr->htab) { 1603 error_setg_errno(errp, errno, 1604 "Could not allocate HPT of order %d", shift); 1605 return; 1606 } 1607 1608 memset(spapr->htab, 0, size); 1609 spapr->htab_shift = shift; 1610 1611 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1612 DIRTY_HPTE(HPTE(spapr->htab, i)); 1613 } 1614 } 1615 /* We're setting up a hash table, so that means we're not radix */ 1616 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1617 } 1618 1619 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1620 { 1621 int hpt_shift; 1622 1623 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1624 || (spapr->cas_reboot 1625 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1626 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1627 } else { 1628 uint64_t current_ram_size; 1629 1630 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1631 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1632 } 1633 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1634 1635 if (spapr->vrma_adjust) { 1636 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1637 spapr->htab_shift); 1638 } 1639 } 1640 1641 static int spapr_reset_drcs(Object *child, void *opaque) 1642 { 1643 sPAPRDRConnector *drc = 1644 (sPAPRDRConnector *) object_dynamic_cast(child, 1645 TYPE_SPAPR_DR_CONNECTOR); 1646 1647 if (drc) { 1648 spapr_drc_reset(drc); 1649 } 1650 1651 return 0; 1652 } 1653 1654 static void spapr_machine_reset(void) 1655 { 1656 MachineState *machine = MACHINE(qdev_get_machine()); 1657 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1658 PowerPCCPU *first_ppc_cpu; 1659 uint32_t rtas_limit; 1660 hwaddr rtas_addr, fdt_addr; 1661 void *fdt; 1662 int rc; 1663 1664 spapr_caps_apply(spapr); 1665 1666 first_ppc_cpu = POWERPC_CPU(first_cpu); 1667 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1668 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1669 spapr->max_compat_pvr)) { 1670 /* If using KVM with radix mode available, VCPUs can be started 1671 * without a HPT because KVM will start them in radix mode. 1672 * Set the GR bit in PATB so that we know there is no HPT. */ 1673 spapr->patb_entry = PATBE1_GR; 1674 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1675 } else { 1676 spapr_setup_hpt_and_vrma(spapr); 1677 } 1678 1679 /* if this reset wasn't generated by CAS, we should reset our 1680 * negotiated options and start from scratch */ 1681 if (!spapr->cas_reboot) { 1682 spapr_ovec_cleanup(spapr->ov5_cas); 1683 spapr->ov5_cas = spapr_ovec_new(); 1684 1685 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1686 } 1687 1688 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1689 spapr_irq_msi_reset(spapr); 1690 } 1691 1692 qemu_devices_reset(); 1693 1694 /* 1695 * This is fixing some of the default configuration of the XIVE 1696 * devices. To be called after the reset of the machine devices. 1697 */ 1698 spapr_irq_reset(spapr, &error_fatal); 1699 1700 /* DRC reset may cause a device to be unplugged. This will cause troubles 1701 * if this device is used by another device (eg, a running vhost backend 1702 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1703 * situations, we reset DRCs after all devices have been reset. 1704 */ 1705 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1706 1707 spapr_clear_pending_events(spapr); 1708 1709 /* 1710 * We place the device tree and RTAS just below either the top of the RMA, 1711 * or just below 2GB, whichever is lower, so that it can be 1712 * processed with 32-bit real mode code if necessary 1713 */ 1714 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1715 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1716 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1717 1718 fdt = spapr_build_fdt(spapr); 1719 1720 spapr_load_rtas(spapr, fdt, rtas_addr); 1721 1722 rc = fdt_pack(fdt); 1723 1724 /* Should only fail if we've built a corrupted tree */ 1725 assert(rc == 0); 1726 1727 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1728 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1729 fdt_totalsize(fdt), FDT_MAX_SIZE); 1730 exit(1); 1731 } 1732 1733 /* Load the fdt */ 1734 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1735 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1736 g_free(spapr->fdt_blob); 1737 spapr->fdt_size = fdt_totalsize(fdt); 1738 spapr->fdt_initial_size = spapr->fdt_size; 1739 spapr->fdt_blob = fdt; 1740 1741 /* Set up the entry state */ 1742 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1743 first_ppc_cpu->env.gpr[5] = 0; 1744 1745 spapr->cas_reboot = false; 1746 } 1747 1748 static void spapr_create_nvram(sPAPRMachineState *spapr) 1749 { 1750 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1751 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1752 1753 if (dinfo) { 1754 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1755 &error_fatal); 1756 } 1757 1758 qdev_init_nofail(dev); 1759 1760 spapr->nvram = (struct sPAPRNVRAM *)dev; 1761 } 1762 1763 static void spapr_rtc_create(sPAPRMachineState *spapr) 1764 { 1765 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1766 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1767 &error_fatal); 1768 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1769 &error_fatal); 1770 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1771 "date", &error_fatal); 1772 } 1773 1774 /* Returns whether we want to use VGA or not */ 1775 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1776 { 1777 switch (vga_interface_type) { 1778 case VGA_NONE: 1779 return false; 1780 case VGA_DEVICE: 1781 return true; 1782 case VGA_STD: 1783 case VGA_VIRTIO: 1784 case VGA_CIRRUS: 1785 return pci_vga_init(pci_bus) != NULL; 1786 default: 1787 error_setg(errp, 1788 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1789 return false; 1790 } 1791 } 1792 1793 static int spapr_pre_load(void *opaque) 1794 { 1795 int rc; 1796 1797 rc = spapr_caps_pre_load(opaque); 1798 if (rc) { 1799 return rc; 1800 } 1801 1802 return 0; 1803 } 1804 1805 static int spapr_post_load(void *opaque, int version_id) 1806 { 1807 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1808 int err = 0; 1809 1810 err = spapr_caps_post_migration(spapr); 1811 if (err) { 1812 return err; 1813 } 1814 1815 /* 1816 * In earlier versions, there was no separate qdev for the PAPR 1817 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1818 * So when migrating from those versions, poke the incoming offset 1819 * value into the RTC device 1820 */ 1821 if (version_id < 3) { 1822 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1823 if (err) { 1824 return err; 1825 } 1826 } 1827 1828 if (kvm_enabled() && spapr->patb_entry) { 1829 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1830 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1831 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1832 1833 /* 1834 * Update LPCR:HR and UPRT as they may not be set properly in 1835 * the stream 1836 */ 1837 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1838 LPCR_HR | LPCR_UPRT); 1839 1840 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1841 if (err) { 1842 error_report("Process table config unsupported by the host"); 1843 return -EINVAL; 1844 } 1845 } 1846 1847 err = spapr_irq_post_load(spapr, version_id); 1848 if (err) { 1849 return err; 1850 } 1851 1852 return err; 1853 } 1854 1855 static int spapr_pre_save(void *opaque) 1856 { 1857 int rc; 1858 1859 rc = spapr_caps_pre_save(opaque); 1860 if (rc) { 1861 return rc; 1862 } 1863 1864 return 0; 1865 } 1866 1867 static bool version_before_3(void *opaque, int version_id) 1868 { 1869 return version_id < 3; 1870 } 1871 1872 static bool spapr_pending_events_needed(void *opaque) 1873 { 1874 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1875 return !QTAILQ_EMPTY(&spapr->pending_events); 1876 } 1877 1878 static const VMStateDescription vmstate_spapr_event_entry = { 1879 .name = "spapr_event_log_entry", 1880 .version_id = 1, 1881 .minimum_version_id = 1, 1882 .fields = (VMStateField[]) { 1883 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1884 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1885 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1886 NULL, extended_length), 1887 VMSTATE_END_OF_LIST() 1888 }, 1889 }; 1890 1891 static const VMStateDescription vmstate_spapr_pending_events = { 1892 .name = "spapr_pending_events", 1893 .version_id = 1, 1894 .minimum_version_id = 1, 1895 .needed = spapr_pending_events_needed, 1896 .fields = (VMStateField[]) { 1897 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1898 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1899 VMSTATE_END_OF_LIST() 1900 }, 1901 }; 1902 1903 static bool spapr_ov5_cas_needed(void *opaque) 1904 { 1905 sPAPRMachineState *spapr = opaque; 1906 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1907 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1908 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1909 bool cas_needed; 1910 1911 /* Prior to the introduction of sPAPROptionVector, we had two option 1912 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1913 * Both of these options encode machine topology into the device-tree 1914 * in such a way that the now-booted OS should still be able to interact 1915 * appropriately with QEMU regardless of what options were actually 1916 * negotiatied on the source side. 1917 * 1918 * As such, we can avoid migrating the CAS-negotiated options if these 1919 * are the only options available on the current machine/platform. 1920 * Since these are the only options available for pseries-2.7 and 1921 * earlier, this allows us to maintain old->new/new->old migration 1922 * compatibility. 1923 * 1924 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1925 * via default pseries-2.8 machines and explicit command-line parameters. 1926 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1927 * of the actual CAS-negotiated values to continue working properly. For 1928 * example, availability of memory unplug depends on knowing whether 1929 * OV5_HP_EVT was negotiated via CAS. 1930 * 1931 * Thus, for any cases where the set of available CAS-negotiatable 1932 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1933 * include the CAS-negotiated options in the migration stream, unless 1934 * if they affect boot time behaviour only. 1935 */ 1936 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1937 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1938 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1939 1940 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1941 * the mask itself since in the future it's possible "legacy" bits may be 1942 * removed via machine options, which could generate a false positive 1943 * that breaks migration. 1944 */ 1945 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1946 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1947 1948 spapr_ovec_cleanup(ov5_mask); 1949 spapr_ovec_cleanup(ov5_legacy); 1950 spapr_ovec_cleanup(ov5_removed); 1951 1952 return cas_needed; 1953 } 1954 1955 static const VMStateDescription vmstate_spapr_ov5_cas = { 1956 .name = "spapr_option_vector_ov5_cas", 1957 .version_id = 1, 1958 .minimum_version_id = 1, 1959 .needed = spapr_ov5_cas_needed, 1960 .fields = (VMStateField[]) { 1961 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1962 vmstate_spapr_ovec, sPAPROptionVector), 1963 VMSTATE_END_OF_LIST() 1964 }, 1965 }; 1966 1967 static bool spapr_patb_entry_needed(void *opaque) 1968 { 1969 sPAPRMachineState *spapr = opaque; 1970 1971 return !!spapr->patb_entry; 1972 } 1973 1974 static const VMStateDescription vmstate_spapr_patb_entry = { 1975 .name = "spapr_patb_entry", 1976 .version_id = 1, 1977 .minimum_version_id = 1, 1978 .needed = spapr_patb_entry_needed, 1979 .fields = (VMStateField[]) { 1980 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1981 VMSTATE_END_OF_LIST() 1982 }, 1983 }; 1984 1985 static bool spapr_irq_map_needed(void *opaque) 1986 { 1987 sPAPRMachineState *spapr = opaque; 1988 1989 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1990 } 1991 1992 static const VMStateDescription vmstate_spapr_irq_map = { 1993 .name = "spapr_irq_map", 1994 .version_id = 1, 1995 .minimum_version_id = 1, 1996 .needed = spapr_irq_map_needed, 1997 .fields = (VMStateField[]) { 1998 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 1999 VMSTATE_END_OF_LIST() 2000 }, 2001 }; 2002 2003 static bool spapr_dtb_needed(void *opaque) 2004 { 2005 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2006 2007 return smc->update_dt_enabled; 2008 } 2009 2010 static int spapr_dtb_pre_load(void *opaque) 2011 { 2012 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 2013 2014 g_free(spapr->fdt_blob); 2015 spapr->fdt_blob = NULL; 2016 spapr->fdt_size = 0; 2017 2018 return 0; 2019 } 2020 2021 static const VMStateDescription vmstate_spapr_dtb = { 2022 .name = "spapr_dtb", 2023 .version_id = 1, 2024 .minimum_version_id = 1, 2025 .needed = spapr_dtb_needed, 2026 .pre_load = spapr_dtb_pre_load, 2027 .fields = (VMStateField[]) { 2028 VMSTATE_UINT32(fdt_initial_size, sPAPRMachineState), 2029 VMSTATE_UINT32(fdt_size, sPAPRMachineState), 2030 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, sPAPRMachineState, 0, NULL, 2031 fdt_size), 2032 VMSTATE_END_OF_LIST() 2033 }, 2034 }; 2035 2036 static const VMStateDescription vmstate_spapr = { 2037 .name = "spapr", 2038 .version_id = 3, 2039 .minimum_version_id = 1, 2040 .pre_load = spapr_pre_load, 2041 .post_load = spapr_post_load, 2042 .pre_save = spapr_pre_save, 2043 .fields = (VMStateField[]) { 2044 /* used to be @next_irq */ 2045 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2046 2047 /* RTC offset */ 2048 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 2049 2050 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 2051 VMSTATE_END_OF_LIST() 2052 }, 2053 .subsections = (const VMStateDescription*[]) { 2054 &vmstate_spapr_ov5_cas, 2055 &vmstate_spapr_patb_entry, 2056 &vmstate_spapr_pending_events, 2057 &vmstate_spapr_cap_htm, 2058 &vmstate_spapr_cap_vsx, 2059 &vmstate_spapr_cap_dfp, 2060 &vmstate_spapr_cap_cfpc, 2061 &vmstate_spapr_cap_sbbc, 2062 &vmstate_spapr_cap_ibs, 2063 &vmstate_spapr_irq_map, 2064 &vmstate_spapr_cap_nested_kvm_hv, 2065 &vmstate_spapr_dtb, 2066 NULL 2067 } 2068 }; 2069 2070 static int htab_save_setup(QEMUFile *f, void *opaque) 2071 { 2072 sPAPRMachineState *spapr = opaque; 2073 2074 /* "Iteration" header */ 2075 if (!spapr->htab_shift) { 2076 qemu_put_be32(f, -1); 2077 } else { 2078 qemu_put_be32(f, spapr->htab_shift); 2079 } 2080 2081 if (spapr->htab) { 2082 spapr->htab_save_index = 0; 2083 spapr->htab_first_pass = true; 2084 } else { 2085 if (spapr->htab_shift) { 2086 assert(kvm_enabled()); 2087 } 2088 } 2089 2090 2091 return 0; 2092 } 2093 2094 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 2095 int chunkstart, int n_valid, int n_invalid) 2096 { 2097 qemu_put_be32(f, chunkstart); 2098 qemu_put_be16(f, n_valid); 2099 qemu_put_be16(f, n_invalid); 2100 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2101 HASH_PTE_SIZE_64 * n_valid); 2102 } 2103 2104 static void htab_save_end_marker(QEMUFile *f) 2105 { 2106 qemu_put_be32(f, 0); 2107 qemu_put_be16(f, 0); 2108 qemu_put_be16(f, 0); 2109 } 2110 2111 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 2112 int64_t max_ns) 2113 { 2114 bool has_timeout = max_ns != -1; 2115 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2116 int index = spapr->htab_save_index; 2117 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2118 2119 assert(spapr->htab_first_pass); 2120 2121 do { 2122 int chunkstart; 2123 2124 /* Consume invalid HPTEs */ 2125 while ((index < htabslots) 2126 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2127 CLEAN_HPTE(HPTE(spapr->htab, index)); 2128 index++; 2129 } 2130 2131 /* Consume valid HPTEs */ 2132 chunkstart = index; 2133 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2134 && HPTE_VALID(HPTE(spapr->htab, index))) { 2135 CLEAN_HPTE(HPTE(spapr->htab, index)); 2136 index++; 2137 } 2138 2139 if (index > chunkstart) { 2140 int n_valid = index - chunkstart; 2141 2142 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2143 2144 if (has_timeout && 2145 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2146 break; 2147 } 2148 } 2149 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2150 2151 if (index >= htabslots) { 2152 assert(index == htabslots); 2153 index = 0; 2154 spapr->htab_first_pass = false; 2155 } 2156 spapr->htab_save_index = index; 2157 } 2158 2159 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2160 int64_t max_ns) 2161 { 2162 bool final = max_ns < 0; 2163 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2164 int examined = 0, sent = 0; 2165 int index = spapr->htab_save_index; 2166 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2167 2168 assert(!spapr->htab_first_pass); 2169 2170 do { 2171 int chunkstart, invalidstart; 2172 2173 /* Consume non-dirty HPTEs */ 2174 while ((index < htabslots) 2175 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2176 index++; 2177 examined++; 2178 } 2179 2180 chunkstart = index; 2181 /* Consume valid dirty HPTEs */ 2182 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2183 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2184 && HPTE_VALID(HPTE(spapr->htab, index))) { 2185 CLEAN_HPTE(HPTE(spapr->htab, index)); 2186 index++; 2187 examined++; 2188 } 2189 2190 invalidstart = index; 2191 /* Consume invalid dirty HPTEs */ 2192 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2193 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2194 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2195 CLEAN_HPTE(HPTE(spapr->htab, index)); 2196 index++; 2197 examined++; 2198 } 2199 2200 if (index > chunkstart) { 2201 int n_valid = invalidstart - chunkstart; 2202 int n_invalid = index - invalidstart; 2203 2204 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2205 sent += index - chunkstart; 2206 2207 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2208 break; 2209 } 2210 } 2211 2212 if (examined >= htabslots) { 2213 break; 2214 } 2215 2216 if (index >= htabslots) { 2217 assert(index == htabslots); 2218 index = 0; 2219 } 2220 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2221 2222 if (index >= htabslots) { 2223 assert(index == htabslots); 2224 index = 0; 2225 } 2226 2227 spapr->htab_save_index = index; 2228 2229 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2230 } 2231 2232 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2233 #define MAX_KVM_BUF_SIZE 2048 2234 2235 static int htab_save_iterate(QEMUFile *f, void *opaque) 2236 { 2237 sPAPRMachineState *spapr = opaque; 2238 int fd; 2239 int rc = 0; 2240 2241 /* Iteration header */ 2242 if (!spapr->htab_shift) { 2243 qemu_put_be32(f, -1); 2244 return 1; 2245 } else { 2246 qemu_put_be32(f, 0); 2247 } 2248 2249 if (!spapr->htab) { 2250 assert(kvm_enabled()); 2251 2252 fd = get_htab_fd(spapr); 2253 if (fd < 0) { 2254 return fd; 2255 } 2256 2257 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2258 if (rc < 0) { 2259 return rc; 2260 } 2261 } else if (spapr->htab_first_pass) { 2262 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2263 } else { 2264 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2265 } 2266 2267 htab_save_end_marker(f); 2268 2269 return rc; 2270 } 2271 2272 static int htab_save_complete(QEMUFile *f, void *opaque) 2273 { 2274 sPAPRMachineState *spapr = opaque; 2275 int fd; 2276 2277 /* Iteration header */ 2278 if (!spapr->htab_shift) { 2279 qemu_put_be32(f, -1); 2280 return 0; 2281 } else { 2282 qemu_put_be32(f, 0); 2283 } 2284 2285 if (!spapr->htab) { 2286 int rc; 2287 2288 assert(kvm_enabled()); 2289 2290 fd = get_htab_fd(spapr); 2291 if (fd < 0) { 2292 return fd; 2293 } 2294 2295 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2296 if (rc < 0) { 2297 return rc; 2298 } 2299 } else { 2300 if (spapr->htab_first_pass) { 2301 htab_save_first_pass(f, spapr, -1); 2302 } 2303 htab_save_later_pass(f, spapr, -1); 2304 } 2305 2306 /* End marker */ 2307 htab_save_end_marker(f); 2308 2309 return 0; 2310 } 2311 2312 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2313 { 2314 sPAPRMachineState *spapr = opaque; 2315 uint32_t section_hdr; 2316 int fd = -1; 2317 Error *local_err = NULL; 2318 2319 if (version_id < 1 || version_id > 1) { 2320 error_report("htab_load() bad version"); 2321 return -EINVAL; 2322 } 2323 2324 section_hdr = qemu_get_be32(f); 2325 2326 if (section_hdr == -1) { 2327 spapr_free_hpt(spapr); 2328 return 0; 2329 } 2330 2331 if (section_hdr) { 2332 /* First section gives the htab size */ 2333 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2334 if (local_err) { 2335 error_report_err(local_err); 2336 return -EINVAL; 2337 } 2338 return 0; 2339 } 2340 2341 if (!spapr->htab) { 2342 assert(kvm_enabled()); 2343 2344 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2345 if (fd < 0) { 2346 error_report_err(local_err); 2347 return fd; 2348 } 2349 } 2350 2351 while (true) { 2352 uint32_t index; 2353 uint16_t n_valid, n_invalid; 2354 2355 index = qemu_get_be32(f); 2356 n_valid = qemu_get_be16(f); 2357 n_invalid = qemu_get_be16(f); 2358 2359 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2360 /* End of Stream */ 2361 break; 2362 } 2363 2364 if ((index + n_valid + n_invalid) > 2365 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2366 /* Bad index in stream */ 2367 error_report( 2368 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2369 index, n_valid, n_invalid, spapr->htab_shift); 2370 return -EINVAL; 2371 } 2372 2373 if (spapr->htab) { 2374 if (n_valid) { 2375 qemu_get_buffer(f, HPTE(spapr->htab, index), 2376 HASH_PTE_SIZE_64 * n_valid); 2377 } 2378 if (n_invalid) { 2379 memset(HPTE(spapr->htab, index + n_valid), 0, 2380 HASH_PTE_SIZE_64 * n_invalid); 2381 } 2382 } else { 2383 int rc; 2384 2385 assert(fd >= 0); 2386 2387 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2388 if (rc < 0) { 2389 return rc; 2390 } 2391 } 2392 } 2393 2394 if (!spapr->htab) { 2395 assert(fd >= 0); 2396 close(fd); 2397 } 2398 2399 return 0; 2400 } 2401 2402 static void htab_save_cleanup(void *opaque) 2403 { 2404 sPAPRMachineState *spapr = opaque; 2405 2406 close_htab_fd(spapr); 2407 } 2408 2409 static SaveVMHandlers savevm_htab_handlers = { 2410 .save_setup = htab_save_setup, 2411 .save_live_iterate = htab_save_iterate, 2412 .save_live_complete_precopy = htab_save_complete, 2413 .save_cleanup = htab_save_cleanup, 2414 .load_state = htab_load, 2415 }; 2416 2417 static void spapr_boot_set(void *opaque, const char *boot_device, 2418 Error **errp) 2419 { 2420 MachineState *machine = MACHINE(opaque); 2421 machine->boot_order = g_strdup(boot_device); 2422 } 2423 2424 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2425 { 2426 MachineState *machine = MACHINE(spapr); 2427 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2428 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2429 int i; 2430 2431 for (i = 0; i < nr_lmbs; i++) { 2432 uint64_t addr; 2433 2434 addr = i * lmb_size + machine->device_memory->base; 2435 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2436 addr / lmb_size); 2437 } 2438 } 2439 2440 /* 2441 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2442 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2443 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2444 */ 2445 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2446 { 2447 int i; 2448 2449 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2450 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2451 " is not aligned to %" PRIu64 " MiB", 2452 machine->ram_size, 2453 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2454 return; 2455 } 2456 2457 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2458 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2459 " is not aligned to %" PRIu64 " MiB", 2460 machine->ram_size, 2461 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2462 return; 2463 } 2464 2465 for (i = 0; i < nb_numa_nodes; i++) { 2466 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2467 error_setg(errp, 2468 "Node %d memory size 0x%" PRIx64 2469 " is not aligned to %" PRIu64 " MiB", 2470 i, numa_info[i].node_mem, 2471 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2472 return; 2473 } 2474 } 2475 } 2476 2477 /* find cpu slot in machine->possible_cpus by core_id */ 2478 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2479 { 2480 int index = id / smp_threads; 2481 2482 if (index >= ms->possible_cpus->len) { 2483 return NULL; 2484 } 2485 if (idx) { 2486 *idx = index; 2487 } 2488 return &ms->possible_cpus->cpus[index]; 2489 } 2490 2491 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2492 { 2493 Error *local_err = NULL; 2494 bool vsmt_user = !!spapr->vsmt; 2495 int kvm_smt = kvmppc_smt_threads(); 2496 int ret; 2497 2498 if (!kvm_enabled() && (smp_threads > 1)) { 2499 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2500 "on a pseries machine"); 2501 goto out; 2502 } 2503 if (!is_power_of_2(smp_threads)) { 2504 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2505 "machine because it must be a power of 2", smp_threads); 2506 goto out; 2507 } 2508 2509 /* Detemine the VSMT mode to use: */ 2510 if (vsmt_user) { 2511 if (spapr->vsmt < smp_threads) { 2512 error_setg(&local_err, "Cannot support VSMT mode %d" 2513 " because it must be >= threads/core (%d)", 2514 spapr->vsmt, smp_threads); 2515 goto out; 2516 } 2517 /* In this case, spapr->vsmt has been set by the command line */ 2518 } else { 2519 /* 2520 * Default VSMT value is tricky, because we need it to be as 2521 * consistent as possible (for migration), but this requires 2522 * changing it for at least some existing cases. We pick 8 as 2523 * the value that we'd get with KVM on POWER8, the 2524 * overwhelmingly common case in production systems. 2525 */ 2526 spapr->vsmt = MAX(8, smp_threads); 2527 } 2528 2529 /* KVM: If necessary, set the SMT mode: */ 2530 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2531 ret = kvmppc_set_smt_threads(spapr->vsmt); 2532 if (ret) { 2533 /* Looks like KVM isn't able to change VSMT mode */ 2534 error_setg(&local_err, 2535 "Failed to set KVM's VSMT mode to %d (errno %d)", 2536 spapr->vsmt, ret); 2537 /* We can live with that if the default one is big enough 2538 * for the number of threads, and a submultiple of the one 2539 * we want. In this case we'll waste some vcpu ids, but 2540 * behaviour will be correct */ 2541 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2542 warn_report_err(local_err); 2543 local_err = NULL; 2544 goto out; 2545 } else { 2546 if (!vsmt_user) { 2547 error_append_hint(&local_err, 2548 "On PPC, a VM with %d threads/core" 2549 " on a host with %d threads/core" 2550 " requires the use of VSMT mode %d.\n", 2551 smp_threads, kvm_smt, spapr->vsmt); 2552 } 2553 kvmppc_hint_smt_possible(&local_err); 2554 goto out; 2555 } 2556 } 2557 } 2558 /* else TCG: nothing to do currently */ 2559 out: 2560 error_propagate(errp, local_err); 2561 } 2562 2563 static void spapr_init_cpus(sPAPRMachineState *spapr) 2564 { 2565 MachineState *machine = MACHINE(spapr); 2566 MachineClass *mc = MACHINE_GET_CLASS(machine); 2567 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2568 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2569 const CPUArchIdList *possible_cpus; 2570 int boot_cores_nr = smp_cpus / smp_threads; 2571 int i; 2572 2573 possible_cpus = mc->possible_cpu_arch_ids(machine); 2574 if (mc->has_hotpluggable_cpus) { 2575 if (smp_cpus % smp_threads) { 2576 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2577 smp_cpus, smp_threads); 2578 exit(1); 2579 } 2580 if (max_cpus % smp_threads) { 2581 error_report("max_cpus (%u) must be multiple of threads (%u)", 2582 max_cpus, smp_threads); 2583 exit(1); 2584 } 2585 } else { 2586 if (max_cpus != smp_cpus) { 2587 error_report("This machine version does not support CPU hotplug"); 2588 exit(1); 2589 } 2590 boot_cores_nr = possible_cpus->len; 2591 } 2592 2593 if (smc->pre_2_10_has_unused_icps) { 2594 int i; 2595 2596 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2597 /* Dummy entries get deregistered when real ICPState objects 2598 * are registered during CPU core hotplug. 2599 */ 2600 pre_2_10_vmstate_register_dummy_icp(i); 2601 } 2602 } 2603 2604 for (i = 0; i < possible_cpus->len; i++) { 2605 int core_id = i * smp_threads; 2606 2607 if (mc->has_hotpluggable_cpus) { 2608 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2609 spapr_vcpu_id(spapr, core_id)); 2610 } 2611 2612 if (i < boot_cores_nr) { 2613 Object *core = object_new(type); 2614 int nr_threads = smp_threads; 2615 2616 /* Handle the partially filled core for older machine types */ 2617 if ((i + 1) * smp_threads >= smp_cpus) { 2618 nr_threads = smp_cpus - i * smp_threads; 2619 } 2620 2621 object_property_set_int(core, nr_threads, "nr-threads", 2622 &error_fatal); 2623 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2624 &error_fatal); 2625 object_property_set_bool(core, true, "realized", &error_fatal); 2626 2627 object_unref(core); 2628 } 2629 } 2630 } 2631 2632 static PCIHostState *spapr_create_default_phb(void) 2633 { 2634 DeviceState *dev; 2635 2636 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2637 qdev_prop_set_uint32(dev, "index", 0); 2638 qdev_init_nofail(dev); 2639 2640 return PCI_HOST_BRIDGE(dev); 2641 } 2642 2643 /* pSeries LPAR / sPAPR hardware init */ 2644 static void spapr_machine_init(MachineState *machine) 2645 { 2646 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2647 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2648 const char *kernel_filename = machine->kernel_filename; 2649 const char *initrd_filename = machine->initrd_filename; 2650 PCIHostState *phb; 2651 int i; 2652 MemoryRegion *sysmem = get_system_memory(); 2653 MemoryRegion *ram = g_new(MemoryRegion, 1); 2654 hwaddr node0_size = spapr_node0_size(machine); 2655 long load_limit, fw_size; 2656 char *filename; 2657 Error *resize_hpt_err = NULL; 2658 2659 msi_nonbroken = true; 2660 2661 QLIST_INIT(&spapr->phbs); 2662 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2663 2664 /* Determine capabilities to run with */ 2665 spapr_caps_init(spapr); 2666 2667 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2668 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2669 /* 2670 * If the user explicitly requested a mode we should either 2671 * supply it, or fail completely (which we do below). But if 2672 * it's not set explicitly, we reset our mode to something 2673 * that works 2674 */ 2675 if (resize_hpt_err) { 2676 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2677 error_free(resize_hpt_err); 2678 resize_hpt_err = NULL; 2679 } else { 2680 spapr->resize_hpt = smc->resize_hpt_default; 2681 } 2682 } 2683 2684 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2685 2686 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2687 /* 2688 * User requested HPT resize, but this host can't supply it. Bail out 2689 */ 2690 error_report_err(resize_hpt_err); 2691 exit(1); 2692 } 2693 2694 spapr->rma_size = node0_size; 2695 2696 /* With KVM, we don't actually know whether KVM supports an 2697 * unbounded RMA (PR KVM) or is limited by the hash table size 2698 * (HV KVM using VRMA), so we always assume the latter 2699 * 2700 * In that case, we also limit the initial allocations for RTAS 2701 * etc... to 256M since we have no way to know what the VRMA size 2702 * is going to be as it depends on the size of the hash table 2703 * which isn't determined yet. 2704 */ 2705 if (kvm_enabled()) { 2706 spapr->vrma_adjust = 1; 2707 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2708 } 2709 2710 /* Actually we don't support unbounded RMA anymore since we added 2711 * proper emulation of HV mode. The max we can get is 16G which 2712 * also happens to be what we configure for PAPR mode so make sure 2713 * we don't do anything bigger than that 2714 */ 2715 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2716 2717 if (spapr->rma_size > node0_size) { 2718 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2719 spapr->rma_size); 2720 exit(1); 2721 } 2722 2723 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2724 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2725 2726 /* 2727 * VSMT must be set in order to be able to compute VCPU ids, ie to 2728 * call spapr_max_server_number() or spapr_vcpu_id(). 2729 */ 2730 spapr_set_vsmt_mode(spapr, &error_fatal); 2731 2732 /* Set up Interrupt Controller before we create the VCPUs */ 2733 spapr_irq_init(spapr, &error_fatal); 2734 2735 /* Set up containers for ibm,client-architecture-support negotiated options 2736 */ 2737 spapr->ov5 = spapr_ovec_new(); 2738 spapr->ov5_cas = spapr_ovec_new(); 2739 2740 if (smc->dr_lmb_enabled) { 2741 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2742 spapr_validate_node_memory(machine, &error_fatal); 2743 } 2744 2745 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2746 2747 /* advertise support for dedicated HP event source to guests */ 2748 if (spapr->use_hotplug_event_source) { 2749 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2750 } 2751 2752 /* advertise support for HPT resizing */ 2753 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2754 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2755 } 2756 2757 /* advertise support for ibm,dyamic-memory-v2 */ 2758 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2759 2760 /* advertise XIVE on POWER9 machines */ 2761 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { 2762 if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 2763 0, spapr->max_compat_pvr)) { 2764 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2765 } else if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { 2766 error_report("XIVE-only machines require a POWER9 CPU"); 2767 exit(1); 2768 } 2769 } 2770 2771 /* init CPUs */ 2772 spapr_init_cpus(spapr); 2773 2774 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2775 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2776 spapr->max_compat_pvr)) { 2777 /* KVM and TCG always allow GTSE with radix... */ 2778 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2779 } 2780 /* ... but not with hash (currently). */ 2781 2782 if (kvm_enabled()) { 2783 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2784 kvmppc_enable_logical_ci_hcalls(); 2785 kvmppc_enable_set_mode_hcall(); 2786 2787 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2788 kvmppc_enable_clear_ref_mod_hcalls(); 2789 } 2790 2791 /* allocate RAM */ 2792 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2793 machine->ram_size); 2794 memory_region_add_subregion(sysmem, 0, ram); 2795 2796 /* always allocate the device memory information */ 2797 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2798 2799 /* initialize hotplug memory address space */ 2800 if (machine->ram_size < machine->maxram_size) { 2801 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2802 /* 2803 * Limit the number of hotpluggable memory slots to half the number 2804 * slots that KVM supports, leaving the other half for PCI and other 2805 * devices. However ensure that number of slots doesn't drop below 32. 2806 */ 2807 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2808 SPAPR_MAX_RAM_SLOTS; 2809 2810 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2811 max_memslots = SPAPR_MAX_RAM_SLOTS; 2812 } 2813 if (machine->ram_slots > max_memslots) { 2814 error_report("Specified number of memory slots %" 2815 PRIu64" exceeds max supported %d", 2816 machine->ram_slots, max_memslots); 2817 exit(1); 2818 } 2819 2820 machine->device_memory->base = ROUND_UP(machine->ram_size, 2821 SPAPR_DEVICE_MEM_ALIGN); 2822 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2823 "device-memory", device_mem_size); 2824 memory_region_add_subregion(sysmem, machine->device_memory->base, 2825 &machine->device_memory->mr); 2826 } 2827 2828 if (smc->dr_lmb_enabled) { 2829 spapr_create_lmb_dr_connectors(spapr); 2830 } 2831 2832 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2833 if (!filename) { 2834 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2835 exit(1); 2836 } 2837 spapr->rtas_size = get_image_size(filename); 2838 if (spapr->rtas_size < 0) { 2839 error_report("Could not get size of LPAR rtas '%s'", filename); 2840 exit(1); 2841 } 2842 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2843 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2844 error_report("Could not load LPAR rtas '%s'", filename); 2845 exit(1); 2846 } 2847 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2848 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2849 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2850 exit(1); 2851 } 2852 g_free(filename); 2853 2854 /* Set up RTAS event infrastructure */ 2855 spapr_events_init(spapr); 2856 2857 /* Set up the RTC RTAS interfaces */ 2858 spapr_rtc_create(spapr); 2859 2860 /* Set up VIO bus */ 2861 spapr->vio_bus = spapr_vio_bus_init(); 2862 2863 for (i = 0; i < serial_max_hds(); i++) { 2864 if (serial_hd(i)) { 2865 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2866 } 2867 } 2868 2869 /* We always have at least the nvram device on VIO */ 2870 spapr_create_nvram(spapr); 2871 2872 /* Set up PCI */ 2873 spapr_pci_rtas_init(); 2874 2875 phb = spapr_create_default_phb(); 2876 2877 for (i = 0; i < nb_nics; i++) { 2878 NICInfo *nd = &nd_table[i]; 2879 2880 if (!nd->model) { 2881 nd->model = g_strdup("spapr-vlan"); 2882 } 2883 2884 if (g_str_equal(nd->model, "spapr-vlan") || 2885 g_str_equal(nd->model, "ibmveth")) { 2886 spapr_vlan_create(spapr->vio_bus, nd); 2887 } else { 2888 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2889 } 2890 } 2891 2892 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2893 spapr_vscsi_create(spapr->vio_bus); 2894 } 2895 2896 /* Graphics */ 2897 if (spapr_vga_init(phb->bus, &error_fatal)) { 2898 spapr->has_graphics = true; 2899 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2900 } 2901 2902 if (machine->usb) { 2903 if (smc->use_ohci_by_default) { 2904 pci_create_simple(phb->bus, -1, "pci-ohci"); 2905 } else { 2906 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2907 } 2908 2909 if (spapr->has_graphics) { 2910 USBBus *usb_bus = usb_bus_find(-1); 2911 2912 usb_create_simple(usb_bus, "usb-kbd"); 2913 usb_create_simple(usb_bus, "usb-mouse"); 2914 } 2915 } 2916 2917 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2918 error_report( 2919 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2920 MIN_RMA_SLOF); 2921 exit(1); 2922 } 2923 2924 if (kernel_filename) { 2925 uint64_t lowaddr = 0; 2926 2927 spapr->kernel_size = load_elf(kernel_filename, NULL, 2928 translate_kernel_address, NULL, 2929 NULL, &lowaddr, NULL, 1, 2930 PPC_ELF_MACHINE, 0, 0); 2931 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2932 spapr->kernel_size = load_elf(kernel_filename, NULL, 2933 translate_kernel_address, NULL, NULL, 2934 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2935 0, 0); 2936 spapr->kernel_le = spapr->kernel_size > 0; 2937 } 2938 if (spapr->kernel_size < 0) { 2939 error_report("error loading %s: %s", kernel_filename, 2940 load_elf_strerror(spapr->kernel_size)); 2941 exit(1); 2942 } 2943 2944 /* load initrd */ 2945 if (initrd_filename) { 2946 /* Try to locate the initrd in the gap between the kernel 2947 * and the firmware. Add a bit of space just in case 2948 */ 2949 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2950 + 0x1ffff) & ~0xffff; 2951 spapr->initrd_size = load_image_targphys(initrd_filename, 2952 spapr->initrd_base, 2953 load_limit 2954 - spapr->initrd_base); 2955 if (spapr->initrd_size < 0) { 2956 error_report("could not load initial ram disk '%s'", 2957 initrd_filename); 2958 exit(1); 2959 } 2960 } 2961 } 2962 2963 if (bios_name == NULL) { 2964 bios_name = FW_FILE_NAME; 2965 } 2966 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2967 if (!filename) { 2968 error_report("Could not find LPAR firmware '%s'", bios_name); 2969 exit(1); 2970 } 2971 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2972 if (fw_size <= 0) { 2973 error_report("Could not load LPAR firmware '%s'", filename); 2974 exit(1); 2975 } 2976 g_free(filename); 2977 2978 /* FIXME: Should register things through the MachineState's qdev 2979 * interface, this is a legacy from the sPAPREnvironment structure 2980 * which predated MachineState but had a similar function */ 2981 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2982 register_savevm_live(NULL, "spapr/htab", -1, 1, 2983 &savevm_htab_handlers, spapr); 2984 2985 qemu_register_boot_set(spapr_boot_set, spapr); 2986 2987 if (kvm_enabled()) { 2988 /* to stop and start vmclock */ 2989 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2990 &spapr->tb); 2991 2992 kvmppc_spapr_enable_inkernel_multitce(); 2993 } 2994 } 2995 2996 static int spapr_kvm_type(const char *vm_type) 2997 { 2998 if (!vm_type) { 2999 return 0; 3000 } 3001 3002 if (!strcmp(vm_type, "HV")) { 3003 return 1; 3004 } 3005 3006 if (!strcmp(vm_type, "PR")) { 3007 return 2; 3008 } 3009 3010 error_report("Unknown kvm-type specified '%s'", vm_type); 3011 exit(1); 3012 } 3013 3014 /* 3015 * Implementation of an interface to adjust firmware path 3016 * for the bootindex property handling. 3017 */ 3018 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3019 DeviceState *dev) 3020 { 3021 #define CAST(type, obj, name) \ 3022 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3023 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3024 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3025 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3026 3027 if (d) { 3028 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3029 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3030 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3031 3032 if (spapr) { 3033 /* 3034 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3035 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3036 * 0x8000 | (target << 8) | (bus << 5) | lun 3037 * (see the "Logical unit addressing format" table in SAM5) 3038 */ 3039 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3040 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3041 (uint64_t)id << 48); 3042 } else if (virtio) { 3043 /* 3044 * We use SRP luns of the form 01000000 | (target << 8) | lun 3045 * in the top 32 bits of the 64-bit LUN 3046 * Note: the quote above is from SLOF and it is wrong, 3047 * the actual binding is: 3048 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3049 */ 3050 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3051 if (d->lun >= 256) { 3052 /* Use the LUN "flat space addressing method" */ 3053 id |= 0x4000; 3054 } 3055 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3056 (uint64_t)id << 32); 3057 } else if (usb) { 3058 /* 3059 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3060 * in the top 32 bits of the 64-bit LUN 3061 */ 3062 unsigned usb_port = atoi(usb->port->path); 3063 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3064 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3065 (uint64_t)id << 32); 3066 } 3067 } 3068 3069 /* 3070 * SLOF probes the USB devices, and if it recognizes that the device is a 3071 * storage device, it changes its name to "storage" instead of "usb-host", 3072 * and additionally adds a child node for the SCSI LUN, so the correct 3073 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3074 */ 3075 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3076 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3077 if (usb_host_dev_is_scsi_storage(usbdev)) { 3078 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3079 } 3080 } 3081 3082 if (phb) { 3083 /* Replace "pci" with "pci@800000020000000" */ 3084 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3085 } 3086 3087 if (vsc) { 3088 /* Same logic as virtio above */ 3089 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3090 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3091 } 3092 3093 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3094 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3095 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3096 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3097 } 3098 3099 return NULL; 3100 } 3101 3102 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3103 { 3104 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3105 3106 return g_strdup(spapr->kvm_type); 3107 } 3108 3109 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3110 { 3111 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3112 3113 g_free(spapr->kvm_type); 3114 spapr->kvm_type = g_strdup(value); 3115 } 3116 3117 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3118 { 3119 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3120 3121 return spapr->use_hotplug_event_source; 3122 } 3123 3124 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3125 Error **errp) 3126 { 3127 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3128 3129 spapr->use_hotplug_event_source = value; 3130 } 3131 3132 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3133 { 3134 return true; 3135 } 3136 3137 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3138 { 3139 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3140 3141 switch (spapr->resize_hpt) { 3142 case SPAPR_RESIZE_HPT_DEFAULT: 3143 return g_strdup("default"); 3144 case SPAPR_RESIZE_HPT_DISABLED: 3145 return g_strdup("disabled"); 3146 case SPAPR_RESIZE_HPT_ENABLED: 3147 return g_strdup("enabled"); 3148 case SPAPR_RESIZE_HPT_REQUIRED: 3149 return g_strdup("required"); 3150 } 3151 g_assert_not_reached(); 3152 } 3153 3154 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3155 { 3156 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3157 3158 if (strcmp(value, "default") == 0) { 3159 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3160 } else if (strcmp(value, "disabled") == 0) { 3161 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3162 } else if (strcmp(value, "enabled") == 0) { 3163 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3164 } else if (strcmp(value, "required") == 0) { 3165 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3166 } else { 3167 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3168 } 3169 } 3170 3171 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3172 void *opaque, Error **errp) 3173 { 3174 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3175 } 3176 3177 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3178 void *opaque, Error **errp) 3179 { 3180 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3181 } 3182 3183 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3184 { 3185 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3186 3187 if (spapr->irq == &spapr_irq_xics_legacy) { 3188 return g_strdup("legacy"); 3189 } else if (spapr->irq == &spapr_irq_xics) { 3190 return g_strdup("xics"); 3191 } else if (spapr->irq == &spapr_irq_xive) { 3192 return g_strdup("xive"); 3193 } else if (spapr->irq == &spapr_irq_dual) { 3194 return g_strdup("dual"); 3195 } 3196 g_assert_not_reached(); 3197 } 3198 3199 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3200 { 3201 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3202 3203 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3204 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3205 return; 3206 } 3207 3208 /* The legacy IRQ backend can not be set */ 3209 if (strcmp(value, "xics") == 0) { 3210 spapr->irq = &spapr_irq_xics; 3211 } else if (strcmp(value, "xive") == 0) { 3212 spapr->irq = &spapr_irq_xive; 3213 } else if (strcmp(value, "dual") == 0) { 3214 spapr->irq = &spapr_irq_dual; 3215 } else { 3216 error_setg(errp, "Bad value for \"ic-mode\" property"); 3217 } 3218 } 3219 3220 static char *spapr_get_host_model(Object *obj, Error **errp) 3221 { 3222 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3223 3224 return g_strdup(spapr->host_model); 3225 } 3226 3227 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3228 { 3229 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3230 3231 g_free(spapr->host_model); 3232 spapr->host_model = g_strdup(value); 3233 } 3234 3235 static char *spapr_get_host_serial(Object *obj, Error **errp) 3236 { 3237 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3238 3239 return g_strdup(spapr->host_serial); 3240 } 3241 3242 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3243 { 3244 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3245 3246 g_free(spapr->host_serial); 3247 spapr->host_serial = g_strdup(value); 3248 } 3249 3250 static void spapr_instance_init(Object *obj) 3251 { 3252 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3253 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3254 3255 spapr->htab_fd = -1; 3256 spapr->use_hotplug_event_source = true; 3257 object_property_add_str(obj, "kvm-type", 3258 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3259 object_property_set_description(obj, "kvm-type", 3260 "Specifies the KVM virtualization mode (HV, PR)", 3261 NULL); 3262 object_property_add_bool(obj, "modern-hotplug-events", 3263 spapr_get_modern_hotplug_events, 3264 spapr_set_modern_hotplug_events, 3265 NULL); 3266 object_property_set_description(obj, "modern-hotplug-events", 3267 "Use dedicated hotplug event mechanism in" 3268 " place of standard EPOW events when possible" 3269 " (required for memory hot-unplug support)", 3270 NULL); 3271 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3272 "Maximum permitted CPU compatibility mode", 3273 &error_fatal); 3274 3275 object_property_add_str(obj, "resize-hpt", 3276 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3277 object_property_set_description(obj, "resize-hpt", 3278 "Resizing of the Hash Page Table (enabled, disabled, required)", 3279 NULL); 3280 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3281 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3282 object_property_set_description(obj, "vsmt", 3283 "Virtual SMT: KVM behaves as if this were" 3284 " the host's SMT mode", &error_abort); 3285 object_property_add_bool(obj, "vfio-no-msix-emulation", 3286 spapr_get_msix_emulation, NULL, NULL); 3287 3288 /* The machine class defines the default interrupt controller mode */ 3289 spapr->irq = smc->irq; 3290 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3291 spapr_set_ic_mode, NULL); 3292 object_property_set_description(obj, "ic-mode", 3293 "Specifies the interrupt controller mode (xics, xive, dual)", 3294 NULL); 3295 3296 object_property_add_str(obj, "host-model", 3297 spapr_get_host_model, spapr_set_host_model, 3298 &error_abort); 3299 object_property_set_description(obj, "host-model", 3300 "Set host's model-id to use - none|passthrough|string", &error_abort); 3301 object_property_add_str(obj, "host-serial", 3302 spapr_get_host_serial, spapr_set_host_serial, 3303 &error_abort); 3304 object_property_set_description(obj, "host-serial", 3305 "Set host's system-id to use - none|passthrough|string", &error_abort); 3306 } 3307 3308 static void spapr_machine_finalizefn(Object *obj) 3309 { 3310 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3311 3312 g_free(spapr->kvm_type); 3313 } 3314 3315 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3316 { 3317 cpu_synchronize_state(cs); 3318 ppc_cpu_do_system_reset(cs); 3319 } 3320 3321 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3322 { 3323 CPUState *cs; 3324 3325 CPU_FOREACH(cs) { 3326 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3327 } 3328 } 3329 3330 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3331 uint32_t node, bool dedicated_hp_event_source, 3332 Error **errp) 3333 { 3334 sPAPRDRConnector *drc; 3335 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3336 int i, fdt_offset, fdt_size; 3337 void *fdt; 3338 uint64_t addr = addr_start; 3339 bool hotplugged = spapr_drc_hotplugged(dev); 3340 Error *local_err = NULL; 3341 3342 for (i = 0; i < nr_lmbs; i++) { 3343 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3344 addr / SPAPR_MEMORY_BLOCK_SIZE); 3345 g_assert(drc); 3346 3347 fdt = create_device_tree(&fdt_size); 3348 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3349 SPAPR_MEMORY_BLOCK_SIZE); 3350 3351 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3352 if (local_err) { 3353 while (addr > addr_start) { 3354 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3355 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3356 addr / SPAPR_MEMORY_BLOCK_SIZE); 3357 spapr_drc_detach(drc); 3358 } 3359 g_free(fdt); 3360 error_propagate(errp, local_err); 3361 return; 3362 } 3363 if (!hotplugged) { 3364 spapr_drc_reset(drc); 3365 } 3366 addr += SPAPR_MEMORY_BLOCK_SIZE; 3367 } 3368 /* send hotplug notification to the 3369 * guest only in case of hotplugged memory 3370 */ 3371 if (hotplugged) { 3372 if (dedicated_hp_event_source) { 3373 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3374 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3375 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3376 nr_lmbs, 3377 spapr_drc_index(drc)); 3378 } else { 3379 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3380 nr_lmbs); 3381 } 3382 } 3383 } 3384 3385 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3386 Error **errp) 3387 { 3388 Error *local_err = NULL; 3389 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3390 PCDIMMDevice *dimm = PC_DIMM(dev); 3391 uint64_t size, addr; 3392 uint32_t node; 3393 3394 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3395 3396 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3397 if (local_err) { 3398 goto out; 3399 } 3400 3401 addr = object_property_get_uint(OBJECT(dimm), 3402 PC_DIMM_ADDR_PROP, &local_err); 3403 if (local_err) { 3404 goto out_unplug; 3405 } 3406 3407 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3408 &error_abort); 3409 spapr_add_lmbs(dev, addr, size, node, 3410 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3411 &local_err); 3412 if (local_err) { 3413 goto out_unplug; 3414 } 3415 3416 return; 3417 3418 out_unplug: 3419 pc_dimm_unplug(dimm, MACHINE(ms)); 3420 out: 3421 error_propagate(errp, local_err); 3422 } 3423 3424 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3425 Error **errp) 3426 { 3427 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3428 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3429 PCDIMMDevice *dimm = PC_DIMM(dev); 3430 Error *local_err = NULL; 3431 uint64_t size; 3432 Object *memdev; 3433 hwaddr pagesize; 3434 3435 if (!smc->dr_lmb_enabled) { 3436 error_setg(errp, "Memory hotplug not supported for this machine"); 3437 return; 3438 } 3439 3440 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3441 if (local_err) { 3442 error_propagate(errp, local_err); 3443 return; 3444 } 3445 3446 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3447 error_setg(errp, "Hotplugged memory size must be a multiple of " 3448 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3449 return; 3450 } 3451 3452 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3453 &error_abort); 3454 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3455 spapr_check_pagesize(spapr, pagesize, &local_err); 3456 if (local_err) { 3457 error_propagate(errp, local_err); 3458 return; 3459 } 3460 3461 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3462 } 3463 3464 struct sPAPRDIMMState { 3465 PCDIMMDevice *dimm; 3466 uint32_t nr_lmbs; 3467 QTAILQ_ENTRY(sPAPRDIMMState) next; 3468 }; 3469 3470 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3471 PCDIMMDevice *dimm) 3472 { 3473 sPAPRDIMMState *dimm_state = NULL; 3474 3475 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3476 if (dimm_state->dimm == dimm) { 3477 break; 3478 } 3479 } 3480 return dimm_state; 3481 } 3482 3483 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3484 uint32_t nr_lmbs, 3485 PCDIMMDevice *dimm) 3486 { 3487 sPAPRDIMMState *ds = NULL; 3488 3489 /* 3490 * If this request is for a DIMM whose removal had failed earlier 3491 * (due to guest's refusal to remove the LMBs), we would have this 3492 * dimm already in the pending_dimm_unplugs list. In that 3493 * case don't add again. 3494 */ 3495 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3496 if (!ds) { 3497 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3498 ds->nr_lmbs = nr_lmbs; 3499 ds->dimm = dimm; 3500 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3501 } 3502 return ds; 3503 } 3504 3505 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3506 sPAPRDIMMState *dimm_state) 3507 { 3508 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3509 g_free(dimm_state); 3510 } 3511 3512 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3513 PCDIMMDevice *dimm) 3514 { 3515 sPAPRDRConnector *drc; 3516 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3517 &error_abort); 3518 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3519 uint32_t avail_lmbs = 0; 3520 uint64_t addr_start, addr; 3521 int i; 3522 3523 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3524 &error_abort); 3525 3526 addr = addr_start; 3527 for (i = 0; i < nr_lmbs; i++) { 3528 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3529 addr / SPAPR_MEMORY_BLOCK_SIZE); 3530 g_assert(drc); 3531 if (drc->dev) { 3532 avail_lmbs++; 3533 } 3534 addr += SPAPR_MEMORY_BLOCK_SIZE; 3535 } 3536 3537 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3538 } 3539 3540 /* Callback to be called during DRC release. */ 3541 void spapr_lmb_release(DeviceState *dev) 3542 { 3543 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3544 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3545 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3546 3547 /* This information will get lost if a migration occurs 3548 * during the unplug process. In this case recover it. */ 3549 if (ds == NULL) { 3550 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3551 g_assert(ds); 3552 /* The DRC being examined by the caller at least must be counted */ 3553 g_assert(ds->nr_lmbs); 3554 } 3555 3556 if (--ds->nr_lmbs) { 3557 return; 3558 } 3559 3560 /* 3561 * Now that all the LMBs have been removed by the guest, call the 3562 * unplug handler chain. This can never fail. 3563 */ 3564 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3565 } 3566 3567 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3568 { 3569 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3570 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3571 3572 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3573 object_unparent(OBJECT(dev)); 3574 spapr_pending_dimm_unplugs_remove(spapr, ds); 3575 } 3576 3577 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3578 DeviceState *dev, Error **errp) 3579 { 3580 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3581 Error *local_err = NULL; 3582 PCDIMMDevice *dimm = PC_DIMM(dev); 3583 uint32_t nr_lmbs; 3584 uint64_t size, addr_start, addr; 3585 int i; 3586 sPAPRDRConnector *drc; 3587 3588 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3589 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3590 3591 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3592 &local_err); 3593 if (local_err) { 3594 goto out; 3595 } 3596 3597 /* 3598 * An existing pending dimm state for this DIMM means that there is an 3599 * unplug operation in progress, waiting for the spapr_lmb_release 3600 * callback to complete the job (BQL can't cover that far). In this case, 3601 * bail out to avoid detaching DRCs that were already released. 3602 */ 3603 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3604 error_setg(&local_err, 3605 "Memory unplug already in progress for device %s", 3606 dev->id); 3607 goto out; 3608 } 3609 3610 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3611 3612 addr = addr_start; 3613 for (i = 0; i < nr_lmbs; i++) { 3614 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3615 addr / SPAPR_MEMORY_BLOCK_SIZE); 3616 g_assert(drc); 3617 3618 spapr_drc_detach(drc); 3619 addr += SPAPR_MEMORY_BLOCK_SIZE; 3620 } 3621 3622 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3623 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3624 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3625 nr_lmbs, spapr_drc_index(drc)); 3626 out: 3627 error_propagate(errp, local_err); 3628 } 3629 3630 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3631 sPAPRMachineState *spapr) 3632 { 3633 PowerPCCPU *cpu = POWERPC_CPU(cs); 3634 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3635 int id = spapr_get_vcpu_id(cpu); 3636 void *fdt; 3637 int offset, fdt_size; 3638 char *nodename; 3639 3640 fdt = create_device_tree(&fdt_size); 3641 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3642 offset = fdt_add_subnode(fdt, 0, nodename); 3643 3644 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3645 g_free(nodename); 3646 3647 *fdt_offset = offset; 3648 return fdt; 3649 } 3650 3651 /* Callback to be called during DRC release. */ 3652 void spapr_core_release(DeviceState *dev) 3653 { 3654 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3655 3656 /* Call the unplug handler chain. This can never fail. */ 3657 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3658 } 3659 3660 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3661 { 3662 MachineState *ms = MACHINE(hotplug_dev); 3663 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3664 CPUCore *cc = CPU_CORE(dev); 3665 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3666 3667 if (smc->pre_2_10_has_unused_icps) { 3668 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3669 int i; 3670 3671 for (i = 0; i < cc->nr_threads; i++) { 3672 CPUState *cs = CPU(sc->threads[i]); 3673 3674 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3675 } 3676 } 3677 3678 assert(core_slot); 3679 core_slot->cpu = NULL; 3680 object_unparent(OBJECT(dev)); 3681 } 3682 3683 static 3684 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3685 Error **errp) 3686 { 3687 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3688 int index; 3689 sPAPRDRConnector *drc; 3690 CPUCore *cc = CPU_CORE(dev); 3691 3692 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3693 error_setg(errp, "Unable to find CPU core with core-id: %d", 3694 cc->core_id); 3695 return; 3696 } 3697 if (index == 0) { 3698 error_setg(errp, "Boot CPU core may not be unplugged"); 3699 return; 3700 } 3701 3702 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3703 spapr_vcpu_id(spapr, cc->core_id)); 3704 g_assert(drc); 3705 3706 spapr_drc_detach(drc); 3707 3708 spapr_hotplug_req_remove_by_index(drc); 3709 } 3710 3711 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3712 Error **errp) 3713 { 3714 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3715 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3716 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3717 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3718 CPUCore *cc = CPU_CORE(dev); 3719 CPUState *cs = CPU(core->threads[0]); 3720 sPAPRDRConnector *drc; 3721 Error *local_err = NULL; 3722 CPUArchId *core_slot; 3723 int index; 3724 bool hotplugged = spapr_drc_hotplugged(dev); 3725 3726 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3727 if (!core_slot) { 3728 error_setg(errp, "Unable to find CPU core with core-id: %d", 3729 cc->core_id); 3730 return; 3731 } 3732 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3733 spapr_vcpu_id(spapr, cc->core_id)); 3734 3735 g_assert(drc || !mc->has_hotpluggable_cpus); 3736 3737 if (drc) { 3738 void *fdt; 3739 int fdt_offset; 3740 3741 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3742 3743 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3744 if (local_err) { 3745 g_free(fdt); 3746 error_propagate(errp, local_err); 3747 return; 3748 } 3749 3750 if (hotplugged) { 3751 /* 3752 * Send hotplug notification interrupt to the guest only 3753 * in case of hotplugged CPUs. 3754 */ 3755 spapr_hotplug_req_add_by_index(drc); 3756 } else { 3757 spapr_drc_reset(drc); 3758 } 3759 } 3760 3761 core_slot->cpu = OBJECT(dev); 3762 3763 if (smc->pre_2_10_has_unused_icps) { 3764 int i; 3765 3766 for (i = 0; i < cc->nr_threads; i++) { 3767 cs = CPU(core->threads[i]); 3768 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3769 } 3770 } 3771 } 3772 3773 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3774 Error **errp) 3775 { 3776 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3777 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3778 Error *local_err = NULL; 3779 CPUCore *cc = CPU_CORE(dev); 3780 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3781 const char *type = object_get_typename(OBJECT(dev)); 3782 CPUArchId *core_slot; 3783 int index; 3784 3785 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3786 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3787 goto out; 3788 } 3789 3790 if (strcmp(base_core_type, type)) { 3791 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3792 goto out; 3793 } 3794 3795 if (cc->core_id % smp_threads) { 3796 error_setg(&local_err, "invalid core id %d", cc->core_id); 3797 goto out; 3798 } 3799 3800 /* 3801 * In general we should have homogeneous threads-per-core, but old 3802 * (pre hotplug support) machine types allow the last core to have 3803 * reduced threads as a compatibility hack for when we allowed 3804 * total vcpus not a multiple of threads-per-core. 3805 */ 3806 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3807 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3808 cc->nr_threads, smp_threads); 3809 goto out; 3810 } 3811 3812 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3813 if (!core_slot) { 3814 error_setg(&local_err, "core id %d out of range", cc->core_id); 3815 goto out; 3816 } 3817 3818 if (core_slot->cpu) { 3819 error_setg(&local_err, "core %d already populated", cc->core_id); 3820 goto out; 3821 } 3822 3823 numa_cpu_pre_plug(core_slot, dev, &local_err); 3824 3825 out: 3826 error_propagate(errp, local_err); 3827 } 3828 3829 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3830 DeviceState *dev, Error **errp) 3831 { 3832 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3833 spapr_memory_plug(hotplug_dev, dev, errp); 3834 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3835 spapr_core_plug(hotplug_dev, dev, errp); 3836 } 3837 } 3838 3839 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3840 DeviceState *dev, Error **errp) 3841 { 3842 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3843 spapr_memory_unplug(hotplug_dev, dev); 3844 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3845 spapr_core_unplug(hotplug_dev, dev); 3846 } 3847 } 3848 3849 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3850 DeviceState *dev, Error **errp) 3851 { 3852 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3853 MachineClass *mc = MACHINE_GET_CLASS(sms); 3854 3855 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3856 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3857 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3858 } else { 3859 /* NOTE: this means there is a window after guest reset, prior to 3860 * CAS negotiation, where unplug requests will fail due to the 3861 * capability not being detected yet. This is a bit different than 3862 * the case with PCI unplug, where the events will be queued and 3863 * eventually handled by the guest after boot 3864 */ 3865 error_setg(errp, "Memory hot unplug not supported for this guest"); 3866 } 3867 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3868 if (!mc->has_hotpluggable_cpus) { 3869 error_setg(errp, "CPU hot unplug not supported on this machine"); 3870 return; 3871 } 3872 spapr_core_unplug_request(hotplug_dev, dev, errp); 3873 } 3874 } 3875 3876 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3877 DeviceState *dev, Error **errp) 3878 { 3879 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3880 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3881 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3882 spapr_core_pre_plug(hotplug_dev, dev, errp); 3883 } 3884 } 3885 3886 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3887 DeviceState *dev) 3888 { 3889 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3890 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3891 return HOTPLUG_HANDLER(machine); 3892 } 3893 return NULL; 3894 } 3895 3896 static CpuInstanceProperties 3897 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3898 { 3899 CPUArchId *core_slot; 3900 MachineClass *mc = MACHINE_GET_CLASS(machine); 3901 3902 /* make sure possible_cpu are intialized */ 3903 mc->possible_cpu_arch_ids(machine); 3904 /* get CPU core slot containing thread that matches cpu_index */ 3905 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3906 assert(core_slot); 3907 return core_slot->props; 3908 } 3909 3910 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3911 { 3912 return idx / smp_cores % nb_numa_nodes; 3913 } 3914 3915 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3916 { 3917 int i; 3918 const char *core_type; 3919 int spapr_max_cores = max_cpus / smp_threads; 3920 MachineClass *mc = MACHINE_GET_CLASS(machine); 3921 3922 if (!mc->has_hotpluggable_cpus) { 3923 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3924 } 3925 if (machine->possible_cpus) { 3926 assert(machine->possible_cpus->len == spapr_max_cores); 3927 return machine->possible_cpus; 3928 } 3929 3930 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3931 if (!core_type) { 3932 error_report("Unable to find sPAPR CPU Core definition"); 3933 exit(1); 3934 } 3935 3936 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3937 sizeof(CPUArchId) * spapr_max_cores); 3938 machine->possible_cpus->len = spapr_max_cores; 3939 for (i = 0; i < machine->possible_cpus->len; i++) { 3940 int core_id = i * smp_threads; 3941 3942 machine->possible_cpus->cpus[i].type = core_type; 3943 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3944 machine->possible_cpus->cpus[i].arch_id = core_id; 3945 machine->possible_cpus->cpus[i].props.has_core_id = true; 3946 machine->possible_cpus->cpus[i].props.core_id = core_id; 3947 } 3948 return machine->possible_cpus; 3949 } 3950 3951 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3952 uint64_t *buid, hwaddr *pio, 3953 hwaddr *mmio32, hwaddr *mmio64, 3954 unsigned n_dma, uint32_t *liobns, Error **errp) 3955 { 3956 /* 3957 * New-style PHB window placement. 3958 * 3959 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3960 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3961 * windows. 3962 * 3963 * Some guest kernels can't work with MMIO windows above 1<<46 3964 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3965 * 3966 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3967 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3968 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3969 * 1TiB 64-bit MMIO windows for each PHB. 3970 */ 3971 const uint64_t base_buid = 0x800000020000000ULL; 3972 int i; 3973 3974 /* Sanity check natural alignments */ 3975 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3976 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3977 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3978 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3979 /* Sanity check bounds */ 3980 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3981 SPAPR_PCI_MEM32_WIN_SIZE); 3982 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3983 SPAPR_PCI_MEM64_WIN_SIZE); 3984 3985 if (index >= SPAPR_MAX_PHBS) { 3986 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3987 SPAPR_MAX_PHBS - 1); 3988 return; 3989 } 3990 3991 *buid = base_buid + index; 3992 for (i = 0; i < n_dma; ++i) { 3993 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3994 } 3995 3996 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3997 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3998 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3999 } 4000 4001 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4002 { 4003 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 4004 4005 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4006 } 4007 4008 static void spapr_ics_resend(XICSFabric *dev) 4009 { 4010 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 4011 4012 ics_resend(spapr->ics); 4013 } 4014 4015 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4016 { 4017 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4018 4019 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4020 } 4021 4022 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4023 Monitor *mon) 4024 { 4025 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 4026 4027 spapr->irq->print_info(spapr, mon); 4028 } 4029 4030 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4031 { 4032 return cpu->vcpu_id; 4033 } 4034 4035 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4036 { 4037 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4038 int vcpu_id; 4039 4040 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4041 4042 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4043 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4044 error_append_hint(errp, "Adjust the number of cpus to %d " 4045 "or try to raise the number of threads per core\n", 4046 vcpu_id * smp_threads / spapr->vsmt); 4047 return; 4048 } 4049 4050 cpu->vcpu_id = vcpu_id; 4051 } 4052 4053 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4054 { 4055 CPUState *cs; 4056 4057 CPU_FOREACH(cs) { 4058 PowerPCCPU *cpu = POWERPC_CPU(cs); 4059 4060 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4061 return cpu; 4062 } 4063 } 4064 4065 return NULL; 4066 } 4067 4068 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4069 { 4070 MachineClass *mc = MACHINE_CLASS(oc); 4071 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4072 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4073 NMIClass *nc = NMI_CLASS(oc); 4074 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4075 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4076 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4077 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4078 4079 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4080 mc->ignore_boot_device_suffixes = true; 4081 4082 /* 4083 * We set up the default / latest behaviour here. The class_init 4084 * functions for the specific versioned machine types can override 4085 * these details for backwards compatibility 4086 */ 4087 mc->init = spapr_machine_init; 4088 mc->reset = spapr_machine_reset; 4089 mc->block_default_type = IF_SCSI; 4090 mc->max_cpus = 1024; 4091 mc->no_parallel = 1; 4092 mc->default_boot_order = ""; 4093 mc->default_ram_size = 512 * MiB; 4094 mc->default_display = "std"; 4095 mc->kvm_type = spapr_kvm_type; 4096 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4097 mc->pci_allow_0_address = true; 4098 assert(!mc->get_hotplug_handler); 4099 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4100 hc->pre_plug = spapr_machine_device_pre_plug; 4101 hc->plug = spapr_machine_device_plug; 4102 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4103 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4104 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4105 hc->unplug_request = spapr_machine_device_unplug_request; 4106 hc->unplug = spapr_machine_device_unplug; 4107 4108 smc->dr_lmb_enabled = true; 4109 smc->update_dt_enabled = true; 4110 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4111 mc->has_hotpluggable_cpus = true; 4112 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4113 fwc->get_dev_path = spapr_get_fw_dev_path; 4114 nc->nmi_monitor_handler = spapr_nmi; 4115 smc->phb_placement = spapr_phb_placement; 4116 vhc->hypercall = emulate_spapr_hypercall; 4117 vhc->hpt_mask = spapr_hpt_mask; 4118 vhc->map_hptes = spapr_map_hptes; 4119 vhc->unmap_hptes = spapr_unmap_hptes; 4120 vhc->store_hpte = spapr_store_hpte; 4121 vhc->get_patbe = spapr_get_patbe; 4122 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4123 xic->ics_get = spapr_ics_get; 4124 xic->ics_resend = spapr_ics_resend; 4125 xic->icp_get = spapr_icp_get; 4126 ispc->print_info = spapr_pic_print_info; 4127 /* Force NUMA node memory size to be a multiple of 4128 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4129 * in which LMBs are represented and hot-added 4130 */ 4131 mc->numa_mem_align_shift = 28; 4132 4133 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4134 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4135 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4136 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4137 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4138 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4139 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4140 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4141 spapr_caps_add_properties(smc, &error_abort); 4142 smc->irq = &spapr_irq_xics; 4143 } 4144 4145 static const TypeInfo spapr_machine_info = { 4146 .name = TYPE_SPAPR_MACHINE, 4147 .parent = TYPE_MACHINE, 4148 .abstract = true, 4149 .instance_size = sizeof(sPAPRMachineState), 4150 .instance_init = spapr_instance_init, 4151 .instance_finalize = spapr_machine_finalizefn, 4152 .class_size = sizeof(sPAPRMachineClass), 4153 .class_init = spapr_machine_class_init, 4154 .interfaces = (InterfaceInfo[]) { 4155 { TYPE_FW_PATH_PROVIDER }, 4156 { TYPE_NMI }, 4157 { TYPE_HOTPLUG_HANDLER }, 4158 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4159 { TYPE_XICS_FABRIC }, 4160 { TYPE_INTERRUPT_STATS_PROVIDER }, 4161 { } 4162 }, 4163 }; 4164 4165 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4166 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4167 void *data) \ 4168 { \ 4169 MachineClass *mc = MACHINE_CLASS(oc); \ 4170 spapr_machine_##suffix##_class_options(mc); \ 4171 if (latest) { \ 4172 mc->alias = "pseries"; \ 4173 mc->is_default = 1; \ 4174 } \ 4175 } \ 4176 static const TypeInfo spapr_machine_##suffix##_info = { \ 4177 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4178 .parent = TYPE_SPAPR_MACHINE, \ 4179 .class_init = spapr_machine_##suffix##_class_init, \ 4180 }; \ 4181 static void spapr_machine_register_##suffix(void) \ 4182 { \ 4183 type_register(&spapr_machine_##suffix##_info); \ 4184 } \ 4185 type_init(spapr_machine_register_##suffix) 4186 4187 /* 4188 * pseries-4.0 4189 */ 4190 static void spapr_machine_4_0_class_options(MachineClass *mc) 4191 { 4192 /* Defaults for the latest behaviour inherited from the base class */ 4193 } 4194 4195 DEFINE_SPAPR_MACHINE(4_0, "4.0", true); 4196 4197 /* 4198 * pseries-3.1 4199 */ 4200 static void spapr_machine_3_1_class_options(MachineClass *mc) 4201 { 4202 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4203 static GlobalProperty compat[] = { 4204 { TYPE_SPAPR_MACHINE, "host-model", "passthrough" }, 4205 { TYPE_SPAPR_MACHINE, "host-serial", "passthrough" }, 4206 }; 4207 4208 spapr_machine_4_0_class_options(mc); 4209 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4210 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4211 4212 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4213 smc->update_dt_enabled = false; 4214 } 4215 4216 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4217 4218 /* 4219 * pseries-3.0 4220 */ 4221 4222 static void spapr_machine_3_0_class_options(MachineClass *mc) 4223 { 4224 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4225 4226 spapr_machine_3_1_class_options(mc); 4227 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4228 4229 smc->legacy_irq_allocation = true; 4230 smc->irq = &spapr_irq_xics_legacy; 4231 } 4232 4233 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4234 4235 /* 4236 * pseries-2.12 4237 */ 4238 static void spapr_machine_2_12_class_options(MachineClass *mc) 4239 { 4240 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4241 static GlobalProperty compat[] = { 4242 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4243 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4244 }; 4245 4246 spapr_machine_3_0_class_options(mc); 4247 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4248 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4249 4250 /* We depend on kvm_enabled() to choose a default value for the 4251 * hpt-max-page-size capability. Of course we can't do it here 4252 * because this is too early and the HW accelerator isn't initialzed 4253 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4254 */ 4255 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4256 } 4257 4258 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4259 4260 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4261 { 4262 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4263 4264 spapr_machine_2_12_class_options(mc); 4265 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4266 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4267 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4268 } 4269 4270 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4271 4272 /* 4273 * pseries-2.11 4274 */ 4275 4276 static void spapr_machine_2_11_class_options(MachineClass *mc) 4277 { 4278 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4279 4280 spapr_machine_2_12_class_options(mc); 4281 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4282 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4283 } 4284 4285 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4286 4287 /* 4288 * pseries-2.10 4289 */ 4290 4291 static void spapr_machine_2_10_class_options(MachineClass *mc) 4292 { 4293 spapr_machine_2_11_class_options(mc); 4294 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4295 } 4296 4297 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4298 4299 /* 4300 * pseries-2.9 4301 */ 4302 4303 static void spapr_machine_2_9_class_options(MachineClass *mc) 4304 { 4305 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4306 static GlobalProperty compat[] = { 4307 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4308 }; 4309 4310 spapr_machine_2_10_class_options(mc); 4311 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4312 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4313 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4314 smc->pre_2_10_has_unused_icps = true; 4315 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4316 } 4317 4318 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4319 4320 /* 4321 * pseries-2.8 4322 */ 4323 4324 static void spapr_machine_2_8_class_options(MachineClass *mc) 4325 { 4326 static GlobalProperty compat[] = { 4327 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4328 }; 4329 4330 spapr_machine_2_9_class_options(mc); 4331 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4332 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4333 mc->numa_mem_align_shift = 23; 4334 } 4335 4336 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4337 4338 /* 4339 * pseries-2.7 4340 */ 4341 4342 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4343 uint64_t *buid, hwaddr *pio, 4344 hwaddr *mmio32, hwaddr *mmio64, 4345 unsigned n_dma, uint32_t *liobns, Error **errp) 4346 { 4347 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4348 const uint64_t base_buid = 0x800000020000000ULL; 4349 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4350 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4351 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4352 const uint32_t max_index = 255; 4353 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4354 4355 uint64_t ram_top = MACHINE(spapr)->ram_size; 4356 hwaddr phb0_base, phb_base; 4357 int i; 4358 4359 /* Do we have device memory? */ 4360 if (MACHINE(spapr)->maxram_size > ram_top) { 4361 /* Can't just use maxram_size, because there may be an 4362 * alignment gap between normal and device memory regions 4363 */ 4364 ram_top = MACHINE(spapr)->device_memory->base + 4365 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4366 } 4367 4368 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4369 4370 if (index > max_index) { 4371 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4372 max_index); 4373 return; 4374 } 4375 4376 *buid = base_buid + index; 4377 for (i = 0; i < n_dma; ++i) { 4378 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4379 } 4380 4381 phb_base = phb0_base + index * phb_spacing; 4382 *pio = phb_base + pio_offset; 4383 *mmio32 = phb_base + mmio_offset; 4384 /* 4385 * We don't set the 64-bit MMIO window, relying on the PHB's 4386 * fallback behaviour of automatically splitting a large "32-bit" 4387 * window into contiguous 32-bit and 64-bit windows 4388 */ 4389 } 4390 4391 static void spapr_machine_2_7_class_options(MachineClass *mc) 4392 { 4393 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4394 static GlobalProperty compat[] = { 4395 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4396 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4397 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4398 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4399 }; 4400 4401 spapr_machine_2_8_class_options(mc); 4402 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4403 mc->default_machine_opts = "modern-hotplug-events=off"; 4404 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4405 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4406 smc->phb_placement = phb_placement_2_7; 4407 } 4408 4409 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4410 4411 /* 4412 * pseries-2.6 4413 */ 4414 4415 static void spapr_machine_2_6_class_options(MachineClass *mc) 4416 { 4417 static GlobalProperty compat[] = { 4418 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4419 }; 4420 4421 spapr_machine_2_7_class_options(mc); 4422 mc->has_hotpluggable_cpus = false; 4423 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4424 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4425 } 4426 4427 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4428 4429 /* 4430 * pseries-2.5 4431 */ 4432 4433 static void spapr_machine_2_5_class_options(MachineClass *mc) 4434 { 4435 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4436 static GlobalProperty compat[] = { 4437 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4438 }; 4439 4440 spapr_machine_2_6_class_options(mc); 4441 smc->use_ohci_by_default = true; 4442 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4443 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4444 } 4445 4446 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4447 4448 /* 4449 * pseries-2.4 4450 */ 4451 4452 static void spapr_machine_2_4_class_options(MachineClass *mc) 4453 { 4454 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4455 4456 spapr_machine_2_5_class_options(mc); 4457 smc->dr_lmb_enabled = false; 4458 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4459 } 4460 4461 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4462 4463 /* 4464 * pseries-2.3 4465 */ 4466 4467 static void spapr_machine_2_3_class_options(MachineClass *mc) 4468 { 4469 static GlobalProperty compat[] = { 4470 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4471 }; 4472 spapr_machine_2_4_class_options(mc); 4473 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4474 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4475 } 4476 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4477 4478 /* 4479 * pseries-2.2 4480 */ 4481 4482 static void spapr_machine_2_2_class_options(MachineClass *mc) 4483 { 4484 static GlobalProperty compat[] = { 4485 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4486 }; 4487 4488 spapr_machine_2_3_class_options(mc); 4489 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4490 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4491 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4492 } 4493 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4494 4495 /* 4496 * pseries-2.1 4497 */ 4498 4499 static void spapr_machine_2_1_class_options(MachineClass *mc) 4500 { 4501 spapr_machine_2_2_class_options(mc); 4502 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4503 } 4504 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4505 4506 static void spapr_machine_register_types(void) 4507 { 4508 type_register_static(&spapr_machine_info); 4509 } 4510 4511 type_init(spapr_machine_register_types) 4512