1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/hostmem.h" 34 #include "sysemu/numa.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/runstate.h" 38 #include "qemu/log.h" 39 #include "hw/fw-path-provider.h" 40 #include "elf.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/cpus.h" 44 #include "sysemu/hw_accel.h" 45 #include "kvm_ppc.h" 46 #include "migration/misc.h" 47 #include "migration/qemu-file-types.h" 48 #include "migration/global_state.h" 49 #include "migration/register.h" 50 #include "migration/blocker.h" 51 #include "mmu-hash64.h" 52 #include "mmu-book3s-v3.h" 53 #include "cpu-models.h" 54 #include "hw/core/cpu.h" 55 56 #include "hw/boards.h" 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/address-spaces.h" 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 87 #include "monitor/monitor.h" 88 89 #include <libfdt.h> 90 91 /* SLOF memory layout: 92 * 93 * SLOF raw image loaded at 0, copies its romfs right below the flat 94 * device-tree, then position SLOF itself 31M below that 95 * 96 * So we set FW_OVERHEAD to 40MB which should account for all of that 97 * and more 98 * 99 * We load our kernel at 4M, leaving space for SLOF initial image 100 */ 101 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 102 #define FW_MAX_SIZE 0x400000 103 #define FW_FILE_NAME "slof.bin" 104 #define FW_OVERHEAD 0x2800000 105 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 106 107 #define MIN_RMA_SLOF (128 * MiB) 108 109 #define PHANDLE_INTC 0x00001111 110 111 /* These two functions implement the VCPU id numbering: one to compute them 112 * all and one to identify thread 0 of a VCORE. Any change to the first one 113 * is likely to have an impact on the second one, so let's keep them close. 114 */ 115 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 116 { 117 MachineState *ms = MACHINE(spapr); 118 unsigned int smp_threads = ms->smp.threads; 119 120 assert(spapr->vsmt); 121 return 122 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 123 } 124 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 125 PowerPCCPU *cpu) 126 { 127 assert(spapr->vsmt); 128 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 129 } 130 131 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 132 { 133 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 134 * and newer QEMUs don't even have them. In both cases, we don't want 135 * to send anything on the wire. 136 */ 137 return false; 138 } 139 140 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 141 .name = "icp/server", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .needed = pre_2_10_vmstate_dummy_icp_needed, 145 .fields = (VMStateField[]) { 146 VMSTATE_UNUSED(4), /* uint32_t xirr */ 147 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 148 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 149 VMSTATE_END_OF_LIST() 150 }, 151 }; 152 153 static void pre_2_10_vmstate_register_dummy_icp(int i) 154 { 155 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 156 (void *)(uintptr_t) i); 157 } 158 159 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 160 { 161 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 162 (void *)(uintptr_t) i); 163 } 164 165 int spapr_max_server_number(SpaprMachineState *spapr) 166 { 167 MachineState *ms = MACHINE(spapr); 168 169 assert(spapr->vsmt); 170 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 171 } 172 173 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 174 int smt_threads) 175 { 176 int i, ret = 0; 177 uint32_t servers_prop[smt_threads]; 178 uint32_t gservers_prop[smt_threads * 2]; 179 int index = spapr_get_vcpu_id(cpu); 180 181 if (cpu->compat_pvr) { 182 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 183 if (ret < 0) { 184 return ret; 185 } 186 } 187 188 /* Build interrupt servers and gservers properties */ 189 for (i = 0; i < smt_threads; i++) { 190 servers_prop[i] = cpu_to_be32(index + i); 191 /* Hack, direct the group queues back to cpu 0 */ 192 gservers_prop[i*2] = cpu_to_be32(index + i); 193 gservers_prop[i*2 + 1] = 0; 194 } 195 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 196 servers_prop, sizeof(servers_prop)); 197 if (ret < 0) { 198 return ret; 199 } 200 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 201 gservers_prop, sizeof(gservers_prop)); 202 203 return ret; 204 } 205 206 static void spapr_dt_pa_features(SpaprMachineState *spapr, 207 PowerPCCPU *cpu, 208 void *fdt, int offset) 209 { 210 uint8_t pa_features_206[] = { 6, 0, 211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 212 uint8_t pa_features_207[] = { 24, 0, 213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 217 uint8_t pa_features_300[] = { 66, 0, 218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 221 /* 6: DS207 */ 222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 223 /* 16: Vector */ 224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 233 /* 42: PM, 44: PC RA, 46: SC vec'd */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 235 /* 48: SIMD, 50: QP BFP, 52: String */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 237 /* 54: DecFP, 56: DecI, 58: SHA */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 239 /* 60: NM atomic, 62: RNG */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 241 }; 242 uint8_t *pa_features = NULL; 243 size_t pa_size; 244 245 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 246 pa_features = pa_features_206; 247 pa_size = sizeof(pa_features_206); 248 } 249 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 250 pa_features = pa_features_207; 251 pa_size = sizeof(pa_features_207); 252 } 253 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 254 pa_features = pa_features_300; 255 pa_size = sizeof(pa_features_300); 256 } 257 if (!pa_features) { 258 return; 259 } 260 261 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 262 /* 263 * Note: we keep CI large pages off by default because a 64K capable 264 * guest provisioned with large pages might otherwise try to map a qemu 265 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 266 * even if that qemu runs on a 4k host. 267 * We dd this bit back here if we are confident this is not an issue 268 */ 269 pa_features[3] |= 0x20; 270 } 271 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 272 pa_features[24] |= 0x80; /* Transactional memory support */ 273 } 274 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 275 /* Workaround for broken kernels that attempt (guest) radix 276 * mode when they can't handle it, if they see the radix bit set 277 * in pa-features. So hide it from them. */ 278 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 279 } 280 281 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 282 } 283 284 static hwaddr spapr_node0_size(MachineState *machine) 285 { 286 if (machine->numa_state->num_nodes) { 287 int i; 288 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 289 if (machine->numa_state->nodes[i].node_mem) { 290 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 291 machine->ram_size); 292 } 293 } 294 } 295 return machine->ram_size; 296 } 297 298 bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr) 299 { 300 MachineState *machine = MACHINE(spapr); 301 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 302 303 return smc->pre_5_2_numa_associativity || 304 machine->numa_state->num_nodes <= 1; 305 } 306 307 static void add_str(GString *s, const gchar *s1) 308 { 309 g_string_append_len(s, s1, strlen(s1) + 1); 310 } 311 312 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 313 hwaddr start, hwaddr size) 314 { 315 char mem_name[32]; 316 uint64_t mem_reg_property[2]; 317 int off; 318 319 mem_reg_property[0] = cpu_to_be64(start); 320 mem_reg_property[1] = cpu_to_be64(size); 321 322 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 323 off = fdt_add_subnode(fdt, 0, mem_name); 324 _FDT(off); 325 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 326 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 327 sizeof(mem_reg_property)))); 328 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 329 return off; 330 } 331 332 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 333 { 334 MemoryDeviceInfoList *info; 335 336 for (info = list; info; info = info->next) { 337 MemoryDeviceInfo *value = info->value; 338 339 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 340 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 341 342 if (addr >= pcdimm_info->addr && 343 addr < (pcdimm_info->addr + pcdimm_info->size)) { 344 return pcdimm_info->node; 345 } 346 } 347 } 348 349 return -1; 350 } 351 352 struct sPAPRDrconfCellV2 { 353 uint32_t seq_lmbs; 354 uint64_t base_addr; 355 uint32_t drc_index; 356 uint32_t aa_index; 357 uint32_t flags; 358 } QEMU_PACKED; 359 360 typedef struct DrconfCellQueue { 361 struct sPAPRDrconfCellV2 cell; 362 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 363 } DrconfCellQueue; 364 365 static DrconfCellQueue * 366 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 367 uint32_t drc_index, uint32_t aa_index, 368 uint32_t flags) 369 { 370 DrconfCellQueue *elem; 371 372 elem = g_malloc0(sizeof(*elem)); 373 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 374 elem->cell.base_addr = cpu_to_be64(base_addr); 375 elem->cell.drc_index = cpu_to_be32(drc_index); 376 elem->cell.aa_index = cpu_to_be32(aa_index); 377 elem->cell.flags = cpu_to_be32(flags); 378 379 return elem; 380 } 381 382 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 383 int offset, MemoryDeviceInfoList *dimms) 384 { 385 MachineState *machine = MACHINE(spapr); 386 uint8_t *int_buf, *cur_index; 387 int ret; 388 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 389 uint64_t addr, cur_addr, size; 390 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 391 uint64_t mem_end = machine->device_memory->base + 392 memory_region_size(&machine->device_memory->mr); 393 uint32_t node, buf_len, nr_entries = 0; 394 SpaprDrc *drc; 395 DrconfCellQueue *elem, *next; 396 MemoryDeviceInfoList *info; 397 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 398 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 399 400 /* Entry to cover RAM and the gap area */ 401 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 402 SPAPR_LMB_FLAGS_RESERVED | 403 SPAPR_LMB_FLAGS_DRC_INVALID); 404 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 405 nr_entries++; 406 407 cur_addr = machine->device_memory->base; 408 for (info = dimms; info; info = info->next) { 409 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 410 411 addr = di->addr; 412 size = di->size; 413 node = di->node; 414 415 /* 416 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 417 * area is marked hotpluggable in the next iteration for the bigger 418 * chunk including the NVDIMM occupied area. 419 */ 420 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 421 continue; 422 423 /* Entry for hot-pluggable area */ 424 if (cur_addr < addr) { 425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 426 g_assert(drc); 427 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 428 cur_addr, spapr_drc_index(drc), -1, 0); 429 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 430 nr_entries++; 431 } 432 433 /* Entry for DIMM */ 434 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 435 g_assert(drc); 436 elem = spapr_get_drconf_cell(size / lmb_size, addr, 437 spapr_drc_index(drc), node, 438 (SPAPR_LMB_FLAGS_ASSIGNED | 439 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 440 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 441 nr_entries++; 442 cur_addr = addr + size; 443 } 444 445 /* Entry for remaining hotpluggable area */ 446 if (cur_addr < mem_end) { 447 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 448 g_assert(drc); 449 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 450 cur_addr, spapr_drc_index(drc), -1, 0); 451 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 452 nr_entries++; 453 } 454 455 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 456 int_buf = cur_index = g_malloc0(buf_len); 457 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 458 cur_index += sizeof(nr_entries); 459 460 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 461 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 462 cur_index += sizeof(elem->cell); 463 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 464 g_free(elem); 465 } 466 467 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 468 g_free(int_buf); 469 if (ret < 0) { 470 return -1; 471 } 472 return 0; 473 } 474 475 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 476 int offset, MemoryDeviceInfoList *dimms) 477 { 478 MachineState *machine = MACHINE(spapr); 479 int i, ret; 480 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 481 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 482 uint32_t nr_lmbs = (machine->device_memory->base + 483 memory_region_size(&machine->device_memory->mr)) / 484 lmb_size; 485 uint32_t *int_buf, *cur_index, buf_len; 486 487 /* 488 * Allocate enough buffer size to fit in ibm,dynamic-memory 489 */ 490 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 491 cur_index = int_buf = g_malloc0(buf_len); 492 int_buf[0] = cpu_to_be32(nr_lmbs); 493 cur_index++; 494 for (i = 0; i < nr_lmbs; i++) { 495 uint64_t addr = i * lmb_size; 496 uint32_t *dynamic_memory = cur_index; 497 498 if (i >= device_lmb_start) { 499 SpaprDrc *drc; 500 501 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 502 g_assert(drc); 503 504 dynamic_memory[0] = cpu_to_be32(addr >> 32); 505 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 506 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 507 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 508 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 509 if (memory_region_present(get_system_memory(), addr)) { 510 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 511 } else { 512 dynamic_memory[5] = cpu_to_be32(0); 513 } 514 } else { 515 /* 516 * LMB information for RMA, boot time RAM and gap b/n RAM and 517 * device memory region -- all these are marked as reserved 518 * and as having no valid DRC. 519 */ 520 dynamic_memory[0] = cpu_to_be32(addr >> 32); 521 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 522 dynamic_memory[2] = cpu_to_be32(0); 523 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 524 dynamic_memory[4] = cpu_to_be32(-1); 525 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 526 SPAPR_LMB_FLAGS_DRC_INVALID); 527 } 528 529 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 530 } 531 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 532 g_free(int_buf); 533 if (ret < 0) { 534 return -1; 535 } 536 return 0; 537 } 538 539 /* 540 * Adds ibm,dynamic-reconfiguration-memory node. 541 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 542 * of this device tree node. 543 */ 544 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 545 void *fdt) 546 { 547 MachineState *machine = MACHINE(spapr); 548 int ret, offset; 549 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 550 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 551 cpu_to_be32(lmb_size & 0xffffffff)}; 552 MemoryDeviceInfoList *dimms = NULL; 553 554 /* 555 * Don't create the node if there is no device memory 556 */ 557 if (machine->ram_size == machine->maxram_size) { 558 return 0; 559 } 560 561 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 562 563 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 564 sizeof(prop_lmb_size)); 565 if (ret < 0) { 566 return ret; 567 } 568 569 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 570 if (ret < 0) { 571 return ret; 572 } 573 574 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 575 if (ret < 0) { 576 return ret; 577 } 578 579 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 580 dimms = qmp_memory_device_list(); 581 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 582 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 583 } else { 584 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 585 } 586 qapi_free_MemoryDeviceInfoList(dimms); 587 588 if (ret < 0) { 589 return ret; 590 } 591 592 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 593 594 return ret; 595 } 596 597 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 598 { 599 MachineState *machine = MACHINE(spapr); 600 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 601 hwaddr mem_start, node_size; 602 int i, nb_nodes = machine->numa_state->num_nodes; 603 NodeInfo *nodes = machine->numa_state->nodes; 604 605 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 606 if (!nodes[i].node_mem) { 607 continue; 608 } 609 if (mem_start >= machine->ram_size) { 610 node_size = 0; 611 } else { 612 node_size = nodes[i].node_mem; 613 if (node_size > machine->ram_size - mem_start) { 614 node_size = machine->ram_size - mem_start; 615 } 616 } 617 if (!mem_start) { 618 /* spapr_machine_init() checks for rma_size <= node0_size 619 * already */ 620 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 621 mem_start += spapr->rma_size; 622 node_size -= spapr->rma_size; 623 } 624 for ( ; node_size; ) { 625 hwaddr sizetmp = pow2floor(node_size); 626 627 /* mem_start != 0 here */ 628 if (ctzl(mem_start) < ctzl(sizetmp)) { 629 sizetmp = 1ULL << ctzl(mem_start); 630 } 631 632 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 633 node_size -= sizetmp; 634 mem_start += sizetmp; 635 } 636 } 637 638 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 639 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 640 int ret; 641 642 g_assert(smc->dr_lmb_enabled); 643 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 644 if (ret) { 645 return ret; 646 } 647 } 648 649 return 0; 650 } 651 652 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 653 SpaprMachineState *spapr) 654 { 655 MachineState *ms = MACHINE(spapr); 656 PowerPCCPU *cpu = POWERPC_CPU(cs); 657 CPUPPCState *env = &cpu->env; 658 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 659 int index = spapr_get_vcpu_id(cpu); 660 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 661 0xffffffff, 0xffffffff}; 662 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 663 : SPAPR_TIMEBASE_FREQ; 664 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 665 uint32_t page_sizes_prop[64]; 666 size_t page_sizes_prop_size; 667 unsigned int smp_threads = ms->smp.threads; 668 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 669 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 670 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 671 SpaprDrc *drc; 672 int drc_index; 673 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 674 int i; 675 676 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 677 if (drc) { 678 drc_index = spapr_drc_index(drc); 679 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 680 } 681 682 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 683 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 684 685 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 686 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 687 env->dcache_line_size))); 688 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 689 env->dcache_line_size))); 690 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 691 env->icache_line_size))); 692 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 693 env->icache_line_size))); 694 695 if (pcc->l1_dcache_size) { 696 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 697 pcc->l1_dcache_size))); 698 } else { 699 warn_report("Unknown L1 dcache size for cpu"); 700 } 701 if (pcc->l1_icache_size) { 702 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 703 pcc->l1_icache_size))); 704 } else { 705 warn_report("Unknown L1 icache size for cpu"); 706 } 707 708 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 709 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 710 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 711 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 712 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 713 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 714 715 if (env->spr_cb[SPR_PURR].oea_read) { 716 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 717 } 718 if (env->spr_cb[SPR_SPURR].oea_read) { 719 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 720 } 721 722 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 723 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 724 segs, sizeof(segs)))); 725 } 726 727 /* Advertise VSX (vector extensions) if available 728 * 1 == VMX / Altivec available 729 * 2 == VSX available 730 * 731 * Only CPUs for which we create core types in spapr_cpu_core.c 732 * are possible, and all of those have VMX */ 733 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 734 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 735 } else { 736 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 737 } 738 739 /* Advertise DFP (Decimal Floating Point) if available 740 * 0 / no property == no DFP 741 * 1 == DFP available */ 742 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 743 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 744 } 745 746 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 747 sizeof(page_sizes_prop)); 748 if (page_sizes_prop_size) { 749 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 750 page_sizes_prop, page_sizes_prop_size))); 751 } 752 753 spapr_dt_pa_features(spapr, cpu, fdt, offset); 754 755 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 756 cs->cpu_index / vcpus_per_socket))); 757 758 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 759 pft_size_prop, sizeof(pft_size_prop)))); 760 761 if (ms->numa_state->num_nodes > 1) { 762 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 763 } 764 765 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 766 767 if (pcc->radix_page_info) { 768 for (i = 0; i < pcc->radix_page_info->count; i++) { 769 radix_AP_encodings[i] = 770 cpu_to_be32(pcc->radix_page_info->entries[i]); 771 } 772 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 773 radix_AP_encodings, 774 pcc->radix_page_info->count * 775 sizeof(radix_AP_encodings[0])))); 776 } 777 778 /* 779 * We set this property to let the guest know that it can use the large 780 * decrementer and its width in bits. 781 */ 782 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 783 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 784 pcc->lrg_decr_bits))); 785 } 786 787 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 788 { 789 CPUState **rev; 790 CPUState *cs; 791 int n_cpus; 792 int cpus_offset; 793 char *nodename; 794 int i; 795 796 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 797 _FDT(cpus_offset); 798 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 799 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 800 801 /* 802 * We walk the CPUs in reverse order to ensure that CPU DT nodes 803 * created by fdt_add_subnode() end up in the right order in FDT 804 * for the guest kernel the enumerate the CPUs correctly. 805 * 806 * The CPU list cannot be traversed in reverse order, so we need 807 * to do extra work. 808 */ 809 n_cpus = 0; 810 rev = NULL; 811 CPU_FOREACH(cs) { 812 rev = g_renew(CPUState *, rev, n_cpus + 1); 813 rev[n_cpus++] = cs; 814 } 815 816 for (i = n_cpus - 1; i >= 0; i--) { 817 CPUState *cs = rev[i]; 818 PowerPCCPU *cpu = POWERPC_CPU(cs); 819 int index = spapr_get_vcpu_id(cpu); 820 DeviceClass *dc = DEVICE_GET_CLASS(cs); 821 int offset; 822 823 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 824 continue; 825 } 826 827 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 828 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 829 g_free(nodename); 830 _FDT(offset); 831 spapr_dt_cpu(cs, fdt, offset, spapr); 832 } 833 834 g_free(rev); 835 } 836 837 static int spapr_dt_rng(void *fdt) 838 { 839 int node; 840 int ret; 841 842 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 843 if (node <= 0) { 844 return -1; 845 } 846 ret = fdt_setprop_string(fdt, node, "device_type", 847 "ibm,platform-facilities"); 848 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 849 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 850 851 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 852 if (node <= 0) { 853 return -1; 854 } 855 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 856 857 return ret ? -1 : 0; 858 } 859 860 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 861 { 862 MachineState *ms = MACHINE(spapr); 863 int rtas; 864 GString *hypertas = g_string_sized_new(256); 865 GString *qemu_hypertas = g_string_sized_new(256); 866 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 867 memory_region_size(&MACHINE(spapr)->device_memory->mr); 868 uint32_t lrdr_capacity[] = { 869 cpu_to_be32(max_device_addr >> 32), 870 cpu_to_be32(max_device_addr & 0xffffffff), 871 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 872 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 873 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 874 }; 875 876 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 877 878 /* hypertas */ 879 add_str(hypertas, "hcall-pft"); 880 add_str(hypertas, "hcall-term"); 881 add_str(hypertas, "hcall-dabr"); 882 add_str(hypertas, "hcall-interrupt"); 883 add_str(hypertas, "hcall-tce"); 884 add_str(hypertas, "hcall-vio"); 885 add_str(hypertas, "hcall-splpar"); 886 add_str(hypertas, "hcall-join"); 887 add_str(hypertas, "hcall-bulk"); 888 add_str(hypertas, "hcall-set-mode"); 889 add_str(hypertas, "hcall-sprg0"); 890 add_str(hypertas, "hcall-copy"); 891 add_str(hypertas, "hcall-debug"); 892 add_str(hypertas, "hcall-vphn"); 893 add_str(qemu_hypertas, "hcall-memop1"); 894 895 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 896 add_str(hypertas, "hcall-multi-tce"); 897 } 898 899 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 900 add_str(hypertas, "hcall-hpt-resize"); 901 } 902 903 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 904 hypertas->str, hypertas->len)); 905 g_string_free(hypertas, TRUE); 906 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 907 qemu_hypertas->str, qemu_hypertas->len)); 908 g_string_free(qemu_hypertas, TRUE); 909 910 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 911 912 /* 913 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 914 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 915 * 916 * The system reset requirements are driven by existing Linux and PowerVM 917 * implementation which (contrary to PAPR) saves r3 in the error log 918 * structure like machine check, so Linux expects to find the saved r3 919 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 920 * does not look at the error value). 921 * 922 * System reset interrupts are not subject to interlock like machine 923 * check, so this memory area could be corrupted if the sreset is 924 * interrupted by a machine check (or vice versa) if it was shared. To 925 * prevent this, system reset uses per-CPU areas for the sreset save 926 * area. A system reset that interrupts a system reset handler could 927 * still overwrite this area, but Linux doesn't try to recover in that 928 * case anyway. 929 * 930 * The extra 8 bytes is required because Linux's FWNMI error log check 931 * is off-by-one. 932 */ 933 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 934 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 935 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 936 RTAS_ERROR_LOG_MAX)); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 938 RTAS_EVENT_SCAN_RATE)); 939 940 g_assert(msi_nonbroken); 941 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 942 943 /* 944 * According to PAPR, rtas ibm,os-term does not guarantee a return 945 * back to the guest cpu. 946 * 947 * While an additional ibm,extended-os-term property indicates 948 * that rtas call return will always occur. Set this property. 949 */ 950 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 951 952 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 953 lrdr_capacity, sizeof(lrdr_capacity))); 954 955 spapr_dt_rtas_tokens(fdt, rtas); 956 } 957 958 /* 959 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 960 * and the XIVE features that the guest may request and thus the valid 961 * values for bytes 23..26 of option vector 5: 962 */ 963 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 964 int chosen) 965 { 966 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 967 968 char val[2 * 4] = { 969 23, 0x00, /* XICS / XIVE mode */ 970 24, 0x00, /* Hash/Radix, filled in below. */ 971 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 972 26, 0x40, /* Radix options: GTSE == yes. */ 973 }; 974 975 if (spapr->irq->xics && spapr->irq->xive) { 976 val[1] = SPAPR_OV5_XIVE_BOTH; 977 } else if (spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 979 } else { 980 assert(spapr->irq->xics); 981 val[1] = SPAPR_OV5_XIVE_LEGACY; 982 } 983 984 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 985 first_ppc_cpu->compat_pvr)) { 986 /* 987 * If we're in a pre POWER9 compat mode then the guest should 988 * do hash and use the legacy interrupt mode 989 */ 990 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 991 val[3] = 0x00; /* Hash */ 992 } else if (kvm_enabled()) { 993 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 994 val[3] = 0x80; /* OV5_MMU_BOTH */ 995 } else if (kvmppc_has_cap_mmu_radix()) { 996 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 997 } else { 998 val[3] = 0x00; /* Hash */ 999 } 1000 } else { 1001 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1002 val[3] = 0xC0; 1003 } 1004 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1005 val, sizeof(val))); 1006 } 1007 1008 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1009 { 1010 MachineState *machine = MACHINE(spapr); 1011 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1012 int chosen; 1013 1014 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1015 1016 if (reset) { 1017 const char *boot_device = machine->boot_order; 1018 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1019 size_t cb = 0; 1020 char *bootlist = get_boot_devices_list(&cb); 1021 1022 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1023 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1024 machine->kernel_cmdline)); 1025 } 1026 1027 if (spapr->initrd_size) { 1028 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1029 spapr->initrd_base)); 1030 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1031 spapr->initrd_base + spapr->initrd_size)); 1032 } 1033 1034 if (spapr->kernel_size) { 1035 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1036 cpu_to_be64(spapr->kernel_size) }; 1037 1038 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1039 &kprop, sizeof(kprop))); 1040 if (spapr->kernel_le) { 1041 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1042 } 1043 } 1044 if (boot_menu) { 1045 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1046 } 1047 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1049 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1050 1051 if (cb && bootlist) { 1052 int i; 1053 1054 for (i = 0; i < cb; i++) { 1055 if (bootlist[i] == '\n') { 1056 bootlist[i] = ' '; 1057 } 1058 } 1059 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1060 } 1061 1062 if (boot_device && strlen(boot_device)) { 1063 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1064 } 1065 1066 if (!spapr->has_graphics && stdout_path) { 1067 /* 1068 * "linux,stdout-path" and "stdout" properties are 1069 * deprecated by linux kernel. New platforms should only 1070 * use the "stdout-path" property. Set the new property 1071 * and continue using older property to remain compatible 1072 * with the existing firmware. 1073 */ 1074 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1075 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1076 } 1077 1078 /* 1079 * We can deal with BAR reallocation just fine, advertise it 1080 * to the guest 1081 */ 1082 if (smc->linux_pci_probe) { 1083 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1084 } 1085 1086 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1087 1088 g_free(stdout_path); 1089 g_free(bootlist); 1090 } 1091 1092 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1093 } 1094 1095 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1096 { 1097 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1098 * KVM to work under pHyp with some guest co-operation */ 1099 int hypervisor; 1100 uint8_t hypercall[16]; 1101 1102 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1103 /* indicate KVM hypercall interface */ 1104 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1105 if (kvmppc_has_cap_fixup_hcalls()) { 1106 /* 1107 * Older KVM versions with older guest kernels were broken 1108 * with the magic page, don't allow the guest to map it. 1109 */ 1110 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1111 sizeof(hypercall))) { 1112 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1113 hypercall, sizeof(hypercall))); 1114 } 1115 } 1116 } 1117 1118 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1119 { 1120 MachineState *machine = MACHINE(spapr); 1121 MachineClass *mc = MACHINE_GET_CLASS(machine); 1122 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1123 uint32_t root_drc_type_mask = 0; 1124 int ret; 1125 void *fdt; 1126 SpaprPhbState *phb; 1127 char *buf; 1128 1129 fdt = g_malloc0(space); 1130 _FDT((fdt_create_empty_tree(fdt, space))); 1131 1132 /* Root node */ 1133 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1134 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1135 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1136 1137 /* Guest UUID & Name*/ 1138 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1139 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1140 if (qemu_uuid_set) { 1141 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1142 } 1143 g_free(buf); 1144 1145 if (qemu_get_vm_name()) { 1146 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1147 qemu_get_vm_name())); 1148 } 1149 1150 /* Host Model & Serial Number */ 1151 if (spapr->host_model) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1153 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1154 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1155 g_free(buf); 1156 } 1157 1158 if (spapr->host_serial) { 1159 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1160 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1161 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1162 g_free(buf); 1163 } 1164 1165 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1166 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1167 1168 /* /interrupt controller */ 1169 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1170 1171 ret = spapr_dt_memory(spapr, fdt); 1172 if (ret < 0) { 1173 error_report("couldn't setup memory nodes in fdt"); 1174 exit(1); 1175 } 1176 1177 /* /vdevice */ 1178 spapr_dt_vdevice(spapr->vio_bus, fdt); 1179 1180 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1181 ret = spapr_dt_rng(fdt); 1182 if (ret < 0) { 1183 error_report("could not set up rng device in the fdt"); 1184 exit(1); 1185 } 1186 } 1187 1188 QLIST_FOREACH(phb, &spapr->phbs, list) { 1189 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1190 if (ret < 0) { 1191 error_report("couldn't setup PCI devices in fdt"); 1192 exit(1); 1193 } 1194 } 1195 1196 spapr_dt_cpus(fdt, spapr); 1197 1198 /* ibm,drc-indexes and friends */ 1199 if (smc->dr_lmb_enabled) { 1200 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1201 } 1202 if (smc->dr_phb_enabled) { 1203 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1204 } 1205 if (mc->nvdimm_supported) { 1206 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1207 } 1208 if (root_drc_type_mask) { 1209 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1210 } 1211 1212 if (mc->has_hotpluggable_cpus) { 1213 int offset = fdt_path_offset(fdt, "/cpus"); 1214 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1215 if (ret < 0) { 1216 error_report("Couldn't set up CPU DR device tree properties"); 1217 exit(1); 1218 } 1219 } 1220 1221 /* /event-sources */ 1222 spapr_dt_events(spapr, fdt); 1223 1224 /* /rtas */ 1225 spapr_dt_rtas(spapr, fdt); 1226 1227 /* /chosen */ 1228 spapr_dt_chosen(spapr, fdt, reset); 1229 1230 /* /hypervisor */ 1231 if (kvm_enabled()) { 1232 spapr_dt_hypervisor(spapr, fdt); 1233 } 1234 1235 /* Build memory reserve map */ 1236 if (reset) { 1237 if (spapr->kernel_size) { 1238 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1239 spapr->kernel_size))); 1240 } 1241 if (spapr->initrd_size) { 1242 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1243 spapr->initrd_size))); 1244 } 1245 } 1246 1247 /* NVDIMM devices */ 1248 if (mc->nvdimm_supported) { 1249 spapr_dt_persistent_memory(spapr, fdt); 1250 } 1251 1252 return fdt; 1253 } 1254 1255 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1256 { 1257 SpaprMachineState *spapr = opaque; 1258 1259 return (addr & 0x0fffffff) + spapr->kernel_addr; 1260 } 1261 1262 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1263 PowerPCCPU *cpu) 1264 { 1265 CPUPPCState *env = &cpu->env; 1266 1267 /* The TCG path should also be holding the BQL at this point */ 1268 g_assert(qemu_mutex_iothread_locked()); 1269 1270 if (msr_pr) { 1271 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1272 env->gpr[3] = H_PRIVILEGE; 1273 } else { 1274 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1275 } 1276 } 1277 1278 struct LPCRSyncState { 1279 target_ulong value; 1280 target_ulong mask; 1281 }; 1282 1283 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1284 { 1285 struct LPCRSyncState *s = arg.host_ptr; 1286 PowerPCCPU *cpu = POWERPC_CPU(cs); 1287 CPUPPCState *env = &cpu->env; 1288 target_ulong lpcr; 1289 1290 cpu_synchronize_state(cs); 1291 lpcr = env->spr[SPR_LPCR]; 1292 lpcr &= ~s->mask; 1293 lpcr |= s->value; 1294 ppc_store_lpcr(cpu, lpcr); 1295 } 1296 1297 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1298 { 1299 CPUState *cs; 1300 struct LPCRSyncState s = { 1301 .value = value, 1302 .mask = mask 1303 }; 1304 CPU_FOREACH(cs) { 1305 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1306 } 1307 } 1308 1309 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1310 { 1311 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1312 1313 /* Copy PATE1:GR into PATE0:HR */ 1314 entry->dw0 = spapr->patb_entry & PATE0_HR; 1315 entry->dw1 = spapr->patb_entry; 1316 } 1317 1318 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1319 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1320 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1321 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1322 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1323 1324 /* 1325 * Get the fd to access the kernel htab, re-opening it if necessary 1326 */ 1327 static int get_htab_fd(SpaprMachineState *spapr) 1328 { 1329 Error *local_err = NULL; 1330 1331 if (spapr->htab_fd >= 0) { 1332 return spapr->htab_fd; 1333 } 1334 1335 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1336 if (spapr->htab_fd < 0) { 1337 error_report_err(local_err); 1338 } 1339 1340 return spapr->htab_fd; 1341 } 1342 1343 void close_htab_fd(SpaprMachineState *spapr) 1344 { 1345 if (spapr->htab_fd >= 0) { 1346 close(spapr->htab_fd); 1347 } 1348 spapr->htab_fd = -1; 1349 } 1350 1351 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1352 { 1353 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1354 1355 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1356 } 1357 1358 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1359 { 1360 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1361 1362 assert(kvm_enabled()); 1363 1364 if (!spapr->htab) { 1365 return 0; 1366 } 1367 1368 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1369 } 1370 1371 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1372 hwaddr ptex, int n) 1373 { 1374 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1375 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1376 1377 if (!spapr->htab) { 1378 /* 1379 * HTAB is controlled by KVM. Fetch into temporary buffer 1380 */ 1381 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1382 kvmppc_read_hptes(hptes, ptex, n); 1383 return hptes; 1384 } 1385 1386 /* 1387 * HTAB is controlled by QEMU. Just point to the internally 1388 * accessible PTEG. 1389 */ 1390 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1391 } 1392 1393 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1394 const ppc_hash_pte64_t *hptes, 1395 hwaddr ptex, int n) 1396 { 1397 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1398 1399 if (!spapr->htab) { 1400 g_free((void *)hptes); 1401 } 1402 1403 /* Nothing to do for qemu managed HPT */ 1404 } 1405 1406 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1407 uint64_t pte0, uint64_t pte1) 1408 { 1409 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1410 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1411 1412 if (!spapr->htab) { 1413 kvmppc_write_hpte(ptex, pte0, pte1); 1414 } else { 1415 if (pte0 & HPTE64_V_VALID) { 1416 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1417 /* 1418 * When setting valid, we write PTE1 first. This ensures 1419 * proper synchronization with the reading code in 1420 * ppc_hash64_pteg_search() 1421 */ 1422 smp_wmb(); 1423 stq_p(spapr->htab + offset, pte0); 1424 } else { 1425 stq_p(spapr->htab + offset, pte0); 1426 /* 1427 * When clearing it we set PTE0 first. This ensures proper 1428 * synchronization with the reading code in 1429 * ppc_hash64_pteg_search() 1430 */ 1431 smp_wmb(); 1432 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1433 } 1434 } 1435 } 1436 1437 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1438 uint64_t pte1) 1439 { 1440 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1441 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1442 1443 if (!spapr->htab) { 1444 /* There should always be a hash table when this is called */ 1445 error_report("spapr_hpte_set_c called with no hash table !"); 1446 return; 1447 } 1448 1449 /* The HW performs a non-atomic byte update */ 1450 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1451 } 1452 1453 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1454 uint64_t pte1) 1455 { 1456 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1457 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1458 1459 if (!spapr->htab) { 1460 /* There should always be a hash table when this is called */ 1461 error_report("spapr_hpte_set_r called with no hash table !"); 1462 return; 1463 } 1464 1465 /* The HW performs a non-atomic byte update */ 1466 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1467 } 1468 1469 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1470 { 1471 int shift; 1472 1473 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1474 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1475 * that's much more than is needed for Linux guests */ 1476 shift = ctz64(pow2ceil(ramsize)) - 7; 1477 shift = MAX(shift, 18); /* Minimum architected size */ 1478 shift = MIN(shift, 46); /* Maximum architected size */ 1479 return shift; 1480 } 1481 1482 void spapr_free_hpt(SpaprMachineState *spapr) 1483 { 1484 g_free(spapr->htab); 1485 spapr->htab = NULL; 1486 spapr->htab_shift = 0; 1487 close_htab_fd(spapr); 1488 } 1489 1490 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1491 { 1492 ERRP_GUARD(); 1493 long rc; 1494 1495 /* Clean up any HPT info from a previous boot */ 1496 spapr_free_hpt(spapr); 1497 1498 rc = kvmppc_reset_htab(shift); 1499 1500 if (rc == -EOPNOTSUPP) { 1501 error_setg(errp, "HPT not supported in nested guests"); 1502 return -EOPNOTSUPP; 1503 } 1504 1505 if (rc < 0) { 1506 /* kernel-side HPT needed, but couldn't allocate one */ 1507 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1508 shift); 1509 error_append_hint(errp, "Try smaller maxmem?\n"); 1510 return -errno; 1511 } else if (rc > 0) { 1512 /* kernel-side HPT allocated */ 1513 if (rc != shift) { 1514 error_setg(errp, 1515 "Requested order %d HPT, but kernel allocated order %ld", 1516 shift, rc); 1517 error_append_hint(errp, "Try smaller maxmem?\n"); 1518 return -ENOSPC; 1519 } 1520 1521 spapr->htab_shift = shift; 1522 spapr->htab = NULL; 1523 } else { 1524 /* kernel-side HPT not needed, allocate in userspace instead */ 1525 size_t size = 1ULL << shift; 1526 int i; 1527 1528 spapr->htab = qemu_memalign(size, size); 1529 memset(spapr->htab, 0, size); 1530 spapr->htab_shift = shift; 1531 1532 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1533 DIRTY_HPTE(HPTE(spapr->htab, i)); 1534 } 1535 } 1536 /* We're setting up a hash table, so that means we're not radix */ 1537 spapr->patb_entry = 0; 1538 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1539 return 0; 1540 } 1541 1542 void spapr_setup_hpt(SpaprMachineState *spapr) 1543 { 1544 int hpt_shift; 1545 1546 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1547 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1548 } else { 1549 uint64_t current_ram_size; 1550 1551 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1552 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1553 } 1554 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1555 1556 if (kvm_enabled()) { 1557 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1558 1559 /* Check our RMA fits in the possible VRMA */ 1560 if (vrma_limit < spapr->rma_size) { 1561 error_report("Unable to create %" HWADDR_PRIu 1562 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1563 spapr->rma_size / MiB, vrma_limit / MiB); 1564 exit(EXIT_FAILURE); 1565 } 1566 } 1567 } 1568 1569 static int spapr_reset_drcs(Object *child, void *opaque) 1570 { 1571 SpaprDrc *drc = 1572 (SpaprDrc *) object_dynamic_cast(child, 1573 TYPE_SPAPR_DR_CONNECTOR); 1574 1575 if (drc) { 1576 spapr_drc_reset(drc); 1577 } 1578 1579 return 0; 1580 } 1581 1582 static void spapr_machine_reset(MachineState *machine) 1583 { 1584 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1585 PowerPCCPU *first_ppc_cpu; 1586 hwaddr fdt_addr; 1587 void *fdt; 1588 int rc; 1589 1590 kvmppc_svm_off(&error_fatal); 1591 spapr_caps_apply(spapr); 1592 1593 first_ppc_cpu = POWERPC_CPU(first_cpu); 1594 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1595 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1596 spapr->max_compat_pvr)) { 1597 /* 1598 * If using KVM with radix mode available, VCPUs can be started 1599 * without a HPT because KVM will start them in radix mode. 1600 * Set the GR bit in PATE so that we know there is no HPT. 1601 */ 1602 spapr->patb_entry = PATE1_GR; 1603 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1604 } else { 1605 spapr_setup_hpt(spapr); 1606 } 1607 1608 qemu_devices_reset(); 1609 1610 spapr_ovec_cleanup(spapr->ov5_cas); 1611 spapr->ov5_cas = spapr_ovec_new(); 1612 1613 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1614 1615 /* 1616 * This is fixing some of the default configuration of the XIVE 1617 * devices. To be called after the reset of the machine devices. 1618 */ 1619 spapr_irq_reset(spapr, &error_fatal); 1620 1621 /* 1622 * There is no CAS under qtest. Simulate one to please the code that 1623 * depends on spapr->ov5_cas. This is especially needed to test device 1624 * unplug, so we do that before resetting the DRCs. 1625 */ 1626 if (qtest_enabled()) { 1627 spapr_ovec_cleanup(spapr->ov5_cas); 1628 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1629 } 1630 1631 /* DRC reset may cause a device to be unplugged. This will cause troubles 1632 * if this device is used by another device (eg, a running vhost backend 1633 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1634 * situations, we reset DRCs after all devices have been reset. 1635 */ 1636 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1637 1638 spapr_clear_pending_events(spapr); 1639 1640 /* 1641 * We place the device tree and RTAS just below either the top of the RMA, 1642 * or just below 2GB, whichever is lower, so that it can be 1643 * processed with 32-bit real mode code if necessary 1644 */ 1645 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1646 1647 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1648 1649 rc = fdt_pack(fdt); 1650 1651 /* Should only fail if we've built a corrupted tree */ 1652 assert(rc == 0); 1653 1654 /* Load the fdt */ 1655 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1656 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1657 g_free(spapr->fdt_blob); 1658 spapr->fdt_size = fdt_totalsize(fdt); 1659 spapr->fdt_initial_size = spapr->fdt_size; 1660 spapr->fdt_blob = fdt; 1661 1662 /* Set up the entry state */ 1663 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1664 first_ppc_cpu->env.gpr[5] = 0; 1665 1666 spapr->fwnmi_system_reset_addr = -1; 1667 spapr->fwnmi_machine_check_addr = -1; 1668 spapr->fwnmi_machine_check_interlock = -1; 1669 1670 /* Signal all vCPUs waiting on this condition */ 1671 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1672 1673 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1674 } 1675 1676 static void spapr_create_nvram(SpaprMachineState *spapr) 1677 { 1678 DeviceState *dev = qdev_new("spapr-nvram"); 1679 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1680 1681 if (dinfo) { 1682 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1683 &error_fatal); 1684 } 1685 1686 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1687 1688 spapr->nvram = (struct SpaprNvram *)dev; 1689 } 1690 1691 static void spapr_rtc_create(SpaprMachineState *spapr) 1692 { 1693 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1694 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1695 &error_fatal, NULL); 1696 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1697 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1698 "date"); 1699 } 1700 1701 /* Returns whether we want to use VGA or not */ 1702 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1703 { 1704 switch (vga_interface_type) { 1705 case VGA_NONE: 1706 return false; 1707 case VGA_DEVICE: 1708 return true; 1709 case VGA_STD: 1710 case VGA_VIRTIO: 1711 case VGA_CIRRUS: 1712 return pci_vga_init(pci_bus) != NULL; 1713 default: 1714 error_setg(errp, 1715 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1716 return false; 1717 } 1718 } 1719 1720 static int spapr_pre_load(void *opaque) 1721 { 1722 int rc; 1723 1724 rc = spapr_caps_pre_load(opaque); 1725 if (rc) { 1726 return rc; 1727 } 1728 1729 return 0; 1730 } 1731 1732 static int spapr_post_load(void *opaque, int version_id) 1733 { 1734 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1735 int err = 0; 1736 1737 err = spapr_caps_post_migration(spapr); 1738 if (err) { 1739 return err; 1740 } 1741 1742 /* 1743 * In earlier versions, there was no separate qdev for the PAPR 1744 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1745 * So when migrating from those versions, poke the incoming offset 1746 * value into the RTC device 1747 */ 1748 if (version_id < 3) { 1749 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1750 if (err) { 1751 return err; 1752 } 1753 } 1754 1755 if (kvm_enabled() && spapr->patb_entry) { 1756 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1757 bool radix = !!(spapr->patb_entry & PATE1_GR); 1758 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1759 1760 /* 1761 * Update LPCR:HR and UPRT as they may not be set properly in 1762 * the stream 1763 */ 1764 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1765 LPCR_HR | LPCR_UPRT); 1766 1767 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1768 if (err) { 1769 error_report("Process table config unsupported by the host"); 1770 return -EINVAL; 1771 } 1772 } 1773 1774 err = spapr_irq_post_load(spapr, version_id); 1775 if (err) { 1776 return err; 1777 } 1778 1779 return err; 1780 } 1781 1782 static int spapr_pre_save(void *opaque) 1783 { 1784 int rc; 1785 1786 rc = spapr_caps_pre_save(opaque); 1787 if (rc) { 1788 return rc; 1789 } 1790 1791 return 0; 1792 } 1793 1794 static bool version_before_3(void *opaque, int version_id) 1795 { 1796 return version_id < 3; 1797 } 1798 1799 static bool spapr_pending_events_needed(void *opaque) 1800 { 1801 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1802 return !QTAILQ_EMPTY(&spapr->pending_events); 1803 } 1804 1805 static const VMStateDescription vmstate_spapr_event_entry = { 1806 .name = "spapr_event_log_entry", 1807 .version_id = 1, 1808 .minimum_version_id = 1, 1809 .fields = (VMStateField[]) { 1810 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1811 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1812 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1813 NULL, extended_length), 1814 VMSTATE_END_OF_LIST() 1815 }, 1816 }; 1817 1818 static const VMStateDescription vmstate_spapr_pending_events = { 1819 .name = "spapr_pending_events", 1820 .version_id = 1, 1821 .minimum_version_id = 1, 1822 .needed = spapr_pending_events_needed, 1823 .fields = (VMStateField[]) { 1824 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1825 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1826 VMSTATE_END_OF_LIST() 1827 }, 1828 }; 1829 1830 static bool spapr_ov5_cas_needed(void *opaque) 1831 { 1832 SpaprMachineState *spapr = opaque; 1833 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1834 bool cas_needed; 1835 1836 /* Prior to the introduction of SpaprOptionVector, we had two option 1837 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1838 * Both of these options encode machine topology into the device-tree 1839 * in such a way that the now-booted OS should still be able to interact 1840 * appropriately with QEMU regardless of what options were actually 1841 * negotiatied on the source side. 1842 * 1843 * As such, we can avoid migrating the CAS-negotiated options if these 1844 * are the only options available on the current machine/platform. 1845 * Since these are the only options available for pseries-2.7 and 1846 * earlier, this allows us to maintain old->new/new->old migration 1847 * compatibility. 1848 * 1849 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1850 * via default pseries-2.8 machines and explicit command-line parameters. 1851 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1852 * of the actual CAS-negotiated values to continue working properly. For 1853 * example, availability of memory unplug depends on knowing whether 1854 * OV5_HP_EVT was negotiated via CAS. 1855 * 1856 * Thus, for any cases where the set of available CAS-negotiatable 1857 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1858 * include the CAS-negotiated options in the migration stream, unless 1859 * if they affect boot time behaviour only. 1860 */ 1861 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1862 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1863 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1864 1865 /* We need extra information if we have any bits outside the mask 1866 * defined above */ 1867 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1868 1869 spapr_ovec_cleanup(ov5_mask); 1870 1871 return cas_needed; 1872 } 1873 1874 static const VMStateDescription vmstate_spapr_ov5_cas = { 1875 .name = "spapr_option_vector_ov5_cas", 1876 .version_id = 1, 1877 .minimum_version_id = 1, 1878 .needed = spapr_ov5_cas_needed, 1879 .fields = (VMStateField[]) { 1880 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1881 vmstate_spapr_ovec, SpaprOptionVector), 1882 VMSTATE_END_OF_LIST() 1883 }, 1884 }; 1885 1886 static bool spapr_patb_entry_needed(void *opaque) 1887 { 1888 SpaprMachineState *spapr = opaque; 1889 1890 return !!spapr->patb_entry; 1891 } 1892 1893 static const VMStateDescription vmstate_spapr_patb_entry = { 1894 .name = "spapr_patb_entry", 1895 .version_id = 1, 1896 .minimum_version_id = 1, 1897 .needed = spapr_patb_entry_needed, 1898 .fields = (VMStateField[]) { 1899 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1900 VMSTATE_END_OF_LIST() 1901 }, 1902 }; 1903 1904 static bool spapr_irq_map_needed(void *opaque) 1905 { 1906 SpaprMachineState *spapr = opaque; 1907 1908 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1909 } 1910 1911 static const VMStateDescription vmstate_spapr_irq_map = { 1912 .name = "spapr_irq_map", 1913 .version_id = 1, 1914 .minimum_version_id = 1, 1915 .needed = spapr_irq_map_needed, 1916 .fields = (VMStateField[]) { 1917 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1918 VMSTATE_END_OF_LIST() 1919 }, 1920 }; 1921 1922 static bool spapr_dtb_needed(void *opaque) 1923 { 1924 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1925 1926 return smc->update_dt_enabled; 1927 } 1928 1929 static int spapr_dtb_pre_load(void *opaque) 1930 { 1931 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1932 1933 g_free(spapr->fdt_blob); 1934 spapr->fdt_blob = NULL; 1935 spapr->fdt_size = 0; 1936 1937 return 0; 1938 } 1939 1940 static const VMStateDescription vmstate_spapr_dtb = { 1941 .name = "spapr_dtb", 1942 .version_id = 1, 1943 .minimum_version_id = 1, 1944 .needed = spapr_dtb_needed, 1945 .pre_load = spapr_dtb_pre_load, 1946 .fields = (VMStateField[]) { 1947 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1948 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1949 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1950 fdt_size), 1951 VMSTATE_END_OF_LIST() 1952 }, 1953 }; 1954 1955 static bool spapr_fwnmi_needed(void *opaque) 1956 { 1957 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1958 1959 return spapr->fwnmi_machine_check_addr != -1; 1960 } 1961 1962 static int spapr_fwnmi_pre_save(void *opaque) 1963 { 1964 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1965 1966 /* 1967 * Check if machine check handling is in progress and print a 1968 * warning message. 1969 */ 1970 if (spapr->fwnmi_machine_check_interlock != -1) { 1971 warn_report("A machine check is being handled during migration. The" 1972 "handler may run and log hardware error on the destination"); 1973 } 1974 1975 return 0; 1976 } 1977 1978 static const VMStateDescription vmstate_spapr_fwnmi = { 1979 .name = "spapr_fwnmi", 1980 .version_id = 1, 1981 .minimum_version_id = 1, 1982 .needed = spapr_fwnmi_needed, 1983 .pre_save = spapr_fwnmi_pre_save, 1984 .fields = (VMStateField[]) { 1985 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1986 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1987 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1988 VMSTATE_END_OF_LIST() 1989 }, 1990 }; 1991 1992 static const VMStateDescription vmstate_spapr = { 1993 .name = "spapr", 1994 .version_id = 3, 1995 .minimum_version_id = 1, 1996 .pre_load = spapr_pre_load, 1997 .post_load = spapr_post_load, 1998 .pre_save = spapr_pre_save, 1999 .fields = (VMStateField[]) { 2000 /* used to be @next_irq */ 2001 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2002 2003 /* RTC offset */ 2004 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2005 2006 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2007 VMSTATE_END_OF_LIST() 2008 }, 2009 .subsections = (const VMStateDescription*[]) { 2010 &vmstate_spapr_ov5_cas, 2011 &vmstate_spapr_patb_entry, 2012 &vmstate_spapr_pending_events, 2013 &vmstate_spapr_cap_htm, 2014 &vmstate_spapr_cap_vsx, 2015 &vmstate_spapr_cap_dfp, 2016 &vmstate_spapr_cap_cfpc, 2017 &vmstate_spapr_cap_sbbc, 2018 &vmstate_spapr_cap_ibs, 2019 &vmstate_spapr_cap_hpt_maxpagesize, 2020 &vmstate_spapr_irq_map, 2021 &vmstate_spapr_cap_nested_kvm_hv, 2022 &vmstate_spapr_dtb, 2023 &vmstate_spapr_cap_large_decr, 2024 &vmstate_spapr_cap_ccf_assist, 2025 &vmstate_spapr_cap_fwnmi, 2026 &vmstate_spapr_fwnmi, 2027 NULL 2028 } 2029 }; 2030 2031 static int htab_save_setup(QEMUFile *f, void *opaque) 2032 { 2033 SpaprMachineState *spapr = opaque; 2034 2035 /* "Iteration" header */ 2036 if (!spapr->htab_shift) { 2037 qemu_put_be32(f, -1); 2038 } else { 2039 qemu_put_be32(f, spapr->htab_shift); 2040 } 2041 2042 if (spapr->htab) { 2043 spapr->htab_save_index = 0; 2044 spapr->htab_first_pass = true; 2045 } else { 2046 if (spapr->htab_shift) { 2047 assert(kvm_enabled()); 2048 } 2049 } 2050 2051 2052 return 0; 2053 } 2054 2055 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2056 int chunkstart, int n_valid, int n_invalid) 2057 { 2058 qemu_put_be32(f, chunkstart); 2059 qemu_put_be16(f, n_valid); 2060 qemu_put_be16(f, n_invalid); 2061 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2062 HASH_PTE_SIZE_64 * n_valid); 2063 } 2064 2065 static void htab_save_end_marker(QEMUFile *f) 2066 { 2067 qemu_put_be32(f, 0); 2068 qemu_put_be16(f, 0); 2069 qemu_put_be16(f, 0); 2070 } 2071 2072 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2073 int64_t max_ns) 2074 { 2075 bool has_timeout = max_ns != -1; 2076 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2077 int index = spapr->htab_save_index; 2078 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2079 2080 assert(spapr->htab_first_pass); 2081 2082 do { 2083 int chunkstart; 2084 2085 /* Consume invalid HPTEs */ 2086 while ((index < htabslots) 2087 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2088 CLEAN_HPTE(HPTE(spapr->htab, index)); 2089 index++; 2090 } 2091 2092 /* Consume valid HPTEs */ 2093 chunkstart = index; 2094 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2095 && HPTE_VALID(HPTE(spapr->htab, index))) { 2096 CLEAN_HPTE(HPTE(spapr->htab, index)); 2097 index++; 2098 } 2099 2100 if (index > chunkstart) { 2101 int n_valid = index - chunkstart; 2102 2103 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2104 2105 if (has_timeout && 2106 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2107 break; 2108 } 2109 } 2110 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2111 2112 if (index >= htabslots) { 2113 assert(index == htabslots); 2114 index = 0; 2115 spapr->htab_first_pass = false; 2116 } 2117 spapr->htab_save_index = index; 2118 } 2119 2120 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2121 int64_t max_ns) 2122 { 2123 bool final = max_ns < 0; 2124 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2125 int examined = 0, sent = 0; 2126 int index = spapr->htab_save_index; 2127 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2128 2129 assert(!spapr->htab_first_pass); 2130 2131 do { 2132 int chunkstart, invalidstart; 2133 2134 /* Consume non-dirty HPTEs */ 2135 while ((index < htabslots) 2136 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2137 index++; 2138 examined++; 2139 } 2140 2141 chunkstart = index; 2142 /* Consume valid dirty HPTEs */ 2143 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2144 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2145 && HPTE_VALID(HPTE(spapr->htab, index))) { 2146 CLEAN_HPTE(HPTE(spapr->htab, index)); 2147 index++; 2148 examined++; 2149 } 2150 2151 invalidstart = index; 2152 /* Consume invalid dirty HPTEs */ 2153 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2154 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2155 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2156 CLEAN_HPTE(HPTE(spapr->htab, index)); 2157 index++; 2158 examined++; 2159 } 2160 2161 if (index > chunkstart) { 2162 int n_valid = invalidstart - chunkstart; 2163 int n_invalid = index - invalidstart; 2164 2165 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2166 sent += index - chunkstart; 2167 2168 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2169 break; 2170 } 2171 } 2172 2173 if (examined >= htabslots) { 2174 break; 2175 } 2176 2177 if (index >= htabslots) { 2178 assert(index == htabslots); 2179 index = 0; 2180 } 2181 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2182 2183 if (index >= htabslots) { 2184 assert(index == htabslots); 2185 index = 0; 2186 } 2187 2188 spapr->htab_save_index = index; 2189 2190 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2191 } 2192 2193 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2194 #define MAX_KVM_BUF_SIZE 2048 2195 2196 static int htab_save_iterate(QEMUFile *f, void *opaque) 2197 { 2198 SpaprMachineState *spapr = opaque; 2199 int fd; 2200 int rc = 0; 2201 2202 /* Iteration header */ 2203 if (!spapr->htab_shift) { 2204 qemu_put_be32(f, -1); 2205 return 1; 2206 } else { 2207 qemu_put_be32(f, 0); 2208 } 2209 2210 if (!spapr->htab) { 2211 assert(kvm_enabled()); 2212 2213 fd = get_htab_fd(spapr); 2214 if (fd < 0) { 2215 return fd; 2216 } 2217 2218 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2219 if (rc < 0) { 2220 return rc; 2221 } 2222 } else if (spapr->htab_first_pass) { 2223 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2224 } else { 2225 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2226 } 2227 2228 htab_save_end_marker(f); 2229 2230 return rc; 2231 } 2232 2233 static int htab_save_complete(QEMUFile *f, void *opaque) 2234 { 2235 SpaprMachineState *spapr = opaque; 2236 int fd; 2237 2238 /* Iteration header */ 2239 if (!spapr->htab_shift) { 2240 qemu_put_be32(f, -1); 2241 return 0; 2242 } else { 2243 qemu_put_be32(f, 0); 2244 } 2245 2246 if (!spapr->htab) { 2247 int rc; 2248 2249 assert(kvm_enabled()); 2250 2251 fd = get_htab_fd(spapr); 2252 if (fd < 0) { 2253 return fd; 2254 } 2255 2256 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2257 if (rc < 0) { 2258 return rc; 2259 } 2260 } else { 2261 if (spapr->htab_first_pass) { 2262 htab_save_first_pass(f, spapr, -1); 2263 } 2264 htab_save_later_pass(f, spapr, -1); 2265 } 2266 2267 /* End marker */ 2268 htab_save_end_marker(f); 2269 2270 return 0; 2271 } 2272 2273 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2274 { 2275 SpaprMachineState *spapr = opaque; 2276 uint32_t section_hdr; 2277 int fd = -1; 2278 Error *local_err = NULL; 2279 2280 if (version_id < 1 || version_id > 1) { 2281 error_report("htab_load() bad version"); 2282 return -EINVAL; 2283 } 2284 2285 section_hdr = qemu_get_be32(f); 2286 2287 if (section_hdr == -1) { 2288 spapr_free_hpt(spapr); 2289 return 0; 2290 } 2291 2292 if (section_hdr) { 2293 int ret; 2294 2295 /* First section gives the htab size */ 2296 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2297 if (ret < 0) { 2298 error_report_err(local_err); 2299 return ret; 2300 } 2301 return 0; 2302 } 2303 2304 if (!spapr->htab) { 2305 assert(kvm_enabled()); 2306 2307 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2308 if (fd < 0) { 2309 error_report_err(local_err); 2310 return fd; 2311 } 2312 } 2313 2314 while (true) { 2315 uint32_t index; 2316 uint16_t n_valid, n_invalid; 2317 2318 index = qemu_get_be32(f); 2319 n_valid = qemu_get_be16(f); 2320 n_invalid = qemu_get_be16(f); 2321 2322 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2323 /* End of Stream */ 2324 break; 2325 } 2326 2327 if ((index + n_valid + n_invalid) > 2328 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2329 /* Bad index in stream */ 2330 error_report( 2331 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2332 index, n_valid, n_invalid, spapr->htab_shift); 2333 return -EINVAL; 2334 } 2335 2336 if (spapr->htab) { 2337 if (n_valid) { 2338 qemu_get_buffer(f, HPTE(spapr->htab, index), 2339 HASH_PTE_SIZE_64 * n_valid); 2340 } 2341 if (n_invalid) { 2342 memset(HPTE(spapr->htab, index + n_valid), 0, 2343 HASH_PTE_SIZE_64 * n_invalid); 2344 } 2345 } else { 2346 int rc; 2347 2348 assert(fd >= 0); 2349 2350 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2351 &local_err); 2352 if (rc < 0) { 2353 error_report_err(local_err); 2354 return rc; 2355 } 2356 } 2357 } 2358 2359 if (!spapr->htab) { 2360 assert(fd >= 0); 2361 close(fd); 2362 } 2363 2364 return 0; 2365 } 2366 2367 static void htab_save_cleanup(void *opaque) 2368 { 2369 SpaprMachineState *spapr = opaque; 2370 2371 close_htab_fd(spapr); 2372 } 2373 2374 static SaveVMHandlers savevm_htab_handlers = { 2375 .save_setup = htab_save_setup, 2376 .save_live_iterate = htab_save_iterate, 2377 .save_live_complete_precopy = htab_save_complete, 2378 .save_cleanup = htab_save_cleanup, 2379 .load_state = htab_load, 2380 }; 2381 2382 static void spapr_boot_set(void *opaque, const char *boot_device, 2383 Error **errp) 2384 { 2385 MachineState *machine = MACHINE(opaque); 2386 machine->boot_order = g_strdup(boot_device); 2387 } 2388 2389 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2390 { 2391 MachineState *machine = MACHINE(spapr); 2392 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2393 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2394 int i; 2395 2396 for (i = 0; i < nr_lmbs; i++) { 2397 uint64_t addr; 2398 2399 addr = i * lmb_size + machine->device_memory->base; 2400 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2401 addr / lmb_size); 2402 } 2403 } 2404 2405 /* 2406 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2407 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2408 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2409 */ 2410 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2411 { 2412 int i; 2413 2414 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2415 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2416 " is not aligned to %" PRIu64 " MiB", 2417 machine->ram_size, 2418 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2419 return; 2420 } 2421 2422 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2423 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2424 " is not aligned to %" PRIu64 " MiB", 2425 machine->ram_size, 2426 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2427 return; 2428 } 2429 2430 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2431 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2432 error_setg(errp, 2433 "Node %d memory size 0x%" PRIx64 2434 " is not aligned to %" PRIu64 " MiB", 2435 i, machine->numa_state->nodes[i].node_mem, 2436 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2437 return; 2438 } 2439 } 2440 } 2441 2442 /* find cpu slot in machine->possible_cpus by core_id */ 2443 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2444 { 2445 int index = id / ms->smp.threads; 2446 2447 if (index >= ms->possible_cpus->len) { 2448 return NULL; 2449 } 2450 if (idx) { 2451 *idx = index; 2452 } 2453 return &ms->possible_cpus->cpus[index]; 2454 } 2455 2456 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2457 { 2458 MachineState *ms = MACHINE(spapr); 2459 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2460 Error *local_err = NULL; 2461 bool vsmt_user = !!spapr->vsmt; 2462 int kvm_smt = kvmppc_smt_threads(); 2463 int ret; 2464 unsigned int smp_threads = ms->smp.threads; 2465 2466 if (!kvm_enabled() && (smp_threads > 1)) { 2467 error_setg(errp, "TCG cannot support more than 1 thread/core " 2468 "on a pseries machine"); 2469 return; 2470 } 2471 if (!is_power_of_2(smp_threads)) { 2472 error_setg(errp, "Cannot support %d threads/core on a pseries " 2473 "machine because it must be a power of 2", smp_threads); 2474 return; 2475 } 2476 2477 /* Detemine the VSMT mode to use: */ 2478 if (vsmt_user) { 2479 if (spapr->vsmt < smp_threads) { 2480 error_setg(errp, "Cannot support VSMT mode %d" 2481 " because it must be >= threads/core (%d)", 2482 spapr->vsmt, smp_threads); 2483 return; 2484 } 2485 /* In this case, spapr->vsmt has been set by the command line */ 2486 } else if (!smc->smp_threads_vsmt) { 2487 /* 2488 * Default VSMT value is tricky, because we need it to be as 2489 * consistent as possible (for migration), but this requires 2490 * changing it for at least some existing cases. We pick 8 as 2491 * the value that we'd get with KVM on POWER8, the 2492 * overwhelmingly common case in production systems. 2493 */ 2494 spapr->vsmt = MAX(8, smp_threads); 2495 } else { 2496 spapr->vsmt = smp_threads; 2497 } 2498 2499 /* KVM: If necessary, set the SMT mode: */ 2500 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2501 ret = kvmppc_set_smt_threads(spapr->vsmt); 2502 if (ret) { 2503 /* Looks like KVM isn't able to change VSMT mode */ 2504 error_setg(&local_err, 2505 "Failed to set KVM's VSMT mode to %d (errno %d)", 2506 spapr->vsmt, ret); 2507 /* We can live with that if the default one is big enough 2508 * for the number of threads, and a submultiple of the one 2509 * we want. In this case we'll waste some vcpu ids, but 2510 * behaviour will be correct */ 2511 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2512 warn_report_err(local_err); 2513 } else { 2514 if (!vsmt_user) { 2515 error_append_hint(&local_err, 2516 "On PPC, a VM with %d threads/core" 2517 " on a host with %d threads/core" 2518 " requires the use of VSMT mode %d.\n", 2519 smp_threads, kvm_smt, spapr->vsmt); 2520 } 2521 kvmppc_error_append_smt_possible_hint(&local_err); 2522 error_propagate(errp, local_err); 2523 } 2524 } 2525 } 2526 /* else TCG: nothing to do currently */ 2527 } 2528 2529 static void spapr_init_cpus(SpaprMachineState *spapr) 2530 { 2531 MachineState *machine = MACHINE(spapr); 2532 MachineClass *mc = MACHINE_GET_CLASS(machine); 2533 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2534 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2535 const CPUArchIdList *possible_cpus; 2536 unsigned int smp_cpus = machine->smp.cpus; 2537 unsigned int smp_threads = machine->smp.threads; 2538 unsigned int max_cpus = machine->smp.max_cpus; 2539 int boot_cores_nr = smp_cpus / smp_threads; 2540 int i; 2541 2542 possible_cpus = mc->possible_cpu_arch_ids(machine); 2543 if (mc->has_hotpluggable_cpus) { 2544 if (smp_cpus % smp_threads) { 2545 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2546 smp_cpus, smp_threads); 2547 exit(1); 2548 } 2549 if (max_cpus % smp_threads) { 2550 error_report("max_cpus (%u) must be multiple of threads (%u)", 2551 max_cpus, smp_threads); 2552 exit(1); 2553 } 2554 } else { 2555 if (max_cpus != smp_cpus) { 2556 error_report("This machine version does not support CPU hotplug"); 2557 exit(1); 2558 } 2559 boot_cores_nr = possible_cpus->len; 2560 } 2561 2562 if (smc->pre_2_10_has_unused_icps) { 2563 int i; 2564 2565 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2566 /* Dummy entries get deregistered when real ICPState objects 2567 * are registered during CPU core hotplug. 2568 */ 2569 pre_2_10_vmstate_register_dummy_icp(i); 2570 } 2571 } 2572 2573 for (i = 0; i < possible_cpus->len; i++) { 2574 int core_id = i * smp_threads; 2575 2576 if (mc->has_hotpluggable_cpus) { 2577 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2578 spapr_vcpu_id(spapr, core_id)); 2579 } 2580 2581 if (i < boot_cores_nr) { 2582 Object *core = object_new(type); 2583 int nr_threads = smp_threads; 2584 2585 /* Handle the partially filled core for older machine types */ 2586 if ((i + 1) * smp_threads >= smp_cpus) { 2587 nr_threads = smp_cpus - i * smp_threads; 2588 } 2589 2590 object_property_set_int(core, "nr-threads", nr_threads, 2591 &error_fatal); 2592 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2593 &error_fatal); 2594 qdev_realize(DEVICE(core), NULL, &error_fatal); 2595 2596 object_unref(core); 2597 } 2598 } 2599 } 2600 2601 static PCIHostState *spapr_create_default_phb(void) 2602 { 2603 DeviceState *dev; 2604 2605 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2606 qdev_prop_set_uint32(dev, "index", 0); 2607 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2608 2609 return PCI_HOST_BRIDGE(dev); 2610 } 2611 2612 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2613 { 2614 MachineState *machine = MACHINE(spapr); 2615 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2616 hwaddr rma_size = machine->ram_size; 2617 hwaddr node0_size = spapr_node0_size(machine); 2618 2619 /* RMA has to fit in the first NUMA node */ 2620 rma_size = MIN(rma_size, node0_size); 2621 2622 /* 2623 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2624 * never exceed that 2625 */ 2626 rma_size = MIN(rma_size, 1 * TiB); 2627 2628 /* 2629 * Clamp the RMA size based on machine type. This is for 2630 * migration compatibility with older qemu versions, which limited 2631 * the RMA size for complicated and mostly bad reasons. 2632 */ 2633 if (smc->rma_limit) { 2634 rma_size = MIN(rma_size, smc->rma_limit); 2635 } 2636 2637 if (rma_size < MIN_RMA_SLOF) { 2638 error_setg(errp, 2639 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2640 "ldMiB guest RMA (Real Mode Area memory)", 2641 MIN_RMA_SLOF / MiB); 2642 return 0; 2643 } 2644 2645 return rma_size; 2646 } 2647 2648 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2649 { 2650 MachineState *machine = MACHINE(spapr); 2651 int i; 2652 2653 for (i = 0; i < machine->ram_slots; i++) { 2654 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2655 } 2656 } 2657 2658 /* pSeries LPAR / sPAPR hardware init */ 2659 static void spapr_machine_init(MachineState *machine) 2660 { 2661 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2662 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2663 MachineClass *mc = MACHINE_GET_CLASS(machine); 2664 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2665 const char *kernel_filename = machine->kernel_filename; 2666 const char *initrd_filename = machine->initrd_filename; 2667 PCIHostState *phb; 2668 int i; 2669 MemoryRegion *sysmem = get_system_memory(); 2670 long load_limit, fw_size; 2671 char *filename; 2672 Error *resize_hpt_err = NULL; 2673 2674 msi_nonbroken = true; 2675 2676 QLIST_INIT(&spapr->phbs); 2677 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2678 2679 /* Determine capabilities to run with */ 2680 spapr_caps_init(spapr); 2681 2682 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2683 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2684 /* 2685 * If the user explicitly requested a mode we should either 2686 * supply it, or fail completely (which we do below). But if 2687 * it's not set explicitly, we reset our mode to something 2688 * that works 2689 */ 2690 if (resize_hpt_err) { 2691 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2692 error_free(resize_hpt_err); 2693 resize_hpt_err = NULL; 2694 } else { 2695 spapr->resize_hpt = smc->resize_hpt_default; 2696 } 2697 } 2698 2699 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2700 2701 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2702 /* 2703 * User requested HPT resize, but this host can't supply it. Bail out 2704 */ 2705 error_report_err(resize_hpt_err); 2706 exit(1); 2707 } 2708 error_free(resize_hpt_err); 2709 2710 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2711 2712 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2713 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2714 2715 /* 2716 * VSMT must be set in order to be able to compute VCPU ids, ie to 2717 * call spapr_max_server_number() or spapr_vcpu_id(). 2718 */ 2719 spapr_set_vsmt_mode(spapr, &error_fatal); 2720 2721 /* Set up Interrupt Controller before we create the VCPUs */ 2722 spapr_irq_init(spapr, &error_fatal); 2723 2724 /* Set up containers for ibm,client-architecture-support negotiated options 2725 */ 2726 spapr->ov5 = spapr_ovec_new(); 2727 spapr->ov5_cas = spapr_ovec_new(); 2728 2729 if (smc->dr_lmb_enabled) { 2730 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2731 spapr_validate_node_memory(machine, &error_fatal); 2732 } 2733 2734 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2735 2736 /* advertise support for dedicated HP event source to guests */ 2737 if (spapr->use_hotplug_event_source) { 2738 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2739 } 2740 2741 /* advertise support for HPT resizing */ 2742 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2743 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2744 } 2745 2746 /* advertise support for ibm,dyamic-memory-v2 */ 2747 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2748 2749 /* advertise XIVE on POWER9 machines */ 2750 if (spapr->irq->xive) { 2751 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2752 } 2753 2754 /* init CPUs */ 2755 spapr_init_cpus(spapr); 2756 2757 /* 2758 * check we don't have a memory-less/cpu-less NUMA node 2759 * Firmware relies on the existing memory/cpu topology to provide the 2760 * NUMA topology to the kernel. 2761 * And the linux kernel needs to know the NUMA topology at start 2762 * to be able to hotplug CPUs later. 2763 */ 2764 if (machine->numa_state->num_nodes) { 2765 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2766 /* check for memory-less node */ 2767 if (machine->numa_state->nodes[i].node_mem == 0) { 2768 CPUState *cs; 2769 int found = 0; 2770 /* check for cpu-less node */ 2771 CPU_FOREACH(cs) { 2772 PowerPCCPU *cpu = POWERPC_CPU(cs); 2773 if (cpu->node_id == i) { 2774 found = 1; 2775 break; 2776 } 2777 } 2778 /* memory-less and cpu-less node */ 2779 if (!found) { 2780 error_report( 2781 "Memory-less/cpu-less nodes are not supported (node %d)", 2782 i); 2783 exit(1); 2784 } 2785 } 2786 } 2787 2788 } 2789 2790 /* 2791 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2792 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2793 * called from vPHB reset handler so we initialize the counter here. 2794 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2795 * must be equally distant from any other node. 2796 * The final value of spapr->gpu_numa_id is going to be written to 2797 * max-associativity-domains in spapr_build_fdt(). 2798 */ 2799 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2800 2801 /* Init numa_assoc_array */ 2802 spapr_numa_associativity_init(spapr, machine); 2803 2804 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2805 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2806 spapr->max_compat_pvr)) { 2807 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2808 /* KVM and TCG always allow GTSE with radix... */ 2809 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2810 } 2811 /* ... but not with hash (currently). */ 2812 2813 if (kvm_enabled()) { 2814 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2815 kvmppc_enable_logical_ci_hcalls(); 2816 kvmppc_enable_set_mode_hcall(); 2817 2818 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2819 kvmppc_enable_clear_ref_mod_hcalls(); 2820 2821 /* Enable H_PAGE_INIT */ 2822 kvmppc_enable_h_page_init(); 2823 } 2824 2825 /* map RAM */ 2826 memory_region_add_subregion(sysmem, 0, machine->ram); 2827 2828 /* always allocate the device memory information */ 2829 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2830 2831 /* initialize hotplug memory address space */ 2832 if (machine->ram_size < machine->maxram_size) { 2833 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2834 /* 2835 * Limit the number of hotpluggable memory slots to half the number 2836 * slots that KVM supports, leaving the other half for PCI and other 2837 * devices. However ensure that number of slots doesn't drop below 32. 2838 */ 2839 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2840 SPAPR_MAX_RAM_SLOTS; 2841 2842 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2843 max_memslots = SPAPR_MAX_RAM_SLOTS; 2844 } 2845 if (machine->ram_slots > max_memslots) { 2846 error_report("Specified number of memory slots %" 2847 PRIu64" exceeds max supported %d", 2848 machine->ram_slots, max_memslots); 2849 exit(1); 2850 } 2851 2852 machine->device_memory->base = ROUND_UP(machine->ram_size, 2853 SPAPR_DEVICE_MEM_ALIGN); 2854 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2855 "device-memory", device_mem_size); 2856 memory_region_add_subregion(sysmem, machine->device_memory->base, 2857 &machine->device_memory->mr); 2858 } 2859 2860 if (smc->dr_lmb_enabled) { 2861 spapr_create_lmb_dr_connectors(spapr); 2862 } 2863 2864 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2865 /* Create the error string for live migration blocker */ 2866 error_setg(&spapr->fwnmi_migration_blocker, 2867 "A machine check is being handled during migration. The handler" 2868 "may run and log hardware error on the destination"); 2869 } 2870 2871 if (mc->nvdimm_supported) { 2872 spapr_create_nvdimm_dr_connectors(spapr); 2873 } 2874 2875 /* Set up RTAS event infrastructure */ 2876 spapr_events_init(spapr); 2877 2878 /* Set up the RTC RTAS interfaces */ 2879 spapr_rtc_create(spapr); 2880 2881 /* Set up VIO bus */ 2882 spapr->vio_bus = spapr_vio_bus_init(); 2883 2884 for (i = 0; serial_hd(i); i++) { 2885 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2886 } 2887 2888 /* We always have at least the nvram device on VIO */ 2889 spapr_create_nvram(spapr); 2890 2891 /* 2892 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2893 * connectors (described in root DT node's "ibm,drc-types" property) 2894 * are pre-initialized here. additional child connectors (such as 2895 * connectors for a PHBs PCI slots) are added as needed during their 2896 * parent's realization. 2897 */ 2898 if (smc->dr_phb_enabled) { 2899 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2900 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2901 } 2902 } 2903 2904 /* Set up PCI */ 2905 spapr_pci_rtas_init(); 2906 2907 phb = spapr_create_default_phb(); 2908 2909 for (i = 0; i < nb_nics; i++) { 2910 NICInfo *nd = &nd_table[i]; 2911 2912 if (!nd->model) { 2913 nd->model = g_strdup("spapr-vlan"); 2914 } 2915 2916 if (g_str_equal(nd->model, "spapr-vlan") || 2917 g_str_equal(nd->model, "ibmveth")) { 2918 spapr_vlan_create(spapr->vio_bus, nd); 2919 } else { 2920 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2921 } 2922 } 2923 2924 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2925 spapr_vscsi_create(spapr->vio_bus); 2926 } 2927 2928 /* Graphics */ 2929 if (spapr_vga_init(phb->bus, &error_fatal)) { 2930 spapr->has_graphics = true; 2931 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2932 } 2933 2934 if (machine->usb) { 2935 if (smc->use_ohci_by_default) { 2936 pci_create_simple(phb->bus, -1, "pci-ohci"); 2937 } else { 2938 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2939 } 2940 2941 if (spapr->has_graphics) { 2942 USBBus *usb_bus = usb_bus_find(-1); 2943 2944 usb_create_simple(usb_bus, "usb-kbd"); 2945 usb_create_simple(usb_bus, "usb-mouse"); 2946 } 2947 } 2948 2949 if (kernel_filename) { 2950 spapr->kernel_size = load_elf(kernel_filename, NULL, 2951 translate_kernel_address, spapr, 2952 NULL, NULL, NULL, NULL, 1, 2953 PPC_ELF_MACHINE, 0, 0); 2954 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2955 spapr->kernel_size = load_elf(kernel_filename, NULL, 2956 translate_kernel_address, spapr, 2957 NULL, NULL, NULL, NULL, 0, 2958 PPC_ELF_MACHINE, 0, 0); 2959 spapr->kernel_le = spapr->kernel_size > 0; 2960 } 2961 if (spapr->kernel_size < 0) { 2962 error_report("error loading %s: %s", kernel_filename, 2963 load_elf_strerror(spapr->kernel_size)); 2964 exit(1); 2965 } 2966 2967 /* load initrd */ 2968 if (initrd_filename) { 2969 /* Try to locate the initrd in the gap between the kernel 2970 * and the firmware. Add a bit of space just in case 2971 */ 2972 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2973 + 0x1ffff) & ~0xffff; 2974 spapr->initrd_size = load_image_targphys(initrd_filename, 2975 spapr->initrd_base, 2976 load_limit 2977 - spapr->initrd_base); 2978 if (spapr->initrd_size < 0) { 2979 error_report("could not load initial ram disk '%s'", 2980 initrd_filename); 2981 exit(1); 2982 } 2983 } 2984 } 2985 2986 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2987 if (!filename) { 2988 error_report("Could not find LPAR firmware '%s'", bios_name); 2989 exit(1); 2990 } 2991 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2992 if (fw_size <= 0) { 2993 error_report("Could not load LPAR firmware '%s'", filename); 2994 exit(1); 2995 } 2996 g_free(filename); 2997 2998 /* FIXME: Should register things through the MachineState's qdev 2999 * interface, this is a legacy from the sPAPREnvironment structure 3000 * which predated MachineState but had a similar function */ 3001 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3002 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3003 &savevm_htab_handlers, spapr); 3004 3005 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3006 3007 qemu_register_boot_set(spapr_boot_set, spapr); 3008 3009 /* 3010 * Nothing needs to be done to resume a suspended guest because 3011 * suspending does not change the machine state, so no need for 3012 * a ->wakeup method. 3013 */ 3014 qemu_register_wakeup_support(); 3015 3016 if (kvm_enabled()) { 3017 /* to stop and start vmclock */ 3018 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3019 &spapr->tb); 3020 3021 kvmppc_spapr_enable_inkernel_multitce(); 3022 } 3023 3024 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3025 } 3026 3027 #define DEFAULT_KVM_TYPE "auto" 3028 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3029 { 3030 /* 3031 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3032 * accomodate the 'HV' and 'PV' formats that exists in the 3033 * wild. The 'auto' mode is being introduced already as 3034 * lower-case, thus we don't need to bother checking for 3035 * "AUTO". 3036 */ 3037 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3038 return 0; 3039 } 3040 3041 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3042 return 1; 3043 } 3044 3045 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3046 return 2; 3047 } 3048 3049 error_report("Unknown kvm-type specified '%s'", vm_type); 3050 exit(1); 3051 } 3052 3053 /* 3054 * Implementation of an interface to adjust firmware path 3055 * for the bootindex property handling. 3056 */ 3057 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3058 DeviceState *dev) 3059 { 3060 #define CAST(type, obj, name) \ 3061 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3062 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3063 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3064 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3065 3066 if (d) { 3067 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3068 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3069 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3070 3071 if (spapr) { 3072 /* 3073 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3074 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3075 * 0x8000 | (target << 8) | (bus << 5) | lun 3076 * (see the "Logical unit addressing format" table in SAM5) 3077 */ 3078 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3079 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3080 (uint64_t)id << 48); 3081 } else if (virtio) { 3082 /* 3083 * We use SRP luns of the form 01000000 | (target << 8) | lun 3084 * in the top 32 bits of the 64-bit LUN 3085 * Note: the quote above is from SLOF and it is wrong, 3086 * the actual binding is: 3087 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3088 */ 3089 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3090 if (d->lun >= 256) { 3091 /* Use the LUN "flat space addressing method" */ 3092 id |= 0x4000; 3093 } 3094 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3095 (uint64_t)id << 32); 3096 } else if (usb) { 3097 /* 3098 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3099 * in the top 32 bits of the 64-bit LUN 3100 */ 3101 unsigned usb_port = atoi(usb->port->path); 3102 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3103 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3104 (uint64_t)id << 32); 3105 } 3106 } 3107 3108 /* 3109 * SLOF probes the USB devices, and if it recognizes that the device is a 3110 * storage device, it changes its name to "storage" instead of "usb-host", 3111 * and additionally adds a child node for the SCSI LUN, so the correct 3112 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3113 */ 3114 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3115 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3116 if (usb_host_dev_is_scsi_storage(usbdev)) { 3117 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3118 } 3119 } 3120 3121 if (phb) { 3122 /* Replace "pci" with "pci@800000020000000" */ 3123 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3124 } 3125 3126 if (vsc) { 3127 /* Same logic as virtio above */ 3128 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3129 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3130 } 3131 3132 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3133 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3134 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3135 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3136 } 3137 3138 return NULL; 3139 } 3140 3141 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3142 { 3143 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3144 3145 return g_strdup(spapr->kvm_type); 3146 } 3147 3148 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3149 { 3150 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3151 3152 g_free(spapr->kvm_type); 3153 spapr->kvm_type = g_strdup(value); 3154 } 3155 3156 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3157 { 3158 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3159 3160 return spapr->use_hotplug_event_source; 3161 } 3162 3163 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3164 Error **errp) 3165 { 3166 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3167 3168 spapr->use_hotplug_event_source = value; 3169 } 3170 3171 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3172 { 3173 return true; 3174 } 3175 3176 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3177 { 3178 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3179 3180 switch (spapr->resize_hpt) { 3181 case SPAPR_RESIZE_HPT_DEFAULT: 3182 return g_strdup("default"); 3183 case SPAPR_RESIZE_HPT_DISABLED: 3184 return g_strdup("disabled"); 3185 case SPAPR_RESIZE_HPT_ENABLED: 3186 return g_strdup("enabled"); 3187 case SPAPR_RESIZE_HPT_REQUIRED: 3188 return g_strdup("required"); 3189 } 3190 g_assert_not_reached(); 3191 } 3192 3193 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3194 { 3195 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3196 3197 if (strcmp(value, "default") == 0) { 3198 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3199 } else if (strcmp(value, "disabled") == 0) { 3200 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3201 } else if (strcmp(value, "enabled") == 0) { 3202 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3203 } else if (strcmp(value, "required") == 0) { 3204 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3205 } else { 3206 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3207 } 3208 } 3209 3210 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3211 { 3212 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3213 3214 if (spapr->irq == &spapr_irq_xics_legacy) { 3215 return g_strdup("legacy"); 3216 } else if (spapr->irq == &spapr_irq_xics) { 3217 return g_strdup("xics"); 3218 } else if (spapr->irq == &spapr_irq_xive) { 3219 return g_strdup("xive"); 3220 } else if (spapr->irq == &spapr_irq_dual) { 3221 return g_strdup("dual"); 3222 } 3223 g_assert_not_reached(); 3224 } 3225 3226 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3227 { 3228 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3229 3230 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3231 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3232 return; 3233 } 3234 3235 /* The legacy IRQ backend can not be set */ 3236 if (strcmp(value, "xics") == 0) { 3237 spapr->irq = &spapr_irq_xics; 3238 } else if (strcmp(value, "xive") == 0) { 3239 spapr->irq = &spapr_irq_xive; 3240 } else if (strcmp(value, "dual") == 0) { 3241 spapr->irq = &spapr_irq_dual; 3242 } else { 3243 error_setg(errp, "Bad value for \"ic-mode\" property"); 3244 } 3245 } 3246 3247 static char *spapr_get_host_model(Object *obj, Error **errp) 3248 { 3249 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3250 3251 return g_strdup(spapr->host_model); 3252 } 3253 3254 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3255 { 3256 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3257 3258 g_free(spapr->host_model); 3259 spapr->host_model = g_strdup(value); 3260 } 3261 3262 static char *spapr_get_host_serial(Object *obj, Error **errp) 3263 { 3264 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3265 3266 return g_strdup(spapr->host_serial); 3267 } 3268 3269 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3270 { 3271 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3272 3273 g_free(spapr->host_serial); 3274 spapr->host_serial = g_strdup(value); 3275 } 3276 3277 static void spapr_instance_init(Object *obj) 3278 { 3279 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3280 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3281 MachineState *ms = MACHINE(spapr); 3282 MachineClass *mc = MACHINE_GET_CLASS(ms); 3283 3284 /* 3285 * NVDIMM support went live in 5.1 without considering that, in 3286 * other archs, the user needs to enable NVDIMM support with the 3287 * 'nvdimm' machine option and the default behavior is NVDIMM 3288 * support disabled. It is too late to roll back to the standard 3289 * behavior without breaking 5.1 guests. 3290 */ 3291 if (mc->nvdimm_supported) { 3292 ms->nvdimms_state->is_enabled = true; 3293 } 3294 3295 spapr->htab_fd = -1; 3296 spapr->use_hotplug_event_source = true; 3297 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3298 object_property_add_str(obj, "kvm-type", 3299 spapr_get_kvm_type, spapr_set_kvm_type); 3300 object_property_set_description(obj, "kvm-type", 3301 "Specifies the KVM virtualization mode (auto," 3302 " hv, pr). Defaults to 'auto'. This mode will use" 3303 " any available KVM module loaded in the host," 3304 " where kvm_hv takes precedence if both kvm_hv and" 3305 " kvm_pr are loaded."); 3306 object_property_add_bool(obj, "modern-hotplug-events", 3307 spapr_get_modern_hotplug_events, 3308 spapr_set_modern_hotplug_events); 3309 object_property_set_description(obj, "modern-hotplug-events", 3310 "Use dedicated hotplug event mechanism in" 3311 " place of standard EPOW events when possible" 3312 " (required for memory hot-unplug support)"); 3313 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3314 "Maximum permitted CPU compatibility mode"); 3315 3316 object_property_add_str(obj, "resize-hpt", 3317 spapr_get_resize_hpt, spapr_set_resize_hpt); 3318 object_property_set_description(obj, "resize-hpt", 3319 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3320 object_property_add_uint32_ptr(obj, "vsmt", 3321 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3322 object_property_set_description(obj, "vsmt", 3323 "Virtual SMT: KVM behaves as if this were" 3324 " the host's SMT mode"); 3325 3326 object_property_add_bool(obj, "vfio-no-msix-emulation", 3327 spapr_get_msix_emulation, NULL); 3328 3329 object_property_add_uint64_ptr(obj, "kernel-addr", 3330 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3331 object_property_set_description(obj, "kernel-addr", 3332 stringify(KERNEL_LOAD_ADDR) 3333 " for -kernel is the default"); 3334 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3335 /* The machine class defines the default interrupt controller mode */ 3336 spapr->irq = smc->irq; 3337 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3338 spapr_set_ic_mode); 3339 object_property_set_description(obj, "ic-mode", 3340 "Specifies the interrupt controller mode (xics, xive, dual)"); 3341 3342 object_property_add_str(obj, "host-model", 3343 spapr_get_host_model, spapr_set_host_model); 3344 object_property_set_description(obj, "host-model", 3345 "Host model to advertise in guest device tree"); 3346 object_property_add_str(obj, "host-serial", 3347 spapr_get_host_serial, spapr_set_host_serial); 3348 object_property_set_description(obj, "host-serial", 3349 "Host serial number to advertise in guest device tree"); 3350 } 3351 3352 static void spapr_machine_finalizefn(Object *obj) 3353 { 3354 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3355 3356 g_free(spapr->kvm_type); 3357 } 3358 3359 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3360 { 3361 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3362 PowerPCCPU *cpu = POWERPC_CPU(cs); 3363 CPUPPCState *env = &cpu->env; 3364 3365 cpu_synchronize_state(cs); 3366 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3367 if (spapr->fwnmi_system_reset_addr != -1) { 3368 uint64_t rtas_addr, addr; 3369 3370 /* get rtas addr from fdt */ 3371 rtas_addr = spapr_get_rtas_addr(); 3372 if (!rtas_addr) { 3373 qemu_system_guest_panicked(NULL); 3374 return; 3375 } 3376 3377 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3378 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3379 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3380 env->gpr[3] = addr; 3381 } 3382 ppc_cpu_do_system_reset(cs); 3383 if (spapr->fwnmi_system_reset_addr != -1) { 3384 env->nip = spapr->fwnmi_system_reset_addr; 3385 } 3386 } 3387 3388 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3389 { 3390 CPUState *cs; 3391 3392 CPU_FOREACH(cs) { 3393 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3394 } 3395 } 3396 3397 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3398 void *fdt, int *fdt_start_offset, Error **errp) 3399 { 3400 uint64_t addr; 3401 uint32_t node; 3402 3403 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3404 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3405 &error_abort); 3406 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3407 SPAPR_MEMORY_BLOCK_SIZE); 3408 return 0; 3409 } 3410 3411 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3412 bool dedicated_hp_event_source) 3413 { 3414 SpaprDrc *drc; 3415 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3416 int i; 3417 uint64_t addr = addr_start; 3418 bool hotplugged = spapr_drc_hotplugged(dev); 3419 3420 for (i = 0; i < nr_lmbs; i++) { 3421 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3422 addr / SPAPR_MEMORY_BLOCK_SIZE); 3423 g_assert(drc); 3424 3425 /* 3426 * memory_device_get_free_addr() provided a range of free addresses 3427 * that doesn't overlap with any existing mapping at pre-plug. The 3428 * corresponding LMB DRCs are thus assumed to be all attachable. 3429 */ 3430 spapr_drc_attach(drc, dev); 3431 if (!hotplugged) { 3432 spapr_drc_reset(drc); 3433 } 3434 addr += SPAPR_MEMORY_BLOCK_SIZE; 3435 } 3436 /* send hotplug notification to the 3437 * guest only in case of hotplugged memory 3438 */ 3439 if (hotplugged) { 3440 if (dedicated_hp_event_source) { 3441 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3442 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3443 g_assert(drc); 3444 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3445 nr_lmbs, 3446 spapr_drc_index(drc)); 3447 } else { 3448 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3449 nr_lmbs); 3450 } 3451 } 3452 } 3453 3454 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3455 { 3456 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3457 PCDIMMDevice *dimm = PC_DIMM(dev); 3458 uint64_t size, addr; 3459 int64_t slot; 3460 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3461 3462 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3463 3464 pc_dimm_plug(dimm, MACHINE(ms)); 3465 3466 if (!is_nvdimm) { 3467 addr = object_property_get_uint(OBJECT(dimm), 3468 PC_DIMM_ADDR_PROP, &error_abort); 3469 spapr_add_lmbs(dev, addr, size, 3470 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3471 } else { 3472 slot = object_property_get_int(OBJECT(dimm), 3473 PC_DIMM_SLOT_PROP, &error_abort); 3474 /* We should have valid slot number at this point */ 3475 g_assert(slot >= 0); 3476 spapr_add_nvdimm(dev, slot); 3477 } 3478 } 3479 3480 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3481 Error **errp) 3482 { 3483 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3484 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3485 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3486 PCDIMMDevice *dimm = PC_DIMM(dev); 3487 Error *local_err = NULL; 3488 uint64_t size; 3489 Object *memdev; 3490 hwaddr pagesize; 3491 3492 if (!smc->dr_lmb_enabled) { 3493 error_setg(errp, "Memory hotplug not supported for this machine"); 3494 return; 3495 } 3496 3497 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3498 if (local_err) { 3499 error_propagate(errp, local_err); 3500 return; 3501 } 3502 3503 if (is_nvdimm) { 3504 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3505 return; 3506 } 3507 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3508 error_setg(errp, "Hotplugged memory size must be a multiple of " 3509 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3510 return; 3511 } 3512 3513 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3514 &error_abort); 3515 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3516 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3517 return; 3518 } 3519 3520 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3521 } 3522 3523 struct SpaprDimmState { 3524 PCDIMMDevice *dimm; 3525 uint32_t nr_lmbs; 3526 QTAILQ_ENTRY(SpaprDimmState) next; 3527 }; 3528 3529 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3530 PCDIMMDevice *dimm) 3531 { 3532 SpaprDimmState *dimm_state = NULL; 3533 3534 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3535 if (dimm_state->dimm == dimm) { 3536 break; 3537 } 3538 } 3539 return dimm_state; 3540 } 3541 3542 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3543 uint32_t nr_lmbs, 3544 PCDIMMDevice *dimm) 3545 { 3546 SpaprDimmState *ds = NULL; 3547 3548 /* 3549 * If this request is for a DIMM whose removal had failed earlier 3550 * (due to guest's refusal to remove the LMBs), we would have this 3551 * dimm already in the pending_dimm_unplugs list. In that 3552 * case don't add again. 3553 */ 3554 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3555 if (!ds) { 3556 ds = g_malloc0(sizeof(SpaprDimmState)); 3557 ds->nr_lmbs = nr_lmbs; 3558 ds->dimm = dimm; 3559 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3560 } 3561 return ds; 3562 } 3563 3564 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3565 SpaprDimmState *dimm_state) 3566 { 3567 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3568 g_free(dimm_state); 3569 } 3570 3571 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3572 PCDIMMDevice *dimm) 3573 { 3574 SpaprDrc *drc; 3575 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3576 &error_abort); 3577 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3578 uint32_t avail_lmbs = 0; 3579 uint64_t addr_start, addr; 3580 int i; 3581 3582 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3583 &error_abort); 3584 3585 addr = addr_start; 3586 for (i = 0; i < nr_lmbs; i++) { 3587 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3588 addr / SPAPR_MEMORY_BLOCK_SIZE); 3589 g_assert(drc); 3590 if (drc->dev) { 3591 avail_lmbs++; 3592 } 3593 addr += SPAPR_MEMORY_BLOCK_SIZE; 3594 } 3595 3596 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3597 } 3598 3599 /* Callback to be called during DRC release. */ 3600 void spapr_lmb_release(DeviceState *dev) 3601 { 3602 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3603 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3604 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3605 3606 /* This information will get lost if a migration occurs 3607 * during the unplug process. In this case recover it. */ 3608 if (ds == NULL) { 3609 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3610 g_assert(ds); 3611 /* The DRC being examined by the caller at least must be counted */ 3612 g_assert(ds->nr_lmbs); 3613 } 3614 3615 if (--ds->nr_lmbs) { 3616 return; 3617 } 3618 3619 /* 3620 * Now that all the LMBs have been removed by the guest, call the 3621 * unplug handler chain. This can never fail. 3622 */ 3623 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3624 object_unparent(OBJECT(dev)); 3625 } 3626 3627 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3628 { 3629 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3630 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3631 3632 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3633 qdev_unrealize(dev); 3634 spapr_pending_dimm_unplugs_remove(spapr, ds); 3635 } 3636 3637 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3638 DeviceState *dev, Error **errp) 3639 { 3640 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3641 PCDIMMDevice *dimm = PC_DIMM(dev); 3642 uint32_t nr_lmbs; 3643 uint64_t size, addr_start, addr; 3644 int i; 3645 SpaprDrc *drc; 3646 3647 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3648 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3649 return; 3650 } 3651 3652 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3653 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3654 3655 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3656 &error_abort); 3657 3658 /* 3659 * An existing pending dimm state for this DIMM means that there is an 3660 * unplug operation in progress, waiting for the spapr_lmb_release 3661 * callback to complete the job (BQL can't cover that far). In this case, 3662 * bail out to avoid detaching DRCs that were already released. 3663 */ 3664 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3665 error_setg(errp, "Memory unplug already in progress for device %s", 3666 dev->id); 3667 return; 3668 } 3669 3670 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3671 3672 addr = addr_start; 3673 for (i = 0; i < nr_lmbs; i++) { 3674 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3675 addr / SPAPR_MEMORY_BLOCK_SIZE); 3676 g_assert(drc); 3677 3678 spapr_drc_detach(drc); 3679 addr += SPAPR_MEMORY_BLOCK_SIZE; 3680 } 3681 3682 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3683 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3684 g_assert(drc); 3685 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3686 nr_lmbs, spapr_drc_index(drc)); 3687 } 3688 3689 /* Callback to be called during DRC release. */ 3690 void spapr_core_release(DeviceState *dev) 3691 { 3692 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3693 3694 /* Call the unplug handler chain. This can never fail. */ 3695 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3696 object_unparent(OBJECT(dev)); 3697 } 3698 3699 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3700 { 3701 MachineState *ms = MACHINE(hotplug_dev); 3702 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3703 CPUCore *cc = CPU_CORE(dev); 3704 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3705 3706 if (smc->pre_2_10_has_unused_icps) { 3707 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3708 int i; 3709 3710 for (i = 0; i < cc->nr_threads; i++) { 3711 CPUState *cs = CPU(sc->threads[i]); 3712 3713 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3714 } 3715 } 3716 3717 assert(core_slot); 3718 core_slot->cpu = NULL; 3719 qdev_unrealize(dev); 3720 } 3721 3722 static 3723 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3724 Error **errp) 3725 { 3726 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3727 int index; 3728 SpaprDrc *drc; 3729 CPUCore *cc = CPU_CORE(dev); 3730 3731 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3732 error_setg(errp, "Unable to find CPU core with core-id: %d", 3733 cc->core_id); 3734 return; 3735 } 3736 if (index == 0) { 3737 error_setg(errp, "Boot CPU core may not be unplugged"); 3738 return; 3739 } 3740 3741 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3742 spapr_vcpu_id(spapr, cc->core_id)); 3743 g_assert(drc); 3744 3745 if (!spapr_drc_unplug_requested(drc)) { 3746 spapr_drc_detach(drc); 3747 spapr_hotplug_req_remove_by_index(drc); 3748 } 3749 } 3750 3751 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3752 void *fdt, int *fdt_start_offset, Error **errp) 3753 { 3754 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3755 CPUState *cs = CPU(core->threads[0]); 3756 PowerPCCPU *cpu = POWERPC_CPU(cs); 3757 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3758 int id = spapr_get_vcpu_id(cpu); 3759 char *nodename; 3760 int offset; 3761 3762 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3763 offset = fdt_add_subnode(fdt, 0, nodename); 3764 g_free(nodename); 3765 3766 spapr_dt_cpu(cs, fdt, offset, spapr); 3767 3768 *fdt_start_offset = offset; 3769 return 0; 3770 } 3771 3772 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3773 { 3774 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3775 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3776 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3777 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3778 CPUCore *cc = CPU_CORE(dev); 3779 CPUState *cs; 3780 SpaprDrc *drc; 3781 CPUArchId *core_slot; 3782 int index; 3783 bool hotplugged = spapr_drc_hotplugged(dev); 3784 int i; 3785 3786 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3787 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3788 3789 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3790 spapr_vcpu_id(spapr, cc->core_id)); 3791 3792 g_assert(drc || !mc->has_hotpluggable_cpus); 3793 3794 if (drc) { 3795 /* 3796 * spapr_core_pre_plug() already buys us this is a brand new 3797 * core being plugged into a free slot. Nothing should already 3798 * be attached to the corresponding DRC. 3799 */ 3800 spapr_drc_attach(drc, dev); 3801 3802 if (hotplugged) { 3803 /* 3804 * Send hotplug notification interrupt to the guest only 3805 * in case of hotplugged CPUs. 3806 */ 3807 spapr_hotplug_req_add_by_index(drc); 3808 } else { 3809 spapr_drc_reset(drc); 3810 } 3811 } 3812 3813 core_slot->cpu = OBJECT(dev); 3814 3815 /* 3816 * Set compatibility mode to match the boot CPU, which was either set 3817 * by the machine reset code or by CAS. This really shouldn't fail at 3818 * this point. 3819 */ 3820 if (hotplugged) { 3821 for (i = 0; i < cc->nr_threads; i++) { 3822 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3823 &error_abort); 3824 } 3825 } 3826 3827 if (smc->pre_2_10_has_unused_icps) { 3828 for (i = 0; i < cc->nr_threads; i++) { 3829 cs = CPU(core->threads[i]); 3830 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3831 } 3832 } 3833 } 3834 3835 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3836 Error **errp) 3837 { 3838 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3839 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3840 CPUCore *cc = CPU_CORE(dev); 3841 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3842 const char *type = object_get_typename(OBJECT(dev)); 3843 CPUArchId *core_slot; 3844 int index; 3845 unsigned int smp_threads = machine->smp.threads; 3846 3847 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3848 error_setg(errp, "CPU hotplug not supported for this machine"); 3849 return; 3850 } 3851 3852 if (strcmp(base_core_type, type)) { 3853 error_setg(errp, "CPU core type should be %s", base_core_type); 3854 return; 3855 } 3856 3857 if (cc->core_id % smp_threads) { 3858 error_setg(errp, "invalid core id %d", cc->core_id); 3859 return; 3860 } 3861 3862 /* 3863 * In general we should have homogeneous threads-per-core, but old 3864 * (pre hotplug support) machine types allow the last core to have 3865 * reduced threads as a compatibility hack for when we allowed 3866 * total vcpus not a multiple of threads-per-core. 3867 */ 3868 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3869 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3870 smp_threads); 3871 return; 3872 } 3873 3874 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3875 if (!core_slot) { 3876 error_setg(errp, "core id %d out of range", cc->core_id); 3877 return; 3878 } 3879 3880 if (core_slot->cpu) { 3881 error_setg(errp, "core %d already populated", cc->core_id); 3882 return; 3883 } 3884 3885 numa_cpu_pre_plug(core_slot, dev, errp); 3886 } 3887 3888 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3889 void *fdt, int *fdt_start_offset, Error **errp) 3890 { 3891 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3892 int intc_phandle; 3893 3894 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3895 if (intc_phandle <= 0) { 3896 return -1; 3897 } 3898 3899 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3900 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3901 return -1; 3902 } 3903 3904 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3905 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3906 3907 return 0; 3908 } 3909 3910 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3911 Error **errp) 3912 { 3913 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3914 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3915 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3916 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3917 SpaprDrc *drc; 3918 3919 if (dev->hotplugged && !smc->dr_phb_enabled) { 3920 error_setg(errp, "PHB hotplug not supported for this machine"); 3921 return false; 3922 } 3923 3924 if (sphb->index == (uint32_t)-1) { 3925 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3926 return false; 3927 } 3928 3929 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3930 if (drc && drc->dev) { 3931 error_setg(errp, "PHB %d already attached", sphb->index); 3932 return false; 3933 } 3934 3935 /* 3936 * This will check that sphb->index doesn't exceed the maximum number of 3937 * PHBs for the current machine type. 3938 */ 3939 return 3940 smc->phb_placement(spapr, sphb->index, 3941 &sphb->buid, &sphb->io_win_addr, 3942 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3943 windows_supported, sphb->dma_liobn, 3944 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3945 errp); 3946 } 3947 3948 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3949 { 3950 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3951 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3952 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3953 SpaprDrc *drc; 3954 bool hotplugged = spapr_drc_hotplugged(dev); 3955 3956 if (!smc->dr_phb_enabled) { 3957 return; 3958 } 3959 3960 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3961 /* hotplug hooks should check it's enabled before getting this far */ 3962 assert(drc); 3963 3964 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 3965 spapr_drc_attach(drc, dev); 3966 3967 if (hotplugged) { 3968 spapr_hotplug_req_add_by_index(drc); 3969 } else { 3970 spapr_drc_reset(drc); 3971 } 3972 } 3973 3974 void spapr_phb_release(DeviceState *dev) 3975 { 3976 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3977 3978 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3979 object_unparent(OBJECT(dev)); 3980 } 3981 3982 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3983 { 3984 qdev_unrealize(dev); 3985 } 3986 3987 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3988 DeviceState *dev, Error **errp) 3989 { 3990 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3991 SpaprDrc *drc; 3992 3993 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3994 assert(drc); 3995 3996 if (!spapr_drc_unplug_requested(drc)) { 3997 spapr_drc_detach(drc); 3998 spapr_hotplug_req_remove_by_index(drc); 3999 } 4000 } 4001 4002 static 4003 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4004 Error **errp) 4005 { 4006 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4007 4008 if (spapr->tpm_proxy != NULL) { 4009 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4010 return false; 4011 } 4012 4013 return true; 4014 } 4015 4016 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4017 { 4018 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4019 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4020 4021 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4022 g_assert(spapr->tpm_proxy == NULL); 4023 4024 spapr->tpm_proxy = tpm_proxy; 4025 } 4026 4027 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4028 { 4029 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4030 4031 qdev_unrealize(dev); 4032 object_unparent(OBJECT(dev)); 4033 spapr->tpm_proxy = NULL; 4034 } 4035 4036 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4037 DeviceState *dev, Error **errp) 4038 { 4039 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4040 spapr_memory_plug(hotplug_dev, dev); 4041 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4042 spapr_core_plug(hotplug_dev, dev); 4043 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4044 spapr_phb_plug(hotplug_dev, dev); 4045 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4046 spapr_tpm_proxy_plug(hotplug_dev, dev); 4047 } 4048 } 4049 4050 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4051 DeviceState *dev, Error **errp) 4052 { 4053 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4054 spapr_memory_unplug(hotplug_dev, dev); 4055 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4056 spapr_core_unplug(hotplug_dev, dev); 4057 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4058 spapr_phb_unplug(hotplug_dev, dev); 4059 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4060 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4061 } 4062 } 4063 4064 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4065 DeviceState *dev, Error **errp) 4066 { 4067 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4068 MachineClass *mc = MACHINE_GET_CLASS(sms); 4069 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4070 4071 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4072 if (!smc->pre_6_0_memory_unplug || 4073 spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4074 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4075 } else { 4076 /* NOTE: this means there is a window after guest reset, prior to 4077 * CAS negotiation, where unplug requests will fail due to the 4078 * capability not being detected yet. This is a bit different than 4079 * the case with PCI unplug, where the events will be queued and 4080 * eventually handled by the guest after boot 4081 */ 4082 error_setg(errp, "Memory hot unplug not supported for this guest"); 4083 } 4084 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4085 if (!mc->has_hotpluggable_cpus) { 4086 error_setg(errp, "CPU hot unplug not supported on this machine"); 4087 return; 4088 } 4089 spapr_core_unplug_request(hotplug_dev, dev, errp); 4090 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4091 if (!smc->dr_phb_enabled) { 4092 error_setg(errp, "PHB hot unplug not supported on this machine"); 4093 return; 4094 } 4095 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4096 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4097 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4098 } 4099 } 4100 4101 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4102 DeviceState *dev, Error **errp) 4103 { 4104 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4105 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4106 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4107 spapr_core_pre_plug(hotplug_dev, dev, errp); 4108 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4109 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4110 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4111 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4112 } 4113 } 4114 4115 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4116 DeviceState *dev) 4117 { 4118 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4119 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4120 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4121 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4122 return HOTPLUG_HANDLER(machine); 4123 } 4124 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4125 PCIDevice *pcidev = PCI_DEVICE(dev); 4126 PCIBus *root = pci_device_root_bus(pcidev); 4127 SpaprPhbState *phb = 4128 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4129 TYPE_SPAPR_PCI_HOST_BRIDGE); 4130 4131 if (phb) { 4132 return HOTPLUG_HANDLER(phb); 4133 } 4134 } 4135 return NULL; 4136 } 4137 4138 static CpuInstanceProperties 4139 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4140 { 4141 CPUArchId *core_slot; 4142 MachineClass *mc = MACHINE_GET_CLASS(machine); 4143 4144 /* make sure possible_cpu are intialized */ 4145 mc->possible_cpu_arch_ids(machine); 4146 /* get CPU core slot containing thread that matches cpu_index */ 4147 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4148 assert(core_slot); 4149 return core_slot->props; 4150 } 4151 4152 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4153 { 4154 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4155 } 4156 4157 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4158 { 4159 int i; 4160 unsigned int smp_threads = machine->smp.threads; 4161 unsigned int smp_cpus = machine->smp.cpus; 4162 const char *core_type; 4163 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4164 MachineClass *mc = MACHINE_GET_CLASS(machine); 4165 4166 if (!mc->has_hotpluggable_cpus) { 4167 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4168 } 4169 if (machine->possible_cpus) { 4170 assert(machine->possible_cpus->len == spapr_max_cores); 4171 return machine->possible_cpus; 4172 } 4173 4174 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4175 if (!core_type) { 4176 error_report("Unable to find sPAPR CPU Core definition"); 4177 exit(1); 4178 } 4179 4180 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4181 sizeof(CPUArchId) * spapr_max_cores); 4182 machine->possible_cpus->len = spapr_max_cores; 4183 for (i = 0; i < machine->possible_cpus->len; i++) { 4184 int core_id = i * smp_threads; 4185 4186 machine->possible_cpus->cpus[i].type = core_type; 4187 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4188 machine->possible_cpus->cpus[i].arch_id = core_id; 4189 machine->possible_cpus->cpus[i].props.has_core_id = true; 4190 machine->possible_cpus->cpus[i].props.core_id = core_id; 4191 } 4192 return machine->possible_cpus; 4193 } 4194 4195 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4196 uint64_t *buid, hwaddr *pio, 4197 hwaddr *mmio32, hwaddr *mmio64, 4198 unsigned n_dma, uint32_t *liobns, 4199 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4200 { 4201 /* 4202 * New-style PHB window placement. 4203 * 4204 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4205 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4206 * windows. 4207 * 4208 * Some guest kernels can't work with MMIO windows above 1<<46 4209 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4210 * 4211 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4212 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4213 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4214 * 1TiB 64-bit MMIO windows for each PHB. 4215 */ 4216 const uint64_t base_buid = 0x800000020000000ULL; 4217 int i; 4218 4219 /* Sanity check natural alignments */ 4220 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4221 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4222 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4223 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4224 /* Sanity check bounds */ 4225 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4226 SPAPR_PCI_MEM32_WIN_SIZE); 4227 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4228 SPAPR_PCI_MEM64_WIN_SIZE); 4229 4230 if (index >= SPAPR_MAX_PHBS) { 4231 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4232 SPAPR_MAX_PHBS - 1); 4233 return false; 4234 } 4235 4236 *buid = base_buid + index; 4237 for (i = 0; i < n_dma; ++i) { 4238 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4239 } 4240 4241 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4242 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4243 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4244 4245 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4246 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4247 return true; 4248 } 4249 4250 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4251 { 4252 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4253 4254 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4255 } 4256 4257 static void spapr_ics_resend(XICSFabric *dev) 4258 { 4259 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4260 4261 ics_resend(spapr->ics); 4262 } 4263 4264 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4265 { 4266 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4267 4268 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4269 } 4270 4271 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4272 Monitor *mon) 4273 { 4274 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4275 4276 spapr_irq_print_info(spapr, mon); 4277 monitor_printf(mon, "irqchip: %s\n", 4278 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4279 } 4280 4281 /* 4282 * This is a XIVE only operation 4283 */ 4284 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4285 uint8_t nvt_blk, uint32_t nvt_idx, 4286 bool cam_ignore, uint8_t priority, 4287 uint32_t logic_serv, XiveTCTXMatch *match) 4288 { 4289 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4290 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4291 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4292 int count; 4293 4294 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4295 priority, logic_serv, match); 4296 if (count < 0) { 4297 return count; 4298 } 4299 4300 /* 4301 * When we implement the save and restore of the thread interrupt 4302 * contexts in the enter/exit CPU handlers of the machine and the 4303 * escalations in QEMU, we should be able to handle non dispatched 4304 * vCPUs. 4305 * 4306 * Until this is done, the sPAPR machine should find at least one 4307 * matching context always. 4308 */ 4309 if (count == 0) { 4310 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4311 nvt_blk, nvt_idx); 4312 } 4313 4314 return count; 4315 } 4316 4317 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4318 { 4319 return cpu->vcpu_id; 4320 } 4321 4322 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4323 { 4324 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4325 MachineState *ms = MACHINE(spapr); 4326 int vcpu_id; 4327 4328 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4329 4330 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4331 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4332 error_append_hint(errp, "Adjust the number of cpus to %d " 4333 "or try to raise the number of threads per core\n", 4334 vcpu_id * ms->smp.threads / spapr->vsmt); 4335 return false; 4336 } 4337 4338 cpu->vcpu_id = vcpu_id; 4339 return true; 4340 } 4341 4342 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4343 { 4344 CPUState *cs; 4345 4346 CPU_FOREACH(cs) { 4347 PowerPCCPU *cpu = POWERPC_CPU(cs); 4348 4349 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4350 return cpu; 4351 } 4352 } 4353 4354 return NULL; 4355 } 4356 4357 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4358 { 4359 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4360 4361 /* These are only called by TCG, KVM maintains dispatch state */ 4362 4363 spapr_cpu->prod = false; 4364 if (spapr_cpu->vpa_addr) { 4365 CPUState *cs = CPU(cpu); 4366 uint32_t dispatch; 4367 4368 dispatch = ldl_be_phys(cs->as, 4369 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4370 dispatch++; 4371 if ((dispatch & 1) != 0) { 4372 qemu_log_mask(LOG_GUEST_ERROR, 4373 "VPA: incorrect dispatch counter value for " 4374 "dispatched partition %u, correcting.\n", dispatch); 4375 dispatch++; 4376 } 4377 stl_be_phys(cs->as, 4378 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4379 } 4380 } 4381 4382 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4383 { 4384 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4385 4386 if (spapr_cpu->vpa_addr) { 4387 CPUState *cs = CPU(cpu); 4388 uint32_t dispatch; 4389 4390 dispatch = ldl_be_phys(cs->as, 4391 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4392 dispatch++; 4393 if ((dispatch & 1) != 1) { 4394 qemu_log_mask(LOG_GUEST_ERROR, 4395 "VPA: incorrect dispatch counter value for " 4396 "preempted partition %u, correcting.\n", dispatch); 4397 dispatch++; 4398 } 4399 stl_be_phys(cs->as, 4400 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4401 } 4402 } 4403 4404 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4405 { 4406 MachineClass *mc = MACHINE_CLASS(oc); 4407 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4408 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4409 NMIClass *nc = NMI_CLASS(oc); 4410 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4411 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4412 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4413 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4414 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4415 4416 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4417 mc->ignore_boot_device_suffixes = true; 4418 4419 /* 4420 * We set up the default / latest behaviour here. The class_init 4421 * functions for the specific versioned machine types can override 4422 * these details for backwards compatibility 4423 */ 4424 mc->init = spapr_machine_init; 4425 mc->reset = spapr_machine_reset; 4426 mc->block_default_type = IF_SCSI; 4427 mc->max_cpus = 1024; 4428 mc->no_parallel = 1; 4429 mc->default_boot_order = ""; 4430 mc->default_ram_size = 512 * MiB; 4431 mc->default_ram_id = "ppc_spapr.ram"; 4432 mc->default_display = "std"; 4433 mc->kvm_type = spapr_kvm_type; 4434 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4435 mc->pci_allow_0_address = true; 4436 assert(!mc->get_hotplug_handler); 4437 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4438 hc->pre_plug = spapr_machine_device_pre_plug; 4439 hc->plug = spapr_machine_device_plug; 4440 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4441 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4442 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4443 hc->unplug_request = spapr_machine_device_unplug_request; 4444 hc->unplug = spapr_machine_device_unplug; 4445 4446 smc->dr_lmb_enabled = true; 4447 smc->update_dt_enabled = true; 4448 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4449 mc->has_hotpluggable_cpus = true; 4450 mc->nvdimm_supported = true; 4451 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4452 fwc->get_dev_path = spapr_get_fw_dev_path; 4453 nc->nmi_monitor_handler = spapr_nmi; 4454 smc->phb_placement = spapr_phb_placement; 4455 vhc->hypercall = emulate_spapr_hypercall; 4456 vhc->hpt_mask = spapr_hpt_mask; 4457 vhc->map_hptes = spapr_map_hptes; 4458 vhc->unmap_hptes = spapr_unmap_hptes; 4459 vhc->hpte_set_c = spapr_hpte_set_c; 4460 vhc->hpte_set_r = spapr_hpte_set_r; 4461 vhc->get_pate = spapr_get_pate; 4462 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4463 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4464 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4465 xic->ics_get = spapr_ics_get; 4466 xic->ics_resend = spapr_ics_resend; 4467 xic->icp_get = spapr_icp_get; 4468 ispc->print_info = spapr_pic_print_info; 4469 /* Force NUMA node memory size to be a multiple of 4470 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4471 * in which LMBs are represented and hot-added 4472 */ 4473 mc->numa_mem_align_shift = 28; 4474 mc->auto_enable_numa = true; 4475 4476 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4477 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4478 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4479 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4480 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4481 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4482 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4483 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4484 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4485 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4486 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4487 spapr_caps_add_properties(smc); 4488 smc->irq = &spapr_irq_dual; 4489 smc->dr_phb_enabled = true; 4490 smc->linux_pci_probe = true; 4491 smc->smp_threads_vsmt = true; 4492 smc->nr_xirqs = SPAPR_NR_XIRQS; 4493 xfc->match_nvt = spapr_match_nvt; 4494 } 4495 4496 static const TypeInfo spapr_machine_info = { 4497 .name = TYPE_SPAPR_MACHINE, 4498 .parent = TYPE_MACHINE, 4499 .abstract = true, 4500 .instance_size = sizeof(SpaprMachineState), 4501 .instance_init = spapr_instance_init, 4502 .instance_finalize = spapr_machine_finalizefn, 4503 .class_size = sizeof(SpaprMachineClass), 4504 .class_init = spapr_machine_class_init, 4505 .interfaces = (InterfaceInfo[]) { 4506 { TYPE_FW_PATH_PROVIDER }, 4507 { TYPE_NMI }, 4508 { TYPE_HOTPLUG_HANDLER }, 4509 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4510 { TYPE_XICS_FABRIC }, 4511 { TYPE_INTERRUPT_STATS_PROVIDER }, 4512 { TYPE_XIVE_FABRIC }, 4513 { } 4514 }, 4515 }; 4516 4517 static void spapr_machine_latest_class_options(MachineClass *mc) 4518 { 4519 mc->alias = "pseries"; 4520 mc->is_default = true; 4521 } 4522 4523 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4524 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4525 void *data) \ 4526 { \ 4527 MachineClass *mc = MACHINE_CLASS(oc); \ 4528 spapr_machine_##suffix##_class_options(mc); \ 4529 if (latest) { \ 4530 spapr_machine_latest_class_options(mc); \ 4531 } \ 4532 } \ 4533 static const TypeInfo spapr_machine_##suffix##_info = { \ 4534 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4535 .parent = TYPE_SPAPR_MACHINE, \ 4536 .class_init = spapr_machine_##suffix##_class_init, \ 4537 }; \ 4538 static void spapr_machine_register_##suffix(void) \ 4539 { \ 4540 type_register(&spapr_machine_##suffix##_info); \ 4541 } \ 4542 type_init(spapr_machine_register_##suffix) 4543 4544 /* 4545 * pseries-6.0 4546 */ 4547 static void spapr_machine_6_0_class_options(MachineClass *mc) 4548 { 4549 /* Defaults for the latest behaviour inherited from the base class */ 4550 } 4551 4552 DEFINE_SPAPR_MACHINE(6_0, "6.0", true); 4553 4554 /* 4555 * pseries-5.2 4556 */ 4557 static void spapr_machine_5_2_class_options(MachineClass *mc) 4558 { 4559 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4560 4561 spapr_machine_6_0_class_options(mc); 4562 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4563 smc->pre_6_0_memory_unplug = true; 4564 } 4565 4566 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4567 4568 /* 4569 * pseries-5.1 4570 */ 4571 static void spapr_machine_5_1_class_options(MachineClass *mc) 4572 { 4573 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4574 4575 spapr_machine_5_2_class_options(mc); 4576 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4577 smc->pre_5_2_numa_associativity = true; 4578 } 4579 4580 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4581 4582 /* 4583 * pseries-5.0 4584 */ 4585 static void spapr_machine_5_0_class_options(MachineClass *mc) 4586 { 4587 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4588 static GlobalProperty compat[] = { 4589 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4590 }; 4591 4592 spapr_machine_5_1_class_options(mc); 4593 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4594 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4595 mc->numa_mem_supported = true; 4596 smc->pre_5_1_assoc_refpoints = true; 4597 } 4598 4599 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4600 4601 /* 4602 * pseries-4.2 4603 */ 4604 static void spapr_machine_4_2_class_options(MachineClass *mc) 4605 { 4606 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4607 4608 spapr_machine_5_0_class_options(mc); 4609 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4610 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4611 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4612 smc->rma_limit = 16 * GiB; 4613 mc->nvdimm_supported = false; 4614 } 4615 4616 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4617 4618 /* 4619 * pseries-4.1 4620 */ 4621 static void spapr_machine_4_1_class_options(MachineClass *mc) 4622 { 4623 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4624 static GlobalProperty compat[] = { 4625 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4626 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4627 }; 4628 4629 spapr_machine_4_2_class_options(mc); 4630 smc->linux_pci_probe = false; 4631 smc->smp_threads_vsmt = false; 4632 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4633 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4634 } 4635 4636 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4637 4638 /* 4639 * pseries-4.0 4640 */ 4641 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4642 uint64_t *buid, hwaddr *pio, 4643 hwaddr *mmio32, hwaddr *mmio64, 4644 unsigned n_dma, uint32_t *liobns, 4645 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4646 { 4647 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4648 liobns, nv2gpa, nv2atsd, errp)) { 4649 return false; 4650 } 4651 4652 *nv2gpa = 0; 4653 *nv2atsd = 0; 4654 return true; 4655 } 4656 static void spapr_machine_4_0_class_options(MachineClass *mc) 4657 { 4658 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4659 4660 spapr_machine_4_1_class_options(mc); 4661 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4662 smc->phb_placement = phb_placement_4_0; 4663 smc->irq = &spapr_irq_xics; 4664 smc->pre_4_1_migration = true; 4665 } 4666 4667 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4668 4669 /* 4670 * pseries-3.1 4671 */ 4672 static void spapr_machine_3_1_class_options(MachineClass *mc) 4673 { 4674 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4675 4676 spapr_machine_4_0_class_options(mc); 4677 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4678 4679 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4680 smc->update_dt_enabled = false; 4681 smc->dr_phb_enabled = false; 4682 smc->broken_host_serial_model = true; 4683 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4684 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4685 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4686 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4687 } 4688 4689 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4690 4691 /* 4692 * pseries-3.0 4693 */ 4694 4695 static void spapr_machine_3_0_class_options(MachineClass *mc) 4696 { 4697 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4698 4699 spapr_machine_3_1_class_options(mc); 4700 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4701 4702 smc->legacy_irq_allocation = true; 4703 smc->nr_xirqs = 0x400; 4704 smc->irq = &spapr_irq_xics_legacy; 4705 } 4706 4707 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4708 4709 /* 4710 * pseries-2.12 4711 */ 4712 static void spapr_machine_2_12_class_options(MachineClass *mc) 4713 { 4714 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4715 static GlobalProperty compat[] = { 4716 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4717 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4718 }; 4719 4720 spapr_machine_3_0_class_options(mc); 4721 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4722 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4723 4724 /* We depend on kvm_enabled() to choose a default value for the 4725 * hpt-max-page-size capability. Of course we can't do it here 4726 * because this is too early and the HW accelerator isn't initialzed 4727 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4728 */ 4729 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4730 } 4731 4732 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4733 4734 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4735 { 4736 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4737 4738 spapr_machine_2_12_class_options(mc); 4739 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4740 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4741 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4742 } 4743 4744 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4745 4746 /* 4747 * pseries-2.11 4748 */ 4749 4750 static void spapr_machine_2_11_class_options(MachineClass *mc) 4751 { 4752 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4753 4754 spapr_machine_2_12_class_options(mc); 4755 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4756 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4757 } 4758 4759 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4760 4761 /* 4762 * pseries-2.10 4763 */ 4764 4765 static void spapr_machine_2_10_class_options(MachineClass *mc) 4766 { 4767 spapr_machine_2_11_class_options(mc); 4768 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4769 } 4770 4771 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4772 4773 /* 4774 * pseries-2.9 4775 */ 4776 4777 static void spapr_machine_2_9_class_options(MachineClass *mc) 4778 { 4779 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4780 static GlobalProperty compat[] = { 4781 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4782 }; 4783 4784 spapr_machine_2_10_class_options(mc); 4785 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4786 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4787 smc->pre_2_10_has_unused_icps = true; 4788 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4789 } 4790 4791 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4792 4793 /* 4794 * pseries-2.8 4795 */ 4796 4797 static void spapr_machine_2_8_class_options(MachineClass *mc) 4798 { 4799 static GlobalProperty compat[] = { 4800 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4801 }; 4802 4803 spapr_machine_2_9_class_options(mc); 4804 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4805 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4806 mc->numa_mem_align_shift = 23; 4807 } 4808 4809 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4810 4811 /* 4812 * pseries-2.7 4813 */ 4814 4815 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4816 uint64_t *buid, hwaddr *pio, 4817 hwaddr *mmio32, hwaddr *mmio64, 4818 unsigned n_dma, uint32_t *liobns, 4819 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4820 { 4821 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4822 const uint64_t base_buid = 0x800000020000000ULL; 4823 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4824 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4825 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4826 const uint32_t max_index = 255; 4827 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4828 4829 uint64_t ram_top = MACHINE(spapr)->ram_size; 4830 hwaddr phb0_base, phb_base; 4831 int i; 4832 4833 /* Do we have device memory? */ 4834 if (MACHINE(spapr)->maxram_size > ram_top) { 4835 /* Can't just use maxram_size, because there may be an 4836 * alignment gap between normal and device memory regions 4837 */ 4838 ram_top = MACHINE(spapr)->device_memory->base + 4839 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4840 } 4841 4842 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4843 4844 if (index > max_index) { 4845 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4846 max_index); 4847 return false; 4848 } 4849 4850 *buid = base_buid + index; 4851 for (i = 0; i < n_dma; ++i) { 4852 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4853 } 4854 4855 phb_base = phb0_base + index * phb_spacing; 4856 *pio = phb_base + pio_offset; 4857 *mmio32 = phb_base + mmio_offset; 4858 /* 4859 * We don't set the 64-bit MMIO window, relying on the PHB's 4860 * fallback behaviour of automatically splitting a large "32-bit" 4861 * window into contiguous 32-bit and 64-bit windows 4862 */ 4863 4864 *nv2gpa = 0; 4865 *nv2atsd = 0; 4866 return true; 4867 } 4868 4869 static void spapr_machine_2_7_class_options(MachineClass *mc) 4870 { 4871 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4872 static GlobalProperty compat[] = { 4873 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4874 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4875 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4876 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4877 }; 4878 4879 spapr_machine_2_8_class_options(mc); 4880 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4881 mc->default_machine_opts = "modern-hotplug-events=off"; 4882 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4883 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4884 smc->phb_placement = phb_placement_2_7; 4885 } 4886 4887 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4888 4889 /* 4890 * pseries-2.6 4891 */ 4892 4893 static void spapr_machine_2_6_class_options(MachineClass *mc) 4894 { 4895 static GlobalProperty compat[] = { 4896 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4897 }; 4898 4899 spapr_machine_2_7_class_options(mc); 4900 mc->has_hotpluggable_cpus = false; 4901 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4902 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4903 } 4904 4905 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4906 4907 /* 4908 * pseries-2.5 4909 */ 4910 4911 static void spapr_machine_2_5_class_options(MachineClass *mc) 4912 { 4913 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4914 static GlobalProperty compat[] = { 4915 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4916 }; 4917 4918 spapr_machine_2_6_class_options(mc); 4919 smc->use_ohci_by_default = true; 4920 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4921 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4922 } 4923 4924 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4925 4926 /* 4927 * pseries-2.4 4928 */ 4929 4930 static void spapr_machine_2_4_class_options(MachineClass *mc) 4931 { 4932 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4933 4934 spapr_machine_2_5_class_options(mc); 4935 smc->dr_lmb_enabled = false; 4936 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4937 } 4938 4939 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4940 4941 /* 4942 * pseries-2.3 4943 */ 4944 4945 static void spapr_machine_2_3_class_options(MachineClass *mc) 4946 { 4947 static GlobalProperty compat[] = { 4948 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4949 }; 4950 spapr_machine_2_4_class_options(mc); 4951 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4952 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4953 } 4954 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4955 4956 /* 4957 * pseries-2.2 4958 */ 4959 4960 static void spapr_machine_2_2_class_options(MachineClass *mc) 4961 { 4962 static GlobalProperty compat[] = { 4963 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4964 }; 4965 4966 spapr_machine_2_3_class_options(mc); 4967 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4968 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4969 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4970 } 4971 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4972 4973 /* 4974 * pseries-2.1 4975 */ 4976 4977 static void spapr_machine_2_1_class_options(MachineClass *mc) 4978 { 4979 spapr_machine_2_2_class_options(mc); 4980 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4981 } 4982 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4983 4984 static void spapr_machine_register_types(void) 4985 { 4986 type_register_static(&spapr_machine_info); 4987 } 4988 4989 type_init(spapr_machine_register_types) 4990