1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define FDT_MAX_SIZE 0x100000 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 /* Populate the "ibm,pa-features" property */ 221 static void spapr_populate_pa_features(SpaprMachineState *spapr, 222 PowerPCCPU *cpu, 223 void *fdt, int offset) 224 { 225 uint8_t pa_features_206[] = { 6, 0, 226 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 227 uint8_t pa_features_207[] = { 24, 0, 228 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 230 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 232 uint8_t pa_features_300[] = { 66, 0, 233 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 234 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 235 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 236 /* 6: DS207 */ 237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 238 /* 16: Vector */ 239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 240 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 242 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 244 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 245 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 246 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 248 /* 42: PM, 44: PC RA, 46: SC vec'd */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 250 /* 48: SIMD, 50: QP BFP, 52: String */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 252 /* 54: DecFP, 56: DecI, 58: SHA */ 253 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 254 /* 60: NM atomic, 62: RNG */ 255 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 256 }; 257 uint8_t *pa_features = NULL; 258 size_t pa_size; 259 260 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 261 pa_features = pa_features_206; 262 pa_size = sizeof(pa_features_206); 263 } 264 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 265 pa_features = pa_features_207; 266 pa_size = sizeof(pa_features_207); 267 } 268 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 269 pa_features = pa_features_300; 270 pa_size = sizeof(pa_features_300); 271 } 272 if (!pa_features) { 273 return; 274 } 275 276 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 277 /* 278 * Note: we keep CI large pages off by default because a 64K capable 279 * guest provisioned with large pages might otherwise try to map a qemu 280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 281 * even if that qemu runs on a 4k host. 282 * We dd this bit back here if we are confident this is not an issue 283 */ 284 pa_features[3] |= 0x20; 285 } 286 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 287 pa_features[24] |= 0x80; /* Transactional memory support */ 288 } 289 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 290 /* Workaround for broken kernels that attempt (guest) radix 291 * mode when they can't handle it, if they see the radix bit set 292 * in pa-features. So hide it from them. */ 293 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 294 } 295 296 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 297 } 298 299 static hwaddr spapr_node0_size(MachineState *machine) 300 { 301 if (machine->numa_state->num_nodes) { 302 int i; 303 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 304 if (machine->numa_state->nodes[i].node_mem) { 305 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 306 machine->ram_size); 307 } 308 } 309 } 310 return machine->ram_size; 311 } 312 313 static void add_str(GString *s, const gchar *s1) 314 { 315 g_string_append_len(s, s1, strlen(s1) + 1); 316 } 317 318 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 319 hwaddr size) 320 { 321 uint32_t associativity[] = { 322 cpu_to_be32(0x4), /* length */ 323 cpu_to_be32(0x0), cpu_to_be32(0x0), 324 cpu_to_be32(0x0), cpu_to_be32(nodeid) 325 }; 326 char mem_name[32]; 327 uint64_t mem_reg_property[2]; 328 int off; 329 330 mem_reg_property[0] = cpu_to_be64(start); 331 mem_reg_property[1] = cpu_to_be64(size); 332 333 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 334 off = fdt_add_subnode(fdt, 0, mem_name); 335 _FDT(off); 336 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 337 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 338 sizeof(mem_reg_property)))); 339 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 340 sizeof(associativity)))); 341 return off; 342 } 343 344 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 345 { 346 MemoryDeviceInfoList *info; 347 348 for (info = list; info; info = info->next) { 349 MemoryDeviceInfo *value = info->value; 350 351 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 352 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 353 354 if (addr >= pcdimm_info->addr && 355 addr < (pcdimm_info->addr + pcdimm_info->size)) { 356 return pcdimm_info->node; 357 } 358 } 359 } 360 361 return -1; 362 } 363 364 struct sPAPRDrconfCellV2 { 365 uint32_t seq_lmbs; 366 uint64_t base_addr; 367 uint32_t drc_index; 368 uint32_t aa_index; 369 uint32_t flags; 370 } QEMU_PACKED; 371 372 typedef struct DrconfCellQueue { 373 struct sPAPRDrconfCellV2 cell; 374 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 375 } DrconfCellQueue; 376 377 static DrconfCellQueue * 378 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 379 uint32_t drc_index, uint32_t aa_index, 380 uint32_t flags) 381 { 382 DrconfCellQueue *elem; 383 384 elem = g_malloc0(sizeof(*elem)); 385 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 386 elem->cell.base_addr = cpu_to_be64(base_addr); 387 elem->cell.drc_index = cpu_to_be32(drc_index); 388 elem->cell.aa_index = cpu_to_be32(aa_index); 389 elem->cell.flags = cpu_to_be32(flags); 390 391 return elem; 392 } 393 394 /* ibm,dynamic-memory-v2 */ 395 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 396 int offset, MemoryDeviceInfoList *dimms) 397 { 398 MachineState *machine = MACHINE(spapr); 399 uint8_t *int_buf, *cur_index; 400 int ret; 401 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 402 uint64_t addr, cur_addr, size; 403 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 404 uint64_t mem_end = machine->device_memory->base + 405 memory_region_size(&machine->device_memory->mr); 406 uint32_t node, buf_len, nr_entries = 0; 407 SpaprDrc *drc; 408 DrconfCellQueue *elem, *next; 409 MemoryDeviceInfoList *info; 410 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 411 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 412 413 /* Entry to cover RAM and the gap area */ 414 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 415 SPAPR_LMB_FLAGS_RESERVED | 416 SPAPR_LMB_FLAGS_DRC_INVALID); 417 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 418 nr_entries++; 419 420 cur_addr = machine->device_memory->base; 421 for (info = dimms; info; info = info->next) { 422 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 423 424 addr = di->addr; 425 size = di->size; 426 node = di->node; 427 428 /* 429 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 430 * area is marked hotpluggable in the next iteration for the bigger 431 * chunk including the NVDIMM occupied area. 432 */ 433 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 434 continue; 435 436 /* Entry for hot-pluggable area */ 437 if (cur_addr < addr) { 438 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 439 g_assert(drc); 440 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 441 cur_addr, spapr_drc_index(drc), -1, 0); 442 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 443 nr_entries++; 444 } 445 446 /* Entry for DIMM */ 447 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 448 g_assert(drc); 449 elem = spapr_get_drconf_cell(size / lmb_size, addr, 450 spapr_drc_index(drc), node, 451 SPAPR_LMB_FLAGS_ASSIGNED); 452 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 453 nr_entries++; 454 cur_addr = addr + size; 455 } 456 457 /* Entry for remaining hotpluggable area */ 458 if (cur_addr < mem_end) { 459 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 460 g_assert(drc); 461 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 462 cur_addr, spapr_drc_index(drc), -1, 0); 463 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 464 nr_entries++; 465 } 466 467 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 468 int_buf = cur_index = g_malloc0(buf_len); 469 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 470 cur_index += sizeof(nr_entries); 471 472 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 473 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 474 cur_index += sizeof(elem->cell); 475 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 476 g_free(elem); 477 } 478 479 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 480 g_free(int_buf); 481 if (ret < 0) { 482 return -1; 483 } 484 return 0; 485 } 486 487 /* ibm,dynamic-memory */ 488 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 489 int offset, MemoryDeviceInfoList *dimms) 490 { 491 MachineState *machine = MACHINE(spapr); 492 int i, ret; 493 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 494 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 495 uint32_t nr_lmbs = (machine->device_memory->base + 496 memory_region_size(&machine->device_memory->mr)) / 497 lmb_size; 498 uint32_t *int_buf, *cur_index, buf_len; 499 500 /* 501 * Allocate enough buffer size to fit in ibm,dynamic-memory 502 */ 503 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 504 cur_index = int_buf = g_malloc0(buf_len); 505 int_buf[0] = cpu_to_be32(nr_lmbs); 506 cur_index++; 507 for (i = 0; i < nr_lmbs; i++) { 508 uint64_t addr = i * lmb_size; 509 uint32_t *dynamic_memory = cur_index; 510 511 if (i >= device_lmb_start) { 512 SpaprDrc *drc; 513 514 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 515 g_assert(drc); 516 517 dynamic_memory[0] = cpu_to_be32(addr >> 32); 518 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 519 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 520 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 521 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 522 if (memory_region_present(get_system_memory(), addr)) { 523 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 524 } else { 525 dynamic_memory[5] = cpu_to_be32(0); 526 } 527 } else { 528 /* 529 * LMB information for RMA, boot time RAM and gap b/n RAM and 530 * device memory region -- all these are marked as reserved 531 * and as having no valid DRC. 532 */ 533 dynamic_memory[0] = cpu_to_be32(addr >> 32); 534 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 535 dynamic_memory[2] = cpu_to_be32(0); 536 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 537 dynamic_memory[4] = cpu_to_be32(-1); 538 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 539 SPAPR_LMB_FLAGS_DRC_INVALID); 540 } 541 542 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 543 } 544 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 545 g_free(int_buf); 546 if (ret < 0) { 547 return -1; 548 } 549 return 0; 550 } 551 552 /* 553 * Adds ibm,dynamic-reconfiguration-memory node. 554 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 555 * of this device tree node. 556 */ 557 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 558 { 559 MachineState *machine = MACHINE(spapr); 560 int nb_numa_nodes = machine->numa_state->num_nodes; 561 int ret, i, offset; 562 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 563 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 564 uint32_t *int_buf, *cur_index, buf_len; 565 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 566 MemoryDeviceInfoList *dimms = NULL; 567 568 /* 569 * Don't create the node if there is no device memory 570 */ 571 if (machine->ram_size == machine->maxram_size) { 572 return 0; 573 } 574 575 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 576 577 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 578 sizeof(prop_lmb_size)); 579 if (ret < 0) { 580 return ret; 581 } 582 583 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 584 if (ret < 0) { 585 return ret; 586 } 587 588 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 589 if (ret < 0) { 590 return ret; 591 } 592 593 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 594 dimms = qmp_memory_device_list(); 595 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 596 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 597 } else { 598 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 599 } 600 qapi_free_MemoryDeviceInfoList(dimms); 601 602 if (ret < 0) { 603 return ret; 604 } 605 606 /* ibm,associativity-lookup-arrays */ 607 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 608 cur_index = int_buf = g_malloc0(buf_len); 609 int_buf[0] = cpu_to_be32(nr_nodes); 610 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 611 cur_index += 2; 612 for (i = 0; i < nr_nodes; i++) { 613 uint32_t associativity[] = { 614 cpu_to_be32(0x0), 615 cpu_to_be32(0x0), 616 cpu_to_be32(0x0), 617 cpu_to_be32(i) 618 }; 619 memcpy(cur_index, associativity, sizeof(associativity)); 620 cur_index += 4; 621 } 622 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 623 (cur_index - int_buf) * sizeof(uint32_t)); 624 g_free(int_buf); 625 626 return ret; 627 } 628 629 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 630 { 631 MachineState *machine = MACHINE(spapr); 632 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 633 hwaddr mem_start, node_size; 634 int i, nb_nodes = machine->numa_state->num_nodes; 635 NodeInfo *nodes = machine->numa_state->nodes; 636 637 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 638 if (!nodes[i].node_mem) { 639 continue; 640 } 641 if (mem_start >= machine->ram_size) { 642 node_size = 0; 643 } else { 644 node_size = nodes[i].node_mem; 645 if (node_size > machine->ram_size - mem_start) { 646 node_size = machine->ram_size - mem_start; 647 } 648 } 649 if (!mem_start) { 650 /* spapr_machine_init() checks for rma_size <= node0_size 651 * already */ 652 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 653 mem_start += spapr->rma_size; 654 node_size -= spapr->rma_size; 655 } 656 for ( ; node_size; ) { 657 hwaddr sizetmp = pow2floor(node_size); 658 659 /* mem_start != 0 here */ 660 if (ctzl(mem_start) < ctzl(sizetmp)) { 661 sizetmp = 1ULL << ctzl(mem_start); 662 } 663 664 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 665 node_size -= sizetmp; 666 mem_start += sizetmp; 667 } 668 } 669 670 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 671 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 672 int ret; 673 674 g_assert(smc->dr_lmb_enabled); 675 ret = spapr_populate_drconf_memory(spapr, fdt); 676 if (ret) { 677 return ret; 678 } 679 } 680 681 return 0; 682 } 683 684 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 685 SpaprMachineState *spapr) 686 { 687 MachineState *ms = MACHINE(spapr); 688 PowerPCCPU *cpu = POWERPC_CPU(cs); 689 CPUPPCState *env = &cpu->env; 690 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 691 int index = spapr_get_vcpu_id(cpu); 692 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 693 0xffffffff, 0xffffffff}; 694 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 695 : SPAPR_TIMEBASE_FREQ; 696 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 697 uint32_t page_sizes_prop[64]; 698 size_t page_sizes_prop_size; 699 unsigned int smp_threads = ms->smp.threads; 700 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 701 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 702 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 703 SpaprDrc *drc; 704 int drc_index; 705 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 706 int i; 707 708 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 709 if (drc) { 710 drc_index = spapr_drc_index(drc); 711 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 712 } 713 714 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 715 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 716 717 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 718 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 719 env->dcache_line_size))); 720 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 721 env->dcache_line_size))); 722 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 723 env->icache_line_size))); 724 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 725 env->icache_line_size))); 726 727 if (pcc->l1_dcache_size) { 728 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 729 pcc->l1_dcache_size))); 730 } else { 731 warn_report("Unknown L1 dcache size for cpu"); 732 } 733 if (pcc->l1_icache_size) { 734 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 735 pcc->l1_icache_size))); 736 } else { 737 warn_report("Unknown L1 icache size for cpu"); 738 } 739 740 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 741 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 742 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 743 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 744 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 745 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 746 747 if (env->spr_cb[SPR_PURR].oea_read) { 748 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 749 } 750 if (env->spr_cb[SPR_SPURR].oea_read) { 751 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 752 } 753 754 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 755 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 756 segs, sizeof(segs)))); 757 } 758 759 /* Advertise VSX (vector extensions) if available 760 * 1 == VMX / Altivec available 761 * 2 == VSX available 762 * 763 * Only CPUs for which we create core types in spapr_cpu_core.c 764 * are possible, and all of those have VMX */ 765 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 767 } else { 768 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 769 } 770 771 /* Advertise DFP (Decimal Floating Point) if available 772 * 0 / no property == no DFP 773 * 1 == DFP available */ 774 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 775 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 776 } 777 778 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 779 sizeof(page_sizes_prop)); 780 if (page_sizes_prop_size) { 781 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 782 page_sizes_prop, page_sizes_prop_size))); 783 } 784 785 spapr_populate_pa_features(spapr, cpu, fdt, offset); 786 787 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 788 cs->cpu_index / vcpus_per_socket))); 789 790 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 791 pft_size_prop, sizeof(pft_size_prop)))); 792 793 if (ms->numa_state->num_nodes > 1) { 794 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 795 } 796 797 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 798 799 if (pcc->radix_page_info) { 800 for (i = 0; i < pcc->radix_page_info->count; i++) { 801 radix_AP_encodings[i] = 802 cpu_to_be32(pcc->radix_page_info->entries[i]); 803 } 804 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 805 radix_AP_encodings, 806 pcc->radix_page_info->count * 807 sizeof(radix_AP_encodings[0])))); 808 } 809 810 /* 811 * We set this property to let the guest know that it can use the large 812 * decrementer and its width in bits. 813 */ 814 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 815 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 816 pcc->lrg_decr_bits))); 817 } 818 819 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 820 { 821 CPUState **rev; 822 CPUState *cs; 823 int n_cpus; 824 int cpus_offset; 825 char *nodename; 826 int i; 827 828 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 829 _FDT(cpus_offset); 830 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 831 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 832 833 /* 834 * We walk the CPUs in reverse order to ensure that CPU DT nodes 835 * created by fdt_add_subnode() end up in the right order in FDT 836 * for the guest kernel the enumerate the CPUs correctly. 837 * 838 * The CPU list cannot be traversed in reverse order, so we need 839 * to do extra work. 840 */ 841 n_cpus = 0; 842 rev = NULL; 843 CPU_FOREACH(cs) { 844 rev = g_renew(CPUState *, rev, n_cpus + 1); 845 rev[n_cpus++] = cs; 846 } 847 848 for (i = n_cpus - 1; i >= 0; i--) { 849 CPUState *cs = rev[i]; 850 PowerPCCPU *cpu = POWERPC_CPU(cs); 851 int index = spapr_get_vcpu_id(cpu); 852 DeviceClass *dc = DEVICE_GET_CLASS(cs); 853 int offset; 854 855 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 856 continue; 857 } 858 859 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 860 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 861 g_free(nodename); 862 _FDT(offset); 863 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 864 } 865 866 g_free(rev); 867 } 868 869 static int spapr_rng_populate_dt(void *fdt) 870 { 871 int node; 872 int ret; 873 874 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 875 if (node <= 0) { 876 return -1; 877 } 878 ret = fdt_setprop_string(fdt, node, "device_type", 879 "ibm,platform-facilities"); 880 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 881 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 882 883 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 884 if (node <= 0) { 885 return -1; 886 } 887 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 888 889 return ret ? -1 : 0; 890 } 891 892 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 893 { 894 MachineState *ms = MACHINE(spapr); 895 int rtas; 896 GString *hypertas = g_string_sized_new(256); 897 GString *qemu_hypertas = g_string_sized_new(256); 898 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 899 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 900 memory_region_size(&MACHINE(spapr)->device_memory->mr); 901 uint32_t lrdr_capacity[] = { 902 cpu_to_be32(max_device_addr >> 32), 903 cpu_to_be32(max_device_addr & 0xffffffff), 904 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 905 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 906 }; 907 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 908 uint32_t maxdomains[] = { 909 cpu_to_be32(4), 910 maxdomain, 911 maxdomain, 912 maxdomain, 913 cpu_to_be32(spapr->gpu_numa_id), 914 }; 915 916 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 917 918 /* hypertas */ 919 add_str(hypertas, "hcall-pft"); 920 add_str(hypertas, "hcall-term"); 921 add_str(hypertas, "hcall-dabr"); 922 add_str(hypertas, "hcall-interrupt"); 923 add_str(hypertas, "hcall-tce"); 924 add_str(hypertas, "hcall-vio"); 925 add_str(hypertas, "hcall-splpar"); 926 add_str(hypertas, "hcall-join"); 927 add_str(hypertas, "hcall-bulk"); 928 add_str(hypertas, "hcall-set-mode"); 929 add_str(hypertas, "hcall-sprg0"); 930 add_str(hypertas, "hcall-copy"); 931 add_str(hypertas, "hcall-debug"); 932 add_str(hypertas, "hcall-vphn"); 933 add_str(qemu_hypertas, "hcall-memop1"); 934 935 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 936 add_str(hypertas, "hcall-multi-tce"); 937 } 938 939 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 940 add_str(hypertas, "hcall-hpt-resize"); 941 } 942 943 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 944 hypertas->str, hypertas->len)); 945 g_string_free(hypertas, TRUE); 946 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 947 qemu_hypertas->str, qemu_hypertas->len)); 948 g_string_free(qemu_hypertas, TRUE); 949 950 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 951 refpoints, sizeof(refpoints))); 952 953 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 954 maxdomains, sizeof(maxdomains))); 955 956 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_SIZE)); 957 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 958 RTAS_ERROR_LOG_MAX)); 959 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 960 RTAS_EVENT_SCAN_RATE)); 961 962 g_assert(msi_nonbroken); 963 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 964 965 /* 966 * According to PAPR, rtas ibm,os-term does not guarantee a return 967 * back to the guest cpu. 968 * 969 * While an additional ibm,extended-os-term property indicates 970 * that rtas call return will always occur. Set this property. 971 */ 972 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 973 974 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 975 lrdr_capacity, sizeof(lrdr_capacity))); 976 977 spapr_dt_rtas_tokens(fdt, rtas); 978 } 979 980 /* 981 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 982 * and the XIVE features that the guest may request and thus the valid 983 * values for bytes 23..26 of option vector 5: 984 */ 985 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 986 int chosen) 987 { 988 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 989 990 char val[2 * 4] = { 991 23, 0x00, /* XICS / XIVE mode */ 992 24, 0x00, /* Hash/Radix, filled in below. */ 993 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 994 26, 0x40, /* Radix options: GTSE == yes. */ 995 }; 996 997 if (spapr->irq->xics && spapr->irq->xive) { 998 val[1] = SPAPR_OV5_XIVE_BOTH; 999 } else if (spapr->irq->xive) { 1000 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1001 } else { 1002 assert(spapr->irq->xics); 1003 val[1] = SPAPR_OV5_XIVE_LEGACY; 1004 } 1005 1006 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1007 first_ppc_cpu->compat_pvr)) { 1008 /* 1009 * If we're in a pre POWER9 compat mode then the guest should 1010 * do hash and use the legacy interrupt mode 1011 */ 1012 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1013 val[3] = 0x00; /* Hash */ 1014 } else if (kvm_enabled()) { 1015 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1016 val[3] = 0x80; /* OV5_MMU_BOTH */ 1017 } else if (kvmppc_has_cap_mmu_radix()) { 1018 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1019 } else { 1020 val[3] = 0x00; /* Hash */ 1021 } 1022 } else { 1023 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1024 val[3] = 0xC0; 1025 } 1026 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1027 val, sizeof(val))); 1028 } 1029 1030 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1031 { 1032 MachineState *machine = MACHINE(spapr); 1033 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1034 int chosen; 1035 1036 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1037 1038 if (reset) { 1039 const char *boot_device = machine->boot_order; 1040 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1041 size_t cb = 0; 1042 char *bootlist = get_boot_devices_list(&cb); 1043 1044 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1045 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1046 machine->kernel_cmdline)); 1047 } 1048 1049 if (spapr->initrd_size) { 1050 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1051 spapr->initrd_base)); 1052 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1053 spapr->initrd_base + spapr->initrd_size)); 1054 } 1055 1056 if (spapr->kernel_size) { 1057 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1058 cpu_to_be64(spapr->kernel_size) }; 1059 1060 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1061 &kprop, sizeof(kprop))); 1062 if (spapr->kernel_le) { 1063 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1064 } 1065 } 1066 if (boot_menu) { 1067 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1068 } 1069 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1070 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1071 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1072 1073 if (cb && bootlist) { 1074 int i; 1075 1076 for (i = 0; i < cb; i++) { 1077 if (bootlist[i] == '\n') { 1078 bootlist[i] = ' '; 1079 } 1080 } 1081 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1082 } 1083 1084 if (boot_device && strlen(boot_device)) { 1085 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1086 } 1087 1088 if (!spapr->has_graphics && stdout_path) { 1089 /* 1090 * "linux,stdout-path" and "stdout" properties are 1091 * deprecated by linux kernel. New platforms should only 1092 * use the "stdout-path" property. Set the new property 1093 * and continue using older property to remain compatible 1094 * with the existing firmware. 1095 */ 1096 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1097 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1098 } 1099 1100 /* 1101 * We can deal with BAR reallocation just fine, advertise it 1102 * to the guest 1103 */ 1104 if (smc->linux_pci_probe) { 1105 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1106 } 1107 1108 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1109 1110 g_free(stdout_path); 1111 g_free(bootlist); 1112 } 1113 1114 _FDT(spapr_ovec_populate_dt(fdt, chosen, spapr->ov5_cas, 1115 "ibm,architecture-vec-5")); 1116 } 1117 1118 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1119 { 1120 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1121 * KVM to work under pHyp with some guest co-operation */ 1122 int hypervisor; 1123 uint8_t hypercall[16]; 1124 1125 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1126 /* indicate KVM hypercall interface */ 1127 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1128 if (kvmppc_has_cap_fixup_hcalls()) { 1129 /* 1130 * Older KVM versions with older guest kernels were broken 1131 * with the magic page, don't allow the guest to map it. 1132 */ 1133 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1134 sizeof(hypercall))) { 1135 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1136 hypercall, sizeof(hypercall))); 1137 } 1138 } 1139 } 1140 1141 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1142 { 1143 MachineState *machine = MACHINE(spapr); 1144 MachineClass *mc = MACHINE_GET_CLASS(machine); 1145 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1146 int ret; 1147 void *fdt; 1148 SpaprPhbState *phb; 1149 char *buf; 1150 1151 fdt = g_malloc0(space); 1152 _FDT((fdt_create_empty_tree(fdt, space))); 1153 1154 /* Root node */ 1155 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1156 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1157 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1158 1159 /* Guest UUID & Name*/ 1160 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1161 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1162 if (qemu_uuid_set) { 1163 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1164 } 1165 g_free(buf); 1166 1167 if (qemu_get_vm_name()) { 1168 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1169 qemu_get_vm_name())); 1170 } 1171 1172 /* Host Model & Serial Number */ 1173 if (spapr->host_model) { 1174 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1175 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1176 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1177 g_free(buf); 1178 } 1179 1180 if (spapr->host_serial) { 1181 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1182 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1183 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1184 g_free(buf); 1185 } 1186 1187 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1188 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1189 1190 /* /interrupt controller */ 1191 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1192 1193 ret = spapr_populate_memory(spapr, fdt); 1194 if (ret < 0) { 1195 error_report("couldn't setup memory nodes in fdt"); 1196 exit(1); 1197 } 1198 1199 /* /vdevice */ 1200 spapr_dt_vdevice(spapr->vio_bus, fdt); 1201 1202 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1203 ret = spapr_rng_populate_dt(fdt); 1204 if (ret < 0) { 1205 error_report("could not set up rng device in the fdt"); 1206 exit(1); 1207 } 1208 } 1209 1210 QLIST_FOREACH(phb, &spapr->phbs, list) { 1211 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1212 if (ret < 0) { 1213 error_report("couldn't setup PCI devices in fdt"); 1214 exit(1); 1215 } 1216 } 1217 1218 /* cpus */ 1219 spapr_populate_cpus_dt_node(fdt, spapr); 1220 1221 if (smc->dr_lmb_enabled) { 1222 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1223 } 1224 1225 if (mc->has_hotpluggable_cpus) { 1226 int offset = fdt_path_offset(fdt, "/cpus"); 1227 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1228 if (ret < 0) { 1229 error_report("Couldn't set up CPU DR device tree properties"); 1230 exit(1); 1231 } 1232 } 1233 1234 /* /event-sources */ 1235 spapr_dt_events(spapr, fdt); 1236 1237 /* /rtas */ 1238 spapr_dt_rtas(spapr, fdt); 1239 1240 /* /chosen */ 1241 spapr_dt_chosen(spapr, fdt, reset); 1242 1243 /* /hypervisor */ 1244 if (kvm_enabled()) { 1245 spapr_dt_hypervisor(spapr, fdt); 1246 } 1247 1248 /* Build memory reserve map */ 1249 if (reset) { 1250 if (spapr->kernel_size) { 1251 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1252 spapr->kernel_size))); 1253 } 1254 if (spapr->initrd_size) { 1255 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1256 spapr->initrd_size))); 1257 } 1258 } 1259 1260 if (smc->dr_phb_enabled) { 1261 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1262 if (ret < 0) { 1263 error_report("Couldn't set up PHB DR device tree properties"); 1264 exit(1); 1265 } 1266 } 1267 1268 /* NVDIMM devices */ 1269 if (mc->nvdimm_supported) { 1270 spapr_dt_persistent_memory(fdt); 1271 } 1272 1273 return fdt; 1274 } 1275 1276 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1277 { 1278 SpaprMachineState *spapr = opaque; 1279 1280 return (addr & 0x0fffffff) + spapr->kernel_addr; 1281 } 1282 1283 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1284 PowerPCCPU *cpu) 1285 { 1286 CPUPPCState *env = &cpu->env; 1287 1288 /* The TCG path should also be holding the BQL at this point */ 1289 g_assert(qemu_mutex_iothread_locked()); 1290 1291 if (msr_pr) { 1292 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1293 env->gpr[3] = H_PRIVILEGE; 1294 } else { 1295 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1296 } 1297 } 1298 1299 struct LPCRSyncState { 1300 target_ulong value; 1301 target_ulong mask; 1302 }; 1303 1304 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1305 { 1306 struct LPCRSyncState *s = arg.host_ptr; 1307 PowerPCCPU *cpu = POWERPC_CPU(cs); 1308 CPUPPCState *env = &cpu->env; 1309 target_ulong lpcr; 1310 1311 cpu_synchronize_state(cs); 1312 lpcr = env->spr[SPR_LPCR]; 1313 lpcr &= ~s->mask; 1314 lpcr |= s->value; 1315 ppc_store_lpcr(cpu, lpcr); 1316 } 1317 1318 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1319 { 1320 CPUState *cs; 1321 struct LPCRSyncState s = { 1322 .value = value, 1323 .mask = mask 1324 }; 1325 CPU_FOREACH(cs) { 1326 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1327 } 1328 } 1329 1330 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1331 { 1332 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1333 1334 /* Copy PATE1:GR into PATE0:HR */ 1335 entry->dw0 = spapr->patb_entry & PATE0_HR; 1336 entry->dw1 = spapr->patb_entry; 1337 } 1338 1339 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1340 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1341 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1342 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1343 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1344 1345 /* 1346 * Get the fd to access the kernel htab, re-opening it if necessary 1347 */ 1348 static int get_htab_fd(SpaprMachineState *spapr) 1349 { 1350 Error *local_err = NULL; 1351 1352 if (spapr->htab_fd >= 0) { 1353 return spapr->htab_fd; 1354 } 1355 1356 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1357 if (spapr->htab_fd < 0) { 1358 error_report_err(local_err); 1359 } 1360 1361 return spapr->htab_fd; 1362 } 1363 1364 void close_htab_fd(SpaprMachineState *spapr) 1365 { 1366 if (spapr->htab_fd >= 0) { 1367 close(spapr->htab_fd); 1368 } 1369 spapr->htab_fd = -1; 1370 } 1371 1372 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1373 { 1374 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1375 1376 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1377 } 1378 1379 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1380 { 1381 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1382 1383 assert(kvm_enabled()); 1384 1385 if (!spapr->htab) { 1386 return 0; 1387 } 1388 1389 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1390 } 1391 1392 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1393 hwaddr ptex, int n) 1394 { 1395 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1396 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1397 1398 if (!spapr->htab) { 1399 /* 1400 * HTAB is controlled by KVM. Fetch into temporary buffer 1401 */ 1402 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1403 kvmppc_read_hptes(hptes, ptex, n); 1404 return hptes; 1405 } 1406 1407 /* 1408 * HTAB is controlled by QEMU. Just point to the internally 1409 * accessible PTEG. 1410 */ 1411 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1412 } 1413 1414 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1415 const ppc_hash_pte64_t *hptes, 1416 hwaddr ptex, int n) 1417 { 1418 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1419 1420 if (!spapr->htab) { 1421 g_free((void *)hptes); 1422 } 1423 1424 /* Nothing to do for qemu managed HPT */ 1425 } 1426 1427 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1428 uint64_t pte0, uint64_t pte1) 1429 { 1430 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1431 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1432 1433 if (!spapr->htab) { 1434 kvmppc_write_hpte(ptex, pte0, pte1); 1435 } else { 1436 if (pte0 & HPTE64_V_VALID) { 1437 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1438 /* 1439 * When setting valid, we write PTE1 first. This ensures 1440 * proper synchronization with the reading code in 1441 * ppc_hash64_pteg_search() 1442 */ 1443 smp_wmb(); 1444 stq_p(spapr->htab + offset, pte0); 1445 } else { 1446 stq_p(spapr->htab + offset, pte0); 1447 /* 1448 * When clearing it we set PTE0 first. This ensures proper 1449 * synchronization with the reading code in 1450 * ppc_hash64_pteg_search() 1451 */ 1452 smp_wmb(); 1453 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1454 } 1455 } 1456 } 1457 1458 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1459 uint64_t pte1) 1460 { 1461 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1462 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1463 1464 if (!spapr->htab) { 1465 /* There should always be a hash table when this is called */ 1466 error_report("spapr_hpte_set_c called with no hash table !"); 1467 return; 1468 } 1469 1470 /* The HW performs a non-atomic byte update */ 1471 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1472 } 1473 1474 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1475 uint64_t pte1) 1476 { 1477 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1478 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1479 1480 if (!spapr->htab) { 1481 /* There should always be a hash table when this is called */ 1482 error_report("spapr_hpte_set_r called with no hash table !"); 1483 return; 1484 } 1485 1486 /* The HW performs a non-atomic byte update */ 1487 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1488 } 1489 1490 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1491 { 1492 int shift; 1493 1494 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1495 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1496 * that's much more than is needed for Linux guests */ 1497 shift = ctz64(pow2ceil(ramsize)) - 7; 1498 shift = MAX(shift, 18); /* Minimum architected size */ 1499 shift = MIN(shift, 46); /* Maximum architected size */ 1500 return shift; 1501 } 1502 1503 void spapr_free_hpt(SpaprMachineState *spapr) 1504 { 1505 g_free(spapr->htab); 1506 spapr->htab = NULL; 1507 spapr->htab_shift = 0; 1508 close_htab_fd(spapr); 1509 } 1510 1511 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1512 Error **errp) 1513 { 1514 long rc; 1515 1516 /* Clean up any HPT info from a previous boot */ 1517 spapr_free_hpt(spapr); 1518 1519 rc = kvmppc_reset_htab(shift); 1520 if (rc < 0) { 1521 /* kernel-side HPT needed, but couldn't allocate one */ 1522 error_setg_errno(errp, errno, 1523 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1524 shift); 1525 /* This is almost certainly fatal, but if the caller really 1526 * wants to carry on with shift == 0, it's welcome to try */ 1527 } else if (rc > 0) { 1528 /* kernel-side HPT allocated */ 1529 if (rc != shift) { 1530 error_setg(errp, 1531 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1532 shift, rc); 1533 } 1534 1535 spapr->htab_shift = shift; 1536 spapr->htab = NULL; 1537 } else { 1538 /* kernel-side HPT not needed, allocate in userspace instead */ 1539 size_t size = 1ULL << shift; 1540 int i; 1541 1542 spapr->htab = qemu_memalign(size, size); 1543 if (!spapr->htab) { 1544 error_setg_errno(errp, errno, 1545 "Could not allocate HPT of order %d", shift); 1546 return; 1547 } 1548 1549 memset(spapr->htab, 0, size); 1550 spapr->htab_shift = shift; 1551 1552 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1553 DIRTY_HPTE(HPTE(spapr->htab, i)); 1554 } 1555 } 1556 /* We're setting up a hash table, so that means we're not radix */ 1557 spapr->patb_entry = 0; 1558 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1559 } 1560 1561 void spapr_setup_hpt(SpaprMachineState *spapr) 1562 { 1563 int hpt_shift; 1564 1565 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1566 || (spapr->cas_reboot 1567 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1568 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1569 } else { 1570 uint64_t current_ram_size; 1571 1572 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1573 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1574 } 1575 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1576 1577 if (kvm_enabled()) { 1578 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1579 1580 /* Check our RMA fits in the possible VRMA */ 1581 if (vrma_limit < spapr->rma_size) { 1582 error_report("Unable to create %" HWADDR_PRIu 1583 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1584 spapr->rma_size / MiB, vrma_limit / MiB); 1585 exit(EXIT_FAILURE); 1586 } 1587 } 1588 } 1589 1590 static int spapr_reset_drcs(Object *child, void *opaque) 1591 { 1592 SpaprDrc *drc = 1593 (SpaprDrc *) object_dynamic_cast(child, 1594 TYPE_SPAPR_DR_CONNECTOR); 1595 1596 if (drc) { 1597 spapr_drc_reset(drc); 1598 } 1599 1600 return 0; 1601 } 1602 1603 static void spapr_machine_reset(MachineState *machine) 1604 { 1605 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1606 PowerPCCPU *first_ppc_cpu; 1607 hwaddr fdt_addr; 1608 void *fdt; 1609 int rc; 1610 1611 kvmppc_svm_off(&error_fatal); 1612 spapr_caps_apply(spapr); 1613 1614 first_ppc_cpu = POWERPC_CPU(first_cpu); 1615 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1616 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1617 spapr->max_compat_pvr)) { 1618 /* 1619 * If using KVM with radix mode available, VCPUs can be started 1620 * without a HPT because KVM will start them in radix mode. 1621 * Set the GR bit in PATE so that we know there is no HPT. 1622 */ 1623 spapr->patb_entry = PATE1_GR; 1624 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1625 } else { 1626 spapr_setup_hpt(spapr); 1627 } 1628 1629 qemu_devices_reset(); 1630 1631 /* 1632 * If this reset wasn't generated by CAS, we should reset our 1633 * negotiated options and start from scratch 1634 */ 1635 if (!spapr->cas_reboot) { 1636 spapr_ovec_cleanup(spapr->ov5_cas); 1637 spapr->ov5_cas = spapr_ovec_new(); 1638 1639 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1640 } 1641 1642 /* 1643 * This is fixing some of the default configuration of the XIVE 1644 * devices. To be called after the reset of the machine devices. 1645 */ 1646 spapr_irq_reset(spapr, &error_fatal); 1647 1648 /* 1649 * There is no CAS under qtest. Simulate one to please the code that 1650 * depends on spapr->ov5_cas. This is especially needed to test device 1651 * unplug, so we do that before resetting the DRCs. 1652 */ 1653 if (qtest_enabled()) { 1654 spapr_ovec_cleanup(spapr->ov5_cas); 1655 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1656 } 1657 1658 /* DRC reset may cause a device to be unplugged. This will cause troubles 1659 * if this device is used by another device (eg, a running vhost backend 1660 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1661 * situations, we reset DRCs after all devices have been reset. 1662 */ 1663 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1664 1665 spapr_clear_pending_events(spapr); 1666 1667 /* 1668 * We place the device tree and RTAS just below either the top of the RMA, 1669 * or just below 2GB, whichever is lower, so that it can be 1670 * processed with 32-bit real mode code if necessary 1671 */ 1672 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1673 1674 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1675 1676 rc = fdt_pack(fdt); 1677 1678 /* Should only fail if we've built a corrupted tree */ 1679 assert(rc == 0); 1680 1681 /* Load the fdt */ 1682 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1683 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1684 g_free(spapr->fdt_blob); 1685 spapr->fdt_size = fdt_totalsize(fdt); 1686 spapr->fdt_initial_size = spapr->fdt_size; 1687 spapr->fdt_blob = fdt; 1688 1689 /* Set up the entry state */ 1690 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1691 first_ppc_cpu->env.gpr[5] = 0; 1692 1693 spapr->cas_reboot = false; 1694 1695 spapr->mc_status = -1; 1696 spapr->guest_machine_check_addr = -1; 1697 1698 /* Signal all vCPUs waiting on this condition */ 1699 qemu_cond_broadcast(&spapr->mc_delivery_cond); 1700 1701 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1702 } 1703 1704 static void spapr_create_nvram(SpaprMachineState *spapr) 1705 { 1706 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1707 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1708 1709 if (dinfo) { 1710 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1711 &error_fatal); 1712 } 1713 1714 qdev_init_nofail(dev); 1715 1716 spapr->nvram = (struct SpaprNvram *)dev; 1717 } 1718 1719 static void spapr_rtc_create(SpaprMachineState *spapr) 1720 { 1721 object_initialize_child(OBJECT(spapr), "rtc", 1722 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1723 &error_fatal, NULL); 1724 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1725 &error_fatal); 1726 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1727 "date", &error_fatal); 1728 } 1729 1730 /* Returns whether we want to use VGA or not */ 1731 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1732 { 1733 switch (vga_interface_type) { 1734 case VGA_NONE: 1735 return false; 1736 case VGA_DEVICE: 1737 return true; 1738 case VGA_STD: 1739 case VGA_VIRTIO: 1740 case VGA_CIRRUS: 1741 return pci_vga_init(pci_bus) != NULL; 1742 default: 1743 error_setg(errp, 1744 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1745 return false; 1746 } 1747 } 1748 1749 static int spapr_pre_load(void *opaque) 1750 { 1751 int rc; 1752 1753 rc = spapr_caps_pre_load(opaque); 1754 if (rc) { 1755 return rc; 1756 } 1757 1758 return 0; 1759 } 1760 1761 static int spapr_post_load(void *opaque, int version_id) 1762 { 1763 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1764 int err = 0; 1765 1766 err = spapr_caps_post_migration(spapr); 1767 if (err) { 1768 return err; 1769 } 1770 1771 /* 1772 * In earlier versions, there was no separate qdev for the PAPR 1773 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1774 * So when migrating from those versions, poke the incoming offset 1775 * value into the RTC device 1776 */ 1777 if (version_id < 3) { 1778 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1779 if (err) { 1780 return err; 1781 } 1782 } 1783 1784 if (kvm_enabled() && spapr->patb_entry) { 1785 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1786 bool radix = !!(spapr->patb_entry & PATE1_GR); 1787 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1788 1789 /* 1790 * Update LPCR:HR and UPRT as they may not be set properly in 1791 * the stream 1792 */ 1793 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1794 LPCR_HR | LPCR_UPRT); 1795 1796 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1797 if (err) { 1798 error_report("Process table config unsupported by the host"); 1799 return -EINVAL; 1800 } 1801 } 1802 1803 err = spapr_irq_post_load(spapr, version_id); 1804 if (err) { 1805 return err; 1806 } 1807 1808 return err; 1809 } 1810 1811 static int spapr_pre_save(void *opaque) 1812 { 1813 int rc; 1814 1815 rc = spapr_caps_pre_save(opaque); 1816 if (rc) { 1817 return rc; 1818 } 1819 1820 return 0; 1821 } 1822 1823 static bool version_before_3(void *opaque, int version_id) 1824 { 1825 return version_id < 3; 1826 } 1827 1828 static bool spapr_pending_events_needed(void *opaque) 1829 { 1830 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1831 return !QTAILQ_EMPTY(&spapr->pending_events); 1832 } 1833 1834 static const VMStateDescription vmstate_spapr_event_entry = { 1835 .name = "spapr_event_log_entry", 1836 .version_id = 1, 1837 .minimum_version_id = 1, 1838 .fields = (VMStateField[]) { 1839 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1840 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1841 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1842 NULL, extended_length), 1843 VMSTATE_END_OF_LIST() 1844 }, 1845 }; 1846 1847 static const VMStateDescription vmstate_spapr_pending_events = { 1848 .name = "spapr_pending_events", 1849 .version_id = 1, 1850 .minimum_version_id = 1, 1851 .needed = spapr_pending_events_needed, 1852 .fields = (VMStateField[]) { 1853 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1854 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1855 VMSTATE_END_OF_LIST() 1856 }, 1857 }; 1858 1859 static bool spapr_ov5_cas_needed(void *opaque) 1860 { 1861 SpaprMachineState *spapr = opaque; 1862 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1863 bool cas_needed; 1864 1865 /* Prior to the introduction of SpaprOptionVector, we had two option 1866 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1867 * Both of these options encode machine topology into the device-tree 1868 * in such a way that the now-booted OS should still be able to interact 1869 * appropriately with QEMU regardless of what options were actually 1870 * negotiatied on the source side. 1871 * 1872 * As such, we can avoid migrating the CAS-negotiated options if these 1873 * are the only options available on the current machine/platform. 1874 * Since these are the only options available for pseries-2.7 and 1875 * earlier, this allows us to maintain old->new/new->old migration 1876 * compatibility. 1877 * 1878 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1879 * via default pseries-2.8 machines and explicit command-line parameters. 1880 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1881 * of the actual CAS-negotiated values to continue working properly. For 1882 * example, availability of memory unplug depends on knowing whether 1883 * OV5_HP_EVT was negotiated via CAS. 1884 * 1885 * Thus, for any cases where the set of available CAS-negotiatable 1886 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1887 * include the CAS-negotiated options in the migration stream, unless 1888 * if they affect boot time behaviour only. 1889 */ 1890 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1891 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1892 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1893 1894 /* We need extra information if we have any bits outside the mask 1895 * defined above */ 1896 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1897 1898 spapr_ovec_cleanup(ov5_mask); 1899 1900 return cas_needed; 1901 } 1902 1903 static const VMStateDescription vmstate_spapr_ov5_cas = { 1904 .name = "spapr_option_vector_ov5_cas", 1905 .version_id = 1, 1906 .minimum_version_id = 1, 1907 .needed = spapr_ov5_cas_needed, 1908 .fields = (VMStateField[]) { 1909 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1910 vmstate_spapr_ovec, SpaprOptionVector), 1911 VMSTATE_END_OF_LIST() 1912 }, 1913 }; 1914 1915 static bool spapr_patb_entry_needed(void *opaque) 1916 { 1917 SpaprMachineState *spapr = opaque; 1918 1919 return !!spapr->patb_entry; 1920 } 1921 1922 static const VMStateDescription vmstate_spapr_patb_entry = { 1923 .name = "spapr_patb_entry", 1924 .version_id = 1, 1925 .minimum_version_id = 1, 1926 .needed = spapr_patb_entry_needed, 1927 .fields = (VMStateField[]) { 1928 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1929 VMSTATE_END_OF_LIST() 1930 }, 1931 }; 1932 1933 static bool spapr_irq_map_needed(void *opaque) 1934 { 1935 SpaprMachineState *spapr = opaque; 1936 1937 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1938 } 1939 1940 static const VMStateDescription vmstate_spapr_irq_map = { 1941 .name = "spapr_irq_map", 1942 .version_id = 1, 1943 .minimum_version_id = 1, 1944 .needed = spapr_irq_map_needed, 1945 .fields = (VMStateField[]) { 1946 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1947 VMSTATE_END_OF_LIST() 1948 }, 1949 }; 1950 1951 static bool spapr_dtb_needed(void *opaque) 1952 { 1953 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1954 1955 return smc->update_dt_enabled; 1956 } 1957 1958 static int spapr_dtb_pre_load(void *opaque) 1959 { 1960 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1961 1962 g_free(spapr->fdt_blob); 1963 spapr->fdt_blob = NULL; 1964 spapr->fdt_size = 0; 1965 1966 return 0; 1967 } 1968 1969 static const VMStateDescription vmstate_spapr_dtb = { 1970 .name = "spapr_dtb", 1971 .version_id = 1, 1972 .minimum_version_id = 1, 1973 .needed = spapr_dtb_needed, 1974 .pre_load = spapr_dtb_pre_load, 1975 .fields = (VMStateField[]) { 1976 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1977 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1978 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1979 fdt_size), 1980 VMSTATE_END_OF_LIST() 1981 }, 1982 }; 1983 1984 static bool spapr_fwnmi_needed(void *opaque) 1985 { 1986 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1987 1988 return spapr->guest_machine_check_addr != -1; 1989 } 1990 1991 static int spapr_fwnmi_pre_save(void *opaque) 1992 { 1993 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1994 1995 /* 1996 * Check if machine check handling is in progress and print a 1997 * warning message. 1998 */ 1999 if (spapr->mc_status != -1) { 2000 warn_report("A machine check is being handled during migration. The" 2001 "handler may run and log hardware error on the destination"); 2002 } 2003 2004 return 0; 2005 } 2006 2007 static const VMStateDescription vmstate_spapr_machine_check = { 2008 .name = "spapr_machine_check", 2009 .version_id = 1, 2010 .minimum_version_id = 1, 2011 .needed = spapr_fwnmi_needed, 2012 .pre_save = spapr_fwnmi_pre_save, 2013 .fields = (VMStateField[]) { 2014 VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), 2015 VMSTATE_INT32(mc_status, SpaprMachineState), 2016 VMSTATE_END_OF_LIST() 2017 }, 2018 }; 2019 2020 static const VMStateDescription vmstate_spapr = { 2021 .name = "spapr", 2022 .version_id = 3, 2023 .minimum_version_id = 1, 2024 .pre_load = spapr_pre_load, 2025 .post_load = spapr_post_load, 2026 .pre_save = spapr_pre_save, 2027 .fields = (VMStateField[]) { 2028 /* used to be @next_irq */ 2029 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2030 2031 /* RTC offset */ 2032 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2033 2034 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2035 VMSTATE_END_OF_LIST() 2036 }, 2037 .subsections = (const VMStateDescription*[]) { 2038 &vmstate_spapr_ov5_cas, 2039 &vmstate_spapr_patb_entry, 2040 &vmstate_spapr_pending_events, 2041 &vmstate_spapr_cap_htm, 2042 &vmstate_spapr_cap_vsx, 2043 &vmstate_spapr_cap_dfp, 2044 &vmstate_spapr_cap_cfpc, 2045 &vmstate_spapr_cap_sbbc, 2046 &vmstate_spapr_cap_ibs, 2047 &vmstate_spapr_cap_hpt_maxpagesize, 2048 &vmstate_spapr_irq_map, 2049 &vmstate_spapr_cap_nested_kvm_hv, 2050 &vmstate_spapr_dtb, 2051 &vmstate_spapr_cap_large_decr, 2052 &vmstate_spapr_cap_ccf_assist, 2053 &vmstate_spapr_cap_fwnmi, 2054 &vmstate_spapr_machine_check, 2055 NULL 2056 } 2057 }; 2058 2059 static int htab_save_setup(QEMUFile *f, void *opaque) 2060 { 2061 SpaprMachineState *spapr = opaque; 2062 2063 /* "Iteration" header */ 2064 if (!spapr->htab_shift) { 2065 qemu_put_be32(f, -1); 2066 } else { 2067 qemu_put_be32(f, spapr->htab_shift); 2068 } 2069 2070 if (spapr->htab) { 2071 spapr->htab_save_index = 0; 2072 spapr->htab_first_pass = true; 2073 } else { 2074 if (spapr->htab_shift) { 2075 assert(kvm_enabled()); 2076 } 2077 } 2078 2079 2080 return 0; 2081 } 2082 2083 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2084 int chunkstart, int n_valid, int n_invalid) 2085 { 2086 qemu_put_be32(f, chunkstart); 2087 qemu_put_be16(f, n_valid); 2088 qemu_put_be16(f, n_invalid); 2089 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2090 HASH_PTE_SIZE_64 * n_valid); 2091 } 2092 2093 static void htab_save_end_marker(QEMUFile *f) 2094 { 2095 qemu_put_be32(f, 0); 2096 qemu_put_be16(f, 0); 2097 qemu_put_be16(f, 0); 2098 } 2099 2100 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2101 int64_t max_ns) 2102 { 2103 bool has_timeout = max_ns != -1; 2104 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2105 int index = spapr->htab_save_index; 2106 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2107 2108 assert(spapr->htab_first_pass); 2109 2110 do { 2111 int chunkstart; 2112 2113 /* Consume invalid HPTEs */ 2114 while ((index < htabslots) 2115 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2116 CLEAN_HPTE(HPTE(spapr->htab, index)); 2117 index++; 2118 } 2119 2120 /* Consume valid HPTEs */ 2121 chunkstart = index; 2122 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2123 && HPTE_VALID(HPTE(spapr->htab, index))) { 2124 CLEAN_HPTE(HPTE(spapr->htab, index)); 2125 index++; 2126 } 2127 2128 if (index > chunkstart) { 2129 int n_valid = index - chunkstart; 2130 2131 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2132 2133 if (has_timeout && 2134 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2135 break; 2136 } 2137 } 2138 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2139 2140 if (index >= htabslots) { 2141 assert(index == htabslots); 2142 index = 0; 2143 spapr->htab_first_pass = false; 2144 } 2145 spapr->htab_save_index = index; 2146 } 2147 2148 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2149 int64_t max_ns) 2150 { 2151 bool final = max_ns < 0; 2152 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2153 int examined = 0, sent = 0; 2154 int index = spapr->htab_save_index; 2155 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2156 2157 assert(!spapr->htab_first_pass); 2158 2159 do { 2160 int chunkstart, invalidstart; 2161 2162 /* Consume non-dirty HPTEs */ 2163 while ((index < htabslots) 2164 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2165 index++; 2166 examined++; 2167 } 2168 2169 chunkstart = index; 2170 /* Consume valid dirty HPTEs */ 2171 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2172 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2173 && HPTE_VALID(HPTE(spapr->htab, index))) { 2174 CLEAN_HPTE(HPTE(spapr->htab, index)); 2175 index++; 2176 examined++; 2177 } 2178 2179 invalidstart = index; 2180 /* Consume invalid dirty HPTEs */ 2181 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2182 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2183 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2184 CLEAN_HPTE(HPTE(spapr->htab, index)); 2185 index++; 2186 examined++; 2187 } 2188 2189 if (index > chunkstart) { 2190 int n_valid = invalidstart - chunkstart; 2191 int n_invalid = index - invalidstart; 2192 2193 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2194 sent += index - chunkstart; 2195 2196 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2197 break; 2198 } 2199 } 2200 2201 if (examined >= htabslots) { 2202 break; 2203 } 2204 2205 if (index >= htabslots) { 2206 assert(index == htabslots); 2207 index = 0; 2208 } 2209 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2210 2211 if (index >= htabslots) { 2212 assert(index == htabslots); 2213 index = 0; 2214 } 2215 2216 spapr->htab_save_index = index; 2217 2218 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2219 } 2220 2221 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2222 #define MAX_KVM_BUF_SIZE 2048 2223 2224 static int htab_save_iterate(QEMUFile *f, void *opaque) 2225 { 2226 SpaprMachineState *spapr = opaque; 2227 int fd; 2228 int rc = 0; 2229 2230 /* Iteration header */ 2231 if (!spapr->htab_shift) { 2232 qemu_put_be32(f, -1); 2233 return 1; 2234 } else { 2235 qemu_put_be32(f, 0); 2236 } 2237 2238 if (!spapr->htab) { 2239 assert(kvm_enabled()); 2240 2241 fd = get_htab_fd(spapr); 2242 if (fd < 0) { 2243 return fd; 2244 } 2245 2246 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2247 if (rc < 0) { 2248 return rc; 2249 } 2250 } else if (spapr->htab_first_pass) { 2251 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2252 } else { 2253 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2254 } 2255 2256 htab_save_end_marker(f); 2257 2258 return rc; 2259 } 2260 2261 static int htab_save_complete(QEMUFile *f, void *opaque) 2262 { 2263 SpaprMachineState *spapr = opaque; 2264 int fd; 2265 2266 /* Iteration header */ 2267 if (!spapr->htab_shift) { 2268 qemu_put_be32(f, -1); 2269 return 0; 2270 } else { 2271 qemu_put_be32(f, 0); 2272 } 2273 2274 if (!spapr->htab) { 2275 int rc; 2276 2277 assert(kvm_enabled()); 2278 2279 fd = get_htab_fd(spapr); 2280 if (fd < 0) { 2281 return fd; 2282 } 2283 2284 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2285 if (rc < 0) { 2286 return rc; 2287 } 2288 } else { 2289 if (spapr->htab_first_pass) { 2290 htab_save_first_pass(f, spapr, -1); 2291 } 2292 htab_save_later_pass(f, spapr, -1); 2293 } 2294 2295 /* End marker */ 2296 htab_save_end_marker(f); 2297 2298 return 0; 2299 } 2300 2301 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2302 { 2303 SpaprMachineState *spapr = opaque; 2304 uint32_t section_hdr; 2305 int fd = -1; 2306 Error *local_err = NULL; 2307 2308 if (version_id < 1 || version_id > 1) { 2309 error_report("htab_load() bad version"); 2310 return -EINVAL; 2311 } 2312 2313 section_hdr = qemu_get_be32(f); 2314 2315 if (section_hdr == -1) { 2316 spapr_free_hpt(spapr); 2317 return 0; 2318 } 2319 2320 if (section_hdr) { 2321 /* First section gives the htab size */ 2322 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2323 if (local_err) { 2324 error_report_err(local_err); 2325 return -EINVAL; 2326 } 2327 return 0; 2328 } 2329 2330 if (!spapr->htab) { 2331 assert(kvm_enabled()); 2332 2333 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2334 if (fd < 0) { 2335 error_report_err(local_err); 2336 return fd; 2337 } 2338 } 2339 2340 while (true) { 2341 uint32_t index; 2342 uint16_t n_valid, n_invalid; 2343 2344 index = qemu_get_be32(f); 2345 n_valid = qemu_get_be16(f); 2346 n_invalid = qemu_get_be16(f); 2347 2348 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2349 /* End of Stream */ 2350 break; 2351 } 2352 2353 if ((index + n_valid + n_invalid) > 2354 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2355 /* Bad index in stream */ 2356 error_report( 2357 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2358 index, n_valid, n_invalid, spapr->htab_shift); 2359 return -EINVAL; 2360 } 2361 2362 if (spapr->htab) { 2363 if (n_valid) { 2364 qemu_get_buffer(f, HPTE(spapr->htab, index), 2365 HASH_PTE_SIZE_64 * n_valid); 2366 } 2367 if (n_invalid) { 2368 memset(HPTE(spapr->htab, index + n_valid), 0, 2369 HASH_PTE_SIZE_64 * n_invalid); 2370 } 2371 } else { 2372 int rc; 2373 2374 assert(fd >= 0); 2375 2376 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2377 if (rc < 0) { 2378 return rc; 2379 } 2380 } 2381 } 2382 2383 if (!spapr->htab) { 2384 assert(fd >= 0); 2385 close(fd); 2386 } 2387 2388 return 0; 2389 } 2390 2391 static void htab_save_cleanup(void *opaque) 2392 { 2393 SpaprMachineState *spapr = opaque; 2394 2395 close_htab_fd(spapr); 2396 } 2397 2398 static SaveVMHandlers savevm_htab_handlers = { 2399 .save_setup = htab_save_setup, 2400 .save_live_iterate = htab_save_iterate, 2401 .save_live_complete_precopy = htab_save_complete, 2402 .save_cleanup = htab_save_cleanup, 2403 .load_state = htab_load, 2404 }; 2405 2406 static void spapr_boot_set(void *opaque, const char *boot_device, 2407 Error **errp) 2408 { 2409 MachineState *machine = MACHINE(opaque); 2410 machine->boot_order = g_strdup(boot_device); 2411 } 2412 2413 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2414 { 2415 MachineState *machine = MACHINE(spapr); 2416 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2417 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2418 int i; 2419 2420 for (i = 0; i < nr_lmbs; i++) { 2421 uint64_t addr; 2422 2423 addr = i * lmb_size + machine->device_memory->base; 2424 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2425 addr / lmb_size); 2426 } 2427 } 2428 2429 /* 2430 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2431 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2432 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2433 */ 2434 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2435 { 2436 int i; 2437 2438 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2439 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2440 " is not aligned to %" PRIu64 " MiB", 2441 machine->ram_size, 2442 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2443 return; 2444 } 2445 2446 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2447 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2448 " is not aligned to %" PRIu64 " MiB", 2449 machine->ram_size, 2450 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2451 return; 2452 } 2453 2454 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2455 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2456 error_setg(errp, 2457 "Node %d memory size 0x%" PRIx64 2458 " is not aligned to %" PRIu64 " MiB", 2459 i, machine->numa_state->nodes[i].node_mem, 2460 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2461 return; 2462 } 2463 } 2464 } 2465 2466 /* find cpu slot in machine->possible_cpus by core_id */ 2467 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2468 { 2469 int index = id / ms->smp.threads; 2470 2471 if (index >= ms->possible_cpus->len) { 2472 return NULL; 2473 } 2474 if (idx) { 2475 *idx = index; 2476 } 2477 return &ms->possible_cpus->cpus[index]; 2478 } 2479 2480 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2481 { 2482 MachineState *ms = MACHINE(spapr); 2483 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2484 Error *local_err = NULL; 2485 bool vsmt_user = !!spapr->vsmt; 2486 int kvm_smt = kvmppc_smt_threads(); 2487 int ret; 2488 unsigned int smp_threads = ms->smp.threads; 2489 2490 if (!kvm_enabled() && (smp_threads > 1)) { 2491 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2492 "on a pseries machine"); 2493 goto out; 2494 } 2495 if (!is_power_of_2(smp_threads)) { 2496 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2497 "machine because it must be a power of 2", smp_threads); 2498 goto out; 2499 } 2500 2501 /* Detemine the VSMT mode to use: */ 2502 if (vsmt_user) { 2503 if (spapr->vsmt < smp_threads) { 2504 error_setg(&local_err, "Cannot support VSMT mode %d" 2505 " because it must be >= threads/core (%d)", 2506 spapr->vsmt, smp_threads); 2507 goto out; 2508 } 2509 /* In this case, spapr->vsmt has been set by the command line */ 2510 } else if (!smc->smp_threads_vsmt) { 2511 /* 2512 * Default VSMT value is tricky, because we need it to be as 2513 * consistent as possible (for migration), but this requires 2514 * changing it for at least some existing cases. We pick 8 as 2515 * the value that we'd get with KVM on POWER8, the 2516 * overwhelmingly common case in production systems. 2517 */ 2518 spapr->vsmt = MAX(8, smp_threads); 2519 } else { 2520 spapr->vsmt = smp_threads; 2521 } 2522 2523 /* KVM: If necessary, set the SMT mode: */ 2524 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2525 ret = kvmppc_set_smt_threads(spapr->vsmt); 2526 if (ret) { 2527 /* Looks like KVM isn't able to change VSMT mode */ 2528 error_setg(&local_err, 2529 "Failed to set KVM's VSMT mode to %d (errno %d)", 2530 spapr->vsmt, ret); 2531 /* We can live with that if the default one is big enough 2532 * for the number of threads, and a submultiple of the one 2533 * we want. In this case we'll waste some vcpu ids, but 2534 * behaviour will be correct */ 2535 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2536 warn_report_err(local_err); 2537 local_err = NULL; 2538 goto out; 2539 } else { 2540 if (!vsmt_user) { 2541 error_append_hint(&local_err, 2542 "On PPC, a VM with %d threads/core" 2543 " on a host with %d threads/core" 2544 " requires the use of VSMT mode %d.\n", 2545 smp_threads, kvm_smt, spapr->vsmt); 2546 } 2547 kvmppc_error_append_smt_possible_hint(&local_err); 2548 goto out; 2549 } 2550 } 2551 } 2552 /* else TCG: nothing to do currently */ 2553 out: 2554 error_propagate(errp, local_err); 2555 } 2556 2557 static void spapr_init_cpus(SpaprMachineState *spapr) 2558 { 2559 MachineState *machine = MACHINE(spapr); 2560 MachineClass *mc = MACHINE_GET_CLASS(machine); 2561 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2562 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2563 const CPUArchIdList *possible_cpus; 2564 unsigned int smp_cpus = machine->smp.cpus; 2565 unsigned int smp_threads = machine->smp.threads; 2566 unsigned int max_cpus = machine->smp.max_cpus; 2567 int boot_cores_nr = smp_cpus / smp_threads; 2568 int i; 2569 2570 possible_cpus = mc->possible_cpu_arch_ids(machine); 2571 if (mc->has_hotpluggable_cpus) { 2572 if (smp_cpus % smp_threads) { 2573 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2574 smp_cpus, smp_threads); 2575 exit(1); 2576 } 2577 if (max_cpus % smp_threads) { 2578 error_report("max_cpus (%u) must be multiple of threads (%u)", 2579 max_cpus, smp_threads); 2580 exit(1); 2581 } 2582 } else { 2583 if (max_cpus != smp_cpus) { 2584 error_report("This machine version does not support CPU hotplug"); 2585 exit(1); 2586 } 2587 boot_cores_nr = possible_cpus->len; 2588 } 2589 2590 if (smc->pre_2_10_has_unused_icps) { 2591 int i; 2592 2593 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2594 /* Dummy entries get deregistered when real ICPState objects 2595 * are registered during CPU core hotplug. 2596 */ 2597 pre_2_10_vmstate_register_dummy_icp(i); 2598 } 2599 } 2600 2601 for (i = 0; i < possible_cpus->len; i++) { 2602 int core_id = i * smp_threads; 2603 2604 if (mc->has_hotpluggable_cpus) { 2605 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2606 spapr_vcpu_id(spapr, core_id)); 2607 } 2608 2609 if (i < boot_cores_nr) { 2610 Object *core = object_new(type); 2611 int nr_threads = smp_threads; 2612 2613 /* Handle the partially filled core for older machine types */ 2614 if ((i + 1) * smp_threads >= smp_cpus) { 2615 nr_threads = smp_cpus - i * smp_threads; 2616 } 2617 2618 object_property_set_int(core, nr_threads, "nr-threads", 2619 &error_fatal); 2620 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2621 &error_fatal); 2622 object_property_set_bool(core, true, "realized", &error_fatal); 2623 2624 object_unref(core); 2625 } 2626 } 2627 } 2628 2629 static PCIHostState *spapr_create_default_phb(void) 2630 { 2631 DeviceState *dev; 2632 2633 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2634 qdev_prop_set_uint32(dev, "index", 0); 2635 qdev_init_nofail(dev); 2636 2637 return PCI_HOST_BRIDGE(dev); 2638 } 2639 2640 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2641 { 2642 MachineState *machine = MACHINE(spapr); 2643 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2644 hwaddr rma_size = machine->ram_size; 2645 hwaddr node0_size = spapr_node0_size(machine); 2646 2647 /* RMA has to fit in the first NUMA node */ 2648 rma_size = MIN(rma_size, node0_size); 2649 2650 /* 2651 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2652 * never exceed that 2653 */ 2654 rma_size = MIN(rma_size, 1 * TiB); 2655 2656 /* 2657 * Clamp the RMA size based on machine type. This is for 2658 * migration compatibility with older qemu versions, which limited 2659 * the RMA size for complicated and mostly bad reasons. 2660 */ 2661 if (smc->rma_limit) { 2662 rma_size = MIN(rma_size, smc->rma_limit); 2663 } 2664 2665 if (rma_size < MIN_RMA_SLOF) { 2666 error_setg(errp, 2667 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2668 "ldMiB guest RMA (Real Mode Area memory)", 2669 MIN_RMA_SLOF / MiB); 2670 return 0; 2671 } 2672 2673 return rma_size; 2674 } 2675 2676 /* pSeries LPAR / sPAPR hardware init */ 2677 static void spapr_machine_init(MachineState *machine) 2678 { 2679 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2680 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2681 MachineClass *mc = MACHINE_GET_CLASS(machine); 2682 const char *kernel_filename = machine->kernel_filename; 2683 const char *initrd_filename = machine->initrd_filename; 2684 PCIHostState *phb; 2685 int i; 2686 MemoryRegion *sysmem = get_system_memory(); 2687 long load_limit, fw_size; 2688 char *filename; 2689 Error *resize_hpt_err = NULL; 2690 2691 msi_nonbroken = true; 2692 2693 QLIST_INIT(&spapr->phbs); 2694 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2695 2696 /* Determine capabilities to run with */ 2697 spapr_caps_init(spapr); 2698 2699 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2700 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2701 /* 2702 * If the user explicitly requested a mode we should either 2703 * supply it, or fail completely (which we do below). But if 2704 * it's not set explicitly, we reset our mode to something 2705 * that works 2706 */ 2707 if (resize_hpt_err) { 2708 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2709 error_free(resize_hpt_err); 2710 resize_hpt_err = NULL; 2711 } else { 2712 spapr->resize_hpt = smc->resize_hpt_default; 2713 } 2714 } 2715 2716 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2717 2718 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2719 /* 2720 * User requested HPT resize, but this host can't supply it. Bail out 2721 */ 2722 error_report_err(resize_hpt_err); 2723 exit(1); 2724 } 2725 2726 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2727 2728 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2729 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2730 2731 /* 2732 * VSMT must be set in order to be able to compute VCPU ids, ie to 2733 * call spapr_max_server_number() or spapr_vcpu_id(). 2734 */ 2735 spapr_set_vsmt_mode(spapr, &error_fatal); 2736 2737 /* Set up Interrupt Controller before we create the VCPUs */ 2738 spapr_irq_init(spapr, &error_fatal); 2739 2740 /* Set up containers for ibm,client-architecture-support negotiated options 2741 */ 2742 spapr->ov5 = spapr_ovec_new(); 2743 spapr->ov5_cas = spapr_ovec_new(); 2744 2745 if (smc->dr_lmb_enabled) { 2746 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2747 spapr_validate_node_memory(machine, &error_fatal); 2748 } 2749 2750 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2751 2752 /* advertise support for dedicated HP event source to guests */ 2753 if (spapr->use_hotplug_event_source) { 2754 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2755 } 2756 2757 /* advertise support for HPT resizing */ 2758 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2759 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2760 } 2761 2762 /* advertise support for ibm,dyamic-memory-v2 */ 2763 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2764 2765 /* advertise XIVE on POWER9 machines */ 2766 if (spapr->irq->xive) { 2767 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2768 } 2769 2770 /* init CPUs */ 2771 spapr_init_cpus(spapr); 2772 2773 /* 2774 * check we don't have a memory-less/cpu-less NUMA node 2775 * Firmware relies on the existing memory/cpu topology to provide the 2776 * NUMA topology to the kernel. 2777 * And the linux kernel needs to know the NUMA topology at start 2778 * to be able to hotplug CPUs later. 2779 */ 2780 if (machine->numa_state->num_nodes) { 2781 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2782 /* check for memory-less node */ 2783 if (machine->numa_state->nodes[i].node_mem == 0) { 2784 CPUState *cs; 2785 int found = 0; 2786 /* check for cpu-less node */ 2787 CPU_FOREACH(cs) { 2788 PowerPCCPU *cpu = POWERPC_CPU(cs); 2789 if (cpu->node_id == i) { 2790 found = 1; 2791 break; 2792 } 2793 } 2794 /* memory-less and cpu-less node */ 2795 if (!found) { 2796 error_report( 2797 "Memory-less/cpu-less nodes are not supported (node %d)", 2798 i); 2799 exit(1); 2800 } 2801 } 2802 } 2803 2804 } 2805 2806 /* 2807 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2808 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2809 * called from vPHB reset handler so we initialize the counter here. 2810 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2811 * must be equally distant from any other node. 2812 * The final value of spapr->gpu_numa_id is going to be written to 2813 * max-associativity-domains in spapr_build_fdt(). 2814 */ 2815 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2816 2817 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2818 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2819 spapr->max_compat_pvr)) { 2820 /* KVM and TCG always allow GTSE with radix... */ 2821 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2822 } 2823 /* ... but not with hash (currently). */ 2824 2825 if (kvm_enabled()) { 2826 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2827 kvmppc_enable_logical_ci_hcalls(); 2828 kvmppc_enable_set_mode_hcall(); 2829 2830 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2831 kvmppc_enable_clear_ref_mod_hcalls(); 2832 2833 /* Enable H_PAGE_INIT */ 2834 kvmppc_enable_h_page_init(); 2835 } 2836 2837 /* map RAM */ 2838 memory_region_add_subregion(sysmem, 0, machine->ram); 2839 2840 /* always allocate the device memory information */ 2841 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2842 2843 /* initialize hotplug memory address space */ 2844 if (machine->ram_size < machine->maxram_size) { 2845 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2846 /* 2847 * Limit the number of hotpluggable memory slots to half the number 2848 * slots that KVM supports, leaving the other half for PCI and other 2849 * devices. However ensure that number of slots doesn't drop below 32. 2850 */ 2851 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2852 SPAPR_MAX_RAM_SLOTS; 2853 2854 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2855 max_memslots = SPAPR_MAX_RAM_SLOTS; 2856 } 2857 if (machine->ram_slots > max_memslots) { 2858 error_report("Specified number of memory slots %" 2859 PRIu64" exceeds max supported %d", 2860 machine->ram_slots, max_memslots); 2861 exit(1); 2862 } 2863 2864 machine->device_memory->base = ROUND_UP(machine->ram_size, 2865 SPAPR_DEVICE_MEM_ALIGN); 2866 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2867 "device-memory", device_mem_size); 2868 memory_region_add_subregion(sysmem, machine->device_memory->base, 2869 &machine->device_memory->mr); 2870 } 2871 2872 if (smc->dr_lmb_enabled) { 2873 spapr_create_lmb_dr_connectors(spapr); 2874 } 2875 2876 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) { 2877 /* Create the error string for live migration blocker */ 2878 error_setg(&spapr->fwnmi_migration_blocker, 2879 "A machine check is being handled during migration. The handler" 2880 "may run and log hardware error on the destination"); 2881 } 2882 2883 if (mc->nvdimm_supported) { 2884 spapr_create_nvdimm_dr_connectors(spapr); 2885 } 2886 2887 /* Set up RTAS event infrastructure */ 2888 spapr_events_init(spapr); 2889 2890 /* Set up the RTC RTAS interfaces */ 2891 spapr_rtc_create(spapr); 2892 2893 /* Set up VIO bus */ 2894 spapr->vio_bus = spapr_vio_bus_init(); 2895 2896 for (i = 0; i < serial_max_hds(); i++) { 2897 if (serial_hd(i)) { 2898 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2899 } 2900 } 2901 2902 /* We always have at least the nvram device on VIO */ 2903 spapr_create_nvram(spapr); 2904 2905 /* 2906 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2907 * connectors (described in root DT node's "ibm,drc-types" property) 2908 * are pre-initialized here. additional child connectors (such as 2909 * connectors for a PHBs PCI slots) are added as needed during their 2910 * parent's realization. 2911 */ 2912 if (smc->dr_phb_enabled) { 2913 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2914 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2915 } 2916 } 2917 2918 /* Set up PCI */ 2919 spapr_pci_rtas_init(); 2920 2921 phb = spapr_create_default_phb(); 2922 2923 for (i = 0; i < nb_nics; i++) { 2924 NICInfo *nd = &nd_table[i]; 2925 2926 if (!nd->model) { 2927 nd->model = g_strdup("spapr-vlan"); 2928 } 2929 2930 if (g_str_equal(nd->model, "spapr-vlan") || 2931 g_str_equal(nd->model, "ibmveth")) { 2932 spapr_vlan_create(spapr->vio_bus, nd); 2933 } else { 2934 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2935 } 2936 } 2937 2938 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2939 spapr_vscsi_create(spapr->vio_bus); 2940 } 2941 2942 /* Graphics */ 2943 if (spapr_vga_init(phb->bus, &error_fatal)) { 2944 spapr->has_graphics = true; 2945 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2946 } 2947 2948 if (machine->usb) { 2949 if (smc->use_ohci_by_default) { 2950 pci_create_simple(phb->bus, -1, "pci-ohci"); 2951 } else { 2952 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2953 } 2954 2955 if (spapr->has_graphics) { 2956 USBBus *usb_bus = usb_bus_find(-1); 2957 2958 usb_create_simple(usb_bus, "usb-kbd"); 2959 usb_create_simple(usb_bus, "usb-mouse"); 2960 } 2961 } 2962 2963 if (kernel_filename) { 2964 uint64_t lowaddr = 0; 2965 2966 spapr->kernel_size = load_elf(kernel_filename, NULL, 2967 translate_kernel_address, spapr, 2968 NULL, &lowaddr, NULL, NULL, 1, 2969 PPC_ELF_MACHINE, 0, 0); 2970 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2971 spapr->kernel_size = load_elf(kernel_filename, NULL, 2972 translate_kernel_address, spapr, NULL, 2973 &lowaddr, NULL, NULL, 0, 2974 PPC_ELF_MACHINE, 2975 0, 0); 2976 spapr->kernel_le = spapr->kernel_size > 0; 2977 } 2978 if (spapr->kernel_size < 0) { 2979 error_report("error loading %s: %s", kernel_filename, 2980 load_elf_strerror(spapr->kernel_size)); 2981 exit(1); 2982 } 2983 2984 /* load initrd */ 2985 if (initrd_filename) { 2986 /* Try to locate the initrd in the gap between the kernel 2987 * and the firmware. Add a bit of space just in case 2988 */ 2989 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2990 + 0x1ffff) & ~0xffff; 2991 spapr->initrd_size = load_image_targphys(initrd_filename, 2992 spapr->initrd_base, 2993 load_limit 2994 - spapr->initrd_base); 2995 if (spapr->initrd_size < 0) { 2996 error_report("could not load initial ram disk '%s'", 2997 initrd_filename); 2998 exit(1); 2999 } 3000 } 3001 } 3002 3003 if (bios_name == NULL) { 3004 bios_name = FW_FILE_NAME; 3005 } 3006 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3007 if (!filename) { 3008 error_report("Could not find LPAR firmware '%s'", bios_name); 3009 exit(1); 3010 } 3011 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3012 if (fw_size <= 0) { 3013 error_report("Could not load LPAR firmware '%s'", filename); 3014 exit(1); 3015 } 3016 g_free(filename); 3017 3018 /* FIXME: Should register things through the MachineState's qdev 3019 * interface, this is a legacy from the sPAPREnvironment structure 3020 * which predated MachineState but had a similar function */ 3021 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3022 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3023 &savevm_htab_handlers, spapr); 3024 3025 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3026 &error_fatal); 3027 3028 qemu_register_boot_set(spapr_boot_set, spapr); 3029 3030 /* 3031 * Nothing needs to be done to resume a suspended guest because 3032 * suspending does not change the machine state, so no need for 3033 * a ->wakeup method. 3034 */ 3035 qemu_register_wakeup_support(); 3036 3037 if (kvm_enabled()) { 3038 /* to stop and start vmclock */ 3039 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3040 &spapr->tb); 3041 3042 kvmppc_spapr_enable_inkernel_multitce(); 3043 } 3044 3045 qemu_cond_init(&spapr->mc_delivery_cond); 3046 } 3047 3048 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3049 { 3050 if (!vm_type) { 3051 return 0; 3052 } 3053 3054 if (!strcmp(vm_type, "HV")) { 3055 return 1; 3056 } 3057 3058 if (!strcmp(vm_type, "PR")) { 3059 return 2; 3060 } 3061 3062 error_report("Unknown kvm-type specified '%s'", vm_type); 3063 exit(1); 3064 } 3065 3066 /* 3067 * Implementation of an interface to adjust firmware path 3068 * for the bootindex property handling. 3069 */ 3070 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3071 DeviceState *dev) 3072 { 3073 #define CAST(type, obj, name) \ 3074 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3075 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3076 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3077 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3078 3079 if (d) { 3080 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3081 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3082 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3083 3084 if (spapr) { 3085 /* 3086 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3087 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3088 * 0x8000 | (target << 8) | (bus << 5) | lun 3089 * (see the "Logical unit addressing format" table in SAM5) 3090 */ 3091 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3092 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3093 (uint64_t)id << 48); 3094 } else if (virtio) { 3095 /* 3096 * We use SRP luns of the form 01000000 | (target << 8) | lun 3097 * in the top 32 bits of the 64-bit LUN 3098 * Note: the quote above is from SLOF and it is wrong, 3099 * the actual binding is: 3100 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3101 */ 3102 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3103 if (d->lun >= 256) { 3104 /* Use the LUN "flat space addressing method" */ 3105 id |= 0x4000; 3106 } 3107 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3108 (uint64_t)id << 32); 3109 } else if (usb) { 3110 /* 3111 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3112 * in the top 32 bits of the 64-bit LUN 3113 */ 3114 unsigned usb_port = atoi(usb->port->path); 3115 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3116 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3117 (uint64_t)id << 32); 3118 } 3119 } 3120 3121 /* 3122 * SLOF probes the USB devices, and if it recognizes that the device is a 3123 * storage device, it changes its name to "storage" instead of "usb-host", 3124 * and additionally adds a child node for the SCSI LUN, so the correct 3125 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3126 */ 3127 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3128 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3129 if (usb_host_dev_is_scsi_storage(usbdev)) { 3130 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3131 } 3132 } 3133 3134 if (phb) { 3135 /* Replace "pci" with "pci@800000020000000" */ 3136 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3137 } 3138 3139 if (vsc) { 3140 /* Same logic as virtio above */ 3141 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3142 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3143 } 3144 3145 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3146 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3147 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3148 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3149 } 3150 3151 return NULL; 3152 } 3153 3154 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3155 { 3156 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3157 3158 return g_strdup(spapr->kvm_type); 3159 } 3160 3161 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3162 { 3163 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3164 3165 g_free(spapr->kvm_type); 3166 spapr->kvm_type = g_strdup(value); 3167 } 3168 3169 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3170 { 3171 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3172 3173 return spapr->use_hotplug_event_source; 3174 } 3175 3176 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3177 Error **errp) 3178 { 3179 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3180 3181 spapr->use_hotplug_event_source = value; 3182 } 3183 3184 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3185 { 3186 return true; 3187 } 3188 3189 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3190 { 3191 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3192 3193 switch (spapr->resize_hpt) { 3194 case SPAPR_RESIZE_HPT_DEFAULT: 3195 return g_strdup("default"); 3196 case SPAPR_RESIZE_HPT_DISABLED: 3197 return g_strdup("disabled"); 3198 case SPAPR_RESIZE_HPT_ENABLED: 3199 return g_strdup("enabled"); 3200 case SPAPR_RESIZE_HPT_REQUIRED: 3201 return g_strdup("required"); 3202 } 3203 g_assert_not_reached(); 3204 } 3205 3206 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3207 { 3208 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3209 3210 if (strcmp(value, "default") == 0) { 3211 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3212 } else if (strcmp(value, "disabled") == 0) { 3213 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3214 } else if (strcmp(value, "enabled") == 0) { 3215 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3216 } else if (strcmp(value, "required") == 0) { 3217 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3218 } else { 3219 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3220 } 3221 } 3222 3223 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3224 void *opaque, Error **errp) 3225 { 3226 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3227 } 3228 3229 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3230 void *opaque, Error **errp) 3231 { 3232 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3233 } 3234 3235 static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name, 3236 void *opaque, Error **errp) 3237 { 3238 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3239 } 3240 3241 static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name, 3242 void *opaque, Error **errp) 3243 { 3244 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3245 } 3246 3247 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3248 { 3249 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3250 3251 if (spapr->irq == &spapr_irq_xics_legacy) { 3252 return g_strdup("legacy"); 3253 } else if (spapr->irq == &spapr_irq_xics) { 3254 return g_strdup("xics"); 3255 } else if (spapr->irq == &spapr_irq_xive) { 3256 return g_strdup("xive"); 3257 } else if (spapr->irq == &spapr_irq_dual) { 3258 return g_strdup("dual"); 3259 } 3260 g_assert_not_reached(); 3261 } 3262 3263 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3264 { 3265 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3266 3267 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3268 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3269 return; 3270 } 3271 3272 /* The legacy IRQ backend can not be set */ 3273 if (strcmp(value, "xics") == 0) { 3274 spapr->irq = &spapr_irq_xics; 3275 } else if (strcmp(value, "xive") == 0) { 3276 spapr->irq = &spapr_irq_xive; 3277 } else if (strcmp(value, "dual") == 0) { 3278 spapr->irq = &spapr_irq_dual; 3279 } else { 3280 error_setg(errp, "Bad value for \"ic-mode\" property"); 3281 } 3282 } 3283 3284 static char *spapr_get_host_model(Object *obj, Error **errp) 3285 { 3286 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3287 3288 return g_strdup(spapr->host_model); 3289 } 3290 3291 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3292 { 3293 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3294 3295 g_free(spapr->host_model); 3296 spapr->host_model = g_strdup(value); 3297 } 3298 3299 static char *spapr_get_host_serial(Object *obj, Error **errp) 3300 { 3301 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3302 3303 return g_strdup(spapr->host_serial); 3304 } 3305 3306 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3307 { 3308 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3309 3310 g_free(spapr->host_serial); 3311 spapr->host_serial = g_strdup(value); 3312 } 3313 3314 static void spapr_instance_init(Object *obj) 3315 { 3316 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3317 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3318 3319 spapr->htab_fd = -1; 3320 spapr->use_hotplug_event_source = true; 3321 object_property_add_str(obj, "kvm-type", 3322 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3323 object_property_set_description(obj, "kvm-type", 3324 "Specifies the KVM virtualization mode (HV, PR)", 3325 NULL); 3326 object_property_add_bool(obj, "modern-hotplug-events", 3327 spapr_get_modern_hotplug_events, 3328 spapr_set_modern_hotplug_events, 3329 NULL); 3330 object_property_set_description(obj, "modern-hotplug-events", 3331 "Use dedicated hotplug event mechanism in" 3332 " place of standard EPOW events when possible" 3333 " (required for memory hot-unplug support)", 3334 NULL); 3335 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3336 "Maximum permitted CPU compatibility mode", 3337 &error_fatal); 3338 3339 object_property_add_str(obj, "resize-hpt", 3340 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3341 object_property_set_description(obj, "resize-hpt", 3342 "Resizing of the Hash Page Table (enabled, disabled, required)", 3343 NULL); 3344 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3345 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3346 object_property_set_description(obj, "vsmt", 3347 "Virtual SMT: KVM behaves as if this were" 3348 " the host's SMT mode", &error_abort); 3349 object_property_add_bool(obj, "vfio-no-msix-emulation", 3350 spapr_get_msix_emulation, NULL, NULL); 3351 3352 object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr, 3353 spapr_set_kernel_addr, NULL, &spapr->kernel_addr, 3354 &error_abort); 3355 object_property_set_description(obj, "kernel-addr", 3356 stringify(KERNEL_LOAD_ADDR) 3357 " for -kernel is the default", 3358 NULL); 3359 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3360 /* The machine class defines the default interrupt controller mode */ 3361 spapr->irq = smc->irq; 3362 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3363 spapr_set_ic_mode, NULL); 3364 object_property_set_description(obj, "ic-mode", 3365 "Specifies the interrupt controller mode (xics, xive, dual)", 3366 NULL); 3367 3368 object_property_add_str(obj, "host-model", 3369 spapr_get_host_model, spapr_set_host_model, 3370 &error_abort); 3371 object_property_set_description(obj, "host-model", 3372 "Host model to advertise in guest device tree", &error_abort); 3373 object_property_add_str(obj, "host-serial", 3374 spapr_get_host_serial, spapr_set_host_serial, 3375 &error_abort); 3376 object_property_set_description(obj, "host-serial", 3377 "Host serial number to advertise in guest device tree", &error_abort); 3378 } 3379 3380 static void spapr_machine_finalizefn(Object *obj) 3381 { 3382 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3383 3384 g_free(spapr->kvm_type); 3385 } 3386 3387 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3388 { 3389 cpu_synchronize_state(cs); 3390 ppc_cpu_do_system_reset(cs); 3391 } 3392 3393 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3394 { 3395 CPUState *cs; 3396 3397 CPU_FOREACH(cs) { 3398 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3399 } 3400 } 3401 3402 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3403 void *fdt, int *fdt_start_offset, Error **errp) 3404 { 3405 uint64_t addr; 3406 uint32_t node; 3407 3408 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3409 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3410 &error_abort); 3411 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3412 SPAPR_MEMORY_BLOCK_SIZE); 3413 return 0; 3414 } 3415 3416 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3417 bool dedicated_hp_event_source, Error **errp) 3418 { 3419 SpaprDrc *drc; 3420 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3421 int i; 3422 uint64_t addr = addr_start; 3423 bool hotplugged = spapr_drc_hotplugged(dev); 3424 Error *local_err = NULL; 3425 3426 for (i = 0; i < nr_lmbs; i++) { 3427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3428 addr / SPAPR_MEMORY_BLOCK_SIZE); 3429 g_assert(drc); 3430 3431 spapr_drc_attach(drc, dev, &local_err); 3432 if (local_err) { 3433 while (addr > addr_start) { 3434 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3436 addr / SPAPR_MEMORY_BLOCK_SIZE); 3437 spapr_drc_detach(drc); 3438 } 3439 error_propagate(errp, local_err); 3440 return; 3441 } 3442 if (!hotplugged) { 3443 spapr_drc_reset(drc); 3444 } 3445 addr += SPAPR_MEMORY_BLOCK_SIZE; 3446 } 3447 /* send hotplug notification to the 3448 * guest only in case of hotplugged memory 3449 */ 3450 if (hotplugged) { 3451 if (dedicated_hp_event_source) { 3452 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3453 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3454 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3455 nr_lmbs, 3456 spapr_drc_index(drc)); 3457 } else { 3458 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3459 nr_lmbs); 3460 } 3461 } 3462 } 3463 3464 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3465 Error **errp) 3466 { 3467 Error *local_err = NULL; 3468 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3469 PCDIMMDevice *dimm = PC_DIMM(dev); 3470 uint64_t size, addr, slot; 3471 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3472 3473 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3474 3475 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3476 if (local_err) { 3477 goto out; 3478 } 3479 3480 if (!is_nvdimm) { 3481 addr = object_property_get_uint(OBJECT(dimm), 3482 PC_DIMM_ADDR_PROP, &local_err); 3483 if (local_err) { 3484 goto out_unplug; 3485 } 3486 spapr_add_lmbs(dev, addr, size, 3487 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3488 &local_err); 3489 } else { 3490 slot = object_property_get_uint(OBJECT(dimm), 3491 PC_DIMM_SLOT_PROP, &local_err); 3492 if (local_err) { 3493 goto out_unplug; 3494 } 3495 spapr_add_nvdimm(dev, slot, &local_err); 3496 } 3497 3498 if (local_err) { 3499 goto out_unplug; 3500 } 3501 3502 return; 3503 3504 out_unplug: 3505 pc_dimm_unplug(dimm, MACHINE(ms)); 3506 out: 3507 error_propagate(errp, local_err); 3508 } 3509 3510 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3511 Error **errp) 3512 { 3513 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3514 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3515 const MachineClass *mc = MACHINE_CLASS(smc); 3516 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3517 PCDIMMDevice *dimm = PC_DIMM(dev); 3518 Error *local_err = NULL; 3519 uint64_t size; 3520 Object *memdev; 3521 hwaddr pagesize; 3522 3523 if (!smc->dr_lmb_enabled) { 3524 error_setg(errp, "Memory hotplug not supported for this machine"); 3525 return; 3526 } 3527 3528 if (is_nvdimm && !mc->nvdimm_supported) { 3529 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3530 return; 3531 } 3532 3533 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3534 if (local_err) { 3535 error_propagate(errp, local_err); 3536 return; 3537 } 3538 3539 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3540 error_setg(errp, "Hotplugged memory size must be a multiple of " 3541 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3542 return; 3543 } else if (is_nvdimm) { 3544 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3545 if (local_err) { 3546 error_propagate(errp, local_err); 3547 return; 3548 } 3549 } 3550 3551 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3552 &error_abort); 3553 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3554 spapr_check_pagesize(spapr, pagesize, &local_err); 3555 if (local_err) { 3556 error_propagate(errp, local_err); 3557 return; 3558 } 3559 3560 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3561 } 3562 3563 struct SpaprDimmState { 3564 PCDIMMDevice *dimm; 3565 uint32_t nr_lmbs; 3566 QTAILQ_ENTRY(SpaprDimmState) next; 3567 }; 3568 3569 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3570 PCDIMMDevice *dimm) 3571 { 3572 SpaprDimmState *dimm_state = NULL; 3573 3574 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3575 if (dimm_state->dimm == dimm) { 3576 break; 3577 } 3578 } 3579 return dimm_state; 3580 } 3581 3582 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3583 uint32_t nr_lmbs, 3584 PCDIMMDevice *dimm) 3585 { 3586 SpaprDimmState *ds = NULL; 3587 3588 /* 3589 * If this request is for a DIMM whose removal had failed earlier 3590 * (due to guest's refusal to remove the LMBs), we would have this 3591 * dimm already in the pending_dimm_unplugs list. In that 3592 * case don't add again. 3593 */ 3594 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3595 if (!ds) { 3596 ds = g_malloc0(sizeof(SpaprDimmState)); 3597 ds->nr_lmbs = nr_lmbs; 3598 ds->dimm = dimm; 3599 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3600 } 3601 return ds; 3602 } 3603 3604 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3605 SpaprDimmState *dimm_state) 3606 { 3607 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3608 g_free(dimm_state); 3609 } 3610 3611 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3612 PCDIMMDevice *dimm) 3613 { 3614 SpaprDrc *drc; 3615 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3616 &error_abort); 3617 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3618 uint32_t avail_lmbs = 0; 3619 uint64_t addr_start, addr; 3620 int i; 3621 3622 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3623 &error_abort); 3624 3625 addr = addr_start; 3626 for (i = 0; i < nr_lmbs; i++) { 3627 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3628 addr / SPAPR_MEMORY_BLOCK_SIZE); 3629 g_assert(drc); 3630 if (drc->dev) { 3631 avail_lmbs++; 3632 } 3633 addr += SPAPR_MEMORY_BLOCK_SIZE; 3634 } 3635 3636 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3637 } 3638 3639 /* Callback to be called during DRC release. */ 3640 void spapr_lmb_release(DeviceState *dev) 3641 { 3642 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3643 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3644 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3645 3646 /* This information will get lost if a migration occurs 3647 * during the unplug process. In this case recover it. */ 3648 if (ds == NULL) { 3649 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3650 g_assert(ds); 3651 /* The DRC being examined by the caller at least must be counted */ 3652 g_assert(ds->nr_lmbs); 3653 } 3654 3655 if (--ds->nr_lmbs) { 3656 return; 3657 } 3658 3659 /* 3660 * Now that all the LMBs have been removed by the guest, call the 3661 * unplug handler chain. This can never fail. 3662 */ 3663 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3664 object_unparent(OBJECT(dev)); 3665 } 3666 3667 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3668 { 3669 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3670 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3671 3672 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3673 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3674 spapr_pending_dimm_unplugs_remove(spapr, ds); 3675 } 3676 3677 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3678 DeviceState *dev, Error **errp) 3679 { 3680 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3681 Error *local_err = NULL; 3682 PCDIMMDevice *dimm = PC_DIMM(dev); 3683 uint32_t nr_lmbs; 3684 uint64_t size, addr_start, addr; 3685 int i; 3686 SpaprDrc *drc; 3687 3688 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3689 error_setg(&local_err, 3690 "nvdimm device hot unplug is not supported yet."); 3691 goto out; 3692 } 3693 3694 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3695 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3696 3697 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3698 &local_err); 3699 if (local_err) { 3700 goto out; 3701 } 3702 3703 /* 3704 * An existing pending dimm state for this DIMM means that there is an 3705 * unplug operation in progress, waiting for the spapr_lmb_release 3706 * callback to complete the job (BQL can't cover that far). In this case, 3707 * bail out to avoid detaching DRCs that were already released. 3708 */ 3709 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3710 error_setg(&local_err, 3711 "Memory unplug already in progress for device %s", 3712 dev->id); 3713 goto out; 3714 } 3715 3716 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3717 3718 addr = addr_start; 3719 for (i = 0; i < nr_lmbs; i++) { 3720 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3721 addr / SPAPR_MEMORY_BLOCK_SIZE); 3722 g_assert(drc); 3723 3724 spapr_drc_detach(drc); 3725 addr += SPAPR_MEMORY_BLOCK_SIZE; 3726 } 3727 3728 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3729 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3730 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3731 nr_lmbs, spapr_drc_index(drc)); 3732 out: 3733 error_propagate(errp, local_err); 3734 } 3735 3736 /* Callback to be called during DRC release. */ 3737 void spapr_core_release(DeviceState *dev) 3738 { 3739 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3740 3741 /* Call the unplug handler chain. This can never fail. */ 3742 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3743 object_unparent(OBJECT(dev)); 3744 } 3745 3746 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3747 { 3748 MachineState *ms = MACHINE(hotplug_dev); 3749 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3750 CPUCore *cc = CPU_CORE(dev); 3751 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3752 3753 if (smc->pre_2_10_has_unused_icps) { 3754 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3755 int i; 3756 3757 for (i = 0; i < cc->nr_threads; i++) { 3758 CPUState *cs = CPU(sc->threads[i]); 3759 3760 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3761 } 3762 } 3763 3764 assert(core_slot); 3765 core_slot->cpu = NULL; 3766 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3767 } 3768 3769 static 3770 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3771 Error **errp) 3772 { 3773 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3774 int index; 3775 SpaprDrc *drc; 3776 CPUCore *cc = CPU_CORE(dev); 3777 3778 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3779 error_setg(errp, "Unable to find CPU core with core-id: %d", 3780 cc->core_id); 3781 return; 3782 } 3783 if (index == 0) { 3784 error_setg(errp, "Boot CPU core may not be unplugged"); 3785 return; 3786 } 3787 3788 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3789 spapr_vcpu_id(spapr, cc->core_id)); 3790 g_assert(drc); 3791 3792 if (!spapr_drc_unplug_requested(drc)) { 3793 spapr_drc_detach(drc); 3794 spapr_hotplug_req_remove_by_index(drc); 3795 } 3796 } 3797 3798 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3799 void *fdt, int *fdt_start_offset, Error **errp) 3800 { 3801 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3802 CPUState *cs = CPU(core->threads[0]); 3803 PowerPCCPU *cpu = POWERPC_CPU(cs); 3804 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3805 int id = spapr_get_vcpu_id(cpu); 3806 char *nodename; 3807 int offset; 3808 3809 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3810 offset = fdt_add_subnode(fdt, 0, nodename); 3811 g_free(nodename); 3812 3813 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3814 3815 *fdt_start_offset = offset; 3816 return 0; 3817 } 3818 3819 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3820 Error **errp) 3821 { 3822 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3823 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3824 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3825 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3826 CPUCore *cc = CPU_CORE(dev); 3827 CPUState *cs; 3828 SpaprDrc *drc; 3829 Error *local_err = NULL; 3830 CPUArchId *core_slot; 3831 int index; 3832 bool hotplugged = spapr_drc_hotplugged(dev); 3833 int i; 3834 3835 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3836 if (!core_slot) { 3837 error_setg(errp, "Unable to find CPU core with core-id: %d", 3838 cc->core_id); 3839 return; 3840 } 3841 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3842 spapr_vcpu_id(spapr, cc->core_id)); 3843 3844 g_assert(drc || !mc->has_hotpluggable_cpus); 3845 3846 if (drc) { 3847 spapr_drc_attach(drc, dev, &local_err); 3848 if (local_err) { 3849 error_propagate(errp, local_err); 3850 return; 3851 } 3852 3853 if (hotplugged) { 3854 /* 3855 * Send hotplug notification interrupt to the guest only 3856 * in case of hotplugged CPUs. 3857 */ 3858 spapr_hotplug_req_add_by_index(drc); 3859 } else { 3860 spapr_drc_reset(drc); 3861 } 3862 } 3863 3864 core_slot->cpu = OBJECT(dev); 3865 3866 if (smc->pre_2_10_has_unused_icps) { 3867 for (i = 0; i < cc->nr_threads; i++) { 3868 cs = CPU(core->threads[i]); 3869 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3870 } 3871 } 3872 3873 /* 3874 * Set compatibility mode to match the boot CPU, which was either set 3875 * by the machine reset code or by CAS. 3876 */ 3877 if (hotplugged) { 3878 for (i = 0; i < cc->nr_threads; i++) { 3879 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3880 &local_err); 3881 if (local_err) { 3882 error_propagate(errp, local_err); 3883 return; 3884 } 3885 } 3886 } 3887 } 3888 3889 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3890 Error **errp) 3891 { 3892 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3893 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3894 Error *local_err = NULL; 3895 CPUCore *cc = CPU_CORE(dev); 3896 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3897 const char *type = object_get_typename(OBJECT(dev)); 3898 CPUArchId *core_slot; 3899 int index; 3900 unsigned int smp_threads = machine->smp.threads; 3901 3902 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3903 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3904 goto out; 3905 } 3906 3907 if (strcmp(base_core_type, type)) { 3908 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3909 goto out; 3910 } 3911 3912 if (cc->core_id % smp_threads) { 3913 error_setg(&local_err, "invalid core id %d", cc->core_id); 3914 goto out; 3915 } 3916 3917 /* 3918 * In general we should have homogeneous threads-per-core, but old 3919 * (pre hotplug support) machine types allow the last core to have 3920 * reduced threads as a compatibility hack for when we allowed 3921 * total vcpus not a multiple of threads-per-core. 3922 */ 3923 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3924 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3925 cc->nr_threads, smp_threads); 3926 goto out; 3927 } 3928 3929 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3930 if (!core_slot) { 3931 error_setg(&local_err, "core id %d out of range", cc->core_id); 3932 goto out; 3933 } 3934 3935 if (core_slot->cpu) { 3936 error_setg(&local_err, "core %d already populated", cc->core_id); 3937 goto out; 3938 } 3939 3940 numa_cpu_pre_plug(core_slot, dev, &local_err); 3941 3942 out: 3943 error_propagate(errp, local_err); 3944 } 3945 3946 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3947 void *fdt, int *fdt_start_offset, Error **errp) 3948 { 3949 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3950 int intc_phandle; 3951 3952 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3953 if (intc_phandle <= 0) { 3954 return -1; 3955 } 3956 3957 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3958 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3959 return -1; 3960 } 3961 3962 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3963 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3964 3965 return 0; 3966 } 3967 3968 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3969 Error **errp) 3970 { 3971 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3972 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3973 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3974 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3975 3976 if (dev->hotplugged && !smc->dr_phb_enabled) { 3977 error_setg(errp, "PHB hotplug not supported for this machine"); 3978 return; 3979 } 3980 3981 if (sphb->index == (uint32_t)-1) { 3982 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3983 return; 3984 } 3985 3986 /* 3987 * This will check that sphb->index doesn't exceed the maximum number of 3988 * PHBs for the current machine type. 3989 */ 3990 smc->phb_placement(spapr, sphb->index, 3991 &sphb->buid, &sphb->io_win_addr, 3992 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3993 windows_supported, sphb->dma_liobn, 3994 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3995 errp); 3996 } 3997 3998 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3999 Error **errp) 4000 { 4001 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4002 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4003 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4004 SpaprDrc *drc; 4005 bool hotplugged = spapr_drc_hotplugged(dev); 4006 Error *local_err = NULL; 4007 4008 if (!smc->dr_phb_enabled) { 4009 return; 4010 } 4011 4012 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4013 /* hotplug hooks should check it's enabled before getting this far */ 4014 assert(drc); 4015 4016 spapr_drc_attach(drc, DEVICE(dev), &local_err); 4017 if (local_err) { 4018 error_propagate(errp, local_err); 4019 return; 4020 } 4021 4022 if (hotplugged) { 4023 spapr_hotplug_req_add_by_index(drc); 4024 } else { 4025 spapr_drc_reset(drc); 4026 } 4027 } 4028 4029 void spapr_phb_release(DeviceState *dev) 4030 { 4031 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4032 4033 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4034 object_unparent(OBJECT(dev)); 4035 } 4036 4037 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4038 { 4039 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4040 } 4041 4042 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4043 DeviceState *dev, Error **errp) 4044 { 4045 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4046 SpaprDrc *drc; 4047 4048 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4049 assert(drc); 4050 4051 if (!spapr_drc_unplug_requested(drc)) { 4052 spapr_drc_detach(drc); 4053 spapr_hotplug_req_remove_by_index(drc); 4054 } 4055 } 4056 4057 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4058 Error **errp) 4059 { 4060 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4061 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4062 4063 if (spapr->tpm_proxy != NULL) { 4064 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4065 return; 4066 } 4067 4068 spapr->tpm_proxy = tpm_proxy; 4069 } 4070 4071 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4072 { 4073 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4074 4075 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4076 object_unparent(OBJECT(dev)); 4077 spapr->tpm_proxy = NULL; 4078 } 4079 4080 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4081 DeviceState *dev, Error **errp) 4082 { 4083 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4084 spapr_memory_plug(hotplug_dev, dev, errp); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4086 spapr_core_plug(hotplug_dev, dev, errp); 4087 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4088 spapr_phb_plug(hotplug_dev, dev, errp); 4089 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4090 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4091 } 4092 } 4093 4094 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4095 DeviceState *dev, Error **errp) 4096 { 4097 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4098 spapr_memory_unplug(hotplug_dev, dev); 4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4100 spapr_core_unplug(hotplug_dev, dev); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4102 spapr_phb_unplug(hotplug_dev, dev); 4103 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4104 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4105 } 4106 } 4107 4108 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4109 DeviceState *dev, Error **errp) 4110 { 4111 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4112 MachineClass *mc = MACHINE_GET_CLASS(sms); 4113 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4114 4115 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4116 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4117 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4118 } else { 4119 /* NOTE: this means there is a window after guest reset, prior to 4120 * CAS negotiation, where unplug requests will fail due to the 4121 * capability not being detected yet. This is a bit different than 4122 * the case with PCI unplug, where the events will be queued and 4123 * eventually handled by the guest after boot 4124 */ 4125 error_setg(errp, "Memory hot unplug not supported for this guest"); 4126 } 4127 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4128 if (!mc->has_hotpluggable_cpus) { 4129 error_setg(errp, "CPU hot unplug not supported on this machine"); 4130 return; 4131 } 4132 spapr_core_unplug_request(hotplug_dev, dev, errp); 4133 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4134 if (!smc->dr_phb_enabled) { 4135 error_setg(errp, "PHB hot unplug not supported on this machine"); 4136 return; 4137 } 4138 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4139 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4140 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4141 } 4142 } 4143 4144 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4145 DeviceState *dev, Error **errp) 4146 { 4147 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4148 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4149 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4150 spapr_core_pre_plug(hotplug_dev, dev, errp); 4151 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4152 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4153 } 4154 } 4155 4156 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4157 DeviceState *dev) 4158 { 4159 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4160 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4161 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4162 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4163 return HOTPLUG_HANDLER(machine); 4164 } 4165 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4166 PCIDevice *pcidev = PCI_DEVICE(dev); 4167 PCIBus *root = pci_device_root_bus(pcidev); 4168 SpaprPhbState *phb = 4169 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4170 TYPE_SPAPR_PCI_HOST_BRIDGE); 4171 4172 if (phb) { 4173 return HOTPLUG_HANDLER(phb); 4174 } 4175 } 4176 return NULL; 4177 } 4178 4179 static CpuInstanceProperties 4180 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4181 { 4182 CPUArchId *core_slot; 4183 MachineClass *mc = MACHINE_GET_CLASS(machine); 4184 4185 /* make sure possible_cpu are intialized */ 4186 mc->possible_cpu_arch_ids(machine); 4187 /* get CPU core slot containing thread that matches cpu_index */ 4188 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4189 assert(core_slot); 4190 return core_slot->props; 4191 } 4192 4193 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4194 { 4195 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4196 } 4197 4198 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4199 { 4200 int i; 4201 unsigned int smp_threads = machine->smp.threads; 4202 unsigned int smp_cpus = machine->smp.cpus; 4203 const char *core_type; 4204 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4205 MachineClass *mc = MACHINE_GET_CLASS(machine); 4206 4207 if (!mc->has_hotpluggable_cpus) { 4208 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4209 } 4210 if (machine->possible_cpus) { 4211 assert(machine->possible_cpus->len == spapr_max_cores); 4212 return machine->possible_cpus; 4213 } 4214 4215 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4216 if (!core_type) { 4217 error_report("Unable to find sPAPR CPU Core definition"); 4218 exit(1); 4219 } 4220 4221 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4222 sizeof(CPUArchId) * spapr_max_cores); 4223 machine->possible_cpus->len = spapr_max_cores; 4224 for (i = 0; i < machine->possible_cpus->len; i++) { 4225 int core_id = i * smp_threads; 4226 4227 machine->possible_cpus->cpus[i].type = core_type; 4228 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4229 machine->possible_cpus->cpus[i].arch_id = core_id; 4230 machine->possible_cpus->cpus[i].props.has_core_id = true; 4231 machine->possible_cpus->cpus[i].props.core_id = core_id; 4232 } 4233 return machine->possible_cpus; 4234 } 4235 4236 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4237 uint64_t *buid, hwaddr *pio, 4238 hwaddr *mmio32, hwaddr *mmio64, 4239 unsigned n_dma, uint32_t *liobns, 4240 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4241 { 4242 /* 4243 * New-style PHB window placement. 4244 * 4245 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4246 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4247 * windows. 4248 * 4249 * Some guest kernels can't work with MMIO windows above 1<<46 4250 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4251 * 4252 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4253 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4254 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4255 * 1TiB 64-bit MMIO windows for each PHB. 4256 */ 4257 const uint64_t base_buid = 0x800000020000000ULL; 4258 int i; 4259 4260 /* Sanity check natural alignments */ 4261 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4262 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4263 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4264 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4265 /* Sanity check bounds */ 4266 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4267 SPAPR_PCI_MEM32_WIN_SIZE); 4268 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4269 SPAPR_PCI_MEM64_WIN_SIZE); 4270 4271 if (index >= SPAPR_MAX_PHBS) { 4272 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4273 SPAPR_MAX_PHBS - 1); 4274 return; 4275 } 4276 4277 *buid = base_buid + index; 4278 for (i = 0; i < n_dma; ++i) { 4279 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4280 } 4281 4282 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4283 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4284 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4285 4286 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4287 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4288 } 4289 4290 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4291 { 4292 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4293 4294 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4295 } 4296 4297 static void spapr_ics_resend(XICSFabric *dev) 4298 { 4299 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4300 4301 ics_resend(spapr->ics); 4302 } 4303 4304 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4305 { 4306 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4307 4308 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4309 } 4310 4311 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4312 Monitor *mon) 4313 { 4314 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4315 4316 spapr_irq_print_info(spapr, mon); 4317 monitor_printf(mon, "irqchip: %s\n", 4318 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4319 } 4320 4321 /* 4322 * This is a XIVE only operation 4323 */ 4324 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4325 uint8_t nvt_blk, uint32_t nvt_idx, 4326 bool cam_ignore, uint8_t priority, 4327 uint32_t logic_serv, XiveTCTXMatch *match) 4328 { 4329 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4330 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4331 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4332 int count; 4333 4334 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4335 priority, logic_serv, match); 4336 if (count < 0) { 4337 return count; 4338 } 4339 4340 /* 4341 * When we implement the save and restore of the thread interrupt 4342 * contexts in the enter/exit CPU handlers of the machine and the 4343 * escalations in QEMU, we should be able to handle non dispatched 4344 * vCPUs. 4345 * 4346 * Until this is done, the sPAPR machine should find at least one 4347 * matching context always. 4348 */ 4349 if (count == 0) { 4350 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4351 nvt_blk, nvt_idx); 4352 } 4353 4354 return count; 4355 } 4356 4357 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4358 { 4359 return cpu->vcpu_id; 4360 } 4361 4362 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4363 { 4364 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4365 MachineState *ms = MACHINE(spapr); 4366 int vcpu_id; 4367 4368 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4369 4370 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4371 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4372 error_append_hint(errp, "Adjust the number of cpus to %d " 4373 "or try to raise the number of threads per core\n", 4374 vcpu_id * ms->smp.threads / spapr->vsmt); 4375 return; 4376 } 4377 4378 cpu->vcpu_id = vcpu_id; 4379 } 4380 4381 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4382 { 4383 CPUState *cs; 4384 4385 CPU_FOREACH(cs) { 4386 PowerPCCPU *cpu = POWERPC_CPU(cs); 4387 4388 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4389 return cpu; 4390 } 4391 } 4392 4393 return NULL; 4394 } 4395 4396 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4397 { 4398 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4399 4400 /* These are only called by TCG, KVM maintains dispatch state */ 4401 4402 spapr_cpu->prod = false; 4403 if (spapr_cpu->vpa_addr) { 4404 CPUState *cs = CPU(cpu); 4405 uint32_t dispatch; 4406 4407 dispatch = ldl_be_phys(cs->as, 4408 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4409 dispatch++; 4410 if ((dispatch & 1) != 0) { 4411 qemu_log_mask(LOG_GUEST_ERROR, 4412 "VPA: incorrect dispatch counter value for " 4413 "dispatched partition %u, correcting.\n", dispatch); 4414 dispatch++; 4415 } 4416 stl_be_phys(cs->as, 4417 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4418 } 4419 } 4420 4421 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4422 { 4423 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4424 4425 if (spapr_cpu->vpa_addr) { 4426 CPUState *cs = CPU(cpu); 4427 uint32_t dispatch; 4428 4429 dispatch = ldl_be_phys(cs->as, 4430 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4431 dispatch++; 4432 if ((dispatch & 1) != 1) { 4433 qemu_log_mask(LOG_GUEST_ERROR, 4434 "VPA: incorrect dispatch counter value for " 4435 "preempted partition %u, correcting.\n", dispatch); 4436 dispatch++; 4437 } 4438 stl_be_phys(cs->as, 4439 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4440 } 4441 } 4442 4443 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4444 { 4445 MachineClass *mc = MACHINE_CLASS(oc); 4446 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4447 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4448 NMIClass *nc = NMI_CLASS(oc); 4449 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4450 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4451 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4452 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4453 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4454 4455 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4456 mc->ignore_boot_device_suffixes = true; 4457 4458 /* 4459 * We set up the default / latest behaviour here. The class_init 4460 * functions for the specific versioned machine types can override 4461 * these details for backwards compatibility 4462 */ 4463 mc->init = spapr_machine_init; 4464 mc->reset = spapr_machine_reset; 4465 mc->block_default_type = IF_SCSI; 4466 mc->max_cpus = 1024; 4467 mc->no_parallel = 1; 4468 mc->default_boot_order = ""; 4469 mc->default_ram_size = 512 * MiB; 4470 mc->default_ram_id = "ppc_spapr.ram"; 4471 mc->default_display = "std"; 4472 mc->kvm_type = spapr_kvm_type; 4473 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4474 mc->pci_allow_0_address = true; 4475 assert(!mc->get_hotplug_handler); 4476 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4477 hc->pre_plug = spapr_machine_device_pre_plug; 4478 hc->plug = spapr_machine_device_plug; 4479 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4480 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4481 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4482 hc->unplug_request = spapr_machine_device_unplug_request; 4483 hc->unplug = spapr_machine_device_unplug; 4484 4485 smc->dr_lmb_enabled = true; 4486 smc->update_dt_enabled = true; 4487 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4488 mc->has_hotpluggable_cpus = true; 4489 mc->nvdimm_supported = true; 4490 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4491 fwc->get_dev_path = spapr_get_fw_dev_path; 4492 nc->nmi_monitor_handler = spapr_nmi; 4493 smc->phb_placement = spapr_phb_placement; 4494 vhc->hypercall = emulate_spapr_hypercall; 4495 vhc->hpt_mask = spapr_hpt_mask; 4496 vhc->map_hptes = spapr_map_hptes; 4497 vhc->unmap_hptes = spapr_unmap_hptes; 4498 vhc->hpte_set_c = spapr_hpte_set_c; 4499 vhc->hpte_set_r = spapr_hpte_set_r; 4500 vhc->get_pate = spapr_get_pate; 4501 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4502 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4503 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4504 xic->ics_get = spapr_ics_get; 4505 xic->ics_resend = spapr_ics_resend; 4506 xic->icp_get = spapr_icp_get; 4507 ispc->print_info = spapr_pic_print_info; 4508 /* Force NUMA node memory size to be a multiple of 4509 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4510 * in which LMBs are represented and hot-added 4511 */ 4512 mc->numa_mem_align_shift = 28; 4513 mc->numa_mem_supported = true; 4514 mc->auto_enable_numa = true; 4515 4516 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4517 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4518 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4519 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4520 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4521 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4522 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4523 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4524 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4525 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4526 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON; 4527 spapr_caps_add_properties(smc, &error_abort); 4528 smc->irq = &spapr_irq_dual; 4529 smc->dr_phb_enabled = true; 4530 smc->linux_pci_probe = true; 4531 smc->smp_threads_vsmt = true; 4532 smc->nr_xirqs = SPAPR_NR_XIRQS; 4533 xfc->match_nvt = spapr_match_nvt; 4534 } 4535 4536 static const TypeInfo spapr_machine_info = { 4537 .name = TYPE_SPAPR_MACHINE, 4538 .parent = TYPE_MACHINE, 4539 .abstract = true, 4540 .instance_size = sizeof(SpaprMachineState), 4541 .instance_init = spapr_instance_init, 4542 .instance_finalize = spapr_machine_finalizefn, 4543 .class_size = sizeof(SpaprMachineClass), 4544 .class_init = spapr_machine_class_init, 4545 .interfaces = (InterfaceInfo[]) { 4546 { TYPE_FW_PATH_PROVIDER }, 4547 { TYPE_NMI }, 4548 { TYPE_HOTPLUG_HANDLER }, 4549 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4550 { TYPE_XICS_FABRIC }, 4551 { TYPE_INTERRUPT_STATS_PROVIDER }, 4552 { TYPE_XIVE_FABRIC }, 4553 { } 4554 }, 4555 }; 4556 4557 static void spapr_machine_latest_class_options(MachineClass *mc) 4558 { 4559 mc->alias = "pseries"; 4560 mc->is_default = true; 4561 } 4562 4563 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4564 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4565 void *data) \ 4566 { \ 4567 MachineClass *mc = MACHINE_CLASS(oc); \ 4568 spapr_machine_##suffix##_class_options(mc); \ 4569 if (latest) { \ 4570 spapr_machine_latest_class_options(mc); \ 4571 } \ 4572 } \ 4573 static const TypeInfo spapr_machine_##suffix##_info = { \ 4574 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4575 .parent = TYPE_SPAPR_MACHINE, \ 4576 .class_init = spapr_machine_##suffix##_class_init, \ 4577 }; \ 4578 static void spapr_machine_register_##suffix(void) \ 4579 { \ 4580 type_register(&spapr_machine_##suffix##_info); \ 4581 } \ 4582 type_init(spapr_machine_register_##suffix) 4583 4584 /* 4585 * pseries-5.0 4586 */ 4587 static void spapr_machine_5_0_class_options(MachineClass *mc) 4588 { 4589 /* Defaults for the latest behaviour inherited from the base class */ 4590 } 4591 4592 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4593 4594 /* 4595 * pseries-4.2 4596 */ 4597 static void spapr_machine_4_2_class_options(MachineClass *mc) 4598 { 4599 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4600 4601 spapr_machine_5_0_class_options(mc); 4602 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4603 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4604 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; 4605 smc->rma_limit = 16 * GiB; 4606 mc->nvdimm_supported = false; 4607 } 4608 4609 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4610 4611 /* 4612 * pseries-4.1 4613 */ 4614 static void spapr_machine_4_1_class_options(MachineClass *mc) 4615 { 4616 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4617 static GlobalProperty compat[] = { 4618 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4619 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4620 }; 4621 4622 spapr_machine_4_2_class_options(mc); 4623 smc->linux_pci_probe = false; 4624 smc->smp_threads_vsmt = false; 4625 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4626 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4627 } 4628 4629 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4630 4631 /* 4632 * pseries-4.0 4633 */ 4634 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4635 uint64_t *buid, hwaddr *pio, 4636 hwaddr *mmio32, hwaddr *mmio64, 4637 unsigned n_dma, uint32_t *liobns, 4638 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4639 { 4640 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4641 nv2gpa, nv2atsd, errp); 4642 *nv2gpa = 0; 4643 *nv2atsd = 0; 4644 } 4645 4646 static void spapr_machine_4_0_class_options(MachineClass *mc) 4647 { 4648 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4649 4650 spapr_machine_4_1_class_options(mc); 4651 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4652 smc->phb_placement = phb_placement_4_0; 4653 smc->irq = &spapr_irq_xics; 4654 smc->pre_4_1_migration = true; 4655 } 4656 4657 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4658 4659 /* 4660 * pseries-3.1 4661 */ 4662 static void spapr_machine_3_1_class_options(MachineClass *mc) 4663 { 4664 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4665 4666 spapr_machine_4_0_class_options(mc); 4667 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4668 4669 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4670 smc->update_dt_enabled = false; 4671 smc->dr_phb_enabled = false; 4672 smc->broken_host_serial_model = true; 4673 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4674 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4675 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4676 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4677 } 4678 4679 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4680 4681 /* 4682 * pseries-3.0 4683 */ 4684 4685 static void spapr_machine_3_0_class_options(MachineClass *mc) 4686 { 4687 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4688 4689 spapr_machine_3_1_class_options(mc); 4690 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4691 4692 smc->legacy_irq_allocation = true; 4693 smc->nr_xirqs = 0x400; 4694 smc->irq = &spapr_irq_xics_legacy; 4695 } 4696 4697 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4698 4699 /* 4700 * pseries-2.12 4701 */ 4702 static void spapr_machine_2_12_class_options(MachineClass *mc) 4703 { 4704 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4705 static GlobalProperty compat[] = { 4706 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4707 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4708 }; 4709 4710 spapr_machine_3_0_class_options(mc); 4711 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4712 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4713 4714 /* We depend on kvm_enabled() to choose a default value for the 4715 * hpt-max-page-size capability. Of course we can't do it here 4716 * because this is too early and the HW accelerator isn't initialzed 4717 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4718 */ 4719 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4720 } 4721 4722 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4723 4724 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4725 { 4726 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4727 4728 spapr_machine_2_12_class_options(mc); 4729 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4730 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4731 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4732 } 4733 4734 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4735 4736 /* 4737 * pseries-2.11 4738 */ 4739 4740 static void spapr_machine_2_11_class_options(MachineClass *mc) 4741 { 4742 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4743 4744 spapr_machine_2_12_class_options(mc); 4745 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4746 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4747 } 4748 4749 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4750 4751 /* 4752 * pseries-2.10 4753 */ 4754 4755 static void spapr_machine_2_10_class_options(MachineClass *mc) 4756 { 4757 spapr_machine_2_11_class_options(mc); 4758 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4759 } 4760 4761 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4762 4763 /* 4764 * pseries-2.9 4765 */ 4766 4767 static void spapr_machine_2_9_class_options(MachineClass *mc) 4768 { 4769 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4770 static GlobalProperty compat[] = { 4771 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4772 }; 4773 4774 spapr_machine_2_10_class_options(mc); 4775 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4776 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4777 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4778 smc->pre_2_10_has_unused_icps = true; 4779 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4780 } 4781 4782 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4783 4784 /* 4785 * pseries-2.8 4786 */ 4787 4788 static void spapr_machine_2_8_class_options(MachineClass *mc) 4789 { 4790 static GlobalProperty compat[] = { 4791 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4792 }; 4793 4794 spapr_machine_2_9_class_options(mc); 4795 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4796 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4797 mc->numa_mem_align_shift = 23; 4798 } 4799 4800 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4801 4802 /* 4803 * pseries-2.7 4804 */ 4805 4806 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4807 uint64_t *buid, hwaddr *pio, 4808 hwaddr *mmio32, hwaddr *mmio64, 4809 unsigned n_dma, uint32_t *liobns, 4810 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4811 { 4812 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4813 const uint64_t base_buid = 0x800000020000000ULL; 4814 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4815 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4816 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4817 const uint32_t max_index = 255; 4818 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4819 4820 uint64_t ram_top = MACHINE(spapr)->ram_size; 4821 hwaddr phb0_base, phb_base; 4822 int i; 4823 4824 /* Do we have device memory? */ 4825 if (MACHINE(spapr)->maxram_size > ram_top) { 4826 /* Can't just use maxram_size, because there may be an 4827 * alignment gap between normal and device memory regions 4828 */ 4829 ram_top = MACHINE(spapr)->device_memory->base + 4830 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4831 } 4832 4833 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4834 4835 if (index > max_index) { 4836 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4837 max_index); 4838 return; 4839 } 4840 4841 *buid = base_buid + index; 4842 for (i = 0; i < n_dma; ++i) { 4843 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4844 } 4845 4846 phb_base = phb0_base + index * phb_spacing; 4847 *pio = phb_base + pio_offset; 4848 *mmio32 = phb_base + mmio_offset; 4849 /* 4850 * We don't set the 64-bit MMIO window, relying on the PHB's 4851 * fallback behaviour of automatically splitting a large "32-bit" 4852 * window into contiguous 32-bit and 64-bit windows 4853 */ 4854 4855 *nv2gpa = 0; 4856 *nv2atsd = 0; 4857 } 4858 4859 static void spapr_machine_2_7_class_options(MachineClass *mc) 4860 { 4861 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4862 static GlobalProperty compat[] = { 4863 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4864 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4865 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4866 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4867 }; 4868 4869 spapr_machine_2_8_class_options(mc); 4870 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4871 mc->default_machine_opts = "modern-hotplug-events=off"; 4872 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4873 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4874 smc->phb_placement = phb_placement_2_7; 4875 } 4876 4877 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4878 4879 /* 4880 * pseries-2.6 4881 */ 4882 4883 static void spapr_machine_2_6_class_options(MachineClass *mc) 4884 { 4885 static GlobalProperty compat[] = { 4886 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4887 }; 4888 4889 spapr_machine_2_7_class_options(mc); 4890 mc->has_hotpluggable_cpus = false; 4891 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4892 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4893 } 4894 4895 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4896 4897 /* 4898 * pseries-2.5 4899 */ 4900 4901 static void spapr_machine_2_5_class_options(MachineClass *mc) 4902 { 4903 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4904 static GlobalProperty compat[] = { 4905 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4906 }; 4907 4908 spapr_machine_2_6_class_options(mc); 4909 smc->use_ohci_by_default = true; 4910 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4911 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4912 } 4913 4914 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4915 4916 /* 4917 * pseries-2.4 4918 */ 4919 4920 static void spapr_machine_2_4_class_options(MachineClass *mc) 4921 { 4922 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4923 4924 spapr_machine_2_5_class_options(mc); 4925 smc->dr_lmb_enabled = false; 4926 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4927 } 4928 4929 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4930 4931 /* 4932 * pseries-2.3 4933 */ 4934 4935 static void spapr_machine_2_3_class_options(MachineClass *mc) 4936 { 4937 static GlobalProperty compat[] = { 4938 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4939 }; 4940 spapr_machine_2_4_class_options(mc); 4941 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4942 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4943 } 4944 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4945 4946 /* 4947 * pseries-2.2 4948 */ 4949 4950 static void spapr_machine_2_2_class_options(MachineClass *mc) 4951 { 4952 static GlobalProperty compat[] = { 4953 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4954 }; 4955 4956 spapr_machine_2_3_class_options(mc); 4957 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4958 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4959 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4960 } 4961 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4962 4963 /* 4964 * pseries-2.1 4965 */ 4966 4967 static void spapr_machine_2_1_class_options(MachineClass *mc) 4968 { 4969 spapr_machine_2_2_class_options(mc); 4970 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4971 } 4972 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4973 4974 static void spapr_machine_register_types(void) 4975 { 4976 type_register_static(&spapr_machine_info); 4977 } 4978 4979 type_init(spapr_machine_register_types) 4980