1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "qemu/log.h" 42 #include "hw/fw-path-provider.h" 43 #include "elf.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/cpus.h" 47 #include "sysemu/hw_accel.h" 48 #include "kvm_ppc.h" 49 #include "migration/misc.h" 50 #include "migration/qemu-file-types.h" 51 #include "migration/global_state.h" 52 #include "migration/register.h" 53 #include "migration/blocker.h" 54 #include "mmu-hash64.h" 55 #include "mmu-book3s-v3.h" 56 #include "cpu-models.h" 57 #include "hw/core/cpu.h" 58 59 #include "hw/ppc/ppc.h" 60 #include "hw/loader.h" 61 62 #include "hw/ppc/fdt.h" 63 #include "hw/ppc/spapr.h" 64 #include "hw/ppc/spapr_nested.h" 65 #include "hw/ppc/spapr_vio.h" 66 #include "hw/ppc/vof.h" 67 #include "hw/qdev-properties.h" 68 #include "hw/pci-host/spapr.h" 69 #include "hw/pci/msi.h" 70 71 #include "hw/pci/pci.h" 72 #include "hw/scsi/scsi.h" 73 #include "hw/virtio/virtio-scsi.h" 74 #include "hw/virtio/vhost-scsi-common.h" 75 76 #include "exec/ram_addr.h" 77 #include "hw/usb.h" 78 #include "qemu/config-file.h" 79 #include "qemu/error-report.h" 80 #include "trace.h" 81 #include "hw/nmi.h" 82 #include "hw/intc/intc.h" 83 84 #include "hw/ppc/spapr_cpu_core.h" 85 #include "hw/mem/memory-device.h" 86 #include "hw/ppc/spapr_tpm_proxy.h" 87 #include "hw/ppc/spapr_nvdimm.h" 88 #include "hw/ppc/spapr_numa.h" 89 #include "hw/ppc/pef.h" 90 91 #include "monitor/monitor.h" 92 93 #include <libfdt.h> 94 95 /* SLOF memory layout: 96 * 97 * SLOF raw image loaded at 0, copies its romfs right below the flat 98 * device-tree, then position SLOF itself 31M below that 99 * 100 * So we set FW_OVERHEAD to 40MB which should account for all of that 101 * and more 102 * 103 * We load our kernel at 4M, leaving space for SLOF initial image 104 */ 105 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 106 #define FW_MAX_SIZE 0x400000 107 #define FW_FILE_NAME "slof.bin" 108 #define FW_FILE_NAME_VOF "vof.bin" 109 #define FW_OVERHEAD 0x2800000 110 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 111 112 #define MIN_RMA_SLOF (128 * MiB) 113 114 #define PHANDLE_INTC 0x00001111 115 116 /* These two functions implement the VCPU id numbering: one to compute them 117 * all and one to identify thread 0 of a VCORE. Any change to the first one 118 * is likely to have an impact on the second one, so let's keep them close. 119 */ 120 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 121 { 122 MachineState *ms = MACHINE(spapr); 123 unsigned int smp_threads = ms->smp.threads; 124 125 assert(spapr->vsmt); 126 return 127 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 128 } 129 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 130 PowerPCCPU *cpu) 131 { 132 assert(spapr->vsmt); 133 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 134 } 135 136 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 137 { 138 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 139 * and newer QEMUs don't even have them. In both cases, we don't want 140 * to send anything on the wire. 141 */ 142 return false; 143 } 144 145 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 146 /* 147 * Hack ahead. We can't have two devices with the same name and 148 * instance id. So I rename this to pass make check. 149 * Real help from people who knows the hardware is needed. 150 */ 151 .name = "icp/server", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .needed = pre_2_10_vmstate_dummy_icp_needed, 155 .fields = (const VMStateField[]) { 156 VMSTATE_UNUSED(4), /* uint32_t xirr */ 157 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 158 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 159 VMSTATE_END_OF_LIST() 160 }, 161 }; 162 163 /* 164 * See comment in hw/intc/xics.c:icp_realize() 165 * 166 * You have to remove vmstate_replace_hack_for_ppc() when you remove 167 * the machine types that need the following function. 168 */ 169 static void pre_2_10_vmstate_register_dummy_icp(int i) 170 { 171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 172 (void *)(uintptr_t) i); 173 } 174 175 /* 176 * See comment in hw/intc/xics.c:icp_realize() 177 * 178 * You have to remove vmstate_replace_hack_for_ppc() when you remove 179 * the machine types that need the following function. 180 */ 181 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 182 { 183 /* 184 * This used to be: 185 * 186 * vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 187 * (void *)(uintptr_t) i); 188 */ 189 } 190 191 int spapr_max_server_number(SpaprMachineState *spapr) 192 { 193 MachineState *ms = MACHINE(spapr); 194 195 assert(spapr->vsmt); 196 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 197 } 198 199 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 200 int smt_threads) 201 { 202 int i, ret = 0; 203 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 204 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 205 int index = spapr_get_vcpu_id(cpu); 206 207 if (cpu->compat_pvr) { 208 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 209 if (ret < 0) { 210 return ret; 211 } 212 } 213 214 /* Build interrupt servers and gservers properties */ 215 for (i = 0; i < smt_threads; i++) { 216 servers_prop[i] = cpu_to_be32(index + i); 217 /* Hack, direct the group queues back to cpu 0 */ 218 gservers_prop[i*2] = cpu_to_be32(index + i); 219 gservers_prop[i*2 + 1] = 0; 220 } 221 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 222 servers_prop, sizeof(*servers_prop) * smt_threads); 223 if (ret < 0) { 224 return ret; 225 } 226 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 227 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 228 229 return ret; 230 } 231 232 static void spapr_dt_pa_features(SpaprMachineState *spapr, 233 PowerPCCPU *cpu, 234 void *fdt, int offset) 235 { 236 /* 237 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 238 * but not MTTCG, so disable it. To advertise it, a cap would have 239 * to be added, or support implemented for MTTCG. 240 * 241 * Copy/paste is not supported by TCG, so it is not advertised. KVM 242 * can execute them but it has no accelerator drivers which are usable, 243 * so there isn't much need for it anyway. 244 */ 245 246 uint8_t pa_features_206[] = { 6, 0, 247 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 248 uint8_t pa_features_207[] = { 24, 0, 249 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 250 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 251 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 252 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 253 uint8_t pa_features_300[] = { 66, 0, 254 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 255 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 256 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 257 /* 6: DS207 */ 258 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 259 /* 16: Vector */ 260 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 261 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 262 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 263 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 264 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 265 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 266 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 267 /* 36: SPR SO, 40: Radix MMU */ 268 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 269 /* 42: PM, 44: PC RA, 46: SC vec'd */ 270 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 271 /* 48: SIMD, 50: QP BFP, 52: String */ 272 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 273 /* 54: DecFP, 56: DecI, 58: SHA */ 274 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 275 /* 60: NM atomic, 62: RNG */ 276 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 277 }; 278 uint8_t *pa_features = NULL; 279 size_t pa_size; 280 281 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 282 pa_features = pa_features_206; 283 pa_size = sizeof(pa_features_206); 284 } 285 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 286 pa_features = pa_features_207; 287 pa_size = sizeof(pa_features_207); 288 } 289 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 290 pa_features = pa_features_300; 291 pa_size = sizeof(pa_features_300); 292 } 293 if (!pa_features) { 294 return; 295 } 296 297 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 298 /* 299 * Note: we keep CI large pages off by default because a 64K capable 300 * guest provisioned with large pages might otherwise try to map a qemu 301 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 302 * even if that qemu runs on a 4k host. 303 * We dd this bit back here if we are confident this is not an issue 304 */ 305 pa_features[3] |= 0x20; 306 } 307 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 308 pa_features[24] |= 0x80; /* Transactional memory support */ 309 } 310 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 311 /* Workaround for broken kernels that attempt (guest) radix 312 * mode when they can't handle it, if they see the radix bit set 313 * in pa-features. So hide it from them. */ 314 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 315 } 316 317 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 318 } 319 320 static hwaddr spapr_node0_size(MachineState *machine) 321 { 322 if (machine->numa_state->num_nodes) { 323 int i; 324 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 325 if (machine->numa_state->nodes[i].node_mem) { 326 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 327 machine->ram_size); 328 } 329 } 330 } 331 return machine->ram_size; 332 } 333 334 static void add_str(GString *s, const gchar *s1) 335 { 336 g_string_append_len(s, s1, strlen(s1) + 1); 337 } 338 339 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 340 hwaddr start, hwaddr size) 341 { 342 char mem_name[32]; 343 uint64_t mem_reg_property[2]; 344 int off; 345 346 mem_reg_property[0] = cpu_to_be64(start); 347 mem_reg_property[1] = cpu_to_be64(size); 348 349 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 350 off = fdt_add_subnode(fdt, 0, mem_name); 351 _FDT(off); 352 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 353 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 354 sizeof(mem_reg_property)))); 355 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 356 return off; 357 } 358 359 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 360 { 361 MemoryDeviceInfoList *info; 362 363 for (info = list; info; info = info->next) { 364 MemoryDeviceInfo *value = info->value; 365 366 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 367 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 368 369 if (addr >= pcdimm_info->addr && 370 addr < (pcdimm_info->addr + pcdimm_info->size)) { 371 return pcdimm_info->node; 372 } 373 } 374 } 375 376 return -1; 377 } 378 379 struct sPAPRDrconfCellV2 { 380 uint32_t seq_lmbs; 381 uint64_t base_addr; 382 uint32_t drc_index; 383 uint32_t aa_index; 384 uint32_t flags; 385 } QEMU_PACKED; 386 387 typedef struct DrconfCellQueue { 388 struct sPAPRDrconfCellV2 cell; 389 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 390 } DrconfCellQueue; 391 392 static DrconfCellQueue * 393 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 394 uint32_t drc_index, uint32_t aa_index, 395 uint32_t flags) 396 { 397 DrconfCellQueue *elem; 398 399 elem = g_malloc0(sizeof(*elem)); 400 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 401 elem->cell.base_addr = cpu_to_be64(base_addr); 402 elem->cell.drc_index = cpu_to_be32(drc_index); 403 elem->cell.aa_index = cpu_to_be32(aa_index); 404 elem->cell.flags = cpu_to_be32(flags); 405 406 return elem; 407 } 408 409 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 410 int offset, MemoryDeviceInfoList *dimms) 411 { 412 MachineState *machine = MACHINE(spapr); 413 uint8_t *int_buf, *cur_index; 414 int ret; 415 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 416 uint64_t addr, cur_addr, size; 417 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 418 uint64_t mem_end = machine->device_memory->base + 419 memory_region_size(&machine->device_memory->mr); 420 uint32_t node, buf_len, nr_entries = 0; 421 SpaprDrc *drc; 422 DrconfCellQueue *elem, *next; 423 MemoryDeviceInfoList *info; 424 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 425 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 426 427 /* Entry to cover RAM and the gap area */ 428 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 429 SPAPR_LMB_FLAGS_RESERVED | 430 SPAPR_LMB_FLAGS_DRC_INVALID); 431 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 432 nr_entries++; 433 434 cur_addr = machine->device_memory->base; 435 for (info = dimms; info; info = info->next) { 436 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 437 438 addr = di->addr; 439 size = di->size; 440 node = di->node; 441 442 /* 443 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 444 * area is marked hotpluggable in the next iteration for the bigger 445 * chunk including the NVDIMM occupied area. 446 */ 447 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 448 continue; 449 450 /* Entry for hot-pluggable area */ 451 if (cur_addr < addr) { 452 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 453 g_assert(drc); 454 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 455 cur_addr, spapr_drc_index(drc), -1, 0); 456 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 457 nr_entries++; 458 } 459 460 /* Entry for DIMM */ 461 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 462 g_assert(drc); 463 elem = spapr_get_drconf_cell(size / lmb_size, addr, 464 spapr_drc_index(drc), node, 465 (SPAPR_LMB_FLAGS_ASSIGNED | 466 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 467 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 468 nr_entries++; 469 cur_addr = addr + size; 470 } 471 472 /* Entry for remaining hotpluggable area */ 473 if (cur_addr < mem_end) { 474 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 475 g_assert(drc); 476 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 477 cur_addr, spapr_drc_index(drc), -1, 0); 478 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 479 nr_entries++; 480 } 481 482 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 483 int_buf = cur_index = g_malloc0(buf_len); 484 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 485 cur_index += sizeof(nr_entries); 486 487 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 488 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 489 cur_index += sizeof(elem->cell); 490 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 491 g_free(elem); 492 } 493 494 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 495 g_free(int_buf); 496 if (ret < 0) { 497 return -1; 498 } 499 return 0; 500 } 501 502 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 503 int offset, MemoryDeviceInfoList *dimms) 504 { 505 MachineState *machine = MACHINE(spapr); 506 int i, ret; 507 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 508 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 509 uint32_t nr_lmbs = (machine->device_memory->base + 510 memory_region_size(&machine->device_memory->mr)) / 511 lmb_size; 512 uint32_t *int_buf, *cur_index, buf_len; 513 514 /* 515 * Allocate enough buffer size to fit in ibm,dynamic-memory 516 */ 517 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 518 cur_index = int_buf = g_malloc0(buf_len); 519 int_buf[0] = cpu_to_be32(nr_lmbs); 520 cur_index++; 521 for (i = 0; i < nr_lmbs; i++) { 522 uint64_t addr = i * lmb_size; 523 uint32_t *dynamic_memory = cur_index; 524 525 if (i >= device_lmb_start) { 526 SpaprDrc *drc; 527 528 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 529 g_assert(drc); 530 531 dynamic_memory[0] = cpu_to_be32(addr >> 32); 532 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 533 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 534 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 535 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 536 if (memory_region_present(get_system_memory(), addr)) { 537 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 538 } else { 539 dynamic_memory[5] = cpu_to_be32(0); 540 } 541 } else { 542 /* 543 * LMB information for RMA, boot time RAM and gap b/n RAM and 544 * device memory region -- all these are marked as reserved 545 * and as having no valid DRC. 546 */ 547 dynamic_memory[0] = cpu_to_be32(addr >> 32); 548 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 549 dynamic_memory[2] = cpu_to_be32(0); 550 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 551 dynamic_memory[4] = cpu_to_be32(-1); 552 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 553 SPAPR_LMB_FLAGS_DRC_INVALID); 554 } 555 556 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 557 } 558 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 559 g_free(int_buf); 560 if (ret < 0) { 561 return -1; 562 } 563 return 0; 564 } 565 566 /* 567 * Adds ibm,dynamic-reconfiguration-memory node. 568 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 569 * of this device tree node. 570 */ 571 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 572 void *fdt) 573 { 574 MachineState *machine = MACHINE(spapr); 575 int ret, offset; 576 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 577 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 578 cpu_to_be32(lmb_size & 0xffffffff)}; 579 MemoryDeviceInfoList *dimms = NULL; 580 581 /* Don't create the node if there is no device memory. */ 582 if (!machine->device_memory) { 583 return 0; 584 } 585 586 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 587 588 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 589 sizeof(prop_lmb_size)); 590 if (ret < 0) { 591 return ret; 592 } 593 594 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 595 if (ret < 0) { 596 return ret; 597 } 598 599 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 600 if (ret < 0) { 601 return ret; 602 } 603 604 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 605 dimms = qmp_memory_device_list(); 606 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 607 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 608 } else { 609 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 610 } 611 qapi_free_MemoryDeviceInfoList(dimms); 612 613 if (ret < 0) { 614 return ret; 615 } 616 617 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 618 619 return ret; 620 } 621 622 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 623 { 624 MachineState *machine = MACHINE(spapr); 625 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 626 hwaddr mem_start, node_size; 627 int i, nb_nodes = machine->numa_state->num_nodes; 628 NodeInfo *nodes = machine->numa_state->nodes; 629 630 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 631 if (!nodes[i].node_mem) { 632 continue; 633 } 634 if (mem_start >= machine->ram_size) { 635 node_size = 0; 636 } else { 637 node_size = nodes[i].node_mem; 638 if (node_size > machine->ram_size - mem_start) { 639 node_size = machine->ram_size - mem_start; 640 } 641 } 642 if (!mem_start) { 643 /* spapr_machine_init() checks for rma_size <= node0_size 644 * already */ 645 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 646 mem_start += spapr->rma_size; 647 node_size -= spapr->rma_size; 648 } 649 for ( ; node_size; ) { 650 hwaddr sizetmp = pow2floor(node_size); 651 652 /* mem_start != 0 here */ 653 if (ctzl(mem_start) < ctzl(sizetmp)) { 654 sizetmp = 1ULL << ctzl(mem_start); 655 } 656 657 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 658 node_size -= sizetmp; 659 mem_start += sizetmp; 660 } 661 } 662 663 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 664 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 665 int ret; 666 667 g_assert(smc->dr_lmb_enabled); 668 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 669 if (ret) { 670 return ret; 671 } 672 } 673 674 return 0; 675 } 676 677 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 678 SpaprMachineState *spapr) 679 { 680 MachineState *ms = MACHINE(spapr); 681 PowerPCCPU *cpu = POWERPC_CPU(cs); 682 CPUPPCState *env = &cpu->env; 683 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 684 int index = spapr_get_vcpu_id(cpu); 685 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 686 0xffffffff, 0xffffffff}; 687 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 688 : SPAPR_TIMEBASE_FREQ; 689 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 690 uint32_t page_sizes_prop[64]; 691 size_t page_sizes_prop_size; 692 unsigned int smp_threads = ms->smp.threads; 693 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 694 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 695 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 696 SpaprDrc *drc; 697 int drc_index; 698 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 699 int i; 700 701 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 702 if (drc) { 703 drc_index = spapr_drc_index(drc); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 705 } 706 707 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 708 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 709 710 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 711 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 712 env->dcache_line_size))); 713 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 714 env->dcache_line_size))); 715 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 716 env->icache_line_size))); 717 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 718 env->icache_line_size))); 719 720 if (pcc->l1_dcache_size) { 721 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 722 pcc->l1_dcache_size))); 723 } else { 724 warn_report("Unknown L1 dcache size for cpu"); 725 } 726 if (pcc->l1_icache_size) { 727 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 728 pcc->l1_icache_size))); 729 } else { 730 warn_report("Unknown L1 icache size for cpu"); 731 } 732 733 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 734 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 735 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 736 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 737 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 738 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 739 740 if (ppc_has_spr(cpu, SPR_PURR)) { 741 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 742 } 743 if (ppc_has_spr(cpu, SPR_PURR)) { 744 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 745 } 746 747 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 748 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 749 segs, sizeof(segs)))); 750 } 751 752 /* Advertise VSX (vector extensions) if available 753 * 1 == VMX / Altivec available 754 * 2 == VSX available 755 * 756 * Only CPUs for which we create core types in spapr_cpu_core.c 757 * are possible, and all of those have VMX */ 758 if (env->insns_flags & PPC_ALTIVEC) { 759 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 760 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 761 } else { 762 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 763 } 764 } 765 766 /* Advertise DFP (Decimal Floating Point) if available 767 * 0 / no property == no DFP 768 * 1 == DFP available */ 769 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 770 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 771 } 772 773 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 774 sizeof(page_sizes_prop)); 775 if (page_sizes_prop_size) { 776 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 777 page_sizes_prop, page_sizes_prop_size))); 778 } 779 780 spapr_dt_pa_features(spapr, cpu, fdt, offset); 781 782 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 783 cs->cpu_index / vcpus_per_socket))); 784 785 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 786 pft_size_prop, sizeof(pft_size_prop)))); 787 788 if (ms->numa_state->num_nodes > 1) { 789 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 790 } 791 792 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 793 794 if (pcc->radix_page_info) { 795 for (i = 0; i < pcc->radix_page_info->count; i++) { 796 radix_AP_encodings[i] = 797 cpu_to_be32(pcc->radix_page_info->entries[i]); 798 } 799 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 800 radix_AP_encodings, 801 pcc->radix_page_info->count * 802 sizeof(radix_AP_encodings[0])))); 803 } 804 805 /* 806 * We set this property to let the guest know that it can use the large 807 * decrementer and its width in bits. 808 */ 809 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 810 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 811 pcc->lrg_decr_bits))); 812 } 813 814 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 815 int cpus_offset) 816 { 817 PowerPCCPU *cpu = POWERPC_CPU(cs); 818 int index = spapr_get_vcpu_id(cpu); 819 DeviceClass *dc = DEVICE_GET_CLASS(cs); 820 g_autofree char *nodename = NULL; 821 int offset; 822 823 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 824 return; 825 } 826 827 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 828 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 829 _FDT(offset); 830 spapr_dt_cpu(cs, fdt, offset, spapr); 831 } 832 833 834 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 835 { 836 CPUState **rev; 837 CPUState *cs; 838 int n_cpus; 839 int cpus_offset; 840 int i; 841 842 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 843 _FDT(cpus_offset); 844 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 845 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 846 847 /* 848 * We walk the CPUs in reverse order to ensure that CPU DT nodes 849 * created by fdt_add_subnode() end up in the right order in FDT 850 * for the guest kernel the enumerate the CPUs correctly. 851 * 852 * The CPU list cannot be traversed in reverse order, so we need 853 * to do extra work. 854 */ 855 n_cpus = 0; 856 rev = NULL; 857 CPU_FOREACH(cs) { 858 rev = g_renew(CPUState *, rev, n_cpus + 1); 859 rev[n_cpus++] = cs; 860 } 861 862 for (i = n_cpus - 1; i >= 0; i--) { 863 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 864 } 865 866 g_free(rev); 867 } 868 869 static int spapr_dt_rng(void *fdt) 870 { 871 int node; 872 int ret; 873 874 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 875 if (node <= 0) { 876 return -1; 877 } 878 ret = fdt_setprop_string(fdt, node, "device_type", 879 "ibm,platform-facilities"); 880 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 881 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 882 883 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 884 if (node <= 0) { 885 return -1; 886 } 887 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 888 889 return ret ? -1 : 0; 890 } 891 892 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 893 { 894 MachineState *ms = MACHINE(spapr); 895 int rtas; 896 GString *hypertas = g_string_sized_new(256); 897 GString *qemu_hypertas = g_string_sized_new(256); 898 uint32_t lrdr_capacity[] = { 899 0, 900 0, 901 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 902 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 903 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 904 }; 905 906 /* Do we have device memory? */ 907 if (MACHINE(spapr)->device_memory) { 908 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 909 memory_region_size(&MACHINE(spapr)->device_memory->mr); 910 911 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 912 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 913 } 914 915 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 916 917 /* hypertas */ 918 add_str(hypertas, "hcall-pft"); 919 add_str(hypertas, "hcall-term"); 920 add_str(hypertas, "hcall-dabr"); 921 add_str(hypertas, "hcall-interrupt"); 922 add_str(hypertas, "hcall-tce"); 923 add_str(hypertas, "hcall-vio"); 924 add_str(hypertas, "hcall-splpar"); 925 add_str(hypertas, "hcall-join"); 926 add_str(hypertas, "hcall-bulk"); 927 add_str(hypertas, "hcall-set-mode"); 928 add_str(hypertas, "hcall-sprg0"); 929 add_str(hypertas, "hcall-copy"); 930 add_str(hypertas, "hcall-debug"); 931 add_str(hypertas, "hcall-vphn"); 932 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 933 add_str(hypertas, "hcall-rpt-invalidate"); 934 } 935 936 add_str(qemu_hypertas, "hcall-memop1"); 937 938 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 939 add_str(hypertas, "hcall-multi-tce"); 940 } 941 942 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 943 add_str(hypertas, "hcall-hpt-resize"); 944 } 945 946 add_str(hypertas, "hcall-watchdog"); 947 948 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 949 hypertas->str, hypertas->len)); 950 g_string_free(hypertas, TRUE); 951 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 952 qemu_hypertas->str, qemu_hypertas->len)); 953 g_string_free(qemu_hypertas, TRUE); 954 955 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 956 957 /* 958 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 959 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 960 * 961 * The system reset requirements are driven by existing Linux and PowerVM 962 * implementation which (contrary to PAPR) saves r3 in the error log 963 * structure like machine check, so Linux expects to find the saved r3 964 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 965 * does not look at the error value). 966 * 967 * System reset interrupts are not subject to interlock like machine 968 * check, so this memory area could be corrupted if the sreset is 969 * interrupted by a machine check (or vice versa) if it was shared. To 970 * prevent this, system reset uses per-CPU areas for the sreset save 971 * area. A system reset that interrupts a system reset handler could 972 * still overwrite this area, but Linux doesn't try to recover in that 973 * case anyway. 974 * 975 * The extra 8 bytes is required because Linux's FWNMI error log check 976 * is off-by-one. 977 * 978 * RTAS_MIN_SIZE is required for the RTAS blob itself. 979 */ 980 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 981 RTAS_ERROR_LOG_MAX + 982 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 983 sizeof(uint64_t))); 984 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 985 RTAS_ERROR_LOG_MAX)); 986 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 987 RTAS_EVENT_SCAN_RATE)); 988 989 g_assert(msi_nonbroken); 990 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 991 992 /* 993 * According to PAPR, rtas ibm,os-term does not guarantee a return 994 * back to the guest cpu. 995 * 996 * While an additional ibm,extended-os-term property indicates 997 * that rtas call return will always occur. Set this property. 998 */ 999 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1000 1001 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1002 lrdr_capacity, sizeof(lrdr_capacity))); 1003 1004 spapr_dt_rtas_tokens(fdt, rtas); 1005 } 1006 1007 /* 1008 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1009 * and the XIVE features that the guest may request and thus the valid 1010 * values for bytes 23..26 of option vector 5: 1011 */ 1012 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1013 int chosen) 1014 { 1015 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1016 1017 char val[2 * 4] = { 1018 23, 0x00, /* XICS / XIVE mode */ 1019 24, 0x00, /* Hash/Radix, filled in below. */ 1020 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1021 26, 0x40, /* Radix options: GTSE == yes. */ 1022 }; 1023 1024 if (spapr->irq->xics && spapr->irq->xive) { 1025 val[1] = SPAPR_OV5_XIVE_BOTH; 1026 } else if (spapr->irq->xive) { 1027 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1028 } else { 1029 assert(spapr->irq->xics); 1030 val[1] = SPAPR_OV5_XIVE_LEGACY; 1031 } 1032 1033 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1034 first_ppc_cpu->compat_pvr)) { 1035 /* 1036 * If we're in a pre POWER9 compat mode then the guest should 1037 * do hash and use the legacy interrupt mode 1038 */ 1039 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1040 val[3] = 0x00; /* Hash */ 1041 spapr_check_mmu_mode(false); 1042 } else if (kvm_enabled()) { 1043 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1044 val[3] = 0x80; /* OV5_MMU_BOTH */ 1045 } else if (kvmppc_has_cap_mmu_radix()) { 1046 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1047 } else { 1048 val[3] = 0x00; /* Hash */ 1049 } 1050 } else { 1051 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1052 val[3] = 0xC0; 1053 } 1054 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1055 val, sizeof(val))); 1056 } 1057 1058 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1059 { 1060 MachineState *machine = MACHINE(spapr); 1061 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1062 int chosen; 1063 1064 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1065 1066 if (reset) { 1067 const char *boot_device = spapr->boot_device; 1068 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1069 size_t cb = 0; 1070 g_autofree char *bootlist = get_boot_devices_list(&cb); 1071 1072 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1073 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1074 machine->kernel_cmdline)); 1075 } 1076 1077 if (spapr->initrd_size) { 1078 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1079 spapr->initrd_base)); 1080 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1081 spapr->initrd_base + spapr->initrd_size)); 1082 } 1083 1084 if (spapr->kernel_size) { 1085 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1086 cpu_to_be64(spapr->kernel_size) }; 1087 1088 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1089 &kprop, sizeof(kprop))); 1090 if (spapr->kernel_le) { 1091 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1092 } 1093 } 1094 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1095 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1096 } 1097 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1098 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1099 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1100 1101 if (cb && bootlist) { 1102 int i; 1103 1104 for (i = 0; i < cb; i++) { 1105 if (bootlist[i] == '\n') { 1106 bootlist[i] = ' '; 1107 } 1108 } 1109 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1110 } 1111 1112 if (boot_device && strlen(boot_device)) { 1113 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1114 } 1115 1116 if (spapr->want_stdout_path && stdout_path) { 1117 /* 1118 * "linux,stdout-path" and "stdout" properties are 1119 * deprecated by linux kernel. New platforms should only 1120 * use the "stdout-path" property. Set the new property 1121 * and continue using older property to remain compatible 1122 * with the existing firmware. 1123 */ 1124 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1125 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1126 } 1127 1128 /* 1129 * We can deal with BAR reallocation just fine, advertise it 1130 * to the guest 1131 */ 1132 if (smc->linux_pci_probe) { 1133 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1134 } 1135 1136 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1137 } 1138 1139 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1140 1141 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1142 } 1143 1144 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1145 { 1146 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1147 * KVM to work under pHyp with some guest co-operation */ 1148 int hypervisor; 1149 uint8_t hypercall[16]; 1150 1151 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1152 /* indicate KVM hypercall interface */ 1153 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1154 if (kvmppc_has_cap_fixup_hcalls()) { 1155 /* 1156 * Older KVM versions with older guest kernels were broken 1157 * with the magic page, don't allow the guest to map it. 1158 */ 1159 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1160 sizeof(hypercall))) { 1161 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1162 hypercall, sizeof(hypercall))); 1163 } 1164 } 1165 } 1166 1167 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1168 { 1169 MachineState *machine = MACHINE(spapr); 1170 MachineClass *mc = MACHINE_GET_CLASS(machine); 1171 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1172 uint32_t root_drc_type_mask = 0; 1173 int ret; 1174 void *fdt; 1175 SpaprPhbState *phb; 1176 char *buf; 1177 1178 fdt = g_malloc0(space); 1179 _FDT((fdt_create_empty_tree(fdt, space))); 1180 1181 /* Root node */ 1182 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1183 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1184 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1185 1186 /* Guest UUID & Name*/ 1187 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1188 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1189 if (qemu_uuid_set) { 1190 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1191 } 1192 g_free(buf); 1193 1194 if (qemu_get_vm_name()) { 1195 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1196 qemu_get_vm_name())); 1197 } 1198 1199 /* Host Model & Serial Number */ 1200 if (spapr->host_model) { 1201 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1202 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1203 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1204 g_free(buf); 1205 } 1206 1207 if (spapr->host_serial) { 1208 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1209 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1210 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1211 g_free(buf); 1212 } 1213 1214 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1215 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1216 1217 /* /interrupt controller */ 1218 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1219 1220 ret = spapr_dt_memory(spapr, fdt); 1221 if (ret < 0) { 1222 error_report("couldn't setup memory nodes in fdt"); 1223 exit(1); 1224 } 1225 1226 /* /vdevice */ 1227 spapr_dt_vdevice(spapr->vio_bus, fdt); 1228 1229 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1230 ret = spapr_dt_rng(fdt); 1231 if (ret < 0) { 1232 error_report("could not set up rng device in the fdt"); 1233 exit(1); 1234 } 1235 } 1236 1237 QLIST_FOREACH(phb, &spapr->phbs, list) { 1238 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1239 if (ret < 0) { 1240 error_report("couldn't setup PCI devices in fdt"); 1241 exit(1); 1242 } 1243 } 1244 1245 spapr_dt_cpus(fdt, spapr); 1246 1247 /* ibm,drc-indexes and friends */ 1248 if (smc->dr_lmb_enabled) { 1249 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1250 } 1251 if (smc->dr_phb_enabled) { 1252 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1253 } 1254 if (mc->nvdimm_supported) { 1255 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1256 } 1257 if (root_drc_type_mask) { 1258 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1259 } 1260 1261 if (mc->has_hotpluggable_cpus) { 1262 int offset = fdt_path_offset(fdt, "/cpus"); 1263 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1264 if (ret < 0) { 1265 error_report("Couldn't set up CPU DR device tree properties"); 1266 exit(1); 1267 } 1268 } 1269 1270 /* /event-sources */ 1271 spapr_dt_events(spapr, fdt); 1272 1273 /* /rtas */ 1274 spapr_dt_rtas(spapr, fdt); 1275 1276 /* /chosen */ 1277 spapr_dt_chosen(spapr, fdt, reset); 1278 1279 /* /hypervisor */ 1280 if (kvm_enabled()) { 1281 spapr_dt_hypervisor(spapr, fdt); 1282 } 1283 1284 /* Build memory reserve map */ 1285 if (reset) { 1286 if (spapr->kernel_size) { 1287 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1288 spapr->kernel_size))); 1289 } 1290 if (spapr->initrd_size) { 1291 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1292 spapr->initrd_size))); 1293 } 1294 } 1295 1296 /* NVDIMM devices */ 1297 if (mc->nvdimm_supported) { 1298 spapr_dt_persistent_memory(spapr, fdt); 1299 } 1300 1301 return fdt; 1302 } 1303 1304 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1305 { 1306 SpaprMachineState *spapr = opaque; 1307 1308 return (addr & 0x0fffffff) + spapr->kernel_addr; 1309 } 1310 1311 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1312 PowerPCCPU *cpu) 1313 { 1314 CPUPPCState *env = &cpu->env; 1315 1316 /* The TCG path should also be holding the BQL at this point */ 1317 g_assert(bql_locked()); 1318 1319 g_assert(!vhyp_cpu_in_nested(cpu)); 1320 1321 if (FIELD_EX64(env->msr, MSR, PR)) { 1322 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1323 env->gpr[3] = H_PRIVILEGE; 1324 } else { 1325 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1326 } 1327 } 1328 1329 struct LPCRSyncState { 1330 target_ulong value; 1331 target_ulong mask; 1332 }; 1333 1334 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1335 { 1336 struct LPCRSyncState *s = arg.host_ptr; 1337 PowerPCCPU *cpu = POWERPC_CPU(cs); 1338 CPUPPCState *env = &cpu->env; 1339 target_ulong lpcr; 1340 1341 cpu_synchronize_state(cs); 1342 lpcr = env->spr[SPR_LPCR]; 1343 lpcr &= ~s->mask; 1344 lpcr |= s->value; 1345 ppc_store_lpcr(cpu, lpcr); 1346 } 1347 1348 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1349 { 1350 CPUState *cs; 1351 struct LPCRSyncState s = { 1352 .value = value, 1353 .mask = mask 1354 }; 1355 CPU_FOREACH(cs) { 1356 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1357 } 1358 } 1359 1360 /* May be used when the machine is not running */ 1361 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1362 { 1363 CPUState *cs; 1364 CPU_FOREACH(cs) { 1365 PowerPCCPU *cpu = POWERPC_CPU(cs); 1366 CPUPPCState *env = &cpu->env; 1367 target_ulong lpcr; 1368 1369 lpcr = env->spr[SPR_LPCR]; 1370 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1371 ppc_store_lpcr(cpu, lpcr); 1372 } 1373 } 1374 1375 1376 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1377 target_ulong lpid, ppc_v3_pate_t *entry) 1378 { 1379 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1380 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1381 1382 if (!spapr_cpu->in_nested) { 1383 assert(lpid == 0); 1384 1385 /* Copy PATE1:GR into PATE0:HR */ 1386 entry->dw0 = spapr->patb_entry & PATE0_HR; 1387 entry->dw1 = spapr->patb_entry; 1388 1389 } else { 1390 uint64_t patb, pats; 1391 1392 assert(lpid != 0); 1393 1394 patb = spapr->nested_ptcr & PTCR_PATB; 1395 pats = spapr->nested_ptcr & PTCR_PATS; 1396 1397 /* Check if partition table is properly aligned */ 1398 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 1399 return false; 1400 } 1401 1402 /* Calculate number of entries */ 1403 pats = 1ull << (pats + 12 - 4); 1404 if (pats <= lpid) { 1405 return false; 1406 } 1407 1408 /* Grab entry */ 1409 patb += 16 * lpid; 1410 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1411 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1412 } 1413 1414 return true; 1415 } 1416 1417 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1418 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1419 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1420 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1421 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1422 1423 /* 1424 * Get the fd to access the kernel htab, re-opening it if necessary 1425 */ 1426 static int get_htab_fd(SpaprMachineState *spapr) 1427 { 1428 Error *local_err = NULL; 1429 1430 if (spapr->htab_fd >= 0) { 1431 return spapr->htab_fd; 1432 } 1433 1434 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1435 if (spapr->htab_fd < 0) { 1436 error_report_err(local_err); 1437 } 1438 1439 return spapr->htab_fd; 1440 } 1441 1442 void close_htab_fd(SpaprMachineState *spapr) 1443 { 1444 if (spapr->htab_fd >= 0) { 1445 close(spapr->htab_fd); 1446 } 1447 spapr->htab_fd = -1; 1448 } 1449 1450 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1451 { 1452 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1453 1454 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1455 } 1456 1457 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1458 { 1459 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1460 1461 assert(kvm_enabled()); 1462 1463 if (!spapr->htab) { 1464 return 0; 1465 } 1466 1467 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1468 } 1469 1470 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1471 hwaddr ptex, int n) 1472 { 1473 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1474 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1475 1476 if (!spapr->htab) { 1477 /* 1478 * HTAB is controlled by KVM. Fetch into temporary buffer 1479 */ 1480 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1481 kvmppc_read_hptes(hptes, ptex, n); 1482 return hptes; 1483 } 1484 1485 /* 1486 * HTAB is controlled by QEMU. Just point to the internally 1487 * accessible PTEG. 1488 */ 1489 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1490 } 1491 1492 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1493 const ppc_hash_pte64_t *hptes, 1494 hwaddr ptex, int n) 1495 { 1496 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1497 1498 if (!spapr->htab) { 1499 g_free((void *)hptes); 1500 } 1501 1502 /* Nothing to do for qemu managed HPT */ 1503 } 1504 1505 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1506 uint64_t pte0, uint64_t pte1) 1507 { 1508 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1509 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1510 1511 if (!spapr->htab) { 1512 kvmppc_write_hpte(ptex, pte0, pte1); 1513 } else { 1514 if (pte0 & HPTE64_V_VALID) { 1515 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1516 /* 1517 * When setting valid, we write PTE1 first. This ensures 1518 * proper synchronization with the reading code in 1519 * ppc_hash64_pteg_search() 1520 */ 1521 smp_wmb(); 1522 stq_p(spapr->htab + offset, pte0); 1523 } else { 1524 stq_p(spapr->htab + offset, pte0); 1525 /* 1526 * When clearing it we set PTE0 first. This ensures proper 1527 * synchronization with the reading code in 1528 * ppc_hash64_pteg_search() 1529 */ 1530 smp_wmb(); 1531 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1532 } 1533 } 1534 } 1535 1536 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1537 uint64_t pte1) 1538 { 1539 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1540 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1541 1542 if (!spapr->htab) { 1543 /* There should always be a hash table when this is called */ 1544 error_report("spapr_hpte_set_c called with no hash table !"); 1545 return; 1546 } 1547 1548 /* The HW performs a non-atomic byte update */ 1549 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1550 } 1551 1552 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1553 uint64_t pte1) 1554 { 1555 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1556 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1557 1558 if (!spapr->htab) { 1559 /* There should always be a hash table when this is called */ 1560 error_report("spapr_hpte_set_r called with no hash table !"); 1561 return; 1562 } 1563 1564 /* The HW performs a non-atomic byte update */ 1565 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1566 } 1567 1568 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1569 { 1570 int shift; 1571 1572 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1573 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1574 * that's much more than is needed for Linux guests */ 1575 shift = ctz64(pow2ceil(ramsize)) - 7; 1576 shift = MAX(shift, 18); /* Minimum architected size */ 1577 shift = MIN(shift, 46); /* Maximum architected size */ 1578 return shift; 1579 } 1580 1581 void spapr_free_hpt(SpaprMachineState *spapr) 1582 { 1583 qemu_vfree(spapr->htab); 1584 spapr->htab = NULL; 1585 spapr->htab_shift = 0; 1586 close_htab_fd(spapr); 1587 } 1588 1589 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1590 { 1591 ERRP_GUARD(); 1592 long rc; 1593 1594 /* Clean up any HPT info from a previous boot */ 1595 spapr_free_hpt(spapr); 1596 1597 rc = kvmppc_reset_htab(shift); 1598 1599 if (rc == -EOPNOTSUPP) { 1600 error_setg(errp, "HPT not supported in nested guests"); 1601 return -EOPNOTSUPP; 1602 } 1603 1604 if (rc < 0) { 1605 /* kernel-side HPT needed, but couldn't allocate one */ 1606 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1607 shift); 1608 error_append_hint(errp, "Try smaller maxmem?\n"); 1609 return -errno; 1610 } else if (rc > 0) { 1611 /* kernel-side HPT allocated */ 1612 if (rc != shift) { 1613 error_setg(errp, 1614 "Requested order %d HPT, but kernel allocated order %ld", 1615 shift, rc); 1616 error_append_hint(errp, "Try smaller maxmem?\n"); 1617 return -ENOSPC; 1618 } 1619 1620 spapr->htab_shift = shift; 1621 spapr->htab = NULL; 1622 } else { 1623 /* kernel-side HPT not needed, allocate in userspace instead */ 1624 size_t size = 1ULL << shift; 1625 int i; 1626 1627 spapr->htab = qemu_memalign(size, size); 1628 memset(spapr->htab, 0, size); 1629 spapr->htab_shift = shift; 1630 1631 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1632 DIRTY_HPTE(HPTE(spapr->htab, i)); 1633 } 1634 } 1635 /* We're setting up a hash table, so that means we're not radix */ 1636 spapr->patb_entry = 0; 1637 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1638 return 0; 1639 } 1640 1641 void spapr_setup_hpt(SpaprMachineState *spapr) 1642 { 1643 int hpt_shift; 1644 1645 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1646 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1647 } else { 1648 uint64_t current_ram_size; 1649 1650 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1651 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1652 } 1653 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1654 1655 if (kvm_enabled()) { 1656 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1657 1658 /* Check our RMA fits in the possible VRMA */ 1659 if (vrma_limit < spapr->rma_size) { 1660 error_report("Unable to create %" HWADDR_PRIu 1661 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1662 spapr->rma_size / MiB, vrma_limit / MiB); 1663 exit(EXIT_FAILURE); 1664 } 1665 } 1666 } 1667 1668 void spapr_check_mmu_mode(bool guest_radix) 1669 { 1670 if (guest_radix) { 1671 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1672 error_report("Guest requested unavailable MMU mode (radix)."); 1673 exit(EXIT_FAILURE); 1674 } 1675 } else { 1676 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1677 && !kvmppc_has_cap_mmu_hash_v3()) { 1678 error_report("Guest requested unavailable MMU mode (hash)."); 1679 exit(EXIT_FAILURE); 1680 } 1681 } 1682 } 1683 1684 static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) 1685 { 1686 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1687 PowerPCCPU *first_ppc_cpu; 1688 hwaddr fdt_addr; 1689 void *fdt; 1690 int rc; 1691 1692 if (reason != SHUTDOWN_CAUSE_SNAPSHOT_LOAD) { 1693 /* 1694 * Record-replay snapshot load must not consume random, this was 1695 * already replayed from initial machine reset. 1696 */ 1697 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1698 } 1699 1700 pef_kvm_reset(machine->cgs, &error_fatal); 1701 spapr_caps_apply(spapr); 1702 1703 first_ppc_cpu = POWERPC_CPU(first_cpu); 1704 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1705 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1706 spapr->max_compat_pvr)) { 1707 /* 1708 * If using KVM with radix mode available, VCPUs can be started 1709 * without a HPT because KVM will start them in radix mode. 1710 * Set the GR bit in PATE so that we know there is no HPT. 1711 */ 1712 spapr->patb_entry = PATE1_GR; 1713 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1714 } else { 1715 spapr_setup_hpt(spapr); 1716 } 1717 1718 qemu_devices_reset(reason); 1719 1720 spapr_ovec_cleanup(spapr->ov5_cas); 1721 spapr->ov5_cas = spapr_ovec_new(); 1722 1723 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1724 1725 /* 1726 * This is fixing some of the default configuration of the XIVE 1727 * devices. To be called after the reset of the machine devices. 1728 */ 1729 spapr_irq_reset(spapr, &error_fatal); 1730 1731 /* 1732 * There is no CAS under qtest. Simulate one to please the code that 1733 * depends on spapr->ov5_cas. This is especially needed to test device 1734 * unplug, so we do that before resetting the DRCs. 1735 */ 1736 if (qtest_enabled()) { 1737 spapr_ovec_cleanup(spapr->ov5_cas); 1738 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1739 } 1740 1741 spapr_nvdimm_finish_flushes(); 1742 1743 /* DRC reset may cause a device to be unplugged. This will cause troubles 1744 * if this device is used by another device (eg, a running vhost backend 1745 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1746 * situations, we reset DRCs after all devices have been reset. 1747 */ 1748 spapr_drc_reset_all(spapr); 1749 1750 spapr_clear_pending_events(spapr); 1751 1752 /* 1753 * We place the device tree just below either the top of the RMA, 1754 * or just below 2GB, whichever is lower, so that it can be 1755 * processed with 32-bit real mode code if necessary 1756 */ 1757 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1758 1759 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1760 if (spapr->vof) { 1761 spapr_vof_reset(spapr, fdt, &error_fatal); 1762 /* 1763 * Do not pack the FDT as the client may change properties. 1764 * VOF client does not expect the FDT so we do not load it to the VM. 1765 */ 1766 } else { 1767 rc = fdt_pack(fdt); 1768 /* Should only fail if we've built a corrupted tree */ 1769 assert(rc == 0); 1770 1771 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1772 0, fdt_addr, 0); 1773 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1774 } 1775 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1776 1777 g_free(spapr->fdt_blob); 1778 spapr->fdt_size = fdt_totalsize(fdt); 1779 spapr->fdt_initial_size = spapr->fdt_size; 1780 spapr->fdt_blob = fdt; 1781 1782 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1783 machine->fdt = fdt; 1784 1785 /* Set up the entry state */ 1786 first_ppc_cpu->env.gpr[5] = 0; 1787 1788 spapr->fwnmi_system_reset_addr = -1; 1789 spapr->fwnmi_machine_check_addr = -1; 1790 spapr->fwnmi_machine_check_interlock = -1; 1791 1792 /* Signal all vCPUs waiting on this condition */ 1793 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1794 1795 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1796 } 1797 1798 static void spapr_create_nvram(SpaprMachineState *spapr) 1799 { 1800 DeviceState *dev = qdev_new("spapr-nvram"); 1801 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1802 1803 if (dinfo) { 1804 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1805 &error_fatal); 1806 } 1807 1808 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1809 1810 spapr->nvram = (struct SpaprNvram *)dev; 1811 } 1812 1813 static void spapr_rtc_create(SpaprMachineState *spapr) 1814 { 1815 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1816 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1817 &error_fatal, NULL); 1818 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1819 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1820 "date"); 1821 } 1822 1823 /* Returns whether we want to use VGA or not */ 1824 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1825 { 1826 vga_interface_created = true; 1827 switch (vga_interface_type) { 1828 case VGA_NONE: 1829 return false; 1830 case VGA_DEVICE: 1831 return true; 1832 case VGA_STD: 1833 case VGA_VIRTIO: 1834 case VGA_CIRRUS: 1835 return pci_vga_init(pci_bus) != NULL; 1836 default: 1837 error_setg(errp, 1838 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1839 return false; 1840 } 1841 } 1842 1843 static int spapr_pre_load(void *opaque) 1844 { 1845 int rc; 1846 1847 rc = spapr_caps_pre_load(opaque); 1848 if (rc) { 1849 return rc; 1850 } 1851 1852 return 0; 1853 } 1854 1855 static int spapr_post_load(void *opaque, int version_id) 1856 { 1857 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1858 int err = 0; 1859 1860 err = spapr_caps_post_migration(spapr); 1861 if (err) { 1862 return err; 1863 } 1864 1865 /* 1866 * In earlier versions, there was no separate qdev for the PAPR 1867 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1868 * So when migrating from those versions, poke the incoming offset 1869 * value into the RTC device 1870 */ 1871 if (version_id < 3) { 1872 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1873 if (err) { 1874 return err; 1875 } 1876 } 1877 1878 if (kvm_enabled() && spapr->patb_entry) { 1879 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1880 bool radix = !!(spapr->patb_entry & PATE1_GR); 1881 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1882 1883 /* 1884 * Update LPCR:HR and UPRT as they may not be set properly in 1885 * the stream 1886 */ 1887 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1888 LPCR_HR | LPCR_UPRT); 1889 1890 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1891 if (err) { 1892 error_report("Process table config unsupported by the host"); 1893 return -EINVAL; 1894 } 1895 } 1896 1897 err = spapr_irq_post_load(spapr, version_id); 1898 if (err) { 1899 return err; 1900 } 1901 1902 return err; 1903 } 1904 1905 static int spapr_pre_save(void *opaque) 1906 { 1907 int rc; 1908 1909 rc = spapr_caps_pre_save(opaque); 1910 if (rc) { 1911 return rc; 1912 } 1913 1914 return 0; 1915 } 1916 1917 static bool version_before_3(void *opaque, int version_id) 1918 { 1919 return version_id < 3; 1920 } 1921 1922 static bool spapr_pending_events_needed(void *opaque) 1923 { 1924 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1925 return !QTAILQ_EMPTY(&spapr->pending_events); 1926 } 1927 1928 static const VMStateDescription vmstate_spapr_event_entry = { 1929 .name = "spapr_event_log_entry", 1930 .version_id = 1, 1931 .minimum_version_id = 1, 1932 .fields = (const VMStateField[]) { 1933 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1934 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1935 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1936 NULL, extended_length), 1937 VMSTATE_END_OF_LIST() 1938 }, 1939 }; 1940 1941 static const VMStateDescription vmstate_spapr_pending_events = { 1942 .name = "spapr_pending_events", 1943 .version_id = 1, 1944 .minimum_version_id = 1, 1945 .needed = spapr_pending_events_needed, 1946 .fields = (const VMStateField[]) { 1947 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1948 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1949 VMSTATE_END_OF_LIST() 1950 }, 1951 }; 1952 1953 static bool spapr_ov5_cas_needed(void *opaque) 1954 { 1955 SpaprMachineState *spapr = opaque; 1956 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1957 bool cas_needed; 1958 1959 /* Prior to the introduction of SpaprOptionVector, we had two option 1960 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1961 * Both of these options encode machine topology into the device-tree 1962 * in such a way that the now-booted OS should still be able to interact 1963 * appropriately with QEMU regardless of what options were actually 1964 * negotiatied on the source side. 1965 * 1966 * As such, we can avoid migrating the CAS-negotiated options if these 1967 * are the only options available on the current machine/platform. 1968 * Since these are the only options available for pseries-2.7 and 1969 * earlier, this allows us to maintain old->new/new->old migration 1970 * compatibility. 1971 * 1972 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1973 * via default pseries-2.8 machines and explicit command-line parameters. 1974 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1975 * of the actual CAS-negotiated values to continue working properly. For 1976 * example, availability of memory unplug depends on knowing whether 1977 * OV5_HP_EVT was negotiated via CAS. 1978 * 1979 * Thus, for any cases where the set of available CAS-negotiatable 1980 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1981 * include the CAS-negotiated options in the migration stream, unless 1982 * if they affect boot time behaviour only. 1983 */ 1984 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1985 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1986 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1987 1988 /* We need extra information if we have any bits outside the mask 1989 * defined above */ 1990 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1991 1992 spapr_ovec_cleanup(ov5_mask); 1993 1994 return cas_needed; 1995 } 1996 1997 static const VMStateDescription vmstate_spapr_ov5_cas = { 1998 .name = "spapr_option_vector_ov5_cas", 1999 .version_id = 1, 2000 .minimum_version_id = 1, 2001 .needed = spapr_ov5_cas_needed, 2002 .fields = (const VMStateField[]) { 2003 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 2004 vmstate_spapr_ovec, SpaprOptionVector), 2005 VMSTATE_END_OF_LIST() 2006 }, 2007 }; 2008 2009 static bool spapr_patb_entry_needed(void *opaque) 2010 { 2011 SpaprMachineState *spapr = opaque; 2012 2013 return !!spapr->patb_entry; 2014 } 2015 2016 static const VMStateDescription vmstate_spapr_patb_entry = { 2017 .name = "spapr_patb_entry", 2018 .version_id = 1, 2019 .minimum_version_id = 1, 2020 .needed = spapr_patb_entry_needed, 2021 .fields = (const VMStateField[]) { 2022 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2023 VMSTATE_END_OF_LIST() 2024 }, 2025 }; 2026 2027 static bool spapr_irq_map_needed(void *opaque) 2028 { 2029 SpaprMachineState *spapr = opaque; 2030 2031 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2032 } 2033 2034 static const VMStateDescription vmstate_spapr_irq_map = { 2035 .name = "spapr_irq_map", 2036 .version_id = 1, 2037 .minimum_version_id = 1, 2038 .needed = spapr_irq_map_needed, 2039 .fields = (const VMStateField[]) { 2040 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2041 VMSTATE_END_OF_LIST() 2042 }, 2043 }; 2044 2045 static bool spapr_dtb_needed(void *opaque) 2046 { 2047 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2048 2049 return smc->update_dt_enabled; 2050 } 2051 2052 static int spapr_dtb_pre_load(void *opaque) 2053 { 2054 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2055 2056 g_free(spapr->fdt_blob); 2057 spapr->fdt_blob = NULL; 2058 spapr->fdt_size = 0; 2059 2060 return 0; 2061 } 2062 2063 static const VMStateDescription vmstate_spapr_dtb = { 2064 .name = "spapr_dtb", 2065 .version_id = 1, 2066 .minimum_version_id = 1, 2067 .needed = spapr_dtb_needed, 2068 .pre_load = spapr_dtb_pre_load, 2069 .fields = (const VMStateField[]) { 2070 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2071 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2072 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2073 fdt_size), 2074 VMSTATE_END_OF_LIST() 2075 }, 2076 }; 2077 2078 static bool spapr_fwnmi_needed(void *opaque) 2079 { 2080 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2081 2082 return spapr->fwnmi_machine_check_addr != -1; 2083 } 2084 2085 static int spapr_fwnmi_pre_save(void *opaque) 2086 { 2087 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2088 2089 /* 2090 * Check if machine check handling is in progress and print a 2091 * warning message. 2092 */ 2093 if (spapr->fwnmi_machine_check_interlock != -1) { 2094 warn_report("A machine check is being handled during migration. The" 2095 "handler may run and log hardware error on the destination"); 2096 } 2097 2098 return 0; 2099 } 2100 2101 static const VMStateDescription vmstate_spapr_fwnmi = { 2102 .name = "spapr_fwnmi", 2103 .version_id = 1, 2104 .minimum_version_id = 1, 2105 .needed = spapr_fwnmi_needed, 2106 .pre_save = spapr_fwnmi_pre_save, 2107 .fields = (const VMStateField[]) { 2108 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2109 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2110 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2111 VMSTATE_END_OF_LIST() 2112 }, 2113 }; 2114 2115 static const VMStateDescription vmstate_spapr = { 2116 .name = "spapr", 2117 .version_id = 3, 2118 .minimum_version_id = 1, 2119 .pre_load = spapr_pre_load, 2120 .post_load = spapr_post_load, 2121 .pre_save = spapr_pre_save, 2122 .fields = (const VMStateField[]) { 2123 /* used to be @next_irq */ 2124 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2125 2126 /* RTC offset */ 2127 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2128 2129 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2130 VMSTATE_END_OF_LIST() 2131 }, 2132 .subsections = (const VMStateDescription * const []) { 2133 &vmstate_spapr_ov5_cas, 2134 &vmstate_spapr_patb_entry, 2135 &vmstate_spapr_pending_events, 2136 &vmstate_spapr_cap_htm, 2137 &vmstate_spapr_cap_vsx, 2138 &vmstate_spapr_cap_dfp, 2139 &vmstate_spapr_cap_cfpc, 2140 &vmstate_spapr_cap_sbbc, 2141 &vmstate_spapr_cap_ibs, 2142 &vmstate_spapr_cap_hpt_maxpagesize, 2143 &vmstate_spapr_irq_map, 2144 &vmstate_spapr_cap_nested_kvm_hv, 2145 &vmstate_spapr_dtb, 2146 &vmstate_spapr_cap_large_decr, 2147 &vmstate_spapr_cap_ccf_assist, 2148 &vmstate_spapr_cap_fwnmi, 2149 &vmstate_spapr_fwnmi, 2150 &vmstate_spapr_cap_rpt_invalidate, 2151 NULL 2152 } 2153 }; 2154 2155 static int htab_save_setup(QEMUFile *f, void *opaque) 2156 { 2157 SpaprMachineState *spapr = opaque; 2158 2159 /* "Iteration" header */ 2160 if (!spapr->htab_shift) { 2161 qemu_put_be32(f, -1); 2162 } else { 2163 qemu_put_be32(f, spapr->htab_shift); 2164 } 2165 2166 if (spapr->htab) { 2167 spapr->htab_save_index = 0; 2168 spapr->htab_first_pass = true; 2169 } else { 2170 if (spapr->htab_shift) { 2171 assert(kvm_enabled()); 2172 } 2173 } 2174 2175 2176 return 0; 2177 } 2178 2179 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2180 int chunkstart, int n_valid, int n_invalid) 2181 { 2182 qemu_put_be32(f, chunkstart); 2183 qemu_put_be16(f, n_valid); 2184 qemu_put_be16(f, n_invalid); 2185 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2186 HASH_PTE_SIZE_64 * n_valid); 2187 } 2188 2189 static void htab_save_end_marker(QEMUFile *f) 2190 { 2191 qemu_put_be32(f, 0); 2192 qemu_put_be16(f, 0); 2193 qemu_put_be16(f, 0); 2194 } 2195 2196 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2197 int64_t max_ns) 2198 { 2199 bool has_timeout = max_ns != -1; 2200 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2201 int index = spapr->htab_save_index; 2202 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2203 2204 assert(spapr->htab_first_pass); 2205 2206 do { 2207 int chunkstart; 2208 2209 /* Consume invalid HPTEs */ 2210 while ((index < htabslots) 2211 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2212 CLEAN_HPTE(HPTE(spapr->htab, index)); 2213 index++; 2214 } 2215 2216 /* Consume valid HPTEs */ 2217 chunkstart = index; 2218 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2219 && HPTE_VALID(HPTE(spapr->htab, index))) { 2220 CLEAN_HPTE(HPTE(spapr->htab, index)); 2221 index++; 2222 } 2223 2224 if (index > chunkstart) { 2225 int n_valid = index - chunkstart; 2226 2227 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2228 2229 if (has_timeout && 2230 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2231 break; 2232 } 2233 } 2234 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2235 2236 if (index >= htabslots) { 2237 assert(index == htabslots); 2238 index = 0; 2239 spapr->htab_first_pass = false; 2240 } 2241 spapr->htab_save_index = index; 2242 } 2243 2244 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2245 int64_t max_ns) 2246 { 2247 bool final = max_ns < 0; 2248 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2249 int examined = 0, sent = 0; 2250 int index = spapr->htab_save_index; 2251 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2252 2253 assert(!spapr->htab_first_pass); 2254 2255 do { 2256 int chunkstart, invalidstart; 2257 2258 /* Consume non-dirty HPTEs */ 2259 while ((index < htabslots) 2260 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2261 index++; 2262 examined++; 2263 } 2264 2265 chunkstart = index; 2266 /* Consume valid dirty HPTEs */ 2267 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2268 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2269 && HPTE_VALID(HPTE(spapr->htab, index))) { 2270 CLEAN_HPTE(HPTE(spapr->htab, index)); 2271 index++; 2272 examined++; 2273 } 2274 2275 invalidstart = index; 2276 /* Consume invalid dirty HPTEs */ 2277 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2278 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2279 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2280 CLEAN_HPTE(HPTE(spapr->htab, index)); 2281 index++; 2282 examined++; 2283 } 2284 2285 if (index > chunkstart) { 2286 int n_valid = invalidstart - chunkstart; 2287 int n_invalid = index - invalidstart; 2288 2289 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2290 sent += index - chunkstart; 2291 2292 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2293 break; 2294 } 2295 } 2296 2297 if (examined >= htabslots) { 2298 break; 2299 } 2300 2301 if (index >= htabslots) { 2302 assert(index == htabslots); 2303 index = 0; 2304 } 2305 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2306 2307 if (index >= htabslots) { 2308 assert(index == htabslots); 2309 index = 0; 2310 } 2311 2312 spapr->htab_save_index = index; 2313 2314 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2315 } 2316 2317 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2318 #define MAX_KVM_BUF_SIZE 2048 2319 2320 static int htab_save_iterate(QEMUFile *f, void *opaque) 2321 { 2322 SpaprMachineState *spapr = opaque; 2323 int fd; 2324 int rc = 0; 2325 2326 /* Iteration header */ 2327 if (!spapr->htab_shift) { 2328 qemu_put_be32(f, -1); 2329 return 1; 2330 } else { 2331 qemu_put_be32(f, 0); 2332 } 2333 2334 if (!spapr->htab) { 2335 assert(kvm_enabled()); 2336 2337 fd = get_htab_fd(spapr); 2338 if (fd < 0) { 2339 return fd; 2340 } 2341 2342 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2343 if (rc < 0) { 2344 return rc; 2345 } 2346 } else if (spapr->htab_first_pass) { 2347 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2348 } else { 2349 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2350 } 2351 2352 htab_save_end_marker(f); 2353 2354 return rc; 2355 } 2356 2357 static int htab_save_complete(QEMUFile *f, void *opaque) 2358 { 2359 SpaprMachineState *spapr = opaque; 2360 int fd; 2361 2362 /* Iteration header */ 2363 if (!spapr->htab_shift) { 2364 qemu_put_be32(f, -1); 2365 return 0; 2366 } else { 2367 qemu_put_be32(f, 0); 2368 } 2369 2370 if (!spapr->htab) { 2371 int rc; 2372 2373 assert(kvm_enabled()); 2374 2375 fd = get_htab_fd(spapr); 2376 if (fd < 0) { 2377 return fd; 2378 } 2379 2380 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2381 if (rc < 0) { 2382 return rc; 2383 } 2384 } else { 2385 if (spapr->htab_first_pass) { 2386 htab_save_first_pass(f, spapr, -1); 2387 } 2388 htab_save_later_pass(f, spapr, -1); 2389 } 2390 2391 /* End marker */ 2392 htab_save_end_marker(f); 2393 2394 return 0; 2395 } 2396 2397 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2398 { 2399 SpaprMachineState *spapr = opaque; 2400 uint32_t section_hdr; 2401 int fd = -1; 2402 Error *local_err = NULL; 2403 2404 if (version_id < 1 || version_id > 1) { 2405 error_report("htab_load() bad version"); 2406 return -EINVAL; 2407 } 2408 2409 section_hdr = qemu_get_be32(f); 2410 2411 if (section_hdr == -1) { 2412 spapr_free_hpt(spapr); 2413 return 0; 2414 } 2415 2416 if (section_hdr) { 2417 int ret; 2418 2419 /* First section gives the htab size */ 2420 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2421 if (ret < 0) { 2422 error_report_err(local_err); 2423 return ret; 2424 } 2425 return 0; 2426 } 2427 2428 if (!spapr->htab) { 2429 assert(kvm_enabled()); 2430 2431 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2432 if (fd < 0) { 2433 error_report_err(local_err); 2434 return fd; 2435 } 2436 } 2437 2438 while (true) { 2439 uint32_t index; 2440 uint16_t n_valid, n_invalid; 2441 2442 index = qemu_get_be32(f); 2443 n_valid = qemu_get_be16(f); 2444 n_invalid = qemu_get_be16(f); 2445 2446 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2447 /* End of Stream */ 2448 break; 2449 } 2450 2451 if ((index + n_valid + n_invalid) > 2452 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2453 /* Bad index in stream */ 2454 error_report( 2455 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2456 index, n_valid, n_invalid, spapr->htab_shift); 2457 return -EINVAL; 2458 } 2459 2460 if (spapr->htab) { 2461 if (n_valid) { 2462 qemu_get_buffer(f, HPTE(spapr->htab, index), 2463 HASH_PTE_SIZE_64 * n_valid); 2464 } 2465 if (n_invalid) { 2466 memset(HPTE(spapr->htab, index + n_valid), 0, 2467 HASH_PTE_SIZE_64 * n_invalid); 2468 } 2469 } else { 2470 int rc; 2471 2472 assert(fd >= 0); 2473 2474 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2475 &local_err); 2476 if (rc < 0) { 2477 error_report_err(local_err); 2478 return rc; 2479 } 2480 } 2481 } 2482 2483 if (!spapr->htab) { 2484 assert(fd >= 0); 2485 close(fd); 2486 } 2487 2488 return 0; 2489 } 2490 2491 static void htab_save_cleanup(void *opaque) 2492 { 2493 SpaprMachineState *spapr = opaque; 2494 2495 close_htab_fd(spapr); 2496 } 2497 2498 static SaveVMHandlers savevm_htab_handlers = { 2499 .save_setup = htab_save_setup, 2500 .save_live_iterate = htab_save_iterate, 2501 .save_live_complete_precopy = htab_save_complete, 2502 .save_cleanup = htab_save_cleanup, 2503 .load_state = htab_load, 2504 }; 2505 2506 static void spapr_boot_set(void *opaque, const char *boot_device, 2507 Error **errp) 2508 { 2509 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2510 2511 g_free(spapr->boot_device); 2512 spapr->boot_device = g_strdup(boot_device); 2513 } 2514 2515 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2516 { 2517 MachineState *machine = MACHINE(spapr); 2518 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2519 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2520 int i; 2521 2522 g_assert(!nr_lmbs || machine->device_memory); 2523 for (i = 0; i < nr_lmbs; i++) { 2524 uint64_t addr; 2525 2526 addr = i * lmb_size + machine->device_memory->base; 2527 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2528 addr / lmb_size); 2529 } 2530 } 2531 2532 /* 2533 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2534 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2535 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2536 */ 2537 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2538 { 2539 int i; 2540 2541 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2542 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2543 " is not aligned to %" PRIu64 " MiB", 2544 machine->ram_size, 2545 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2546 return; 2547 } 2548 2549 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2550 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2551 " is not aligned to %" PRIu64 " MiB", 2552 machine->ram_size, 2553 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2554 return; 2555 } 2556 2557 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2558 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2559 error_setg(errp, 2560 "Node %d memory size 0x%" PRIx64 2561 " is not aligned to %" PRIu64 " MiB", 2562 i, machine->numa_state->nodes[i].node_mem, 2563 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2564 return; 2565 } 2566 } 2567 } 2568 2569 /* find cpu slot in machine->possible_cpus by core_id */ 2570 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2571 { 2572 int index = id / ms->smp.threads; 2573 2574 if (index >= ms->possible_cpus->len) { 2575 return NULL; 2576 } 2577 if (idx) { 2578 *idx = index; 2579 } 2580 return &ms->possible_cpus->cpus[index]; 2581 } 2582 2583 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2584 { 2585 MachineState *ms = MACHINE(spapr); 2586 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2587 Error *local_err = NULL; 2588 bool vsmt_user = !!spapr->vsmt; 2589 int kvm_smt = kvmppc_smt_threads(); 2590 int ret; 2591 unsigned int smp_threads = ms->smp.threads; 2592 2593 if (tcg_enabled()) { 2594 if (smp_threads > 1 && 2595 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2596 spapr->max_compat_pvr)) { 2597 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2598 return; 2599 } 2600 2601 if (smp_threads > 8) { 2602 error_setg(errp, "TCG cannot support more than 8 threads/core " 2603 "on a pseries machine"); 2604 return; 2605 } 2606 } 2607 if (!is_power_of_2(smp_threads)) { 2608 error_setg(errp, "Cannot support %d threads/core on a pseries " 2609 "machine because it must be a power of 2", smp_threads); 2610 return; 2611 } 2612 2613 /* Determine the VSMT mode to use: */ 2614 if (vsmt_user) { 2615 if (spapr->vsmt < smp_threads) { 2616 error_setg(errp, "Cannot support VSMT mode %d" 2617 " because it must be >= threads/core (%d)", 2618 spapr->vsmt, smp_threads); 2619 return; 2620 } 2621 /* In this case, spapr->vsmt has been set by the command line */ 2622 } else if (!smc->smp_threads_vsmt) { 2623 /* 2624 * Default VSMT value is tricky, because we need it to be as 2625 * consistent as possible (for migration), but this requires 2626 * changing it for at least some existing cases. We pick 8 as 2627 * the value that we'd get with KVM on POWER8, the 2628 * overwhelmingly common case in production systems. 2629 */ 2630 spapr->vsmt = MAX(8, smp_threads); 2631 } else { 2632 spapr->vsmt = smp_threads; 2633 } 2634 2635 /* KVM: If necessary, set the SMT mode: */ 2636 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2637 ret = kvmppc_set_smt_threads(spapr->vsmt); 2638 if (ret) { 2639 /* Looks like KVM isn't able to change VSMT mode */ 2640 error_setg(&local_err, 2641 "Failed to set KVM's VSMT mode to %d (errno %d)", 2642 spapr->vsmt, ret); 2643 /* We can live with that if the default one is big enough 2644 * for the number of threads, and a submultiple of the one 2645 * we want. In this case we'll waste some vcpu ids, but 2646 * behaviour will be correct */ 2647 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2648 warn_report_err(local_err); 2649 } else { 2650 if (!vsmt_user) { 2651 error_append_hint(&local_err, 2652 "On PPC, a VM with %d threads/core" 2653 " on a host with %d threads/core" 2654 " requires the use of VSMT mode %d.\n", 2655 smp_threads, kvm_smt, spapr->vsmt); 2656 } 2657 kvmppc_error_append_smt_possible_hint(&local_err); 2658 error_propagate(errp, local_err); 2659 } 2660 } 2661 } 2662 /* else TCG: nothing to do currently */ 2663 } 2664 2665 static void spapr_init_cpus(SpaprMachineState *spapr) 2666 { 2667 MachineState *machine = MACHINE(spapr); 2668 MachineClass *mc = MACHINE_GET_CLASS(machine); 2669 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2670 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2671 const CPUArchIdList *possible_cpus; 2672 unsigned int smp_cpus = machine->smp.cpus; 2673 unsigned int smp_threads = machine->smp.threads; 2674 unsigned int max_cpus = machine->smp.max_cpus; 2675 int boot_cores_nr = smp_cpus / smp_threads; 2676 int i; 2677 2678 possible_cpus = mc->possible_cpu_arch_ids(machine); 2679 if (mc->has_hotpluggable_cpus) { 2680 if (smp_cpus % smp_threads) { 2681 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2682 smp_cpus, smp_threads); 2683 exit(1); 2684 } 2685 if (max_cpus % smp_threads) { 2686 error_report("max_cpus (%u) must be multiple of threads (%u)", 2687 max_cpus, smp_threads); 2688 exit(1); 2689 } 2690 } else { 2691 if (max_cpus != smp_cpus) { 2692 error_report("This machine version does not support CPU hotplug"); 2693 exit(1); 2694 } 2695 boot_cores_nr = possible_cpus->len; 2696 } 2697 2698 if (smc->pre_2_10_has_unused_icps) { 2699 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2700 /* Dummy entries get deregistered when real ICPState objects 2701 * are registered during CPU core hotplug. 2702 */ 2703 pre_2_10_vmstate_register_dummy_icp(i); 2704 } 2705 } 2706 2707 for (i = 0; i < possible_cpus->len; i++) { 2708 int core_id = i * smp_threads; 2709 2710 if (mc->has_hotpluggable_cpus) { 2711 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2712 spapr_vcpu_id(spapr, core_id)); 2713 } 2714 2715 if (i < boot_cores_nr) { 2716 Object *core = object_new(type); 2717 int nr_threads = smp_threads; 2718 2719 /* Handle the partially filled core for older machine types */ 2720 if ((i + 1) * smp_threads >= smp_cpus) { 2721 nr_threads = smp_cpus - i * smp_threads; 2722 } 2723 2724 object_property_set_int(core, "nr-threads", nr_threads, 2725 &error_fatal); 2726 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2727 &error_fatal); 2728 qdev_realize(DEVICE(core), NULL, &error_fatal); 2729 2730 object_unref(core); 2731 } 2732 } 2733 } 2734 2735 static PCIHostState *spapr_create_default_phb(void) 2736 { 2737 DeviceState *dev; 2738 2739 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2740 qdev_prop_set_uint32(dev, "index", 0); 2741 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2742 2743 return PCI_HOST_BRIDGE(dev); 2744 } 2745 2746 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2747 { 2748 MachineState *machine = MACHINE(spapr); 2749 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2750 hwaddr rma_size = machine->ram_size; 2751 hwaddr node0_size = spapr_node0_size(machine); 2752 2753 /* RMA has to fit in the first NUMA node */ 2754 rma_size = MIN(rma_size, node0_size); 2755 2756 /* 2757 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2758 * never exceed that 2759 */ 2760 rma_size = MIN(rma_size, 1 * TiB); 2761 2762 /* 2763 * Clamp the RMA size based on machine type. This is for 2764 * migration compatibility with older qemu versions, which limited 2765 * the RMA size for complicated and mostly bad reasons. 2766 */ 2767 if (smc->rma_limit) { 2768 rma_size = MIN(rma_size, smc->rma_limit); 2769 } 2770 2771 if (rma_size < MIN_RMA_SLOF) { 2772 error_setg(errp, 2773 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2774 "ldMiB guest RMA (Real Mode Area memory)", 2775 MIN_RMA_SLOF / MiB); 2776 return 0; 2777 } 2778 2779 return rma_size; 2780 } 2781 2782 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2783 { 2784 MachineState *machine = MACHINE(spapr); 2785 int i; 2786 2787 for (i = 0; i < machine->ram_slots; i++) { 2788 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2789 } 2790 } 2791 2792 /* pSeries LPAR / sPAPR hardware init */ 2793 static void spapr_machine_init(MachineState *machine) 2794 { 2795 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2796 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2797 MachineClass *mc = MACHINE_GET_CLASS(machine); 2798 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2799 const char *bios_name = machine->firmware ?: bios_default; 2800 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2801 const char *kernel_filename = machine->kernel_filename; 2802 const char *initrd_filename = machine->initrd_filename; 2803 PCIHostState *phb; 2804 bool has_vga; 2805 int i; 2806 MemoryRegion *sysmem = get_system_memory(); 2807 long load_limit, fw_size; 2808 Error *resize_hpt_err = NULL; 2809 NICInfo *nd; 2810 2811 if (!filename) { 2812 error_report("Could not find LPAR firmware '%s'", bios_name); 2813 exit(1); 2814 } 2815 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2816 if (fw_size <= 0) { 2817 error_report("Could not load LPAR firmware '%s'", filename); 2818 exit(1); 2819 } 2820 2821 /* 2822 * if Secure VM (PEF) support is configured, then initialize it 2823 */ 2824 pef_kvm_init(machine->cgs, &error_fatal); 2825 2826 msi_nonbroken = true; 2827 2828 QLIST_INIT(&spapr->phbs); 2829 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2830 2831 /* Determine capabilities to run with */ 2832 spapr_caps_init(spapr); 2833 2834 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2835 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2836 /* 2837 * If the user explicitly requested a mode we should either 2838 * supply it, or fail completely (which we do below). But if 2839 * it's not set explicitly, we reset our mode to something 2840 * that works 2841 */ 2842 if (resize_hpt_err) { 2843 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2844 error_free(resize_hpt_err); 2845 resize_hpt_err = NULL; 2846 } else { 2847 spapr->resize_hpt = smc->resize_hpt_default; 2848 } 2849 } 2850 2851 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2852 2853 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2854 /* 2855 * User requested HPT resize, but this host can't supply it. Bail out 2856 */ 2857 error_report_err(resize_hpt_err); 2858 exit(1); 2859 } 2860 error_free(resize_hpt_err); 2861 2862 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2863 2864 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2865 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2866 2867 /* 2868 * VSMT must be set in order to be able to compute VCPU ids, ie to 2869 * call spapr_max_server_number() or spapr_vcpu_id(). 2870 */ 2871 spapr_set_vsmt_mode(spapr, &error_fatal); 2872 2873 /* Set up Interrupt Controller before we create the VCPUs */ 2874 spapr_irq_init(spapr, &error_fatal); 2875 2876 /* Set up containers for ibm,client-architecture-support negotiated options 2877 */ 2878 spapr->ov5 = spapr_ovec_new(); 2879 spapr->ov5_cas = spapr_ovec_new(); 2880 2881 if (smc->dr_lmb_enabled) { 2882 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2883 spapr_validate_node_memory(machine, &error_fatal); 2884 } 2885 2886 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2887 2888 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2889 if (!smc->pre_6_2_numa_affinity) { 2890 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2891 } 2892 2893 /* advertise support for dedicated HP event source to guests */ 2894 if (spapr->use_hotplug_event_source) { 2895 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2896 } 2897 2898 /* advertise support for HPT resizing */ 2899 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2900 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2901 } 2902 2903 /* advertise support for ibm,dyamic-memory-v2 */ 2904 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2905 2906 /* advertise XIVE on POWER9 machines */ 2907 if (spapr->irq->xive) { 2908 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2909 } 2910 2911 /* init CPUs */ 2912 spapr_init_cpus(spapr); 2913 2914 /* Init numa_assoc_array */ 2915 spapr_numa_associativity_init(spapr, machine); 2916 2917 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2918 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2919 spapr->max_compat_pvr)) { 2920 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2921 /* KVM and TCG always allow GTSE with radix... */ 2922 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2923 } 2924 /* ... but not with hash (currently). */ 2925 2926 if (kvm_enabled()) { 2927 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2928 kvmppc_enable_logical_ci_hcalls(); 2929 kvmppc_enable_set_mode_hcall(); 2930 2931 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2932 kvmppc_enable_clear_ref_mod_hcalls(); 2933 2934 /* Enable H_PAGE_INIT */ 2935 kvmppc_enable_h_page_init(); 2936 } 2937 2938 /* map RAM */ 2939 memory_region_add_subregion(sysmem, 0, machine->ram); 2940 2941 /* initialize hotplug memory address space */ 2942 if (machine->ram_size < machine->maxram_size) { 2943 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2944 hwaddr device_mem_base; 2945 2946 /* 2947 * Limit the number of hotpluggable memory slots to half the number 2948 * slots that KVM supports, leaving the other half for PCI and other 2949 * devices. However ensure that number of slots doesn't drop below 32. 2950 */ 2951 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2952 SPAPR_MAX_RAM_SLOTS; 2953 2954 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2955 max_memslots = SPAPR_MAX_RAM_SLOTS; 2956 } 2957 if (machine->ram_slots > max_memslots) { 2958 error_report("Specified number of memory slots %" 2959 PRIu64" exceeds max supported %d", 2960 machine->ram_slots, max_memslots); 2961 exit(1); 2962 } 2963 2964 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 2965 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 2966 } 2967 2968 if (smc->dr_lmb_enabled) { 2969 spapr_create_lmb_dr_connectors(spapr); 2970 } 2971 2972 if (mc->nvdimm_supported) { 2973 spapr_create_nvdimm_dr_connectors(spapr); 2974 } 2975 2976 /* Set up RTAS event infrastructure */ 2977 spapr_events_init(spapr); 2978 2979 /* Set up the RTC RTAS interfaces */ 2980 spapr_rtc_create(spapr); 2981 2982 /* Set up VIO bus */ 2983 spapr->vio_bus = spapr_vio_bus_init(); 2984 2985 for (i = 0; serial_hd(i); i++) { 2986 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2987 } 2988 2989 /* We always have at least the nvram device on VIO */ 2990 spapr_create_nvram(spapr); 2991 2992 /* 2993 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2994 * connectors (described in root DT node's "ibm,drc-types" property) 2995 * are pre-initialized here. additional child connectors (such as 2996 * connectors for a PHBs PCI slots) are added as needed during their 2997 * parent's realization. 2998 */ 2999 if (smc->dr_phb_enabled) { 3000 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 3001 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 3002 } 3003 } 3004 3005 /* Set up PCI */ 3006 spapr_pci_rtas_init(); 3007 3008 phb = spapr_create_default_phb(); 3009 3010 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 3011 spapr_vlan_create(spapr->vio_bus, nd); 3012 } 3013 3014 pci_init_nic_devices(phb->bus, NULL); 3015 3016 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 3017 spapr_vscsi_create(spapr->vio_bus); 3018 } 3019 3020 /* Graphics */ 3021 has_vga = spapr_vga_init(phb->bus, &error_fatal); 3022 if (has_vga) { 3023 spapr->want_stdout_path = !machine->enable_graphics; 3024 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3025 } else { 3026 spapr->want_stdout_path = true; 3027 } 3028 3029 if (machine->usb) { 3030 if (smc->use_ohci_by_default) { 3031 pci_create_simple(phb->bus, -1, "pci-ohci"); 3032 } else { 3033 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3034 } 3035 3036 if (has_vga) { 3037 USBBus *usb_bus; 3038 3039 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3040 &error_abort)); 3041 usb_create_simple(usb_bus, "usb-kbd"); 3042 usb_create_simple(usb_bus, "usb-mouse"); 3043 } 3044 } 3045 3046 if (kernel_filename) { 3047 uint64_t loaded_addr = 0; 3048 3049 spapr->kernel_size = load_elf(kernel_filename, NULL, 3050 translate_kernel_address, spapr, 3051 NULL, &loaded_addr, NULL, NULL, 1, 3052 PPC_ELF_MACHINE, 0, 0); 3053 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3054 spapr->kernel_size = load_elf(kernel_filename, NULL, 3055 translate_kernel_address, spapr, 3056 NULL, &loaded_addr, NULL, NULL, 0, 3057 PPC_ELF_MACHINE, 0, 0); 3058 spapr->kernel_le = spapr->kernel_size > 0; 3059 } 3060 if (spapr->kernel_size < 0) { 3061 error_report("error loading %s: %s", kernel_filename, 3062 load_elf_strerror(spapr->kernel_size)); 3063 exit(1); 3064 } 3065 3066 if (spapr->kernel_addr != loaded_addr) { 3067 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3068 " to 0x%"PRIx64, 3069 spapr->kernel_addr, loaded_addr); 3070 spapr->kernel_addr = loaded_addr; 3071 } 3072 3073 /* load initrd */ 3074 if (initrd_filename) { 3075 /* Try to locate the initrd in the gap between the kernel 3076 * and the firmware. Add a bit of space just in case 3077 */ 3078 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3079 + 0x1ffff) & ~0xffff; 3080 spapr->initrd_size = load_image_targphys(initrd_filename, 3081 spapr->initrd_base, 3082 load_limit 3083 - spapr->initrd_base); 3084 if (spapr->initrd_size < 0) { 3085 error_report("could not load initial ram disk '%s'", 3086 initrd_filename); 3087 exit(1); 3088 } 3089 } 3090 } 3091 3092 /* FIXME: Should register things through the MachineState's qdev 3093 * interface, this is a legacy from the sPAPREnvironment structure 3094 * which predated MachineState but had a similar function */ 3095 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3096 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3097 &savevm_htab_handlers, spapr); 3098 3099 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3100 3101 qemu_register_boot_set(spapr_boot_set, spapr); 3102 3103 /* 3104 * Nothing needs to be done to resume a suspended guest because 3105 * suspending does not change the machine state, so no need for 3106 * a ->wakeup method. 3107 */ 3108 qemu_register_wakeup_support(); 3109 3110 if (kvm_enabled()) { 3111 /* to stop and start vmclock */ 3112 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3113 &spapr->tb); 3114 3115 kvmppc_spapr_enable_inkernel_multitce(); 3116 } 3117 3118 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3119 if (spapr->vof) { 3120 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3121 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3122 } 3123 3124 spapr_watchdog_init(spapr); 3125 } 3126 3127 #define DEFAULT_KVM_TYPE "auto" 3128 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3129 { 3130 /* 3131 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3132 * accommodate the 'HV' and 'PV' formats that exists in the 3133 * wild. The 'auto' mode is being introduced already as 3134 * lower-case, thus we don't need to bother checking for 3135 * "AUTO". 3136 */ 3137 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3138 return 0; 3139 } 3140 3141 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3142 return 1; 3143 } 3144 3145 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3146 return 2; 3147 } 3148 3149 error_report("Unknown kvm-type specified '%s'", vm_type); 3150 return -1; 3151 } 3152 3153 /* 3154 * Implementation of an interface to adjust firmware path 3155 * for the bootindex property handling. 3156 */ 3157 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3158 DeviceState *dev) 3159 { 3160 #define CAST(type, obj, name) \ 3161 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3162 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3163 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3164 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3165 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3166 3167 if (d && bus) { 3168 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3169 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3170 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3171 3172 if (spapr) { 3173 /* 3174 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3175 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3176 * 0x8000 | (target << 8) | (bus << 5) | lun 3177 * (see the "Logical unit addressing format" table in SAM5) 3178 */ 3179 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3180 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3181 (uint64_t)id << 48); 3182 } else if (virtio) { 3183 /* 3184 * We use SRP luns of the form 01000000 | (target << 8) | lun 3185 * in the top 32 bits of the 64-bit LUN 3186 * Note: the quote above is from SLOF and it is wrong, 3187 * the actual binding is: 3188 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3189 */ 3190 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3191 if (d->lun >= 256) { 3192 /* Use the LUN "flat space addressing method" */ 3193 id |= 0x4000; 3194 } 3195 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3196 (uint64_t)id << 32); 3197 } else if (usb) { 3198 /* 3199 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3200 * in the top 32 bits of the 64-bit LUN 3201 */ 3202 unsigned usb_port = atoi(usb->port->path); 3203 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3204 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3205 (uint64_t)id << 32); 3206 } 3207 } 3208 3209 /* 3210 * SLOF probes the USB devices, and if it recognizes that the device is a 3211 * storage device, it changes its name to "storage" instead of "usb-host", 3212 * and additionally adds a child node for the SCSI LUN, so the correct 3213 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3214 */ 3215 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3216 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3217 if (usb_device_is_scsi_storage(usbdev)) { 3218 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3219 } 3220 } 3221 3222 if (phb) { 3223 /* Replace "pci" with "pci@800000020000000" */ 3224 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3225 } 3226 3227 if (vsc) { 3228 /* Same logic as virtio above */ 3229 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3230 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3231 } 3232 3233 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3234 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3235 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3236 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3237 } 3238 3239 if (pcidev) { 3240 return spapr_pci_fw_dev_name(pcidev); 3241 } 3242 3243 return NULL; 3244 } 3245 3246 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3247 { 3248 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3249 3250 return g_strdup(spapr->kvm_type); 3251 } 3252 3253 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3254 { 3255 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3256 3257 g_free(spapr->kvm_type); 3258 spapr->kvm_type = g_strdup(value); 3259 } 3260 3261 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3262 { 3263 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3264 3265 return spapr->use_hotplug_event_source; 3266 } 3267 3268 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3269 Error **errp) 3270 { 3271 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3272 3273 spapr->use_hotplug_event_source = value; 3274 } 3275 3276 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3277 { 3278 return true; 3279 } 3280 3281 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3282 { 3283 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3284 3285 switch (spapr->resize_hpt) { 3286 case SPAPR_RESIZE_HPT_DEFAULT: 3287 return g_strdup("default"); 3288 case SPAPR_RESIZE_HPT_DISABLED: 3289 return g_strdup("disabled"); 3290 case SPAPR_RESIZE_HPT_ENABLED: 3291 return g_strdup("enabled"); 3292 case SPAPR_RESIZE_HPT_REQUIRED: 3293 return g_strdup("required"); 3294 } 3295 g_assert_not_reached(); 3296 } 3297 3298 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3299 { 3300 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3301 3302 if (strcmp(value, "default") == 0) { 3303 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3304 } else if (strcmp(value, "disabled") == 0) { 3305 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3306 } else if (strcmp(value, "enabled") == 0) { 3307 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3308 } else if (strcmp(value, "required") == 0) { 3309 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3310 } else { 3311 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3312 } 3313 } 3314 3315 static bool spapr_get_vof(Object *obj, Error **errp) 3316 { 3317 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3318 3319 return spapr->vof != NULL; 3320 } 3321 3322 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3323 { 3324 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3325 3326 if (spapr->vof) { 3327 vof_cleanup(spapr->vof); 3328 g_free(spapr->vof); 3329 spapr->vof = NULL; 3330 } 3331 if (!value) { 3332 return; 3333 } 3334 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3335 } 3336 3337 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3338 { 3339 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3340 3341 if (spapr->irq == &spapr_irq_xics_legacy) { 3342 return g_strdup("legacy"); 3343 } else if (spapr->irq == &spapr_irq_xics) { 3344 return g_strdup("xics"); 3345 } else if (spapr->irq == &spapr_irq_xive) { 3346 return g_strdup("xive"); 3347 } else if (spapr->irq == &spapr_irq_dual) { 3348 return g_strdup("dual"); 3349 } 3350 g_assert_not_reached(); 3351 } 3352 3353 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3354 { 3355 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3356 3357 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3358 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3359 return; 3360 } 3361 3362 /* The legacy IRQ backend can not be set */ 3363 if (strcmp(value, "xics") == 0) { 3364 spapr->irq = &spapr_irq_xics; 3365 } else if (strcmp(value, "xive") == 0) { 3366 spapr->irq = &spapr_irq_xive; 3367 } else if (strcmp(value, "dual") == 0) { 3368 spapr->irq = &spapr_irq_dual; 3369 } else { 3370 error_setg(errp, "Bad value for \"ic-mode\" property"); 3371 } 3372 } 3373 3374 static char *spapr_get_host_model(Object *obj, Error **errp) 3375 { 3376 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3377 3378 return g_strdup(spapr->host_model); 3379 } 3380 3381 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3382 { 3383 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3384 3385 g_free(spapr->host_model); 3386 spapr->host_model = g_strdup(value); 3387 } 3388 3389 static char *spapr_get_host_serial(Object *obj, Error **errp) 3390 { 3391 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3392 3393 return g_strdup(spapr->host_serial); 3394 } 3395 3396 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3397 { 3398 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3399 3400 g_free(spapr->host_serial); 3401 spapr->host_serial = g_strdup(value); 3402 } 3403 3404 static void spapr_instance_init(Object *obj) 3405 { 3406 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3407 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3408 MachineState *ms = MACHINE(spapr); 3409 MachineClass *mc = MACHINE_GET_CLASS(ms); 3410 3411 /* 3412 * NVDIMM support went live in 5.1 without considering that, in 3413 * other archs, the user needs to enable NVDIMM support with the 3414 * 'nvdimm' machine option and the default behavior is NVDIMM 3415 * support disabled. It is too late to roll back to the standard 3416 * behavior without breaking 5.1 guests. 3417 */ 3418 if (mc->nvdimm_supported) { 3419 ms->nvdimms_state->is_enabled = true; 3420 } 3421 3422 spapr->htab_fd = -1; 3423 spapr->use_hotplug_event_source = true; 3424 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3425 object_property_add_str(obj, "kvm-type", 3426 spapr_get_kvm_type, spapr_set_kvm_type); 3427 object_property_set_description(obj, "kvm-type", 3428 "Specifies the KVM virtualization mode (auto," 3429 " hv, pr). Defaults to 'auto'. This mode will use" 3430 " any available KVM module loaded in the host," 3431 " where kvm_hv takes precedence if both kvm_hv and" 3432 " kvm_pr are loaded."); 3433 object_property_add_bool(obj, "modern-hotplug-events", 3434 spapr_get_modern_hotplug_events, 3435 spapr_set_modern_hotplug_events); 3436 object_property_set_description(obj, "modern-hotplug-events", 3437 "Use dedicated hotplug event mechanism in" 3438 " place of standard EPOW events when possible" 3439 " (required for memory hot-unplug support)"); 3440 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3441 "Maximum permitted CPU compatibility mode"); 3442 3443 object_property_add_str(obj, "resize-hpt", 3444 spapr_get_resize_hpt, spapr_set_resize_hpt); 3445 object_property_set_description(obj, "resize-hpt", 3446 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3447 object_property_add_uint32_ptr(obj, "vsmt", 3448 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3449 object_property_set_description(obj, "vsmt", 3450 "Virtual SMT: KVM behaves as if this were" 3451 " the host's SMT mode"); 3452 3453 object_property_add_bool(obj, "vfio-no-msix-emulation", 3454 spapr_get_msix_emulation, NULL); 3455 3456 object_property_add_uint64_ptr(obj, "kernel-addr", 3457 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3458 object_property_set_description(obj, "kernel-addr", 3459 stringify(KERNEL_LOAD_ADDR) 3460 " for -kernel is the default"); 3461 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3462 3463 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3464 object_property_set_description(obj, "x-vof", 3465 "Enable Virtual Open Firmware (experimental)"); 3466 3467 /* The machine class defines the default interrupt controller mode */ 3468 spapr->irq = smc->irq; 3469 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3470 spapr_set_ic_mode); 3471 object_property_set_description(obj, "ic-mode", 3472 "Specifies the interrupt controller mode (xics, xive, dual)"); 3473 3474 object_property_add_str(obj, "host-model", 3475 spapr_get_host_model, spapr_set_host_model); 3476 object_property_set_description(obj, "host-model", 3477 "Host model to advertise in guest device tree"); 3478 object_property_add_str(obj, "host-serial", 3479 spapr_get_host_serial, spapr_set_host_serial); 3480 object_property_set_description(obj, "host-serial", 3481 "Host serial number to advertise in guest device tree"); 3482 } 3483 3484 static void spapr_machine_finalizefn(Object *obj) 3485 { 3486 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3487 3488 g_free(spapr->kvm_type); 3489 } 3490 3491 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3492 { 3493 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3494 PowerPCCPU *cpu = POWERPC_CPU(cs); 3495 CPUPPCState *env = &cpu->env; 3496 3497 cpu_synchronize_state(cs); 3498 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3499 if (spapr->fwnmi_system_reset_addr != -1) { 3500 uint64_t rtas_addr, addr; 3501 3502 /* get rtas addr from fdt */ 3503 rtas_addr = spapr_get_rtas_addr(); 3504 if (!rtas_addr) { 3505 qemu_system_guest_panicked(NULL); 3506 return; 3507 } 3508 3509 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3510 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3511 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3512 env->gpr[3] = addr; 3513 } 3514 ppc_cpu_do_system_reset(cs); 3515 if (spapr->fwnmi_system_reset_addr != -1) { 3516 env->nip = spapr->fwnmi_system_reset_addr; 3517 } 3518 } 3519 3520 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3521 { 3522 CPUState *cs; 3523 3524 CPU_FOREACH(cs) { 3525 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3526 } 3527 } 3528 3529 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3530 void *fdt, int *fdt_start_offset, Error **errp) 3531 { 3532 uint64_t addr; 3533 uint32_t node; 3534 3535 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3536 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3537 &error_abort); 3538 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3539 SPAPR_MEMORY_BLOCK_SIZE); 3540 return 0; 3541 } 3542 3543 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3544 bool dedicated_hp_event_source) 3545 { 3546 SpaprDrc *drc; 3547 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3548 int i; 3549 uint64_t addr = addr_start; 3550 bool hotplugged = spapr_drc_hotplugged(dev); 3551 3552 for (i = 0; i < nr_lmbs; i++) { 3553 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3554 addr / SPAPR_MEMORY_BLOCK_SIZE); 3555 g_assert(drc); 3556 3557 /* 3558 * memory_device_get_free_addr() provided a range of free addresses 3559 * that doesn't overlap with any existing mapping at pre-plug. The 3560 * corresponding LMB DRCs are thus assumed to be all attachable. 3561 */ 3562 spapr_drc_attach(drc, dev); 3563 if (!hotplugged) { 3564 spapr_drc_reset(drc); 3565 } 3566 addr += SPAPR_MEMORY_BLOCK_SIZE; 3567 } 3568 /* send hotplug notification to the 3569 * guest only in case of hotplugged memory 3570 */ 3571 if (hotplugged) { 3572 if (dedicated_hp_event_source) { 3573 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3574 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3575 g_assert(drc); 3576 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3577 nr_lmbs, 3578 spapr_drc_index(drc)); 3579 } else { 3580 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3581 nr_lmbs); 3582 } 3583 } 3584 } 3585 3586 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3587 { 3588 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3589 PCDIMMDevice *dimm = PC_DIMM(dev); 3590 uint64_t size, addr; 3591 int64_t slot; 3592 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3593 3594 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3595 3596 pc_dimm_plug(dimm, MACHINE(ms)); 3597 3598 if (!is_nvdimm) { 3599 addr = object_property_get_uint(OBJECT(dimm), 3600 PC_DIMM_ADDR_PROP, &error_abort); 3601 spapr_add_lmbs(dev, addr, size, 3602 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3603 } else { 3604 slot = object_property_get_int(OBJECT(dimm), 3605 PC_DIMM_SLOT_PROP, &error_abort); 3606 /* We should have valid slot number at this point */ 3607 g_assert(slot >= 0); 3608 spapr_add_nvdimm(dev, slot); 3609 } 3610 } 3611 3612 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3613 Error **errp) 3614 { 3615 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3616 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3617 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3618 PCDIMMDevice *dimm = PC_DIMM(dev); 3619 Error *local_err = NULL; 3620 uint64_t size; 3621 Object *memdev; 3622 hwaddr pagesize; 3623 3624 if (!smc->dr_lmb_enabled) { 3625 error_setg(errp, "Memory hotplug not supported for this machine"); 3626 return; 3627 } 3628 3629 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3630 if (local_err) { 3631 error_propagate(errp, local_err); 3632 return; 3633 } 3634 3635 if (is_nvdimm) { 3636 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3637 return; 3638 } 3639 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3640 error_setg(errp, "Hotplugged memory size must be a multiple of " 3641 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3642 return; 3643 } 3644 3645 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3646 &error_abort); 3647 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3648 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3649 return; 3650 } 3651 3652 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3653 } 3654 3655 struct SpaprDimmState { 3656 PCDIMMDevice *dimm; 3657 uint32_t nr_lmbs; 3658 QTAILQ_ENTRY(SpaprDimmState) next; 3659 }; 3660 3661 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3662 PCDIMMDevice *dimm) 3663 { 3664 SpaprDimmState *dimm_state = NULL; 3665 3666 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3667 if (dimm_state->dimm == dimm) { 3668 break; 3669 } 3670 } 3671 return dimm_state; 3672 } 3673 3674 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3675 uint32_t nr_lmbs, 3676 PCDIMMDevice *dimm) 3677 { 3678 SpaprDimmState *ds = NULL; 3679 3680 /* 3681 * If this request is for a DIMM whose removal had failed earlier 3682 * (due to guest's refusal to remove the LMBs), we would have this 3683 * dimm already in the pending_dimm_unplugs list. In that 3684 * case don't add again. 3685 */ 3686 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3687 if (!ds) { 3688 ds = g_new0(SpaprDimmState, 1); 3689 ds->nr_lmbs = nr_lmbs; 3690 ds->dimm = dimm; 3691 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3692 } 3693 return ds; 3694 } 3695 3696 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3697 SpaprDimmState *dimm_state) 3698 { 3699 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3700 g_free(dimm_state); 3701 } 3702 3703 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3704 PCDIMMDevice *dimm) 3705 { 3706 SpaprDrc *drc; 3707 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3708 &error_abort); 3709 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3710 uint32_t avail_lmbs = 0; 3711 uint64_t addr_start, addr; 3712 int i; 3713 3714 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3715 &error_abort); 3716 3717 addr = addr_start; 3718 for (i = 0; i < nr_lmbs; i++) { 3719 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3720 addr / SPAPR_MEMORY_BLOCK_SIZE); 3721 g_assert(drc); 3722 if (drc->dev) { 3723 avail_lmbs++; 3724 } 3725 addr += SPAPR_MEMORY_BLOCK_SIZE; 3726 } 3727 3728 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3729 } 3730 3731 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3732 { 3733 SpaprDimmState *ds; 3734 PCDIMMDevice *dimm; 3735 SpaprDrc *drc; 3736 uint32_t nr_lmbs; 3737 uint64_t size, addr_start, addr; 3738 g_autofree char *qapi_error = NULL; 3739 int i; 3740 3741 if (!dev) { 3742 return; 3743 } 3744 3745 dimm = PC_DIMM(dev); 3746 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3747 3748 /* 3749 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3750 * unplug state, but one of its DRC is marked as unplug_requested. 3751 * This is bad and weird enough to g_assert() out. 3752 */ 3753 g_assert(ds); 3754 3755 spapr_pending_dimm_unplugs_remove(spapr, ds); 3756 3757 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3758 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3759 3760 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3761 &error_abort); 3762 3763 addr = addr_start; 3764 for (i = 0; i < nr_lmbs; i++) { 3765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3766 addr / SPAPR_MEMORY_BLOCK_SIZE); 3767 g_assert(drc); 3768 3769 drc->unplug_requested = false; 3770 addr += SPAPR_MEMORY_BLOCK_SIZE; 3771 } 3772 3773 /* 3774 * Tell QAPI that something happened and the memory 3775 * hotunplug wasn't successful. Keep sending 3776 * MEM_UNPLUG_ERROR even while sending 3777 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3778 * MEM_UNPLUG_ERROR is due. 3779 */ 3780 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3781 "for device %s", dev->id); 3782 3783 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3784 3785 qapi_event_send_device_unplug_guest_error(dev->id, 3786 dev->canonical_path); 3787 } 3788 3789 /* Callback to be called during DRC release. */ 3790 void spapr_lmb_release(DeviceState *dev) 3791 { 3792 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3793 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3794 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3795 3796 /* This information will get lost if a migration occurs 3797 * during the unplug process. In this case recover it. */ 3798 if (ds == NULL) { 3799 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3800 g_assert(ds); 3801 /* The DRC being examined by the caller at least must be counted */ 3802 g_assert(ds->nr_lmbs); 3803 } 3804 3805 if (--ds->nr_lmbs) { 3806 return; 3807 } 3808 3809 /* 3810 * Now that all the LMBs have been removed by the guest, call the 3811 * unplug handler chain. This can never fail. 3812 */ 3813 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3814 object_unparent(OBJECT(dev)); 3815 } 3816 3817 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3818 { 3819 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3820 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3821 3822 /* We really shouldn't get this far without anything to unplug */ 3823 g_assert(ds); 3824 3825 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3826 qdev_unrealize(dev); 3827 spapr_pending_dimm_unplugs_remove(spapr, ds); 3828 } 3829 3830 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3831 DeviceState *dev, Error **errp) 3832 { 3833 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3834 PCDIMMDevice *dimm = PC_DIMM(dev); 3835 uint32_t nr_lmbs; 3836 uint64_t size, addr_start, addr; 3837 int i; 3838 SpaprDrc *drc; 3839 3840 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3841 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3842 return; 3843 } 3844 3845 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3846 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3847 3848 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3849 &error_abort); 3850 3851 /* 3852 * An existing pending dimm state for this DIMM means that there is an 3853 * unplug operation in progress, waiting for the spapr_lmb_release 3854 * callback to complete the job (BQL can't cover that far). In this case, 3855 * bail out to avoid detaching DRCs that were already released. 3856 */ 3857 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3858 error_setg(errp, "Memory unplug already in progress for device %s", 3859 dev->id); 3860 return; 3861 } 3862 3863 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3864 3865 addr = addr_start; 3866 for (i = 0; i < nr_lmbs; i++) { 3867 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3868 addr / SPAPR_MEMORY_BLOCK_SIZE); 3869 g_assert(drc); 3870 3871 spapr_drc_unplug_request(drc); 3872 addr += SPAPR_MEMORY_BLOCK_SIZE; 3873 } 3874 3875 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3876 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3877 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3878 nr_lmbs, spapr_drc_index(drc)); 3879 } 3880 3881 /* Callback to be called during DRC release. */ 3882 void spapr_core_release(DeviceState *dev) 3883 { 3884 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3885 3886 /* Call the unplug handler chain. This can never fail. */ 3887 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3888 object_unparent(OBJECT(dev)); 3889 } 3890 3891 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3892 { 3893 MachineState *ms = MACHINE(hotplug_dev); 3894 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3895 CPUCore *cc = CPU_CORE(dev); 3896 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3897 3898 if (smc->pre_2_10_has_unused_icps) { 3899 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3900 int i; 3901 3902 for (i = 0; i < cc->nr_threads; i++) { 3903 CPUState *cs = CPU(sc->threads[i]); 3904 3905 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3906 } 3907 } 3908 3909 assert(core_slot); 3910 core_slot->cpu = NULL; 3911 qdev_unrealize(dev); 3912 } 3913 3914 static 3915 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3916 Error **errp) 3917 { 3918 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3919 int index; 3920 SpaprDrc *drc; 3921 CPUCore *cc = CPU_CORE(dev); 3922 3923 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3924 error_setg(errp, "Unable to find CPU core with core-id: %d", 3925 cc->core_id); 3926 return; 3927 } 3928 if (index == 0) { 3929 error_setg(errp, "Boot CPU core may not be unplugged"); 3930 return; 3931 } 3932 3933 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3934 spapr_vcpu_id(spapr, cc->core_id)); 3935 g_assert(drc); 3936 3937 if (!spapr_drc_unplug_requested(drc)) { 3938 spapr_drc_unplug_request(drc); 3939 } 3940 3941 /* 3942 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3943 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3944 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3945 * attempt (e.g. the kernel will refuse to remove the last online 3946 * CPU), we will never attempt it again because unplug_requested 3947 * will still be 'true' in that case. 3948 */ 3949 spapr_hotplug_req_remove_by_index(drc); 3950 } 3951 3952 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3953 void *fdt, int *fdt_start_offset, Error **errp) 3954 { 3955 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3956 CPUState *cs = CPU(core->threads[0]); 3957 PowerPCCPU *cpu = POWERPC_CPU(cs); 3958 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3959 int id = spapr_get_vcpu_id(cpu); 3960 g_autofree char *nodename = NULL; 3961 int offset; 3962 3963 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3964 offset = fdt_add_subnode(fdt, 0, nodename); 3965 3966 spapr_dt_cpu(cs, fdt, offset, spapr); 3967 3968 /* 3969 * spapr_dt_cpu() does not fill the 'name' property in the 3970 * CPU node. The function is called during boot process, before 3971 * and after CAS, and overwriting the 'name' property written 3972 * by SLOF is not allowed. 3973 * 3974 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3975 * CPUs more compatible with the coldplugged ones, which have 3976 * the 'name' property. Linux Kernel also relies on this 3977 * property to identify CPU nodes. 3978 */ 3979 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3980 3981 *fdt_start_offset = offset; 3982 return 0; 3983 } 3984 3985 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3986 { 3987 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3988 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3989 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3990 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3991 CPUCore *cc = CPU_CORE(dev); 3992 CPUState *cs; 3993 SpaprDrc *drc; 3994 CPUArchId *core_slot; 3995 int index; 3996 bool hotplugged = spapr_drc_hotplugged(dev); 3997 int i; 3998 3999 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4000 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 4001 4002 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 4003 spapr_vcpu_id(spapr, cc->core_id)); 4004 4005 g_assert(drc || !mc->has_hotpluggable_cpus); 4006 4007 if (drc) { 4008 /* 4009 * spapr_core_pre_plug() already buys us this is a brand new 4010 * core being plugged into a free slot. Nothing should already 4011 * be attached to the corresponding DRC. 4012 */ 4013 spapr_drc_attach(drc, dev); 4014 4015 if (hotplugged) { 4016 /* 4017 * Send hotplug notification interrupt to the guest only 4018 * in case of hotplugged CPUs. 4019 */ 4020 spapr_hotplug_req_add_by_index(drc); 4021 } else { 4022 spapr_drc_reset(drc); 4023 } 4024 } 4025 4026 core_slot->cpu = OBJECT(dev); 4027 4028 /* 4029 * Set compatibility mode to match the boot CPU, which was either set 4030 * by the machine reset code or by CAS. This really shouldn't fail at 4031 * this point. 4032 */ 4033 if (hotplugged) { 4034 for (i = 0; i < cc->nr_threads; i++) { 4035 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 4036 &error_abort); 4037 } 4038 } 4039 4040 if (smc->pre_2_10_has_unused_icps) { 4041 for (i = 0; i < cc->nr_threads; i++) { 4042 cs = CPU(core->threads[i]); 4043 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 4044 } 4045 } 4046 } 4047 4048 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4049 Error **errp) 4050 { 4051 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 4052 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 4053 CPUCore *cc = CPU_CORE(dev); 4054 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4055 const char *type = object_get_typename(OBJECT(dev)); 4056 CPUArchId *core_slot; 4057 int index; 4058 unsigned int smp_threads = machine->smp.threads; 4059 4060 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4061 error_setg(errp, "CPU hotplug not supported for this machine"); 4062 return; 4063 } 4064 4065 if (strcmp(base_core_type, type)) { 4066 error_setg(errp, "CPU core type should be %s", base_core_type); 4067 return; 4068 } 4069 4070 if (cc->core_id % smp_threads) { 4071 error_setg(errp, "invalid core id %d", cc->core_id); 4072 return; 4073 } 4074 4075 /* 4076 * In general we should have homogeneous threads-per-core, but old 4077 * (pre hotplug support) machine types allow the last core to have 4078 * reduced threads as a compatibility hack for when we allowed 4079 * total vcpus not a multiple of threads-per-core. 4080 */ 4081 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4082 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4083 smp_threads); 4084 return; 4085 } 4086 4087 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4088 if (!core_slot) { 4089 error_setg(errp, "core id %d out of range", cc->core_id); 4090 return; 4091 } 4092 4093 if (core_slot->cpu) { 4094 error_setg(errp, "core %d already populated", cc->core_id); 4095 return; 4096 } 4097 4098 numa_cpu_pre_plug(core_slot, dev, errp); 4099 } 4100 4101 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4102 void *fdt, int *fdt_start_offset, Error **errp) 4103 { 4104 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4105 int intc_phandle; 4106 4107 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4108 if (intc_phandle <= 0) { 4109 return -1; 4110 } 4111 4112 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4113 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4114 return -1; 4115 } 4116 4117 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4118 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4119 4120 return 0; 4121 } 4122 4123 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4124 Error **errp) 4125 { 4126 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4127 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4128 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4129 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4130 SpaprDrc *drc; 4131 4132 if (dev->hotplugged && !smc->dr_phb_enabled) { 4133 error_setg(errp, "PHB hotplug not supported for this machine"); 4134 return false; 4135 } 4136 4137 if (sphb->index == (uint32_t)-1) { 4138 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4139 return false; 4140 } 4141 4142 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4143 if (drc && drc->dev) { 4144 error_setg(errp, "PHB %d already attached", sphb->index); 4145 return false; 4146 } 4147 4148 /* 4149 * This will check that sphb->index doesn't exceed the maximum number of 4150 * PHBs for the current machine type. 4151 */ 4152 return 4153 smc->phb_placement(spapr, sphb->index, 4154 &sphb->buid, &sphb->io_win_addr, 4155 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4156 windows_supported, sphb->dma_liobn, 4157 errp); 4158 } 4159 4160 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4161 { 4162 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4163 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4164 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4165 SpaprDrc *drc; 4166 bool hotplugged = spapr_drc_hotplugged(dev); 4167 4168 if (!smc->dr_phb_enabled) { 4169 return; 4170 } 4171 4172 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4173 /* hotplug hooks should check it's enabled before getting this far */ 4174 assert(drc); 4175 4176 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4177 spapr_drc_attach(drc, dev); 4178 4179 if (hotplugged) { 4180 spapr_hotplug_req_add_by_index(drc); 4181 } else { 4182 spapr_drc_reset(drc); 4183 } 4184 } 4185 4186 void spapr_phb_release(DeviceState *dev) 4187 { 4188 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4189 4190 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4191 object_unparent(OBJECT(dev)); 4192 } 4193 4194 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4195 { 4196 qdev_unrealize(dev); 4197 } 4198 4199 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4200 DeviceState *dev, Error **errp) 4201 { 4202 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4203 SpaprDrc *drc; 4204 4205 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4206 assert(drc); 4207 4208 if (!spapr_drc_unplug_requested(drc)) { 4209 spapr_drc_unplug_request(drc); 4210 spapr_hotplug_req_remove_by_index(drc); 4211 } else { 4212 error_setg(errp, 4213 "PCI Host Bridge unplug already in progress for device %s", 4214 dev->id); 4215 } 4216 } 4217 4218 static 4219 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4220 Error **errp) 4221 { 4222 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4223 4224 if (spapr->tpm_proxy != NULL) { 4225 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4226 return false; 4227 } 4228 4229 return true; 4230 } 4231 4232 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4233 { 4234 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4235 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4236 4237 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4238 g_assert(spapr->tpm_proxy == NULL); 4239 4240 spapr->tpm_proxy = tpm_proxy; 4241 } 4242 4243 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4244 { 4245 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4246 4247 qdev_unrealize(dev); 4248 object_unparent(OBJECT(dev)); 4249 spapr->tpm_proxy = NULL; 4250 } 4251 4252 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4253 DeviceState *dev, Error **errp) 4254 { 4255 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4256 spapr_memory_plug(hotplug_dev, dev); 4257 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4258 spapr_core_plug(hotplug_dev, dev); 4259 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4260 spapr_phb_plug(hotplug_dev, dev); 4261 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4262 spapr_tpm_proxy_plug(hotplug_dev, dev); 4263 } 4264 } 4265 4266 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4267 DeviceState *dev, Error **errp) 4268 { 4269 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4270 spapr_memory_unplug(hotplug_dev, dev); 4271 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4272 spapr_core_unplug(hotplug_dev, dev); 4273 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4274 spapr_phb_unplug(hotplug_dev, dev); 4275 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4276 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4277 } 4278 } 4279 4280 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4281 { 4282 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4283 /* 4284 * CAS will process all pending unplug requests. 4285 * 4286 * HACK: a guest could theoretically have cleared all bits in OV5, 4287 * but none of the guests we care for do. 4288 */ 4289 spapr_ovec_empty(spapr->ov5_cas); 4290 } 4291 4292 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4293 DeviceState *dev, Error **errp) 4294 { 4295 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4296 MachineClass *mc = MACHINE_GET_CLASS(sms); 4297 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4298 4299 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4300 if (spapr_memory_hot_unplug_supported(sms)) { 4301 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4302 } else { 4303 error_setg(errp, "Memory hot unplug not supported for this guest"); 4304 } 4305 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4306 if (!mc->has_hotpluggable_cpus) { 4307 error_setg(errp, "CPU hot unplug not supported on this machine"); 4308 return; 4309 } 4310 spapr_core_unplug_request(hotplug_dev, dev, errp); 4311 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4312 if (!smc->dr_phb_enabled) { 4313 error_setg(errp, "PHB hot unplug not supported on this machine"); 4314 return; 4315 } 4316 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4317 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4318 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4319 } 4320 } 4321 4322 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4323 DeviceState *dev, Error **errp) 4324 { 4325 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4326 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4327 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4328 spapr_core_pre_plug(hotplug_dev, dev, errp); 4329 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4330 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4331 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4332 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4333 } 4334 } 4335 4336 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4337 DeviceState *dev) 4338 { 4339 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4340 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4341 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4342 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4343 return HOTPLUG_HANDLER(machine); 4344 } 4345 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4346 PCIDevice *pcidev = PCI_DEVICE(dev); 4347 PCIBus *root = pci_device_root_bus(pcidev); 4348 SpaprPhbState *phb = 4349 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4350 TYPE_SPAPR_PCI_HOST_BRIDGE); 4351 4352 if (phb) { 4353 return HOTPLUG_HANDLER(phb); 4354 } 4355 } 4356 return NULL; 4357 } 4358 4359 static CpuInstanceProperties 4360 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4361 { 4362 CPUArchId *core_slot; 4363 MachineClass *mc = MACHINE_GET_CLASS(machine); 4364 4365 /* make sure possible_cpu are initialized */ 4366 mc->possible_cpu_arch_ids(machine); 4367 /* get CPU core slot containing thread that matches cpu_index */ 4368 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4369 assert(core_slot); 4370 return core_slot->props; 4371 } 4372 4373 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4374 { 4375 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4376 } 4377 4378 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4379 { 4380 int i; 4381 unsigned int smp_threads = machine->smp.threads; 4382 unsigned int smp_cpus = machine->smp.cpus; 4383 const char *core_type; 4384 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4385 MachineClass *mc = MACHINE_GET_CLASS(machine); 4386 4387 if (!mc->has_hotpluggable_cpus) { 4388 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4389 } 4390 if (machine->possible_cpus) { 4391 assert(machine->possible_cpus->len == spapr_max_cores); 4392 return machine->possible_cpus; 4393 } 4394 4395 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4396 if (!core_type) { 4397 error_report("Unable to find sPAPR CPU Core definition"); 4398 exit(1); 4399 } 4400 4401 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4402 sizeof(CPUArchId) * spapr_max_cores); 4403 machine->possible_cpus->len = spapr_max_cores; 4404 for (i = 0; i < machine->possible_cpus->len; i++) { 4405 int core_id = i * smp_threads; 4406 4407 machine->possible_cpus->cpus[i].type = core_type; 4408 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4409 machine->possible_cpus->cpus[i].arch_id = core_id; 4410 machine->possible_cpus->cpus[i].props.has_core_id = true; 4411 machine->possible_cpus->cpus[i].props.core_id = core_id; 4412 } 4413 return machine->possible_cpus; 4414 } 4415 4416 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4417 uint64_t *buid, hwaddr *pio, 4418 hwaddr *mmio32, hwaddr *mmio64, 4419 unsigned n_dma, uint32_t *liobns, Error **errp) 4420 { 4421 /* 4422 * New-style PHB window placement. 4423 * 4424 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4425 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4426 * windows. 4427 * 4428 * Some guest kernels can't work with MMIO windows above 1<<46 4429 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4430 * 4431 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4432 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4433 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4434 * 1TiB 64-bit MMIO windows for each PHB. 4435 */ 4436 const uint64_t base_buid = 0x800000020000000ULL; 4437 int i; 4438 4439 /* Sanity check natural alignments */ 4440 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4441 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4442 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4443 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4444 /* Sanity check bounds */ 4445 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4446 SPAPR_PCI_MEM32_WIN_SIZE); 4447 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4448 SPAPR_PCI_MEM64_WIN_SIZE); 4449 4450 if (index >= SPAPR_MAX_PHBS) { 4451 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4452 SPAPR_MAX_PHBS - 1); 4453 return false; 4454 } 4455 4456 *buid = base_buid + index; 4457 for (i = 0; i < n_dma; ++i) { 4458 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4459 } 4460 4461 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4462 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4463 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4464 return true; 4465 } 4466 4467 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4468 { 4469 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4470 4471 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4472 } 4473 4474 static void spapr_ics_resend(XICSFabric *dev) 4475 { 4476 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4477 4478 ics_resend(spapr->ics); 4479 } 4480 4481 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4482 { 4483 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4484 4485 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4486 } 4487 4488 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4489 Monitor *mon) 4490 { 4491 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4492 4493 spapr_irq_print_info(spapr, mon); 4494 monitor_printf(mon, "irqchip: %s\n", 4495 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4496 } 4497 4498 /* 4499 * This is a XIVE only operation 4500 */ 4501 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4502 uint8_t nvt_blk, uint32_t nvt_idx, 4503 bool cam_ignore, uint8_t priority, 4504 uint32_t logic_serv, XiveTCTXMatch *match) 4505 { 4506 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4507 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4508 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4509 int count; 4510 4511 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4512 priority, logic_serv, match); 4513 if (count < 0) { 4514 return count; 4515 } 4516 4517 /* 4518 * When we implement the save and restore of the thread interrupt 4519 * contexts in the enter/exit CPU handlers of the machine and the 4520 * escalations in QEMU, we should be able to handle non dispatched 4521 * vCPUs. 4522 * 4523 * Until this is done, the sPAPR machine should find at least one 4524 * matching context always. 4525 */ 4526 if (count == 0) { 4527 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4528 nvt_blk, nvt_idx); 4529 } 4530 4531 return count; 4532 } 4533 4534 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4535 { 4536 return cpu->vcpu_id; 4537 } 4538 4539 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4540 { 4541 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4542 MachineState *ms = MACHINE(spapr); 4543 int vcpu_id; 4544 4545 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4546 4547 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4548 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4549 error_append_hint(errp, "Adjust the number of cpus to %d " 4550 "or try to raise the number of threads per core\n", 4551 vcpu_id * ms->smp.threads / spapr->vsmt); 4552 return false; 4553 } 4554 4555 cpu->vcpu_id = vcpu_id; 4556 return true; 4557 } 4558 4559 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4560 { 4561 CPUState *cs; 4562 4563 CPU_FOREACH(cs) { 4564 PowerPCCPU *cpu = POWERPC_CPU(cs); 4565 4566 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4567 return cpu; 4568 } 4569 } 4570 4571 return NULL; 4572 } 4573 4574 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4575 { 4576 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4577 4578 return spapr_cpu->in_nested; 4579 } 4580 4581 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4582 { 4583 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4584 4585 /* These are only called by TCG, KVM maintains dispatch state */ 4586 4587 spapr_cpu->prod = false; 4588 if (spapr_cpu->vpa_addr) { 4589 CPUState *cs = CPU(cpu); 4590 uint32_t dispatch; 4591 4592 dispatch = ldl_be_phys(cs->as, 4593 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4594 dispatch++; 4595 if ((dispatch & 1) != 0) { 4596 qemu_log_mask(LOG_GUEST_ERROR, 4597 "VPA: incorrect dispatch counter value for " 4598 "dispatched partition %u, correcting.\n", dispatch); 4599 dispatch++; 4600 } 4601 stl_be_phys(cs->as, 4602 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4603 } 4604 } 4605 4606 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4607 { 4608 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4609 4610 if (spapr_cpu->vpa_addr) { 4611 CPUState *cs = CPU(cpu); 4612 uint32_t dispatch; 4613 4614 dispatch = ldl_be_phys(cs->as, 4615 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4616 dispatch++; 4617 if ((dispatch & 1) != 1) { 4618 qemu_log_mask(LOG_GUEST_ERROR, 4619 "VPA: incorrect dispatch counter value for " 4620 "preempted partition %u, correcting.\n", dispatch); 4621 dispatch++; 4622 } 4623 stl_be_phys(cs->as, 4624 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4625 } 4626 } 4627 4628 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4629 { 4630 MachineClass *mc = MACHINE_CLASS(oc); 4631 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4632 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4633 NMIClass *nc = NMI_CLASS(oc); 4634 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4635 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4636 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4637 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4638 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4639 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4640 4641 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4642 mc->ignore_boot_device_suffixes = true; 4643 4644 /* 4645 * We set up the default / latest behaviour here. The class_init 4646 * functions for the specific versioned machine types can override 4647 * these details for backwards compatibility 4648 */ 4649 mc->init = spapr_machine_init; 4650 mc->reset = spapr_machine_reset; 4651 mc->block_default_type = IF_SCSI; 4652 4653 /* 4654 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4655 * In TCG the limit is restricted by the range of CPU IPIs available. 4656 */ 4657 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4658 4659 mc->no_parallel = 1; 4660 mc->default_boot_order = ""; 4661 mc->default_ram_size = 512 * MiB; 4662 mc->default_ram_id = "ppc_spapr.ram"; 4663 mc->default_display = "std"; 4664 mc->kvm_type = spapr_kvm_type; 4665 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4666 mc->pci_allow_0_address = true; 4667 assert(!mc->get_hotplug_handler); 4668 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4669 hc->pre_plug = spapr_machine_device_pre_plug; 4670 hc->plug = spapr_machine_device_plug; 4671 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4672 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4673 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4674 hc->unplug_request = spapr_machine_device_unplug_request; 4675 hc->unplug = spapr_machine_device_unplug; 4676 4677 smc->dr_lmb_enabled = true; 4678 smc->update_dt_enabled = true; 4679 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4680 mc->has_hotpluggable_cpus = true; 4681 mc->nvdimm_supported = true; 4682 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4683 fwc->get_dev_path = spapr_get_fw_dev_path; 4684 nc->nmi_monitor_handler = spapr_nmi; 4685 smc->phb_placement = spapr_phb_placement; 4686 vhc->cpu_in_nested = spapr_cpu_in_nested; 4687 vhc->deliver_hv_excp = spapr_exit_nested; 4688 vhc->hypercall = emulate_spapr_hypercall; 4689 vhc->hpt_mask = spapr_hpt_mask; 4690 vhc->map_hptes = spapr_map_hptes; 4691 vhc->unmap_hptes = spapr_unmap_hptes; 4692 vhc->hpte_set_c = spapr_hpte_set_c; 4693 vhc->hpte_set_r = spapr_hpte_set_r; 4694 vhc->get_pate = spapr_get_pate; 4695 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4696 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4697 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4698 xic->ics_get = spapr_ics_get; 4699 xic->ics_resend = spapr_ics_resend; 4700 xic->icp_get = spapr_icp_get; 4701 ispc->print_info = spapr_pic_print_info; 4702 /* Force NUMA node memory size to be a multiple of 4703 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4704 * in which LMBs are represented and hot-added 4705 */ 4706 mc->numa_mem_align_shift = 28; 4707 mc->auto_enable_numa = true; 4708 4709 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4710 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4711 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4712 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4713 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4714 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4715 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4716 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4717 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4718 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4719 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4720 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4721 4722 /* 4723 * This cap specifies whether the AIL 3 mode for 4724 * H_SET_RESOURCE is supported. The default is modified 4725 * by default_caps_with_cpu(). 4726 */ 4727 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4728 spapr_caps_add_properties(smc); 4729 smc->irq = &spapr_irq_dual; 4730 smc->dr_phb_enabled = true; 4731 smc->linux_pci_probe = true; 4732 smc->smp_threads_vsmt = true; 4733 smc->nr_xirqs = SPAPR_NR_XIRQS; 4734 xfc->match_nvt = spapr_match_nvt; 4735 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4736 vmc->quiesce = spapr_vof_quiesce; 4737 vmc->setprop = spapr_vof_setprop; 4738 } 4739 4740 static const TypeInfo spapr_machine_info = { 4741 .name = TYPE_SPAPR_MACHINE, 4742 .parent = TYPE_MACHINE, 4743 .abstract = true, 4744 .instance_size = sizeof(SpaprMachineState), 4745 .instance_init = spapr_instance_init, 4746 .instance_finalize = spapr_machine_finalizefn, 4747 .class_size = sizeof(SpaprMachineClass), 4748 .class_init = spapr_machine_class_init, 4749 .interfaces = (InterfaceInfo[]) { 4750 { TYPE_FW_PATH_PROVIDER }, 4751 { TYPE_NMI }, 4752 { TYPE_HOTPLUG_HANDLER }, 4753 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4754 { TYPE_XICS_FABRIC }, 4755 { TYPE_INTERRUPT_STATS_PROVIDER }, 4756 { TYPE_XIVE_FABRIC }, 4757 { TYPE_VOF_MACHINE_IF }, 4758 { } 4759 }, 4760 }; 4761 4762 static void spapr_machine_latest_class_options(MachineClass *mc) 4763 { 4764 mc->alias = "pseries"; 4765 mc->is_default = true; 4766 } 4767 4768 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4769 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4770 void *data) \ 4771 { \ 4772 MachineClass *mc = MACHINE_CLASS(oc); \ 4773 spapr_machine_##suffix##_class_options(mc); \ 4774 if (latest) { \ 4775 spapr_machine_latest_class_options(mc); \ 4776 } \ 4777 } \ 4778 static const TypeInfo spapr_machine_##suffix##_info = { \ 4779 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4780 .parent = TYPE_SPAPR_MACHINE, \ 4781 .class_init = spapr_machine_##suffix##_class_init, \ 4782 }; \ 4783 static void spapr_machine_register_##suffix(void) \ 4784 { \ 4785 type_register(&spapr_machine_##suffix##_info); \ 4786 } \ 4787 type_init(spapr_machine_register_##suffix) 4788 4789 /* 4790 * pseries-9.0 4791 */ 4792 static void spapr_machine_9_0_class_options(MachineClass *mc) 4793 { 4794 /* Defaults for the latest behaviour inherited from the base class */ 4795 } 4796 4797 DEFINE_SPAPR_MACHINE(9_0, "9.0", true); 4798 4799 /* 4800 * pseries-8.2 4801 */ 4802 static void spapr_machine_8_2_class_options(MachineClass *mc) 4803 { 4804 spapr_machine_9_0_class_options(mc); 4805 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4806 } 4807 4808 DEFINE_SPAPR_MACHINE(8_2, "8.2", false); 4809 4810 /* 4811 * pseries-8.1 4812 */ 4813 static void spapr_machine_8_1_class_options(MachineClass *mc) 4814 { 4815 spapr_machine_8_2_class_options(mc); 4816 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4817 } 4818 4819 DEFINE_SPAPR_MACHINE(8_1, "8.1", false); 4820 4821 /* 4822 * pseries-8.0 4823 */ 4824 static void spapr_machine_8_0_class_options(MachineClass *mc) 4825 { 4826 spapr_machine_8_1_class_options(mc); 4827 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4828 } 4829 4830 DEFINE_SPAPR_MACHINE(8_0, "8.0", false); 4831 4832 /* 4833 * pseries-7.2 4834 */ 4835 static void spapr_machine_7_2_class_options(MachineClass *mc) 4836 { 4837 spapr_machine_8_0_class_options(mc); 4838 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4839 } 4840 4841 DEFINE_SPAPR_MACHINE(7_2, "7.2", false); 4842 4843 /* 4844 * pseries-7.1 4845 */ 4846 static void spapr_machine_7_1_class_options(MachineClass *mc) 4847 { 4848 spapr_machine_7_2_class_options(mc); 4849 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4850 } 4851 4852 DEFINE_SPAPR_MACHINE(7_1, "7.1", false); 4853 4854 /* 4855 * pseries-7.0 4856 */ 4857 static void spapr_machine_7_0_class_options(MachineClass *mc) 4858 { 4859 spapr_machine_7_1_class_options(mc); 4860 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4861 } 4862 4863 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4864 4865 /* 4866 * pseries-6.2 4867 */ 4868 static void spapr_machine_6_2_class_options(MachineClass *mc) 4869 { 4870 spapr_machine_7_0_class_options(mc); 4871 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4872 } 4873 4874 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4875 4876 /* 4877 * pseries-6.1 4878 */ 4879 static void spapr_machine_6_1_class_options(MachineClass *mc) 4880 { 4881 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4882 4883 spapr_machine_6_2_class_options(mc); 4884 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4885 smc->pre_6_2_numa_affinity = true; 4886 mc->smp_props.prefer_sockets = true; 4887 } 4888 4889 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4890 4891 /* 4892 * pseries-6.0 4893 */ 4894 static void spapr_machine_6_0_class_options(MachineClass *mc) 4895 { 4896 spapr_machine_6_1_class_options(mc); 4897 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4898 } 4899 4900 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4901 4902 /* 4903 * pseries-5.2 4904 */ 4905 static void spapr_machine_5_2_class_options(MachineClass *mc) 4906 { 4907 spapr_machine_6_0_class_options(mc); 4908 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4909 } 4910 4911 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4912 4913 /* 4914 * pseries-5.1 4915 */ 4916 static void spapr_machine_5_1_class_options(MachineClass *mc) 4917 { 4918 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4919 4920 spapr_machine_5_2_class_options(mc); 4921 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4922 smc->pre_5_2_numa_associativity = true; 4923 } 4924 4925 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4926 4927 /* 4928 * pseries-5.0 4929 */ 4930 static void spapr_machine_5_0_class_options(MachineClass *mc) 4931 { 4932 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4933 static GlobalProperty compat[] = { 4934 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4935 }; 4936 4937 spapr_machine_5_1_class_options(mc); 4938 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4939 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4940 mc->numa_mem_supported = true; 4941 smc->pre_5_1_assoc_refpoints = true; 4942 } 4943 4944 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4945 4946 /* 4947 * pseries-4.2 4948 */ 4949 static void spapr_machine_4_2_class_options(MachineClass *mc) 4950 { 4951 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4952 4953 spapr_machine_5_0_class_options(mc); 4954 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4955 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4956 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4957 smc->rma_limit = 16 * GiB; 4958 mc->nvdimm_supported = false; 4959 } 4960 4961 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4962 4963 /* 4964 * pseries-4.1 4965 */ 4966 static void spapr_machine_4_1_class_options(MachineClass *mc) 4967 { 4968 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4969 static GlobalProperty compat[] = { 4970 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4971 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4972 }; 4973 4974 spapr_machine_4_2_class_options(mc); 4975 smc->linux_pci_probe = false; 4976 smc->smp_threads_vsmt = false; 4977 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4978 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4979 } 4980 4981 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4982 4983 /* 4984 * pseries-4.0 4985 */ 4986 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4987 uint64_t *buid, hwaddr *pio, 4988 hwaddr *mmio32, hwaddr *mmio64, 4989 unsigned n_dma, uint32_t *liobns, Error **errp) 4990 { 4991 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4992 liobns, errp)) { 4993 return false; 4994 } 4995 return true; 4996 } 4997 static void spapr_machine_4_0_class_options(MachineClass *mc) 4998 { 4999 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5000 5001 spapr_machine_4_1_class_options(mc); 5002 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 5003 smc->phb_placement = phb_placement_4_0; 5004 smc->irq = &spapr_irq_xics; 5005 smc->pre_4_1_migration = true; 5006 } 5007 5008 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 5009 5010 /* 5011 * pseries-3.1 5012 */ 5013 static void spapr_machine_3_1_class_options(MachineClass *mc) 5014 { 5015 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5016 5017 spapr_machine_4_0_class_options(mc); 5018 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 5019 5020 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 5021 smc->update_dt_enabled = false; 5022 smc->dr_phb_enabled = false; 5023 smc->broken_host_serial_model = true; 5024 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5025 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5026 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5027 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5028 } 5029 5030 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 5031 5032 /* 5033 * pseries-3.0 5034 */ 5035 5036 static void spapr_machine_3_0_class_options(MachineClass *mc) 5037 { 5038 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5039 5040 spapr_machine_3_1_class_options(mc); 5041 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5042 5043 smc->legacy_irq_allocation = true; 5044 smc->nr_xirqs = 0x400; 5045 smc->irq = &spapr_irq_xics_legacy; 5046 } 5047 5048 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 5049 5050 /* 5051 * pseries-2.12 5052 */ 5053 static void spapr_machine_2_12_class_options(MachineClass *mc) 5054 { 5055 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5056 static GlobalProperty compat[] = { 5057 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 5058 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 5059 }; 5060 5061 spapr_machine_3_0_class_options(mc); 5062 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 5063 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5064 5065 /* We depend on kvm_enabled() to choose a default value for the 5066 * hpt-max-page-size capability. Of course we can't do it here 5067 * because this is too early and the HW accelerator isn't initialized 5068 * yet. Postpone this to machine init (see default_caps_with_cpu()). 5069 */ 5070 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 5071 } 5072 5073 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 5074 5075 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 5076 { 5077 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5078 5079 spapr_machine_2_12_class_options(mc); 5080 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 5081 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 5082 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 5083 } 5084 5085 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 5086 5087 /* 5088 * pseries-2.11 5089 */ 5090 5091 static void spapr_machine_2_11_class_options(MachineClass *mc) 5092 { 5093 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5094 5095 spapr_machine_2_12_class_options(mc); 5096 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5097 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5098 mc->deprecation_reason = "old and not maintained - use a 2.12+ version"; 5099 } 5100 5101 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 5102 5103 /* 5104 * pseries-2.10 5105 */ 5106 5107 static void spapr_machine_2_10_class_options(MachineClass *mc) 5108 { 5109 spapr_machine_2_11_class_options(mc); 5110 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5111 } 5112 5113 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 5114 5115 /* 5116 * pseries-2.9 5117 */ 5118 5119 static void spapr_machine_2_9_class_options(MachineClass *mc) 5120 { 5121 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5122 static GlobalProperty compat[] = { 5123 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5124 }; 5125 5126 spapr_machine_2_10_class_options(mc); 5127 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5128 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5129 smc->pre_2_10_has_unused_icps = true; 5130 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5131 } 5132 5133 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5134 5135 /* 5136 * pseries-2.8 5137 */ 5138 5139 static void spapr_machine_2_8_class_options(MachineClass *mc) 5140 { 5141 static GlobalProperty compat[] = { 5142 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5143 }; 5144 5145 spapr_machine_2_9_class_options(mc); 5146 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5147 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5148 mc->numa_mem_align_shift = 23; 5149 } 5150 5151 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5152 5153 /* 5154 * pseries-2.7 5155 */ 5156 5157 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5158 uint64_t *buid, hwaddr *pio, 5159 hwaddr *mmio32, hwaddr *mmio64, 5160 unsigned n_dma, uint32_t *liobns, Error **errp) 5161 { 5162 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5163 const uint64_t base_buid = 0x800000020000000ULL; 5164 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5165 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5166 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5167 const uint32_t max_index = 255; 5168 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5169 5170 uint64_t ram_top = MACHINE(spapr)->ram_size; 5171 hwaddr phb0_base, phb_base; 5172 int i; 5173 5174 /* Do we have device memory? */ 5175 if (MACHINE(spapr)->device_memory) { 5176 /* Can't just use maxram_size, because there may be an 5177 * alignment gap between normal and device memory regions 5178 */ 5179 ram_top = MACHINE(spapr)->device_memory->base + 5180 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5181 } 5182 5183 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5184 5185 if (index > max_index) { 5186 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5187 max_index); 5188 return false; 5189 } 5190 5191 *buid = base_buid + index; 5192 for (i = 0; i < n_dma; ++i) { 5193 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5194 } 5195 5196 phb_base = phb0_base + index * phb_spacing; 5197 *pio = phb_base + pio_offset; 5198 *mmio32 = phb_base + mmio_offset; 5199 /* 5200 * We don't set the 64-bit MMIO window, relying on the PHB's 5201 * fallback behaviour of automatically splitting a large "32-bit" 5202 * window into contiguous 32-bit and 64-bit windows 5203 */ 5204 5205 return true; 5206 } 5207 5208 static void spapr_machine_2_7_class_options(MachineClass *mc) 5209 { 5210 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5211 static GlobalProperty compat[] = { 5212 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5213 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5214 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5215 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5216 }; 5217 5218 spapr_machine_2_8_class_options(mc); 5219 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5220 mc->default_machine_opts = "modern-hotplug-events=off"; 5221 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5222 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5223 smc->phb_placement = phb_placement_2_7; 5224 } 5225 5226 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5227 5228 /* 5229 * pseries-2.6 5230 */ 5231 5232 static void spapr_machine_2_6_class_options(MachineClass *mc) 5233 { 5234 static GlobalProperty compat[] = { 5235 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5236 }; 5237 5238 spapr_machine_2_7_class_options(mc); 5239 mc->has_hotpluggable_cpus = false; 5240 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5241 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5242 } 5243 5244 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5245 5246 /* 5247 * pseries-2.5 5248 */ 5249 5250 static void spapr_machine_2_5_class_options(MachineClass *mc) 5251 { 5252 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5253 static GlobalProperty compat[] = { 5254 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5255 }; 5256 5257 spapr_machine_2_6_class_options(mc); 5258 smc->use_ohci_by_default = true; 5259 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5260 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5261 } 5262 5263 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5264 5265 /* 5266 * pseries-2.4 5267 */ 5268 5269 static void spapr_machine_2_4_class_options(MachineClass *mc) 5270 { 5271 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5272 5273 spapr_machine_2_5_class_options(mc); 5274 smc->dr_lmb_enabled = false; 5275 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5276 } 5277 5278 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5279 5280 /* 5281 * pseries-2.3 5282 */ 5283 5284 static void spapr_machine_2_3_class_options(MachineClass *mc) 5285 { 5286 static GlobalProperty compat[] = { 5287 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5288 }; 5289 spapr_machine_2_4_class_options(mc); 5290 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5291 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5292 } 5293 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5294 5295 /* 5296 * pseries-2.2 5297 */ 5298 5299 static void spapr_machine_2_2_class_options(MachineClass *mc) 5300 { 5301 static GlobalProperty compat[] = { 5302 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5303 }; 5304 5305 spapr_machine_2_3_class_options(mc); 5306 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5307 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5308 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5309 } 5310 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5311 5312 /* 5313 * pseries-2.1 5314 */ 5315 5316 static void spapr_machine_2_1_class_options(MachineClass *mc) 5317 { 5318 spapr_machine_2_2_class_options(mc); 5319 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5320 } 5321 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5322 5323 static void spapr_machine_register_types(void) 5324 { 5325 type_register_static(&spapr_machine_info); 5326 } 5327 5328 type_init(spapr_machine_register_types) 5329