1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2017 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "hw/rtc/m48t59.h" 29 #include "hw/char/serial.h" 30 #include "hw/block/fdc.h" 31 #include "net/net.h" 32 #include "hw/isa/isa.h" 33 #include "hw/pci/pci.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/boards.h" 37 #include "qapi/error.h" 38 #include "qemu/error-report.h" 39 #include "qemu/log.h" 40 #include "hw/loader.h" 41 #include "hw/rtc/mc146818rtc.h" 42 #include "hw/isa/pc87312.h" 43 #include "hw/qdev-properties.h" 44 #include "sysemu/arch_init.h" 45 #include "sysemu/kvm.h" 46 #include "sysemu/reset.h" 47 #include "exec/address-spaces.h" 48 #include "trace.h" 49 #include "elf.h" 50 #include "qemu/units.h" 51 #include "kvm_ppc.h" 52 53 /* SMP is not enabled, for now */ 54 #define MAX_CPUS 1 55 56 #define MAX_IDE_BUS 2 57 58 #define CFG_ADDR 0xf0000510 59 60 #define KERNEL_LOAD_ADDR 0x01000000 61 #define INITRD_LOAD_ADDR 0x01800000 62 63 #define NVRAM_SIZE 0x2000 64 65 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 66 Error **errp) 67 { 68 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 69 } 70 71 static void ppc_prep_reset(void *opaque) 72 { 73 PowerPCCPU *cpu = opaque; 74 75 cpu_reset(CPU(cpu)); 76 } 77 78 79 /*****************************************************************************/ 80 /* NVRAM helpers */ 81 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 82 { 83 NvramClass *k = NVRAM_GET_CLASS(nvram); 84 return (k->read)(nvram, addr); 85 } 86 87 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 88 { 89 NvramClass *k = NVRAM_GET_CLASS(nvram); 90 (k->write)(nvram, addr, val); 91 } 92 93 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 94 { 95 nvram_write(nvram, addr, value); 96 } 97 98 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 99 { 100 return nvram_read(nvram, addr); 101 } 102 103 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 104 { 105 nvram_write(nvram, addr, value >> 8); 106 nvram_write(nvram, addr + 1, value & 0xFF); 107 } 108 109 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 110 { 111 uint16_t tmp; 112 113 tmp = nvram_read(nvram, addr) << 8; 114 tmp |= nvram_read(nvram, addr + 1); 115 116 return tmp; 117 } 118 119 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 120 { 121 nvram_write(nvram, addr, value >> 24); 122 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 123 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 124 nvram_write(nvram, addr + 3, value & 0xFF); 125 } 126 127 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 128 uint32_t max) 129 { 130 int i; 131 132 for (i = 0; i < max && str[i] != '\0'; i++) { 133 nvram_write(nvram, addr + i, str[i]); 134 } 135 nvram_write(nvram, addr + i, str[i]); 136 nvram_write(nvram, addr + max - 1, '\0'); 137 } 138 139 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 140 { 141 uint16_t tmp; 142 uint16_t pd, pd1, pd2; 143 144 tmp = prev >> 8; 145 pd = prev ^ value; 146 pd1 = pd & 0x000F; 147 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 148 tmp ^= (pd1 << 3) | (pd1 << 8); 149 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 150 151 return tmp; 152 } 153 154 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 155 { 156 uint32_t i; 157 uint16_t crc = 0xFFFF; 158 int odd; 159 160 odd = count & 1; 161 count &= ~1; 162 for (i = 0; i != count; i++) { 163 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 164 } 165 if (odd) { 166 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 167 } 168 169 return crc; 170 } 171 172 #define CMDLINE_ADDR 0x017ff000 173 174 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 175 const char *arch, 176 uint32_t RAM_size, int boot_device, 177 uint32_t kernel_image, uint32_t kernel_size, 178 const char *cmdline, 179 uint32_t initrd_image, uint32_t initrd_size, 180 uint32_t NVRAM_image, 181 int width, int height, int depth) 182 { 183 uint16_t crc; 184 185 /* Set parameters for Open Hack'Ware BIOS */ 186 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 187 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 188 NVRAM_set_word(nvram, 0x14, NVRAM_size); 189 NVRAM_set_string(nvram, 0x20, arch, 16); 190 NVRAM_set_lword(nvram, 0x30, RAM_size); 191 NVRAM_set_byte(nvram, 0x34, boot_device); 192 NVRAM_set_lword(nvram, 0x38, kernel_image); 193 NVRAM_set_lword(nvram, 0x3C, kernel_size); 194 if (cmdline) { 195 /* XXX: put the cmdline in NVRAM too ? */ 196 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 197 cmdline); 198 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 199 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 200 } else { 201 NVRAM_set_lword(nvram, 0x40, 0); 202 NVRAM_set_lword(nvram, 0x44, 0); 203 } 204 NVRAM_set_lword(nvram, 0x48, initrd_image); 205 NVRAM_set_lword(nvram, 0x4C, initrd_size); 206 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 207 208 NVRAM_set_word(nvram, 0x54, width); 209 NVRAM_set_word(nvram, 0x56, height); 210 NVRAM_set_word(nvram, 0x58, depth); 211 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 212 NVRAM_set_word(nvram, 0xFC, crc); 213 214 return 0; 215 } 216 217 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 218 { 219 uint16_t checksum = *(uint16_t *)opaque; 220 ISADevice *rtc; 221 222 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 223 rtc = ISA_DEVICE(dev); 224 rtc_set_memory(rtc, 0x2e, checksum & 0xff); 225 rtc_set_memory(rtc, 0x3e, checksum & 0xff); 226 rtc_set_memory(rtc, 0x2f, checksum >> 8); 227 rtc_set_memory(rtc, 0x3f, checksum >> 8); 228 229 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), 230 "date"); 231 } 232 return 0; 233 } 234 235 static void ibm_40p_init(MachineState *machine) 236 { 237 const char *bios_name = machine->firmware ?: "openbios-ppc"; 238 CPUPPCState *env = NULL; 239 uint16_t cmos_checksum; 240 PowerPCCPU *cpu; 241 DeviceState *dev, *i82378_dev; 242 SysBusDevice *pcihost, *s; 243 Nvram *m48t59 = NULL; 244 PCIBus *pci_bus; 245 ISADevice *isa_dev; 246 ISABus *isa_bus; 247 void *fw_cfg; 248 int i; 249 uint32_t kernel_base = 0, initrd_base = 0; 250 long kernel_size = 0, initrd_size = 0; 251 char boot_device; 252 253 /* init CPU */ 254 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 255 env = &cpu->env; 256 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 257 error_report("only 6xx bus is supported on this machine"); 258 exit(1); 259 } 260 261 if (env->flags & POWERPC_FLAG_RTC_CLK) { 262 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 263 cpu_ppc_tb_init(env, 7812500UL); 264 } else { 265 /* Set time-base frequency to 100 Mhz */ 266 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 267 } 268 qemu_register_reset(ppc_prep_reset, cpu); 269 270 /* PCI host */ 271 dev = qdev_new("raven-pcihost"); 272 qdev_prop_set_string(dev, "bios-name", bios_name); 273 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 274 pcihost = SYS_BUS_DEVICE(dev); 275 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); 276 sysbus_realize_and_unref(pcihost, &error_fatal); 277 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 278 if (!pci_bus) { 279 error_report("could not create PCI host controller"); 280 exit(1); 281 } 282 283 /* PCI -> ISA bridge */ 284 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); 285 qdev_connect_gpio_out(i82378_dev, 0, 286 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 287 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); 288 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); 289 290 /* Memory controller */ 291 isa_dev = isa_new("rs6000-mc"); 292 dev = DEVICE(isa_dev); 293 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); 294 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 295 296 /* RTC */ 297 isa_dev = isa_new(TYPE_MC146818_RTC); 298 dev = DEVICE(isa_dev); 299 qdev_prop_set_int32(dev, "base_year", 1900); 300 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 301 302 /* initialize CMOS checksums */ 303 cmos_checksum = 0x6aa9; 304 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, 305 &cmos_checksum); 306 307 /* add some more devices */ 308 if (defaults_enabled()) { 309 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); 310 311 isa_dev = isa_new("cs4231a"); 312 dev = DEVICE(isa_dev); 313 qdev_prop_set_uint32(dev, "iobase", 0x830); 314 qdev_prop_set_uint32(dev, "irq", 10); 315 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 316 317 isa_dev = isa_new("pc87312"); 318 dev = DEVICE(isa_dev); 319 qdev_prop_set_uint32(dev, "config", 12); 320 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 321 322 isa_dev = isa_new("prep-systemio"); 323 dev = DEVICE(isa_dev); 324 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); 325 qdev_prop_set_uint32(dev, "equipment", 0xc0); 326 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 327 328 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), 329 "lsi53c810")); 330 lsi53c8xx_handle_legacy_cmdline(dev); 331 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); 332 333 /* XXX: s3-trio at PCI_DEVFN(2, 0) */ 334 pci_vga_init(pci_bus); 335 336 for (i = 0; i < nb_nics; i++) { 337 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", 338 i == 0 ? "3" : NULL); 339 } 340 } 341 342 /* Prepare firmware configuration for OpenBIOS */ 343 dev = qdev_new(TYPE_FW_CFG_MEM); 344 fw_cfg = FW_CFG(dev); 345 qdev_prop_set_uint32(dev, "data_width", 1); 346 qdev_prop_set_bit(dev, "dma_enabled", false); 347 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 348 OBJECT(fw_cfg)); 349 s = SYS_BUS_DEVICE(dev); 350 sysbus_realize_and_unref(s, &error_fatal); 351 sysbus_mmio_map(s, 0, CFG_ADDR); 352 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 353 354 if (machine->kernel_filename) { 355 /* load kernel */ 356 kernel_base = KERNEL_LOAD_ADDR; 357 kernel_size = load_image_targphys(machine->kernel_filename, 358 kernel_base, 359 machine->ram_size - kernel_base); 360 if (kernel_size < 0) { 361 error_report("could not load kernel '%s'", 362 machine->kernel_filename); 363 exit(1); 364 } 365 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 366 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 367 /* load initrd */ 368 if (machine->initrd_filename) { 369 initrd_base = INITRD_LOAD_ADDR; 370 initrd_size = load_image_targphys(machine->initrd_filename, 371 initrd_base, 372 machine->ram_size - initrd_base); 373 if (initrd_size < 0) { 374 error_report("could not load initial ram disk '%s'", 375 machine->initrd_filename); 376 exit(1); 377 } 378 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 379 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 380 } 381 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 382 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 383 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 384 machine->kernel_cmdline); 385 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 386 machine->kernel_cmdline); 387 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 388 strlen(machine->kernel_cmdline) + 1); 389 } 390 boot_device = 'm'; 391 } else { 392 boot_device = machine->boot_order[0]; 393 } 394 395 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 396 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 397 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); 398 399 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 400 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 401 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 402 403 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 404 if (kvm_enabled()) { 405 uint8_t *hypercall; 406 407 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 408 hypercall = g_malloc(16); 409 kvmppc_get_hypercall(env, hypercall, 16); 410 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 411 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 412 } else { 413 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); 414 } 415 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); 416 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 417 418 /* Prepare firmware configuration for Open Hack'Ware */ 419 if (m48t59) { 420 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size, 421 boot_device, 422 kernel_base, kernel_size, 423 machine->kernel_cmdline, 424 initrd_base, initrd_size, 425 /* XXX: need an option to load a NVRAM image */ 426 0, 427 graphic_width, graphic_height, graphic_depth); 428 } 429 } 430 431 static void ibm_40p_machine_init(MachineClass *mc) 432 { 433 mc->desc = "IBM RS/6000 7020 (40p)", 434 mc->init = ibm_40p_init; 435 mc->max_cpus = 1; 436 mc->default_ram_size = 128 * MiB; 437 mc->block_default_type = IF_SCSI; 438 mc->default_boot_order = "c"; 439 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); 440 mc->default_display = "std"; 441 } 442 443 DEFINE_MACHINE("40p", ibm_40p_machine_init) 444