1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw.h" 25 #include "nvram.h" 26 #include "pc.h" 27 #include "serial.h" 28 #include "fdc.h" 29 #include "net.h" 30 #include "sysemu.h" 31 #include "isa.h" 32 #include "pci/pci.h" 33 #include "pci/pci_host.h" 34 #include "ppc.h" 35 #include "boards.h" 36 #include "qemu-log.h" 37 #include "ide.h" 38 #include "loader.h" 39 #include "mc146818rtc.h" 40 #include "blockdev.h" 41 #include "arch_init.h" 42 #include "exec-memory.h" 43 44 //#define HARD_DEBUG_PPC_IO 45 //#define DEBUG_PPC_IO 46 47 /* SMP is not enabled, for now */ 48 #define MAX_CPUS 1 49 50 #define MAX_IDE_BUS 2 51 52 #define BIOS_SIZE (1024 * 1024) 53 #define BIOS_FILENAME "ppc_rom.bin" 54 #define KERNEL_LOAD_ADDR 0x01000000 55 #define INITRD_LOAD_ADDR 0x01800000 56 57 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) 58 #define DEBUG_PPC_IO 59 #endif 60 61 #if defined (HARD_DEBUG_PPC_IO) 62 #define PPC_IO_DPRINTF(fmt, ...) \ 63 do { \ 64 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ 65 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ 66 } else { \ 67 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ 68 } \ 69 } while (0) 70 #elif defined (DEBUG_PPC_IO) 71 #define PPC_IO_DPRINTF(fmt, ...) \ 72 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) 73 #else 74 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) 75 #endif 76 77 /* Constants for devices init */ 78 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 79 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 80 static const int ide_irq[2] = { 13, 13 }; 81 82 #define NE2000_NB_MAX 6 83 84 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 85 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 86 87 /* ISA IO ports bridge */ 88 #define PPC_IO_BASE 0x80000000 89 90 /* PowerPC control and status registers */ 91 #if 0 // Not used 92 static struct { 93 /* IDs */ 94 uint32_t veni_devi; 95 uint32_t revi; 96 /* Control and status */ 97 uint32_t gcsr; 98 uint32_t xcfr; 99 uint32_t ct32; 100 uint32_t mcsr; 101 /* General purpose registers */ 102 uint32_t gprg[6]; 103 /* Exceptions */ 104 uint32_t feen; 105 uint32_t fest; 106 uint32_t fema; 107 uint32_t fecl; 108 uint32_t eeen; 109 uint32_t eest; 110 uint32_t eecl; 111 uint32_t eeint; 112 uint32_t eemck0; 113 uint32_t eemck1; 114 /* Error diagnostic */ 115 } XCSR; 116 117 static void PPC_XCSR_writeb (void *opaque, 118 hwaddr addr, uint32_t value) 119 { 120 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 121 value); 122 } 123 124 static void PPC_XCSR_writew (void *opaque, 125 hwaddr addr, uint32_t value) 126 { 127 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 128 value); 129 } 130 131 static void PPC_XCSR_writel (void *opaque, 132 hwaddr addr, uint32_t value) 133 { 134 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 135 value); 136 } 137 138 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) 139 { 140 uint32_t retval = 0; 141 142 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 143 retval); 144 145 return retval; 146 } 147 148 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) 149 { 150 uint32_t retval = 0; 151 152 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 153 retval); 154 155 return retval; 156 } 157 158 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) 159 { 160 uint32_t retval = 0; 161 162 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 163 retval); 164 165 return retval; 166 } 167 168 static const MemoryRegionOps PPC_XCSR_ops = { 169 .old_mmio = { 170 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, 171 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, 172 }, 173 .endianness = DEVICE_LITTLE_ENDIAN, 174 }; 175 176 #endif 177 178 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 179 typedef struct sysctrl_t { 180 qemu_irq reset_irq; 181 M48t59State *nvram; 182 uint8_t state; 183 uint8_t syscontrol; 184 uint8_t fake_io[2]; 185 int contiguous_map; 186 int endian; 187 } sysctrl_t; 188 189 enum { 190 STATE_HARDFILE = 0x01, 191 }; 192 193 static sysctrl_t *sysctrl; 194 195 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) 196 { 197 sysctrl_t *sysctrl = opaque; 198 199 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, 200 val); 201 sysctrl->fake_io[addr - 0x0398] = val; 202 } 203 204 static uint32_t PREP_io_read (void *opaque, uint32_t addr) 205 { 206 sysctrl_t *sysctrl = opaque; 207 208 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, 209 sysctrl->fake_io[addr - 0x0398]); 210 return sysctrl->fake_io[addr - 0x0398]; 211 } 212 213 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 214 { 215 sysctrl_t *sysctrl = opaque; 216 217 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", 218 addr - PPC_IO_BASE, val); 219 switch (addr) { 220 case 0x0092: 221 /* Special port 92 */ 222 /* Check soft reset asked */ 223 if (val & 0x01) { 224 qemu_irq_raise(sysctrl->reset_irq); 225 } else { 226 qemu_irq_lower(sysctrl->reset_irq); 227 } 228 /* Check LE mode */ 229 if (val & 0x02) { 230 sysctrl->endian = 1; 231 } else { 232 sysctrl->endian = 0; 233 } 234 break; 235 case 0x0800: 236 /* Motorola CPU configuration register : read-only */ 237 break; 238 case 0x0802: 239 /* Motorola base module feature register : read-only */ 240 break; 241 case 0x0803: 242 /* Motorola base module status register : read-only */ 243 break; 244 case 0x0808: 245 /* Hardfile light register */ 246 if (val & 1) 247 sysctrl->state |= STATE_HARDFILE; 248 else 249 sysctrl->state &= ~STATE_HARDFILE; 250 break; 251 case 0x0810: 252 /* Password protect 1 register */ 253 if (sysctrl->nvram != NULL) 254 m48t59_toggle_lock(sysctrl->nvram, 1); 255 break; 256 case 0x0812: 257 /* Password protect 2 register */ 258 if (sysctrl->nvram != NULL) 259 m48t59_toggle_lock(sysctrl->nvram, 2); 260 break; 261 case 0x0814: 262 /* L2 invalidate register */ 263 // tlb_flush(first_cpu, 1); 264 break; 265 case 0x081C: 266 /* system control register */ 267 sysctrl->syscontrol = val & 0x0F; 268 break; 269 case 0x0850: 270 /* I/O map type register */ 271 sysctrl->contiguous_map = val & 0x01; 272 break; 273 default: 274 printf("ERROR: unaffected IO port write: %04" PRIx32 275 " => %02" PRIx32"\n", addr, val); 276 break; 277 } 278 } 279 280 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 281 { 282 sysctrl_t *sysctrl = opaque; 283 uint32_t retval = 0xFF; 284 285 switch (addr) { 286 case 0x0092: 287 /* Special port 92 */ 288 retval = 0x00; 289 break; 290 case 0x0800: 291 /* Motorola CPU configuration register */ 292 retval = 0xEF; /* MPC750 */ 293 break; 294 case 0x0802: 295 /* Motorola Base module feature register */ 296 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 297 break; 298 case 0x0803: 299 /* Motorola base module status register */ 300 retval = 0xE0; /* Standard MPC750 */ 301 break; 302 case 0x080C: 303 /* Equipment present register: 304 * no L2 cache 305 * no upgrade processor 306 * no cards in PCI slots 307 * SCSI fuse is bad 308 */ 309 retval = 0x3C; 310 break; 311 case 0x0810: 312 /* Motorola base module extended feature register */ 313 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 314 break; 315 case 0x0814: 316 /* L2 invalidate: don't care */ 317 break; 318 case 0x0818: 319 /* Keylock */ 320 retval = 0x00; 321 break; 322 case 0x081C: 323 /* system control register 324 * 7 - 6 / 1 - 0: L2 cache enable 325 */ 326 retval = sysctrl->syscontrol; 327 break; 328 case 0x0823: 329 /* */ 330 retval = 0x03; /* no L2 cache */ 331 break; 332 case 0x0850: 333 /* I/O map type register */ 334 retval = sysctrl->contiguous_map; 335 break; 336 default: 337 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 338 break; 339 } 340 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", 341 addr - PPC_IO_BASE, retval); 342 343 return retval; 344 } 345 346 static inline hwaddr prep_IO_address(sysctrl_t *sysctrl, 347 hwaddr addr) 348 { 349 if (sysctrl->contiguous_map == 0) { 350 /* 64 KB contiguous space for IOs */ 351 addr &= 0xFFFF; 352 } else { 353 /* 8 MB non-contiguous space for IOs */ 354 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); 355 } 356 357 return addr; 358 } 359 360 static void PPC_prep_io_writeb (void *opaque, hwaddr addr, 361 uint32_t value) 362 { 363 sysctrl_t *sysctrl = opaque; 364 365 addr = prep_IO_address(sysctrl, addr); 366 cpu_outb(addr, value); 367 } 368 369 static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr) 370 { 371 sysctrl_t *sysctrl = opaque; 372 uint32_t ret; 373 374 addr = prep_IO_address(sysctrl, addr); 375 ret = cpu_inb(addr); 376 377 return ret; 378 } 379 380 static void PPC_prep_io_writew (void *opaque, hwaddr addr, 381 uint32_t value) 382 { 383 sysctrl_t *sysctrl = opaque; 384 385 addr = prep_IO_address(sysctrl, addr); 386 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); 387 cpu_outw(addr, value); 388 } 389 390 static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr) 391 { 392 sysctrl_t *sysctrl = opaque; 393 uint32_t ret; 394 395 addr = prep_IO_address(sysctrl, addr); 396 ret = cpu_inw(addr); 397 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); 398 399 return ret; 400 } 401 402 static void PPC_prep_io_writel (void *opaque, hwaddr addr, 403 uint32_t value) 404 { 405 sysctrl_t *sysctrl = opaque; 406 407 addr = prep_IO_address(sysctrl, addr); 408 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); 409 cpu_outl(addr, value); 410 } 411 412 static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr) 413 { 414 sysctrl_t *sysctrl = opaque; 415 uint32_t ret; 416 417 addr = prep_IO_address(sysctrl, addr); 418 ret = cpu_inl(addr); 419 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); 420 421 return ret; 422 } 423 424 static const MemoryRegionOps PPC_prep_io_ops = { 425 .old_mmio = { 426 .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, 427 .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, 428 }, 429 .endianness = DEVICE_LITTLE_ENDIAN, 430 }; 431 432 #define NVRAM_SIZE 0x2000 433 434 static void cpu_request_exit(void *opaque, int irq, int level) 435 { 436 CPUPPCState *env = cpu_single_env; 437 438 if (env && level) { 439 cpu_exit(env); 440 } 441 } 442 443 static void ppc_prep_reset(void *opaque) 444 { 445 PowerPCCPU *cpu = opaque; 446 447 cpu_reset(CPU(cpu)); 448 } 449 450 /* PowerPC PREP hardware initialisation */ 451 static void ppc_prep_init(QEMUMachineInitArgs *args) 452 { 453 ram_addr_t ram_size = args->ram_size; 454 const char *cpu_model = args->cpu_model; 455 const char *kernel_filename = args->kernel_filename; 456 const char *kernel_cmdline = args->kernel_cmdline; 457 const char *initrd_filename = args->initrd_filename; 458 const char *boot_device = args->boot_device; 459 MemoryRegion *sysmem = get_system_memory(); 460 PowerPCCPU *cpu = NULL; 461 CPUPPCState *env = NULL; 462 char *filename; 463 nvram_t nvram; 464 M48t59State *m48t59; 465 MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); 466 #if 0 467 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 468 #endif 469 int linux_boot, i, nb_nics1, bios_size; 470 MemoryRegion *ram = g_new(MemoryRegion, 1); 471 MemoryRegion *bios = g_new(MemoryRegion, 1); 472 uint32_t kernel_base, initrd_base; 473 long kernel_size, initrd_size; 474 DeviceState *dev; 475 PCIHostState *pcihost; 476 PCIBus *pci_bus; 477 PCIDevice *pci; 478 ISABus *isa_bus; 479 qemu_irq *cpu_exit_irq; 480 int ppc_boot_device; 481 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 482 DriveInfo *fd[MAX_FD]; 483 484 sysctrl = g_malloc0(sizeof(sysctrl_t)); 485 486 linux_boot = (kernel_filename != NULL); 487 488 /* init CPUs */ 489 if (cpu_model == NULL) 490 cpu_model = "602"; 491 for (i = 0; i < smp_cpus; i++) { 492 cpu = cpu_ppc_init(cpu_model); 493 if (cpu == NULL) { 494 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 495 exit(1); 496 } 497 env = &cpu->env; 498 499 if (env->flags & POWERPC_FLAG_RTC_CLK) { 500 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 501 cpu_ppc_tb_init(env, 7812500UL); 502 } else { 503 /* Set time-base frequency to 100 Mhz */ 504 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 505 } 506 qemu_register_reset(ppc_prep_reset, cpu); 507 } 508 509 /* allocate RAM */ 510 memory_region_init_ram(ram, "ppc_prep.ram", ram_size); 511 vmstate_register_ram_global(ram); 512 memory_region_add_subregion(sysmem, 0, ram); 513 514 /* allocate and load BIOS */ 515 memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE); 516 memory_region_set_readonly(bios, true); 517 memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios); 518 vmstate_register_ram_global(bios); 519 if (bios_name == NULL) 520 bios_name = BIOS_FILENAME; 521 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 522 if (filename) { 523 bios_size = get_image_size(filename); 524 } else { 525 bios_size = -1; 526 } 527 if (bios_size > 0 && bios_size <= BIOS_SIZE) { 528 hwaddr bios_addr; 529 bios_size = (bios_size + 0xfff) & ~0xfff; 530 bios_addr = (uint32_t)(-bios_size); 531 bios_size = load_image_targphys(filename, bios_addr, bios_size); 532 } 533 if (bios_size < 0 || bios_size > BIOS_SIZE) { 534 hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); 535 } 536 if (filename) { 537 g_free(filename); 538 } 539 540 if (linux_boot) { 541 kernel_base = KERNEL_LOAD_ADDR; 542 /* now we can load the kernel */ 543 kernel_size = load_image_targphys(kernel_filename, kernel_base, 544 ram_size - kernel_base); 545 if (kernel_size < 0) { 546 hw_error("qemu: could not load kernel '%s'\n", kernel_filename); 547 exit(1); 548 } 549 /* load initrd */ 550 if (initrd_filename) { 551 initrd_base = INITRD_LOAD_ADDR; 552 initrd_size = load_image_targphys(initrd_filename, initrd_base, 553 ram_size - initrd_base); 554 if (initrd_size < 0) { 555 hw_error("qemu: could not load initial ram disk '%s'\n", 556 initrd_filename); 557 } 558 } else { 559 initrd_base = 0; 560 initrd_size = 0; 561 } 562 ppc_boot_device = 'm'; 563 } else { 564 kernel_base = 0; 565 kernel_size = 0; 566 initrd_base = 0; 567 initrd_size = 0; 568 ppc_boot_device = '\0'; 569 /* For now, OHW cannot boot from the network. */ 570 for (i = 0; boot_device[i] != '\0'; i++) { 571 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 572 ppc_boot_device = boot_device[i]; 573 break; 574 } 575 } 576 if (ppc_boot_device == '\0') { 577 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 578 exit(1); 579 } 580 } 581 582 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 583 hw_error("Only 6xx bus is supported on PREP machine\n"); 584 } 585 586 dev = qdev_create(NULL, "raven-pcihost"); 587 pcihost = PCI_HOST_BRIDGE(dev); 588 pcihost->address_space = get_system_memory(); 589 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 590 qdev_init_nofail(dev); 591 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 592 if (pci_bus == NULL) { 593 fprintf(stderr, "Couldn't create PCI host controller.\n"); 594 exit(1); 595 } 596 597 /* PCI -> ISA bridge */ 598 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 599 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 600 qdev_connect_gpio_out(&pci->qdev, 0, 601 first_cpu->irq_inputs[PPC6xx_INPUT_INT]); 602 qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq); 603 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 604 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 605 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 606 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 607 isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0")); 608 609 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ 610 memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl, 611 "ppc-io", 0x00800000); 612 memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); 613 614 /* init basic PC hardware */ 615 pci_vga_init(pci_bus); 616 617 if (serial_hds[0]) 618 serial_isa_init(isa_bus, 0, serial_hds[0]); 619 nb_nics1 = nb_nics; 620 if (nb_nics1 > NE2000_NB_MAX) 621 nb_nics1 = NE2000_NB_MAX; 622 for(i = 0; i < nb_nics1; i++) { 623 if (nd_table[i].model == NULL) { 624 nd_table[i].model = g_strdup("ne2k_isa"); 625 } 626 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 627 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 628 &nd_table[i]); 629 } else { 630 pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); 631 } 632 } 633 634 ide_drive_get(hd, MAX_IDE_BUS); 635 for(i = 0; i < MAX_IDE_BUS; i++) { 636 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 637 hd[2 * i], 638 hd[2 * i + 1]); 639 } 640 isa_create_simple(isa_bus, "i8042"); 641 642 // SB16_init(); 643 644 for(i = 0; i < MAX_FD; i++) { 645 fd[i] = drive_get(IF_FLOPPY, 0, i); 646 } 647 fdctrl_init_isa(isa_bus, fd); 648 649 /* Register fake IO ports for PREP */ 650 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; 651 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); 652 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); 653 /* System control ports */ 654 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); 655 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); 656 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); 657 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); 658 /* PowerPC control and status register group */ 659 #if 0 660 memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); 661 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); 662 #endif 663 664 if (usb_enabled(false)) { 665 pci_create_simple(pci_bus, -1, "pci-ohci"); 666 } 667 668 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); 669 if (m48t59 == NULL) 670 return; 671 sysctrl->nvram = m48t59; 672 673 /* Initialise NVRAM */ 674 nvram.opaque = m48t59; 675 nvram.read_fn = &m48t59_read; 676 nvram.write_fn = &m48t59_write; 677 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, 678 kernel_base, kernel_size, 679 kernel_cmdline, 680 initrd_base, initrd_size, 681 /* XXX: need an option to load a NVRAM image */ 682 0, 683 graphic_width, graphic_height, graphic_depth); 684 685 /* Special port to get debug messages from Open-Firmware */ 686 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); 687 688 /* Initialize audio subsystem */ 689 audio_init(isa_bus, pci_bus); 690 } 691 692 static QEMUMachine prep_machine = { 693 .name = "prep", 694 .desc = "PowerPC PREP platform", 695 .init = ppc_prep_init, 696 .max_cpus = MAX_CPUS, 697 }; 698 699 static void prep_machine_init(void) 700 { 701 qemu_register_machine(&prep_machine); 702 } 703 704 machine_init(prep_machine_init); 705