1 /* 2 * QEMU PowerPC Booke hardware System Emulator 3 * 4 * Copyright (c) 2011 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "exec/target_page.h" 28 #include "hw/ppc/ppc.h" 29 #include "qemu/timer.h" 30 #include "system/reset.h" 31 #include "system/runstate.h" 32 #include "hw/loader.h" 33 #include "kvm_ppc.h" 34 35 void booke_set_tlb(ppcemb_tlb_t *tlb, target_ulong va, hwaddr pa, 36 target_ulong size) 37 { 38 tlb->attr = 0; 39 tlb->prot = PAGE_RWX << 4 | PAGE_VALID; 40 tlb->size = size; 41 tlb->EPN = va & TARGET_PAGE_MASK; 42 tlb->RPN = pa & TARGET_PAGE_MASK; 43 tlb->PID = 0; 44 } 45 46 /* Timer Control Register */ 47 48 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ 49 #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT) 50 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ 51 #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT) 52 #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */ 53 #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */ 54 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ 55 #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT) 56 #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */ 57 #define TCR_ARE (1U << 22) /* Auto-Reload Enable */ 58 59 /* Timer Control Register (e500 specific fields) */ 60 61 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */ 62 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT) 63 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */ 64 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT) 65 66 /* Timer Status Register */ 67 68 #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */ 69 #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */ 70 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ 71 #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT) 72 #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */ 73 #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */ 74 75 typedef struct booke_timer_t booke_timer_t; 76 struct booke_timer_t { 77 78 uint64_t fit_next; 79 QEMUTimer *fit_timer; 80 81 uint64_t wdt_next; 82 QEMUTimer *wdt_timer; 83 84 uint32_t flags; 85 }; 86 87 static void booke_update_irq(PowerPCCPU *cpu) 88 { 89 CPUPPCState *env = &cpu->env; 90 91 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 92 (env->spr[SPR_BOOKE_TSR] & TSR_DIS 93 && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); 94 95 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 96 (env->spr[SPR_BOOKE_TSR] & TSR_WIS 97 && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); 98 99 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 100 (env->spr[SPR_BOOKE_TSR] & TSR_FIS 101 && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); 102 } 103 104 /* Return the location of the bit of time base at which the FIT will raise an 105 interrupt */ 106 static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) 107 { 108 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; 109 110 if (tb_env->flags & PPC_TIMER_E500) { 111 /* e500 Fixed-interval timer period extension */ 112 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) 113 >> TCR_E500_FPEXT_SHIFT; 114 fp = 63 - (fp | fpext << 2); 115 } else { 116 fp = env->fit_period[fp]; 117 } 118 119 return fp; 120 } 121 122 /* Return the location of the bit of time base at which the WDT will raise an 123 interrupt */ 124 static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) 125 { 126 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; 127 128 if (tb_env->flags & PPC_TIMER_E500) { 129 /* e500 Watchdog timer period extension */ 130 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) 131 >> TCR_E500_WPEXT_SHIFT; 132 wp = 63 - (wp | wpext << 2); 133 } else { 134 wp = env->wdt_period[wp]; 135 } 136 137 return wp; 138 } 139 140 static void booke_update_fixed_timer(CPUPPCState *env, 141 uint8_t target_bit, 142 uint64_t *next, 143 QEMUTimer *timer, 144 int tsr_bit) 145 { 146 ppc_tb_t *tb_env = env->tb_env; 147 uint64_t delta_tick, ticks = 0; 148 uint64_t tb; 149 uint64_t period; 150 uint64_t now; 151 152 if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) { 153 /* 154 * Don't arm the timer again when the guest has the current 155 * interrupt still pending. Wait for it to ack it. 156 */ 157 return; 158 } 159 160 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 161 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset); 162 period = 1ULL << target_bit; 163 delta_tick = period - (tb & (period - 1)); 164 165 /* the timer triggers only when the selected bit toggles from 0 to 1 */ 166 if (tb & period) { 167 ticks = period; 168 } 169 170 if (ticks + delta_tick < ticks) { 171 /* Overflow, so assume the biggest number we can express. */ 172 ticks = UINT64_MAX; 173 } else { 174 ticks += delta_tick; 175 } 176 177 *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 178 if ((*next < now) || (*next > INT64_MAX)) { 179 /* Overflow, so assume the biggest number the qemu timer supports. */ 180 *next = INT64_MAX; 181 } 182 183 /* XXX: If expire time is now. We can't run the callback because we don't 184 * have access to it. So we just set the timer one nanosecond later. 185 */ 186 187 if (*next == now) { 188 (*next)++; 189 } else { 190 /* 191 * There's no point to fake any granularity that's more fine grained 192 * than milliseconds. Anything beyond that just overloads the system. 193 */ 194 *next = MAX(*next, now + SCALE_MS); 195 } 196 197 /* Fire the next timer */ 198 timer_mod(timer, *next); 199 } 200 201 static void booke_decr_cb(void *opaque) 202 { 203 PowerPCCPU *cpu = opaque; 204 CPUPPCState *env = &cpu->env; 205 206 env->spr[SPR_BOOKE_TSR] |= TSR_DIS; 207 booke_update_irq(cpu); 208 209 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) { 210 /* Do not reload 0, it is already there. It would just trigger 211 * the timer again and lead to infinite loop */ 212 if (env->spr[SPR_BOOKE_DECAR] != 0) { 213 /* Auto Reload */ 214 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]); 215 } 216 } 217 } 218 219 static void booke_fit_cb(void *opaque) 220 { 221 PowerPCCPU *cpu = opaque; 222 CPUPPCState *env = &cpu->env; 223 ppc_tb_t *tb_env; 224 booke_timer_t *booke_timer; 225 226 tb_env = env->tb_env; 227 booke_timer = tb_env->opaque; 228 env->spr[SPR_BOOKE_TSR] |= TSR_FIS; 229 230 booke_update_irq(cpu); 231 232 booke_update_fixed_timer(env, 233 booke_get_fit_target(env, tb_env), 234 &booke_timer->fit_next, 235 booke_timer->fit_timer, 236 TSR_FIS); 237 } 238 239 static void booke_wdt_cb(void *opaque) 240 { 241 PowerPCCPU *cpu = opaque; 242 CPUPPCState *env = &cpu->env; 243 ppc_tb_t *tb_env; 244 booke_timer_t *booke_timer; 245 246 tb_env = env->tb_env; 247 booke_timer = tb_env->opaque; 248 249 /* TODO: There's lots of complicated stuff to do here */ 250 251 booke_update_irq(cpu); 252 253 booke_update_fixed_timer(env, 254 booke_get_wdt_target(env, tb_env), 255 &booke_timer->wdt_next, 256 booke_timer->wdt_timer, 257 TSR_WIS); 258 } 259 260 void store_booke_tsr(CPUPPCState *env, target_ulong val) 261 { 262 PowerPCCPU *cpu = env_archcpu(env); 263 ppc_tb_t *tb_env = env->tb_env; 264 booke_timer_t *booke_timer = tb_env->opaque; 265 266 env->spr[SPR_BOOKE_TSR] &= ~val; 267 kvmppc_clear_tsr_bits(cpu, val); 268 269 if (val & TSR_FIS) { 270 booke_update_fixed_timer(env, 271 booke_get_fit_target(env, tb_env), 272 &booke_timer->fit_next, 273 booke_timer->fit_timer, 274 TSR_FIS); 275 } 276 277 if (val & TSR_WIS) { 278 booke_update_fixed_timer(env, 279 booke_get_wdt_target(env, tb_env), 280 &booke_timer->wdt_next, 281 booke_timer->wdt_timer, 282 TSR_WIS); 283 } 284 285 booke_update_irq(cpu); 286 } 287 288 void store_booke_tcr(CPUPPCState *env, target_ulong val) 289 { 290 PowerPCCPU *cpu = env_archcpu(env); 291 ppc_tb_t *tb_env = env->tb_env; 292 booke_timer_t *booke_timer = tb_env->opaque; 293 294 env->spr[SPR_BOOKE_TCR] = val; 295 kvmppc_set_tcr(cpu); 296 297 booke_update_irq(cpu); 298 299 booke_update_fixed_timer(env, 300 booke_get_fit_target(env, tb_env), 301 &booke_timer->fit_next, 302 booke_timer->fit_timer, 303 TSR_FIS); 304 305 booke_update_fixed_timer(env, 306 booke_get_wdt_target(env, tb_env), 307 &booke_timer->wdt_next, 308 booke_timer->wdt_timer, 309 TSR_WIS); 310 } 311 312 static void ppc_booke_timer_reset_handle(void *opaque) 313 { 314 PowerPCCPU *cpu = opaque; 315 CPUPPCState *env = &cpu->env; 316 317 store_booke_tcr(env, 0); 318 store_booke_tsr(env, -1); 319 } 320 321 /* 322 * This function will be called whenever the CPU state changes. 323 * CPU states are defined "typedef enum RunState". 324 * Regarding timer, When CPU state changes to running after debug halt 325 * or similar cases which takes time then in between final watchdog 326 * expiry happenes. This will cause exit to QEMU and configured watchdog 327 * action will be taken. To avoid this we always clear the watchdog state when 328 * state changes to running. 329 */ 330 static void cpu_state_change_handler(void *opaque, bool running, RunState state) 331 { 332 PowerPCCPU *cpu = opaque; 333 CPUPPCState *env = &cpu->env; 334 335 if (!running) { 336 return; 337 } 338 339 /* 340 * Clear watchdog interrupt condition by clearing TSR. 341 */ 342 store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); 343 } 344 345 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) 346 { 347 ppc_tb_t *tb_env; 348 booke_timer_t *booke_timer; 349 int ret = 0; 350 351 tb_env = g_new0(ppc_tb_t, 1); 352 booke_timer = g_new0(booke_timer_t, 1); 353 354 cpu->env.tb_env = tb_env; 355 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; 356 357 tb_env->tb_freq = freq; 358 tb_env->decr_freq = freq; 359 tb_env->opaque = booke_timer; 360 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu); 361 362 booke_timer->fit_timer = 363 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu); 364 booke_timer->wdt_timer = 365 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu); 366 367 ret = kvmppc_booke_watchdog_enable(cpu); 368 369 if (ret) { 370 /* TODO: Start the QEMU emulated watchdog if not running on KVM. 371 * Also start the QEMU emulated watchdog if KVM does not support 372 * emulated watchdog or somehow it is not enabled (supported but 373 * not enabled is though some bug and requires debugging :)). 374 */ 375 } 376 377 qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu); 378 379 qemu_register_reset(ppc_booke_timer_reset_handle, cpu); 380 } 381