1 /* 2 * QEMU PowerPC PowerNV Emulation of a few OCC related registers 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License, version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "target/ppc/cpu.h" 21 #include "qapi/error.h" 22 #include "qemu/log.h" 23 #include "qemu/module.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/ppc/pnv.h" 27 #include "hw/ppc/pnv_chip.h" 28 #include "hw/ppc/pnv_xscom.h" 29 #include "hw/ppc/pnv_occ.h" 30 31 #define P8_HOMER_OPAL_DATA_OFFSET 0x1F8000 32 #define P9_HOMER_OPAL_DATA_OFFSET 0x0E2000 33 34 #define OCB_OCI_OCCMISC 0x4020 35 #define OCB_OCI_OCCMISC_AND 0x4021 36 #define OCB_OCI_OCCMISC_OR 0x4022 37 #define OCCMISC_PSI_IRQ PPC_BIT(0) 38 #define OCCMISC_IRQ_SHMEM PPC_BIT(3) 39 40 /* OCC sensors */ 41 #define OCC_SENSOR_DATA_BLOCK_OFFSET 0x0000 42 #define OCC_SENSOR_DATA_VALID 0x0001 43 #define OCC_SENSOR_DATA_VERSION 0x0002 44 #define OCC_SENSOR_DATA_READING_VERSION 0x0004 45 #define OCC_SENSOR_DATA_NR_SENSORS 0x0008 46 #define OCC_SENSOR_DATA_NAMES_OFFSET 0x0010 47 #define OCC_SENSOR_DATA_READING_PING_OFFSET 0x0014 48 #define OCC_SENSOR_DATA_READING_PONG_OFFSET 0x000c 49 #define OCC_SENSOR_DATA_NAME_LENGTH 0x000d 50 #define OCC_SENSOR_NAME_STRUCTURE_TYPE 0x0023 51 #define OCC_SENSOR_LOC_CORE 0x0022 52 #define OCC_SENSOR_LOC_GPU 0x0020 53 #define OCC_SENSOR_TYPE_POWER 0x0003 54 #define OCC_SENSOR_NAME 0x0005 55 #define HWMON_SENSORS_MASK 0x001e 56 57 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) 58 { 59 val &= PPC_BITMASK(0, 18); /* Mask out unimplemented bits */ 60 61 occ->occmisc = val; 62 63 /* 64 * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear 65 * how that is handled in PSI so it is level-triggered here, which is not 66 * really correct (but skiboot is okay with it). 67 */ 68 qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); 69 } 70 71 static void pnv_occ_raise_msg_irq(PnvOCC *occ) 72 { 73 pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHMEM); 74 } 75 76 static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr, 77 unsigned size) 78 { 79 PnvOCC *occ = PNV_OCC(opaque); 80 uint32_t offset = addr >> 3; 81 uint64_t val = 0; 82 83 switch (offset) { 84 case OCB_OCI_OCCMISC: 85 val = occ->occmisc; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 89 HWADDR_PRIx "\n", addr >> 3); 90 } 91 return val; 92 } 93 94 static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr, 95 uint64_t val, unsigned size) 96 { 97 PnvOCC *occ = PNV_OCC(opaque); 98 uint32_t offset = addr >> 3; 99 100 switch (offset) { 101 case OCB_OCI_OCCMISC_AND: 102 pnv_occ_set_misc(occ, occ->occmisc & val); 103 break; 104 case OCB_OCI_OCCMISC_OR: 105 pnv_occ_set_misc(occ, occ->occmisc | val); 106 break; 107 case OCB_OCI_OCCMISC: 108 pnv_occ_set_misc(occ, val); 109 break; 110 default: 111 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 112 HWADDR_PRIx "\n", addr >> 3); 113 } 114 } 115 116 static uint64_t pnv_occ_common_area_read(void *opaque, hwaddr addr, 117 unsigned width) 118 { 119 switch (addr) { 120 /* 121 * occ-sensor sanity check that asserts the sensor 122 * header block 123 */ 124 case OCC_SENSOR_DATA_BLOCK_OFFSET: 125 case OCC_SENSOR_DATA_VALID: 126 case OCC_SENSOR_DATA_VERSION: 127 case OCC_SENSOR_DATA_READING_VERSION: 128 case OCC_SENSOR_DATA_NR_SENSORS: 129 case OCC_SENSOR_DATA_NAMES_OFFSET: 130 case OCC_SENSOR_DATA_READING_PING_OFFSET: 131 case OCC_SENSOR_DATA_READING_PONG_OFFSET: 132 case OCC_SENSOR_NAME_STRUCTURE_TYPE: 133 return 1; 134 case OCC_SENSOR_DATA_NAME_LENGTH: 135 return 0x30; 136 case OCC_SENSOR_LOC_CORE: 137 return 0x0040; 138 case OCC_SENSOR_TYPE_POWER: 139 return 0x0080; 140 case OCC_SENSOR_NAME: 141 return 0x1000; 142 case HWMON_SENSORS_MASK: 143 case OCC_SENSOR_LOC_GPU: 144 return 0x8e00; 145 } 146 return 0; 147 } 148 149 static void pnv_occ_common_area_write(void *opaque, hwaddr addr, 150 uint64_t val, unsigned width) 151 { 152 /* callback function defined to occ common area write */ 153 return; 154 } 155 156 static const MemoryRegionOps pnv_occ_power8_xscom_ops = { 157 .read = pnv_occ_power8_xscom_read, 158 .write = pnv_occ_power8_xscom_write, 159 .valid.min_access_size = 8, 160 .valid.max_access_size = 8, 161 .impl.min_access_size = 8, 162 .impl.max_access_size = 8, 163 .endianness = DEVICE_BIG_ENDIAN, 164 }; 165 166 const MemoryRegionOps pnv_occ_sram_ops = { 167 .read = pnv_occ_common_area_read, 168 .write = pnv_occ_common_area_write, 169 .valid.min_access_size = 1, 170 .valid.max_access_size = 8, 171 .impl.min_access_size = 1, 172 .impl.max_access_size = 8, 173 .endianness = DEVICE_BIG_ENDIAN, 174 }; 175 176 static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) 177 { 178 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 179 DeviceClass *dc = DEVICE_CLASS(klass); 180 181 dc->desc = "PowerNV OCC Controller (POWER8)"; 182 poc->opal_shared_memory_offset = P8_HOMER_OPAL_DATA_OFFSET; 183 poc->opal_shared_memory_version = 0x02; 184 poc->xscom_size = PNV_XSCOM_OCC_SIZE; 185 poc->xscom_ops = &pnv_occ_power8_xscom_ops; 186 } 187 188 static const TypeInfo pnv_occ_power8_type_info = { 189 .name = TYPE_PNV8_OCC, 190 .parent = TYPE_PNV_OCC, 191 .instance_size = sizeof(PnvOCC), 192 .class_init = pnv_occ_power8_class_init, 193 }; 194 195 #define P9_OCB_OCI_OCCMISC 0x6080 196 #define P9_OCB_OCI_OCCMISC_CLEAR 0x6081 197 #define P9_OCB_OCI_OCCMISC_OR 0x6082 198 199 200 static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr, 201 unsigned size) 202 { 203 PnvOCC *occ = PNV_OCC(opaque); 204 uint32_t offset = addr >> 3; 205 uint64_t val = 0; 206 207 switch (offset) { 208 case P9_OCB_OCI_OCCMISC: 209 val = occ->occmisc; 210 break; 211 default: 212 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 213 HWADDR_PRIx "\n", addr >> 3); 214 } 215 return val; 216 } 217 218 static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr, 219 uint64_t val, unsigned size) 220 { 221 PnvOCC *occ = PNV_OCC(opaque); 222 uint32_t offset = addr >> 3; 223 224 switch (offset) { 225 case P9_OCB_OCI_OCCMISC_CLEAR: 226 pnv_occ_set_misc(occ, 0); 227 break; 228 case P9_OCB_OCI_OCCMISC_OR: 229 pnv_occ_set_misc(occ, occ->occmisc | val); 230 break; 231 case P9_OCB_OCI_OCCMISC: 232 pnv_occ_set_misc(occ, val); 233 break; 234 default: 235 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 236 HWADDR_PRIx "\n", addr >> 3); 237 } 238 } 239 240 static const MemoryRegionOps pnv_occ_power9_xscom_ops = { 241 .read = pnv_occ_power9_xscom_read, 242 .write = pnv_occ_power9_xscom_write, 243 .valid.min_access_size = 8, 244 .valid.max_access_size = 8, 245 .impl.min_access_size = 8, 246 .impl.max_access_size = 8, 247 .endianness = DEVICE_BIG_ENDIAN, 248 }; 249 250 static void pnv_occ_power9_class_init(ObjectClass *klass, void *data) 251 { 252 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 253 DeviceClass *dc = DEVICE_CLASS(klass); 254 255 dc->desc = "PowerNV OCC Controller (POWER9)"; 256 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; 257 poc->opal_shared_memory_version = 0x90; 258 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; 259 poc->xscom_ops = &pnv_occ_power9_xscom_ops; 260 assert(!dc->user_creatable); 261 } 262 263 static const TypeInfo pnv_occ_power9_type_info = { 264 .name = TYPE_PNV9_OCC, 265 .parent = TYPE_PNV_OCC, 266 .instance_size = sizeof(PnvOCC), 267 .class_init = pnv_occ_power9_class_init, 268 }; 269 270 static void pnv_occ_power10_class_init(ObjectClass *klass, void *data) 271 { 272 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 273 DeviceClass *dc = DEVICE_CLASS(klass); 274 275 dc->desc = "PowerNV OCC Controller (POWER10)"; 276 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; 277 poc->opal_shared_memory_version = 0xA0; 278 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; 279 poc->xscom_ops = &pnv_occ_power9_xscom_ops; 280 assert(!dc->user_creatable); 281 } 282 283 static const TypeInfo pnv_occ_power10_type_info = { 284 .name = TYPE_PNV10_OCC, 285 .parent = TYPE_PNV_OCC, 286 .class_init = pnv_occ_power10_class_init, 287 }; 288 289 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp); 290 static bool occ_model_tick(PnvOCC *occ); 291 292 /* Relatively arbitrary */ 293 #define OCC_POLL_MS 100 294 295 static void occ_state_machine_timer(void *opaque) 296 { 297 PnvOCC *occ = opaque; 298 uint64_t next = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + OCC_POLL_MS; 299 300 if (occ_model_tick(occ)) { 301 timer_mod(&occ->state_machine_timer, next); 302 } 303 } 304 305 static void pnv_occ_realize(DeviceState *dev, Error **errp) 306 { 307 PnvOCC *occ = PNV_OCC(dev); 308 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 309 PnvHomer *homer = occ->homer; 310 311 assert(homer); 312 313 if (!occ_init_homer_memory(occ, errp)) { 314 return; 315 } 316 317 occ->occmisc = 0; 318 319 /* XScom region for OCC registers */ 320 pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, 321 occ, "xscom-occ", poc->xscom_size); 322 323 /* OCC common area mmio region for OCC SRAM registers */ 324 memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops, 325 occ, "occ-common-area", 326 PNV_OCC_SENSOR_DATA_BLOCK_SIZE); 327 328 qdev_init_gpio_out(dev, &occ->psi_irq, 1); 329 330 timer_init_ms(&occ->state_machine_timer, QEMU_CLOCK_VIRTUAL, 331 occ_state_machine_timer, occ); 332 timer_mod(&occ->state_machine_timer, OCC_POLL_MS); 333 } 334 335 static const Property pnv_occ_properties[] = { 336 DEFINE_PROP_LINK("homer", PnvOCC, homer, TYPE_PNV_HOMER, PnvHomer *), 337 }; 338 339 static void pnv_occ_class_init(ObjectClass *klass, void *data) 340 { 341 DeviceClass *dc = DEVICE_CLASS(klass); 342 343 dc->realize = pnv_occ_realize; 344 device_class_set_props(dc, pnv_occ_properties); 345 dc->user_creatable = false; 346 } 347 348 static const TypeInfo pnv_occ_type_info = { 349 .name = TYPE_PNV_OCC, 350 .parent = TYPE_DEVICE, 351 .instance_size = sizeof(PnvOCC), 352 .class_init = pnv_occ_class_init, 353 .class_size = sizeof(PnvOCCClass), 354 .abstract = true, 355 }; 356 357 static void pnv_occ_register_types(void) 358 { 359 type_register_static(&pnv_occ_type_info); 360 type_register_static(&pnv_occ_power8_type_info); 361 type_register_static(&pnv_occ_power9_type_info); 362 type_register_static(&pnv_occ_power10_type_info); 363 } 364 365 type_init(pnv_occ_register_types); 366 367 /* 368 * From skiboot/hw/occ.c with following changes: 369 * - tab to space conversion 370 * - Type conversions u8->uint8_t s8->int8_t __be16->uint16_t etc 371 * - __packed -> QEMU_PACKED 372 */ 373 /* OCC Communication Area for PStates */ 374 375 #define OPAL_DYNAMIC_DATA_OFFSET 0x0B80 376 /* relative to HOMER_OPAL_DATA_OFFSET */ 377 378 #define MAX_PSTATES 256 379 #define MAX_P8_CORES 12 380 #define MAX_P9_CORES 24 381 #define MAX_P10_CORES 32 382 383 #define MAX_OPAL_CMD_DATA_LENGTH 4090 384 #define MAX_OCC_RSP_DATA_LENGTH 8698 385 386 #define P8_PIR_CORE_MASK 0xFFF8 387 #define P9_PIR_QUAD_MASK 0xFFF0 388 #define P10_PIR_CHIP_MASK 0x0000 389 #define FREQ_MAX_IN_DOMAIN 0 390 #define FREQ_MOST_RECENTLY_SET 1 391 392 /** 393 * OCC-OPAL Shared Memory Region 394 * 395 * Reference document : 396 * https://github.com/open-power/docs/blob/master/occ/OCC_OpenPwr_FW_Interfaces.pdf 397 * 398 * Supported layout versions: 399 * - 0x01, 0x02 : P8 400 * https://github.com/open-power/occ/blob/master_p8/src/occ/proc/proc_pstate.h 401 * 402 * - 0x90 : P9 403 * https://github.com/open-power/occ/blob/master/src/occ_405/proc/proc_pstate.h 404 * In 0x90 the data is separated into :- 405 * -- Static Data (struct occ_pstate_table): Data is written once by OCC 406 * -- Dynamic Data (struct occ_dynamic_data): Data is updated at runtime 407 * 408 * struct occ_pstate_table - Pstate table layout 409 * @valid: Indicates if data is valid 410 * @version: Layout version [Major/Minor] 411 * @v2.throttle: Reason for limiting the max pstate 412 * @v9.occ_role: OCC role (Master/Slave) 413 * @v#.pstate_min: Minimum pstate ever allowed 414 * @v#.pstate_nom: Nominal pstate 415 * @v#.pstate_turbo: Maximum turbo pstate 416 * @v#.pstate_ultra_turbo: Maximum ultra turbo pstate and the maximum 417 * pstate ever allowed 418 * @v#.pstates: Pstate-id and frequency list from Pmax to Pmin 419 * @v#.pstates.id: Pstate-id 420 * @v#.pstates.flags: Pstate-flag(reserved) 421 * @v2.pstates.vdd: Voltage Identifier 422 * @v2.pstates.vcs: Voltage Identifier 423 * @v#.pstates.freq_khz: Frequency in KHz 424 * @v#.core_max[1..N]: Max pstate with N active cores 425 * @spare/reserved/pad: Unused data 426 */ 427 struct occ_pstate_table { 428 uint8_t valid; 429 uint8_t version; 430 union QEMU_PACKED { 431 struct QEMU_PACKED { /* Version 0x01 and 0x02 */ 432 uint8_t throttle; 433 int8_t pstate_min; 434 int8_t pstate_nom; 435 int8_t pstate_turbo; 436 int8_t pstate_ultra_turbo; 437 uint8_t spare; 438 uint64_t reserved; 439 struct QEMU_PACKED { 440 int8_t id; 441 uint8_t flags; 442 uint8_t vdd; 443 uint8_t vcs; 444 uint32_t freq_khz; 445 } pstates[MAX_PSTATES]; 446 int8_t core_max[MAX_P8_CORES]; 447 uint8_t pad[100]; 448 } v2; 449 struct QEMU_PACKED { /* Version 0x90 */ 450 uint8_t occ_role; 451 uint8_t pstate_min; 452 uint8_t pstate_nom; 453 uint8_t pstate_turbo; 454 uint8_t pstate_ultra_turbo; 455 uint8_t spare; 456 uint64_t reserved1; 457 uint64_t reserved2; 458 struct QEMU_PACKED { 459 uint8_t id; 460 uint8_t flags; 461 uint16_t reserved; 462 uint32_t freq_khz; 463 } pstates[MAX_PSTATES]; 464 uint8_t core_max[MAX_P9_CORES]; 465 uint8_t pad[56]; 466 } v9; 467 struct QEMU_PACKED { /* Version 0xA0 */ 468 uint8_t occ_role; 469 uint8_t pstate_min; 470 uint8_t pstate_fixed_freq; 471 uint8_t pstate_base; 472 uint8_t pstate_ultra_turbo; 473 uint8_t pstate_fmax; 474 uint8_t minor; 475 uint8_t pstate_bottom_throttle; 476 uint8_t spare; 477 uint8_t spare1; 478 uint32_t reserved_32; 479 uint64_t reserved_64; 480 struct QEMU_PACKED { 481 uint8_t id; 482 uint8_t valid; 483 uint16_t reserved; 484 uint32_t freq_khz; 485 } pstates[MAX_PSTATES]; 486 uint8_t core_max[MAX_P10_CORES]; 487 uint8_t pad[48]; 488 } v10; 489 }; 490 } QEMU_PACKED; 491 492 /** 493 * OPAL-OCC Command Response Interface 494 * 495 * OPAL-OCC Command Buffer 496 * 497 * --------------------------------------------------------------------- 498 * | OPAL | Cmd | OPAL | | Cmd Data | Cmd Data | OPAL | 499 * | Cmd | Request | OCC | Reserved | Length | Length | Cmd | 500 * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | 501 * --------------------------------------------------------------------- 502 * | ….OPAL Command Data up to max of Cmd Data Length 4090 bytes | 503 * | | 504 * --------------------------------------------------------------------- 505 * 506 * OPAL Command Flag 507 * 508 * ----------------------------------------------------------------- 509 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | 510 * | (msb) | | | | | | | (lsb) | 511 * ----------------------------------------------------------------- 512 * |Cmd | | | | | | | | 513 * |Ready | | | | | | | | 514 * ----------------------------------------------------------------- 515 * 516 * struct opal_command_buffer - Defines the layout of OPAL command buffer 517 * @flag: Provides general status of the command 518 * @request_id: Token to identify request 519 * @cmd: Command sent 520 * @data_size: Command data length 521 * @data: Command specific data 522 * @spare: Unused byte 523 */ 524 struct opal_command_buffer { 525 uint8_t flag; 526 uint8_t request_id; 527 uint8_t cmd; 528 uint8_t spare; 529 uint16_t data_size; 530 uint8_t data[MAX_OPAL_CMD_DATA_LENGTH]; 531 } QEMU_PACKED; 532 533 /** 534 * OPAL-OCC Response Buffer 535 * 536 * --------------------------------------------------------------------- 537 * | OCC | Cmd | OPAL | Response | Rsp Data | Rsp Data | OPAL | 538 * | Rsp | Request | OCC | Status | Length | Length | Rsp | 539 * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | 540 * --------------------------------------------------------------------- 541 * | ….OPAL Response Data up to max of Rsp Data Length 8698 bytes | 542 * | | 543 * --------------------------------------------------------------------- 544 * 545 * OCC Response Flag 546 * 547 * ----------------------------------------------------------------- 548 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | 549 * | (msb) | | | | | | | (lsb) | 550 * ----------------------------------------------------------------- 551 * | | | | | | |OCC in | Rsp | 552 * | | | | | | |progress|Ready | 553 * ----------------------------------------------------------------- 554 * 555 * struct occ_response_buffer - Defines the layout of OCC response buffer 556 * @flag: Provides general status of the response 557 * @request_id: Token to identify request 558 * @cmd: Command requested 559 * @status: Indicates success/failure status of 560 * the command 561 * @data_size: Response data length 562 * @data: Response specific data 563 */ 564 struct occ_response_buffer { 565 uint8_t flag; 566 uint8_t request_id; 567 uint8_t cmd; 568 uint8_t status; 569 uint16_t data_size; 570 uint8_t data[MAX_OCC_RSP_DATA_LENGTH]; 571 } QEMU_PACKED; 572 573 /** 574 * OCC-OPAL Shared Memory Interface Dynamic Data Vx90 575 * 576 * struct occ_dynamic_data - Contains runtime attributes 577 * @occ_state: Current state of OCC 578 * @major_version: Major version number 579 * @minor_version: Minor version number (backwards compatible) 580 * Version 1 indicates GPU presence populated 581 * @gpus_present: Bitmask of GPUs present (on systems where GPU 582 * presence is detected through APSS) 583 * @cpu_throttle: Reason for limiting the max pstate 584 * @mem_throttle: Reason for throttling memory 585 * @quick_pwr_drop: Indicates if QPD is asserted 586 * @pwr_shifting_ratio: Indicates the current percentage of power to 587 * take away from the CPU vs GPU when shifting 588 * power to maintain a power cap. Value of 100 589 * means take all power from CPU. 590 * @pwr_cap_type: Indicates type of power cap in effect 591 * @hard_min_pwr_cap: Hard minimum system power cap in Watts. 592 * Guaranteed unless hardware failure 593 * @max_pwr_cap: Maximum allowed system power cap in Watts 594 * @cur_pwr_cap: Current system power cap 595 * @soft_min_pwr_cap: Soft powercap minimum. OCC may or may not be 596 * able to maintain this 597 * @spare/reserved: Unused data 598 * @cmd: Opal Command Buffer 599 * @rsp: OCC Response Buffer 600 */ 601 struct occ_dynamic_data { 602 uint8_t occ_state; 603 uint8_t major_version; 604 uint8_t minor_version; 605 uint8_t gpus_present; 606 union QEMU_PACKED { 607 struct QEMU_PACKED { /* Version 0x90 */ 608 uint8_t spare1; 609 } v9; 610 struct QEMU_PACKED { /* Version 0xA0 */ 611 uint8_t wof_enabled; 612 } v10; 613 }; 614 uint8_t cpu_throttle; 615 uint8_t mem_throttle; 616 uint8_t quick_pwr_drop; 617 uint8_t pwr_shifting_ratio; 618 uint8_t pwr_cap_type; 619 uint16_t hard_min_pwr_cap; 620 uint16_t max_pwr_cap; 621 uint16_t cur_pwr_cap; 622 uint16_t soft_min_pwr_cap; 623 uint8_t pad[110]; 624 struct opal_command_buffer cmd; 625 struct occ_response_buffer rsp; 626 } QEMU_PACKED; 627 628 enum occ_response_status { 629 OCC_RSP_SUCCESS = 0x00, 630 OCC_RSP_INVALID_COMMAND = 0x11, 631 OCC_RSP_INVALID_CMD_DATA_LENGTH = 0x12, 632 OCC_RSP_INVALID_DATA = 0x13, 633 OCC_RSP_INTERNAL_ERROR = 0x15, 634 }; 635 636 #define OCC_ROLE_SLAVE 0x00 637 #define OCC_ROLE_MASTER 0x01 638 639 #define OCC_FLAG_RSP_READY 0x01 640 #define OCC_FLAG_CMD_IN_PROGRESS 0x02 641 #define OPAL_FLAG_CMD_READY 0x80 642 643 #define PCAP_MAX_POWER_W 100 644 #define PCAP_SOFT_MIN_POWER_W 20 645 #define PCAP_HARD_MIN_POWER_W 10 646 647 static bool occ_write_static_data(PnvOCC *occ, 648 struct occ_pstate_table *static_data, 649 Error **errp) 650 { 651 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 652 PnvHomer *homer = occ->homer; 653 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 654 MemTxResult ret; 655 656 ret = address_space_write(&address_space_memory, static_addr, 657 MEMTXATTRS_UNSPECIFIED, static_data, 658 sizeof(*static_data)); 659 if (ret != MEMTX_OK) { 660 error_setg(errp, "OCC: cannot write OCC-OPAL static data"); 661 return false; 662 } 663 664 return true; 665 } 666 667 static bool occ_read_dynamic_data(PnvOCC *occ, 668 struct occ_dynamic_data *dynamic_data, 669 Error **errp) 670 { 671 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 672 PnvHomer *homer = occ->homer; 673 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 674 hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET; 675 MemTxResult ret; 676 677 ret = address_space_read(&address_space_memory, dynamic_addr, 678 MEMTXATTRS_UNSPECIFIED, dynamic_data, 679 sizeof(*dynamic_data)); 680 if (ret != MEMTX_OK) { 681 error_setg(errp, "OCC: cannot read OCC-OPAL dynamic data"); 682 return false; 683 } 684 685 return true; 686 } 687 688 static bool occ_write_dynamic_data(PnvOCC *occ, 689 struct occ_dynamic_data *dynamic_data, 690 Error **errp) 691 { 692 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 693 PnvHomer *homer = occ->homer; 694 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 695 hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET; 696 MemTxResult ret; 697 698 ret = address_space_write(&address_space_memory, dynamic_addr, 699 MEMTXATTRS_UNSPECIFIED, dynamic_data, 700 sizeof(*dynamic_data)); 701 if (ret != MEMTX_OK) { 702 error_setg(errp, "OCC: cannot write OCC-OPAL dynamic data"); 703 return false; 704 } 705 706 return true; 707 } 708 709 static bool occ_opal_send_response(PnvOCC *occ, 710 struct occ_dynamic_data *dynamic_data, 711 enum occ_response_status status, 712 uint8_t *data, uint16_t datalen) 713 { 714 struct opal_command_buffer *cmd = &dynamic_data->cmd; 715 struct occ_response_buffer *rsp = &dynamic_data->rsp; 716 717 rsp->request_id = cmd->request_id; 718 rsp->cmd = cmd->cmd; 719 rsp->status = status; 720 rsp->data_size = cpu_to_be16(datalen); 721 if (datalen) { 722 memcpy(rsp->data, data, datalen); 723 } 724 if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { 725 return false; 726 } 727 /* Would be a memory barrier here */ 728 rsp->flag = OCC_FLAG_RSP_READY; 729 cmd->flag = 0; 730 if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { 731 return false; 732 } 733 734 pnv_occ_raise_msg_irq(occ); 735 736 return true; 737 } 738 739 /* Returns error status */ 740 static bool occ_opal_process_command(PnvOCC *occ, 741 struct occ_dynamic_data *dynamic_data) 742 { 743 struct opal_command_buffer *cmd = &dynamic_data->cmd; 744 struct occ_response_buffer *rsp = &dynamic_data->rsp; 745 746 if (rsp->flag == 0) { 747 /* Spend one "tick" in the in-progress state */ 748 rsp->flag = OCC_FLAG_CMD_IN_PROGRESS; 749 return occ_write_dynamic_data(occ, dynamic_data, NULL); 750 } else if (rsp->flag != OCC_FLAG_CMD_IN_PROGRESS) { 751 return occ_opal_send_response(occ, dynamic_data, 752 OCC_RSP_INTERNAL_ERROR, 753 NULL, 0); 754 } 755 756 switch (cmd->cmd) { 757 case 0xD1: { /* SET_POWER_CAP */ 758 uint16_t data; 759 if (be16_to_cpu(cmd->data_size) != 2) { 760 return occ_opal_send_response(occ, dynamic_data, 761 OCC_RSP_INVALID_CMD_DATA_LENGTH, 762 (uint8_t *)&dynamic_data->cur_pwr_cap, 763 2); 764 } 765 data = be16_to_cpu(*(uint16_t *)cmd->data); 766 if (data == 0) { /* clear power cap */ 767 dynamic_data->pwr_cap_type = 0x00; /* none */ 768 data = PCAP_MAX_POWER_W; 769 } else { 770 dynamic_data->pwr_cap_type = 0x02; /* user set in-band */ 771 if (data < PCAP_HARD_MIN_POWER_W) { 772 data = PCAP_HARD_MIN_POWER_W; 773 } else if (data > PCAP_MAX_POWER_W) { 774 data = PCAP_MAX_POWER_W; 775 } 776 } 777 dynamic_data->cur_pwr_cap = cpu_to_be16(data); 778 return occ_opal_send_response(occ, dynamic_data, 779 OCC_RSP_SUCCESS, 780 (uint8_t *)&dynamic_data->cur_pwr_cap, 2); 781 } 782 783 default: 784 return occ_opal_send_response(occ, dynamic_data, 785 OCC_RSP_INVALID_COMMAND, 786 NULL, 0); 787 } 788 g_assert_not_reached(); 789 } 790 791 static bool occ_model_tick(PnvOCC *occ) 792 { 793 struct occ_dynamic_data dynamic_data; 794 795 if (!occ_read_dynamic_data(occ, &dynamic_data, NULL)) { 796 /* Can't move OCC state field to safe because we can't map it! */ 797 qemu_log("OCC: failed to read HOMER data, shutting down OCC\n"); 798 return false; 799 } 800 if (dynamic_data.cmd.flag == OPAL_FLAG_CMD_READY) { 801 if (!occ_opal_process_command(occ, &dynamic_data)) { 802 qemu_log("OCC: failed to write HOMER data, shutting down OCC\n"); 803 return false; 804 } 805 } 806 807 return true; 808 } 809 810 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp) 811 { 812 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 813 PnvHomer *homer = occ->homer; 814 PnvChip *chip = homer->chip; 815 struct occ_pstate_table static_data; 816 struct occ_dynamic_data dynamic_data; 817 int i; 818 819 memset(&static_data, 0, sizeof(static_data)); 820 static_data.valid = 1; 821 static_data.version = poc->opal_shared_memory_version; 822 switch (poc->opal_shared_memory_version) { 823 case 0x02: 824 static_data.v2.throttle = 0; 825 static_data.v2.pstate_min = -2; 826 static_data.v2.pstate_nom = -1; 827 static_data.v2.pstate_turbo = -1; 828 static_data.v2.pstate_ultra_turbo = 0; 829 static_data.v2.pstates[0].id = 0; 830 static_data.v2.pstates[1].freq_khz = cpu_to_be32(4000000); 831 static_data.v2.pstates[1].id = -1; 832 static_data.v2.pstates[1].freq_khz = cpu_to_be32(3000000); 833 static_data.v2.pstates[2].id = -2; 834 static_data.v2.pstates[2].freq_khz = cpu_to_be32(2000000); 835 for (i = 0; i < chip->nr_cores; i++) { 836 static_data.v2.core_max[i] = 1; 837 } 838 break; 839 case 0x90: 840 if (chip->chip_id == 0) { 841 static_data.v9.occ_role = OCC_ROLE_MASTER; 842 } else { 843 static_data.v9.occ_role = OCC_ROLE_SLAVE; 844 } 845 static_data.v9.pstate_min = 2; 846 static_data.v9.pstate_nom = 1; 847 static_data.v9.pstate_turbo = 1; 848 static_data.v9.pstate_ultra_turbo = 0; 849 static_data.v9.pstates[0].id = 0; 850 static_data.v9.pstates[0].freq_khz = cpu_to_be32(4000000); 851 static_data.v9.pstates[1].id = 1; 852 static_data.v9.pstates[1].freq_khz = cpu_to_be32(3000000); 853 static_data.v9.pstates[2].id = 2; 854 static_data.v9.pstates[2].freq_khz = cpu_to_be32(2000000); 855 for (i = 0; i < chip->nr_cores; i++) { 856 static_data.v9.core_max[i] = 1; 857 } 858 break; 859 case 0xA0: 860 if (chip->chip_id == 0) { 861 static_data.v10.occ_role = OCC_ROLE_MASTER; 862 } else { 863 static_data.v10.occ_role = OCC_ROLE_SLAVE; 864 } 865 static_data.v10.pstate_min = 4; 866 static_data.v10.pstate_fixed_freq = 3; 867 static_data.v10.pstate_base = 2; 868 static_data.v10.pstate_ultra_turbo = 0; 869 static_data.v10.pstate_fmax = 1; 870 static_data.v10.minor = 0x01; 871 static_data.v10.pstates[0].valid = 1; 872 static_data.v10.pstates[0].id = 0; 873 static_data.v10.pstates[0].freq_khz = cpu_to_be32(4200000); 874 static_data.v10.pstates[1].valid = 1; 875 static_data.v10.pstates[1].id = 1; 876 static_data.v10.pstates[1].freq_khz = cpu_to_be32(4000000); 877 static_data.v10.pstates[2].valid = 1; 878 static_data.v10.pstates[2].id = 2; 879 static_data.v10.pstates[2].freq_khz = cpu_to_be32(3800000); 880 static_data.v10.pstates[3].valid = 1; 881 static_data.v10.pstates[3].id = 3; 882 static_data.v10.pstates[3].freq_khz = cpu_to_be32(3000000); 883 static_data.v10.pstates[4].valid = 1; 884 static_data.v10.pstates[4].id = 4; 885 static_data.v10.pstates[4].freq_khz = cpu_to_be32(2000000); 886 for (i = 0; i < chip->nr_cores; i++) { 887 static_data.v10.core_max[i] = 1; 888 } 889 break; 890 default: 891 g_assert_not_reached(); 892 } 893 if (!occ_write_static_data(occ, &static_data, errp)) { 894 return false; 895 } 896 897 memset(&dynamic_data, 0, sizeof(dynamic_data)); 898 dynamic_data.occ_state = 0x3; /* active */ 899 dynamic_data.major_version = 0x0; 900 dynamic_data.hard_min_pwr_cap = cpu_to_be16(PCAP_HARD_MIN_POWER_W); 901 dynamic_data.max_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W); 902 dynamic_data.cur_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W); 903 dynamic_data.soft_min_pwr_cap = cpu_to_be16(PCAP_SOFT_MIN_POWER_W); 904 switch (poc->opal_shared_memory_version) { 905 case 0xA0: 906 dynamic_data.minor_version = 0x1; 907 dynamic_data.v10.wof_enabled = 0x1; 908 break; 909 case 0x90: 910 dynamic_data.minor_version = 0x1; 911 break; 912 case 0x02: 913 dynamic_data.minor_version = 0x0; 914 break; 915 default: 916 g_assert_not_reached(); 917 } 918 if (!occ_write_dynamic_data(occ, &dynamic_data, errp)) { 919 return false; 920 } 921 922 return true; 923 } 924