1 /* 2 * QEMU PowerPC PowerNV Emulation of a few OCC related registers 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License, version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "target/ppc/cpu.h" 21 #include "qapi/error.h" 22 #include "qemu/log.h" 23 #include "qemu/module.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/ppc/pnv.h" 27 #include "hw/ppc/pnv_chip.h" 28 #include "hw/ppc/pnv_xscom.h" 29 #include "hw/ppc/pnv_occ.h" 30 31 #define P8_HOMER_OPAL_DATA_OFFSET 0x1F8000 32 #define P9_HOMER_OPAL_DATA_OFFSET 0x0E2000 33 34 #define OCB_OCI_OCCMISC 0x4020 35 #define OCB_OCI_OCCMISC_AND 0x4021 36 #define OCB_OCI_OCCMISC_OR 0x4022 37 #define OCCMISC_PSI_IRQ PPC_BIT(0) 38 #define OCCMISC_IRQ_SHMEM PPC_BIT(3) 39 40 /* OCC sensors */ 41 #define OCC_SENSOR_DATA_BLOCK_OFFSET 0x0000 42 #define OCC_SENSOR_DATA_VALID 0x0001 43 #define OCC_SENSOR_DATA_VERSION 0x0002 44 #define OCC_SENSOR_DATA_READING_VERSION 0x0004 45 #define OCC_SENSOR_DATA_NR_SENSORS 0x0008 46 #define OCC_SENSOR_DATA_NAMES_OFFSET 0x0010 47 #define OCC_SENSOR_DATA_READING_PING_OFFSET 0x0014 48 #define OCC_SENSOR_DATA_READING_PONG_OFFSET 0x000c 49 #define OCC_SENSOR_DATA_NAME_LENGTH 0x000d 50 #define OCC_SENSOR_NAME_STRUCTURE_TYPE 0x0023 51 #define OCC_SENSOR_LOC_CORE 0x0022 52 #define OCC_SENSOR_LOC_GPU 0x0020 53 #define OCC_SENSOR_TYPE_POWER 0x0003 54 #define OCC_SENSOR_NAME 0x0005 55 #define HWMON_SENSORS_MASK 0x001e 56 57 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) 58 { 59 val &= PPC_BITMASK(0, 18); /* Mask out unimplemented bits */ 60 61 occ->occmisc = val; 62 63 /* 64 * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear 65 * how that is handled in PSI so it is level-triggered here, which is not 66 * really correct (but skiboot is okay with it). 67 */ 68 qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); 69 } 70 71 static void pnv_occ_raise_msg_irq(PnvOCC *occ) 72 { 73 pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHMEM); 74 } 75 76 static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr, 77 unsigned size) 78 { 79 PnvOCC *occ = PNV_OCC(opaque); 80 uint32_t offset = addr >> 3; 81 uint64_t val = 0; 82 83 switch (offset) { 84 case OCB_OCI_OCCMISC: 85 val = occ->occmisc; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 89 HWADDR_PRIx "\n", addr >> 3); 90 } 91 return val; 92 } 93 94 static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr, 95 uint64_t val, unsigned size) 96 { 97 PnvOCC *occ = PNV_OCC(opaque); 98 uint32_t offset = addr >> 3; 99 100 switch (offset) { 101 case OCB_OCI_OCCMISC_AND: 102 pnv_occ_set_misc(occ, occ->occmisc & val); 103 break; 104 case OCB_OCI_OCCMISC_OR: 105 pnv_occ_set_misc(occ, occ->occmisc | val); 106 break; 107 case OCB_OCI_OCCMISC: 108 pnv_occ_set_misc(occ, val); 109 break; 110 default: 111 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 112 HWADDR_PRIx "\n", addr >> 3); 113 } 114 } 115 116 static uint64_t pnv_occ_common_area_read(void *opaque, hwaddr addr, 117 unsigned width) 118 { 119 switch (addr) { 120 /* 121 * occ-sensor sanity check that asserts the sensor 122 * header block 123 */ 124 case OCC_SENSOR_DATA_BLOCK_OFFSET: 125 case OCC_SENSOR_DATA_VALID: 126 case OCC_SENSOR_DATA_VERSION: 127 case OCC_SENSOR_DATA_READING_VERSION: 128 case OCC_SENSOR_DATA_NR_SENSORS: 129 case OCC_SENSOR_DATA_NAMES_OFFSET: 130 case OCC_SENSOR_DATA_READING_PING_OFFSET: 131 case OCC_SENSOR_DATA_READING_PONG_OFFSET: 132 case OCC_SENSOR_NAME_STRUCTURE_TYPE: 133 return 1; 134 case OCC_SENSOR_DATA_NAME_LENGTH: 135 return 0x30; 136 case OCC_SENSOR_LOC_CORE: 137 return 0x0040; 138 case OCC_SENSOR_TYPE_POWER: 139 return 0x0080; 140 case OCC_SENSOR_NAME: 141 return 0x1000; 142 case HWMON_SENSORS_MASK: 143 case OCC_SENSOR_LOC_GPU: 144 return 0x8e00; 145 } 146 return 0; 147 } 148 149 static void pnv_occ_common_area_write(void *opaque, hwaddr addr, 150 uint64_t val, unsigned width) 151 { 152 /* callback function defined to occ common area write */ 153 return; 154 } 155 156 static const MemoryRegionOps pnv_occ_power8_xscom_ops = { 157 .read = pnv_occ_power8_xscom_read, 158 .write = pnv_occ_power8_xscom_write, 159 .valid.min_access_size = 8, 160 .valid.max_access_size = 8, 161 .impl.min_access_size = 8, 162 .impl.max_access_size = 8, 163 .endianness = DEVICE_BIG_ENDIAN, 164 }; 165 166 const MemoryRegionOps pnv_occ_sram_ops = { 167 .read = pnv_occ_common_area_read, 168 .write = pnv_occ_common_area_write, 169 .valid.min_access_size = 1, 170 .valid.max_access_size = 8, 171 .impl.min_access_size = 1, 172 .impl.max_access_size = 8, 173 .endianness = DEVICE_BIG_ENDIAN, 174 }; 175 176 static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) 177 { 178 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 179 DeviceClass *dc = DEVICE_CLASS(klass); 180 181 dc->desc = "PowerNV OCC Controller (POWER8)"; 182 poc->opal_shared_memory_offset = P8_HOMER_OPAL_DATA_OFFSET; 183 poc->opal_shared_memory_version = 0x02; 184 poc->xscom_size = PNV_XSCOM_OCC_SIZE; 185 poc->xscom_ops = &pnv_occ_power8_xscom_ops; 186 } 187 188 static const TypeInfo pnv_occ_power8_type_info = { 189 .name = TYPE_PNV8_OCC, 190 .parent = TYPE_PNV_OCC, 191 .instance_size = sizeof(PnvOCC), 192 .class_init = pnv_occ_power8_class_init, 193 }; 194 195 #define P9_OCB_OCI_OCCMISC 0x6080 196 #define P9_OCB_OCI_OCCMISC_CLEAR 0x6081 197 #define P9_OCB_OCI_OCCMISC_OR 0x6082 198 199 200 static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr, 201 unsigned size) 202 { 203 PnvOCC *occ = PNV_OCC(opaque); 204 uint32_t offset = addr >> 3; 205 uint64_t val = 0; 206 207 switch (offset) { 208 case P9_OCB_OCI_OCCMISC: 209 val = occ->occmisc; 210 break; 211 default: 212 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 213 HWADDR_PRIx "\n", addr >> 3); 214 } 215 return val; 216 } 217 218 static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr, 219 uint64_t val, unsigned size) 220 { 221 PnvOCC *occ = PNV_OCC(opaque); 222 uint32_t offset = addr >> 3; 223 224 switch (offset) { 225 case P9_OCB_OCI_OCCMISC_CLEAR: 226 pnv_occ_set_misc(occ, 0); 227 break; 228 case P9_OCB_OCI_OCCMISC_OR: 229 pnv_occ_set_misc(occ, occ->occmisc | val); 230 break; 231 case P9_OCB_OCI_OCCMISC: 232 pnv_occ_set_misc(occ, val); 233 break; 234 default: 235 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 236 HWADDR_PRIx "\n", addr >> 3); 237 } 238 } 239 240 static const MemoryRegionOps pnv_occ_power9_xscom_ops = { 241 .read = pnv_occ_power9_xscom_read, 242 .write = pnv_occ_power9_xscom_write, 243 .valid.min_access_size = 8, 244 .valid.max_access_size = 8, 245 .impl.min_access_size = 8, 246 .impl.max_access_size = 8, 247 .endianness = DEVICE_BIG_ENDIAN, 248 }; 249 250 static void pnv_occ_power9_class_init(ObjectClass *klass, void *data) 251 { 252 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 253 DeviceClass *dc = DEVICE_CLASS(klass); 254 255 dc->desc = "PowerNV OCC Controller (POWER9)"; 256 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; 257 poc->opal_shared_memory_version = 0x90; 258 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; 259 poc->xscom_ops = &pnv_occ_power9_xscom_ops; 260 assert(!dc->user_creatable); 261 } 262 263 static const TypeInfo pnv_occ_power9_type_info = { 264 .name = TYPE_PNV9_OCC, 265 .parent = TYPE_PNV_OCC, 266 .instance_size = sizeof(PnvOCC), 267 .class_init = pnv_occ_power9_class_init, 268 }; 269 270 static void pnv_occ_power10_class_init(ObjectClass *klass, void *data) 271 { 272 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 273 DeviceClass *dc = DEVICE_CLASS(klass); 274 275 dc->desc = "PowerNV OCC Controller (POWER10)"; 276 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; 277 poc->opal_shared_memory_version = 0xA0; 278 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; 279 poc->xscom_ops = &pnv_occ_power9_xscom_ops; 280 assert(!dc->user_creatable); 281 } 282 283 static const TypeInfo pnv_occ_power10_type_info = { 284 .name = TYPE_PNV10_OCC, 285 .parent = TYPE_PNV_OCC, 286 .class_init = pnv_occ_power10_class_init, 287 }; 288 289 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp); 290 static bool occ_model_tick(PnvOCC *occ); 291 292 /* Relatively arbitrary */ 293 #define OCC_POLL_MS 100 294 295 static void occ_state_machine_timer(void *opaque) 296 { 297 PnvOCC *occ = opaque; 298 uint64_t next = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + OCC_POLL_MS; 299 300 if (occ_model_tick(occ)) { 301 timer_mod(&occ->state_machine_timer, next); 302 } 303 } 304 305 static void pnv_occ_realize(DeviceState *dev, Error **errp) 306 { 307 PnvOCC *occ = PNV_OCC(dev); 308 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 309 PnvHomer *homer = occ->homer; 310 311 assert(homer); 312 313 if (!occ_init_homer_memory(occ, errp)) { 314 return; 315 } 316 317 occ->occmisc = 0; 318 319 /* XScom region for OCC registers */ 320 pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, 321 occ, "xscom-occ", poc->xscom_size); 322 323 /* OCC common area mmio region for OCC SRAM registers */ 324 memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops, 325 occ, "occ-common-area", 326 PNV_OCC_SENSOR_DATA_BLOCK_SIZE); 327 328 qdev_init_gpio_out(dev, &occ->psi_irq, 1); 329 330 timer_init_ms(&occ->state_machine_timer, QEMU_CLOCK_VIRTUAL, 331 occ_state_machine_timer, occ); 332 timer_mod(&occ->state_machine_timer, OCC_POLL_MS); 333 } 334 335 static const Property pnv_occ_properties[] = { 336 DEFINE_PROP_LINK("homer", PnvOCC, homer, TYPE_PNV_HOMER, PnvHomer *), 337 }; 338 339 static void pnv_occ_class_init(ObjectClass *klass, void *data) 340 { 341 DeviceClass *dc = DEVICE_CLASS(klass); 342 343 dc->realize = pnv_occ_realize; 344 device_class_set_props(dc, pnv_occ_properties); 345 dc->user_creatable = false; 346 } 347 348 static const TypeInfo pnv_occ_type_info = { 349 .name = TYPE_PNV_OCC, 350 .parent = TYPE_DEVICE, 351 .instance_size = sizeof(PnvOCC), 352 .class_init = pnv_occ_class_init, 353 .class_size = sizeof(PnvOCCClass), 354 .abstract = true, 355 }; 356 357 static void pnv_occ_register_types(void) 358 { 359 type_register_static(&pnv_occ_type_info); 360 type_register_static(&pnv_occ_power8_type_info); 361 type_register_static(&pnv_occ_power9_type_info); 362 type_register_static(&pnv_occ_power10_type_info); 363 } 364 365 type_init(pnv_occ_register_types); 366 367 /* From skiboot/hw/occ.c with tab to space conversion */ 368 /* OCC Communication Area for PStates */ 369 370 #define OPAL_DYNAMIC_DATA_OFFSET 0x0B80 371 /* relative to HOMER_OPAL_DATA_OFFSET */ 372 373 #define MAX_PSTATES 256 374 #define MAX_P8_CORES 12 375 #define MAX_P9_CORES 24 376 #define MAX_P10_CORES 32 377 378 #define MAX_OPAL_CMD_DATA_LENGTH 4090 379 #define MAX_OCC_RSP_DATA_LENGTH 8698 380 381 #define P8_PIR_CORE_MASK 0xFFF8 382 #define P9_PIR_QUAD_MASK 0xFFF0 383 #define P10_PIR_CHIP_MASK 0x0000 384 #define FREQ_MAX_IN_DOMAIN 0 385 #define FREQ_MOST_RECENTLY_SET 1 386 387 #define u8 uint8_t 388 #define s8 int8_t 389 #define u16 uint16_t 390 #define s16 int16_t 391 #define u32 uint32_t 392 #define s32 int32_t 393 #define u64 uint64_t 394 #define s64 int64_t 395 #define __be16 uint16_t 396 #define __be32 uint32_t 397 #ifndef __packed 398 #define __packed QEMU_PACKED 399 #endif /* !__packed */ 400 401 /** 402 * OCC-OPAL Shared Memory Region 403 * 404 * Reference document : 405 * https://github.com/open-power/docs/blob/master/occ/OCC_OpenPwr_FW_Interfaces.pdf 406 * 407 * Supported layout versions: 408 * - 0x01, 0x02 : P8 409 * https://github.com/open-power/occ/blob/master_p8/src/occ/proc/proc_pstate.h 410 * 411 * - 0x90 : P9 412 * https://github.com/open-power/occ/blob/master/src/occ_405/proc/proc_pstate.h 413 * In 0x90 the data is separated into :- 414 * -- Static Data (struct occ_pstate_table): Data is written once by OCC 415 * -- Dynamic Data (struct occ_dynamic_data): Data is updated at runtime 416 * 417 * struct occ_pstate_table - Pstate table layout 418 * @valid: Indicates if data is valid 419 * @version: Layout version [Major/Minor] 420 * @v2.throttle: Reason for limiting the max pstate 421 * @v9.occ_role: OCC role (Master/Slave) 422 * @v#.pstate_min: Minimum pstate ever allowed 423 * @v#.pstate_nom: Nominal pstate 424 * @v#.pstate_turbo: Maximum turbo pstate 425 * @v#.pstate_ultra_turbo: Maximum ultra turbo pstate and the maximum 426 * pstate ever allowed 427 * @v#.pstates: Pstate-id and frequency list from Pmax to Pmin 428 * @v#.pstates.id: Pstate-id 429 * @v#.pstates.flags: Pstate-flag(reserved) 430 * @v2.pstates.vdd: Voltage Identifier 431 * @v2.pstates.vcs: Voltage Identifier 432 * @v#.pstates.freq_khz: Frequency in KHz 433 * @v#.core_max[1..N]: Max pstate with N active cores 434 * @spare/reserved/pad: Unused data 435 */ 436 struct occ_pstate_table { 437 u8 valid; 438 u8 version; 439 union __packed { 440 struct __packed { /* Version 0x01 and 0x02 */ 441 u8 throttle; 442 s8 pstate_min; 443 s8 pstate_nom; 444 s8 pstate_turbo; 445 s8 pstate_ultra_turbo; 446 u8 spare; 447 u64 reserved; 448 struct __packed { 449 s8 id; 450 u8 flags; 451 u8 vdd; 452 u8 vcs; 453 __be32 freq_khz; 454 } pstates[MAX_PSTATES]; 455 s8 core_max[MAX_P8_CORES]; 456 u8 pad[100]; 457 } v2; 458 struct __packed { /* Version 0x90 */ 459 u8 occ_role; 460 u8 pstate_min; 461 u8 pstate_nom; 462 u8 pstate_turbo; 463 u8 pstate_ultra_turbo; 464 u8 spare; 465 u64 reserved1; 466 u64 reserved2; 467 struct __packed { 468 u8 id; 469 u8 flags; 470 u16 reserved; 471 __be32 freq_khz; 472 } pstates[MAX_PSTATES]; 473 u8 core_max[MAX_P9_CORES]; 474 u8 pad[56]; 475 } v9; 476 struct __packed { /* Version 0xA0 */ 477 u8 occ_role; 478 u8 pstate_min; 479 u8 pstate_fixed_freq; 480 u8 pstate_base; 481 u8 pstate_ultra_turbo; 482 u8 pstate_fmax; 483 u8 minor; 484 u8 pstate_bottom_throttle; 485 u8 spare; 486 u8 spare1; 487 u32 reserved_32; 488 u64 reserved_64; 489 struct __packed { 490 u8 id; 491 u8 valid; 492 u16 reserved; 493 __be32 freq_khz; 494 } pstates[MAX_PSTATES]; 495 u8 core_max[MAX_P10_CORES]; 496 u8 pad[48]; 497 } v10; 498 }; 499 } __packed; 500 501 /** 502 * OPAL-OCC Command Response Interface 503 * 504 * OPAL-OCC Command Buffer 505 * 506 * --------------------------------------------------------------------- 507 * | OPAL | Cmd | OPAL | | Cmd Data | Cmd Data | OPAL | 508 * | Cmd | Request | OCC | Reserved | Length | Length | Cmd | 509 * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | 510 * --------------------------------------------------------------------- 511 * | ….OPAL Command Data up to max of Cmd Data Length 4090 bytes | 512 * | | 513 * --------------------------------------------------------------------- 514 * 515 * OPAL Command Flag 516 * 517 * ----------------------------------------------------------------- 518 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | 519 * | (msb) | | | | | | | (lsb) | 520 * ----------------------------------------------------------------- 521 * |Cmd | | | | | | | | 522 * |Ready | | | | | | | | 523 * ----------------------------------------------------------------- 524 * 525 * struct opal_command_buffer - Defines the layout of OPAL command buffer 526 * @flag: Provides general status of the command 527 * @request_id: Token to identify request 528 * @cmd: Command sent 529 * @data_size: Command data length 530 * @data: Command specific data 531 * @spare: Unused byte 532 */ 533 struct opal_command_buffer { 534 u8 flag; 535 u8 request_id; 536 u8 cmd; 537 u8 spare; 538 __be16 data_size; 539 u8 data[MAX_OPAL_CMD_DATA_LENGTH]; 540 } __packed; 541 542 /** 543 * OPAL-OCC Response Buffer 544 * 545 * --------------------------------------------------------------------- 546 * | OCC | Cmd | OPAL | Response | Rsp Data | Rsp Data | OPAL | 547 * | Rsp | Request | OCC | Status | Length | Length | Rsp | 548 * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | 549 * --------------------------------------------------------------------- 550 * | ….OPAL Response Data up to max of Rsp Data Length 8698 bytes | 551 * | | 552 * --------------------------------------------------------------------- 553 * 554 * OCC Response Flag 555 * 556 * ----------------------------------------------------------------- 557 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | 558 * | (msb) | | | | | | | (lsb) | 559 * ----------------------------------------------------------------- 560 * | | | | | | |OCC in | Rsp | 561 * | | | | | | |progress|Ready | 562 * ----------------------------------------------------------------- 563 * 564 * struct occ_response_buffer - Defines the layout of OCC response buffer 565 * @flag: Provides general status of the response 566 * @request_id: Token to identify request 567 * @cmd: Command requested 568 * @status: Indicates success/failure status of 569 * the command 570 * @data_size: Response data length 571 * @data: Response specific data 572 */ 573 struct occ_response_buffer { 574 u8 flag; 575 u8 request_id; 576 u8 cmd; 577 u8 status; 578 __be16 data_size; 579 u8 data[MAX_OCC_RSP_DATA_LENGTH]; 580 } __packed; 581 582 /** 583 * OCC-OPAL Shared Memory Interface Dynamic Data Vx90 584 * 585 * struct occ_dynamic_data - Contains runtime attributes 586 * @occ_state: Current state of OCC 587 * @major_version: Major version number 588 * @minor_version: Minor version number (backwards compatible) 589 * Version 1 indicates GPU presence populated 590 * @gpus_present: Bitmask of GPUs present (on systems where GPU 591 * presence is detected through APSS) 592 * @cpu_throttle: Reason for limiting the max pstate 593 * @mem_throttle: Reason for throttling memory 594 * @quick_pwr_drop: Indicates if QPD is asserted 595 * @pwr_shifting_ratio: Indicates the current percentage of power to 596 * take away from the CPU vs GPU when shifting 597 * power to maintain a power cap. Value of 100 598 * means take all power from CPU. 599 * @pwr_cap_type: Indicates type of power cap in effect 600 * @hard_min_pwr_cap: Hard minimum system power cap in Watts. 601 * Guaranteed unless hardware failure 602 * @max_pwr_cap: Maximum allowed system power cap in Watts 603 * @cur_pwr_cap: Current system power cap 604 * @soft_min_pwr_cap: Soft powercap minimum. OCC may or may not be 605 * able to maintain this 606 * @spare/reserved: Unused data 607 * @cmd: Opal Command Buffer 608 * @rsp: OCC Response Buffer 609 */ 610 struct occ_dynamic_data { 611 u8 occ_state; 612 u8 major_version; 613 u8 minor_version; 614 u8 gpus_present; 615 union __packed { 616 struct __packed { /* Version 0x90 */ 617 u8 spare1; 618 } v9; 619 struct __packed { /* Version 0xA0 */ 620 u8 wof_enabled; 621 } v10; 622 }; 623 u8 cpu_throttle; 624 u8 mem_throttle; 625 u8 quick_pwr_drop; 626 u8 pwr_shifting_ratio; 627 u8 pwr_cap_type; 628 __be16 hard_min_pwr_cap; 629 __be16 max_pwr_cap; 630 __be16 cur_pwr_cap; 631 __be16 soft_min_pwr_cap; 632 u8 pad[110]; 633 struct opal_command_buffer cmd; 634 struct occ_response_buffer rsp; 635 } __packed; 636 637 enum occ_response_status { 638 OCC_RSP_SUCCESS = 0x00, 639 OCC_RSP_INVALID_COMMAND = 0x11, 640 OCC_RSP_INVALID_CMD_DATA_LENGTH = 0x12, 641 OCC_RSP_INVALID_DATA = 0x13, 642 OCC_RSP_INTERNAL_ERROR = 0x15, 643 }; 644 645 #define OCC_ROLE_SLAVE 0x00 646 #define OCC_ROLE_MASTER 0x01 647 648 #define OCC_FLAG_RSP_READY 0x01 649 #define OCC_FLAG_CMD_IN_PROGRESS 0x02 650 #define OPAL_FLAG_CMD_READY 0x80 651 652 #define PCAP_MAX_POWER_W 100 653 #define PCAP_SOFT_MIN_POWER_W 20 654 #define PCAP_HARD_MIN_POWER_W 10 655 656 static bool occ_write_static_data(PnvOCC *occ, 657 struct occ_pstate_table *static_data, 658 Error **errp) 659 { 660 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 661 PnvHomer *homer = occ->homer; 662 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 663 MemTxResult ret; 664 665 ret = address_space_write(&address_space_memory, static_addr, 666 MEMTXATTRS_UNSPECIFIED, static_data, 667 sizeof(*static_data)); 668 if (ret != MEMTX_OK) { 669 error_setg(errp, "OCC: cannot write OCC-OPAL static data"); 670 return false; 671 } 672 673 return true; 674 } 675 676 static bool occ_read_dynamic_data(PnvOCC *occ, 677 struct occ_dynamic_data *dynamic_data, 678 Error **errp) 679 { 680 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 681 PnvHomer *homer = occ->homer; 682 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 683 hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET; 684 MemTxResult ret; 685 686 ret = address_space_read(&address_space_memory, dynamic_addr, 687 MEMTXATTRS_UNSPECIFIED, dynamic_data, 688 sizeof(*dynamic_data)); 689 if (ret != MEMTX_OK) { 690 error_setg(errp, "OCC: cannot read OCC-OPAL dynamic data"); 691 return false; 692 } 693 694 return true; 695 } 696 697 static bool occ_write_dynamic_data(PnvOCC *occ, 698 struct occ_dynamic_data *dynamic_data, 699 Error **errp) 700 { 701 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 702 PnvHomer *homer = occ->homer; 703 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 704 hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET; 705 MemTxResult ret; 706 707 ret = address_space_write(&address_space_memory, dynamic_addr, 708 MEMTXATTRS_UNSPECIFIED, dynamic_data, 709 sizeof(*dynamic_data)); 710 if (ret != MEMTX_OK) { 711 error_setg(errp, "OCC: cannot write OCC-OPAL dynamic data"); 712 return false; 713 } 714 715 return true; 716 } 717 718 static bool occ_opal_send_response(PnvOCC *occ, 719 struct occ_dynamic_data *dynamic_data, 720 enum occ_response_status status, 721 uint8_t *data, uint16_t datalen) 722 { 723 struct opal_command_buffer *cmd = &dynamic_data->cmd; 724 struct occ_response_buffer *rsp = &dynamic_data->rsp; 725 726 rsp->request_id = cmd->request_id; 727 rsp->cmd = cmd->cmd; 728 rsp->status = status; 729 rsp->data_size = cpu_to_be16(datalen); 730 if (datalen) { 731 memcpy(rsp->data, data, datalen); 732 } 733 if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { 734 return false; 735 } 736 /* Would be a memory barrier here */ 737 rsp->flag = OCC_FLAG_RSP_READY; 738 cmd->flag = 0; 739 if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { 740 return false; 741 } 742 743 pnv_occ_raise_msg_irq(occ); 744 745 return true; 746 } 747 748 /* Returns error status */ 749 static bool occ_opal_process_command(PnvOCC *occ, 750 struct occ_dynamic_data *dynamic_data) 751 { 752 struct opal_command_buffer *cmd = &dynamic_data->cmd; 753 struct occ_response_buffer *rsp = &dynamic_data->rsp; 754 755 if (rsp->flag == 0) { 756 /* Spend one "tick" in the in-progress state */ 757 rsp->flag = OCC_FLAG_CMD_IN_PROGRESS; 758 return occ_write_dynamic_data(occ, dynamic_data, NULL); 759 } else if (rsp->flag != OCC_FLAG_CMD_IN_PROGRESS) { 760 return occ_opal_send_response(occ, dynamic_data, 761 OCC_RSP_INTERNAL_ERROR, 762 NULL, 0); 763 } 764 765 switch (cmd->cmd) { 766 case 0xD1: { /* SET_POWER_CAP */ 767 uint16_t data; 768 if (be16_to_cpu(cmd->data_size) != 2) { 769 return occ_opal_send_response(occ, dynamic_data, 770 OCC_RSP_INVALID_CMD_DATA_LENGTH, 771 (uint8_t *)&dynamic_data->cur_pwr_cap, 772 2); 773 } 774 data = be16_to_cpu(*(uint16_t *)cmd->data); 775 if (data == 0) { /* clear power cap */ 776 dynamic_data->pwr_cap_type = 0x00; /* none */ 777 data = PCAP_MAX_POWER_W; 778 } else { 779 dynamic_data->pwr_cap_type = 0x02; /* user set in-band */ 780 if (data < PCAP_HARD_MIN_POWER_W) { 781 data = PCAP_HARD_MIN_POWER_W; 782 } else if (data > PCAP_MAX_POWER_W) { 783 data = PCAP_MAX_POWER_W; 784 } 785 } 786 dynamic_data->cur_pwr_cap = cpu_to_be16(data); 787 return occ_opal_send_response(occ, dynamic_data, 788 OCC_RSP_SUCCESS, 789 (uint8_t *)&dynamic_data->cur_pwr_cap, 2); 790 } 791 792 default: 793 return occ_opal_send_response(occ, dynamic_data, 794 OCC_RSP_INVALID_COMMAND, 795 NULL, 0); 796 } 797 g_assert_not_reached(); 798 } 799 800 static bool occ_model_tick(PnvOCC *occ) 801 { 802 struct occ_dynamic_data dynamic_data; 803 804 if (!occ_read_dynamic_data(occ, &dynamic_data, NULL)) { 805 /* Can't move OCC state field to safe because we can't map it! */ 806 qemu_log("OCC: failed to read HOMER data, shutting down OCC\n"); 807 return false; 808 } 809 if (dynamic_data.cmd.flag == OPAL_FLAG_CMD_READY) { 810 if (!occ_opal_process_command(occ, &dynamic_data)) { 811 qemu_log("OCC: failed to write HOMER data, shutting down OCC\n"); 812 return false; 813 } 814 } 815 816 return true; 817 } 818 819 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp) 820 { 821 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 822 PnvHomer *homer = occ->homer; 823 PnvChip *chip = homer->chip; 824 struct occ_pstate_table static_data; 825 struct occ_dynamic_data dynamic_data; 826 int i; 827 828 memset(&static_data, 0, sizeof(static_data)); 829 static_data.valid = 1; 830 static_data.version = poc->opal_shared_memory_version; 831 switch (poc->opal_shared_memory_version) { 832 case 0x02: 833 static_data.v2.throttle = 0; 834 static_data.v2.pstate_min = -2; 835 static_data.v2.pstate_nom = -1; 836 static_data.v2.pstate_turbo = -1; 837 static_data.v2.pstate_ultra_turbo = 0; 838 static_data.v2.pstates[0].id = 0; 839 static_data.v2.pstates[1].freq_khz = cpu_to_be32(4000000); 840 static_data.v2.pstates[1].id = -1; 841 static_data.v2.pstates[1].freq_khz = cpu_to_be32(3000000); 842 static_data.v2.pstates[2].id = -2; 843 static_data.v2.pstates[2].freq_khz = cpu_to_be32(2000000); 844 for (i = 0; i < chip->nr_cores; i++) { 845 static_data.v2.core_max[i] = 1; 846 } 847 break; 848 case 0x90: 849 if (chip->chip_id == 0) { 850 static_data.v9.occ_role = OCC_ROLE_MASTER; 851 } else { 852 static_data.v9.occ_role = OCC_ROLE_SLAVE; 853 } 854 static_data.v9.pstate_min = 2; 855 static_data.v9.pstate_nom = 1; 856 static_data.v9.pstate_turbo = 1; 857 static_data.v9.pstate_ultra_turbo = 0; 858 static_data.v9.pstates[0].id = 0; 859 static_data.v9.pstates[0].freq_khz = cpu_to_be32(4000000); 860 static_data.v9.pstates[1].id = 1; 861 static_data.v9.pstates[1].freq_khz = cpu_to_be32(3000000); 862 static_data.v9.pstates[2].id = 2; 863 static_data.v9.pstates[2].freq_khz = cpu_to_be32(2000000); 864 for (i = 0; i < chip->nr_cores; i++) { 865 static_data.v9.core_max[i] = 1; 866 } 867 break; 868 case 0xA0: 869 if (chip->chip_id == 0) { 870 static_data.v10.occ_role = OCC_ROLE_MASTER; 871 } else { 872 static_data.v10.occ_role = OCC_ROLE_SLAVE; 873 } 874 static_data.v10.pstate_min = 4; 875 static_data.v10.pstate_fixed_freq = 3; 876 static_data.v10.pstate_base = 2; 877 static_data.v10.pstate_ultra_turbo = 0; 878 static_data.v10.pstate_fmax = 1; 879 static_data.v10.minor = 0x01; 880 static_data.v10.pstates[0].valid = 1; 881 static_data.v10.pstates[0].id = 0; 882 static_data.v10.pstates[0].freq_khz = cpu_to_be32(4200000); 883 static_data.v10.pstates[1].valid = 1; 884 static_data.v10.pstates[1].id = 1; 885 static_data.v10.pstates[1].freq_khz = cpu_to_be32(4000000); 886 static_data.v10.pstates[2].valid = 1; 887 static_data.v10.pstates[2].id = 2; 888 static_data.v10.pstates[2].freq_khz = cpu_to_be32(3800000); 889 static_data.v10.pstates[3].valid = 1; 890 static_data.v10.pstates[3].id = 3; 891 static_data.v10.pstates[3].freq_khz = cpu_to_be32(3000000); 892 static_data.v10.pstates[4].valid = 1; 893 static_data.v10.pstates[4].id = 4; 894 static_data.v10.pstates[4].freq_khz = cpu_to_be32(2000000); 895 for (i = 0; i < chip->nr_cores; i++) { 896 static_data.v10.core_max[i] = 1; 897 } 898 break; 899 default: 900 g_assert_not_reached(); 901 } 902 if (!occ_write_static_data(occ, &static_data, errp)) { 903 return false; 904 } 905 906 memset(&dynamic_data, 0, sizeof(dynamic_data)); 907 dynamic_data.occ_state = 0x3; /* active */ 908 dynamic_data.major_version = 0x0; 909 dynamic_data.hard_min_pwr_cap = cpu_to_be16(PCAP_HARD_MIN_POWER_W); 910 dynamic_data.max_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W); 911 dynamic_data.cur_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W); 912 dynamic_data.soft_min_pwr_cap = cpu_to_be16(PCAP_SOFT_MIN_POWER_W); 913 switch (poc->opal_shared_memory_version) { 914 case 0xA0: 915 dynamic_data.minor_version = 0x1; 916 dynamic_data.v10.wof_enabled = 0x1; 917 break; 918 case 0x90: 919 dynamic_data.minor_version = 0x1; 920 break; 921 case 0x02: 922 dynamic_data.minor_version = 0x0; 923 break; 924 default: 925 g_assert_not_reached(); 926 } 927 if (!occ_write_dynamic_data(occ, &dynamic_data, errp)) { 928 return false; 929 } 930 931 return true; 932 } 933