1 /* 2 * QEMU PowerPC PowerNV LPC controller 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/sysemu.h" 22 #include "target/ppc/cpu.h" 23 #include "qapi/error.h" 24 #include "qemu/log.h" 25 #include "hw/isa/isa.h" 26 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_lpc.h" 29 #include "hw/ppc/pnv_xscom.h" 30 #include "hw/ppc/fdt.h" 31 32 #include <libfdt.h> 33 34 enum { 35 ECCB_CTL = 0, 36 ECCB_RESET = 1, 37 ECCB_STAT = 2, 38 ECCB_DATA = 3, 39 }; 40 41 /* OPB Master LS registers */ 42 #define OPB_MASTER_LS_IRQ_STAT 0x50 43 #define OPB_MASTER_IRQ_LPC 0x00000800 44 #define OPB_MASTER_LS_IRQ_MASK 0x54 45 #define OPB_MASTER_LS_IRQ_POL 0x58 46 #define OPB_MASTER_LS_IRQ_INPUT 0x5c 47 48 /* LPC HC registers */ 49 #define LPC_HC_FW_SEG_IDSEL 0x24 50 #define LPC_HC_FW_RD_ACC_SIZE 0x28 51 #define LPC_HC_FW_RD_1B 0x00000000 52 #define LPC_HC_FW_RD_2B 0x01000000 53 #define LPC_HC_FW_RD_4B 0x02000000 54 #define LPC_HC_FW_RD_16B 0x04000000 55 #define LPC_HC_FW_RD_128B 0x07000000 56 #define LPC_HC_IRQSER_CTRL 0x30 57 #define LPC_HC_IRQSER_EN 0x80000000 58 #define LPC_HC_IRQSER_QMODE 0x40000000 59 #define LPC_HC_IRQSER_START_MASK 0x03000000 60 #define LPC_HC_IRQSER_START_4CLK 0x00000000 61 #define LPC_HC_IRQSER_START_6CLK 0x01000000 62 #define LPC_HC_IRQSER_START_8CLK 0x02000000 63 #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */ 64 #define LPC_HC_IRQSTAT 0x38 65 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ 66 #define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */ 67 #define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000 68 #define LPC_HC_IRQ_LRESET 0x00000400 69 #define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080 70 #define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040 71 #define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020 72 #define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010 73 #define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008 74 #define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004 75 #define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002 76 #define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001 77 #define LPC_HC_ERROR_ADDRESS 0x40 78 79 #define LPC_OPB_SIZE 0x100000000ull 80 81 #define ISA_IO_SIZE 0x00010000 82 #define ISA_MEM_SIZE 0x10000000 83 #define ISA_FW_SIZE 0x10000000 84 #define LPC_IO_OPB_ADDR 0xd0010000 85 #define LPC_IO_OPB_SIZE 0x00010000 86 #define LPC_MEM_OPB_ADDR 0xe0010000 87 #define LPC_MEM_OPB_SIZE 0x10000000 88 #define LPC_FW_OPB_ADDR 0xf0000000 89 #define LPC_FW_OPB_SIZE 0x10000000 90 91 #define LPC_OPB_REGS_OPB_ADDR 0xc0010000 92 #define LPC_OPB_REGS_OPB_SIZE 0x00000060 93 #define LPC_OPB_REGS_OPBA_ADDR 0xc0011000 94 #define LPC_OPB_REGS_OPBA_SIZE 0x00000008 95 #define LPC_HC_REGS_OPB_ADDR 0xc0012000 96 #define LPC_HC_REGS_OPB_SIZE 0x00000100 97 98 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 99 { 100 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; 101 char *name; 102 int offset; 103 uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE; 104 uint32_t reg[] = { 105 cpu_to_be32(lpc_pcba), 106 cpu_to_be32(PNV_XSCOM_LPC_SIZE) 107 }; 108 109 name = g_strdup_printf("isa@%x", lpc_pcba); 110 offset = fdt_add_subnode(fdt, xscom_offset, name); 111 _FDT(offset); 112 g_free(name); 113 114 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 115 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); 116 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); 117 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 118 return 0; 119 } 120 121 /* 122 * These read/write handlers of the OPB address space should be common 123 * with the P9 LPC Controller which uses direct MMIOs. 124 * 125 * TODO: rework to use address_space_stq() and address_space_ldq() 126 * instead. 127 */ 128 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 129 int sz) 130 { 131 /* XXX Handle access size limits and FW read caching here */ 132 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 133 data, sz, false); 134 } 135 136 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 137 int sz) 138 { 139 /* XXX Handle access size limits here */ 140 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 141 data, sz, true); 142 } 143 144 #define ECCB_CTL_READ PPC_BIT(15) 145 #define ECCB_CTL_SZ_LSH (63 - 7) 146 #define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7) 147 #define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63) 148 149 #define ECCB_STAT_OP_DONE PPC_BIT(52) 150 #define ECCB_STAT_OP_ERR PPC_BIT(52) 151 #define ECCB_STAT_RD_DATA_LSH (63 - 37) 152 #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH) 153 154 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd) 155 { 156 /* XXX Check for magic bits at the top, addr size etc... */ 157 unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH; 158 uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK; 159 uint8_t data[8]; 160 bool success; 161 162 if (sz > sizeof(data)) { 163 qemu_log_mask(LOG_GUEST_ERROR, 164 "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz); 165 return; 166 } 167 168 if (cmd & ECCB_CTL_READ) { 169 success = opb_read(lpc, opb_addr, data, sz); 170 if (success) { 171 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 172 (((uint64_t)data[0]) << 24 | 173 ((uint64_t)data[1]) << 16 | 174 ((uint64_t)data[2]) << 8 | 175 ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH; 176 } else { 177 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 178 (0xffffffffull << ECCB_STAT_RD_DATA_LSH); 179 } 180 } else { 181 data[0] = lpc->eccb_data_reg >> 24; 182 data[1] = lpc->eccb_data_reg >> 16; 183 data[2] = lpc->eccb_data_reg >> 8; 184 data[3] = lpc->eccb_data_reg; 185 186 success = opb_write(lpc, opb_addr, data, sz); 187 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE; 188 } 189 /* XXX Which error bit (if any) to signal OPB error ? */ 190 } 191 192 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size) 193 { 194 PnvLpcController *lpc = PNV_LPC(opaque); 195 uint32_t offset = addr >> 3; 196 uint64_t val = 0; 197 198 switch (offset & 3) { 199 case ECCB_CTL: 200 case ECCB_RESET: 201 val = 0; 202 break; 203 case ECCB_STAT: 204 val = lpc->eccb_stat_reg; 205 lpc->eccb_stat_reg = 0; 206 break; 207 case ECCB_DATA: 208 val = ((uint64_t)lpc->eccb_data_reg) << 32; 209 break; 210 } 211 return val; 212 } 213 214 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr, 215 uint64_t val, unsigned size) 216 { 217 PnvLpcController *lpc = PNV_LPC(opaque); 218 uint32_t offset = addr >> 3; 219 220 switch (offset & 3) { 221 case ECCB_CTL: 222 pnv_lpc_do_eccb(lpc, val); 223 break; 224 case ECCB_RESET: 225 /* XXXX */ 226 break; 227 case ECCB_STAT: 228 break; 229 case ECCB_DATA: 230 lpc->eccb_data_reg = val >> 32; 231 break; 232 } 233 } 234 235 static const MemoryRegionOps pnv_lpc_xscom_ops = { 236 .read = pnv_lpc_xscom_read, 237 .write = pnv_lpc_xscom_write, 238 .valid.min_access_size = 8, 239 .valid.max_access_size = 8, 240 .impl.min_access_size = 8, 241 .impl.max_access_size = 8, 242 .endianness = DEVICE_BIG_ENDIAN, 243 }; 244 245 static void pnv_lpc_eval_irqs(PnvLpcController *lpc) 246 { 247 bool lpc_to_opb_irq = false; 248 249 /* Update LPC controller to OPB line */ 250 if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { 251 uint32_t irqs; 252 253 irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; 254 lpc_to_opb_irq = (irqs != 0); 255 } 256 257 /* We don't honor the polarity register, it's pointless and unused 258 * anyway 259 */ 260 if (lpc_to_opb_irq) { 261 lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; 262 } else { 263 lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; 264 } 265 266 /* Update OPB internal latch */ 267 lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; 268 269 /* Reflect the interrupt */ 270 pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0); 271 } 272 273 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) 274 { 275 PnvLpcController *lpc = opaque; 276 uint64_t val = 0xfffffffffffffffful; 277 278 switch (addr) { 279 case LPC_HC_FW_SEG_IDSEL: 280 val = lpc->lpc_hc_fw_seg_idsel; 281 break; 282 case LPC_HC_FW_RD_ACC_SIZE: 283 val = lpc->lpc_hc_fw_rd_acc_size; 284 break; 285 case LPC_HC_IRQSER_CTRL: 286 val = lpc->lpc_hc_irqser_ctrl; 287 break; 288 case LPC_HC_IRQMASK: 289 val = lpc->lpc_hc_irqmask; 290 break; 291 case LPC_HC_IRQSTAT: 292 val = lpc->lpc_hc_irqstat; 293 break; 294 case LPC_HC_ERROR_ADDRESS: 295 val = lpc->lpc_hc_error_addr; 296 break; 297 default: 298 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" 299 HWADDR_PRIx "\n", addr); 300 } 301 return val; 302 } 303 304 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, 305 unsigned size) 306 { 307 PnvLpcController *lpc = opaque; 308 309 /* XXX Filter out reserved bits */ 310 311 switch (addr) { 312 case LPC_HC_FW_SEG_IDSEL: 313 /* XXX Actually figure out how that works as this impact 314 * memory regions/aliases 315 */ 316 lpc->lpc_hc_fw_seg_idsel = val; 317 break; 318 case LPC_HC_FW_RD_ACC_SIZE: 319 lpc->lpc_hc_fw_rd_acc_size = val; 320 break; 321 case LPC_HC_IRQSER_CTRL: 322 lpc->lpc_hc_irqser_ctrl = val; 323 pnv_lpc_eval_irqs(lpc); 324 break; 325 case LPC_HC_IRQMASK: 326 lpc->lpc_hc_irqmask = val; 327 pnv_lpc_eval_irqs(lpc); 328 break; 329 case LPC_HC_IRQSTAT: 330 lpc->lpc_hc_irqstat &= ~val; 331 pnv_lpc_eval_irqs(lpc); 332 break; 333 case LPC_HC_ERROR_ADDRESS: 334 break; 335 default: 336 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" 337 HWADDR_PRIx "\n", addr); 338 } 339 } 340 341 static const MemoryRegionOps lpc_hc_ops = { 342 .read = lpc_hc_read, 343 .write = lpc_hc_write, 344 .endianness = DEVICE_BIG_ENDIAN, 345 .valid = { 346 .min_access_size = 4, 347 .max_access_size = 4, 348 }, 349 .impl = { 350 .min_access_size = 4, 351 .max_access_size = 4, 352 }, 353 }; 354 355 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size) 356 { 357 PnvLpcController *lpc = opaque; 358 uint64_t val = 0xfffffffffffffffful; 359 360 switch (addr) { 361 case OPB_MASTER_LS_IRQ_STAT: 362 val = lpc->opb_irq_stat; 363 break; 364 case OPB_MASTER_LS_IRQ_MASK: 365 val = lpc->opb_irq_mask; 366 break; 367 case OPB_MASTER_LS_IRQ_POL: 368 val = lpc->opb_irq_pol; 369 break; 370 case OPB_MASTER_LS_IRQ_INPUT: 371 val = lpc->opb_irq_input; 372 break; 373 default: 374 qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%" 375 HWADDR_PRIx "\n", addr); 376 } 377 378 return val; 379 } 380 381 static void opb_master_write(void *opaque, hwaddr addr, 382 uint64_t val, unsigned size) 383 { 384 PnvLpcController *lpc = opaque; 385 386 switch (addr) { 387 case OPB_MASTER_LS_IRQ_STAT: 388 lpc->opb_irq_stat &= ~val; 389 pnv_lpc_eval_irqs(lpc); 390 break; 391 case OPB_MASTER_LS_IRQ_MASK: 392 lpc->opb_irq_mask = val; 393 pnv_lpc_eval_irqs(lpc); 394 break; 395 case OPB_MASTER_LS_IRQ_POL: 396 lpc->opb_irq_pol = val; 397 pnv_lpc_eval_irqs(lpc); 398 break; 399 case OPB_MASTER_LS_IRQ_INPUT: 400 /* Read only */ 401 break; 402 default: 403 qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%" 404 HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val); 405 } 406 } 407 408 static const MemoryRegionOps opb_master_ops = { 409 .read = opb_master_read, 410 .write = opb_master_write, 411 .endianness = DEVICE_BIG_ENDIAN, 412 .valid = { 413 .min_access_size = 4, 414 .max_access_size = 4, 415 }, 416 .impl = { 417 .min_access_size = 4, 418 .max_access_size = 4, 419 }, 420 }; 421 422 static void pnv_lpc_realize(DeviceState *dev, Error **errp) 423 { 424 PnvLpcController *lpc = PNV_LPC(dev); 425 Object *obj; 426 Error *error = NULL; 427 428 /* Reg inits */ 429 lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; 430 431 /* Create address space and backing MR for the OPB bus */ 432 memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull); 433 address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb"); 434 435 /* Create ISA IO and Mem space regions which are the root of 436 * the ISA bus (ie, ISA address spaces). We don't create a 437 * separate one for FW which we alias to memory. 438 */ 439 memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE); 440 memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE); 441 memory_region_init(&lpc->isa_fw, OBJECT(dev), "isa-fw", ISA_FW_SIZE); 442 443 /* Create windows from the OPB space to the ISA space */ 444 memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io", 445 &lpc->isa_io, 0, LPC_IO_OPB_SIZE); 446 memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR, 447 &lpc->opb_isa_io); 448 memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem", 449 &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE); 450 memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR, 451 &lpc->opb_isa_mem); 452 memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw", 453 &lpc->isa_fw, 0, LPC_FW_OPB_SIZE); 454 memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR, 455 &lpc->opb_isa_fw); 456 457 /* Create MMIO regions for LPC HC and OPB registers */ 458 memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops, 459 lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE); 460 memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR, 461 &lpc->opb_master_regs); 462 memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc, 463 "lpc-hc", LPC_HC_REGS_OPB_SIZE); 464 memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR, 465 &lpc->lpc_hc_regs); 466 467 /* XScom region for LPC registers */ 468 pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), 469 &pnv_lpc_xscom_ops, lpc, "xscom-lpc", 470 PNV_XSCOM_LPC_SIZE); 471 472 /* get PSI object from chip */ 473 obj = object_property_get_link(OBJECT(dev), "psi", &error); 474 if (!obj) { 475 error_setg(errp, "%s: required link 'psi' not found: %s", 476 __func__, error_get_pretty(error)); 477 return; 478 } 479 lpc->psi = PNV_PSI(obj); 480 } 481 482 static void pnv_lpc_class_init(ObjectClass *klass, void *data) 483 { 484 DeviceClass *dc = DEVICE_CLASS(klass); 485 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 486 487 xdc->dt_xscom = pnv_lpc_dt_xscom; 488 489 dc->realize = pnv_lpc_realize; 490 } 491 492 static const TypeInfo pnv_lpc_info = { 493 .name = TYPE_PNV_LPC, 494 .parent = TYPE_DEVICE, 495 .instance_size = sizeof(PnvLpcController), 496 .class_init = pnv_lpc_class_init, 497 .interfaces = (InterfaceInfo[]) { 498 { TYPE_PNV_XSCOM_INTERFACE }, 499 { } 500 } 501 }; 502 503 static void pnv_lpc_register_types(void) 504 { 505 type_register_static(&pnv_lpc_info); 506 } 507 508 type_init(pnv_lpc_register_types) 509 510 /* If we don't use the built-in LPC interrupt deserializer, we need 511 * to provide a set of qirqs for the ISA bus or things will go bad. 512 * 513 * Most machines using pre-Naples chips (without said deserializer) 514 * have a CPLD that will collect the SerIRQ and shoot them as a 515 * single level interrupt to the P8 chip. So let's setup a hook 516 * for doing just that. 517 */ 518 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) 519 { 520 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 521 uint32_t old_state = pnv->cpld_irqstate; 522 PnvLpcController *lpc = PNV_LPC(opaque); 523 524 if (level) { 525 pnv->cpld_irqstate |= 1u << n; 526 } else { 527 pnv->cpld_irqstate &= ~(1u << n); 528 } 529 530 if (pnv->cpld_irqstate != old_state) { 531 pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0); 532 } 533 } 534 535 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) 536 { 537 PnvLpcController *lpc = PNV_LPC(opaque); 538 539 /* The Naples HW latches the 1 levels, clearing is done by SW */ 540 if (level) { 541 lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; 542 pnv_lpc_eval_irqs(lpc); 543 } 544 } 545 546 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp) 547 { 548 Error *local_err = NULL; 549 ISABus *isa_bus; 550 qemu_irq *irqs; 551 qemu_irq_handler handler; 552 553 /* let isa_bus_new() create its own bridge on SysBus otherwise 554 * devices speficied on the command line won't find the bus and 555 * will fail to create. 556 */ 557 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err); 558 if (local_err) { 559 error_propagate(errp, local_err); 560 return NULL; 561 } 562 563 /* Not all variants have a working serial irq decoder. If not, 564 * handling of LPC interrupts becomes a platform issue (some 565 * platforms have a CPLD to do it). 566 */ 567 if (use_cpld) { 568 handler = pnv_lpc_isa_irq_handler_cpld; 569 } else { 570 handler = pnv_lpc_isa_irq_handler; 571 } 572 573 irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS); 574 575 isa_bus_irqs(isa_bus, irqs); 576 return isa_bus; 577 } 578