1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016-2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/datadir.h" 24 #include "qemu/units.h" 25 #include "qemu/cutils.h" 26 #include "qapi/error.h" 27 #include "system/qtest.h" 28 #include "system/system.h" 29 #include "system/numa.h" 30 #include "system/reset.h" 31 #include "system/runstate.h" 32 #include "system/cpus.h" 33 #include "system/device_tree.h" 34 #include "system/hw_accel.h" 35 #include "target/ppc/cpu.h" 36 #include "hw/ppc/fdt.h" 37 #include "hw/ppc/ppc.h" 38 #include "hw/ppc/pnv.h" 39 #include "hw/ppc/pnv_core.h" 40 #include "hw/loader.h" 41 #include "hw/nmi.h" 42 #include "qapi/visitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci-host/pnv_phb.h" 48 #include "hw/pci-host/pnv_phb3.h" 49 #include "hw/pci-host/pnv_phb4.h" 50 51 #include "hw/ppc/xics.h" 52 #include "hw/qdev-properties.h" 53 #include "hw/ppc/pnv_chip.h" 54 #include "hw/ppc/pnv_xscom.h" 55 #include "hw/ppc/pnv_pnor.h" 56 57 #include "hw/isa/isa.h" 58 #include "hw/char/serial-isa.h" 59 #include "hw/rtc/mc146818rtc.h" 60 61 #include <libfdt.h> 62 63 #define FDT_MAX_SIZE (1 * MiB) 64 65 #define FW_FILE_NAME "skiboot.lid" 66 #define FW_LOAD_ADDR 0x0 67 #define FW_MAX_SIZE (16 * MiB) 68 69 #define PNOR_FILE_NAME "pnv-pnor.bin" 70 71 #define KERNEL_LOAD_ADDR 0x20000000 72 #define KERNEL_MAX_SIZE (128 * MiB) 73 #define INITRD_LOAD_ADDR 0x28000000 74 #define INITRD_MAX_SIZE (128 * MiB) 75 76 static const char *pnv_chip_core_typename(const PnvChip *o) 77 { 78 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 79 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 80 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 81 const char *core_type = object_class_get_name(object_class_by_name(s)); 82 g_free(s); 83 return core_type; 84 } 85 86 /* 87 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 88 * 4 * 4 sockets * 12 cores * 8 threads = 1536 89 * Let's make it 2^11 90 */ 91 #define MAX_CPUS 2048 92 93 /* 94 * Memory nodes are created by hostboot, one for each range of memory 95 * that has a different "affinity". In practice, it means one range 96 * per chip. 97 */ 98 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 99 { 100 char *mem_name; 101 uint64_t mem_reg_property[2]; 102 int off; 103 104 mem_reg_property[0] = cpu_to_be64(start); 105 mem_reg_property[1] = cpu_to_be64(size); 106 107 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 108 off = fdt_add_subnode(fdt, 0, mem_name); 109 g_free(mem_name); 110 111 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 112 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 113 sizeof(mem_reg_property)))); 114 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 115 } 116 117 static int get_cpus_node(void *fdt) 118 { 119 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 120 121 if (cpus_offset < 0) { 122 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 123 if (cpus_offset) { 124 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 125 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 126 } 127 } 128 _FDT(cpus_offset); 129 return cpus_offset; 130 } 131 132 /* 133 * The PowerNV cores (and threads) need to use real HW ids and not an 134 * incremental index like it has been done on other platforms. This HW 135 * id is stored in the CPU PIR, it is used to create cpu nodes in the 136 * device tree, used in XSCOM to address cores and in interrupt 137 * servers. 138 */ 139 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 140 { 141 PowerPCCPU *cpu = pc->threads[0]; 142 CPUState *cs = CPU(cpu); 143 DeviceClass *dc = DEVICE_GET_CLASS(cs); 144 int smt_threads = CPU_CORE(pc)->nr_threads; 145 CPUPPCState *env = &cpu->env; 146 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 147 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 148 uint32_t *servers_prop; 149 int i; 150 uint32_t pir, tir; 151 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 152 0xffffffff, 0xffffffff}; 153 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 154 uint32_t cpufreq = 1000000000; 155 uint32_t page_sizes_prop[64]; 156 size_t page_sizes_prop_size; 157 int offset; 158 char *nodename; 159 int cpus_offset = get_cpus_node(fdt); 160 161 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); 162 163 /* Only one DT node per (big) core */ 164 g_assert(tir == 0); 165 166 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 167 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 168 _FDT(offset); 169 g_free(nodename); 170 171 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 172 173 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 174 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 175 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 176 177 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 179 env->dcache_line_size))); 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 181 env->dcache_line_size))); 182 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 183 env->icache_line_size))); 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 185 env->icache_line_size))); 186 187 if (pcc->l1_dcache_size) { 188 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 189 pcc->l1_dcache_size))); 190 } else { 191 warn_report("Unknown L1 dcache size for cpu"); 192 } 193 if (pcc->l1_icache_size) { 194 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 195 pcc->l1_icache_size))); 196 } else { 197 warn_report("Unknown L1 icache size for cpu"); 198 } 199 200 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 201 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 202 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 203 cpu->hash64_opts->slb_size))); 204 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 205 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 206 207 if (ppc_has_spr(cpu, SPR_PURR)) { 208 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 209 } 210 211 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 212 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 213 segs, sizeof(segs)))); 214 } 215 216 /* 217 * Advertise VMX/VSX (vector extensions) if available 218 * 0 / no property == no vector extensions 219 * 1 == VMX / Altivec available 220 * 2 == VSX available 221 */ 222 if (env->insns_flags & PPC_ALTIVEC) { 223 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 224 225 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 226 } 227 228 /* 229 * Advertise DFP (Decimal Floating Point) if available 230 * 0 / no property == no DFP 231 * 1 == DFP available 232 */ 233 if (env->insns_flags2 & PPC2_DFP) { 234 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 235 } 236 237 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 238 sizeof(page_sizes_prop)); 239 if (page_sizes_prop_size) { 240 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 241 page_sizes_prop, page_sizes_prop_size))); 242 } 243 244 /* Build interrupt servers properties */ 245 if (pc->big_core) { 246 servers_prop = g_new(uint32_t, smt_threads * 2); 247 for (i = 0; i < smt_threads; i++) { 248 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 249 servers_prop[i * 2] = cpu_to_be32(pir); 250 251 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); 252 servers_prop[i * 2 + 1] = cpu_to_be32(pir); 253 } 254 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 255 servers_prop, sizeof(*servers_prop) * smt_threads 256 * 2))); 257 } else { 258 servers_prop = g_new(uint32_t, smt_threads); 259 for (i = 0; i < smt_threads; i++) { 260 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 261 servers_prop[i] = cpu_to_be32(pir); 262 } 263 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 264 servers_prop, sizeof(*servers_prop) * smt_threads))); 265 } 266 g_free(servers_prop); 267 268 return offset; 269 } 270 271 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 272 uint32_t nr_threads) 273 { 274 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 275 uint32_t pir; 276 uint64_t addr; 277 char *name; 278 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 279 uint32_t irange[2], i, rsize; 280 uint64_t *reg; 281 int offset; 282 283 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 284 addr = PNV_ICP_BASE(chip) | (pir << 12); 285 286 irange[0] = cpu_to_be32(pir); 287 irange[1] = cpu_to_be32(nr_threads); 288 289 rsize = sizeof(uint64_t) * 2 * nr_threads; 290 reg = g_malloc(rsize); 291 for (i = 0; i < nr_threads; i++) { 292 /* We know P8 PIR is linear with thread id */ 293 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 294 reg[i * 2 + 1] = cpu_to_be64(0x1000); 295 } 296 297 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 298 offset = fdt_add_subnode(fdt, 0, name); 299 _FDT(offset); 300 g_free(name); 301 302 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 303 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 304 _FDT((fdt_setprop_string(fdt, offset, "device_type", 305 "PowerPC-External-Interrupt-Presentation"))); 306 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 307 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 308 irange, sizeof(irange)))); 309 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 310 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 311 g_free(reg); 312 } 313 314 /* 315 * Adds a PnvPHB to the chip on P8. 316 * Implemented here, like for defaults PHBs 317 */ 318 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 319 { 320 Pnv8Chip *chip8 = PNV8_CHIP(chip); 321 322 phb->chip = chip; 323 324 chip8->phbs[chip8->num_phbs] = phb; 325 chip8->num_phbs++; 326 return chip; 327 } 328 329 /* 330 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 331 * HTM is always enabled because TCG does implement HTM, it's just a 332 * degenerate implementation. 333 */ 334 static const uint8_t pa_features_207[] = { 24, 0, 335 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 336 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 337 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 338 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 339 340 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 341 { 342 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 343 int i; 344 345 pnv_dt_xscom(chip, fdt, 0, 346 cpu_to_be64(PNV_XSCOM_BASE(chip)), 347 cpu_to_be64(PNV_XSCOM_SIZE), 348 compat, sizeof(compat)); 349 350 for (i = 0; i < chip->nr_cores; i++) { 351 PnvCore *pnv_core = chip->cores[i]; 352 int offset; 353 354 offset = pnv_dt_core(chip, pnv_core, fdt); 355 356 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 357 pa_features_207, sizeof(pa_features_207)))); 358 359 /* Interrupt Control Presenters (ICP). One per core. */ 360 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 361 } 362 363 if (chip->ram_size) { 364 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 365 } 366 } 367 368 /* 369 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 370 */ 371 static const uint8_t pa_features_300[] = { 66, 0, 372 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 373 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 374 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 375 /* 6: DS207 */ 376 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 377 /* 16: Vector */ 378 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 379 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 380 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 381 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 382 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 383 /* 32: LE atomic, 34: EBB + ext EBB */ 384 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 385 /* 40: Radix MMU */ 386 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 387 /* 42: PM, 44: PC RA, 46: SC vec'd */ 388 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 389 /* 48: SIMD, 50: QP BFP, 52: String */ 390 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 391 /* 54: DecFP, 56: DecI, 58: SHA */ 392 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 393 /* 60: NM atomic, 62: RNG */ 394 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 395 }; 396 397 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 398 { 399 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 400 int i; 401 402 pnv_dt_xscom(chip, fdt, 0, 403 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 404 cpu_to_be64(PNV9_XSCOM_SIZE), 405 compat, sizeof(compat)); 406 407 for (i = 0; i < chip->nr_cores; i++) { 408 PnvCore *pnv_core = chip->cores[i]; 409 int offset; 410 411 offset = pnv_dt_core(chip, pnv_core, fdt); 412 413 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 414 pa_features_300, sizeof(pa_features_300)))); 415 416 if (pnv_core->big_core) { 417 i++; /* Big-core groups two QEMU cores */ 418 } 419 } 420 421 if (chip->ram_size) { 422 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 423 } 424 425 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 426 } 427 428 /* 429 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 430 * always disables copy/paste. 431 */ 432 static const uint8_t pa_features_31[] = { 74, 0, 433 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 434 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 435 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 436 /* 6: DS207 */ 437 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 438 /* 16: Vector */ 439 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 440 /* 18: Vec. Scalar, 20: Vec. XOR */ 441 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 442 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 443 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 444 /* 32: LE atomic, 34: EBB + ext EBB */ 445 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 446 /* 40: Radix MMU */ 447 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 448 /* 42: PM, 44: PC RA, 46: SC vec'd */ 449 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 450 /* 48: SIMD, 50: QP BFP, 52: String */ 451 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 452 /* 54: DecFP, 56: DecI, 58: SHA */ 453 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 454 /* 60: NM atomic, 62: RNG */ 455 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 456 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 457 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 458 /* 72: [P]HASHST/[P]HASHCHK */ 459 0x80, 0x00, /* 72 - 73 */ 460 }; 461 462 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 463 { 464 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 465 int i; 466 467 pnv_dt_xscom(chip, fdt, 0, 468 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 469 cpu_to_be64(PNV10_XSCOM_SIZE), 470 compat, sizeof(compat)); 471 472 for (i = 0; i < chip->nr_cores; i++) { 473 PnvCore *pnv_core = chip->cores[i]; 474 int offset; 475 476 offset = pnv_dt_core(chip, pnv_core, fdt); 477 478 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 479 pa_features_31, sizeof(pa_features_31)))); 480 481 if (pnv_core->big_core) { 482 i++; /* Big-core groups two QEMU cores */ 483 } 484 } 485 486 if (chip->ram_size) { 487 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 488 } 489 490 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 491 } 492 493 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 494 { 495 uint32_t io_base = d->ioport_id; 496 uint32_t io_regs[] = { 497 cpu_to_be32(1), 498 cpu_to_be32(io_base), 499 cpu_to_be32(2) 500 }; 501 char *name; 502 int node; 503 504 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 505 node = fdt_add_subnode(fdt, lpc_off, name); 506 _FDT(node); 507 g_free(name); 508 509 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 510 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 511 } 512 513 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 514 { 515 const char compatible[] = "ns16550\0pnpPNP,501"; 516 uint32_t io_base = d->ioport_id; 517 uint32_t io_regs[] = { 518 cpu_to_be32(1), 519 cpu_to_be32(io_base), 520 cpu_to_be32(8) 521 }; 522 uint32_t irq; 523 char *name; 524 int node; 525 526 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 527 528 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 529 node = fdt_add_subnode(fdt, lpc_off, name); 530 _FDT(node); 531 g_free(name); 532 533 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 534 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 535 sizeof(compatible)))); 536 537 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 538 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 539 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 540 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 541 fdt_get_phandle(fdt, lpc_off)))); 542 543 /* This is needed by Linux */ 544 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 545 } 546 547 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 548 { 549 const char compatible[] = "bt\0ipmi-bt"; 550 uint32_t io_base; 551 uint32_t io_regs[] = { 552 cpu_to_be32(1), 553 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 554 cpu_to_be32(3) 555 }; 556 uint32_t irq; 557 char *name; 558 int node; 559 560 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 561 io_regs[1] = cpu_to_be32(io_base); 562 563 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 564 565 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 566 node = fdt_add_subnode(fdt, lpc_off, name); 567 _FDT(node); 568 g_free(name); 569 570 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 571 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 572 sizeof(compatible)))); 573 574 /* Mark it as reserved to avoid Linux trying to claim it */ 575 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 576 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 577 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 578 fdt_get_phandle(fdt, lpc_off)))); 579 } 580 581 typedef struct ForeachPopulateArgs { 582 void *fdt; 583 int offset; 584 } ForeachPopulateArgs; 585 586 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 587 { 588 ForeachPopulateArgs *args = opaque; 589 ISADevice *d = ISA_DEVICE(dev); 590 591 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 592 pnv_dt_rtc(d, args->fdt, args->offset); 593 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 594 pnv_dt_serial(d, args->fdt, args->offset); 595 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 596 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 597 } else { 598 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 599 d->ioport_id); 600 } 601 602 return 0; 603 } 604 605 /* 606 * The default LPC bus of a multichip system is on chip 0. It's 607 * recognized by the firmware (skiboot) using a "primary" property. 608 */ 609 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 610 { 611 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 612 ForeachPopulateArgs args = { 613 .fdt = fdt, 614 .offset = isa_offset, 615 }; 616 uint32_t phandle; 617 618 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 619 620 phandle = qemu_fdt_alloc_phandle(fdt); 621 assert(phandle > 0); 622 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 623 624 /* 625 * ISA devices are not necessarily parented to the ISA bus so we 626 * can not use object_child_foreach() 627 */ 628 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 629 &args); 630 } 631 632 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 633 { 634 int off; 635 636 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 637 off = fdt_add_subnode(fdt, off, "power-mgt"); 638 639 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 640 } 641 642 static void *pnv_dt_create(MachineState *machine) 643 { 644 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 645 PnvMachineState *pnv = PNV_MACHINE(machine); 646 void *fdt; 647 char *buf; 648 int off; 649 int i; 650 651 fdt = g_malloc0(FDT_MAX_SIZE); 652 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 653 654 /* /qemu node */ 655 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 656 657 /* Root node */ 658 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 659 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 660 _FDT((fdt_setprop_string(fdt, 0, "model", 661 "IBM PowerNV (emulated by qemu)"))); 662 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 663 664 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 665 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 666 if (qemu_uuid_set) { 667 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 668 } 669 g_free(buf); 670 671 off = fdt_add_subnode(fdt, 0, "chosen"); 672 if (machine->kernel_cmdline) { 673 _FDT((fdt_setprop_string(fdt, off, "bootargs", 674 machine->kernel_cmdline))); 675 } 676 677 if (pnv->initrd_size) { 678 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 679 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 680 681 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 682 &start_prop, sizeof(start_prop)))); 683 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 684 &end_prop, sizeof(end_prop)))); 685 } 686 687 /* Populate device tree for each chip */ 688 for (i = 0; i < pnv->num_chips; i++) { 689 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 690 } 691 692 /* Populate ISA devices on chip 0 */ 693 pnv_dt_isa(pnv, fdt); 694 695 if (pnv->bmc) { 696 pnv_dt_bmc_sensors(pnv->bmc, fdt); 697 } 698 699 /* Create an extra node for power management on machines that support it */ 700 if (pmc->dt_power_mgt) { 701 pmc->dt_power_mgt(pnv, fdt); 702 } 703 704 return fdt; 705 } 706 707 static void pnv_powerdown_notify(Notifier *n, void *opaque) 708 { 709 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 710 711 if (pnv->bmc) { 712 pnv_bmc_powerdown(pnv->bmc); 713 } 714 } 715 716 static void pnv_reset(MachineState *machine, ResetType type) 717 { 718 PnvMachineState *pnv = PNV_MACHINE(machine); 719 IPMIBmc *bmc; 720 void *fdt; 721 722 qemu_devices_reset(type); 723 724 /* 725 * The machine should provide by default an internal BMC simulator. 726 * If not, try to use the BMC device that was provided on the command 727 * line. 728 */ 729 bmc = pnv_bmc_find(&error_fatal); 730 if (!pnv->bmc) { 731 if (!bmc) { 732 if (!qtest_enabled()) { 733 warn_report("machine has no BMC device. Use '-device " 734 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 735 "to define one"); 736 } 737 } else { 738 pnv_bmc_set_pnor(bmc, pnv->pnor); 739 pnv->bmc = bmc; 740 } 741 } 742 743 if (machine->fdt) { 744 fdt = machine->fdt; 745 } else { 746 fdt = pnv_dt_create(machine); 747 /* Pack resulting tree */ 748 _FDT((fdt_pack(fdt))); 749 } 750 751 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 752 753 /* Update machine->fdt with latest fdt */ 754 if (machine->fdt != fdt) { 755 /* 756 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 757 * the existing machine->fdt to avoid leaking it during 758 * a reset. 759 */ 760 g_free(machine->fdt); 761 machine->fdt = fdt; 762 } 763 } 764 765 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 766 { 767 Pnv8Chip *chip8 = PNV8_CHIP(chip); 768 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 769 770 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 771 772 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 773 } 774 775 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 776 { 777 Pnv8Chip *chip8 = PNV8_CHIP(chip); 778 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 779 780 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 781 782 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 783 } 784 785 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 786 { 787 Pnv9Chip *chip9 = PNV9_CHIP(chip); 788 qemu_irq irq; 789 790 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 791 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 792 793 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 794 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 795 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 796 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 797 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 798 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 799 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 800 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 801 802 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 803 } 804 805 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 806 { 807 Pnv10Chip *chip10 = PNV10_CHIP(chip); 808 qemu_irq irq; 809 810 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 811 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 812 813 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 814 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 815 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 816 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 817 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 818 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 819 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 820 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 821 822 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 823 } 824 825 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 826 { 827 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 828 } 829 830 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 831 { 832 Pnv8Chip *chip8 = PNV8_CHIP(chip); 833 int i; 834 835 ics_pic_print_info(&chip8->psi.ics, buf); 836 837 for (i = 0; i < chip8->num_phbs; i++) { 838 PnvPHB *phb = chip8->phbs[i]; 839 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 840 841 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 842 ics_pic_print_info(&phb3->lsis, buf); 843 } 844 } 845 846 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 847 { 848 GString *buf = opaque; 849 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 850 851 if (!phb) { 852 return 0; 853 } 854 855 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 856 857 return 0; 858 } 859 860 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 861 { 862 Pnv9Chip *chip9 = PNV9_CHIP(chip); 863 864 pnv_xive_pic_print_info(&chip9->xive, buf); 865 pnv_psi_pic_print_info(&chip9->psi, buf); 866 object_child_foreach_recursive(OBJECT(chip), 867 pnv_chip_power9_pic_print_info_child, buf); 868 } 869 870 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 871 uint32_t core_id) 872 { 873 return PNV_XSCOM_EX_BASE(core_id); 874 } 875 876 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 877 uint32_t core_id) 878 { 879 return PNV9_XSCOM_EC_BASE(core_id); 880 } 881 882 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 883 uint32_t core_id) 884 { 885 return PNV10_XSCOM_EC_BASE(core_id); 886 } 887 888 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 889 { 890 PowerPCCPUClass *ppc_default = 891 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 892 PowerPCCPUClass *ppc = 893 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 894 895 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 896 } 897 898 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 899 { 900 ISADevice *dev = isa_new("isa-ipmi-bt"); 901 902 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 903 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 904 isa_realize_and_unref(dev, bus, &error_fatal); 905 } 906 907 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 908 { 909 Pnv10Chip *chip10 = PNV10_CHIP(chip); 910 911 pnv_xive2_pic_print_info(&chip10->xive, buf); 912 pnv_psi_pic_print_info(&chip10->psi, buf); 913 object_child_foreach_recursive(OBJECT(chip), 914 pnv_chip_power9_pic_print_info_child, buf); 915 } 916 917 /* Always give the first 1GB to chip 0 else we won't boot */ 918 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 919 { 920 MachineState *machine = MACHINE(pnv); 921 uint64_t ram_per_chip; 922 923 assert(machine->ram_size >= 1 * GiB); 924 925 ram_per_chip = machine->ram_size / pnv->num_chips; 926 if (ram_per_chip >= 1 * GiB) { 927 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 928 } 929 930 assert(pnv->num_chips > 1); 931 932 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 933 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 934 } 935 936 static void pnv_init(MachineState *machine) 937 { 938 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 939 PnvMachineState *pnv = PNV_MACHINE(machine); 940 MachineClass *mc = MACHINE_GET_CLASS(machine); 941 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 942 int max_smt_threads = pmc->max_smt_threads; 943 char *fw_filename; 944 long fw_size; 945 uint64_t chip_ram_start = 0; 946 int i; 947 char *chip_typename; 948 DriveInfo *pnor; 949 DeviceState *dev; 950 951 if (kvm_enabled()) { 952 error_report("machine %s does not support the KVM accelerator", 953 mc->name); 954 exit(EXIT_FAILURE); 955 } 956 957 /* allocate RAM */ 958 if (machine->ram_size < mc->default_ram_size) { 959 char *sz = size_to_str(mc->default_ram_size); 960 error_report("Invalid RAM size, should be bigger than %s", sz); 961 g_free(sz); 962 exit(EXIT_FAILURE); 963 } 964 965 /* checks for invalid option combinations */ 966 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { 967 error_report("-append and -dtb cannot be used together, as passed" 968 " command line is ignored in case of custom dtb"); 969 exit(EXIT_FAILURE); 970 } 971 972 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 973 974 /* 975 * Create our simple PNOR device 976 */ 977 dev = qdev_new(TYPE_PNV_PNOR); 978 pnor = drive_get(IF_MTD, 0, 0); 979 if (!pnor && defaults_enabled()) { 980 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, PNOR_FILE_NAME); 981 if (!fw_filename) { 982 warn_report("Could not find PNOR '%s'", PNOR_FILE_NAME); 983 } else { 984 QemuOpts *opts; 985 opts = drive_add(IF_MTD, -1, fw_filename, "format=raw,readonly=on"); 986 pnor = drive_new(opts, IF_MTD, &error_fatal); 987 g_free(fw_filename); 988 } 989 } 990 if (pnor) { 991 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 992 } 993 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 994 pnv->pnor = PNV_PNOR(dev); 995 996 /* load skiboot firmware */ 997 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 998 if (!fw_filename) { 999 error_report("Could not find OPAL firmware '%s'", bios_name); 1000 exit(1); 1001 } 1002 1003 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 1004 if (fw_size < 0) { 1005 error_report("Could not load OPAL firmware '%s'", fw_filename); 1006 exit(1); 1007 } 1008 g_free(fw_filename); 1009 1010 /* load kernel */ 1011 if (machine->kernel_filename) { 1012 long kernel_size; 1013 1014 kernel_size = load_image_targphys(machine->kernel_filename, 1015 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 1016 if (kernel_size < 0) { 1017 error_report("Could not load kernel '%s'", 1018 machine->kernel_filename); 1019 exit(1); 1020 } 1021 } 1022 1023 /* load initrd */ 1024 if (machine->initrd_filename) { 1025 pnv->initrd_base = INITRD_LOAD_ADDR; 1026 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 1027 pnv->initrd_base, INITRD_MAX_SIZE); 1028 if (pnv->initrd_size < 0) { 1029 error_report("Could not load initial ram disk '%s'", 1030 machine->initrd_filename); 1031 exit(1); 1032 } 1033 } 1034 1035 /* load dtb if passed */ 1036 if (machine->dtb) { 1037 int fdt_size; 1038 1039 warn_report("with manually passed dtb, some options like '-append'" 1040 " will get ignored and the dtb passed will be used as-is"); 1041 1042 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ 1043 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 1044 if (!machine->fdt) { 1045 error_report("Could not load dtb '%s'", machine->dtb); 1046 exit(1); 1047 } 1048 } 1049 1050 /* MSIs are supported on this platform */ 1051 msi_nonbroken = true; 1052 1053 /* 1054 * Check compatibility of the specified CPU with the machine 1055 * default. 1056 */ 1057 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 1058 error_report("invalid CPU model '%s' for %s machine", 1059 machine->cpu_type, mc->name); 1060 exit(1); 1061 } 1062 1063 /* Create the processor chips */ 1064 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 1065 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 1066 i, machine->cpu_type); 1067 if (!object_class_by_name(chip_typename)) { 1068 error_report("invalid chip model '%.*s' for %s machine", 1069 i, machine->cpu_type, mc->name); 1070 exit(1); 1071 } 1072 1073 /* Set lpar-per-core mode if lpar-per-thread is not supported */ 1074 if (!pmc->has_lpar_per_thread) { 1075 pnv->lpar_per_core = true; 1076 } 1077 1078 pnv->num_chips = 1079 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1080 1081 if (pnv->big_core) { 1082 if (machine->smp.threads % 2 == 1) { 1083 error_report("Cannot support %d threads with big-core option " 1084 "because it must be an even number", 1085 machine->smp.threads); 1086 exit(1); 1087 } 1088 max_smt_threads *= 2; 1089 } 1090 1091 if (machine->smp.threads > max_smt_threads) { 1092 error_report("Cannot support more than %d threads/core " 1093 "on %s machine", max_smt_threads, mc->desc); 1094 if (pmc->max_smt_threads == 4) { 1095 error_report("(use big-core=on for 8 threads per core)"); 1096 } 1097 exit(1); 1098 } 1099 1100 if (pnv->big_core) { 1101 /* 1102 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1103 * per core, so adjust topology here. pnv_dt_core() processor 1104 * device-tree and TCG SMT code make the 2 cores appear as one big core 1105 * from software point of view. pnv pervasive models and xscoms tend to 1106 * see the big core as 2 small core halves. 1107 */ 1108 machine->smp.cores *= 2; 1109 machine->smp.threads /= 2; 1110 } 1111 1112 if (!is_power_of_2(machine->smp.threads)) { 1113 error_report("Cannot support %d threads/core on a powernv " 1114 "machine because it must be a power of 2", 1115 machine->smp.threads); 1116 exit(1); 1117 } 1118 1119 /* 1120 * TODO: should we decide on how many chips we can create based 1121 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1122 */ 1123 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1124 error_report("invalid number of chips: '%d'", pnv->num_chips); 1125 error_printf( 1126 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1127 exit(1); 1128 } 1129 1130 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1131 for (i = 0; i < pnv->num_chips; i++) { 1132 char chip_name[32]; 1133 Object *chip = OBJECT(qdev_new(chip_typename)); 1134 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1135 1136 pnv->chips[i] = PNV_CHIP(chip); 1137 1138 /* Distribute RAM among the chips */ 1139 object_property_set_int(chip, "ram-start", chip_ram_start, 1140 &error_fatal); 1141 object_property_set_int(chip, "ram-size", chip_ram_size, 1142 &error_fatal); 1143 chip_ram_start += chip_ram_size; 1144 1145 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1146 object_property_add_child(OBJECT(pnv), chip_name, chip); 1147 object_property_set_int(chip, "chip-id", i, &error_fatal); 1148 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1149 &error_fatal); 1150 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1151 &error_fatal); 1152 object_property_set_bool(chip, "big-core", pnv->big_core, 1153 &error_fatal); 1154 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, 1155 &error_fatal); 1156 /* 1157 * The POWER8 machine use the XICS interrupt interface. 1158 * Propagate the XICS fabric to the chip and its controllers. 1159 */ 1160 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1161 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1162 } 1163 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1164 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1165 &error_abort); 1166 } 1167 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1168 } 1169 g_free(chip_typename); 1170 1171 /* Instantiate ISA bus on chip 0 */ 1172 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1173 1174 /* Create serial port */ 1175 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1176 1177 /* Create an RTC ISA device too */ 1178 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1179 1180 /* 1181 * Create the machine BMC simulator and the IPMI BT device for 1182 * communication with the BMC 1183 */ 1184 if (defaults_enabled()) { 1185 pnv->bmc = pnv_bmc_create(pnv->pnor); 1186 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1187 } 1188 1189 /* 1190 * The PNOR is mapped on the LPC FW address space by the BMC. 1191 * Since we can not reach the remote BMC machine with LPC memops, 1192 * map it always for now. 1193 */ 1194 memory_region_add_subregion(pnv->chips[0]->fw_mr, pnv->pnor->lpc_address, 1195 &pnv->pnor->mmio); 1196 1197 /* 1198 * OpenPOWER systems use a IPMI SEL Event message to notify the 1199 * host to powerdown 1200 */ 1201 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1202 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1203 1204 /* 1205 * Create/Connect any machine-specific I2C devices 1206 */ 1207 if (pmc->i2c_init) { 1208 pmc->i2c_init(pnv); 1209 } 1210 } 1211 1212 /* 1213 * 0:21 Reserved - Read as zeros 1214 * 22:24 Chip ID 1215 * 25:28 Core number 1216 * 29:31 Thread ID 1217 */ 1218 static void pnv_get_pir_tir_p8(PnvChip *chip, 1219 uint32_t core_id, uint32_t thread_id, 1220 uint32_t *pir, uint32_t *tir) 1221 { 1222 if (pir) { 1223 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1224 } 1225 if (tir) { 1226 *tir = thread_id; 1227 } 1228 } 1229 1230 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1231 Error **errp) 1232 { 1233 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1234 Error *local_err = NULL; 1235 Object *obj; 1236 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1237 1238 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1239 if (local_err) { 1240 error_propagate(errp, local_err); 1241 return; 1242 } 1243 1244 pnv_cpu->intc = obj; 1245 } 1246 1247 1248 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1249 { 1250 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1251 1252 icp_reset(ICP(pnv_cpu->intc)); 1253 } 1254 1255 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1256 { 1257 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1258 1259 icp_destroy(ICP(pnv_cpu->intc)); 1260 pnv_cpu->intc = NULL; 1261 } 1262 1263 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1264 GString *buf) 1265 { 1266 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1267 } 1268 1269 /* 1270 * 0:48 Reserved - Read as zeroes 1271 * 49:52 Node ID 1272 * 53:55 Chip ID 1273 * 56 Reserved - Read as zero 1274 * 57:61 Core number 1275 * 62:63 Thread ID 1276 * 1277 * We only care about the lower bits. uint32_t is fine for the moment. 1278 */ 1279 static void pnv_get_pir_tir_p9(PnvChip *chip, 1280 uint32_t core_id, uint32_t thread_id, 1281 uint32_t *pir, uint32_t *tir) 1282 { 1283 if (chip->big_core) { 1284 /* Big-core interleaves thread ID between small-cores */ 1285 thread_id <<= 1; 1286 thread_id |= core_id & 1; 1287 core_id >>= 1; 1288 1289 if (pir) { 1290 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1291 } 1292 } else { 1293 if (pir) { 1294 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1295 } 1296 } 1297 if (tir) { 1298 *tir = thread_id; 1299 } 1300 } 1301 1302 /* 1303 * 0:48 Reserved - Read as zeroes 1304 * 49:52 Node ID 1305 * 53:55 Chip ID 1306 * 56 Reserved - Read as zero 1307 * 57:59 Quad ID 1308 * 60 Core Chiplet Pair ID 1309 * 61:63 Thread/Core Chiplet ID t0-t2 1310 * 1311 * We only care about the lower bits. uint32_t is fine for the moment. 1312 */ 1313 static void pnv_get_pir_tir_p10(PnvChip *chip, 1314 uint32_t core_id, uint32_t thread_id, 1315 uint32_t *pir, uint32_t *tir) 1316 { 1317 if (chip->big_core) { 1318 /* Big-core interleaves thread ID between small-cores */ 1319 thread_id <<= 1; 1320 thread_id |= core_id & 1; 1321 core_id >>= 1; 1322 1323 if (pir) { 1324 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1325 } 1326 } else { 1327 if (pir) { 1328 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1329 } 1330 } 1331 if (tir) { 1332 *tir = thread_id; 1333 } 1334 } 1335 1336 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1337 Error **errp) 1338 { 1339 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1340 Error *local_err = NULL; 1341 Object *obj; 1342 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1343 1344 /* 1345 * The core creates its interrupt presenter but the XIVE interrupt 1346 * controller object is initialized afterwards. Hopefully, it's 1347 * only used at runtime. 1348 */ 1349 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1350 &local_err); 1351 if (local_err) { 1352 error_propagate(errp, local_err); 1353 return; 1354 } 1355 1356 pnv_cpu->intc = obj; 1357 } 1358 1359 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1360 { 1361 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1362 1363 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1364 } 1365 1366 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1367 { 1368 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1369 1370 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1371 pnv_cpu->intc = NULL; 1372 } 1373 1374 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1375 GString *buf) 1376 { 1377 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1378 } 1379 1380 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1381 Error **errp) 1382 { 1383 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1384 Error *local_err = NULL; 1385 Object *obj; 1386 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1387 1388 /* 1389 * The core creates its interrupt presenter but the XIVE2 interrupt 1390 * controller object is initialized afterwards. Hopefully, it's 1391 * only used at runtime. 1392 */ 1393 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1394 &local_err); 1395 if (local_err) { 1396 error_propagate(errp, local_err); 1397 return; 1398 } 1399 1400 pnv_cpu->intc = obj; 1401 } 1402 1403 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1404 { 1405 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1406 1407 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1408 } 1409 1410 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1411 { 1412 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1413 1414 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1415 pnv_cpu->intc = NULL; 1416 } 1417 1418 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1419 GString *buf) 1420 { 1421 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1422 } 1423 1424 /* 1425 * Allowed core identifiers on a POWER8 Processor Chip : 1426 * 1427 * <EX0 reserved> 1428 * EX1 - Venice only 1429 * EX2 - Venice only 1430 * EX3 - Venice only 1431 * EX4 1432 * EX5 1433 * EX6 1434 * <EX7,8 reserved> <reserved> 1435 * EX9 - Venice only 1436 * EX10 - Venice only 1437 * EX11 - Venice only 1438 * EX12 1439 * EX13 1440 * EX14 1441 * <EX15 reserved> 1442 */ 1443 #define POWER8E_CORE_MASK (0x7070ull) 1444 #define POWER8_CORE_MASK (0x7e7eull) 1445 1446 /* 1447 * POWER9 has 24 cores, ids starting at 0x0 1448 */ 1449 #define POWER9_CORE_MASK (0xffffffffffffffull) 1450 1451 1452 #define POWER10_CORE_MASK (0xffffffffffffffull) 1453 1454 static void pnv_chip_power8_instance_init(Object *obj) 1455 { 1456 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1457 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1458 int i; 1459 1460 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1461 (Object **)&chip8->xics, 1462 object_property_allow_set_link, 1463 OBJ_PROP_LINK_STRONG); 1464 1465 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1466 1467 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1468 1469 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1470 1471 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1472 1473 if (defaults_enabled()) { 1474 chip8->num_phbs = pcc->num_phbs; 1475 1476 for (i = 0; i < chip8->num_phbs; i++) { 1477 Object *phb = object_new(TYPE_PNV_PHB); 1478 1479 /* 1480 * We need the chip to parent the PHB to allow the DT 1481 * to build correctly (via pnv_xscom_dt()). 1482 * 1483 * TODO: the PHB should be parented by a PEC device that, at 1484 * this moment, is not modelled powernv8/phb3. 1485 */ 1486 object_property_add_child(obj, "phb[*]", phb); 1487 chip8->phbs[i] = PNV_PHB(phb); 1488 } 1489 } 1490 1491 } 1492 1493 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1494 { 1495 PnvChip *chip = PNV_CHIP(chip8); 1496 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1497 int i, j; 1498 char *name; 1499 1500 name = g_strdup_printf("icp-%x", chip->chip_id); 1501 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1502 g_free(name); 1503 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1504 &chip8->icp_mmio); 1505 1506 /* Map the ICP registers for each thread */ 1507 for (i = 0; i < chip->nr_cores; i++) { 1508 PnvCore *pnv_core = chip->cores[i]; 1509 int core_hwid = CPU_CORE(pnv_core)->core_id; 1510 1511 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1512 uint32_t pir; 1513 PnvICPState *icp; 1514 1515 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1516 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1517 1518 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1519 &icp->mmio); 1520 } 1521 } 1522 } 1523 1524 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1525 { 1526 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1527 PnvChip *chip = PNV_CHIP(dev); 1528 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1529 Pnv8Psi *psi8 = &chip8->psi; 1530 Error *local_err = NULL; 1531 int i; 1532 1533 assert(chip8->xics); 1534 1535 /* XSCOM bridge is first */ 1536 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1537 1538 pcc->parent_realize(dev, &local_err); 1539 if (local_err) { 1540 error_propagate(errp, local_err); 1541 return; 1542 } 1543 1544 /* Processor Service Interface (PSI) Host Bridge */ 1545 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1546 &error_fatal); 1547 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1548 OBJECT(chip8->xics), &error_abort); 1549 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1550 return; 1551 } 1552 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1553 &PNV_PSI(psi8)->xscom_regs); 1554 1555 /* Create LPC controller */ 1556 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1557 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1558 1559 chip->fw_mr = &chip8->lpc.isa_fw; 1560 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1561 (uint64_t) PNV_XSCOM_BASE(chip), 1562 PNV_XSCOM_LPC_BASE); 1563 1564 /* 1565 * Interrupt Management Area. This is the memory region holding 1566 * all the Interrupt Control Presenter (ICP) registers 1567 */ 1568 pnv_chip_icp_realize(chip8, &local_err); 1569 if (local_err) { 1570 error_propagate(errp, local_err); 1571 return; 1572 } 1573 1574 /* HOMER (must be created before OCC) */ 1575 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1576 &error_abort); 1577 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1578 return; 1579 } 1580 /* Homer Xscom region */ 1581 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1582 /* Homer RAM region */ 1583 memory_region_add_subregion(get_system_memory(), chip8->homer.base, 1584 &chip8->homer.mem); 1585 1586 /* Create the simplified OCC model */ 1587 object_property_set_link(OBJECT(&chip8->occ), "homer", 1588 OBJECT(&chip8->homer), &error_abort); 1589 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1590 return; 1591 } 1592 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1593 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1594 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1595 1596 /* OCC SRAM model */ 1597 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1598 &chip8->occ.sram_regs); 1599 1600 /* PHB controllers */ 1601 for (i = 0; i < chip8->num_phbs; i++) { 1602 PnvPHB *phb = chip8->phbs[i]; 1603 1604 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1605 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1606 &error_fatal); 1607 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1608 &error_fatal); 1609 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1610 return; 1611 } 1612 } 1613 } 1614 1615 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1616 { 1617 addr &= (PNV_XSCOM_SIZE - 1); 1618 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1619 } 1620 1621 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1622 { 1623 DeviceClass *dc = DEVICE_CLASS(klass); 1624 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1625 1626 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1627 k->cores_mask = POWER8E_CORE_MASK; 1628 k->num_phbs = 3; 1629 k->get_pir_tir = pnv_get_pir_tir_p8; 1630 k->intc_create = pnv_chip_power8_intc_create; 1631 k->intc_reset = pnv_chip_power8_intc_reset; 1632 k->intc_destroy = pnv_chip_power8_intc_destroy; 1633 k->intc_print_info = pnv_chip_power8_intc_print_info; 1634 k->isa_create = pnv_chip_power8_isa_create; 1635 k->dt_populate = pnv_chip_power8_dt_populate; 1636 k->pic_print_info = pnv_chip_power8_pic_print_info; 1637 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1638 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1639 dc->desc = "PowerNV Chip POWER8E"; 1640 1641 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1642 &k->parent_realize); 1643 } 1644 1645 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1646 { 1647 DeviceClass *dc = DEVICE_CLASS(klass); 1648 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1649 1650 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1651 k->cores_mask = POWER8_CORE_MASK; 1652 k->num_phbs = 3; 1653 k->get_pir_tir = pnv_get_pir_tir_p8; 1654 k->intc_create = pnv_chip_power8_intc_create; 1655 k->intc_reset = pnv_chip_power8_intc_reset; 1656 k->intc_destroy = pnv_chip_power8_intc_destroy; 1657 k->intc_print_info = pnv_chip_power8_intc_print_info; 1658 k->isa_create = pnv_chip_power8_isa_create; 1659 k->dt_populate = pnv_chip_power8_dt_populate; 1660 k->pic_print_info = pnv_chip_power8_pic_print_info; 1661 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1662 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1663 dc->desc = "PowerNV Chip POWER8"; 1664 1665 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1666 &k->parent_realize); 1667 } 1668 1669 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1670 { 1671 DeviceClass *dc = DEVICE_CLASS(klass); 1672 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1673 1674 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1675 k->cores_mask = POWER8_CORE_MASK; 1676 k->num_phbs = 4; 1677 k->get_pir_tir = pnv_get_pir_tir_p8; 1678 k->intc_create = pnv_chip_power8_intc_create; 1679 k->intc_reset = pnv_chip_power8_intc_reset; 1680 k->intc_destroy = pnv_chip_power8_intc_destroy; 1681 k->intc_print_info = pnv_chip_power8_intc_print_info; 1682 k->isa_create = pnv_chip_power8nvl_isa_create; 1683 k->dt_populate = pnv_chip_power8_dt_populate; 1684 k->pic_print_info = pnv_chip_power8_pic_print_info; 1685 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1686 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1687 dc->desc = "PowerNV Chip POWER8NVL"; 1688 1689 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1690 &k->parent_realize); 1691 } 1692 1693 static void pnv_chip_power9_instance_init(Object *obj) 1694 { 1695 PnvChip *chip = PNV_CHIP(obj); 1696 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1697 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1698 int i; 1699 1700 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1701 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1702 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1703 "xive-fabric"); 1704 1705 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1706 1707 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1708 1709 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1710 1711 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1712 1713 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1714 1715 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1716 1717 /* Number of PECs is the chip default */ 1718 chip->num_pecs = pcc->num_pecs; 1719 1720 for (i = 0; i < chip->num_pecs; i++) { 1721 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1722 TYPE_PNV_PHB4_PEC); 1723 } 1724 1725 for (i = 0; i < pcc->i2c_num_engines; i++) { 1726 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1727 } 1728 } 1729 1730 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1731 PnvCore *pnv_core, 1732 const char *type) 1733 { 1734 char eq_name[32]; 1735 int core_id = CPU_CORE(pnv_core)->core_id; 1736 1737 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1738 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1739 sizeof(*eq), type, 1740 &error_fatal, NULL); 1741 1742 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1743 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1744 } 1745 1746 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1747 { 1748 PnvChip *chip = PNV_CHIP(chip9); 1749 int i; 1750 1751 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1752 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1753 1754 for (i = 0; i < chip9->nr_quads; i++) { 1755 PnvQuad *eq = &chip9->quads[i]; 1756 1757 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1758 PNV_QUAD_TYPE_NAME("power9")); 1759 1760 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1761 &eq->xscom_regs); 1762 } 1763 } 1764 1765 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1766 { 1767 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1768 int i; 1769 1770 for (i = 0; i < chip->num_pecs; i++) { 1771 PnvPhb4PecState *pec = &chip9->pecs[i]; 1772 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1773 uint32_t pec_cplt_base; 1774 uint32_t pec_nest_base; 1775 uint32_t pec_pci_base; 1776 1777 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1778 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1779 &error_fatal); 1780 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1781 &error_fatal); 1782 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1783 return; 1784 } 1785 1786 pec_cplt_base = pecc->xscom_cplt_base(pec); 1787 pec_nest_base = pecc->xscom_nest_base(pec); 1788 pec_pci_base = pecc->xscom_pci_base(pec); 1789 1790 pnv_xscom_add_subregion(chip, pec_cplt_base, 1791 &pec->nest_pervasive.xscom_ctrl_regs_mr); 1792 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1793 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1794 } 1795 } 1796 1797 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1798 { 1799 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1800 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1801 PnvChip *chip = PNV_CHIP(dev); 1802 Pnv9Psi *psi9 = &chip9->psi; 1803 Error *local_err = NULL; 1804 int i; 1805 1806 /* XSCOM bridge is first */ 1807 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1808 1809 pcc->parent_realize(dev, &local_err); 1810 if (local_err) { 1811 error_propagate(errp, local_err); 1812 return; 1813 } 1814 1815 /* ADU */ 1816 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1817 &error_abort); 1818 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1819 return; 1820 } 1821 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1822 &chip9->adu.xscom_regs); 1823 1824 pnv_chip_quad_realize(chip9, &local_err); 1825 if (local_err) { 1826 error_propagate(errp, local_err); 1827 return; 1828 } 1829 1830 /* XIVE interrupt controller (POWER9) */ 1831 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1832 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1833 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1834 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1835 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1836 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1837 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1838 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1839 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1840 &error_abort); 1841 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1842 return; 1843 } 1844 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1845 &chip9->xive.xscom_regs); 1846 1847 /* Processor Service Interface (PSI) Host Bridge */ 1848 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1849 &error_fatal); 1850 /* This is the only device with 4k ESB pages */ 1851 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1852 &error_fatal); 1853 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1854 return; 1855 } 1856 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1857 &PNV_PSI(psi9)->xscom_regs); 1858 1859 /* LPC */ 1860 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1861 return; 1862 } 1863 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1864 &chip9->lpc.xscom_regs); 1865 1866 chip->fw_mr = &chip9->lpc.isa_fw; 1867 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1868 (uint64_t) PNV9_LPCM_BASE(chip)); 1869 1870 /* ChipTOD */ 1871 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1872 chip->chip_id == 0, &error_abort); 1873 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1874 chip->chip_id == 1, &error_abort); 1875 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1876 &error_abort); 1877 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1878 return; 1879 } 1880 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1881 &chip9->chiptod.xscom_regs); 1882 1883 /* SBE */ 1884 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1885 return; 1886 } 1887 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1888 &chip9->sbe.xscom_ctrl_regs); 1889 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1890 &chip9->sbe.xscom_mbox_regs); 1891 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1892 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1893 1894 /* HOMER (must be created before OCC) */ 1895 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1896 &error_abort); 1897 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1898 return; 1899 } 1900 /* Homer Xscom region */ 1901 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1902 /* Homer RAM region */ 1903 memory_region_add_subregion(get_system_memory(), chip9->homer.base, 1904 &chip9->homer.mem); 1905 1906 /* Create the simplified OCC model */ 1907 object_property_set_link(OBJECT(&chip9->occ), "homer", 1908 OBJECT(&chip9->homer), &error_abort); 1909 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1910 return; 1911 } 1912 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1913 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1914 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1915 1916 /* OCC SRAM model */ 1917 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1918 &chip9->occ.sram_regs); 1919 1920 /* PEC PHBs */ 1921 pnv_chip_power9_pec_realize(chip, &local_err); 1922 if (local_err) { 1923 error_propagate(errp, local_err); 1924 return; 1925 } 1926 1927 /* 1928 * I2C 1929 */ 1930 for (i = 0; i < pcc->i2c_num_engines; i++) { 1931 Object *obj = OBJECT(&chip9->i2c[i]); 1932 1933 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1934 object_property_set_int(obj, "num-busses", 1935 pcc->i2c_ports_per_engine[i], 1936 &error_fatal); 1937 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1938 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1939 return; 1940 } 1941 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1942 (chip9->i2c[i].engine - 1) * 1943 PNV9_XSCOM_I2CM_SIZE, 1944 &chip9->i2c[i].xscom_regs); 1945 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1946 qdev_get_gpio_in(DEVICE(psi9), 1947 PSIHB9_IRQ_SBE_I2C)); 1948 } 1949 } 1950 1951 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1952 { 1953 addr &= (PNV9_XSCOM_SIZE - 1); 1954 return addr >> 3; 1955 } 1956 1957 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1958 { 1959 DeviceClass *dc = DEVICE_CLASS(klass); 1960 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1961 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1962 1963 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1964 k->cores_mask = POWER9_CORE_MASK; 1965 k->get_pir_tir = pnv_get_pir_tir_p9; 1966 k->intc_create = pnv_chip_power9_intc_create; 1967 k->intc_reset = pnv_chip_power9_intc_reset; 1968 k->intc_destroy = pnv_chip_power9_intc_destroy; 1969 k->intc_print_info = pnv_chip_power9_intc_print_info; 1970 k->isa_create = pnv_chip_power9_isa_create; 1971 k->dt_populate = pnv_chip_power9_dt_populate; 1972 k->pic_print_info = pnv_chip_power9_pic_print_info; 1973 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1974 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1975 dc->desc = "PowerNV Chip POWER9"; 1976 k->num_pecs = PNV9_CHIP_MAX_PEC; 1977 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1978 k->i2c_ports_per_engine = i2c_ports_per_engine; 1979 1980 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1981 &k->parent_realize); 1982 } 1983 1984 static void pnv_chip_power10_instance_init(Object *obj) 1985 { 1986 PnvChip *chip = PNV_CHIP(obj); 1987 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1988 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1989 int i; 1990 1991 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1992 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1993 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1994 "xive-fabric"); 1995 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1996 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1997 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1998 TYPE_PNV10_CHIPTOD); 1999 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 2000 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 2001 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 2002 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 2003 TYPE_PNV_N1_CHIPLET); 2004 2005 chip->num_pecs = pcc->num_pecs; 2006 2007 for (i = 0; i < chip->num_pecs; i++) { 2008 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 2009 TYPE_PNV_PHB5_PEC); 2010 } 2011 2012 for (i = 0; i < pcc->i2c_num_engines; i++) { 2013 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 2014 } 2015 2016 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2017 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], 2018 TYPE_PNV_SPI); 2019 } 2020 } 2021 2022 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 2023 { 2024 PnvChip *chip = PNV_CHIP(chip10); 2025 int i; 2026 2027 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 2028 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 2029 2030 for (i = 0; i < chip10->nr_quads; i++) { 2031 PnvQuad *eq = &chip10->quads[i]; 2032 2033 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 2034 PNV_QUAD_TYPE_NAME("power10")); 2035 2036 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 2037 &eq->xscom_regs); 2038 2039 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 2040 &eq->xscom_qme_regs); 2041 } 2042 } 2043 2044 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 2045 { 2046 Pnv10Chip *chip10 = PNV10_CHIP(chip); 2047 int i; 2048 2049 for (i = 0; i < chip->num_pecs; i++) { 2050 PnvPhb4PecState *pec = &chip10->pecs[i]; 2051 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 2052 uint32_t pec_cplt_base; 2053 uint32_t pec_nest_base; 2054 uint32_t pec_pci_base; 2055 2056 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 2057 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 2058 &error_fatal); 2059 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 2060 &error_fatal); 2061 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 2062 return; 2063 } 2064 2065 pec_cplt_base = pecc->xscom_cplt_base(pec); 2066 pec_nest_base = pecc->xscom_nest_base(pec); 2067 pec_pci_base = pecc->xscom_pci_base(pec); 2068 2069 pnv_xscom_add_subregion(chip, pec_cplt_base, 2070 &pec->nest_pervasive.xscom_ctrl_regs_mr); 2071 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2072 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2073 } 2074 } 2075 2076 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 2077 { 2078 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2079 PnvChip *chip = PNV_CHIP(dev); 2080 Pnv10Chip *chip10 = PNV10_CHIP(dev); 2081 Error *local_err = NULL; 2082 int i; 2083 2084 /* XSCOM bridge is first */ 2085 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 2086 2087 pcc->parent_realize(dev, &local_err); 2088 if (local_err) { 2089 error_propagate(errp, local_err); 2090 return; 2091 } 2092 2093 /* ADU */ 2094 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2095 &error_abort); 2096 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2097 return; 2098 } 2099 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2100 &chip10->adu.xscom_regs); 2101 2102 pnv_chip_power10_quad_realize(chip10, &local_err); 2103 if (local_err) { 2104 error_propagate(errp, local_err); 2105 return; 2106 } 2107 2108 /* XIVE2 interrupt controller (POWER10) */ 2109 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2110 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2111 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2112 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2113 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2114 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2115 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2116 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2117 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2118 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2119 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2120 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2121 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2122 &error_abort); 2123 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2124 return; 2125 } 2126 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2127 &chip10->xive.xscom_regs); 2128 2129 /* Processor Service Interface (PSI) Host Bridge */ 2130 object_property_set_int(OBJECT(&chip10->psi), "bar", 2131 PNV10_PSIHB_BASE(chip), &error_fatal); 2132 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2133 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2134 &error_fatal); 2135 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2136 return; 2137 } 2138 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2139 &PNV_PSI(&chip10->psi)->xscom_regs); 2140 2141 /* LPC */ 2142 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2143 return; 2144 } 2145 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2146 &chip10->lpc.xscom_regs); 2147 2148 chip->fw_mr = &chip10->lpc.isa_fw; 2149 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2150 (uint64_t) PNV10_LPCM_BASE(chip)); 2151 2152 /* ChipTOD */ 2153 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2154 chip->chip_id == 0, &error_abort); 2155 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2156 chip->chip_id == 1, &error_abort); 2157 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2158 &error_abort); 2159 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2160 return; 2161 } 2162 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2163 &chip10->chiptod.xscom_regs); 2164 2165 /* HOMER (must be created before OCC) */ 2166 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2167 &error_abort); 2168 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2169 return; 2170 } 2171 /* Homer Xscom region */ 2172 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2173 &chip10->homer.pba_regs); 2174 /* Homer RAM region */ 2175 memory_region_add_subregion(get_system_memory(), chip10->homer.base, 2176 &chip10->homer.mem); 2177 2178 /* Create the simplified OCC model */ 2179 object_property_set_link(OBJECT(&chip10->occ), "homer", 2180 OBJECT(&chip10->homer), &error_abort); 2181 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2182 return; 2183 } 2184 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2185 &chip10->occ.xscom_regs); 2186 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2187 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2188 2189 /* OCC SRAM model */ 2190 memory_region_add_subregion(get_system_memory(), 2191 PNV10_OCC_SENSOR_BASE(chip), 2192 &chip10->occ.sram_regs); 2193 2194 /* SBE */ 2195 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2196 return; 2197 } 2198 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2199 &chip10->sbe.xscom_ctrl_regs); 2200 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2201 &chip10->sbe.xscom_mbox_regs); 2202 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2203 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2204 2205 /* N1 chiplet */ 2206 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2207 return; 2208 } 2209 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2210 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2211 2212 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2213 &chip10->n1_chiplet.xscom_pb_eq_mr); 2214 2215 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2216 &chip10->n1_chiplet.xscom_pb_es_mr); 2217 2218 /* PHBs */ 2219 pnv_chip_power10_phb_realize(chip, &local_err); 2220 if (local_err) { 2221 error_propagate(errp, local_err); 2222 return; 2223 } 2224 2225 2226 /* 2227 * I2C 2228 */ 2229 for (i = 0; i < pcc->i2c_num_engines; i++) { 2230 Object *obj = OBJECT(&chip10->i2c[i]); 2231 2232 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2233 object_property_set_int(obj, "num-busses", 2234 pcc->i2c_ports_per_engine[i], 2235 &error_fatal); 2236 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2237 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2238 return; 2239 } 2240 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2241 (chip10->i2c[i].engine - 1) * 2242 PNV10_XSCOM_I2CM_SIZE, 2243 &chip10->i2c[i].xscom_regs); 2244 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2245 qdev_get_gpio_in(DEVICE(&chip10->psi), 2246 PSIHB9_IRQ_SBE_I2C)); 2247 } 2248 /* PIB SPI Controller */ 2249 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2250 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", 2251 i, &error_fatal); 2252 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */ 2253 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", 2254 (i == 2) ? 1 : 4, &error_fatal); 2255 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "chip-id", 2256 chip->chip_id, &error_fatal); 2257 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT 2258 (&chip10->pib_spic[i])), errp)) { 2259 return; 2260 } 2261 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + 2262 i * PNV10_XSCOM_PIB_SPIC_SIZE, 2263 &chip10->pib_spic[i].xscom_spic_regs); 2264 } 2265 } 2266 2267 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2268 { 2269 int i; 2270 for (i = 0; i < pnv->num_chips; i++) { 2271 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2272 2273 /* 2274 * Add a PCA9552 I2C device for PCIe hotplug control 2275 * to engine 2, bus 1, address 0x63 2276 */ 2277 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2278 "pca9552", 0x63); 2279 2280 /* 2281 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2282 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2283 * after hypervisor code sets a SLOTx_EN pin high. 2284 */ 2285 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2286 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2287 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2288 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2289 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2290 2291 /* 2292 * Add a PCA9554 I2C device for cable card presence detection 2293 * to engine 2, bus 1, address 0x25 2294 */ 2295 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2296 } 2297 } 2298 2299 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2300 { 2301 addr &= (PNV10_XSCOM_SIZE - 1); 2302 return addr >> 3; 2303 } 2304 2305 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2306 { 2307 DeviceClass *dc = DEVICE_CLASS(klass); 2308 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2309 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2310 2311 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2312 k->cores_mask = POWER10_CORE_MASK; 2313 k->get_pir_tir = pnv_get_pir_tir_p10; 2314 k->intc_create = pnv_chip_power10_intc_create; 2315 k->intc_reset = pnv_chip_power10_intc_reset; 2316 k->intc_destroy = pnv_chip_power10_intc_destroy; 2317 k->intc_print_info = pnv_chip_power10_intc_print_info; 2318 k->isa_create = pnv_chip_power10_isa_create; 2319 k->dt_populate = pnv_chip_power10_dt_populate; 2320 k->pic_print_info = pnv_chip_power10_pic_print_info; 2321 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2322 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2323 dc->desc = "PowerNV Chip POWER10"; 2324 k->num_pecs = PNV10_CHIP_MAX_PEC; 2325 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2326 k->i2c_ports_per_engine = i2c_ports_per_engine; 2327 2328 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2329 &k->parent_realize); 2330 } 2331 2332 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2333 Error **errp) 2334 { 2335 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2336 int cores_max; 2337 2338 /* 2339 * No custom mask for this chip, let's use the default one from * 2340 * the chip class 2341 */ 2342 if (!chip->cores_mask) { 2343 chip->cores_mask = pcc->cores_mask; 2344 } 2345 2346 /* filter alien core ids ! some are reserved */ 2347 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2348 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2349 chip->cores_mask); 2350 return; 2351 } 2352 chip->cores_mask &= pcc->cores_mask; 2353 2354 /* Ensure small-cores a paired up in big-core mode */ 2355 if (pnv->big_core) { 2356 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2357 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2358 2359 if (even_cores ^ (odd_cores >> 1)) { 2360 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2361 return; 2362 } 2363 } 2364 2365 /* now that we have a sane layout, let check the number of cores */ 2366 cores_max = ctpop64(chip->cores_mask); 2367 if (chip->nr_cores > cores_max) { 2368 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2369 cores_max); 2370 return; 2371 } 2372 } 2373 2374 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2375 { 2376 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2377 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); 2378 Error *error = NULL; 2379 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2380 const char *typename = pnv_chip_core_typename(chip); 2381 int i, core_hwid; 2382 2383 if (!object_class_by_name(typename)) { 2384 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2385 return; 2386 } 2387 2388 /* Cores */ 2389 pnv_chip_core_sanitize(pnv, chip, &error); 2390 if (error) { 2391 error_propagate(errp, error); 2392 return; 2393 } 2394 2395 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2396 2397 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2398 && (i < chip->nr_cores); core_hwid++) { 2399 char core_name[32]; 2400 PnvCore *pnv_core; 2401 uint64_t xscom_core_base; 2402 2403 if (!(chip->cores_mask & (1ull << core_hwid))) { 2404 continue; 2405 } 2406 2407 pnv_core = PNV_CORE(object_new(typename)); 2408 2409 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2410 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2411 chip->cores[i] = pnv_core; 2412 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2413 chip->nr_threads, &error_fatal); 2414 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2415 core_hwid, &error_fatal); 2416 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2417 &error_fatal); 2418 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2419 &error_fatal); 2420 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2421 &error_fatal); 2422 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", 2423 pmc->quirk_tb_big_core, &error_fatal); 2424 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", 2425 chip->lpar_per_core, &error_fatal); 2426 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2427 &error_abort); 2428 2429 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2430 2431 /* Each core has an XSCOM MMIO region */ 2432 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2433 2434 pnv_xscom_add_subregion(chip, xscom_core_base, 2435 &pnv_core->xscom_regs); 2436 i++; 2437 } 2438 } 2439 2440 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2441 { 2442 PnvChip *chip = PNV_CHIP(dev); 2443 Error *error = NULL; 2444 2445 /* Cores */ 2446 pnv_chip_core_realize(chip, &error); 2447 if (error) { 2448 error_propagate(errp, error); 2449 return; 2450 } 2451 } 2452 2453 static const Property pnv_chip_properties[] = { 2454 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2455 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2456 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2457 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2458 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2459 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2460 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2461 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false), 2462 }; 2463 2464 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2465 { 2466 DeviceClass *dc = DEVICE_CLASS(klass); 2467 2468 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2469 dc->realize = pnv_chip_realize; 2470 device_class_set_props(dc, pnv_chip_properties); 2471 dc->desc = "PowerNV Chip"; 2472 } 2473 2474 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2475 { 2476 int i; 2477 2478 for (i = 0; i < chip->nr_cores; i++) { 2479 PnvCore *pc = chip->cores[i]; 2480 CPUCore *cc = CPU_CORE(pc); 2481 2482 if (cc->core_id == core_id) { 2483 return pc; 2484 } 2485 } 2486 return NULL; 2487 } 2488 2489 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2490 { 2491 int i, j; 2492 2493 for (i = 0; i < chip->nr_cores; i++) { 2494 PnvCore *pc = chip->cores[i]; 2495 CPUCore *cc = CPU_CORE(pc); 2496 2497 for (j = 0; j < cc->nr_threads; j++) { 2498 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2499 return pc->threads[j]; 2500 } 2501 } 2502 } 2503 return NULL; 2504 } 2505 2506 static void pnv_chip_foreach_cpu(PnvChip *chip, 2507 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2508 void *opaque) 2509 { 2510 int i, j; 2511 2512 for (i = 0; i < chip->nr_cores; i++) { 2513 PnvCore *pc = chip->cores[i]; 2514 2515 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2516 fn(chip, pc->threads[j], opaque); 2517 } 2518 } 2519 } 2520 2521 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2522 { 2523 PnvMachineState *pnv = PNV_MACHINE(xi); 2524 int i, j; 2525 2526 for (i = 0; i < pnv->num_chips; i++) { 2527 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2528 2529 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2530 return &chip8->psi.ics; 2531 } 2532 2533 for (j = 0; j < chip8->num_phbs; j++) { 2534 PnvPHB *phb = chip8->phbs[j]; 2535 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2536 2537 if (ics_valid_irq(&phb3->lsis, irq)) { 2538 return &phb3->lsis; 2539 } 2540 2541 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2542 return ICS(&phb3->msis); 2543 } 2544 } 2545 } 2546 return NULL; 2547 } 2548 2549 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2550 { 2551 int i; 2552 2553 for (i = 0; i < pnv->num_chips; i++) { 2554 PnvChip *chip = pnv->chips[i]; 2555 if (chip->chip_id == chip_id) { 2556 return chip; 2557 } 2558 } 2559 return NULL; 2560 } 2561 2562 static void pnv_ics_resend(XICSFabric *xi) 2563 { 2564 PnvMachineState *pnv = PNV_MACHINE(xi); 2565 int i, j; 2566 2567 for (i = 0; i < pnv->num_chips; i++) { 2568 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2569 2570 ics_resend(&chip8->psi.ics); 2571 2572 for (j = 0; j < chip8->num_phbs; j++) { 2573 PnvPHB *phb = chip8->phbs[j]; 2574 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2575 2576 ics_resend(&phb3->lsis); 2577 ics_resend(ICS(&phb3->msis)); 2578 } 2579 } 2580 } 2581 2582 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2583 { 2584 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2585 2586 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2587 } 2588 2589 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2590 void *opaque) 2591 { 2592 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2593 } 2594 2595 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2596 { 2597 PnvMachineState *pnv = PNV_MACHINE(obj); 2598 int i; 2599 2600 for (i = 0; i < pnv->num_chips; i++) { 2601 PnvChip *chip = pnv->chips[i]; 2602 2603 /* First CPU presenters */ 2604 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2605 2606 /* Then other devices, PHB, PSI, XIVE */ 2607 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2608 } 2609 } 2610 2611 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2612 uint8_t nvt_blk, uint32_t nvt_idx, 2613 bool crowd, bool cam_ignore, uint8_t priority, 2614 uint32_t logic_serv, 2615 XiveTCTXMatch *match) 2616 { 2617 PnvMachineState *pnv = PNV_MACHINE(xfb); 2618 int total_count = 0; 2619 int i; 2620 2621 for (i = 0; i < pnv->num_chips; i++) { 2622 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2623 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2624 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2625 int count; 2626 2627 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, 2628 cam_ignore, priority, logic_serv, match); 2629 2630 if (count < 0) { 2631 return count; 2632 } 2633 2634 total_count += count; 2635 } 2636 2637 return total_count; 2638 } 2639 2640 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2641 uint8_t nvt_blk, uint32_t nvt_idx, 2642 bool crowd, bool cam_ignore, uint8_t priority, 2643 uint32_t logic_serv, 2644 XiveTCTXMatch *match) 2645 { 2646 PnvMachineState *pnv = PNV_MACHINE(xfb); 2647 int total_count = 0; 2648 int i; 2649 2650 for (i = 0; i < pnv->num_chips; i++) { 2651 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2652 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2653 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2654 int count; 2655 2656 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, 2657 cam_ignore, priority, logic_serv, match); 2658 2659 if (count < 0) { 2660 return count; 2661 } 2662 2663 total_count += count; 2664 } 2665 2666 return total_count; 2667 } 2668 2669 static int pnv10_xive_broadcast(XiveFabric *xfb, 2670 uint8_t nvt_blk, uint32_t nvt_idx, 2671 bool crowd, bool cam_ignore, 2672 uint8_t priority) 2673 { 2674 PnvMachineState *pnv = PNV_MACHINE(xfb); 2675 int i; 2676 2677 for (i = 0; i < pnv->num_chips; i++) { 2678 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2679 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2680 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2681 2682 xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority); 2683 } 2684 return 0; 2685 } 2686 2687 static bool pnv_machine_get_big_core(Object *obj, Error **errp) 2688 { 2689 PnvMachineState *pnv = PNV_MACHINE(obj); 2690 return pnv->big_core; 2691 } 2692 2693 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp) 2694 { 2695 PnvMachineState *pnv = PNV_MACHINE(obj); 2696 pnv->big_core = value; 2697 } 2698 2699 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp) 2700 { 2701 PnvMachineState *pnv = PNV_MACHINE(obj); 2702 return pnv->lpar_per_core; 2703 } 2704 2705 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp) 2706 { 2707 PnvMachineState *pnv = PNV_MACHINE(obj); 2708 pnv->lpar_per_core = value; 2709 } 2710 2711 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2712 { 2713 PnvMachineState *pnv = PNV_MACHINE(obj); 2714 2715 return !!pnv->fw_load_addr; 2716 } 2717 2718 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2719 { 2720 PnvMachineState *pnv = PNV_MACHINE(obj); 2721 2722 if (value) { 2723 pnv->fw_load_addr = 0x8000000; 2724 } 2725 } 2726 2727 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2728 { 2729 MachineClass *mc = MACHINE_CLASS(oc); 2730 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2731 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2732 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2733 2734 static GlobalProperty phb_compat[] = { 2735 { TYPE_PNV_PHB, "version", "3" }, 2736 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2737 }; 2738 2739 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2740 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2741 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2742 2743 xic->icp_get = pnv_icp_get; 2744 xic->ics_get = pnv_ics_get; 2745 xic->ics_resend = pnv_ics_resend; 2746 2747 pmc->compat = compat; 2748 pmc->compat_size = sizeof(compat); 2749 pmc->max_smt_threads = 8; 2750 /* POWER8 is always lpar-per-core mode */ 2751 pmc->has_lpar_per_thread = false; 2752 2753 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2754 } 2755 2756 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2757 { 2758 MachineClass *mc = MACHINE_CLASS(oc); 2759 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2760 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2761 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2762 2763 static GlobalProperty phb_compat[] = { 2764 { TYPE_PNV_PHB, "version", "4" }, 2765 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2766 }; 2767 2768 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2769 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2770 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2771 2772 xfc->match_nvt = pnv_match_nvt; 2773 2774 pmc->compat = compat; 2775 pmc->compat_size = sizeof(compat); 2776 pmc->max_smt_threads = 4; 2777 pmc->has_lpar_per_thread = true; 2778 pmc->dt_power_mgt = pnv_dt_power_mgt; 2779 2780 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2781 2782 object_class_property_add_bool(oc, "big-core", 2783 pnv_machine_get_big_core, 2784 pnv_machine_set_big_core); 2785 object_class_property_set_description(oc, "big-core", 2786 "Use big-core (aka fused-core) mode"); 2787 2788 object_class_property_add_bool(oc, "lpar-per-core", 2789 pnv_machine_get_lpar_per_core, 2790 pnv_machine_set_lpar_per_core); 2791 object_class_property_set_description(oc, "lpar-per-core", 2792 "Use 1 LPAR per core mode"); 2793 } 2794 2795 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2796 { 2797 MachineClass *mc = MACHINE_CLASS(oc); 2798 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2799 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2800 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2801 2802 static GlobalProperty phb_compat[] = { 2803 { TYPE_PNV_PHB, "version", "5" }, 2804 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2805 }; 2806 2807 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2808 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2809 2810 mc->alias = "powernv"; 2811 2812 pmc->compat = compat; 2813 pmc->compat_size = sizeof(compat); 2814 pmc->max_smt_threads = 4; 2815 pmc->has_lpar_per_thread = true; 2816 pmc->quirk_tb_big_core = true; 2817 pmc->dt_power_mgt = pnv_dt_power_mgt; 2818 2819 xfc->match_nvt = pnv10_xive_match_nvt; 2820 xfc->broadcast = pnv10_xive_broadcast; 2821 2822 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2823 } 2824 2825 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2826 { 2827 MachineClass *mc = MACHINE_CLASS(oc); 2828 2829 pnv_machine_p10_common_class_init(oc, data); 2830 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2831 2832 /* 2833 * This is the parent of POWER10 Rainier class, so properies go here 2834 * rather than common init (which would add them to both parent and 2835 * child which is invalid). 2836 */ 2837 object_class_property_add_bool(oc, "big-core", 2838 pnv_machine_get_big_core, 2839 pnv_machine_set_big_core); 2840 object_class_property_set_description(oc, "big-core", 2841 "Use big-core (aka fused-core) mode"); 2842 2843 object_class_property_add_bool(oc, "lpar-per-core", 2844 pnv_machine_get_lpar_per_core, 2845 pnv_machine_set_lpar_per_core); 2846 object_class_property_set_description(oc, "lpar-per-core", 2847 "Use 1 LPAR per core mode"); 2848 } 2849 2850 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2851 { 2852 MachineClass *mc = MACHINE_CLASS(oc); 2853 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2854 2855 pnv_machine_p10_common_class_init(oc, data); 2856 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2857 pmc->i2c_init = pnv_rainier_i2c_init; 2858 } 2859 2860 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2861 { 2862 CPUPPCState *env = cpu_env(cs); 2863 2864 cpu_synchronize_state(cs); 2865 ppc_cpu_do_system_reset(cs); 2866 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2867 /* 2868 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2869 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2870 * (PPC_BIT(43)). 2871 */ 2872 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2873 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2874 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2875 } 2876 } else { 2877 /* 2878 * For non-powersave system resets, SRR1[42:45] are defined to be 2879 * implementation-dependent. The POWER9 User Manual specifies that 2880 * an external (SCOM driven, which may come from a BMC nmi command or 2881 * another CPU requesting a NMI IPI) system reset exception should be 2882 * 0b0010 (PPC_BIT(44)). 2883 */ 2884 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2885 } 2886 if (arg.host_int == 1) { 2887 cpu_resume(cs); 2888 } 2889 } 2890 2891 /* 2892 * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was 2893 * paused. 2894 */ 2895 void pnv_cpu_do_nmi_resume(CPUState *cs) 2896 { 2897 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1)); 2898 } 2899 2900 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2901 { 2902 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0)); 2903 } 2904 2905 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2906 { 2907 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2908 int i; 2909 2910 for (i = 0; i < pnv->num_chips; i++) { 2911 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2912 } 2913 } 2914 2915 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2916 { 2917 MachineClass *mc = MACHINE_CLASS(oc); 2918 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2919 NMIClass *nc = NMI_CLASS(oc); 2920 2921 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2922 mc->init = pnv_init; 2923 mc->reset = pnv_reset; 2924 mc->max_cpus = MAX_CPUS; 2925 /* Pnv provides a AHCI device for storage */ 2926 mc->block_default_type = IF_IDE; 2927 mc->no_parallel = 1; 2928 mc->default_boot_order = NULL; 2929 /* 2930 * RAM defaults to less than 2048 for 32-bit hosts, and large 2931 * enough to fit the maximum initrd size at it's load address 2932 */ 2933 mc->default_ram_size = 1 * GiB; 2934 mc->default_ram_id = "pnv.ram"; 2935 ispc->print_info = pnv_pic_print_info; 2936 nc->nmi_monitor_handler = pnv_nmi; 2937 2938 object_class_property_add_bool(oc, "hb-mode", 2939 pnv_machine_get_hb, pnv_machine_set_hb); 2940 object_class_property_set_description(oc, "hb-mode", 2941 "Use a hostboot like boot loader"); 2942 } 2943 2944 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2945 { \ 2946 .name = type, \ 2947 .class_init = class_initfn, \ 2948 .parent = TYPE_PNV8_CHIP, \ 2949 } 2950 2951 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2952 { \ 2953 .name = type, \ 2954 .class_init = class_initfn, \ 2955 .parent = TYPE_PNV9_CHIP, \ 2956 } 2957 2958 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2959 { \ 2960 .name = type, \ 2961 .class_init = class_initfn, \ 2962 .parent = TYPE_PNV10_CHIP, \ 2963 } 2964 2965 static const TypeInfo types[] = { 2966 { 2967 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2968 .parent = MACHINE_TYPE_NAME("powernv10"), 2969 .class_init = pnv_machine_p10_rainier_class_init, 2970 }, 2971 { 2972 .name = MACHINE_TYPE_NAME("powernv10"), 2973 .parent = TYPE_PNV_MACHINE, 2974 .class_init = pnv_machine_power10_class_init, 2975 .interfaces = (InterfaceInfo[]) { 2976 { TYPE_XIVE_FABRIC }, 2977 { }, 2978 }, 2979 }, 2980 { 2981 .name = MACHINE_TYPE_NAME("powernv9"), 2982 .parent = TYPE_PNV_MACHINE, 2983 .class_init = pnv_machine_power9_class_init, 2984 .interfaces = (InterfaceInfo[]) { 2985 { TYPE_XIVE_FABRIC }, 2986 { }, 2987 }, 2988 }, 2989 { 2990 .name = MACHINE_TYPE_NAME("powernv8"), 2991 .parent = TYPE_PNV_MACHINE, 2992 .class_init = pnv_machine_power8_class_init, 2993 .interfaces = (InterfaceInfo[]) { 2994 { TYPE_XICS_FABRIC }, 2995 { }, 2996 }, 2997 }, 2998 { 2999 .name = TYPE_PNV_MACHINE, 3000 .parent = TYPE_MACHINE, 3001 .abstract = true, 3002 .instance_size = sizeof(PnvMachineState), 3003 .class_init = pnv_machine_class_init, 3004 .class_size = sizeof(PnvMachineClass), 3005 .interfaces = (InterfaceInfo[]) { 3006 { TYPE_INTERRUPT_STATS_PROVIDER }, 3007 { TYPE_NMI }, 3008 { }, 3009 }, 3010 }, 3011 { 3012 .name = TYPE_PNV_CHIP, 3013 .parent = TYPE_SYS_BUS_DEVICE, 3014 .class_init = pnv_chip_class_init, 3015 .instance_size = sizeof(PnvChip), 3016 .class_size = sizeof(PnvChipClass), 3017 .abstract = true, 3018 }, 3019 3020 /* 3021 * P10 chip and variants 3022 */ 3023 { 3024 .name = TYPE_PNV10_CHIP, 3025 .parent = TYPE_PNV_CHIP, 3026 .instance_init = pnv_chip_power10_instance_init, 3027 .instance_size = sizeof(Pnv10Chip), 3028 }, 3029 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 3030 3031 /* 3032 * P9 chip and variants 3033 */ 3034 { 3035 .name = TYPE_PNV9_CHIP, 3036 .parent = TYPE_PNV_CHIP, 3037 .instance_init = pnv_chip_power9_instance_init, 3038 .instance_size = sizeof(Pnv9Chip), 3039 }, 3040 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 3041 3042 /* 3043 * P8 chip and variants 3044 */ 3045 { 3046 .name = TYPE_PNV8_CHIP, 3047 .parent = TYPE_PNV_CHIP, 3048 .instance_init = pnv_chip_power8_instance_init, 3049 .instance_size = sizeof(Pnv8Chip), 3050 }, 3051 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 3052 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 3053 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 3054 pnv_chip_power8nvl_class_init), 3055 }; 3056 3057 DEFINE_TYPES(types) 3058