xref: /qemu/hw/ppc/mpc8544_guts.c (revision 8063396bf3459a810d24e3efd6110b8480f0de5b)
1b0fb8423SAlexander Graf /*
2b0fb8423SAlexander Graf  * QEMU PowerPC MPC8544 global util pseudo-device
3b0fb8423SAlexander Graf  *
4b0fb8423SAlexander Graf  * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
5b0fb8423SAlexander Graf  *
6b0fb8423SAlexander Graf  * Author: Alexander Graf, <alex@csgraf.de>
7b0fb8423SAlexander Graf  *
8b0fb8423SAlexander Graf  * This is free software; you can redistribute it and/or modify
9b0fb8423SAlexander Graf  * it under the terms of  the GNU General  Public License as published by
10b0fb8423SAlexander Graf  * the Free Software Foundation;  either version 2 of the  License, or
11b0fb8423SAlexander Graf  * (at your option) any later version.
12b0fb8423SAlexander Graf  *
13b0fb8423SAlexander Graf  * *****************************************************************
14b0fb8423SAlexander Graf  *
15b0fb8423SAlexander Graf  * The documentation for this device is noted in the MPC8544 documentation,
16b0fb8423SAlexander Graf  * file name "MPC8544ERM.pdf". You can easily find it on the web.
17b0fb8423SAlexander Graf  *
18b0fb8423SAlexander Graf  */
19b0fb8423SAlexander Graf 
200d75590dSPeter Maydell #include "qemu/osdep.h"
210b8fa32fSMarkus Armbruster #include "qemu/module.h"
2254d31236SMarkus Armbruster #include "sysemu/runstate.h"
234771d756SPaolo Bonzini #include "cpu.h"
2483c9f4caSPaolo Bonzini #include "hw/sysbus.h"
25db1015e9SEduardo Habkost #include "qom/object.h"
26b0fb8423SAlexander Graf 
27b0fb8423SAlexander Graf #define MPC8544_GUTS_MMIO_SIZE        0x1000
28b0fb8423SAlexander Graf #define MPC8544_GUTS_RSTCR_RESET      0x02
29b0fb8423SAlexander Graf 
30b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORPLLSR    0x00
31b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORBMSR     0x04
32b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORIMPSCR   0x08
33b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR    0x0C
34b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDBGMSR   0x10
35b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR2   0x14
36b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPPORCR     0x20
37b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPIOCR      0x30
38b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPOUTDR     0x40
39b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPINDR      0x50
40b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PMUXCR      0x60
41b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DEVDISR     0x70
42b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_POWMGTCSR   0x80
43b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_MCPSUMR     0x90
44b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTRSCR     0x94
45b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PVR         0xA0
46b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SVR         0xA4
47b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTCR       0xB0
48b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_IOVSELSR    0xC0
49b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCSR      0xB20
50b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCDR      0xB24
51b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCLKDR    0xB28
52b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_CLKOCR      0xE00
53b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS1CR1    0xF04
54b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR1    0xF10
55b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR3    0xF18
56b0fb8423SAlexander Graf 
5743f691e9SAndreas Färber #define TYPE_MPC8544_GUTS "mpc8544-guts"
58*8063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(GutsState, MPC8544_GUTS)
5943f691e9SAndreas Färber 
60b0fb8423SAlexander Graf struct GutsState {
6143f691e9SAndreas Färber     /*< private >*/
6243f691e9SAndreas Färber     SysBusDevice parent_obj;
6343f691e9SAndreas Färber     /*< public >*/
6443f691e9SAndreas Färber 
651c7af35fSAvi Kivity     MemoryRegion iomem;
66b0fb8423SAlexander Graf };
67b0fb8423SAlexander Graf 
68b0fb8423SAlexander Graf 
69a8170e5eSAvi Kivity static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
701c7af35fSAvi Kivity                                   unsigned size)
71b0fb8423SAlexander Graf {
72b0fb8423SAlexander Graf     uint32_t value = 0;
734917cf44SAndreas Färber     PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
744917cf44SAndreas Färber     CPUPPCState *env = &cpu->env;
75b0fb8423SAlexander Graf 
76b0fb8423SAlexander Graf     addr &= MPC8544_GUTS_MMIO_SIZE - 1;
77b0fb8423SAlexander Graf     switch (addr) {
78b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_PVR:
79b0fb8423SAlexander Graf         value = env->spr[SPR_PVR];
80b0fb8423SAlexander Graf         break;
81b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_SVR:
82b0fb8423SAlexander Graf         value = env->spr[SPR_E500_SVR];
83b0fb8423SAlexander Graf         break;
84b0fb8423SAlexander Graf     default:
85b0fb8423SAlexander Graf         fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr);
86b0fb8423SAlexander Graf         break;
87b0fb8423SAlexander Graf     }
88b0fb8423SAlexander Graf 
89b0fb8423SAlexander Graf     return value;
90b0fb8423SAlexander Graf }
91b0fb8423SAlexander Graf 
92a8170e5eSAvi Kivity static void mpc8544_guts_write(void *opaque, hwaddr addr,
931c7af35fSAvi Kivity                                uint64_t value, unsigned size)
94b0fb8423SAlexander Graf {
95b0fb8423SAlexander Graf     addr &= MPC8544_GUTS_MMIO_SIZE - 1;
96b0fb8423SAlexander Graf 
97b0fb8423SAlexander Graf     switch (addr) {
98b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_RSTCR:
99b0fb8423SAlexander Graf         if (value & MPC8544_GUTS_RSTCR_RESET) {
100cf83f140SEric Blake             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
101b0fb8423SAlexander Graf         }
102b0fb8423SAlexander Graf         break;
103b0fb8423SAlexander Graf     default:
104b0fb8423SAlexander Graf         fprintf(stderr, "guts: Unknown register write: %x = %x\n",
1051c7af35fSAvi Kivity                 (int)addr, (unsigned)value);
106b0fb8423SAlexander Graf         break;
107b0fb8423SAlexander Graf     }
108b0fb8423SAlexander Graf }
109b0fb8423SAlexander Graf 
1101c7af35fSAvi Kivity static const MemoryRegionOps mpc8544_guts_ops = {
1111c7af35fSAvi Kivity     .read = mpc8544_guts_read,
1121c7af35fSAvi Kivity     .write = mpc8544_guts_write,
1131c7af35fSAvi Kivity     .endianness = DEVICE_BIG_ENDIAN,
1141c7af35fSAvi Kivity     .valid = {
1151c7af35fSAvi Kivity         .min_access_size = 4,
1161c7af35fSAvi Kivity         .max_access_size = 4,
1171c7af35fSAvi Kivity     },
118b0fb8423SAlexander Graf };
119b0fb8423SAlexander Graf 
1207587ea5bSAndreas Färber static void mpc8544_guts_initfn(Object *obj)
121b0fb8423SAlexander Graf {
1227587ea5bSAndreas Färber     SysBusDevice *d = SYS_BUS_DEVICE(obj);
1237587ea5bSAndreas Färber     GutsState *s = MPC8544_GUTS(obj);
124b0fb8423SAlexander Graf 
12540c5dce9SPaolo Bonzini     memory_region_init_io(&s->iomem, OBJECT(s), &mpc8544_guts_ops, s,
1261f1a83f4SAndreas Färber                           "mpc8544.guts", MPC8544_GUTS_MMIO_SIZE);
1277587ea5bSAndreas Färber     sysbus_init_mmio(d, &s->iomem);
128999e12bbSAnthony Liguori }
129999e12bbSAnthony Liguori 
1308c43a6f0SAndreas Färber static const TypeInfo mpc8544_guts_info = {
13143f691e9SAndreas Färber     .name          = TYPE_MPC8544_GUTS,
13239bffca2SAnthony Liguori     .parent        = TYPE_SYS_BUS_DEVICE,
13339bffca2SAnthony Liguori     .instance_size = sizeof(GutsState),
1347587ea5bSAndreas Färber     .instance_init = mpc8544_guts_initfn,
135b0fb8423SAlexander Graf };
136b0fb8423SAlexander Graf 
13783f7d43aSAndreas Färber static void mpc8544_guts_register_types(void)
138b0fb8423SAlexander Graf {
13939bffca2SAnthony Liguori     type_register_static(&mpc8544_guts_info);
140b0fb8423SAlexander Graf }
14183f7d43aSAndreas Färber 
14283f7d43aSAndreas Färber type_init(mpc8544_guts_register_types)
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