xref: /qemu/hw/ppc/mpc8544_guts.c (revision 794511bc51bc89f384063103653e5f40c75cd49e)
1b0fb8423SAlexander Graf /*
2b0fb8423SAlexander Graf  * QEMU PowerPC MPC8544 global util pseudo-device
3b0fb8423SAlexander Graf  *
4b0fb8423SAlexander Graf  * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
5b0fb8423SAlexander Graf  *
6b0fb8423SAlexander Graf  * Author: Alexander Graf, <alex@csgraf.de>
7b0fb8423SAlexander Graf  *
8b0fb8423SAlexander Graf  * This is free software; you can redistribute it and/or modify
9b0fb8423SAlexander Graf  * it under the terms of  the GNU General  Public License as published by
10b0fb8423SAlexander Graf  * the Free Software Foundation;  either version 2 of the  License, or
11b0fb8423SAlexander Graf  * (at your option) any later version.
12b0fb8423SAlexander Graf  *
13b0fb8423SAlexander Graf  * *****************************************************************
14b0fb8423SAlexander Graf  *
15b0fb8423SAlexander Graf  * The documentation for this device is noted in the MPC8544 documentation,
16b0fb8423SAlexander Graf  * file name "MPC8544ERM.pdf". You can easily find it on the web.
17b0fb8423SAlexander Graf  *
18b0fb8423SAlexander Graf  */
19b0fb8423SAlexander Graf 
200d75590dSPeter Maydell #include "qemu/osdep.h"
210b8fa32fSMarkus Armbruster #include "qemu/module.h"
22b3b5c5d3SCédric Le Goater #include "qemu/log.h"
2354d31236SMarkus Armbruster #include "sysemu/runstate.h"
244771d756SPaolo Bonzini #include "cpu.h"
2583c9f4caSPaolo Bonzini #include "hw/sysbus.h"
26db1015e9SEduardo Habkost #include "qom/object.h"
27b0fb8423SAlexander Graf 
28b0fb8423SAlexander Graf #define MPC8544_GUTS_MMIO_SIZE        0x1000
29b0fb8423SAlexander Graf #define MPC8544_GUTS_RSTCR_RESET      0x02
30b0fb8423SAlexander Graf 
31b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORPLLSR    0x00
32b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORBMSR     0x04
33b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORIMPSCR   0x08
34b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR    0x0C
35b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDBGMSR   0x10
36b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR2   0x14
37b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPPORCR     0x20
38b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPIOCR      0x30
39b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPOUTDR     0x40
40b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPINDR      0x50
41b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PMUXCR      0x60
42b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DEVDISR     0x70
43b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_POWMGTCSR   0x80
44b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_MCPSUMR     0x90
45b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTRSCR     0x94
46b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PVR         0xA0
47b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SVR         0xA4
48b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTCR       0xB0
49b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_IOVSELSR    0xC0
50b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCSR      0xB20
51b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCDR      0xB24
52b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCLKDR    0xB28
53b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_CLKOCR      0xE00
54b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS1CR1    0xF04
55b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR1    0xF10
56b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR3    0xF18
57b0fb8423SAlexander Graf 
5843f691e9SAndreas Färber #define TYPE_MPC8544_GUTS "mpc8544-guts"
598063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(GutsState, MPC8544_GUTS)
6043f691e9SAndreas Färber 
61b0fb8423SAlexander Graf struct GutsState {
6243f691e9SAndreas Färber     /*< private >*/
6343f691e9SAndreas Färber     SysBusDevice parent_obj;
6443f691e9SAndreas Färber     /*< public >*/
6543f691e9SAndreas Färber 
661c7af35fSAvi Kivity     MemoryRegion iomem;
67b0fb8423SAlexander Graf };
68b0fb8423SAlexander Graf 
69b0fb8423SAlexander Graf 
70a8170e5eSAvi Kivity static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
711c7af35fSAvi Kivity                                   unsigned size)
72b0fb8423SAlexander Graf {
73b0fb8423SAlexander Graf     uint32_t value = 0;
74*794511bcSPhilippe Mathieu-Daudé     CPUPPCState *env = cpu_env(current_cpu);
75b0fb8423SAlexander Graf 
76b0fb8423SAlexander Graf     addr &= MPC8544_GUTS_MMIO_SIZE - 1;
77b0fb8423SAlexander Graf     switch (addr) {
78b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_PVR:
79b0fb8423SAlexander Graf         value = env->spr[SPR_PVR];
80b0fb8423SAlexander Graf         break;
81b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_SVR:
82b0fb8423SAlexander Graf         value = env->spr[SPR_E500_SVR];
83b0fb8423SAlexander Graf         break;
84b0fb8423SAlexander Graf     default:
85b3b5c5d3SCédric Le Goater         qemu_log_mask(LOG_GUEST_ERROR,
86b3b5c5d3SCédric Le Goater                       "%s: Unknown register 0x%" HWADDR_PRIx "\n",
87b3b5c5d3SCédric Le Goater                       __func__, addr);
88b0fb8423SAlexander Graf         break;
89b0fb8423SAlexander Graf     }
90b0fb8423SAlexander Graf 
91b0fb8423SAlexander Graf     return value;
92b0fb8423SAlexander Graf }
93b0fb8423SAlexander Graf 
94a8170e5eSAvi Kivity static void mpc8544_guts_write(void *opaque, hwaddr addr,
951c7af35fSAvi Kivity                                uint64_t value, unsigned size)
96b0fb8423SAlexander Graf {
97b0fb8423SAlexander Graf     addr &= MPC8544_GUTS_MMIO_SIZE - 1;
98b0fb8423SAlexander Graf 
99b0fb8423SAlexander Graf     switch (addr) {
100b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_RSTCR:
101b0fb8423SAlexander Graf         if (value & MPC8544_GUTS_RSTCR_RESET) {
102cf83f140SEric Blake             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
103b0fb8423SAlexander Graf         }
104b0fb8423SAlexander Graf         break;
105b0fb8423SAlexander Graf     default:
106b3b5c5d3SCédric Le Goater         qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown register 0x%" HWADDR_PRIx
107b3b5c5d3SCédric Le Goater                        " = 0x%" PRIx64 "\n", __func__, addr, value);
108b0fb8423SAlexander Graf         break;
109b0fb8423SAlexander Graf     }
110b0fb8423SAlexander Graf }
111b0fb8423SAlexander Graf 
1121c7af35fSAvi Kivity static const MemoryRegionOps mpc8544_guts_ops = {
1131c7af35fSAvi Kivity     .read = mpc8544_guts_read,
1141c7af35fSAvi Kivity     .write = mpc8544_guts_write,
1151c7af35fSAvi Kivity     .endianness = DEVICE_BIG_ENDIAN,
1161c7af35fSAvi Kivity     .valid = {
1171c7af35fSAvi Kivity         .min_access_size = 4,
1181c7af35fSAvi Kivity         .max_access_size = 4,
1191c7af35fSAvi Kivity     },
120b0fb8423SAlexander Graf };
121b0fb8423SAlexander Graf 
1227587ea5bSAndreas Färber static void mpc8544_guts_initfn(Object *obj)
123b0fb8423SAlexander Graf {
1247587ea5bSAndreas Färber     SysBusDevice *d = SYS_BUS_DEVICE(obj);
1257587ea5bSAndreas Färber     GutsState *s = MPC8544_GUTS(obj);
126b0fb8423SAlexander Graf 
12740c5dce9SPaolo Bonzini     memory_region_init_io(&s->iomem, OBJECT(s), &mpc8544_guts_ops, s,
1281f1a83f4SAndreas Färber                           "mpc8544.guts", MPC8544_GUTS_MMIO_SIZE);
1297587ea5bSAndreas Färber     sysbus_init_mmio(d, &s->iomem);
130999e12bbSAnthony Liguori }
131999e12bbSAnthony Liguori 
1328c43a6f0SAndreas Färber static const TypeInfo mpc8544_guts_info = {
13343f691e9SAndreas Färber     .name          = TYPE_MPC8544_GUTS,
13439bffca2SAnthony Liguori     .parent        = TYPE_SYS_BUS_DEVICE,
13539bffca2SAnthony Liguori     .instance_size = sizeof(GutsState),
1367587ea5bSAndreas Färber     .instance_init = mpc8544_guts_initfn,
137b0fb8423SAlexander Graf };
138b0fb8423SAlexander Graf 
13983f7d43aSAndreas Färber static void mpc8544_guts_register_types(void)
140b0fb8423SAlexander Graf {
14139bffca2SAnthony Liguori     type_register_static(&mpc8544_guts_info);
142b0fb8423SAlexander Graf }
14383f7d43aSAndreas Färber 
14483f7d43aSAndreas Färber type_init(mpc8544_guts_register_types)
145